133 lines
4.1 KiB
C
133 lines
4.1 KiB
C
#include "hdl_clk.h"
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/********************************************************************************************************
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* @鍑芥暟鍚? hdl_xtal_init
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* @鎻忚堪 澶栭儴鏅舵尟鍒濆鍖?
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* @鍙傛暟 鏃?
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* @杩斿洖鍊? 鏃?
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* @娉ㄦ剰 鏃?
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********************************************************************************************************/
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#if USING_XTAL
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static void hdl_xtal_init(void)
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{
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stc_clock_xtal_init_t stcXtalInit;
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/* XTAL 寮曡剼閰嶇疆 */
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GPIO_AnalogCmd(GPIO_PORT_H, GPIO_PIN_00 | GPIO_PIN_01, ENABLE);
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(void)CLK_XtalStructInit(&stcXtalInit);
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/* 閰嶇疆XTAL鍜屽惎鐢╔TAL */
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stcXtalInit.u8State = CLK_XTAL_ON;
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stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
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stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
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stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
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(void)CLK_XtalInit(&stcXtalInit);
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}
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#endif
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/********************************************************************************************************
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* @鍑芥暟鍚? hdl_pll_init
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* @鎻忚堪 閿佺浉鐜€嶉鍒濆鍖?
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* @鍙傛暟 鏃?
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* @杩斿洖鍊? 鏃?
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* @娉ㄦ剰 鏃?
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********************************************************************************************************/
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static void hdl_pll_init(void)
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{
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stc_clock_pll_init_t stcMPLLInit;
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(void)CLK_PLLStructInit(&stcMPLLInit);
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/* MPLL 閰嶇疆 */
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/* 16MHz/M*N = 16/2*50/2 = 200MHz */
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stcMPLLInit.PLLCFGR = 0UL;
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stcMPLLInit.PLLCFGR_f.PLLM = (2UL - 1UL);
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stcMPLLInit.PLLCFGR_f.PLLN = (50UL - 1UL);
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stcMPLLInit.PLLCFGR_f.PLLP = (2UL - 1UL);
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stcMPLLInit.PLLCFGR_f.PLLQ = (2UL - 1UL);
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stcMPLLInit.PLLCFGR_f.PLLR = (2UL - 1UL);
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stcMPLLInit.u8PLLState = CLK_PLL_ON;
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stcMPLLInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_HRC; /* HRC = 16MHz */
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(void)CLK_PLLInit(&stcMPLLInit);
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}
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/********************************************************************************************************
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* @鍑芥暟鍚? hdl_clk_init
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* @鎻忚堪 鏃堕挓鍒濆鍖?
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* @鍙傛暟 鏃?
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* @杩斿洖鍊? 鏃?
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* @娉ㄦ剰 鏃?
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********************************************************************************************************/
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void hdl_clk_init(void)
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{
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/* 瑙ｉ櫎鍐欎繚鎶?*/
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LL_PERIPH_WE(LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_GPIO | LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM);
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/* 璁剧疆鏃堕挓鍒嗛 */
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CLK_SetClockDiv(CLK_BUS_CLK_ALL, (CLK_HCLK_DIV1 | CLK_EXCLK_DIV2 | CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | \
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CLK_PCLK2_DIV4 | CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2));
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/* SRAM鍒濆鍖栧寘鎷/鍐欑瓑寰呭懆鏈熻缃?*/
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SRAM_SetWaitCycle(SRAM_SRAM_ALL, SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1);
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SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0);
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/* 闂瓨璇诲彇绛夊緟鍛ㄦ湡璁剧疆 */
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EFM_SetWaitCycle(EFM_WAIT_CYCLE5);
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/* XTAL 鍒濆鍖?*/
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// hdl_xtal_init();
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/* XTAL32 鍒濆鍖?*/
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/* MPLL 鍒濆鍖?*/
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hdl_pll_init();
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/* enable LRC */
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/* enable HRC */
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/* 3 cycles for 126MHz ~ 200MHz */
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GPIO_SetReadWaitCycle(GPIO_RD_WAIT3);
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/* 鍒囨崲椹卞姩鑳藉姏 */
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PWC_HighSpeedToHighPerformance();
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EFM_DataCacheResetCmd(ENABLE);
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EFM_DataCacheResetCmd(DISABLE);
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/* Enable cache */
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EFM_CacheCmd(ENABLE);
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/* 浣胯兘鍐欎繚鎶?*/
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LL_PERIPH_WP(LL_PERIPH_EFM | LL_PERIPH_GPIO | LL_PERIPH_SRAM);
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/* 璁剧疆绯荤粺鏃堕挓婧?*/
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CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
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/* 浣胯兘systick */
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(void)SysTick_Init(1000U);
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}
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void hdl_delay_us(uint16_t us)
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{
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for(int i=0;i<us;i++)
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{
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for(int j=0;j<35;j++)
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{
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__NOP();
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}
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}
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}
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void hdl_delay_ms(uint16_t ms)
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{
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for(int i=0;i<ms;i++)
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{
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for(int j=0;j<13000;j++)
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{
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__NOP();
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}
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}
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}
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