294 lines
8.4 KiB
C
294 lines
8.4 KiB
C
/**
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*******************************************************************************
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* @file hc32_ll_fcm.h
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* @brief This file contains all the functions prototypes of the FCM driver
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* library.
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@verbatim
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Change Logs:
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Date Author Notes
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2022-03-31 CDT First version
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2023-06-30 CDT Modify API FCM_DeInit()
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@endverbatim
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*******************************************************************************
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* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by XHSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#ifndef __HC32_LL_FCM_H__
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#define __HC32_LL_FCM_H__
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_ll_def.h"
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#include "hc32f4xx.h"
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#include "hc32f4xx_conf.h"
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/**
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* @addtogroup LL_Driver
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* @{
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*/
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/**
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* @addtogroup LL_FCM
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* @{
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*/
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#if (LL_FCM_ENABLE == DDL_ON)
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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* @defgroup FCM_Global_Types FCM Global Types
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* @{
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*/
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/**
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* @brief FCM Init structure definition
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*/
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typedef struct {
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uint16_t u16LowerLimit; /*!< FCM lower limit value */
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uint16_t u16UpperLimit; /*!< FCM upper limit value */
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uint32_t u32TargetClock; /*!< FCM target clock source selection, @ref FCM_Target_Clock_Src */
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uint32_t u32TargetClockDiv; /*!< FCM target clock source division selection, @ref FCM_Target_Clock_Div */
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uint32_t u32ExtRefClockEnable; /*!< FCM external reference clock function config, @ref FCM_Ext_Ref_Clock_Config */
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uint32_t u32RefClockEdge; /*!< FCM reference clock trigger edge selection, @ref FCM_Ref_Clock_Edge */
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uint32_t u32DigitalFilter; /*!< FCM digital filter function config, @ref FCM_Digital_Filter_Config */
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uint32_t u32RefClock; /*!< FCM reference clock source selection, @ref FCM_Ref_Clock_Src */
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uint32_t u32RefClockDiv; /*!< FCM reference clock source division selection, @ref FCM_Ref_Clock_Div */
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uint32_t u32ExceptionType; /*!< FCM exception type select, @ref FCM_Exception_Type */
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} stc_fcm_init_t;
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/**
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* @}
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*/
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/**
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* @defgroup FCM_Global_Macros FCM Global Macros
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* @{
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*/
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/**
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* @defgroup FCM_Target_Clock_Src FCM Target Clock Source
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* @{
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*/
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#define FCM_TARGET_CLK_XTAL (0x00UL << FCM_MCCR_MCKS_POS)
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#define FCM_TARGET_CLK_XTAL32 (0x01UL << FCM_MCCR_MCKS_POS)
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#define FCM_TARGET_CLK_HRC (0x02UL << FCM_MCCR_MCKS_POS)
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#define FCM_TARGET_CLK_LRC (0x03UL << FCM_MCCR_MCKS_POS)
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#define FCM_TARGET_CLK_SWDTLRC (0x04UL << FCM_MCCR_MCKS_POS)
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#define FCM_TARGET_CLK_PCLK1 (0x05UL << FCM_MCCR_MCKS_POS)
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#define FCM_TARGET_CLK_UPLLP (0x06UL << FCM_MCCR_MCKS_POS)
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#define FCM_TARGET_CLK_MRC (0x07UL << FCM_MCCR_MCKS_POS)
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#define FCM_TARGET_CLK_MPLLP (0x08UL << FCM_MCCR_MCKS_POS)
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/**
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* @}
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*/
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/**
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* @defgroup FCM_Target_Clock_Div FCM Target Clock Division
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* @{
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*/
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#define FCM_TARGET_CLK_DIV1 (0x00UL << FCM_MCCR_MDIVS_POS)
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#define FCM_TARGET_CLK_DIV4 (0x01UL << FCM_MCCR_MDIVS_POS)
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#define FCM_TARGET_CLK_DIV8 (0x02UL << FCM_MCCR_MDIVS_POS)
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#define FCM_TARGET_CLK_DIV32 (0x03UL << FCM_MCCR_MDIVS_POS)
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/**
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* @}
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*/
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/**
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* @defgroup FCM_Ext_Ref_Clock_Config FCM External Reference Clock Config
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* @{
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*/
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#define FCM_EXT_REF_OFF (0x00UL)
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#define FCM_EXT_REF_ON (FCM_RCCR_EXREFE)
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/**
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* @}
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*/
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/**
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* @defgroup FCM_Ref_Clock_Edge FCM Reference Clock Edge
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* @{
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*/
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#define FCM_REF_CLK_RISING (0x00UL)
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#define FCM_REF_CLK_FALLING (FCM_RCCR_EDGES_0)
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#define FCM_REF_CLK_BOTH (FCM_RCCR_EDGES_1)
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/**
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* @}
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*/
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/**
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* @defgroup FCM_Digital_Filter_Config FCM Digital Filter Config
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* @{
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*/
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#define FCM_DIG_FILTER_OFF (0x00UL)
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#define FCM_DIG_FILTER_DIV1 (FCM_RCCR_DNFS_0)
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#define FCM_DIG_FILTER_DIV4 (FCM_RCCR_DNFS_1)
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#define FCM_DIG_FILTER_DIV16 (FCM_RCCR_DNFS)
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/**
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* @}
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*/
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/**
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* @defgroup FCM_Ref_Clock_Src FCM Reference Clock Source
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* @{
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*/
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#define FCM_REF_CLK_EXTCLK (0x00UL << FCM_RCCR_RCKS_POS)
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#define FCM_REF_CLK_XTAL (0x10UL << FCM_RCCR_RCKS_POS)
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#define FCM_REF_CLK_XTAL32 (0x11UL << FCM_RCCR_RCKS_POS)
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#define FCM_REF_CLK_HRC (0x12UL << FCM_RCCR_RCKS_POS)
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#define FCM_REF_CLK_LRC (0x13UL << FCM_RCCR_RCKS_POS)
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#define FCM_REF_CLK_SWDTLRC (0x14UL << FCM_RCCR_RCKS_POS)
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#define FCM_REF_CLK_PCLK1 (0x15UL << FCM_RCCR_RCKS_POS)
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#define FCM_REF_CLK_UPLLP (0x16UL << FCM_RCCR_RCKS_POS)
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#define FCM_REF_CLK_MRC (0x17UL << FCM_RCCR_RCKS_POS)
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#define FCM_REF_CLK_MPLLP (0x18UL << FCM_RCCR_RCKS_POS)
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/**
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* @}
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*/
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/**
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* @defgroup FCM_Ref_Clock_Div FCM Reference Clock Division
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* @{
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*/
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#define FCM_REF_CLK_DIV32 (0x00UL << FCM_RCCR_RDIVS_POS)
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#define FCM_REF_CLK_DIV128 (0x01UL << FCM_RCCR_RDIVS_POS)
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#define FCM_REF_CLK_DIV1024 (0x02UL << FCM_RCCR_RDIVS_POS)
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#define FCM_REF_CLK_DIV8192 (0x03UL << FCM_RCCR_RDIVS_POS)
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/**
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* @}
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*/
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/**
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* @defgroup FCM_Abnormal_Reset_Func FCM Abnormal Reset Function Config
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* @{
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*/
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#define FCM_ERR_RST_OFF (0x00UL)
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#define FCM_ERR_RST_ON (FCM_RIER_ERRE)
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/**
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* @}
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*/
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/**
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* @defgroup FCM_Exception_Type FCM Exception Type
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* @{
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*/
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#define FCM_EXP_TYPE_INT (0x00UL)
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#define FCM_EXP_TYPE_RST (FCM_RIER_ERRINTRS)
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/**
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* @}
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*/
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/**
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* @defgroup FCM_Int_Type FCM Interrupt Type
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* @{
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*/
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#define FCM_INT_OVF (FCM_RIER_OVFIE)
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#define FCM_INT_END (FCM_RIER_MENDIE)
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#define FCM_INT_ERR (FCM_RIER_ERRIE)
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/**
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* @}
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*/
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/**
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* @defgroup FCM_Flag_Sel FCM Status Flag Selection
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* @{
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*/
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#define FCM_FLAG_ERR (FCM_SR_ERRF)
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#define FCM_FLAG_END (FCM_SR_MENDF)
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#define FCM_FLAG_OVF (FCM_SR_OVF)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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Global function prototypes (definition in C source)
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******************************************************************************/
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/**
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* @addtogroup FCM_Global_Functions
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* @{
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*/
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/**
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* @brief Set FCM upper limit value.
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* @param u16Limit
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* @retval None.
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*/
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__STATIC_INLINE void FCM_SetUpperLimit(uint16_t u16Limit)
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{
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WRITE_REG32(CM_FCM->UVR, u16Limit);
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}
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/**
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* @brief Set FCM lower limit value.
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* @param u16Limit
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* @retval None
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*/
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__STATIC_INLINE void FCM_SetLowerLimit(uint16_t u16Limit)
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{
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WRITE_REG32(CM_FCM->LVR, u16Limit);
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}
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int32_t FCM_Init(const stc_fcm_init_t *pstcFcmInit);
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int32_t FCM_StructInit(stc_fcm_init_t *pstcFcmInit);
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int32_t FCM_DeInit(void);
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uint16_t FCM_GetCountValue(void);
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void FCM_SetUpperLimit(uint16_t u16Limit);
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void FCM_SetLowerLimit(uint16_t u16Limit);
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void FCM_SetTargetClock(uint32_t u32ClockSrc, uint32_t u32Div);
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void FCM_SetRefClock(uint32_t u32ClockSrc, uint32_t u32Div);
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en_flag_status_t FCM_GetStatus(uint32_t u32Flag);
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void FCM_ClearStatus(uint32_t u32Flag);
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void FCM_ResetCmd(en_functional_state_t enNewState);
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void FCM_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState);
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void FCM_Cmd(en_functional_state_t enNewState);
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/**
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* @}
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*/
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#endif /* LL_FCM_ENABLE */
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HC32_LL_FCM_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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