1251 lines
40 KiB
C
1251 lines
40 KiB
C
/**
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*******************************************************************************
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* @file hc32_ll_efm.c
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* @brief This file provides firmware functions to manage the Embedded Flash
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* Memory unit (EFM).
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@verbatim
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Change Logs:
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Date Author Notes
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2022-03-31 CDT First version
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2022-10-31 CDT Add API EFM_Protect_Enable & EFM_WriteSecurityCode
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Modify API EFM_Read & EFM_Program
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2023-01-15 CDT Code refine
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2023-06-30 CDT Modify API EFM_Program()
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Modify assert IS_EFM_ADDR() range
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Modify API EFM_Protect_Enable()
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Modify typo
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Modify API EFM_WriteSecurityCode(), switch to read_only mode before exit
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2023-09-30 CDT Remove address assert from EFM_ReadByte()
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Refine EFM_SequenceProgram() & EFM_ChipErase(), and put them in RAM
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Fix bug of EFM_GetSwapStatus()
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@endverbatim
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*******************************************************************************
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* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by XHSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_ll_efm.h"
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#include "hc32_ll_utility.h"
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/**
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* @addtogroup LL_Driver
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* @{
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*/
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/**
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* @defgroup LL_EFM EFM
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* @brief Embedded Flash Management Driver Library
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* @{
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*/
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#if (LL_EFM_ENABLE == DDL_ON)
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/*******************************************************************************
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* Local type definitions ('typedef')
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******************************************************************************/
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/*******************************************************************************
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* Local pre-processor symbols/macros ('#define')
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******************************************************************************/
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/**
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* @defgroup EFM_Local_Macros EFM Local Macros
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* @{
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*/
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#ifndef __EFM_FUNC
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#define __EFM_FUNC __RAM_FUNC
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#endif
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#define REG_LEN (32U)
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#define EFM_TIMEOUT (HCLK_VALUE / 20000UL) /* EFM wait read timeout */
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#define EFM_PGM_TIMEOUT (HCLK_VALUE / 20000UL) /* EFM Program timeout max 53us */
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#define EFM_ERASE_TIMEOUT (HCLK_VALUE / 50UL) /* EFM Erase timeout max 20ms */
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#define EFM_SEQ_PGM_TIMEOUT (HCLK_VALUE / 62500UL) /* EFM Sequence Program timeout max 16us */
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#define REMCR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_EFM->MMF_REMCR0) + (4UL * (x))))
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/**
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* @defgroup EFM_Configuration_Bit_Mask EFM Configuration Bit Mask
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* @{
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*/
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#define EFM_CACHE_ALL (EFM_FRMC_CRST | EFM_FRMC_CACHE)
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/**
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* @}
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*/
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/**
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* @defgroup EFM_protect EFM protect define
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* @{
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*/
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#define EFM_SECURITY_LEN (12UL)
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#define EFM_PROTECT1_KEY (0xAF180402UL)
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#define EFM_PROTECT2_KEY (0xA85173AEUL)
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#define EFM_PROTECT1_ADDR (0x00000410UL)
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#define EFM_PROTECT2_ADDR (0x00000414UL)
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#define EFM_SECURITY_ADDR (0x0317FFECUL)
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#define EFM_SECURITY_ADDR1 (0x0317FFE0UL)
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/**
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* @}
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*/
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/**
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* @defgroup EFM_Check_Parameters_Validity EFM Check Parameters Validity
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* @{
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*/
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/* Parameter validity check for efm chip . */
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#define IS_EFM_CHIP(x) ((x) == EFM_CHIP_ALL)
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/* Parameter validity check for flash latency. */
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#define IS_EFM_WAIT_CYCLE(x) ((x) <= EFM_WAIT_CYCLE15)
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/* Parameter validity check for operate mode. */
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#define IS_EFM_OPERATE_MD(x) \
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( ((x) == EFM_MD_PGM_SINGLE) || \
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((x) == EFM_MD_PGM_READBACK) || \
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((x) == EFM_MD_PGM_SEQ) || \
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((x) == EFM_MD_ERASE_SECTOR) || \
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((x) == EFM_MD_ERASE_ALL_CHIP) || \
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((x) == EFM_MD_READONLY))
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/* Parameter validity check for flash interrupt select. */
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#define IS_EFM_INT_SEL(x) (((x) | EFM_INT_ALL) == EFM_INT_ALL)
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/* Parameter validity check for flash flag. */
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#define IS_EFM_FLAG(x) (((x) | EFM_FLAG_ALL) == EFM_FLAG_ALL)
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/* Parameter validity check for flash clear flag. */
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#define IS_EFM_CLRFLAG(x) (((x) | EFM_FLAG_ALL) == EFM_FLAG_ALL)
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/* Parameter validity check for bus status while flash program or erase. */
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#define IS_EFM_BUS_STATUS(x) \
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( ((x) == EFM_BUS_HOLD) || \
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((x) == EFM_BUS_RELEASE))
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/* Parameter validity check for efm address. */
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#define IS_EFM_ADDR(x) \
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( ((x) <= EFM_END_ADDR) || \
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(((x) >= EFM_OTP_START_ADDR) && ((x) <= EFM_OTP_END_ADDR)) || \
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(((x) >= EFM_SECURITY_START_ADDR) && ((x) <= EFM_SECURITY_END_ADDR)))
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/* Parameter validity check for efm erase address. */
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#define IS_EFM_ERASE_ADDR(x) ((x) <= EFM_END_ADDR)
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/* Parameter validity check for efm erase mode . */
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#define IS_EFM_ERASE_MD(x) \
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( ((x) == EFM_MD_ERASE_ONE_CHIP) || \
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((x) == EFM_MD_ERASE_FULL))
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/* Parameter validity check for EFM lock status. */
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#define IS_EFM_REG_UNLOCK() (CM_EFM->FAPRT == 0x00000001UL)
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/* Parameter validity check for EFM_FWMC register lock status. */
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#define IS_EFM_FWMC_UNLOCK() (bCM_EFM->FWMC_b.PEMODE == 1U)
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/* Parameter validity check for EFM remap lock status. */
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#define IS_EFM_REMAP_UNLOCK() (CM_EFM->MMF_REMPRT == 0x00000001UL)
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/* Parameter validity check for EFM remap index */
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#define IS_EFM_REMAP_IDX(x) \
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( ((x) == EFM_REMAP_IDX0) || \
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((x) == EFM_REMAP_IDX1))
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/* Parameter validity check for EFM remap size */
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#define IS_EFM_REMAP_SIZE(x) \
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( ((x) >= EFM_REMAP_4K) && \
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((x) <= EFM_REMAP_512K))
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/* Parameter validity check for EFM remap address */
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#define IS_EFM_REMAP_ADDR(x) \
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( ((x) <= EFM_REMAP_ROM_END_ADDR) || \
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(((x) >= EFM_REMAP_RAM_START_ADDR) && \
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((x) <= EFM_REMAP_RAM_END_ADDR)))
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/* Parameter validity check for EFM remap state */
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#define IS_EFM_REMAP_STATE(x) \
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( ((x) == EFM_REMAP_OFF) || \
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((x) == EFM_REMAP_ON))
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/* Parameter validity check for EFM security code length */
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#define IS_EFM_SECURITY_CODE_LEN(x) ((x) <= EFM_SECURITY_LEN)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/*******************************************************************************
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* Global variable definitions (declared in header file with 'extern')
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******************************************************************************/
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/*******************************************************************************
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* Local function prototypes ('static')
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******************************************************************************/
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/*******************************************************************************
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* Local variable definitions ('static')
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******************************************************************************/
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/*******************************************************************************
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* Function implementation - global ('extern') and local ('static')
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******************************************************************************/
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/**
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* @defgroup EFM_Local_Functions EFM Local Functions
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* @{
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*/
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/**
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* @brief Wait EFM flag.
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* @param [in] u32Flag Specifies the flag to be wait. @ref EFM_Flag_Sel
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* @param [in] u32Time Specifies the time to wait while the flag not be set.
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* @retval int32_t:
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* - LL_OK: Flag was set.
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* - LL_ERR_TIMEOUT: Flag was not set.
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*/
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static int32_t EFM_WaitFlag(uint32_t u32Flag, uint32_t u32Time)
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{
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__IO uint32_t u32Timeout = 0UL;
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int32_t i32Ret = LL_OK;
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while (SET != EFM_GetStatus(u32Flag)) {
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u32Timeout++;
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if (u32Timeout > u32Time) {
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i32Ret = LL_ERR_TIMEOUT;
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break;
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}
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}
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return i32Ret;
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}
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/**
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* @}
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*/
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/**
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* @defgroup EFM_Global_Functions EFM Global Functions
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* @{
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*/
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/**
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* @brief Enable or disable EFM.
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* @param [in] u32Flash Specifies the FLASH. @ref EFM_Chip_Sel
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* @param [in] enNewState An @ref en_functional_state_t enumeration value.
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* @retval None
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*/
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void EFM_Cmd(uint32_t u32Flash, en_functional_state_t enNewState)
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{
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DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
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DDL_ASSERT(IS_EFM_REG_UNLOCK());
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DDL_ASSERT(IS_EFM_CHIP(u32Flash));
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if (ENABLE == enNewState) {
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CLR_REG32_BIT(CM_EFM->FSTP, u32Flash);
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} else {
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SET_REG32_BIT(CM_EFM->FSTP, u32Flash);
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}
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}
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/**
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* @brief Set the efm read wait cycles.
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* @param [in] u32WaitCycle Specifies the efm read wait cycles.
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* @arg This parameter can be of a value of @ref EFM_Wait_Cycle
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* @retval int32_t:
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* - LL_OK: Program successfully.
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* - LL_ERR_TIMEOUT: EFM is not ready.
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* @note Call EFM_REG_Unlock() unlock EFM register first.
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*/
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int32_t EFM_SetWaitCycle(uint32_t u32WaitCycle)
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{
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uint32_t u32Timeout = 0UL;
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/* Param valid check */
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DDL_ASSERT(IS_EFM_REG_UNLOCK());
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DDL_ASSERT(IS_EFM_WAIT_CYCLE(u32WaitCycle));
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MODIFY_REG32(CM_EFM->FRMC, EFM_FRMC_FLWT, u32WaitCycle);
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while (u32WaitCycle != READ_REG32_BIT(CM_EFM->FRMC, EFM_FRMC_FLWT)) {
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u32Timeout++;
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if (u32Timeout > EFM_TIMEOUT) {
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return LL_ERR_TIMEOUT;
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}
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}
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return LL_OK;
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}
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/**
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* @brief Enable or disable the flash data cache reset.
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* @param [in] enNewState An @ref en_functional_state_t enumeration value.
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* @retval None
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*/
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void EFM_DataCacheResetCmd(en_functional_state_t enNewState)
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{
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DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
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DDL_ASSERT(IS_EFM_REG_UNLOCK());
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WRITE_REG32(bCM_EFM->FRMC_b.CRST, enNewState);
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}
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/**
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* @brief Enable or disable the flash data cache and instruction cache.
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* @param [in] enNewState An @ref en_functional_state_t enumeration value.
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* @retval None
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* @note Call EFM_REG_Unlock() unlock EFM register first.
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*/
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void EFM_CacheCmd(en_functional_state_t enNewState)
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{
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DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
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DDL_ASSERT(IS_EFM_REG_UNLOCK());
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WRITE_REG32(bCM_EFM->FRMC_b.CACHE, enNewState);
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}
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/**
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* @brief Enable or disable the Read of low-voltage mode.
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* @param [in] enNewState An @ref en_functional_state_t enumeration value.
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* @retval None
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* @note Call EFM_REG_Unlock() unlock EFM register first.
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*/
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void EFM_LowVoltageReadCmd(en_functional_state_t enNewState)
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{
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DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
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DDL_ASSERT(IS_EFM_REG_UNLOCK());
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WRITE_REG32(bCM_EFM->FRMC_b.SLPMD, enNewState);
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}
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/**
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* @brief Enable or disable the EFM swap function.
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* @param [in] enNewState An @ref en_functional_state_t enumeration value.
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* @retval int32_t:
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* - LL_OK: Program successfully.
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* - LL_ERR_NOT_RDY: EFM is not ready.
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* @note Call EFM_REG_Unlock() unlock EFM register first.
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*/
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int32_t EFM_SwapCmd(en_functional_state_t enNewState)
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{
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int32_t i32Ret = LL_OK;
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uint32_t u32Tmp;
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DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
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DDL_ASSERT(IS_EFM_REG_UNLOCK());
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DDL_ASSERT(IS_EFM_FWMC_UNLOCK());
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/* Get CACHE status */
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u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
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/* Disable CACHE */
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CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
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if (enNewState == ENABLE) {
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/* Set Program single mode. */
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MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE);
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/* Enable flash swap function */
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RW_MEM32(EFM_SWAP_ADDR) = EFM_SWAP_DATA;
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/* Wait for ready flag. */
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if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_PGM_TIMEOUT)) {
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i32Ret = LL_ERR_NOT_RDY;
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}
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/* CLear the operation end flag. */
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EFM_ClearStatus(EFM_FLAG_OPTEND);
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} else {
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/* Set Sector erase mode. */
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MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR);
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/* Disable flash switch function */
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RW_MEM32(EFM_SWAP_ADDR) = 0x0UL;
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/* Wait for ready flag. */
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if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_ERASE_TIMEOUT)) {
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i32Ret = LL_ERR_NOT_RDY;
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}
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/* CLear the operation end flag. */
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EFM_ClearStatus(EFM_FLAG_OPTEND);
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}
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/* Set read only mode. */
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MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY);
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/* recover CACHE */
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MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp);
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return i32Ret;
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}
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/**
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* @brief Checks whether the swap function enable or disable.
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* @param None
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* @retval An @ref en_flag_status_t enumeration type value.
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*/
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en_flag_status_t EFM_GetSwapStatus(void)
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{
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return ((0UL == READ_REG32(bCM_EFM->FSWP_b.FSWP)) ? SET : RESET);
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}
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/**
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* @brief Enable or disable the EFM low-voltage mode.
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* @param [in] enNewState An @ref en_functional_state_t enumeration value.
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* @retval None
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* @note Call EFM_REG_Unlock() unlock EFM register first.
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*/
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void EFM_LowVoltageCmd(en_functional_state_t enNewState)
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{
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DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
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WRITE_REG32(bCM_EFM->FRMC_b.LVM, enNewState);
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}
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/**
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* @brief Set the FLASH erase program mode .
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* @param [in] u32Mode Specifies the FLASH erase program mode.
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* @arg This parameter can be of a value of @ref EFM_OperateMode_Sel
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* @retval int32_t:
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* - LL_OK: Set mode successfully.
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* - LL_ERR_NOT_RDY: EFM is not ready.
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*/
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int32_t EFM_SetOperateMode(uint32_t u32Mode)
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{
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int32_t i32Ret = LL_OK;
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DDL_ASSERT(IS_EFM_OPERATE_MD(u32Mode));
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DDL_ASSERT(IS_EFM_REG_UNLOCK());
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DDL_ASSERT(IS_EFM_FWMC_UNLOCK());
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if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_SEQ_PGM_TIMEOUT)) {
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i32Ret = LL_ERR_NOT_RDY;
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}
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if (i32Ret == LL_OK) {
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/* Set the program or erase mode. */
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MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, u32Mode);
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}
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return i32Ret;
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}
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/**
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* @brief Enable or Disable EFM interrupt.
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* @param [in] u32EfmInt Specifies the FLASH interrupt source and status. @ref EFM_Interrupt_Sel
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* @arg EFM_INT_OPTEND: End of EFM Operation Interrupt source
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* @arg EFM_INT_PEERR: Program/erase error Interrupt source
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* @arg EFM_INT_COLERR: Read collide error Interrupt source
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* @param [in] enNewState An @ref en_functional_state_t enumeration value.
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* @retval None
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* @note Call EFM_REG_Unlock() unlock EFM register first.
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*/
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void EFM_IntCmd(uint32_t u32EfmInt, en_functional_state_t enNewState)
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{
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DDL_ASSERT(IS_EFM_REG_UNLOCK());
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DDL_ASSERT(IS_EFM_INT_SEL(u32EfmInt));
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DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
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if (ENABLE == enNewState) {
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SET_REG32_BIT(CM_EFM->FITE, u32EfmInt);
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} else {
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CLR_REG32_BIT(CM_EFM->FITE, u32EfmInt);
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}
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}
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/**
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* @brief Check any of the specified flag is set or not.
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* @param [in] u32Flag Specifies the FLASH flag to check.
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* @arg This parameter can be of a value of @ref EFM_Flag_Sel
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* @retval An @ref en_flag_status_t enumeration type value.
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*/
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en_flag_status_t EFM_GetAnyStatus(uint32_t u32Flag)
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{
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DDL_ASSERT(IS_EFM_FLAG(u32Flag));
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return ((0UL == READ_REG32_BIT(CM_EFM->FSR, u32Flag)) ? RESET : SET);
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}
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/**
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* @brief Check all the specified flag is set or not.
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* @param [in] u32Flag Specifies the FLASH flag to check.
|
|
* @arg This parameter can be of a value of @ref EFM_Flag_Sel
|
|
* @retval An @ref en_flag_status_t enumeration type value.
|
|
*/
|
|
en_flag_status_t EFM_GetStatus(uint32_t u32Flag)
|
|
{
|
|
DDL_ASSERT(IS_EFM_FLAG(u32Flag));
|
|
|
|
return ((u32Flag == READ_REG32_BIT(CM_EFM->FSR, u32Flag)) ? SET : RESET);
|
|
}
|
|
|
|
/**
|
|
* @brief Clear the flash flag.
|
|
* @param [in] u32Flag Specifies the FLASH flag to clear.
|
|
* @arg This parameter can be of a value of @ref EFM_Flag_Sel
|
|
* @retval None
|
|
* @note Call EFM_REG_Unlock() unlock EFM register first.
|
|
*/
|
|
void EFM_ClearStatus(uint32_t u32Flag)
|
|
{
|
|
DDL_ASSERT(IS_EFM_REG_UNLOCK());
|
|
DDL_ASSERT(IS_EFM_CLRFLAG(u32Flag));
|
|
|
|
SET_REG32_BIT(CM_EFM->FSCLR, u32Flag);
|
|
}
|
|
|
|
/**
|
|
* @brief Set bus status while flash program or erase.
|
|
* @param [in] u32Status Specifies the new bus status while flash program or erase.
|
|
* This parameter can be one of the following values:
|
|
* @arg EFM_BUS_HOLD: Bus busy while flash program or erase.
|
|
* @arg EFM_BUS_RELEASE: Bus release while flash program or erase.
|
|
* @retval None
|
|
*/
|
|
void EFM_SetBusStatus(uint32_t u32Status)
|
|
{
|
|
DDL_ASSERT(IS_EFM_REG_UNLOCK());
|
|
DDL_ASSERT(IS_EFM_BUS_STATUS(u32Status));
|
|
DDL_ASSERT(IS_EFM_FWMC_UNLOCK());
|
|
|
|
WRITE_REG32(bCM_EFM->FWMC_b.BUSHLDCTL, u32Status);
|
|
}
|
|
|
|
/**
|
|
* @brief EFM read byte.
|
|
* @param [in] u32Addr The specified address to read.
|
|
* @param [in] pu8ReadBuf The specified read buffer.
|
|
* @param [in] u32ByteLen The specified length to read.
|
|
* @retval int32_t:
|
|
* - LL_OK: Read successfully
|
|
* - LL_ERR_INVD_PARAM: Invalid parameter
|
|
* - LL_ERR_NOT_RDY: EFM is not ready.
|
|
*/
|
|
int32_t EFM_ReadByte(uint32_t u32Addr, uint8_t *pu8ReadBuf, uint32_t u32ByteLen)
|
|
{
|
|
int32_t i32Ret = LL_ERR_INVD_PARAM;
|
|
__IO uint8_t *pu8Buf = (uint8_t *)u32Addr;
|
|
uint32_t u32Len = u32ByteLen;
|
|
uint32_t u32ReadyFlag = EFM_FLAG_RDY;
|
|
|
|
DDL_ASSERT(IS_EFM_ADDR(u32Addr));
|
|
DDL_ASSERT(IS_EFM_ADDR(u32Addr + u32ByteLen - 1UL));
|
|
|
|
if (NULL != pu8ReadBuf) {
|
|
|
|
if (LL_OK == EFM_WaitFlag(u32ReadyFlag, EFM_TIMEOUT)) {
|
|
while (0UL != u32Len) {
|
|
*(pu8ReadBuf++) = *(pu8Buf++);
|
|
u32Len--;
|
|
}
|
|
i32Ret = LL_OK;
|
|
} else {
|
|
i32Ret = LL_ERR_NOT_RDY;
|
|
}
|
|
}
|
|
|
|
return i32Ret;
|
|
}
|
|
|
|
/**
|
|
* @brief EFM program (single program mode).
|
|
* @param [in] u32Addr The specified program address.
|
|
* @param [in] pu8Buf The pointer of specified program data.
|
|
* @param [in] u32Len The length of specified program data.
|
|
* @retval int32_t:
|
|
* - LL_OK: Program successful.
|
|
* - LL_ERR_NOT_RDY: EFM if not ready.
|
|
* @note Call EFM_REG_Unlock() unlock EFM register first.
|
|
*/
|
|
int32_t EFM_Program(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len)
|
|
{
|
|
int32_t i32Ret = LL_OK;
|
|
uint32_t u32Tmp;
|
|
uint8_t u8Shift;
|
|
uint32_t u32LoopWords = u32Len >> 2UL;
|
|
uint32_t u32RemainBytes = u32Len % 4UL;
|
|
uint32_t *u32pSource = (uint32_t *)(uint32_t)pu8Buf;
|
|
uint32_t *u32pDest = (uint32_t *)u32Addr;
|
|
uint32_t u32LastWord;
|
|
|
|
DDL_ASSERT(IS_EFM_REG_UNLOCK());
|
|
DDL_ASSERT(IS_EFM_FWMC_UNLOCK());
|
|
DDL_ASSERT(IS_EFM_ADDR(u32Addr));
|
|
DDL_ASSERT(IS_EFM_ADDR(u32Addr + u32Len - 1UL));
|
|
DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr));
|
|
|
|
u8Shift = 0U;
|
|
|
|
/* CLear the error flag. */
|
|
EFM_ClearStatus(EFM_FLAG_ALL);
|
|
/* Get CACHE status */
|
|
u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
|
|
/* Disable CACHE */
|
|
CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
|
|
|
|
/* Set single program mode. */
|
|
MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE);
|
|
|
|
while (u32LoopWords-- > 0UL) {
|
|
/* program data. */
|
|
*u32pDest++ = *u32pSource++;
|
|
/* Wait for ready flag. */
|
|
if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) {
|
|
i32Ret = LL_ERR_NOT_RDY;
|
|
}
|
|
/* CLear the operation end flag. */
|
|
EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift);
|
|
}
|
|
|
|
if (0U != u32RemainBytes) {
|
|
u32LastWord = *u32pSource;
|
|
u32LastWord |= 0xFFFFFFFFUL << (u32RemainBytes * 8UL);
|
|
*u32pDest++ = u32LastWord;
|
|
/* Wait for ready flag. */
|
|
if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) {
|
|
i32Ret = LL_ERR_NOT_RDY;
|
|
}
|
|
/* CLear the operation end flag. */
|
|
EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift);
|
|
|
|
}
|
|
/* Set read only mode. */
|
|
MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY);
|
|
/* Reset cache data */
|
|
/* Recover CACHE function */
|
|
MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp);
|
|
return i32Ret;
|
|
}
|
|
|
|
/**
|
|
* @brief EFM single program mode(Word).
|
|
* @param [in] u32Addr The specified program address.
|
|
* @param [in] u32Data The specified program data.
|
|
* @retval int32_t:
|
|
* - LL_OK: Program successfully
|
|
* - LL_ERR_NOT_RDY: EFM is not ready.
|
|
* @note Call EFM_REG_Unlock() unlock EFM register first.
|
|
*/
|
|
int32_t EFM_ProgramWord(uint32_t u32Addr, uint32_t u32Data)
|
|
{
|
|
int32_t i32Ret = LL_OK;
|
|
uint32_t u32Tmp;
|
|
uint8_t u8Shift;
|
|
|
|
DDL_ASSERT(IS_EFM_REG_UNLOCK());
|
|
DDL_ASSERT(IS_EFM_FWMC_UNLOCK());
|
|
DDL_ASSERT(IS_EFM_ADDR(u32Addr));
|
|
DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr));
|
|
|
|
/* Clear the error flag. */
|
|
EFM_ClearStatus(EFM_FLAG_ALL);
|
|
/* Get CACHE status */
|
|
u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
|
|
/* Disable CACHE function */
|
|
CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
|
|
u8Shift = 0U;
|
|
/* Set single program mode. */
|
|
MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE);
|
|
/* Program data. */
|
|
RW_MEM32(u32Addr) = u32Data;
|
|
|
|
/* Wait for ready flag. */
|
|
if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) {
|
|
i32Ret = LL_ERR_NOT_RDY;
|
|
}
|
|
/* CLear the operation end flag. */
|
|
EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift);
|
|
|
|
/* Set read only mode. */
|
|
MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY);
|
|
|
|
/* Recover CACHE function */
|
|
MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp);
|
|
|
|
return i32Ret;
|
|
}
|
|
|
|
/**
|
|
* @brief EFM single program with read back(Word).
|
|
* @param [in] u32Addr The specified program address.
|
|
* @param [in] u32Data The specified program data.
|
|
* @retval int32_t:
|
|
* - LL_OK: Program successfully
|
|
* - LL_ERR: program error
|
|
* - LL_ERR_NOT_RDY: EFM is not ready.
|
|
* @note Call EFM_REG_Unlock() unlock EFM register first.
|
|
*/
|
|
int32_t EFM_ProgramWordReadBack(uint32_t u32Addr, uint32_t u32Data)
|
|
{
|
|
int32_t i32Ret = LL_OK;
|
|
uint32_t u32Tmp;
|
|
uint8_t u8Shift;
|
|
|
|
DDL_ASSERT(IS_EFM_REG_UNLOCK());
|
|
DDL_ASSERT(IS_EFM_FWMC_UNLOCK());
|
|
DDL_ASSERT(IS_EFM_ADDR(u32Addr));
|
|
DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr));
|
|
|
|
/* Clear the error flag. */
|
|
EFM_ClearStatus(EFM_FLAG_ALL);
|
|
/* Get CACHE status */
|
|
u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
|
|
/* Disable CACHE */
|
|
CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
|
|
u8Shift = 0U;
|
|
/* Set Program and read back mode. */
|
|
MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_READBACK);
|
|
/* Program data. */
|
|
RW_MEM32(u32Addr) = (uint32_t)u32Data;
|
|
|
|
/* Wait for ready flag. */
|
|
if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) {
|
|
i32Ret = LL_ERR_NOT_RDY;
|
|
}
|
|
|
|
/* Get the flag PGMISMTCH */
|
|
if (SET == EFM_GetStatus(EFM_FLAG_PGMISMTCH << u8Shift)) {
|
|
/* Clear flag PGMISMTCH */
|
|
EFM_ClearStatus(EFM_FLAG_PGMISMTCH << u8Shift);
|
|
i32Ret = LL_ERR;
|
|
}
|
|
/* CLear the operation end flag. */
|
|
EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift);
|
|
/* Set read only mode. */
|
|
MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY);
|
|
|
|
/* recover CACHE function */
|
|
MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp);
|
|
|
|
return i32Ret;
|
|
}
|
|
|
|
/**
|
|
* @brief EFM program (sequence program mode).
|
|
* @param [in] u32Addr The specified program address.
|
|
* @param [in] pu8Buf The pointer of specified program data.
|
|
* @param [in] u32Len The length of specified program data.
|
|
* @retval int32_t:
|
|
* - LL_OK: Program successfully
|
|
* - LL_ERR_TIMEOUT: program error timeout
|
|
* @note Call EFM_REG_Unlock() unlock EFM register first.
|
|
* __EFM_FUNC default value is __RAM_FUNC.
|
|
*/
|
|
__EFM_FUNC int32_t EFM_SequenceProgram(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len)
|
|
{
|
|
int32_t i32Ret = LL_OK;
|
|
uint32_t u32Tmp;
|
|
uint32_t u32LoopWords = u32Len >> 2UL;
|
|
uint32_t u32RemainBytes = u32Len % 4UL;
|
|
uint32_t *u32pSource = (uint32_t *)(uint32_t)pu8Buf;
|
|
uint32_t *u32pDest = (uint32_t *)u32Addr;
|
|
uint32_t u32Timeout;
|
|
uint32_t u32LastWord;
|
|
|
|
/* Assert */
|
|
if (!IS_EFM_REG_UNLOCK()) {
|
|
return LL_ERR_NOT_RDY;
|
|
}
|
|
if ((!IS_EFM_FWMC_UNLOCK()) || (!IS_EFM_ADDR(u32Addr)) || (!IS_EFM_ADDR(u32Addr + u32Len - 1UL))) {
|
|
return LL_ERR_INVD_PARAM;
|
|
}
|
|
if (!IS_ADDR_ALIGN_WORD(u32Addr)) {
|
|
return LL_ERR_INVD_PARAM;
|
|
}
|
|
|
|
/* CLear the error flag. */
|
|
SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_ALL);
|
|
/* Get CACHE status */
|
|
u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
|
|
/* Disable CACHE */
|
|
CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
|
|
/* Set sequence program mode. */
|
|
MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SEQ);
|
|
|
|
while (u32LoopWords-- > 0UL) {
|
|
/* program data. */
|
|
*u32pDest++ = *u32pSource++;
|
|
/* wait for operation end flag. */
|
|
u32Timeout = 0UL;
|
|
while (EFM_FLAG_OPTEND != READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_OPTEND)) {
|
|
if (u32Timeout++ >= EFM_PGM_TIMEOUT) {
|
|
i32Ret = LL_ERR_TIMEOUT;
|
|
break;
|
|
}
|
|
}
|
|
/* Clear operation end flag */
|
|
u32Timeout = 0UL;
|
|
while (EFM_FLAG_OPTEND == READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_OPTEND)) {
|
|
SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_OPTEND);
|
|
if (u32Timeout++ >= EFM_TIMEOUT) {
|
|
i32Ret = LL_ERR_TIMEOUT;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (0U != u32RemainBytes) {
|
|
u32LastWord = *u32pSource;
|
|
u32LastWord |= 0xFFFFFFFFUL << (u32RemainBytes * 8UL);
|
|
*u32pDest++ = u32LastWord;
|
|
|
|
/* wait for operation end flag. */
|
|
u32Timeout = 0UL;
|
|
while (EFM_FLAG_OPTEND != READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_OPTEND)) {
|
|
if (u32Timeout++ >= EFM_PGM_TIMEOUT) {
|
|
i32Ret = LL_ERR_TIMEOUT;
|
|
break;
|
|
}
|
|
}
|
|
/* Clear operation end flag */
|
|
u32Timeout = 0UL;
|
|
while (EFM_FLAG_OPTEND == READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_OPTEND)) {
|
|
SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_OPTEND);
|
|
if (u32Timeout++ >= EFM_TIMEOUT) {
|
|
i32Ret = LL_ERR_TIMEOUT;
|
|
break;
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
/* Set read only mode. */
|
|
MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY);
|
|
/* Wait for ready flag. */
|
|
u32Timeout = 0UL;
|
|
while (EFM_FLAG_RDY != READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_RDY)) {
|
|
if (u32Timeout++ >= EFM_PGM_TIMEOUT) {
|
|
i32Ret = LL_ERR_TIMEOUT;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Recover CACHE */
|
|
MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp);
|
|
return i32Ret;
|
|
}
|
|
|
|
/**
|
|
* @brief EFM sector erase.
|
|
* @param [in] u32Addr The address in the specified sector.
|
|
* @retval int32_t:
|
|
* - LL_OK: Erase successful.
|
|
* - LL_ERR_NOT_RDY: EFM is not ready.
|
|
* @note Call EFM_REG_Unlock() unlock EFM register first.
|
|
*/
|
|
int32_t EFM_SectorErase(uint32_t u32Addr)
|
|
{
|
|
int32_t i32Ret = LL_OK;
|
|
uint32_t u32Tmp;
|
|
uint8_t u8Shift;
|
|
|
|
DDL_ASSERT(IS_EFM_ERASE_ADDR(u32Addr));
|
|
DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr));
|
|
DDL_ASSERT(IS_EFM_REG_UNLOCK());
|
|
DDL_ASSERT(IS_EFM_FWMC_UNLOCK());
|
|
|
|
/* CLear the error flag. */
|
|
EFM_ClearStatus(EFM_FLAG_ALL);
|
|
/* Get CACHE status */
|
|
u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
|
|
/* Disable CACHE */
|
|
CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
|
|
u8Shift = 0U;
|
|
/* Set sector erase mode. */
|
|
MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR);
|
|
|
|
/* Erase */
|
|
RW_MEM32(u32Addr) = 0UL;
|
|
|
|
/* Wait for ready flag. */
|
|
if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_ERASE_TIMEOUT)) {
|
|
i32Ret = LL_ERR_NOT_RDY;
|
|
}
|
|
/* Clear the operation end flag */
|
|
EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift);
|
|
/* Set read only mode. */
|
|
MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY);
|
|
/* Recover CACHE */
|
|
MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp);
|
|
|
|
return i32Ret;
|
|
}
|
|
|
|
/**
|
|
* @brief EFM chip erase.
|
|
* @param [in] u8Chip Specifies the chip to be erased @ref EFM_Chip_Sel
|
|
* @retval int32_t:
|
|
* - LL_OK: Erase successfully
|
|
* - LL_ERR_NOT_RDY: EFM is not ready.
|
|
* @note Call EFM_REG_Unlock() unlock EFM register first.
|
|
* __EFM_FUNC default value is __RAM_FUNC.
|
|
*/
|
|
__EFM_FUNC int32_t EFM_ChipErase(uint8_t u8Chip)
|
|
{
|
|
int32_t i32Ret = LL_OK;
|
|
uint32_t u32Tmp;
|
|
uint32_t u32Addr = 0UL;
|
|
uint8_t u8Shift;
|
|
uint32_t u32Timeout;
|
|
|
|
/* Assert */
|
|
if (!IS_EFM_REG_UNLOCK()) {
|
|
return LL_ERR_NOT_RDY;
|
|
}
|
|
if ((!IS_EFM_FWMC_UNLOCK()) || !IS_EFM_CHIP(u8Chip)) {
|
|
return LL_ERR_INVD_PARAM;
|
|
}
|
|
|
|
u8Shift = 0U;
|
|
|
|
/* CLear the error flag. */
|
|
SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_ALL);
|
|
/* Get CACHE status */
|
|
u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
|
|
/* Disable CACHE */
|
|
CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
|
|
|
|
if (EFM_CHIP_ALL == u8Chip) {
|
|
if (1UL == (READ_REG32(bCM_EFM->FSWP_b.FSWP))) {
|
|
/* Set Sector erase mode. */
|
|
MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR);
|
|
/* Disable flash switch function */
|
|
RW_MEM32(EFM_SWAP_ADDR) = 0x0UL;
|
|
/* wait for operation end flag. */
|
|
u32Timeout = 0UL;
|
|
while (EFM_FLAG_OPTEND != READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_OPTEND)) {
|
|
if (u32Timeout++ >= EFM_PGM_TIMEOUT) {
|
|
i32Ret = LL_ERR_TIMEOUT;
|
|
break;
|
|
}
|
|
}
|
|
/* CLear the operation end flag */
|
|
SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_OPTEND);
|
|
}
|
|
}
|
|
|
|
/* Set chip erase mode. */
|
|
MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_ALL_CHIP);
|
|
/* Erase */
|
|
RW_MEM32(u32Addr) = 0UL;
|
|
/* Wait for ready flag. */
|
|
u32Timeout = 0UL;
|
|
while ((EFM_FLAG_RDY << u8Shift) != READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_RDY << u8Shift)) {
|
|
if (u32Timeout++ >= EFM_ERASE_TIMEOUT) {
|
|
i32Ret = LL_ERR_TIMEOUT;
|
|
break;
|
|
}
|
|
}
|
|
/* CLear the operation end flag. */
|
|
SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_OPTEND << u8Shift);
|
|
/* Set read only mode. */
|
|
MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY);
|
|
|
|
/* recover CACHE */
|
|
MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp);
|
|
return i32Ret;
|
|
}
|
|
|
|
/**
|
|
* @brief FWMC register write enable or disable.
|
|
* @param [in] enNewState An @ref en_functional_state_t enumeration value.
|
|
* @retval None
|
|
*/
|
|
void EFM_FWMC_Cmd(en_functional_state_t enNewState)
|
|
{
|
|
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
|
|
|
|
WRITE_REG32(bCM_EFM->FWMC_b.PEMODE, enNewState);
|
|
}
|
|
|
|
/**
|
|
* @brief EFM OTP lock.
|
|
* @param [in] u32Addr Specifies the OTP block
|
|
* @retval int32_t:
|
|
* - LL_OK: Lock successfully
|
|
* - LL_ERR_NOT_RDY: EFM is not ready.
|
|
* @note The address should be word align.
|
|
* Call EFM_REG_Unlock() and EFM_OTP_WP_Unlock() unlock EFM_FWMC register first.
|
|
*/
|
|
int32_t EFM_OTP_Lock(uint32_t u32Addr)
|
|
{
|
|
int32_t i32Ret = LL_OK;
|
|
uint32_t u32Tmp;
|
|
|
|
if ((u32Addr >= EFM_OTP_LOCK_ADDR_START) && (u32Addr < EFM_OTP_LOCK_ADDR_END)) {
|
|
DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr));
|
|
DDL_ASSERT(IS_EFM_FWMC_UNLOCK());
|
|
DDL_ASSERT(IS_EFM_REG_UNLOCK());
|
|
/* Get CACHE status */
|
|
u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
|
|
/* Disable CACHE */
|
|
CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
|
|
|
|
/* Set single program mode. */
|
|
MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE);
|
|
|
|
/* OTP latch */
|
|
RW_MEM32(u32Addr) = (uint32_t)0UL;
|
|
/* Wait for ready flag. */
|
|
if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_ERASE_TIMEOUT)) {
|
|
i32Ret = LL_ERR_NOT_RDY;
|
|
}
|
|
/* CLear the operation end flag. */
|
|
EFM_ClearStatus(EFM_FLAG_OPTEND);
|
|
|
|
/* Set read only mode. */
|
|
MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY);
|
|
|
|
/* Recover CACHE */
|
|
MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp);
|
|
}
|
|
|
|
return i32Ret;
|
|
}
|
|
|
|
/**
|
|
* @brief Set flash protect area.
|
|
* @param [in] u32StartAddr Start address of protect area.
|
|
* @param [in] u32EndAddr End address of protect area.
|
|
* @retval None
|
|
* @note Call EFM_REG_Unlock() unlock EFM register first.
|
|
*/
|
|
void EFM_SetWindowProtectAddr(uint32_t u32StartAddr, uint32_t u32EndAddr)
|
|
{
|
|
DDL_ASSERT(IS_EFM_REG_UNLOCK());
|
|
DDL_ASSERT(IS_EFM_ADDR(u32StartAddr));
|
|
DDL_ASSERT(IS_EFM_ADDR(u32EndAddr));
|
|
/* Set protect area start address */
|
|
WRITE_REG32(CM_EFM->FPMTSW, u32StartAddr);
|
|
/* Set protect area end address */
|
|
WRITE_REG32(CM_EFM->FPMTEW, u32EndAddr);
|
|
}
|
|
|
|
/**
|
|
* @brief Get unique ID.
|
|
* @param [out] pstcUID Unique ID struct
|
|
* @retval Returns the value of the unique ID
|
|
*/
|
|
void EFM_GetUID(stc_efm_unique_id_t *pstcUID)
|
|
{
|
|
if (NULL != pstcUID) {
|
|
pstcUID->u32UniqueID0 = READ_REG32(CM_EFM->UQID0);
|
|
pstcUID->u32UniqueID1 = READ_REG32(CM_EFM->UQID1);
|
|
pstcUID->u32UniqueID2 = READ_REG32(CM_EFM->UQID2);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Init REMAP initial structure with default value.
|
|
* @param [in] pstcEfmRemapInit specifies the Parameter of REMAP.
|
|
* @retval int32_t:
|
|
* - LL_OK: Initialize success
|
|
* - LL_ERR_INVD_PARAM: NULL pointer
|
|
*/
|
|
int32_t EFM_REMAP_StructInit(stc_efm_remap_init_t *pstcEfmRemapInit)
|
|
{
|
|
int32_t i32Ret = LL_OK;
|
|
if (NULL == pstcEfmRemapInit) {
|
|
i32Ret = LL_ERR_INVD_PARAM;
|
|
} else {
|
|
pstcEfmRemapInit->u32State = EFM_REMAP_OFF;
|
|
pstcEfmRemapInit->u32Addr = 0UL;
|
|
pstcEfmRemapInit->u32Size = EFM_REMAP_4K;
|
|
}
|
|
return i32Ret;
|
|
}
|
|
|
|
/**
|
|
* @brief REMAP initialize.
|
|
* @param [in] u8RemapIdx Specifies the remap ID.
|
|
* @param [in] pstcEfmRemapInit specifies the Parameter of REMAP.
|
|
* @retval int32_t:
|
|
* - LL_OK: Initialize success
|
|
* - LL_ERR_INVD_PARAM: NULL pointer
|
|
*/
|
|
int32_t EFM_REMAP_Init(uint8_t u8RemapIdx, stc_efm_remap_init_t *pstcEfmRemapInit)
|
|
{
|
|
int32_t i32Ret = LL_OK;
|
|
__IO uint32_t *REMCRx;
|
|
|
|
if (NULL == pstcEfmRemapInit) {
|
|
i32Ret = LL_ERR_INVD_PARAM;
|
|
} else {
|
|
DDL_ASSERT(IS_EFM_REMAP_UNLOCK());
|
|
DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx));
|
|
DDL_ASSERT(IS_EFM_REMAP_SIZE(pstcEfmRemapInit->u32Size));
|
|
DDL_ASSERT(IS_EFM_REMAP_ADDR(pstcEfmRemapInit->u32Addr));
|
|
DDL_ASSERT(IS_EFM_REMAP_STATE(pstcEfmRemapInit->u32State));
|
|
if ((pstcEfmRemapInit->u32Addr % (1UL << pstcEfmRemapInit->u32Size)) != 0U) {
|
|
i32Ret = LL_ERR_INVD_PARAM;
|
|
} else {
|
|
REMCRx = &REMCR_REG(u8RemapIdx);
|
|
MODIFY_REG32(*REMCRx, EFM_MMF_REMCR_EN | EFM_MMF_REMCR_RMTADDR | EFM_MMF_REMCR_RMSIZE, \
|
|
pstcEfmRemapInit->u32State | pstcEfmRemapInit->u32Addr | pstcEfmRemapInit->u32Size);
|
|
}
|
|
}
|
|
return i32Ret;
|
|
}
|
|
|
|
/**
|
|
* @brief EFM REMAP de-initialize.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void EFM_REMAP_DeInit(void)
|
|
{
|
|
DDL_ASSERT(IS_EFM_REMAP_UNLOCK());
|
|
|
|
WRITE_REG32(CM_EFM->MMF_REMCR0, 0UL);
|
|
WRITE_REG32(CM_EFM->MMF_REMCR1, 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable or disable REMAP function.
|
|
* @param [in] u8RemapIdx Specifies the remap ID.
|
|
* @param [in] enNewState An @ref en_functional_state_t enumeration value.
|
|
* @retval None
|
|
*/
|
|
void EFM_REMAP_Cmd(uint8_t u8RemapIdx, en_functional_state_t enNewState)
|
|
{
|
|
__IO uint32_t *REMCRx;
|
|
|
|
DDL_ASSERT(IS_EFM_REMAP_UNLOCK());
|
|
DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx));
|
|
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
|
|
|
|
REMCRx = &REMCR_REG(u8RemapIdx);
|
|
if (ENABLE == enNewState) {
|
|
SET_REG32_BIT(*REMCRx, EFM_MMF_REMCR_EN);
|
|
} else {
|
|
CLR_REG32_BIT(*REMCRx, EFM_MMF_REMCR_EN);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Set specified REMAP target address.
|
|
* @param [in] u8RemapIdx Specifies the remap ID.
|
|
* @param [in] u32Addr Specifies the target address.
|
|
* @retval None
|
|
*/
|
|
void EFM_REMAP_SetAddr(uint8_t u8RemapIdx, uint32_t u32Addr)
|
|
{
|
|
__IO uint32_t *REMCRx;
|
|
|
|
DDL_ASSERT(IS_EFM_REMAP_UNLOCK());
|
|
DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx));
|
|
DDL_ASSERT(IS_EFM_REMAP_ADDR(u32Addr));
|
|
|
|
REMCRx = &REMCR_REG(u8RemapIdx);
|
|
MODIFY_REG32(*REMCRx, EFM_MMF_REMCR_RMTADDR, u32Addr);
|
|
}
|
|
|
|
/**
|
|
* @brief Set specified REMAP size.
|
|
* @param [in] u8RemapIdx Specifies the remap ID.
|
|
* @param [in] u32Size Specifies the remap size.
|
|
* @retval None
|
|
*/
|
|
void EFM_REMAP_SetSize(uint8_t u8RemapIdx, uint32_t u32Size)
|
|
{
|
|
__IO uint32_t *REMCRx;
|
|
|
|
DDL_ASSERT(IS_EFM_REMAP_UNLOCK());
|
|
DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx));
|
|
DDL_ASSERT(IS_EFM_REMAP_SIZE(u32Size));
|
|
|
|
REMCRx = &REMCR_REG(u8RemapIdx);
|
|
MODIFY_REG32(*REMCRx, EFM_MMF_REMCR_RMSIZE, u32Size);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable efm protect.
|
|
* @param [in] u8Level Specifies the protect level. @ref EFM_Protect_Level
|
|
* @retval None
|
|
*/
|
|
void EFM_Protect_Enable(uint8_t u8Level)
|
|
{
|
|
uint8_t u8Code[12] = {0};
|
|
|
|
(void)EFM_Program(EFM_SECURITY_ADDR1, u8Code, sizeof(u8Code));
|
|
if (EFM_PROTECT_LEVEL1 == u8Level) {
|
|
(void)EFM_ProgramWord(EFM_PROTECT1_ADDR, EFM_PROTECT1_KEY);
|
|
} else if (EFM_PROTECT_LEVEL2 == u8Level) {
|
|
(void)EFM_ProgramWord(EFM_PROTECT2_ADDR, EFM_PROTECT2_KEY);
|
|
} else {
|
|
/* rsvd */
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Write the security code.
|
|
* @param [in] pu8Buf Specifies the security code.
|
|
* @param [in] u32Len Specified the length of the security code.
|
|
* @retval int32_t
|
|
*/
|
|
int32_t EFM_WriteSecurityCode(uint8_t *pu8Buf, uint32_t u32Len)
|
|
{
|
|
int32_t i32Ret = LL_OK;
|
|
uint32_t u32Tmp;
|
|
uint32_t u32LoopWords = u32Len >> 2UL;
|
|
uint32_t *u32pSource = (uint32_t *)(uint32_t)pu8Buf;
|
|
uint32_t *u32pDest = (uint32_t *)EFM_SECURITY_ADDR;
|
|
|
|
DDL_ASSERT(IS_EFM_REG_UNLOCK());
|
|
DDL_ASSERT(IS_EFM_FWMC_UNLOCK());
|
|
DDL_ASSERT(IS_EFM_SECURITY_CODE_LEN(u32Len));
|
|
|
|
/* CLear the error flag. */
|
|
EFM_ClearStatus(EFM_FLAG_ALL);
|
|
/* Get CACHE status */
|
|
u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
|
|
/* Disable CACHE */
|
|
CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
|
|
|
|
/* Set sector erase mode. */
|
|
MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR);
|
|
/* Erase */
|
|
RW_MEM32(EFM_SECURITY_ADDR) = 0UL;
|
|
if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_PGM_TIMEOUT)) {
|
|
i32Ret = LL_ERR_NOT_RDY;
|
|
}
|
|
/* CLear the operation end flag. */
|
|
EFM_ClearStatus(EFM_FLAG_OPTEND);
|
|
|
|
/* Set single program mode. */
|
|
MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE);
|
|
|
|
while (u32LoopWords-- > 0UL) {
|
|
/* program data. */
|
|
*u32pDest++ = *u32pSource++;
|
|
/* Wait for ready flag. */
|
|
if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_PGM_TIMEOUT)) {
|
|
i32Ret = LL_ERR_NOT_RDY;
|
|
}
|
|
/* CLear the operation end flag. */
|
|
EFM_ClearStatus(EFM_FLAG_OPTEND);
|
|
}
|
|
|
|
/* Set read only mode. */
|
|
MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY);
|
|
|
|
/* Recover CACHE function */
|
|
MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp);
|
|
return i32Ret;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* LL_EFM_ENABLE */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/******************************************************************************
|
|
* EOF (not truncated)
|
|
*****************************************************************************/
|