232 lines
8.0 KiB
C
232 lines
8.0 KiB
C
/**
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*******************************************************************************
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* @file hc32_ll_sram.h
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* @brief This file contains all the functions prototypes of the SRAM driver
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* library.
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@verbatim
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Change Logs:
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Date Author Notes
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2022-03-31 CDT First version
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2022-10-31 CDT Deleted redundant comments
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2023-06-30 CDT Modify typo
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@endverbatim
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*******************************************************************************
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* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by XHSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#ifndef __HC32_LL_SRAM_H__
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#define __HC32_LL_SRAM_H__
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_ll_def.h"
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#include "hc32f4xx.h"
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#include "hc32f4xx_conf.h"
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/**
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* @addtogroup LL_Driver
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* @{
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*/
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/**
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* @addtogroup LL_SRAM
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* @{
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*/
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#if (LL_SRAM_ENABLE == DDL_ON)
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/**
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* @defgroup SRAM_Global_Macros SRAM Global Macros
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* @{
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*/
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/**
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* @defgroup SRAM_Sel SRAM Selection
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* @{
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*/
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#define SRAM_SRAMH (1UL << 2U) /*!< SRAMH: 0x1FFF8000~0x1FFFFFFF, 32KB */
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#define SRAM_SRAM12 (1UL << 0U) /*!< SRAM1: 0x20000000~0x2000FFFF, 64KB
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SRAM2: 0x20010000~0x2001FFFF, 64KB */
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#define SRAM_SRAM3 (1UL << 1U) /*!< SRAM3: 0x20020000~0x20026FFF, 28KB */
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#define SRAM_SRAMR (1UL << 3U) /*!< Ret_SRAM: 0x200F0000~0x200F0FFF, 4KB */
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#define SRAM_SRAM_ALL (SRAM_SRAMH | SRAM_SRAM12 | SRAM_SRAM3 | SRAM_SRAMR)
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#define SRAM_ECC_SRAM3 (SRAM_SRAM3)
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/**
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* @}
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*/
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/**
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* @defgroup SRAM_Access_Wait_Cycle SRAM Access Wait Cycle
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* @{
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*/
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#define SRAM_WAIT_CYCLE0 (0U) /*!< Wait 0 CPU cycle. */
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#define SRAM_WAIT_CYCLE1 (1U) /*!< Wait 1 CPU cycle. */
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#define SRAM_WAIT_CYCLE2 (2U) /*!< Wait 2 CPU cycles. */
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#define SRAM_WAIT_CYCLE3 (3U) /*!< Wait 3 CPU cycles. */
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#define SRAM_WAIT_CYCLE4 (4U) /*!< Wait 4 CPU cycles. */
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#define SRAM_WAIT_CYCLE5 (5U) /*!< Wait 5 CPU cycles. */
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#define SRAM_WAIT_CYCLE6 (6U) /*!< Wait 6 CPU cycles. */
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#define SRAM_WAIT_CYCLE7 (7U) /*!< Wait 7 CPU cycles. */
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/**
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* @}
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*/
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/**
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* @defgroup SRAM_Err_Mode SRAM Error Mode
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* @note Even-parity check error, ECC check error.
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* @{
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*/
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#define SRAM_ERR_MD_NMI (0UL) /*!< Non-maskable interrupt occurrence while check error occurs. */
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#define SRAM_ERR_MD_RST (1UL) /*!< System reset occurrence while check error occurs. */
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/**
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* @}
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*/
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/**
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* @defgroup SRAM_ECC_Mode SRAM ECC Mode
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* @{
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*/
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#define SRAM_ECC_MD_INVD (0U) /*!< The ECC mode is invalid. */
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#define SRAM_ECC_MD1 (SRAMC_CKCR_ECCMOD_0) /*!< When 1-bit error occurs:
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ECC error corrects.
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No 1-bit-error status flag setting, no interrupt or reset.
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When 2-bit error occurs:
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ECC error detects.
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2-bit-error status flag sets and interrupt or reset occurs. */
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#define SRAM_ECC_MD2 (SRAMC_CKCR_ECCMOD_1) /*!< When 1-bit error occurs:
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ECC error corrects.
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1-bit-error status flag sets, no interrupt or reset.
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When 2-bit error occurs:
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ECC error detects.
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2-bit-error status flag sets and interrupt or reset occurs. */
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#define SRAM_ECC_MD3 (SRAMC_CKCR_ECCMOD) /*!< When 1-bit error occurs:
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ECC error corrects.
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1-bit-error status flag sets and interrupt or reset occurs.
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When 2-bit error occurs:
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ECC error detects.
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2-bit-error status flag sets and interrupt or reset occurs. */
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/**
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* @}
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*/
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/**
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* @defgroup SRAM_Err_Status_Flag SRAM Error Status Flag
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* @{
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*/
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#define SRAM_FLAG_SRAM3_1ERR (SRAMC_CKSR_SRAM3_1ERR) /*!< SRAM3 ECC 1-bit error. */
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#define SRAM_FLAG_SRAM3_2ERR (SRAMC_CKSR_SRAM3_2ERR) /*!< SRAM3 ECC 2-bit error. */
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#define SRAM_FLAG_SRAM12_PYERR (SRAMC_CKSR_SRAM12_PYERR) /*!< SRAM12 parity error. */
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#define SRAM_FLAG_SRAMH_PYERR (SRAMC_CKSR_SRAMH_PYERR) /*!< SRAMH parity error. */
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#define SRAM_FLAG_SRAMR_PYERR (SRAMC_CKSR_SRAMR_PYERR) /*!< SRAMR parity error. */
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#define SRAM_FLAG_ALL (0x1FUL)
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/**
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* @}
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*/
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/**
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* @defgroup SRAM_Reg_Protect_Key SRAM Register Protect Key
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* @{
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*/
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#define SRAM_REG_LOCK_KEY (0x76U)
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#define SRAM_REG_UNLOCK_KEY (0x77U)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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Global function prototypes (definition in C source)
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******************************************************************************/
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/**
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* @addtogroup SRAM_Global_Functions
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* @{
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*/
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/**
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* @brief Lock SRAM registers, write protect.
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* @param None
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* @retval None
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*/
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__STATIC_INLINE void SRAM_REG_Lock(void)
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{
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WRITE_REG32(CM_SRAMC->WTPR, SRAM_REG_LOCK_KEY);
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WRITE_REG32(CM_SRAMC->CKPR, SRAM_REG_LOCK_KEY);
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}
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/**
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* @brief Unlock SRAM registers, write enable.
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* @param None
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* @retval None
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*/
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__STATIC_INLINE void SRAM_REG_Unlock(void)
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{
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WRITE_REG32(CM_SRAMC->WTPR, SRAM_REG_UNLOCK_KEY);
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WRITE_REG32(CM_SRAMC->CKPR, SRAM_REG_UNLOCK_KEY);
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}
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void SRAM_Init(void);
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void SRAM_DeInit(void);
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void SRAM_REG_Lock(void);
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void SRAM_REG_Unlock(void);
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void SRAM_SetWaitCycle(uint32_t u32SramSel, uint32_t u32WriteCycle, uint32_t u32ReadCycle);
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void SRAM_SetEccMode(uint32_t u32SramSel, uint32_t u32EccMode);
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void SRAM_SetErrorMode(uint32_t u32SramSel, uint32_t u32ErrMode);
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en_flag_status_t SRAM_GetStatus(uint32_t u32Flag);
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void SRAM_ClearStatus(uint32_t u32Flag);
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/**
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* @}
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*/
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#endif /* LL_SRAM_ENABLE */
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HC32_LL_SRAM_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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