初始版本
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/**
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*******************************************************************************
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* @file hc32_ll_clk.h
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* @brief This file contains all the functions prototypes of the CLK driver
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* library.
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@verbatim
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Change Logs:
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Date Author Notes
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2022-03-31 CDT First version
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2022-06-30 CDT Refine stc_clock_freq_t
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@endverbatim
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*******************************************************************************
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* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by XHSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#ifndef __HC32_LL_CLK_H__
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#define __HC32_LL_CLK_H__
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_ll_def.h"
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#include "hc32f4xx.h"
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#include "hc32f4xx_conf.h"
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/**
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* @addtogroup LL_Driver
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* @{
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*/
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/**
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* @addtogroup LL_CLK
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* @{
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*/
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#if (LL_CLK_ENABLE == DDL_ON)
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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* @defgroup CLK_Global_Types CLK Global Types
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* @{
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*/
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/**
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* @brief CLK XTAL configuration structure definition
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*/
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typedef struct {
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uint8_t u8State; /*!< The new state of the XTAL.
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This parameter can be a value of @ref CLK_XTAL_Config */
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uint8_t u8Drv; /*!< The XTAL drive ability.
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This parameter can be a value of @ref CLK_XTAL_Config */
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uint8_t u8Mode; /*!< The XTAL mode selection osc or exclk.
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This parameter can be a value of @ref CLK_XTAL_Config */
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uint8_t u8SuperDrv; /*!< The XTAL super drive on or off.
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This parameter can be a value of @ref CLK_XTAL_Config */
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uint8_t u8StableTime; /*!< The XTAL stable time selection.
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This parameter can be a value of @ref CLK_XTAL_Config */
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} stc_clock_xtal_init_t;
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/**
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* @brief CLK XTAL fault detect configuration structure definition
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*/
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typedef struct {
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uint8_t u8State; /*!< Specifies the new state of XTALSTD.
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This parameter can be a value of @ref CLK_XTALSTD_Config */
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uint8_t u8Mode; /*!< Specifies the XTALSTD mode.
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This parameter can be a value of @ref CLK_XTALSTD_Config */
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uint8_t u8Int; /*!< Specifies the XTALSTD interrupt on or off.
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This parameter can be a value of @ref CLK_XTALSTD_Config */
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uint8_t u8Reset; /*!< Specifies the XTALSTD reset on or off.
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This parameter can be a value of @ref CLK_XTALSTD_Config */
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} stc_clock_xtalstd_init_t;
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/**
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* @brief CLK XTAL32 configuration structure definition
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*/
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typedef struct {
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uint8_t u8State; /*!< Xtal32 new state,
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@ref CLK_XTAL32_Config for details */
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uint8_t u8Drv; /*!< Xtal32 drive capacity setting,
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@ref CLK_XTAL32_Config for details */
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uint8_t u8Filter; /*!< Xtal32 noise filter setting,
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@ref CLK_XTAL32_Config for details */
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} stc_clock_xtal32_init_t;
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/**
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* @brief CLK clock frequency configuration structure definition
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*/
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typedef struct {
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union {
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uint32_t SCFGR; /*!< clock frequency config register */
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struct {
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uint32_t PCLK0S : 3; /*!< PCLK0 */
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uint32_t resvd0 : 1; /*!< reserved */
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uint32_t PCLK1S : 3; /*!< PCLK1 */
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uint32_t resvd1 : 1; /*!< reserved */
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uint32_t PCLK2S : 3; /*!< PCLK2 */
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uint32_t resvd2 : 1; /*!< reserved */
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uint32_t PCLK3S : 3; /*!< PCLK3 */
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uint32_t resvd3 : 1; /*!< reserved */
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uint32_t PCLK4S : 3; /*!< PCLK4 */
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uint32_t resvd4 : 1; /*!< reserved */
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uint32_t EXCKS : 3; /*!< EXCLK */
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uint32_t resvd5 : 1; /*!< reserved */
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uint32_t HCLKS : 3; /*!< HCLK */
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uint32_t resvd6 : 5; /*!< reserved */
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} SCFGR_f;
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};
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} stc_clock_scale_t;
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/**
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* @brief CLK PLL configuration structure definition
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* @note PLL for MPLL
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*/
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typedef struct {
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uint8_t u8PLLState; /*!< PLL new state, @ref CLK_PLL_Config for details */
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union {
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uint32_t PLLCFGR; /*!< PLL config register */
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struct {
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uint32_t PLLM : 5; /*!< PLL M divide */
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uint32_t resvd0 : 2; /*!< reserved */
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uint32_t PLLSRC : 1; /*!< PLL/PLLA source clock select */
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uint32_t PLLN : 9; /*!< PLL N multi */
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uint32_t resvd1 : 3; /*!< reserved */
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uint32_t PLLR : 4; /*!< PLL R divide */
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uint32_t PLLQ : 4; /*!< PLL Q divide */
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uint32_t PLLP : 4; /*!< PLL P divide */
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} PLLCFGR_f;
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};
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} stc_clock_pll_init_t;
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/**
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* @brief CLK PLLx configuration structure definition
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* @note PLLx for UPLL while HC32F460,HC32F451,HC32F452
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* PLLx for PLLA while HC32F4A0
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*/
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typedef struct {
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uint8_t u8PLLState; /*!< PLLx new state, @ref CLK_PLLx_State for details */
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union {
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uint32_t PLLCFGR; /*!< PLLx config register */
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struct {
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uint32_t PLLM : 5; /*!< PLLx M divide */
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uint32_t resvd0 : 3; /*!< reserved */
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uint32_t PLLN : 9; /*!< PLLx N multi- */
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uint32_t resvd1 : 3; /*!< reserved */
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uint32_t PLLR : 4; /*!< PLLx R divide */
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uint32_t PLLQ : 4; /*!< PLLx Q divide */
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uint32_t PLLP : 4; /*!< PLLx P divide */
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} PLLCFGR_f;
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};
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} stc_clock_pllx_init_t;
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/**
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* @brief CLK bus frequency structure definition
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*/
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typedef struct {
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uint32_t u32SysclkFreq; /*!< System clock frequency. */
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uint32_t u32HclkFreq; /*!< Hclk frequency. */
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uint32_t u32Pclk0Freq; /*!< Pclk0 frequency. */
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uint32_t u32Pclk1Freq; /*!< Pclk1 frequency. */
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uint32_t u32Pclk2Freq; /*!< Pclk2 frequency. */
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uint32_t u32Pclk3Freq; /*!< Pclk3 frequency. */
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uint32_t u32Pclk4Freq; /*!< Pclk4 frequency. */
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uint32_t u32ExclkFreq; /*!< Exclk frequency. */
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} stc_clock_freq_t;
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/**
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* @brief CLK PLL clock frequency structure definition
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*/
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typedef struct {
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uint32_t u32PllVcin; /*!< PLL vcin clock frequency. */
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uint32_t u32PllVco; /*!< PLL vco clock frequency. */
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uint32_t u32PllP; /*!< PLLp clock frequency. */
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uint32_t u32PllQ; /*!< PLLq clock frequency. */
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uint32_t u32PllR; /*!< PLLr clock frequency. */
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uint32_t u32PllxVcin; /*!< pllx vcin clock frequency. */
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uint32_t u32PllxVco; /*!< pllx vco clock frequency. */
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uint32_t u32PllxP; /*!< pllxp clock frequency. */
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uint32_t u32PllxQ; /*!< pllxq clock frequency. */
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uint32_t u32PllxR; /*!< pllxr clock frequency. */
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} stc_pll_clock_freq_t;
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/**
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* @}
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*/
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/**
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* @defgroup CLK_Global_Macros CLK Global Macros
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* @{
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*/
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/**
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* @defgroup CLK_PLLx_State CLK PLLx State
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* @note PLLx for UPLL while HC32F460,HC32F451,HC32F452
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* PLLx for PLLA while HC32F4A0
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* @{
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*/
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#define CLK_PLLX_OFF (0x01U)
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#define CLK_PLLX_ON (0x00U)
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/**
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* @}
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*/
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/**
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* @defgroup CLK_PLL_Config PLL Config
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* @{
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*/
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/**
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* @brief PLL function config.
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*/
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#define CLK_PLL_OFF (0x01U)
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#define CLK_PLL_ON (0x00U)
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/**
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* @brief PLL source clock selection.
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*/
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#define CLK_PLL_SRC_XTAL (0x00UL)
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#define CLK_PLL_SRC_HRC (0x01UL)
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/**
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* @}
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*/
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/**
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* @defgroup CLK_XTAL_Config XTAL Config
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* @{
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*/
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/**
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* @brief XTAL function config.
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*/
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#define CLK_XTAL_OFF (CMU_XTALCR_XTALSTP)
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#define CLK_XTAL_ON (0x00U)
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/**
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* @brief XTAL driver ability
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* @note
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* @verbatim
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* High | Mid | Low | ULow |
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* [20~25] | [16~20) | (8~16) | [4~8] |
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* @endverbatim
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*/
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#define CLK_XTAL_DRV_HIGH (0x00U << CMU_XTALCFGR_XTALDRV_POS)
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#define CLK_XTAL_DRV_MID (0x01U << CMU_XTALCFGR_XTALDRV_POS)
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#define CLK_XTAL_DRV_LOW (0x02U << CMU_XTALCFGR_XTALDRV_POS)
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#define CLK_XTAL_DRV_ULOW (0x03U << CMU_XTALCFGR_XTALDRV_POS)
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/**
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* @brief XTAL super drive on or off
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*/
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#define CLK_XTAL_SUPDRV_ON (CMU_XTALCFGR_SUPDRV)
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#define CLK_XTAL_SUPDRV_OFF (0x00U)
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/**
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* @brief XTAL mode selection osc or exclk
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*/
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#define CLK_XTAL_MD_OSC (0x00U)
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#define CLK_XTAL_MD_EXCLK (CMU_XTALCFGR_XTALMS)
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/**
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* @brief XTAL stable time selection.
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* @note a cycle of stable counter = a cycle of LRC divide by 8
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*/
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#define CLK_XTAL_STB_133US (0x01U) /*!< 35 stable count cycle, approx. 133us */
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#define CLK_XTAL_STB_255US (0x02U) /*!< 67 stable count cycle, approx. 255us */
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#define CLK_XTAL_STB_499US (0x03U) /*!< 131 stable count cycle, approx. 499us */
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#define CLK_XTAL_STB_988US (0x04U) /*!< 259 stable count cycle, approx. 988us */
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#define CLK_XTAL_STB_2MS (0x05U) /*!< 547 stable count cycle, approx. 2ms */
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#define CLK_XTAL_STB_4MS (0x06U) /*!< 1059 stable count cycle, approx. 4ms */
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#define CLK_XTAL_STB_8MS (0x07U) /*!< 2147 stable count cycle, approx. 8ms */
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#define CLK_XTAL_STB_16MS (0x08U) /*!< 4291 stable count cycle, approx. 16ms */
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#define CLK_XTAL_STB_31MS (0x09U) /*!< 8163 stable count cycle, approx. 32ms */
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/**
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* @}
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*/
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/**
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* @defgroup CLK_XTALSTD_Config XTALSTD Config
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* @{
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*/
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/**
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* @brief XTAL error detection on or off
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*/
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#define CLK_XTALSTD_OFF (0x00U)
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#define CLK_XTALSTD_ON (CMU_XTALSTDCR_XTALSTDE)
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/**
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* @brief XTALSTD mode selection
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*/
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#define CLK_XTALSTD_MD_RST (CMU_XTALSTDCR_XTALSTDRIS)
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#define CLK_XTALSTD_MD_INT (0x00U)
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/**
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* @brief XTALSTD reset on or off
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*/
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#define CLK_XTALSTD_RST_OFF (0x00U)
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#define CLK_XTALSTD_RST_ON (CMU_XTALSTDCR_XTALSTDRE)
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/**
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* @brief XTALSTD interrupt on or off
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*/
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#define CLK_XTALSTD_INT_OFF (0x00U)
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#define CLK_XTALSTD_INT_ON (CMU_XTALSTDCR_XTALSTDIE)
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/**
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* @}
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*/
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/**
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* @defgroup CLK_XTAL32_Config XTAL32 Config
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* @{
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*/
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/**
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* @brief XTAL32 function config.
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*/
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#define CLK_XTAL32_OFF (CMU_XTAL32CR_XTAL32STP)
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#define CLK_XTAL32_ON (0x00U)
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/**
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* @brief XTAL32 driver ability.
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*/
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#define CLK_XTAL32_DRV_MID (0x00U)
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#define CLK_XTAL32_DRV_HIGH (0x01U)
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/**
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* @brief XTAL32 filtering selection.
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*/
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#define CLK_XTAL32_FILTER_ALL_MD (0x00U) /*!< Valid in run,stop,power down mode. */
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#define CLK_XTAL32_FILTER_RUN_MD (0x01U) /*!< Valid in run mode. */
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#define CLK_XTAL32_FILTER_OFF (0x03U) /*!< Invalid in run,stop,power down mode. */
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/**
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* @}
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*/
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/**
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* @defgroup CLK_HRC_Config HRC Config
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* @{
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*/
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#define CLK_HRC_OFF (CMU_HRCCR_HRCSTP)
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#define CLK_HRC_ON (0x00U)
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/**
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* @}
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*/
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/**
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* @defgroup CLK_STB_Flag CLK Stable Flags
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* @{
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*/
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#define CLK_STB_FLAG_HRC (CMU_OSCSTBSR_HRCSTBF)
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#define CLK_STB_FLAG_XTAL (CMU_OSCSTBSR_XTALSTBF)
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#define CLK_STB_FLAG_PLL (CMU_OSCSTBSR_MPLLSTBF)
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#define CLK_STB_FLAG_PLLX (CMU_OSCSTBSR_UPLLSTBF)
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#define CLK_STB_FLAG_MASK (CMU_OSCSTBSR_HRCSTBF | CMU_OSCSTBSR_XTALSTBF | \
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CMU_OSCSTBSR_MPLLSTBF | CMU_OSCSTBSR_UPLLSTBF)
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/**
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* @}
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*/
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/**
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* @defgroup CLK_System_Clock_Source System Clock Source
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* @{
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*/
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#define CLK_SYSCLK_SRC_HRC (0x00U)
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#define CLK_SYSCLK_SRC_MRC (0x01U)
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#define CLK_SYSCLK_SRC_LRC (0x02U)
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#define CLK_SYSCLK_SRC_XTAL (0x03U)
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#define CLK_SYSCLK_SRC_XTAL32 (0x04U)
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#define CLK_SYSCLK_SRC_PLL (0x05U)
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/**
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* @}
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*/
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/**
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* @defgroup CLK_Bus_Clock_Sel Clock Bus Clock Category Selection
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* @{
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*/
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#define CLK_BUS_PCLK0 (CMU_SCFGR_PCLK0S)
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#define CLK_BUS_PCLK1 (CMU_SCFGR_PCLK1S)
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#define CLK_BUS_PCLK2 (CMU_SCFGR_PCLK2S)
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#define CLK_BUS_PCLK3 (CMU_SCFGR_PCLK3S)
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#define CLK_BUS_PCLK4 (CMU_SCFGR_PCLK4S)
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#define CLK_BUS_EXCLK (CMU_SCFGR_EXCKS)
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#define CLK_BUS_HCLK (CMU_SCFGR_HCLKS)
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#define CLK_BUS_CLK_ALL (CLK_BUS_PCLK0 | CLK_BUS_PCLK1 | CLK_BUS_PCLK2 | CLK_BUS_PCLK3 | \
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CLK_BUS_PCLK4 | CLK_BUS_EXCLK | CLK_BUS_HCLK)
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/**
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* @}
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*/
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/**
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* @defgroup CLK_Clock_Divider Clock Divider
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* @{
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*/
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/**
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* @defgroup CLK_System_Clock_Divider System Clock Divider
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* @{
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*/
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#define CLK_SYSCLK_DIV1 (0x00U)
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#define CLK_SYSCLK_DIV2 (0x01U)
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#define CLK_SYSCLK_DIV4 (0x02U)
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#define CLK_SYSCLK_DIV8 (0x03U)
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#define CLK_SYSCLK_DIV16 (0x04U)
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#define CLK_SYSCLK_DIV32 (0x05U)
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#define CLK_SYSCLK_DIV64 (0x06U)
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/**
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* @}
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||||
*/
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||||
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||||
/**
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||||
* @defgroup CLK_HCLK_Divider CLK HCLK Divider
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||||
* @{
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||||
*/
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#define CLK_HCLK_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_HCLKS_POS)
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#define CLK_HCLK_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_HCLKS_POS)
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#define CLK_HCLK_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_HCLKS_POS)
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#define CLK_HCLK_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_HCLKS_POS)
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#define CLK_HCLK_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_HCLKS_POS)
|
||||
#define CLK_HCLK_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_HCLKS_POS)
|
||||
#define CLK_HCLK_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_HCLKS_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_PCLK1_Divider CLK PCLK1 Divider
|
||||
* @{
|
||||
*/
|
||||
#define CLK_PCLK1_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK1S_POS)
|
||||
#define CLK_PCLK1_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK1S_POS)
|
||||
#define CLK_PCLK1_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK1S_POS)
|
||||
#define CLK_PCLK1_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK1S_POS)
|
||||
#define CLK_PCLK1_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK1S_POS)
|
||||
#define CLK_PCLK1_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK1S_POS)
|
||||
#define CLK_PCLK1_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK1S_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_PCLK4_Divider CLK PCLK4 Divider
|
||||
* @{
|
||||
*/
|
||||
#define CLK_PCLK4_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK4S_POS)
|
||||
#define CLK_PCLK4_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK4S_POS)
|
||||
#define CLK_PCLK4_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK4S_POS)
|
||||
#define CLK_PCLK4_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK4S_POS)
|
||||
#define CLK_PCLK4_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK4S_POS)
|
||||
#define CLK_PCLK4_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK4S_POS)
|
||||
#define CLK_PCLK4_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK4S_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_PCLK3_Divider CLK PCLK3 Divider
|
||||
* @{
|
||||
*/
|
||||
#define CLK_PCLK3_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK3S_POS)
|
||||
#define CLK_PCLK3_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK3S_POS)
|
||||
#define CLK_PCLK3_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK3S_POS)
|
||||
#define CLK_PCLK3_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK3S_POS)
|
||||
#define CLK_PCLK3_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK3S_POS)
|
||||
#define CLK_PCLK3_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK3S_POS)
|
||||
#define CLK_PCLK3_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK3S_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_EXCLK_Divider CLK EXCLK Divider
|
||||
* @{
|
||||
*/
|
||||
#define CLK_EXCLK_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_EXCKS_POS)
|
||||
#define CLK_EXCLK_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_EXCKS_POS)
|
||||
#define CLK_EXCLK_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_EXCKS_POS)
|
||||
#define CLK_EXCLK_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_EXCKS_POS)
|
||||
#define CLK_EXCLK_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_EXCKS_POS)
|
||||
#define CLK_EXCLK_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_EXCKS_POS)
|
||||
#define CLK_EXCLK_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_EXCKS_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_PCLK2_Divider CLK PCLK2 Divider
|
||||
* @{
|
||||
*/
|
||||
#define CLK_PCLK2_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK2S_POS)
|
||||
#define CLK_PCLK2_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK2S_POS)
|
||||
#define CLK_PCLK2_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK2S_POS)
|
||||
#define CLK_PCLK2_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK2S_POS)
|
||||
#define CLK_PCLK2_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK2S_POS)
|
||||
#define CLK_PCLK2_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK2S_POS)
|
||||
#define CLK_PCLK2_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK2S_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_PCLK0_Divider CLK PCLK0 Divider
|
||||
* @{
|
||||
*/
|
||||
#define CLK_PCLK0_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK0S_POS)
|
||||
#define CLK_PCLK0_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK0S_POS)
|
||||
#define CLK_PCLK0_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK0S_POS)
|
||||
#define CLK_PCLK0_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK0S_POS)
|
||||
#define CLK_PCLK0_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK0S_POS)
|
||||
#define CLK_PCLK0_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK0S_POS)
|
||||
#define CLK_PCLK0_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK0S_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_USBCLK_Sel CLK USB Clock Selection
|
||||
* @{
|
||||
*/
|
||||
#define CLK_USBCLK_SYSCLK_DIV2 (0x02U << CMU_USBCKCFGR_USBCKS_POS)
|
||||
#define CLK_USBCLK_SYSCLK_DIV3 (0x03U << CMU_USBCKCFGR_USBCKS_POS)
|
||||
#define CLK_USBCLK_SYSCLK_DIV4 (0x04U << CMU_USBCKCFGR_USBCKS_POS)
|
||||
#define CLK_USBCLK_PLLP (0x08U << CMU_USBCKCFGR_USBCKS_POS)
|
||||
#define CLK_USBCLK_PLLQ (0x09U << CMU_USBCKCFGR_USBCKS_POS)
|
||||
#define CLK_USBCLK_PLLR (0x0AU << CMU_USBCKCFGR_USBCKS_POS)
|
||||
#define CLK_USBCLK_PLLXP (0x0BU << CMU_USBCKCFGR_USBCKS_POS)
|
||||
#define CLK_USBCLK_PLLXQ (0x0CU << CMU_USBCKCFGR_USBCKS_POS)
|
||||
#define CLK_USBCLK_PLLXR (0x0DU << CMU_USBCKCFGR_USBCKS_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_PERIPH_Sel CLK Peripheral Clock Selection
|
||||
* @note ADC,I2S,DAC,TRNG
|
||||
* @{
|
||||
*/
|
||||
/* PCLK2 is used for ADC clock, PCLK3 is used for I2S clock, PCLK4 is used for DAC/TRNG clock */
|
||||
#define CLK_PERIPHCLK_PCLK (0x0000U)
|
||||
#define CLK_PERIPHCLK_PLLP (0x0008U)
|
||||
#define CLK_PERIPHCLK_PLLQ (0x0009U)
|
||||
#define CLK_PERIPHCLK_PLLR (0x000AU)
|
||||
#define CLK_PERIPHCLK_PLLXP (0x000BU)
|
||||
#define CLK_PERIPHCLK_PLLXQ (0x000CU)
|
||||
#define CLK_PERIPHCLK_PLLXR (0x000DU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_I2S_Sel CLK I2S Channel Selection
|
||||
* @{
|
||||
*/
|
||||
#define CLK_I2S1 (0x00U)
|
||||
#define CLK_I2S2 (0x01U)
|
||||
#define CLK_I2S3 (0x02U)
|
||||
#define CLK_I2S4 (0x03U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_TPIU_Divider TPIU clock divider
|
||||
* @{
|
||||
*/
|
||||
#define CLK_TPIUCLK_DIV1 (0x00U)
|
||||
#define CLK_TPIUCLK_DIV2 (0x01U)
|
||||
#define CLK_TPIUCLK_DIV4 (0x02U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_MCO_Channel_Sel CLK MCO Channel Select
|
||||
* @{
|
||||
*/
|
||||
#define CLK_MCO1 (0x00U)
|
||||
#define CLK_MCO2 (0x01U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_MCO_Clock_Source CLK MCO Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define CLK_MCO_SRC_HRC (0x00U)
|
||||
#define CLK_MCO_SRC_MRC (0x01U)
|
||||
#define CLK_MCO_SRC_LRC (0x02U)
|
||||
#define CLK_MCO_SRC_XTAL (0x03U)
|
||||
#define CLK_MCO_SRC_XTAL32 (0x04U)
|
||||
#define CLK_MCO_SRC_PLLP (0x06U)
|
||||
#define CLK_MCO_SRC_PLLXP (0x07U)
|
||||
#define CLK_MCO_SRC_PLLQ (0x08U)
|
||||
#define CLK_MCO_SRC_PLLXQ (0x09U)
|
||||
#define CLK_MCO_SRC_HCLK (0x0BU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_MCO_Clock_Prescaler CLK MCO Clock Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define CLK_MCO_DIV1 (0x00U << CMU_MCOCFGR_MCODIV_POS)
|
||||
#define CLK_MCO_DIV2 (0x01U << CMU_MCOCFGR_MCODIV_POS)
|
||||
#define CLK_MCO_DIV4 (0x02U << CMU_MCOCFGR_MCODIV_POS)
|
||||
#define CLK_MCO_DIV8 (0x03U << CMU_MCOCFGR_MCODIV_POS)
|
||||
#define CLK_MCO_DIV16 (0x04U << CMU_MCOCFGR_MCODIV_POS)
|
||||
#define CLK_MCO_DIV32 (0x05U << CMU_MCOCFGR_MCODIV_POS)
|
||||
#define CLK_MCO_DIV64 (0x06U << CMU_MCOCFGR_MCODIV_POS)
|
||||
#define CLK_MCO_DIV128 (0x07U << CMU_MCOCFGR_MCODIV_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup CLK_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
int32_t CLK_HrcCmd(en_functional_state_t enNewState);
|
||||
int32_t CLK_MrcCmd(en_functional_state_t enNewState);
|
||||
int32_t CLK_LrcCmd(en_functional_state_t enNewState);
|
||||
|
||||
void CLK_HrcTrim(int8_t i8TrimVal);
|
||||
void CLK_MrcTrim(int8_t i8TrimVal);
|
||||
void CLK_LrcTrim(int8_t i8TrimVal);
|
||||
|
||||
int32_t CLK_XtalStructInit(stc_clock_xtal_init_t *pstcXtalInit);
|
||||
int32_t CLK_XtalInit(const stc_clock_xtal_init_t *pstcXtalInit);
|
||||
int32_t CLK_XtalCmd(en_functional_state_t enNewState);
|
||||
|
||||
int32_t CLK_XtalStdStructInit(stc_clock_xtalstd_init_t *pstcXtalStdInit);
|
||||
int32_t CLK_XtalStdInit(const stc_clock_xtalstd_init_t *pstcXtalStdInit);
|
||||
void CLK_ClearXtalStdStatus(void);
|
||||
en_flag_status_t CLK_GetXtalStdStatus(void);
|
||||
|
||||
int32_t CLK_Xtal32StructInit(stc_clock_xtal32_init_t *pstcXtal32Init);
|
||||
int32_t CLK_Xtal32Init(const stc_clock_xtal32_init_t *pstcXtal32Init);
|
||||
int32_t CLK_Xtal32Cmd(en_functional_state_t enNewState);
|
||||
|
||||
void CLK_SetPLLSrc(uint32_t u32PllSrc);
|
||||
int32_t CLK_PLLStructInit(stc_clock_pll_init_t *pstcPLLInit);
|
||||
int32_t CLK_PLLInit(const stc_clock_pll_init_t *pstcPLLInit);
|
||||
int32_t CLK_PLLCmd(en_functional_state_t enNewState);
|
||||
int32_t CLK_GetPLLClockFreq(stc_pll_clock_freq_t *pstcPllClkFreq);
|
||||
int32_t CLK_PLLxStructInit(stc_clock_pllx_init_t *pstcPLLxInit);
|
||||
int32_t CLK_PLLxInit(const stc_clock_pllx_init_t *pstcPLLxInit);
|
||||
int32_t CLK_PLLxCmd(en_functional_state_t enNewState);
|
||||
|
||||
void CLK_MCOConfig(uint8_t u8Ch, uint8_t u8Src, uint8_t u8Div);
|
||||
void CLK_MCOCmd(uint8_t u8Ch, en_functional_state_t enNewState);
|
||||
|
||||
en_flag_status_t CLK_GetStableStatus(uint8_t u8Flag);
|
||||
void CLK_SetSysClockSrc(uint8_t u8Src);
|
||||
void CLK_SetClockDiv(uint32_t u32Clock, uint32_t u32Div);
|
||||
int32_t CLK_GetClockFreq(stc_clock_freq_t *pstcClockFreq);
|
||||
uint32_t CLK_GetBusClockFreq(uint32_t u32Clock);
|
||||
|
||||
void CLK_SetPeriClockSrc(uint16_t u16Src);
|
||||
void CLK_SetUSBClockSrc(uint8_t u8Src);
|
||||
void CLK_SetI2SClockSrc(uint8_t u8Unit, uint8_t u8Src);
|
||||
|
||||
void CLK_TpiuClockCmd(en_functional_state_t enNewState);
|
||||
void CLK_SetTpiuClockDiv(uint8_t u8Div);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_CLK_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_CLK_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
Reference in New Issue
Block a user