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/**
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*******************************************************************************
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* @file system_hc32f460.c
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* @brief This file provides two functions and two global variables to be called
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* from user application.
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@verbatim
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Change Logs:
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Date Author Notes
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2022-03-31 CDT First version
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2022-10-31 CDT Delete the __low_level_init function of IAR and $Sub$$main function of MDK
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@endverbatim
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*******************************************************************************
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* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by XHSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "system_hc32f460.h"
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/**
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* @addtogroup CMSIS
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* @{
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*/
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/**
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* @addtogroup HC32F460_System
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* @{
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*/
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/*******************************************************************************
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* Global pre-processor symbols/macros ('define')
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******************************************************************************/
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/**
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* @defgroup HC32F460_System_Local_Macros HC32F460 System Local Macros
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* @{
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*/
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#define HRC_16MHz_VALUE (16000000UL) /*!< Internal high speed RC freq. */
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#define HRC_20MHz_VALUE (20000000UL) /*!< Internal high speed RC freq. */
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/* HRC select */
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#define HRC_FREQ_MON() (*((volatile uint32_t *)(0x40010684UL)))
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/* Vector Table base offset field */
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#ifndef VECT_TAB_OFFSET
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#define VECT_TAB_OFFSET (0x0UL) /*!< This value must be a multiple of 0x400. */
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#endif
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/**
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* @}
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*/
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/*******************************************************************************
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* Global variable definitions (declared in header file with 'extern')
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******************************************************************************/
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/**
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* @addtogroup HC32F460_System_Global_Variable
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* @{
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*/
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/*!< System clock frequency (Core clock) */
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__NO_INIT uint32_t SystemCoreClock;
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/*!< High speed RC frequency (HCR clock) */
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__NO_INIT uint32_t HRC_VALUE;
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/**
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* @}
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*/
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/*******************************************************************************
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* Local variable definitions ('static')
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******************************************************************************/
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/*******************************************************************************
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* Function implementation - global ('extern') and local ('static')
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******************************************************************************/
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/**
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* @addtogroup HC32F460_System_Global_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system. Initialize the System and update
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* the SystemCoreClock variable.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* Configure the Vector Table relocation */
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extern unsigned char Image$$ER_IROM1$$Base;
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uint32_t rom_base =0u;
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rom_base= (uint32_t)&Image$$ER_IROM1$$Base;
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/* FPU settings */
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 20) | (3UL << 22)); /* set CP10 and CP11 Full Access */
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#endif
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SystemCoreClockUpdate();
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#if defined (ROM_EXT_QSPI)
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SystemInit_QspiMem();
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#endif /* ROM_EXT_QSPI */
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SCB->VTOR = rom_base; /* Vector Table Relocation */
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate(void)
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{
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uint8_t u8SysClkSrc;
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uint32_t plln;
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uint32_t pllp;
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uint32_t pllm;
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uint32_t u32PllSrcFreq;
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/* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */
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if (1UL == (HRC_FREQ_MON() & 1UL)) {
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HRC_VALUE = HRC_16MHz_VALUE;
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} else {
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HRC_VALUE = HRC_20MHz_VALUE;
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}
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u8SysClkSrc = CM_CMU->CKSWR & CMU_CKSWR_CKSW;
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switch (u8SysClkSrc) {
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case 0x00U: /* use internal high speed RC */
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SystemCoreClock = HRC_VALUE;
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break;
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case 0x01U: /* use internal middle speed RC */
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SystemCoreClock = MRC_VALUE;
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break;
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case 0x02U: /* use internal low speed RC */
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SystemCoreClock = LRC_VALUE;
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break;
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case 0x03U: /* use external high speed OSC */
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SystemCoreClock = XTAL_VALUE;
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break;
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case 0x04U: /* use external low speed OSC */
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SystemCoreClock = XTAL32_VALUE;
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break;
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case 0x05U: /* use MPLL */
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/* PLLCLK = ((pllsrc / pllm) * plln) / pllp */
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plln = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLN) >> CMU_PLLCFGR_MPLLN_POS;
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pllp = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLP) >> CMU_PLLCFGR_MPLLP_POS;
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pllm = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLM) >> CMU_PLLCFGR_MPLLM_POS;
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if (0UL == (CM_CMU->PLLCFGR & CMU_PLLCFGR_PLLSRC)) { /* use external highspeed OSC as PLL source */
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u32PllSrcFreq = XTAL_VALUE;
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} else { /* use internal high RC as PLL source */
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u32PllSrcFreq = HRC_VALUE;
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}
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SystemCoreClock = u32PllSrcFreq / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL);
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break;
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default:
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break;
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}
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}
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#if defined (ROM_EXT_QSPI)
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/**
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* @brief Initialize the QSPI memory.
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* @param None
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* @retval None
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*/
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__WEAKDEF void SystemInit_QspiMem(void)
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{
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/* QSPI configure */
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CM_GPIO->PWPR = 0xA501U;
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/* High driver */
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CM_GPIO->PCRC7 = 0x0120U;
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CM_GPIO->PCRC6 = 0x0120U;
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CM_GPIO->PCRD8 = 0x0120U;
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CM_GPIO->PCRD9 = 0x0120U;
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CM_GPIO->PCRD10 = 0x0120U;
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CM_GPIO->PCRD11 = 0x0120U;
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/* Set function */
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CM_GPIO->PFSRC7 = 0x07U;
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CM_GPIO->PFSRC6 = 0x07U;
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CM_GPIO->PFSRD8 = 0x07U;
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CM_GPIO->PFSRD9 = 0x07U;
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CM_GPIO->PFSRD10 = 0x07U;
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CM_GPIO->PFSRD11 = 0x07U;
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/* qspi configure */
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CM_PWC->FCG1 &= ~0x00000008UL;
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CM_QSPI->CR = 0x0002000D;
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CM_QSPI->CSCR = 0x00000001;
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CM_QSPI->FCR = 0x00008332;
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}
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#endif /* ROM_EXT_QSPI */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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