初始版本

This commit is contained in:
2026-04-23 13:49:53 +08:00
parent c1d6ebd38c
commit ac718a463a
257 changed files with 265681 additions and 0 deletions
File diff suppressed because it is too large Load Diff
@@ -0,0 +1,66 @@
/**
*******************************************************************************
* @file hc32f4xx.h
* @brief This file contains the common part of the HC32 series.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4XX_H__
#define __HC32F4XX_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
/**
* @brief HC32F4xx Device Include
*/
#if defined(HC32F460)
#include "hc32f460.h"
#include "system_hc32f460.h"
#else
#error "Please select first the target HC32xxxx device used in your application (in hc32xxxx.h file)"
#endif
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4XX_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/
@@ -0,0 +1,140 @@
/**
*******************************************************************************
* @file system_hc32f460.h
* @brief This file contains all the functions prototypes of the HC32 System.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __SYSTEM_HC32F460_H__
#define __SYSTEM_HC32F460_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#include "hc32f4xx.h"
#include "hc32f4xx_conf.h"
/**
* @addtogroup CMSIS
* @{
*/
/**
* @addtogroup HC32F460_System
* @{
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('define')
******************************************************************************/
/**
* @addtogroup HC32F460_System_Global_Macros
* @{
*/
/**
* @addtogroup HC32F460_System_Clock_Source
* @{
*/
#if !defined (MRC_VALUE)
#define MRC_VALUE (8000000UL) /*!< Internal middle speed RC freq. */
#endif
#if !defined (LRC_VALUE)
#define LRC_VALUE (32768UL) /*!< Internal low speed RC freq. */
#endif
#if !defined (SWDTLRC_VALUE)
#define SWDTLRC_VALUE (10000UL) /*!< Internal SWDT low speed RC freq. */
#endif
#if !defined (XTAL_VALUE)
#define XTAL_VALUE (8000000UL) /*!< External high speed OSC freq. */
#endif
#if !defined (XTAL32_VALUE)
#define XTAL32_VALUE (32768UL) /*!< External low speed OSC freq. */
#endif
#if !defined (HCLK_VALUE)
#define HCLK_VALUE (SystemCoreClock >> ((CM_CMU->SCFGR & CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS))
#endif
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/**
* @addtogroup HC32F460_System_Exported_Variable
* @{
*/
extern uint32_t SystemCoreClock; /*!< System clock frequency (Core clock) */
extern uint32_t HRC_VALUE; /*!< HRC frequency */
/**
* @}
*/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup HC32F460_System_Global_Functions
* @{
*/
extern void SystemInit(void); /*!< Initialize the system */
extern void SystemCoreClockUpdate(void); /*!< Update SystemCoreClock variable */
#if defined (ROM_EXT_QSPI)
void SystemInit_QspiMem(void);
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_HC32F460_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/
@@ -0,0 +1,16 @@
FUNC void Setup (void) {
SP = _RDWORD(0x1FFE0000);
PC = _RDWORD(0x1FFE0004);
_WDWORD(0xE000ED08, 0x1FFE0000);
}
LOAD .\output\release\efm_chip_erase.axf INCREMENTAL
Setup();
g, main
@@ -0,0 +1,618 @@
;/**
; ******************************************************************************
; @file startup_hc32f460.s
; @brief Startup for MDK.
; verbatim
; Change Logs:
; Date Author Notes
; 2022-03-31 CDT First version
; endverbatim
; *****************************************************************************
; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
; *
; * This software component is licensed by XHSC under BSD 3-Clause license
; * (the "License"); You may not use this file except in compliance with the
; * License. You may obtain a copy of the License at:
; * opensource.org/licenses/BSD-3-Clause
; *
; ******************************************************************************
; */
; Stack Configuration
; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
Stack_Size EQU 0x00002000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; Heap Configuration
; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
Heap_Size EQU 0x00002000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; Peripheral Interrupts
DCD IRQ000_Handler
DCD IRQ001_Handler
DCD IRQ002_Handler
DCD IRQ003_Handler
DCD IRQ004_Handler
DCD IRQ005_Handler
DCD IRQ006_Handler
DCD IRQ007_Handler
DCD IRQ008_Handler
DCD IRQ009_Handler
DCD IRQ010_Handler
DCD IRQ011_Handler
DCD IRQ012_Handler
DCD IRQ013_Handler
DCD IRQ014_Handler
DCD IRQ015_Handler
DCD IRQ016_Handler
DCD IRQ017_Handler
DCD IRQ018_Handler
DCD IRQ019_Handler
DCD IRQ020_Handler
DCD IRQ021_Handler
DCD IRQ022_Handler
DCD IRQ023_Handler
DCD IRQ024_Handler
DCD IRQ025_Handler
DCD IRQ026_Handler
DCD IRQ027_Handler
DCD IRQ028_Handler
DCD IRQ029_Handler
DCD IRQ030_Handler
DCD IRQ031_Handler
DCD IRQ032_Handler
DCD IRQ033_Handler
DCD IRQ034_Handler
DCD IRQ035_Handler
DCD IRQ036_Handler
DCD IRQ037_Handler
DCD IRQ038_Handler
DCD IRQ039_Handler
DCD IRQ040_Handler
DCD IRQ041_Handler
DCD IRQ042_Handler
DCD IRQ043_Handler
DCD IRQ044_Handler
DCD IRQ045_Handler
DCD IRQ046_Handler
DCD IRQ047_Handler
DCD IRQ048_Handler
DCD IRQ049_Handler
DCD IRQ050_Handler
DCD IRQ051_Handler
DCD IRQ052_Handler
DCD IRQ053_Handler
DCD IRQ054_Handler
DCD IRQ055_Handler
DCD IRQ056_Handler
DCD IRQ057_Handler
DCD IRQ058_Handler
DCD IRQ059_Handler
DCD IRQ060_Handler
DCD IRQ061_Handler
DCD IRQ062_Handler
DCD IRQ063_Handler
DCD IRQ064_Handler
DCD IRQ065_Handler
DCD IRQ066_Handler
DCD IRQ067_Handler
DCD IRQ068_Handler
DCD IRQ069_Handler
DCD IRQ070_Handler
DCD IRQ071_Handler
DCD IRQ072_Handler
DCD IRQ073_Handler
DCD IRQ074_Handler
DCD IRQ075_Handler
DCD IRQ076_Handler
DCD IRQ077_Handler
DCD IRQ078_Handler
DCD IRQ079_Handler
DCD IRQ080_Handler
DCD IRQ081_Handler
DCD IRQ082_Handler
DCD IRQ083_Handler
DCD IRQ084_Handler
DCD IRQ085_Handler
DCD IRQ086_Handler
DCD IRQ087_Handler
DCD IRQ088_Handler
DCD IRQ089_Handler
DCD IRQ090_Handler
DCD IRQ091_Handler
DCD IRQ092_Handler
DCD IRQ093_Handler
DCD IRQ094_Handler
DCD IRQ095_Handler
DCD IRQ096_Handler
DCD IRQ097_Handler
DCD IRQ098_Handler
DCD IRQ099_Handler
DCD IRQ100_Handler
DCD IRQ101_Handler
DCD IRQ102_Handler
DCD IRQ103_Handler
DCD IRQ104_Handler
DCD IRQ105_Handler
DCD IRQ106_Handler
DCD IRQ107_Handler
DCD IRQ108_Handler
DCD IRQ109_Handler
DCD IRQ110_Handler
DCD IRQ111_Handler
DCD IRQ112_Handler
DCD IRQ113_Handler
DCD IRQ114_Handler
DCD IRQ115_Handler
DCD IRQ116_Handler
DCD IRQ117_Handler
DCD IRQ118_Handler
DCD IRQ119_Handler
DCD IRQ120_Handler
DCD IRQ121_Handler
DCD IRQ122_Handler
DCD IRQ123_Handler
DCD IRQ124_Handler
DCD IRQ125_Handler
DCD IRQ126_Handler
DCD IRQ127_Handler
DCD IRQ128_Handler
DCD IRQ129_Handler
DCD IRQ130_Handler
DCD IRQ131_Handler
DCD IRQ132_Handler
DCD IRQ133_Handler
DCD IRQ134_Handler
DCD IRQ135_Handler
DCD IRQ136_Handler
DCD IRQ137_Handler
DCD IRQ138_Handler
DCD IRQ139_Handler
DCD IRQ140_Handler
DCD IRQ141_Handler
DCD IRQ142_Handler
DCD IRQ143_Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
SET_SRAM3_WAIT
LDR R0, =0x40050804
MOV R1, #0x77
STR R1, [R0]
LDR R0, =0x4005080C
MOV R1, #0x77
STR R1, [R0]
LDR R0, =0x40050800
MOV R1, #0x1100
STR R1, [R0]
LDR R0, =0x40050804
MOV R1, #0x76
STR R1, [R0]
LDR R0, =0x4005080C
MOV R1, #0x76
STR R1, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT IRQ000_Handler [WEAK]
EXPORT IRQ001_Handler [WEAK]
EXPORT IRQ002_Handler [WEAK]
EXPORT IRQ003_Handler [WEAK]
EXPORT IRQ004_Handler [WEAK]
EXPORT IRQ005_Handler [WEAK]
EXPORT IRQ006_Handler [WEAK]
EXPORT IRQ007_Handler [WEAK]
EXPORT IRQ008_Handler [WEAK]
EXPORT IRQ009_Handler [WEAK]
EXPORT IRQ010_Handler [WEAK]
EXPORT IRQ011_Handler [WEAK]
EXPORT IRQ012_Handler [WEAK]
EXPORT IRQ013_Handler [WEAK]
EXPORT IRQ014_Handler [WEAK]
EXPORT IRQ015_Handler [WEAK]
EXPORT IRQ016_Handler [WEAK]
EXPORT IRQ017_Handler [WEAK]
EXPORT IRQ018_Handler [WEAK]
EXPORT IRQ019_Handler [WEAK]
EXPORT IRQ020_Handler [WEAK]
EXPORT IRQ021_Handler [WEAK]
EXPORT IRQ022_Handler [WEAK]
EXPORT IRQ023_Handler [WEAK]
EXPORT IRQ024_Handler [WEAK]
EXPORT IRQ025_Handler [WEAK]
EXPORT IRQ026_Handler [WEAK]
EXPORT IRQ027_Handler [WEAK]
EXPORT IRQ028_Handler [WEAK]
EXPORT IRQ029_Handler [WEAK]
EXPORT IRQ030_Handler [WEAK]
EXPORT IRQ031_Handler [WEAK]
EXPORT IRQ032_Handler [WEAK]
EXPORT IRQ033_Handler [WEAK]
EXPORT IRQ034_Handler [WEAK]
EXPORT IRQ035_Handler [WEAK]
EXPORT IRQ036_Handler [WEAK]
EXPORT IRQ037_Handler [WEAK]
EXPORT IRQ038_Handler [WEAK]
EXPORT IRQ039_Handler [WEAK]
EXPORT IRQ040_Handler [WEAK]
EXPORT IRQ041_Handler [WEAK]
EXPORT IRQ042_Handler [WEAK]
EXPORT IRQ043_Handler [WEAK]
EXPORT IRQ044_Handler [WEAK]
EXPORT IRQ045_Handler [WEAK]
EXPORT IRQ046_Handler [WEAK]
EXPORT IRQ047_Handler [WEAK]
EXPORT IRQ048_Handler [WEAK]
EXPORT IRQ049_Handler [WEAK]
EXPORT IRQ050_Handler [WEAK]
EXPORT IRQ051_Handler [WEAK]
EXPORT IRQ052_Handler [WEAK]
EXPORT IRQ053_Handler [WEAK]
EXPORT IRQ054_Handler [WEAK]
EXPORT IRQ055_Handler [WEAK]
EXPORT IRQ056_Handler [WEAK]
EXPORT IRQ057_Handler [WEAK]
EXPORT IRQ058_Handler [WEAK]
EXPORT IRQ059_Handler [WEAK]
EXPORT IRQ060_Handler [WEAK]
EXPORT IRQ061_Handler [WEAK]
EXPORT IRQ062_Handler [WEAK]
EXPORT IRQ063_Handler [WEAK]
EXPORT IRQ064_Handler [WEAK]
EXPORT IRQ065_Handler [WEAK]
EXPORT IRQ066_Handler [WEAK]
EXPORT IRQ067_Handler [WEAK]
EXPORT IRQ068_Handler [WEAK]
EXPORT IRQ069_Handler [WEAK]
EXPORT IRQ070_Handler [WEAK]
EXPORT IRQ071_Handler [WEAK]
EXPORT IRQ072_Handler [WEAK]
EXPORT IRQ073_Handler [WEAK]
EXPORT IRQ074_Handler [WEAK]
EXPORT IRQ075_Handler [WEAK]
EXPORT IRQ076_Handler [WEAK]
EXPORT IRQ077_Handler [WEAK]
EXPORT IRQ078_Handler [WEAK]
EXPORT IRQ079_Handler [WEAK]
EXPORT IRQ080_Handler [WEAK]
EXPORT IRQ081_Handler [WEAK]
EXPORT IRQ082_Handler [WEAK]
EXPORT IRQ083_Handler [WEAK]
EXPORT IRQ084_Handler [WEAK]
EXPORT IRQ085_Handler [WEAK]
EXPORT IRQ086_Handler [WEAK]
EXPORT IRQ087_Handler [WEAK]
EXPORT IRQ088_Handler [WEAK]
EXPORT IRQ089_Handler [WEAK]
EXPORT IRQ090_Handler [WEAK]
EXPORT IRQ091_Handler [WEAK]
EXPORT IRQ092_Handler [WEAK]
EXPORT IRQ093_Handler [WEAK]
EXPORT IRQ094_Handler [WEAK]
EXPORT IRQ095_Handler [WEAK]
EXPORT IRQ096_Handler [WEAK]
EXPORT IRQ097_Handler [WEAK]
EXPORT IRQ098_Handler [WEAK]
EXPORT IRQ099_Handler [WEAK]
EXPORT IRQ100_Handler [WEAK]
EXPORT IRQ101_Handler [WEAK]
EXPORT IRQ102_Handler [WEAK]
EXPORT IRQ103_Handler [WEAK]
EXPORT IRQ104_Handler [WEAK]
EXPORT IRQ105_Handler [WEAK]
EXPORT IRQ106_Handler [WEAK]
EXPORT IRQ107_Handler [WEAK]
EXPORT IRQ108_Handler [WEAK]
EXPORT IRQ109_Handler [WEAK]
EXPORT IRQ110_Handler [WEAK]
EXPORT IRQ111_Handler [WEAK]
EXPORT IRQ112_Handler [WEAK]
EXPORT IRQ113_Handler [WEAK]
EXPORT IRQ114_Handler [WEAK]
EXPORT IRQ115_Handler [WEAK]
EXPORT IRQ116_Handler [WEAK]
EXPORT IRQ117_Handler [WEAK]
EXPORT IRQ118_Handler [WEAK]
EXPORT IRQ119_Handler [WEAK]
EXPORT IRQ120_Handler [WEAK]
EXPORT IRQ121_Handler [WEAK]
EXPORT IRQ122_Handler [WEAK]
EXPORT IRQ123_Handler [WEAK]
EXPORT IRQ124_Handler [WEAK]
EXPORT IRQ125_Handler [WEAK]
EXPORT IRQ126_Handler [WEAK]
EXPORT IRQ127_Handler [WEAK]
EXPORT IRQ128_Handler [WEAK]
EXPORT IRQ129_Handler [WEAK]
EXPORT IRQ130_Handler [WEAK]
EXPORT IRQ131_Handler [WEAK]
EXPORT IRQ132_Handler [WEAK]
EXPORT IRQ133_Handler [WEAK]
EXPORT IRQ134_Handler [WEAK]
EXPORT IRQ135_Handler [WEAK]
EXPORT IRQ136_Handler [WEAK]
EXPORT IRQ137_Handler [WEAK]
EXPORT IRQ138_Handler [WEAK]
EXPORT IRQ139_Handler [WEAK]
EXPORT IRQ140_Handler [WEAK]
EXPORT IRQ141_Handler [WEAK]
EXPORT IRQ142_Handler [WEAK]
EXPORT IRQ143_Handler [WEAK]
IRQ000_Handler
IRQ001_Handler
IRQ002_Handler
IRQ003_Handler
IRQ004_Handler
IRQ005_Handler
IRQ006_Handler
IRQ007_Handler
IRQ008_Handler
IRQ009_Handler
IRQ010_Handler
IRQ011_Handler
IRQ012_Handler
IRQ013_Handler
IRQ014_Handler
IRQ015_Handler
IRQ016_Handler
IRQ017_Handler
IRQ018_Handler
IRQ019_Handler
IRQ020_Handler
IRQ021_Handler
IRQ022_Handler
IRQ023_Handler
IRQ024_Handler
IRQ025_Handler
IRQ026_Handler
IRQ027_Handler
IRQ028_Handler
IRQ029_Handler
IRQ030_Handler
IRQ031_Handler
IRQ032_Handler
IRQ033_Handler
IRQ034_Handler
IRQ035_Handler
IRQ036_Handler
IRQ037_Handler
IRQ038_Handler
IRQ039_Handler
IRQ040_Handler
IRQ041_Handler
IRQ042_Handler
IRQ043_Handler
IRQ044_Handler
IRQ045_Handler
IRQ046_Handler
IRQ047_Handler
IRQ048_Handler
IRQ049_Handler
IRQ050_Handler
IRQ051_Handler
IRQ052_Handler
IRQ053_Handler
IRQ054_Handler
IRQ055_Handler
IRQ056_Handler
IRQ057_Handler
IRQ058_Handler
IRQ059_Handler
IRQ060_Handler
IRQ061_Handler
IRQ062_Handler
IRQ063_Handler
IRQ064_Handler
IRQ065_Handler
IRQ066_Handler
IRQ067_Handler
IRQ068_Handler
IRQ069_Handler
IRQ070_Handler
IRQ071_Handler
IRQ072_Handler
IRQ073_Handler
IRQ074_Handler
IRQ075_Handler
IRQ076_Handler
IRQ077_Handler
IRQ078_Handler
IRQ079_Handler
IRQ080_Handler
IRQ081_Handler
IRQ082_Handler
IRQ083_Handler
IRQ084_Handler
IRQ085_Handler
IRQ086_Handler
IRQ087_Handler
IRQ088_Handler
IRQ089_Handler
IRQ090_Handler
IRQ091_Handler
IRQ092_Handler
IRQ093_Handler
IRQ094_Handler
IRQ095_Handler
IRQ096_Handler
IRQ097_Handler
IRQ098_Handler
IRQ099_Handler
IRQ100_Handler
IRQ101_Handler
IRQ102_Handler
IRQ103_Handler
IRQ104_Handler
IRQ105_Handler
IRQ106_Handler
IRQ107_Handler
IRQ108_Handler
IRQ109_Handler
IRQ110_Handler
IRQ111_Handler
IRQ112_Handler
IRQ113_Handler
IRQ114_Handler
IRQ115_Handler
IRQ116_Handler
IRQ117_Handler
IRQ118_Handler
IRQ119_Handler
IRQ120_Handler
IRQ121_Handler
IRQ122_Handler
IRQ123_Handler
IRQ124_Handler
IRQ125_Handler
IRQ126_Handler
IRQ127_Handler
IRQ128_Handler
IRQ129_Handler
IRQ130_Handler
IRQ131_Handler
IRQ132_Handler
IRQ133_Handler
IRQ134_Handler
IRQ135_Handler
IRQ136_Handler
IRQ137_Handler
IRQ138_Handler
IRQ139_Handler
IRQ140_Handler
IRQ141_Handler
IRQ142_Handler
IRQ143_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
@@ -0,0 +1,208 @@
/******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*/
/*****************************************************************************/
/* File HC32F460xC.ld */
/* Abstract Linker script for HC32F460 Device with */
/* 256KByte FLASH, 192KByte RAM */
/* Version V1.0 */
/* Date 2022-03-31 */
/*****************************************************************************/
/* Custom defines, according to section 7.7 of the user manual.
Take OTP sector 0 for example. */
__OTP_DATA_START = 0x03000C00;
__OTP_DATA_SIZE = 64;
__OTP_LOCK_START = 0x03000FC0;
__OTP_LOCK_SIZE = 4;
/* Use contiguous memory regions for simple. */
MEMORY
{
FLASH (rx): ORIGIN = 0x00000000, LENGTH = 256K
OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE
OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE
RAM (rwx): ORIGIN = 0x1FFF8000, LENGTH = 188K
RET_RAM (rwx): ORIGIN = 0x200F0000, LENGTH = 4K
}
ENTRY(Reset_Handler)
SECTIONS
{
.vectors :
{
. = ALIGN(4);
KEEP(*(.vectors))
. = ALIGN(4);
} >FLASH
.icg_sec 0x00000400 :
{
KEEP(*(.icg_sec))
} >FLASH
.text :
{
. = ALIGN(4);
*(.text)
*(.text*)
*(.glue_7)
*(.glue_7t)
*(.eh_frame)
KEEP(*(.init))
KEEP(*(.fini))
. = ALIGN(4);
} >FLASH
.rodata :
{
. = ALIGN(4);
*(.rodata)
*(.rodata*)
. = ALIGN(4);
} >FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} >FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} >FLASH
__exidx_end = .;
.preinit_array :
{
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
} >FLASH
.init_array :
{
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
} >FLASH
.fini_array :
{
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4);
} >FLASH
__etext = ALIGN(4);
.otp_data_sec :
{
KEEP(*(.otp_data_sec))
} >OTP_DATA
.otp_lock_sec :
{
KEEP(*(.otp_lock_sec))
} >OTP_LOCK
.data : AT (__etext)
{
. = ALIGN(4);
__data_start__ = .;
*(vtable)
*(.data)
*(.data*)
. = ALIGN(4);
*(.ramfunc)
*(.ramfunc*)
. = ALIGN(4);
__data_end__ = .;
} >RAM
__etext_ret_ram = __etext + ALIGN (SIZEOF(.data), 4);
.ret_ram_data : AT (__etext_ret_ram)
{
. = ALIGN(4);
__data_start_ret_ram__ = .;
*(.ret_ram_data)
*(.ret_ram_data*)
. = ALIGN(4);
__data_end_ret_ram__ = .;
} >RET_RAM
.bss :
{
. = ALIGN(4);
_sbss = .;
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
__bss_end__ = _ebss;
} >RAM
.ret_ram_bss :
{
. = ALIGN(4);
__bss_start_ret_ram__ = .;
*(.ret_ram_bss)
*(.ret_ram_bss*)
. = ALIGN(4);
__bss_end_ret_ram__ = .;
} >RET_RAM
.heap_stack (COPY) :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
PROVIDE(_end = .);
*(.heap*)
. = ALIGN(8);
__HeapLimit = .;
__StackLimit = .;
*(.stack*)
. = ALIGN(8);
__StackTop = .;
} >RAM
/DISCARD/ :
{
libc.a (*)
libm.a (*)
libgcc.a (*)
}
.ARM.attributes 0 : { *(.ARM.attributes) }
PROVIDE(_stack = __StackTop);
PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase);
PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit);
__RamEnd = ORIGIN(RAM) + LENGTH(RAM);
ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack")
}
@@ -0,0 +1,208 @@
/******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*/
/*****************************************************************************/
/* File HC32F460xE.ld */
/* Abstract Linker script for HC32F460 Device with */
/* 512KByte FLASH, 192KByte RAM */
/* Version V1.0 */
/* Date 2022-03-31 */
/*****************************************************************************/
/* Custom defines, according to section 7.7 of the user manual.
Take OTP sector 0 for example. */
__OTP_DATA_START = 0x03000C00;
__OTP_DATA_SIZE = 64;
__OTP_LOCK_START = 0x03000FC0;
__OTP_LOCK_SIZE = 4;
/* Use contiguous memory regions for simple. */
MEMORY
{
FLASH (rx): ORIGIN = 0x00000000, LENGTH = 512K
OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE
OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE
RAM (rwx): ORIGIN = 0x1FFF8000, LENGTH = 188K
RET_RAM (rwx): ORIGIN = 0x200F0000, LENGTH = 4K
}
ENTRY(Reset_Handler)
SECTIONS
{
.vectors :
{
. = ALIGN(4);
KEEP(*(.vectors))
. = ALIGN(4);
} >FLASH
.icg_sec 0x00000400 :
{
KEEP(*(.icg_sec))
} >FLASH
.text :
{
. = ALIGN(4);
*(.text)
*(.text*)
*(.glue_7)
*(.glue_7t)
*(.eh_frame)
KEEP(*(.init))
KEEP(*(.fini))
. = ALIGN(4);
} >FLASH
.rodata :
{
. = ALIGN(4);
*(.rodata)
*(.rodata*)
. = ALIGN(4);
} >FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} >FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} >FLASH
__exidx_end = .;
.preinit_array :
{
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
} >FLASH
.init_array :
{
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
} >FLASH
.fini_array :
{
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4);
} >FLASH
__etext = ALIGN(4);
.otp_data_sec :
{
KEEP(*(.otp_data_sec))
} >OTP_DATA
.otp_lock_sec :
{
KEEP(*(.otp_lock_sec))
} >OTP_LOCK
.data : AT (__etext)
{
. = ALIGN(4);
__data_start__ = .;
*(vtable)
*(.data)
*(.data*)
. = ALIGN(4);
*(.ramfunc)
*(.ramfunc*)
. = ALIGN(4);
__data_end__ = .;
} >RAM
__etext_ret_ram = __etext + ALIGN (SIZEOF(.data), 4);
.ret_ram_data : AT (__etext_ret_ram)
{
. = ALIGN(4);
__data_start_ret_ram__ = .;
*(.ret_ram_data)
*(.ret_ram_data*)
. = ALIGN(4);
__data_end_ret_ram__ = .;
} >RET_RAM
.bss :
{
. = ALIGN(4);
_sbss = .;
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
__bss_end__ = _ebss;
} >RAM
.ret_ram_bss :
{
. = ALIGN(4);
__bss_start_ret_ram__ = .;
*(.ret_ram_bss)
*(.ret_ram_bss*)
. = ALIGN(4);
__bss_end_ret_ram__ = .;
} >RET_RAM
.heap_stack (COPY) :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
PROVIDE(_end = .);
*(.heap*)
. = ALIGN(8);
__HeapLimit = .;
__StackLimit = .;
*(.stack*)
. = ALIGN(8);
__StackTop = .;
} >RAM
/DISCARD/ :
{
libc.a (*)
libm.a (*)
libgcc.a (*)
}
.ARM.attributes 0 : { *(.ARM.attributes) }
PROVIDE(_stack = __StackTop);
PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase);
PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit);
__RamEnd = ORIGIN(RAM) + LENGTH(RAM);
ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack")
}
@@ -0,0 +1,538 @@
;/**
; ******************************************************************************
; @file startup_hc32f460.S
; @brief Startup for GCC.
; verbatim
; Change Logs:
; Date Author Notes
; 2022-03-31 CDT First version
; endverbatim
; *****************************************************************************
; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
; *
; * This software component is licensed by XHSC under BSD 3-Clause license
; * (the "License"); You may not use this file except in compliance with the
; * License. You may obtain a copy of the License at:
; * opensource.org/licenses/BSD-3-Clause
; *
; ******************************************************************************
; */
/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
.syntax unified
.arch armv7e-m
.cpu cortex-m4
.fpu softvfp
.thumb
/*
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Stack_Size, 0x00002000
.section .stack
.align 3
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
/*
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Heap_Size, 0x00002000
.if Heap_Size != 0 /* Heap is provided */
.section .heap
.align 3
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.space Heap_Size
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.endif
/*
;<h> Interrupt vector table start.
*/
.section .vectors, "a", %progbits
.align 2
.type __Vectors, %object
.globl __Vectors
.globl __Vectors_End
.globl __Vectors_Size
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* -14 NMI Handler */
.long HardFault_Handler /* -13 Hard Fault Handler */
.long MemManage_Handler /* -12 MPU Fault Handler */
.long BusFault_Handler /* -11 Bus Fault Handler */
.long UsageFault_Handler /* -10 Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* -5 SVCall Handler */
.long DebugMon_Handler /* -4 Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* -2 PendSV Handler */
.long SysTick_Handler /* -1 SysTick Handler */
/* Interrupts */
.long IRQ000_Handler
.long IRQ001_Handler
.long IRQ002_Handler
.long IRQ003_Handler
.long IRQ004_Handler
.long IRQ005_Handler
.long IRQ006_Handler
.long IRQ007_Handler
.long IRQ008_Handler
.long IRQ009_Handler
.long IRQ010_Handler
.long IRQ011_Handler
.long IRQ012_Handler
.long IRQ013_Handler
.long IRQ014_Handler
.long IRQ015_Handler
.long IRQ016_Handler
.long IRQ017_Handler
.long IRQ018_Handler
.long IRQ019_Handler
.long IRQ020_Handler
.long IRQ021_Handler
.long IRQ022_Handler
.long IRQ023_Handler
.long IRQ024_Handler
.long IRQ025_Handler
.long IRQ026_Handler
.long IRQ027_Handler
.long IRQ028_Handler
.long IRQ029_Handler
.long IRQ030_Handler
.long IRQ031_Handler
.long IRQ032_Handler
.long IRQ033_Handler
.long IRQ034_Handler
.long IRQ035_Handler
.long IRQ036_Handler
.long IRQ037_Handler
.long IRQ038_Handler
.long IRQ039_Handler
.long IRQ040_Handler
.long IRQ041_Handler
.long IRQ042_Handler
.long IRQ043_Handler
.long IRQ044_Handler
.long IRQ045_Handler
.long IRQ046_Handler
.long IRQ047_Handler
.long IRQ048_Handler
.long IRQ049_Handler
.long IRQ050_Handler
.long IRQ051_Handler
.long IRQ052_Handler
.long IRQ053_Handler
.long IRQ054_Handler
.long IRQ055_Handler
.long IRQ056_Handler
.long IRQ057_Handler
.long IRQ058_Handler
.long IRQ059_Handler
.long IRQ060_Handler
.long IRQ061_Handler
.long IRQ062_Handler
.long IRQ063_Handler
.long IRQ064_Handler
.long IRQ065_Handler
.long IRQ066_Handler
.long IRQ067_Handler
.long IRQ068_Handler
.long IRQ069_Handler
.long IRQ070_Handler
.long IRQ071_Handler
.long IRQ072_Handler
.long IRQ073_Handler
.long IRQ074_Handler
.long IRQ075_Handler
.long IRQ076_Handler
.long IRQ077_Handler
.long IRQ078_Handler
.long IRQ079_Handler
.long IRQ080_Handler
.long IRQ081_Handler
.long IRQ082_Handler
.long IRQ083_Handler
.long IRQ084_Handler
.long IRQ085_Handler
.long IRQ086_Handler
.long IRQ087_Handler
.long IRQ088_Handler
.long IRQ089_Handler
.long IRQ090_Handler
.long IRQ091_Handler
.long IRQ092_Handler
.long IRQ093_Handler
.long IRQ094_Handler
.long IRQ095_Handler
.long IRQ096_Handler
.long IRQ097_Handler
.long IRQ098_Handler
.long IRQ099_Handler
.long IRQ100_Handler
.long IRQ101_Handler
.long IRQ102_Handler
.long IRQ103_Handler
.long IRQ104_Handler
.long IRQ105_Handler
.long IRQ106_Handler
.long IRQ107_Handler
.long IRQ108_Handler
.long IRQ109_Handler
.long IRQ110_Handler
.long IRQ111_Handler
.long IRQ112_Handler
.long IRQ113_Handler
.long IRQ114_Handler
.long IRQ115_Handler
.long IRQ116_Handler
.long IRQ117_Handler
.long IRQ118_Handler
.long IRQ119_Handler
.long IRQ120_Handler
.long IRQ121_Handler
.long IRQ122_Handler
.long IRQ123_Handler
.long IRQ124_Handler
.long IRQ125_Handler
.long IRQ126_Handler
.long IRQ127_Handler
.long IRQ128_Handler
.long IRQ129_Handler
.long IRQ130_Handler
.long IRQ131_Handler
.long IRQ132_Handler
.long IRQ133_Handler
.long IRQ134_Handler
.long IRQ135_Handler
.long IRQ136_Handler
.long IRQ137_Handler
.long IRQ138_Handler
.long IRQ139_Handler
.long IRQ140_Handler
.long IRQ141_Handler
.long IRQ142_Handler
.long IRQ143_Handler
__Vectors_End:
.equ __Vectors_Size, __Vectors_End - __Vectors
.size __Vectors, . - __Vectors
/*
;<h> Interrupt vector table end.
*/
/*
;<h> Reset handler start.
*/
.section .text.Reset_Handler
.align 2
.weak Reset_Handler
.type Reset_Handler, %function
.globl Reset_Handler
Reset_Handler:
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
/* Copy data from read only memory to RAM. */
CopyData:
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
CopyLoop:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt CopyLoop
CopyData1:
ldr r1, =__etext_ret_ram
ldr r2, =__data_start_ret_ram__
ldr r3, =__data_end_ret_ram__
CopyLoop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt CopyLoop1
/* This part of work usually is done in C library startup code.
* Otherwise, define this macro to enable it in this startup.
*
* There are two schemes too.
* One can clear multiple BSS sections. Another can only clear one section.
* The former is more size expensive than the latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
/* Clear BSS section. */
ClearBss:
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
ClearLoop:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt ClearLoop
ClearBss1:
ldr r1, =__bss_start_ret_ram__
ldr r2, =__bss_end_ret_ram__
movs r0, 0
ClearLoop1:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt ClearLoop1
SetSRAM3Wait:
ldr r0, =0x40050804
mov r1, #0x77
str r1, [r0]
ldr r0, =0x4005080C
mov r1, #0x77
str r1, [r0]
ldr r0, =0x40050800
mov r1, #0x1100
str r1, [r0]
ldr r0, =0x40050804
mov r1, #0x76
str r1, [r0]
ldr r0, =0x4005080C
mov r1, #0x76
str r1, [r0]
/* Call the clock system initialization function. */
bl SystemInit
/* Call the application's entry point. */
bl main
bx lr
.size Reset_Handler, . - Reset_Handler
/*
;<h> Reset handler end.
*/
/*
;<h> Default handler start.
*/
.section .text.Default_Handler, "ax", %progbits
.align 2
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
/*
;<h> Default handler end.
*/
/* Macro to define default exception/interrupt handlers.
* Default handler are weak symbols with an endless loop.
* They can be overwritten by real handlers.
*/
.macro Set_Default_Handler Handler_Name
.weak \Handler_Name
.set \Handler_Name, Default_Handler
.endm
/* Default exception/interrupt handler */
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler IRQ000_Handler
Set_Default_Handler IRQ001_Handler
Set_Default_Handler IRQ002_Handler
Set_Default_Handler IRQ003_Handler
Set_Default_Handler IRQ004_Handler
Set_Default_Handler IRQ005_Handler
Set_Default_Handler IRQ006_Handler
Set_Default_Handler IRQ007_Handler
Set_Default_Handler IRQ008_Handler
Set_Default_Handler IRQ009_Handler
Set_Default_Handler IRQ010_Handler
Set_Default_Handler IRQ011_Handler
Set_Default_Handler IRQ012_Handler
Set_Default_Handler IRQ013_Handler
Set_Default_Handler IRQ014_Handler
Set_Default_Handler IRQ015_Handler
Set_Default_Handler IRQ016_Handler
Set_Default_Handler IRQ017_Handler
Set_Default_Handler IRQ018_Handler
Set_Default_Handler IRQ019_Handler
Set_Default_Handler IRQ020_Handler
Set_Default_Handler IRQ021_Handler
Set_Default_Handler IRQ022_Handler
Set_Default_Handler IRQ023_Handler
Set_Default_Handler IRQ024_Handler
Set_Default_Handler IRQ025_Handler
Set_Default_Handler IRQ026_Handler
Set_Default_Handler IRQ027_Handler
Set_Default_Handler IRQ028_Handler
Set_Default_Handler IRQ029_Handler
Set_Default_Handler IRQ030_Handler
Set_Default_Handler IRQ031_Handler
Set_Default_Handler IRQ032_Handler
Set_Default_Handler IRQ033_Handler
Set_Default_Handler IRQ034_Handler
Set_Default_Handler IRQ035_Handler
Set_Default_Handler IRQ036_Handler
Set_Default_Handler IRQ037_Handler
Set_Default_Handler IRQ038_Handler
Set_Default_Handler IRQ039_Handler
Set_Default_Handler IRQ040_Handler
Set_Default_Handler IRQ041_Handler
Set_Default_Handler IRQ042_Handler
Set_Default_Handler IRQ043_Handler
Set_Default_Handler IRQ044_Handler
Set_Default_Handler IRQ045_Handler
Set_Default_Handler IRQ046_Handler
Set_Default_Handler IRQ047_Handler
Set_Default_Handler IRQ048_Handler
Set_Default_Handler IRQ049_Handler
Set_Default_Handler IRQ050_Handler
Set_Default_Handler IRQ051_Handler
Set_Default_Handler IRQ052_Handler
Set_Default_Handler IRQ053_Handler
Set_Default_Handler IRQ054_Handler
Set_Default_Handler IRQ055_Handler
Set_Default_Handler IRQ056_Handler
Set_Default_Handler IRQ057_Handler
Set_Default_Handler IRQ058_Handler
Set_Default_Handler IRQ059_Handler
Set_Default_Handler IRQ060_Handler
Set_Default_Handler IRQ061_Handler
Set_Default_Handler IRQ062_Handler
Set_Default_Handler IRQ063_Handler
Set_Default_Handler IRQ064_Handler
Set_Default_Handler IRQ065_Handler
Set_Default_Handler IRQ066_Handler
Set_Default_Handler IRQ067_Handler
Set_Default_Handler IRQ068_Handler
Set_Default_Handler IRQ069_Handler
Set_Default_Handler IRQ070_Handler
Set_Default_Handler IRQ071_Handler
Set_Default_Handler IRQ072_Handler
Set_Default_Handler IRQ073_Handler
Set_Default_Handler IRQ074_Handler
Set_Default_Handler IRQ075_Handler
Set_Default_Handler IRQ076_Handler
Set_Default_Handler IRQ077_Handler
Set_Default_Handler IRQ078_Handler
Set_Default_Handler IRQ079_Handler
Set_Default_Handler IRQ080_Handler
Set_Default_Handler IRQ081_Handler
Set_Default_Handler IRQ082_Handler
Set_Default_Handler IRQ083_Handler
Set_Default_Handler IRQ084_Handler
Set_Default_Handler IRQ085_Handler
Set_Default_Handler IRQ086_Handler
Set_Default_Handler IRQ087_Handler
Set_Default_Handler IRQ088_Handler
Set_Default_Handler IRQ089_Handler
Set_Default_Handler IRQ090_Handler
Set_Default_Handler IRQ091_Handler
Set_Default_Handler IRQ092_Handler
Set_Default_Handler IRQ093_Handler
Set_Default_Handler IRQ094_Handler
Set_Default_Handler IRQ095_Handler
Set_Default_Handler IRQ096_Handler
Set_Default_Handler IRQ097_Handler
Set_Default_Handler IRQ098_Handler
Set_Default_Handler IRQ099_Handler
Set_Default_Handler IRQ100_Handler
Set_Default_Handler IRQ101_Handler
Set_Default_Handler IRQ102_Handler
Set_Default_Handler IRQ103_Handler
Set_Default_Handler IRQ104_Handler
Set_Default_Handler IRQ105_Handler
Set_Default_Handler IRQ106_Handler
Set_Default_Handler IRQ107_Handler
Set_Default_Handler IRQ108_Handler
Set_Default_Handler IRQ109_Handler
Set_Default_Handler IRQ110_Handler
Set_Default_Handler IRQ111_Handler
Set_Default_Handler IRQ112_Handler
Set_Default_Handler IRQ113_Handler
Set_Default_Handler IRQ114_Handler
Set_Default_Handler IRQ115_Handler
Set_Default_Handler IRQ116_Handler
Set_Default_Handler IRQ117_Handler
Set_Default_Handler IRQ118_Handler
Set_Default_Handler IRQ119_Handler
Set_Default_Handler IRQ120_Handler
Set_Default_Handler IRQ121_Handler
Set_Default_Handler IRQ122_Handler
Set_Default_Handler IRQ123_Handler
Set_Default_Handler IRQ124_Handler
Set_Default_Handler IRQ125_Handler
Set_Default_Handler IRQ126_Handler
Set_Default_Handler IRQ127_Handler
Set_Default_Handler IRQ128_Handler
Set_Default_Handler IRQ129_Handler
Set_Default_Handler IRQ130_Handler
Set_Default_Handler IRQ131_Handler
Set_Default_Handler IRQ132_Handler
Set_Default_Handler IRQ133_Handler
Set_Default_Handler IRQ134_Handler
Set_Default_Handler IRQ135_Handler
Set_Default_Handler IRQ136_Handler
Set_Default_Handler IRQ137_Handler
Set_Default_Handler IRQ138_Handler
Set_Default_Handler IRQ139_Handler
Set_Default_Handler IRQ140_Handler
Set_Default_Handler IRQ141_Handler
Set_Default_Handler IRQ142_Handler
Set_Default_Handler IRQ143_Handler
.end
File diff suppressed because it is too large Load Diff
@@ -0,0 +1,16 @@
setup()
{
;
}
execUserPreload()
{
__message "----- Prepare hardware for Flashloader -----\n";
setup();
}
execUserFlashInit() // Called by debugger before loading flash loader in RAM.
{
__message "----- Prepare hardware for Flashloader -----\n";
setup();
}
@@ -0,0 +1,16 @@
setup()
{
;
}
execUserPreload()
{
__message "----- Prepare hardware for Flashloader -----\n";
setup();
}
execUserFlashInit() // Called by debugger before loading flash loader in RAM.
{
__message "----- Prepare hardware for Flashloader -----\n";
setup();
}
@@ -0,0 +1,56 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x1FFF8000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x1FFF8000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x20000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x20020000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x20026FFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
define symbol __ICFEDIT_region_IRAM3_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM4_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM4_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM5_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM5_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x100;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x100;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
@@ -0,0 +1,50 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x0003FFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x03000C00;
define symbol __ICFEDIT_region_IROM2_end__ = 0x03000FFB;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFF8000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x20026FFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
@@ -0,0 +1,50 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x0007FFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x03000C00;
define symbol __ICFEDIT_region_IROM2_end__ = 0x03000FFB;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFF8000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x20026FFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
@@ -0,0 +1,995 @@
;/**
; ******************************************************************************
; @file startup_hc32f460.s
; @brief Startup for IAR.
; verbatim
; Change Logs:
; Date Author Notes
; 2022-03-31 CDT First version
; endverbatim
; *****************************************************************************
; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
; *
; * This software component is licensed by XHSC under BSD 3-Clause license
; * (the "License"); You may not use this file except in compliance with the
; * License. You may obtain a copy of the License at:
; * opensource.org/licenses/BSD-3-Clause
; *
; ******************************************************************************
; */
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK) ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; Peripheral Interrupts
DCD IRQ000_Handler
DCD IRQ001_Handler
DCD IRQ002_Handler
DCD IRQ003_Handler
DCD IRQ004_Handler
DCD IRQ005_Handler
DCD IRQ006_Handler
DCD IRQ007_Handler
DCD IRQ008_Handler
DCD IRQ009_Handler
DCD IRQ010_Handler
DCD IRQ011_Handler
DCD IRQ012_Handler
DCD IRQ013_Handler
DCD IRQ014_Handler
DCD IRQ015_Handler
DCD IRQ016_Handler
DCD IRQ017_Handler
DCD IRQ018_Handler
DCD IRQ019_Handler
DCD IRQ020_Handler
DCD IRQ021_Handler
DCD IRQ022_Handler
DCD IRQ023_Handler
DCD IRQ024_Handler
DCD IRQ025_Handler
DCD IRQ026_Handler
DCD IRQ027_Handler
DCD IRQ028_Handler
DCD IRQ029_Handler
DCD IRQ030_Handler
DCD IRQ031_Handler
DCD IRQ032_Handler
DCD IRQ033_Handler
DCD IRQ034_Handler
DCD IRQ035_Handler
DCD IRQ036_Handler
DCD IRQ037_Handler
DCD IRQ038_Handler
DCD IRQ039_Handler
DCD IRQ040_Handler
DCD IRQ041_Handler
DCD IRQ042_Handler
DCD IRQ043_Handler
DCD IRQ044_Handler
DCD IRQ045_Handler
DCD IRQ046_Handler
DCD IRQ047_Handler
DCD IRQ048_Handler
DCD IRQ049_Handler
DCD IRQ050_Handler
DCD IRQ051_Handler
DCD IRQ052_Handler
DCD IRQ053_Handler
DCD IRQ054_Handler
DCD IRQ055_Handler
DCD IRQ056_Handler
DCD IRQ057_Handler
DCD IRQ058_Handler
DCD IRQ059_Handler
DCD IRQ060_Handler
DCD IRQ061_Handler
DCD IRQ062_Handler
DCD IRQ063_Handler
DCD IRQ064_Handler
DCD IRQ065_Handler
DCD IRQ066_Handler
DCD IRQ067_Handler
DCD IRQ068_Handler
DCD IRQ069_Handler
DCD IRQ070_Handler
DCD IRQ071_Handler
DCD IRQ072_Handler
DCD IRQ073_Handler
DCD IRQ074_Handler
DCD IRQ075_Handler
DCD IRQ076_Handler
DCD IRQ077_Handler
DCD IRQ078_Handler
DCD IRQ079_Handler
DCD IRQ080_Handler
DCD IRQ081_Handler
DCD IRQ082_Handler
DCD IRQ083_Handler
DCD IRQ084_Handler
DCD IRQ085_Handler
DCD IRQ086_Handler
DCD IRQ087_Handler
DCD IRQ088_Handler
DCD IRQ089_Handler
DCD IRQ090_Handler
DCD IRQ091_Handler
DCD IRQ092_Handler
DCD IRQ093_Handler
DCD IRQ094_Handler
DCD IRQ095_Handler
DCD IRQ096_Handler
DCD IRQ097_Handler
DCD IRQ098_Handler
DCD IRQ099_Handler
DCD IRQ100_Handler
DCD IRQ101_Handler
DCD IRQ102_Handler
DCD IRQ103_Handler
DCD IRQ104_Handler
DCD IRQ105_Handler
DCD IRQ106_Handler
DCD IRQ107_Handler
DCD IRQ108_Handler
DCD IRQ109_Handler
DCD IRQ110_Handler
DCD IRQ111_Handler
DCD IRQ112_Handler
DCD IRQ113_Handler
DCD IRQ114_Handler
DCD IRQ115_Handler
DCD IRQ116_Handler
DCD IRQ117_Handler
DCD IRQ118_Handler
DCD IRQ119_Handler
DCD IRQ120_Handler
DCD IRQ121_Handler
DCD IRQ122_Handler
DCD IRQ123_Handler
DCD IRQ124_Handler
DCD IRQ125_Handler
DCD IRQ126_Handler
DCD IRQ127_Handler
DCD IRQ128_Handler
DCD IRQ129_Handler
DCD IRQ130_Handler
DCD IRQ131_Handler
DCD IRQ132_Handler
DCD IRQ133_Handler
DCD IRQ134_Handler
DCD IRQ135_Handler
DCD IRQ136_Handler
DCD IRQ137_Handler
DCD IRQ138_Handler
DCD IRQ139_Handler
DCD IRQ140_Handler
DCD IRQ141_Handler
DCD IRQ142_Handler
DCD IRQ143_Handler
THUMB
; Dummy Exception Handlers (infinite loops which can be modified)
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
;SetSRAM3Wait
LDR R0, =0x40050804
MOV R1, #0x77
STR R1, [R0]
LDR R0, =0x4005080C
MOV R1, #0x77
STR R1, [R0]
LDR R0, =0x40050800
MOV R1, #0x1100
STR R1, [R0]
LDR R0, =0x40050804
MOV R1, #0x76
STR R1, [R0]
LDR R0, =0x4005080C
MOV R1, #0x76
STR R1, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK IRQ000_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ000_Handler
B IRQ000_Handler
PUBWEAK IRQ001_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ001_Handler
B IRQ001_Handler
PUBWEAK IRQ002_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ002_Handler
B IRQ002_Handler
PUBWEAK IRQ003_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ003_Handler
B IRQ003_Handler
PUBWEAK IRQ004_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ004_Handler
B IRQ004_Handler
PUBWEAK IRQ005_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ005_Handler
B IRQ005_Handler
PUBWEAK IRQ006_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ006_Handler
B IRQ006_Handler
PUBWEAK IRQ007_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ007_Handler
B IRQ007_Handler
PUBWEAK IRQ008_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ008_Handler
B IRQ008_Handler
PUBWEAK IRQ009_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ009_Handler
B IRQ009_Handler
PUBWEAK IRQ010_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ010_Handler
B IRQ010_Handler
PUBWEAK IRQ011_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ011_Handler
B IRQ011_Handler
PUBWEAK IRQ012_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ012_Handler
B IRQ012_Handler
PUBWEAK IRQ013_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ013_Handler
B IRQ013_Handler
PUBWEAK IRQ014_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ014_Handler
B IRQ014_Handler
PUBWEAK IRQ015_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ015_Handler
B IRQ015_Handler
PUBWEAK IRQ016_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ016_Handler
B IRQ016_Handler
PUBWEAK IRQ017_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ017_Handler
B IRQ017_Handler
PUBWEAK IRQ018_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ018_Handler
B IRQ018_Handler
PUBWEAK IRQ019_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ019_Handler
B IRQ019_Handler
PUBWEAK IRQ020_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ020_Handler
B IRQ020_Handler
PUBWEAK IRQ021_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ021_Handler
B IRQ021_Handler
PUBWEAK IRQ022_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ022_Handler
B IRQ022_Handler
PUBWEAK IRQ023_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ023_Handler
B IRQ023_Handler
PUBWEAK IRQ024_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ024_Handler
B IRQ024_Handler
PUBWEAK IRQ025_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ025_Handler
B IRQ025_Handler
PUBWEAK IRQ026_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ026_Handler
B IRQ026_Handler
PUBWEAK IRQ027_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ027_Handler
B IRQ027_Handler
PUBWEAK IRQ028_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ028_Handler
B IRQ028_Handler
PUBWEAK IRQ029_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ029_Handler
B IRQ029_Handler
PUBWEAK IRQ030_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ030_Handler
B IRQ030_Handler
PUBWEAK IRQ031_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ031_Handler
B IRQ031_Handler
PUBWEAK IRQ032_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ032_Handler
B IRQ032_Handler
PUBWEAK IRQ033_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ033_Handler
B IRQ033_Handler
PUBWEAK IRQ034_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ034_Handler
B IRQ034_Handler
PUBWEAK IRQ035_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ035_Handler
B IRQ035_Handler
PUBWEAK IRQ036_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ036_Handler
B IRQ036_Handler
PUBWEAK IRQ037_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ037_Handler
B IRQ037_Handler
PUBWEAK IRQ038_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ038_Handler
B IRQ038_Handler
PUBWEAK IRQ039_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ039_Handler
B IRQ039_Handler
PUBWEAK IRQ040_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ040_Handler
B IRQ040_Handler
PUBWEAK IRQ041_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ041_Handler
B IRQ041_Handler
PUBWEAK IRQ042_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ042_Handler
B IRQ042_Handler
PUBWEAK IRQ043_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ043_Handler
B IRQ043_Handler
PUBWEAK IRQ044_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ044_Handler
B IRQ044_Handler
PUBWEAK IRQ045_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ045_Handler
B IRQ045_Handler
PUBWEAK IRQ046_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ046_Handler
B IRQ046_Handler
PUBWEAK IRQ047_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ047_Handler
B IRQ047_Handler
PUBWEAK IRQ048_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ048_Handler
B IRQ048_Handler
PUBWEAK IRQ049_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ049_Handler
B IRQ049_Handler
PUBWEAK IRQ050_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ050_Handler
B IRQ050_Handler
PUBWEAK IRQ051_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ051_Handler
B IRQ051_Handler
PUBWEAK IRQ052_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ052_Handler
B IRQ052_Handler
PUBWEAK IRQ053_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ053_Handler
B IRQ053_Handler
PUBWEAK IRQ054_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ054_Handler
B IRQ054_Handler
PUBWEAK IRQ055_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ055_Handler
B IRQ055_Handler
PUBWEAK IRQ056_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ056_Handler
B IRQ056_Handler
PUBWEAK IRQ057_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ057_Handler
B IRQ057_Handler
PUBWEAK IRQ058_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ058_Handler
B IRQ058_Handler
PUBWEAK IRQ059_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ059_Handler
B IRQ059_Handler
PUBWEAK IRQ060_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ060_Handler
B IRQ060_Handler
PUBWEAK IRQ061_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ061_Handler
B IRQ061_Handler
PUBWEAK IRQ062_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ062_Handler
B IRQ062_Handler
PUBWEAK IRQ063_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ063_Handler
B IRQ063_Handler
PUBWEAK IRQ064_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ064_Handler
B IRQ064_Handler
PUBWEAK IRQ065_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ065_Handler
B IRQ065_Handler
PUBWEAK IRQ066_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ066_Handler
B IRQ066_Handler
PUBWEAK IRQ067_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ067_Handler
B IRQ067_Handler
PUBWEAK IRQ068_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ068_Handler
B IRQ068_Handler
PUBWEAK IRQ069_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ069_Handler
B IRQ069_Handler
PUBWEAK IRQ070_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ070_Handler
B IRQ070_Handler
PUBWEAK IRQ071_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ071_Handler
B IRQ071_Handler
PUBWEAK IRQ072_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ072_Handler
B IRQ072_Handler
PUBWEAK IRQ073_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ073_Handler
B IRQ073_Handler
PUBWEAK IRQ074_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ074_Handler
B IRQ074_Handler
PUBWEAK IRQ075_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ075_Handler
B IRQ075_Handler
PUBWEAK IRQ076_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ076_Handler
B IRQ076_Handler
PUBWEAK IRQ077_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ077_Handler
B IRQ077_Handler
PUBWEAK IRQ078_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ078_Handler
B IRQ078_Handler
PUBWEAK IRQ079_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ079_Handler
B IRQ079_Handler
PUBWEAK IRQ080_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ080_Handler
B IRQ080_Handler
PUBWEAK IRQ081_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ081_Handler
B IRQ081_Handler
PUBWEAK IRQ082_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ082_Handler
B IRQ082_Handler
PUBWEAK IRQ083_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ083_Handler
B IRQ083_Handler
PUBWEAK IRQ084_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ084_Handler
B IRQ084_Handler
PUBWEAK IRQ085_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ085_Handler
B IRQ085_Handler
PUBWEAK IRQ086_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ086_Handler
B IRQ086_Handler
PUBWEAK IRQ087_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ087_Handler
B IRQ087_Handler
PUBWEAK IRQ088_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ088_Handler
B IRQ088_Handler
PUBWEAK IRQ089_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ089_Handler
B IRQ089_Handler
PUBWEAK IRQ090_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ090_Handler
B IRQ090_Handler
PUBWEAK IRQ091_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ091_Handler
B IRQ091_Handler
PUBWEAK IRQ092_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ092_Handler
B IRQ092_Handler
PUBWEAK IRQ093_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ093_Handler
B IRQ093_Handler
PUBWEAK IRQ094_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ094_Handler
B IRQ094_Handler
PUBWEAK IRQ095_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ095_Handler
B IRQ095_Handler
PUBWEAK IRQ096_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ096_Handler
B IRQ096_Handler
PUBWEAK IRQ097_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ097_Handler
B IRQ097_Handler
PUBWEAK IRQ098_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ098_Handler
B IRQ098_Handler
PUBWEAK IRQ099_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ099_Handler
B IRQ099_Handler
PUBWEAK IRQ100_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ100_Handler
B IRQ100_Handler
PUBWEAK IRQ101_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ101_Handler
B IRQ101_Handler
PUBWEAK IRQ102_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ102_Handler
B IRQ102_Handler
PUBWEAK IRQ103_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ103_Handler
B IRQ103_Handler
PUBWEAK IRQ104_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ104_Handler
B IRQ104_Handler
PUBWEAK IRQ105_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ105_Handler
B IRQ105_Handler
PUBWEAK IRQ106_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ106_Handler
B IRQ106_Handler
PUBWEAK IRQ107_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ107_Handler
B IRQ107_Handler
PUBWEAK IRQ108_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ108_Handler
B IRQ108_Handler
PUBWEAK IRQ109_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ109_Handler
B IRQ109_Handler
PUBWEAK IRQ110_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ110_Handler
B IRQ110_Handler
PUBWEAK IRQ111_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ111_Handler
B IRQ111_Handler
PUBWEAK IRQ112_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ112_Handler
B IRQ112_Handler
PUBWEAK IRQ113_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ113_Handler
B IRQ113_Handler
PUBWEAK IRQ114_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ114_Handler
B IRQ114_Handler
PUBWEAK IRQ115_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ115_Handler
B IRQ115_Handler
PUBWEAK IRQ116_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ116_Handler
B IRQ116_Handler
PUBWEAK IRQ117_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ117_Handler
B IRQ117_Handler
PUBWEAK IRQ118_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ118_Handler
B IRQ118_Handler
PUBWEAK IRQ119_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ119_Handler
B IRQ119_Handler
PUBWEAK IRQ120_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ120_Handler
B IRQ120_Handler
PUBWEAK IRQ121_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ121_Handler
B IRQ121_Handler
PUBWEAK IRQ122_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ122_Handler
B IRQ122_Handler
PUBWEAK IRQ123_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ123_Handler
B IRQ123_Handler
PUBWEAK IRQ124_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ124_Handler
B IRQ124_Handler
PUBWEAK IRQ125_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ125_Handler
B IRQ125_Handler
PUBWEAK IRQ126_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ126_Handler
B IRQ126_Handler
PUBWEAK IRQ127_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ127_Handler
B IRQ127_Handler
PUBWEAK IRQ128_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ128_Handler
B IRQ128_Handler
PUBWEAK IRQ129_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ129_Handler
B IRQ129_Handler
PUBWEAK IRQ130_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ130_Handler
B IRQ130_Handler
PUBWEAK IRQ131_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ131_Handler
B IRQ131_Handler
PUBWEAK IRQ132_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ132_Handler
B IRQ132_Handler
PUBWEAK IRQ133_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ133_Handler
B IRQ133_Handler
PUBWEAK IRQ134_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ134_Handler
B IRQ134_Handler
PUBWEAK IRQ135_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ135_Handler
B IRQ135_Handler
PUBWEAK IRQ136_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ136_Handler
B IRQ136_Handler
PUBWEAK IRQ137_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ137_Handler
B IRQ137_Handler
PUBWEAK IRQ138_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ138_Handler
B IRQ138_Handler
PUBWEAK IRQ139_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ139_Handler
B IRQ139_Handler
PUBWEAK IRQ140_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ140_Handler
B IRQ140_Handler
PUBWEAK IRQ141_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ141_Handler
B IRQ141_Handler
PUBWEAK IRQ142_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ142_Handler
B IRQ142_Handler
PUBWEAK IRQ143_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
IRQ143_Handler
B IRQ143_Handler
END
File diff suppressed because it is too large Load Diff
@@ -0,0 +1,215 @@
/**
*******************************************************************************
* @file system_hc32f460.c
* @brief This file provides two functions and two global variables to be called
* from user application.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
2022-10-31 CDT Delete the __low_level_init function of IAR and $Sub$$main function of MDK
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "system_hc32f460.h"
/**
* @addtogroup CMSIS
* @{
*/
/**
* @addtogroup HC32F460_System
* @{
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('define')
******************************************************************************/
/**
* @defgroup HC32F460_System_Local_Macros HC32F460 System Local Macros
* @{
*/
#define HRC_16MHz_VALUE (16000000UL) /*!< Internal high speed RC freq. */
#define HRC_20MHz_VALUE (20000000UL) /*!< Internal high speed RC freq. */
/* HRC select */
#define HRC_FREQ_MON() (*((volatile uint32_t *)(0x40010684UL)))
/* Vector Table base offset field */
#ifndef VECT_TAB_OFFSET
#define VECT_TAB_OFFSET (0x0UL) /*!< This value must be a multiple of 0x400. */
#endif
/**
* @}
*/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/**
* @addtogroup HC32F460_System_Global_Variable
* @{
*/
/*!< System clock frequency (Core clock) */
__NO_INIT uint32_t SystemCoreClock;
/*!< High speed RC frequency (HCR clock) */
__NO_INIT uint32_t HRC_VALUE;
/**
* @}
*/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @addtogroup HC32F460_System_Global_Functions
* @{
*/
/**
* @brief Setup the microcontroller system. Initialize the System and update
* the SystemCoreClock variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* Configure the Vector Table relocation */
extern unsigned char Image$$ER_IROM1$$Base;
uint32_t rom_base =0u;
rom_base= (uint32_t)&Image$$ER_IROM1$$Base;
/* FPU settings */
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 20) | (3UL << 22)); /* set CP10 and CP11 Full Access */
#endif
SystemCoreClockUpdate();
#if defined (ROM_EXT_QSPI)
SystemInit_QspiMem();
#endif /* ROM_EXT_QSPI */
SCB->VTOR = rom_base; /* Vector Table Relocation */
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint8_t u8SysClkSrc;
uint32_t plln;
uint32_t pllp;
uint32_t pllm;
uint32_t u32PllSrcFreq;
/* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */
if (1UL == (HRC_FREQ_MON() & 1UL)) {
HRC_VALUE = HRC_16MHz_VALUE;
} else {
HRC_VALUE = HRC_20MHz_VALUE;
}
u8SysClkSrc = CM_CMU->CKSWR & CMU_CKSWR_CKSW;
switch (u8SysClkSrc) {
case 0x00U: /* use internal high speed RC */
SystemCoreClock = HRC_VALUE;
break;
case 0x01U: /* use internal middle speed RC */
SystemCoreClock = MRC_VALUE;
break;
case 0x02U: /* use internal low speed RC */
SystemCoreClock = LRC_VALUE;
break;
case 0x03U: /* use external high speed OSC */
SystemCoreClock = XTAL_VALUE;
break;
case 0x04U: /* use external low speed OSC */
SystemCoreClock = XTAL32_VALUE;
break;
case 0x05U: /* use MPLL */
/* PLLCLK = ((pllsrc / pllm) * plln) / pllp */
plln = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLN) >> CMU_PLLCFGR_MPLLN_POS;
pllp = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLP) >> CMU_PLLCFGR_MPLLP_POS;
pllm = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLM) >> CMU_PLLCFGR_MPLLM_POS;
if (0UL == (CM_CMU->PLLCFGR & CMU_PLLCFGR_PLLSRC)) { /* use external highspeed OSC as PLL source */
u32PllSrcFreq = XTAL_VALUE;
} else { /* use internal high RC as PLL source */
u32PllSrcFreq = HRC_VALUE;
}
SystemCoreClock = u32PllSrcFreq / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL);
break;
default:
break;
}
}
#if defined (ROM_EXT_QSPI)
/**
* @brief Initialize the QSPI memory.
* @param None
* @retval None
*/
__WEAKDEF void SystemInit_QspiMem(void)
{
/* QSPI configure */
CM_GPIO->PWPR = 0xA501U;
/* High driver */
CM_GPIO->PCRC7 = 0x0120U;
CM_GPIO->PCRC6 = 0x0120U;
CM_GPIO->PCRD8 = 0x0120U;
CM_GPIO->PCRD9 = 0x0120U;
CM_GPIO->PCRD10 = 0x0120U;
CM_GPIO->PCRD11 = 0x0120U;
/* Set function */
CM_GPIO->PFSRC7 = 0x07U;
CM_GPIO->PFSRC6 = 0x07U;
CM_GPIO->PFSRD8 = 0x07U;
CM_GPIO->PFSRD9 = 0x07U;
CM_GPIO->PFSRD10 = 0x07U;
CM_GPIO->PFSRD11 = 0x07U;
/* qspi configure */
CM_PWC->FCG1 &= ~0x00000008UL;
CM_QSPI->CR = 0x0002000D;
CM_QSPI->CSCR = 0x00000001;
CM_QSPI->FCR = 0x00008332;
}
#endif /* ROM_EXT_QSPI */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/