初始版本
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/**
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*******************************************************************************
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* @file hc32f4xx.h
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* @brief This file contains the common part of the HC32 series.
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@verbatim
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Change Logs:
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||||
Date Author Notes
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||||
2022-03-31 CDT First version
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||||
@endverbatim
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||||
*******************************************************************************
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||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
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||||
*
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||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
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||||
*
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*******************************************************************************
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*/
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#ifndef __HC32F4XX_H__
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#define __HC32F4XX_H__
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*******************************************************************************
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* Include files
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******************************************************************************/
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/**
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* @brief HC32F4xx Device Include
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*/
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#if defined(HC32F460)
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#include "hc32f460.h"
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#include "system_hc32f460.h"
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#else
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#error "Please select first the target HC32xxxx device used in your application (in hc32xxxx.h file)"
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#endif
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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* Global function prototypes (definition in C source)
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******************************************************************************/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HC32F4XX_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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@@ -0,0 +1,140 @@
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/**
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*******************************************************************************
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* @file system_hc32f460.h
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* @brief This file contains all the functions prototypes of the HC32 System.
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@verbatim
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||||
Change Logs:
|
||||
Date Author Notes
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||||
2022-03-31 CDT First version
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@endverbatim
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||||
*******************************************************************************
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||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
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||||
*
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||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
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||||
* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#ifndef __SYSTEM_HC32F460_H__
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#define __SYSTEM_HC32F460_H__
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_ll_def.h"
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#include "hc32f4xx.h"
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#include "hc32f4xx_conf.h"
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/**
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* @addtogroup CMSIS
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* @{
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*/
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/**
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* @addtogroup HC32F460_System
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* @{
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*/
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/*******************************************************************************
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* Global pre-processor symbols/macros ('define')
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******************************************************************************/
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/**
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* @addtogroup HC32F460_System_Global_Macros
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* @{
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*/
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/**
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* @addtogroup HC32F460_System_Clock_Source
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* @{
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*/
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#if !defined (MRC_VALUE)
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#define MRC_VALUE (8000000UL) /*!< Internal middle speed RC freq. */
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#endif
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#if !defined (LRC_VALUE)
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#define LRC_VALUE (32768UL) /*!< Internal low speed RC freq. */
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#endif
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#if !defined (SWDTLRC_VALUE)
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#define SWDTLRC_VALUE (10000UL) /*!< Internal SWDT low speed RC freq. */
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#endif
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#if !defined (XTAL_VALUE)
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#define XTAL_VALUE (8000000UL) /*!< External high speed OSC freq. */
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#endif
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#if !defined (XTAL32_VALUE)
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#define XTAL32_VALUE (32768UL) /*!< External low speed OSC freq. */
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#endif
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#if !defined (HCLK_VALUE)
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#define HCLK_VALUE (SystemCoreClock >> ((CM_CMU->SCFGR & CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS))
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#endif
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/**
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* @}
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*/
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|
||||
/**
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||||
* @}
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||||
*/
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||||
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||||
/*******************************************************************************
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||||
* Global variable definitions ('extern')
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******************************************************************************/
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/**
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* @addtogroup HC32F460_System_Exported_Variable
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* @{
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*/
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extern uint32_t SystemCoreClock; /*!< System clock frequency (Core clock) */
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extern uint32_t HRC_VALUE; /*!< HRC frequency */
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/**
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* @}
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*/
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||||
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||||
/*******************************************************************************
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||||
* Global function prototypes (definition in C source)
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******************************************************************************/
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/**
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* @addtogroup HC32F460_System_Global_Functions
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* @{
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*/
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extern void SystemInit(void); /*!< Initialize the system */
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extern void SystemCoreClockUpdate(void); /*!< Update SystemCoreClock variable */
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#if defined (ROM_EXT_QSPI)
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void SystemInit_QspiMem(void);
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#endif
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||||
|
||||
/**
|
||||
* @}
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||||
*/
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||||
|
||||
/**
|
||||
* @}
|
||||
*/
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||||
|
||||
/**
|
||||
* @}
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||||
*/
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||||
|
||||
#ifdef __cplusplus
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||||
}
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||||
#endif
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||||
|
||||
#endif /* __SYSTEM_HC32F460_H__ */
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||||
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||||
/*******************************************************************************
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||||
* EOF (not truncated)
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||||
******************************************************************************/
|
||||
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@@ -0,0 +1,16 @@
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FUNC void Setup (void) {
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||||
|
||||
SP = _RDWORD(0x1FFE0000);
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||||
|
||||
PC = _RDWORD(0x1FFE0004);
|
||||
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||||
_WDWORD(0xE000ED08, 0x1FFE0000);
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||||
|
||||
}
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||||
|
||||
|
||||
LOAD .\output\release\efm_chip_erase.axf INCREMENTAL
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||||
Setup();
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||||
|
||||
g, main
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||||
Binary file not shown.
@@ -0,0 +1,618 @@
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||||
;/**
|
||||
; ******************************************************************************
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||||
; @file startup_hc32f460.s
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||||
; @brief Startup for MDK.
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||||
; verbatim
|
||||
; Change Logs:
|
||||
; Date Author Notes
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||||
; 2022-03-31 CDT First version
|
||||
; endverbatim
|
||||
; *****************************************************************************
|
||||
; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
; *
|
||||
; * This software component is licensed by XHSC under BSD 3-Clause license
|
||||
; * (the "License"); You may not use this file except in compliance with the
|
||||
; * License. You may obtain a copy of the License at:
|
||||
; * opensource.org/licenses/BSD-3-Clause
|
||||
; *
|
||||
; ******************************************************************************
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||||
; */
|
||||
|
||||
; Stack Configuration
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||||
; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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||||
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||||
Stack_Size EQU 0x00002000
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||||
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||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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||||
|
||||
; Heap Configuration
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||||
; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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||||
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||||
Heap_Size EQU 0x00002000
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||||
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||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
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||||
Heap_Mem SPACE Heap_Size
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__heap_limit
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||||
|
||||
PRESERVE8
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THUMB
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||||
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||||
; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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||||
DCD MemManage_Handler ; MPU Fault Handler
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||||
DCD BusFault_Handler ; Bus Fault Handler
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||||
DCD UsageFault_Handler ; Usage Fault Handler
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||||
DCD 0 ; Reserved
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||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
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||||
DCD DebugMon_Handler ; Debug Monitor Handler
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||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; Peripheral Interrupts
|
||||
DCD IRQ000_Handler
|
||||
DCD IRQ001_Handler
|
||||
DCD IRQ002_Handler
|
||||
DCD IRQ003_Handler
|
||||
DCD IRQ004_Handler
|
||||
DCD IRQ005_Handler
|
||||
DCD IRQ006_Handler
|
||||
DCD IRQ007_Handler
|
||||
DCD IRQ008_Handler
|
||||
DCD IRQ009_Handler
|
||||
DCD IRQ010_Handler
|
||||
DCD IRQ011_Handler
|
||||
DCD IRQ012_Handler
|
||||
DCD IRQ013_Handler
|
||||
DCD IRQ014_Handler
|
||||
DCD IRQ015_Handler
|
||||
DCD IRQ016_Handler
|
||||
DCD IRQ017_Handler
|
||||
DCD IRQ018_Handler
|
||||
DCD IRQ019_Handler
|
||||
DCD IRQ020_Handler
|
||||
DCD IRQ021_Handler
|
||||
DCD IRQ022_Handler
|
||||
DCD IRQ023_Handler
|
||||
DCD IRQ024_Handler
|
||||
DCD IRQ025_Handler
|
||||
DCD IRQ026_Handler
|
||||
DCD IRQ027_Handler
|
||||
DCD IRQ028_Handler
|
||||
DCD IRQ029_Handler
|
||||
DCD IRQ030_Handler
|
||||
DCD IRQ031_Handler
|
||||
DCD IRQ032_Handler
|
||||
DCD IRQ033_Handler
|
||||
DCD IRQ034_Handler
|
||||
DCD IRQ035_Handler
|
||||
DCD IRQ036_Handler
|
||||
DCD IRQ037_Handler
|
||||
DCD IRQ038_Handler
|
||||
DCD IRQ039_Handler
|
||||
DCD IRQ040_Handler
|
||||
DCD IRQ041_Handler
|
||||
DCD IRQ042_Handler
|
||||
DCD IRQ043_Handler
|
||||
DCD IRQ044_Handler
|
||||
DCD IRQ045_Handler
|
||||
DCD IRQ046_Handler
|
||||
DCD IRQ047_Handler
|
||||
DCD IRQ048_Handler
|
||||
DCD IRQ049_Handler
|
||||
DCD IRQ050_Handler
|
||||
DCD IRQ051_Handler
|
||||
DCD IRQ052_Handler
|
||||
DCD IRQ053_Handler
|
||||
DCD IRQ054_Handler
|
||||
DCD IRQ055_Handler
|
||||
DCD IRQ056_Handler
|
||||
DCD IRQ057_Handler
|
||||
DCD IRQ058_Handler
|
||||
DCD IRQ059_Handler
|
||||
DCD IRQ060_Handler
|
||||
DCD IRQ061_Handler
|
||||
DCD IRQ062_Handler
|
||||
DCD IRQ063_Handler
|
||||
DCD IRQ064_Handler
|
||||
DCD IRQ065_Handler
|
||||
DCD IRQ066_Handler
|
||||
DCD IRQ067_Handler
|
||||
DCD IRQ068_Handler
|
||||
DCD IRQ069_Handler
|
||||
DCD IRQ070_Handler
|
||||
DCD IRQ071_Handler
|
||||
DCD IRQ072_Handler
|
||||
DCD IRQ073_Handler
|
||||
DCD IRQ074_Handler
|
||||
DCD IRQ075_Handler
|
||||
DCD IRQ076_Handler
|
||||
DCD IRQ077_Handler
|
||||
DCD IRQ078_Handler
|
||||
DCD IRQ079_Handler
|
||||
DCD IRQ080_Handler
|
||||
DCD IRQ081_Handler
|
||||
DCD IRQ082_Handler
|
||||
DCD IRQ083_Handler
|
||||
DCD IRQ084_Handler
|
||||
DCD IRQ085_Handler
|
||||
DCD IRQ086_Handler
|
||||
DCD IRQ087_Handler
|
||||
DCD IRQ088_Handler
|
||||
DCD IRQ089_Handler
|
||||
DCD IRQ090_Handler
|
||||
DCD IRQ091_Handler
|
||||
DCD IRQ092_Handler
|
||||
DCD IRQ093_Handler
|
||||
DCD IRQ094_Handler
|
||||
DCD IRQ095_Handler
|
||||
DCD IRQ096_Handler
|
||||
DCD IRQ097_Handler
|
||||
DCD IRQ098_Handler
|
||||
DCD IRQ099_Handler
|
||||
DCD IRQ100_Handler
|
||||
DCD IRQ101_Handler
|
||||
DCD IRQ102_Handler
|
||||
DCD IRQ103_Handler
|
||||
DCD IRQ104_Handler
|
||||
DCD IRQ105_Handler
|
||||
DCD IRQ106_Handler
|
||||
DCD IRQ107_Handler
|
||||
DCD IRQ108_Handler
|
||||
DCD IRQ109_Handler
|
||||
DCD IRQ110_Handler
|
||||
DCD IRQ111_Handler
|
||||
DCD IRQ112_Handler
|
||||
DCD IRQ113_Handler
|
||||
DCD IRQ114_Handler
|
||||
DCD IRQ115_Handler
|
||||
DCD IRQ116_Handler
|
||||
DCD IRQ117_Handler
|
||||
DCD IRQ118_Handler
|
||||
DCD IRQ119_Handler
|
||||
DCD IRQ120_Handler
|
||||
DCD IRQ121_Handler
|
||||
DCD IRQ122_Handler
|
||||
DCD IRQ123_Handler
|
||||
DCD IRQ124_Handler
|
||||
DCD IRQ125_Handler
|
||||
DCD IRQ126_Handler
|
||||
DCD IRQ127_Handler
|
||||
DCD IRQ128_Handler
|
||||
DCD IRQ129_Handler
|
||||
DCD IRQ130_Handler
|
||||
DCD IRQ131_Handler
|
||||
DCD IRQ132_Handler
|
||||
DCD IRQ133_Handler
|
||||
DCD IRQ134_Handler
|
||||
DCD IRQ135_Handler
|
||||
DCD IRQ136_Handler
|
||||
DCD IRQ137_Handler
|
||||
DCD IRQ138_Handler
|
||||
DCD IRQ139_Handler
|
||||
DCD IRQ140_Handler
|
||||
DCD IRQ141_Handler
|
||||
DCD IRQ142_Handler
|
||||
DCD IRQ143_Handler
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
SET_SRAM3_WAIT
|
||||
LDR R0, =0x40050804
|
||||
MOV R1, #0x77
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =0x4005080C
|
||||
MOV R1, #0x77
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =0x40050800
|
||||
MOV R1, #0x1100
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =0x40050804
|
||||
MOV R1, #0x76
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =0x4005080C
|
||||
MOV R1, #0x76
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT IRQ000_Handler [WEAK]
|
||||
EXPORT IRQ001_Handler [WEAK]
|
||||
EXPORT IRQ002_Handler [WEAK]
|
||||
EXPORT IRQ003_Handler [WEAK]
|
||||
EXPORT IRQ004_Handler [WEAK]
|
||||
EXPORT IRQ005_Handler [WEAK]
|
||||
EXPORT IRQ006_Handler [WEAK]
|
||||
EXPORT IRQ007_Handler [WEAK]
|
||||
EXPORT IRQ008_Handler [WEAK]
|
||||
EXPORT IRQ009_Handler [WEAK]
|
||||
EXPORT IRQ010_Handler [WEAK]
|
||||
EXPORT IRQ011_Handler [WEAK]
|
||||
EXPORT IRQ012_Handler [WEAK]
|
||||
EXPORT IRQ013_Handler [WEAK]
|
||||
EXPORT IRQ014_Handler [WEAK]
|
||||
EXPORT IRQ015_Handler [WEAK]
|
||||
EXPORT IRQ016_Handler [WEAK]
|
||||
EXPORT IRQ017_Handler [WEAK]
|
||||
EXPORT IRQ018_Handler [WEAK]
|
||||
EXPORT IRQ019_Handler [WEAK]
|
||||
EXPORT IRQ020_Handler [WEAK]
|
||||
EXPORT IRQ021_Handler [WEAK]
|
||||
EXPORT IRQ022_Handler [WEAK]
|
||||
EXPORT IRQ023_Handler [WEAK]
|
||||
EXPORT IRQ024_Handler [WEAK]
|
||||
EXPORT IRQ025_Handler [WEAK]
|
||||
EXPORT IRQ026_Handler [WEAK]
|
||||
EXPORT IRQ027_Handler [WEAK]
|
||||
EXPORT IRQ028_Handler [WEAK]
|
||||
EXPORT IRQ029_Handler [WEAK]
|
||||
EXPORT IRQ030_Handler [WEAK]
|
||||
EXPORT IRQ031_Handler [WEAK]
|
||||
EXPORT IRQ032_Handler [WEAK]
|
||||
EXPORT IRQ033_Handler [WEAK]
|
||||
EXPORT IRQ034_Handler [WEAK]
|
||||
EXPORT IRQ035_Handler [WEAK]
|
||||
EXPORT IRQ036_Handler [WEAK]
|
||||
EXPORT IRQ037_Handler [WEAK]
|
||||
EXPORT IRQ038_Handler [WEAK]
|
||||
EXPORT IRQ039_Handler [WEAK]
|
||||
EXPORT IRQ040_Handler [WEAK]
|
||||
EXPORT IRQ041_Handler [WEAK]
|
||||
EXPORT IRQ042_Handler [WEAK]
|
||||
EXPORT IRQ043_Handler [WEAK]
|
||||
EXPORT IRQ044_Handler [WEAK]
|
||||
EXPORT IRQ045_Handler [WEAK]
|
||||
EXPORT IRQ046_Handler [WEAK]
|
||||
EXPORT IRQ047_Handler [WEAK]
|
||||
EXPORT IRQ048_Handler [WEAK]
|
||||
EXPORT IRQ049_Handler [WEAK]
|
||||
EXPORT IRQ050_Handler [WEAK]
|
||||
EXPORT IRQ051_Handler [WEAK]
|
||||
EXPORT IRQ052_Handler [WEAK]
|
||||
EXPORT IRQ053_Handler [WEAK]
|
||||
EXPORT IRQ054_Handler [WEAK]
|
||||
EXPORT IRQ055_Handler [WEAK]
|
||||
EXPORT IRQ056_Handler [WEAK]
|
||||
EXPORT IRQ057_Handler [WEAK]
|
||||
EXPORT IRQ058_Handler [WEAK]
|
||||
EXPORT IRQ059_Handler [WEAK]
|
||||
EXPORT IRQ060_Handler [WEAK]
|
||||
EXPORT IRQ061_Handler [WEAK]
|
||||
EXPORT IRQ062_Handler [WEAK]
|
||||
EXPORT IRQ063_Handler [WEAK]
|
||||
EXPORT IRQ064_Handler [WEAK]
|
||||
EXPORT IRQ065_Handler [WEAK]
|
||||
EXPORT IRQ066_Handler [WEAK]
|
||||
EXPORT IRQ067_Handler [WEAK]
|
||||
EXPORT IRQ068_Handler [WEAK]
|
||||
EXPORT IRQ069_Handler [WEAK]
|
||||
EXPORT IRQ070_Handler [WEAK]
|
||||
EXPORT IRQ071_Handler [WEAK]
|
||||
EXPORT IRQ072_Handler [WEAK]
|
||||
EXPORT IRQ073_Handler [WEAK]
|
||||
EXPORT IRQ074_Handler [WEAK]
|
||||
EXPORT IRQ075_Handler [WEAK]
|
||||
EXPORT IRQ076_Handler [WEAK]
|
||||
EXPORT IRQ077_Handler [WEAK]
|
||||
EXPORT IRQ078_Handler [WEAK]
|
||||
EXPORT IRQ079_Handler [WEAK]
|
||||
EXPORT IRQ080_Handler [WEAK]
|
||||
EXPORT IRQ081_Handler [WEAK]
|
||||
EXPORT IRQ082_Handler [WEAK]
|
||||
EXPORT IRQ083_Handler [WEAK]
|
||||
EXPORT IRQ084_Handler [WEAK]
|
||||
EXPORT IRQ085_Handler [WEAK]
|
||||
EXPORT IRQ086_Handler [WEAK]
|
||||
EXPORT IRQ087_Handler [WEAK]
|
||||
EXPORT IRQ088_Handler [WEAK]
|
||||
EXPORT IRQ089_Handler [WEAK]
|
||||
EXPORT IRQ090_Handler [WEAK]
|
||||
EXPORT IRQ091_Handler [WEAK]
|
||||
EXPORT IRQ092_Handler [WEAK]
|
||||
EXPORT IRQ093_Handler [WEAK]
|
||||
EXPORT IRQ094_Handler [WEAK]
|
||||
EXPORT IRQ095_Handler [WEAK]
|
||||
EXPORT IRQ096_Handler [WEAK]
|
||||
EXPORT IRQ097_Handler [WEAK]
|
||||
EXPORT IRQ098_Handler [WEAK]
|
||||
EXPORT IRQ099_Handler [WEAK]
|
||||
EXPORT IRQ100_Handler [WEAK]
|
||||
EXPORT IRQ101_Handler [WEAK]
|
||||
EXPORT IRQ102_Handler [WEAK]
|
||||
EXPORT IRQ103_Handler [WEAK]
|
||||
EXPORT IRQ104_Handler [WEAK]
|
||||
EXPORT IRQ105_Handler [WEAK]
|
||||
EXPORT IRQ106_Handler [WEAK]
|
||||
EXPORT IRQ107_Handler [WEAK]
|
||||
EXPORT IRQ108_Handler [WEAK]
|
||||
EXPORT IRQ109_Handler [WEAK]
|
||||
EXPORT IRQ110_Handler [WEAK]
|
||||
EXPORT IRQ111_Handler [WEAK]
|
||||
EXPORT IRQ112_Handler [WEAK]
|
||||
EXPORT IRQ113_Handler [WEAK]
|
||||
EXPORT IRQ114_Handler [WEAK]
|
||||
EXPORT IRQ115_Handler [WEAK]
|
||||
EXPORT IRQ116_Handler [WEAK]
|
||||
EXPORT IRQ117_Handler [WEAK]
|
||||
EXPORT IRQ118_Handler [WEAK]
|
||||
EXPORT IRQ119_Handler [WEAK]
|
||||
EXPORT IRQ120_Handler [WEAK]
|
||||
EXPORT IRQ121_Handler [WEAK]
|
||||
EXPORT IRQ122_Handler [WEAK]
|
||||
EXPORT IRQ123_Handler [WEAK]
|
||||
EXPORT IRQ124_Handler [WEAK]
|
||||
EXPORT IRQ125_Handler [WEAK]
|
||||
EXPORT IRQ126_Handler [WEAK]
|
||||
EXPORT IRQ127_Handler [WEAK]
|
||||
EXPORT IRQ128_Handler [WEAK]
|
||||
EXPORT IRQ129_Handler [WEAK]
|
||||
EXPORT IRQ130_Handler [WEAK]
|
||||
EXPORT IRQ131_Handler [WEAK]
|
||||
EXPORT IRQ132_Handler [WEAK]
|
||||
EXPORT IRQ133_Handler [WEAK]
|
||||
EXPORT IRQ134_Handler [WEAK]
|
||||
EXPORT IRQ135_Handler [WEAK]
|
||||
EXPORT IRQ136_Handler [WEAK]
|
||||
EXPORT IRQ137_Handler [WEAK]
|
||||
EXPORT IRQ138_Handler [WEAK]
|
||||
EXPORT IRQ139_Handler [WEAK]
|
||||
EXPORT IRQ140_Handler [WEAK]
|
||||
EXPORT IRQ141_Handler [WEAK]
|
||||
EXPORT IRQ142_Handler [WEAK]
|
||||
EXPORT IRQ143_Handler [WEAK]
|
||||
|
||||
IRQ000_Handler
|
||||
IRQ001_Handler
|
||||
IRQ002_Handler
|
||||
IRQ003_Handler
|
||||
IRQ004_Handler
|
||||
IRQ005_Handler
|
||||
IRQ006_Handler
|
||||
IRQ007_Handler
|
||||
IRQ008_Handler
|
||||
IRQ009_Handler
|
||||
IRQ010_Handler
|
||||
IRQ011_Handler
|
||||
IRQ012_Handler
|
||||
IRQ013_Handler
|
||||
IRQ014_Handler
|
||||
IRQ015_Handler
|
||||
IRQ016_Handler
|
||||
IRQ017_Handler
|
||||
IRQ018_Handler
|
||||
IRQ019_Handler
|
||||
IRQ020_Handler
|
||||
IRQ021_Handler
|
||||
IRQ022_Handler
|
||||
IRQ023_Handler
|
||||
IRQ024_Handler
|
||||
IRQ025_Handler
|
||||
IRQ026_Handler
|
||||
IRQ027_Handler
|
||||
IRQ028_Handler
|
||||
IRQ029_Handler
|
||||
IRQ030_Handler
|
||||
IRQ031_Handler
|
||||
IRQ032_Handler
|
||||
IRQ033_Handler
|
||||
IRQ034_Handler
|
||||
IRQ035_Handler
|
||||
IRQ036_Handler
|
||||
IRQ037_Handler
|
||||
IRQ038_Handler
|
||||
IRQ039_Handler
|
||||
IRQ040_Handler
|
||||
IRQ041_Handler
|
||||
IRQ042_Handler
|
||||
IRQ043_Handler
|
||||
IRQ044_Handler
|
||||
IRQ045_Handler
|
||||
IRQ046_Handler
|
||||
IRQ047_Handler
|
||||
IRQ048_Handler
|
||||
IRQ049_Handler
|
||||
IRQ050_Handler
|
||||
IRQ051_Handler
|
||||
IRQ052_Handler
|
||||
IRQ053_Handler
|
||||
IRQ054_Handler
|
||||
IRQ055_Handler
|
||||
IRQ056_Handler
|
||||
IRQ057_Handler
|
||||
IRQ058_Handler
|
||||
IRQ059_Handler
|
||||
IRQ060_Handler
|
||||
IRQ061_Handler
|
||||
IRQ062_Handler
|
||||
IRQ063_Handler
|
||||
IRQ064_Handler
|
||||
IRQ065_Handler
|
||||
IRQ066_Handler
|
||||
IRQ067_Handler
|
||||
IRQ068_Handler
|
||||
IRQ069_Handler
|
||||
IRQ070_Handler
|
||||
IRQ071_Handler
|
||||
IRQ072_Handler
|
||||
IRQ073_Handler
|
||||
IRQ074_Handler
|
||||
IRQ075_Handler
|
||||
IRQ076_Handler
|
||||
IRQ077_Handler
|
||||
IRQ078_Handler
|
||||
IRQ079_Handler
|
||||
IRQ080_Handler
|
||||
IRQ081_Handler
|
||||
IRQ082_Handler
|
||||
IRQ083_Handler
|
||||
IRQ084_Handler
|
||||
IRQ085_Handler
|
||||
IRQ086_Handler
|
||||
IRQ087_Handler
|
||||
IRQ088_Handler
|
||||
IRQ089_Handler
|
||||
IRQ090_Handler
|
||||
IRQ091_Handler
|
||||
IRQ092_Handler
|
||||
IRQ093_Handler
|
||||
IRQ094_Handler
|
||||
IRQ095_Handler
|
||||
IRQ096_Handler
|
||||
IRQ097_Handler
|
||||
IRQ098_Handler
|
||||
IRQ099_Handler
|
||||
IRQ100_Handler
|
||||
IRQ101_Handler
|
||||
IRQ102_Handler
|
||||
IRQ103_Handler
|
||||
IRQ104_Handler
|
||||
IRQ105_Handler
|
||||
IRQ106_Handler
|
||||
IRQ107_Handler
|
||||
IRQ108_Handler
|
||||
IRQ109_Handler
|
||||
IRQ110_Handler
|
||||
IRQ111_Handler
|
||||
IRQ112_Handler
|
||||
IRQ113_Handler
|
||||
IRQ114_Handler
|
||||
IRQ115_Handler
|
||||
IRQ116_Handler
|
||||
IRQ117_Handler
|
||||
IRQ118_Handler
|
||||
IRQ119_Handler
|
||||
IRQ120_Handler
|
||||
IRQ121_Handler
|
||||
IRQ122_Handler
|
||||
IRQ123_Handler
|
||||
IRQ124_Handler
|
||||
IRQ125_Handler
|
||||
IRQ126_Handler
|
||||
IRQ127_Handler
|
||||
IRQ128_Handler
|
||||
IRQ129_Handler
|
||||
IRQ130_Handler
|
||||
IRQ131_Handler
|
||||
IRQ132_Handler
|
||||
IRQ133_Handler
|
||||
IRQ134_Handler
|
||||
IRQ135_Handler
|
||||
IRQ136_Handler
|
||||
IRQ137_Handler
|
||||
IRQ138_Handler
|
||||
IRQ139_Handler
|
||||
IRQ140_Handler
|
||||
IRQ141_Handler
|
||||
IRQ142_Handler
|
||||
IRQ143_Handler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
@@ -0,0 +1,208 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************/
|
||||
/* File HC32F460xC.ld */
|
||||
/* Abstract Linker script for HC32F460 Device with */
|
||||
/* 256KByte FLASH, 192KByte RAM */
|
||||
/* Version V1.0 */
|
||||
/* Date 2022-03-31 */
|
||||
/*****************************************************************************/
|
||||
|
||||
/* Custom defines, according to section 7.7 of the user manual.
|
||||
Take OTP sector 0 for example. */
|
||||
__OTP_DATA_START = 0x03000C00;
|
||||
__OTP_DATA_SIZE = 64;
|
||||
__OTP_LOCK_START = 0x03000FC0;
|
||||
__OTP_LOCK_SIZE = 4;
|
||||
|
||||
/* Use contiguous memory regions for simple. */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x00000000, LENGTH = 256K
|
||||
OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE
|
||||
OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE
|
||||
RAM (rwx): ORIGIN = 0x1FFF8000, LENGTH = 188K
|
||||
RET_RAM (rwx): ORIGIN = 0x200F0000, LENGTH = 4K
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.vectors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.icg_sec 0x00000400 :
|
||||
{
|
||||
KEEP(*(.icg_sec))
|
||||
} >FLASH
|
||||
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} >FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
__etext = ALIGN(4);
|
||||
|
||||
.otp_data_sec :
|
||||
{
|
||||
KEEP(*(.otp_data_sec))
|
||||
} >OTP_DATA
|
||||
|
||||
.otp_lock_sec :
|
||||
{
|
||||
KEEP(*(.otp_lock_sec))
|
||||
} >OTP_LOCK
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data)
|
||||
*(.data*)
|
||||
. = ALIGN(4);
|
||||
*(.ramfunc)
|
||||
*(.ramfunc*)
|
||||
. = ALIGN(4);
|
||||
__data_end__ = .;
|
||||
} >RAM
|
||||
|
||||
__etext_ret_ram = __etext + ALIGN (SIZEOF(.data), 4);
|
||||
.ret_ram_data : AT (__etext_ret_ram)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__data_start_ret_ram__ = .;
|
||||
*(.ret_ram_data)
|
||||
*(.ret_ram_data*)
|
||||
. = ALIGN(4);
|
||||
__data_end_ret_ram__ = .;
|
||||
} >RET_RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
.ret_ram_bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start_ret_ram__ = .;
|
||||
*(.ret_ram_bss)
|
||||
*(.ret_ram_bss*)
|
||||
. = ALIGN(4);
|
||||
__bss_end_ret_ram__ = .;
|
||||
} >RET_RAM
|
||||
|
||||
.heap_stack (COPY) :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
PROVIDE(_end = .);
|
||||
*(.heap*)
|
||||
. = ALIGN(8);
|
||||
__HeapLimit = .;
|
||||
|
||||
__StackLimit = .;
|
||||
*(.stack*)
|
||||
. = ALIGN(8);
|
||||
__StackTop = .;
|
||||
} >RAM
|
||||
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a (*)
|
||||
libm.a (*)
|
||||
libgcc.a (*)
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
|
||||
PROVIDE(_stack = __StackTop);
|
||||
PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase);
|
||||
PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit);
|
||||
|
||||
__RamEnd = ORIGIN(RAM) + LENGTH(RAM);
|
||||
ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack")
|
||||
}
|
||||
@@ -0,0 +1,208 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************/
|
||||
/* File HC32F460xE.ld */
|
||||
/* Abstract Linker script for HC32F460 Device with */
|
||||
/* 512KByte FLASH, 192KByte RAM */
|
||||
/* Version V1.0 */
|
||||
/* Date 2022-03-31 */
|
||||
/*****************************************************************************/
|
||||
|
||||
/* Custom defines, according to section 7.7 of the user manual.
|
||||
Take OTP sector 0 for example. */
|
||||
__OTP_DATA_START = 0x03000C00;
|
||||
__OTP_DATA_SIZE = 64;
|
||||
__OTP_LOCK_START = 0x03000FC0;
|
||||
__OTP_LOCK_SIZE = 4;
|
||||
|
||||
/* Use contiguous memory regions for simple. */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x00000000, LENGTH = 512K
|
||||
OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE
|
||||
OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE
|
||||
RAM (rwx): ORIGIN = 0x1FFF8000, LENGTH = 188K
|
||||
RET_RAM (rwx): ORIGIN = 0x200F0000, LENGTH = 4K
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.vectors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.icg_sec 0x00000400 :
|
||||
{
|
||||
KEEP(*(.icg_sec))
|
||||
} >FLASH
|
||||
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} >FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
__etext = ALIGN(4);
|
||||
|
||||
.otp_data_sec :
|
||||
{
|
||||
KEEP(*(.otp_data_sec))
|
||||
} >OTP_DATA
|
||||
|
||||
.otp_lock_sec :
|
||||
{
|
||||
KEEP(*(.otp_lock_sec))
|
||||
} >OTP_LOCK
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data)
|
||||
*(.data*)
|
||||
. = ALIGN(4);
|
||||
*(.ramfunc)
|
||||
*(.ramfunc*)
|
||||
. = ALIGN(4);
|
||||
__data_end__ = .;
|
||||
} >RAM
|
||||
|
||||
__etext_ret_ram = __etext + ALIGN (SIZEOF(.data), 4);
|
||||
.ret_ram_data : AT (__etext_ret_ram)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__data_start_ret_ram__ = .;
|
||||
*(.ret_ram_data)
|
||||
*(.ret_ram_data*)
|
||||
. = ALIGN(4);
|
||||
__data_end_ret_ram__ = .;
|
||||
} >RET_RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
.ret_ram_bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start_ret_ram__ = .;
|
||||
*(.ret_ram_bss)
|
||||
*(.ret_ram_bss*)
|
||||
. = ALIGN(4);
|
||||
__bss_end_ret_ram__ = .;
|
||||
} >RET_RAM
|
||||
|
||||
.heap_stack (COPY) :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
PROVIDE(_end = .);
|
||||
*(.heap*)
|
||||
. = ALIGN(8);
|
||||
__HeapLimit = .;
|
||||
|
||||
__StackLimit = .;
|
||||
*(.stack*)
|
||||
. = ALIGN(8);
|
||||
__StackTop = .;
|
||||
} >RAM
|
||||
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a (*)
|
||||
libm.a (*)
|
||||
libgcc.a (*)
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
|
||||
PROVIDE(_stack = __StackTop);
|
||||
PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase);
|
||||
PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit);
|
||||
|
||||
__RamEnd = ORIGIN(RAM) + LENGTH(RAM);
|
||||
ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack")
|
||||
}
|
||||
@@ -0,0 +1,538 @@
|
||||
;/**
|
||||
; ******************************************************************************
|
||||
; @file startup_hc32f460.S
|
||||
; @brief Startup for GCC.
|
||||
; verbatim
|
||||
; Change Logs:
|
||||
; Date Author Notes
|
||||
; 2022-03-31 CDT First version
|
||||
; endverbatim
|
||||
; *****************************************************************************
|
||||
; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
; *
|
||||
; * This software component is licensed by XHSC under BSD 3-Clause license
|
||||
; * (the "License"); You may not use this file except in compliance with the
|
||||
; * License. You may obtain a copy of the License at:
|
||||
; * opensource.org/licenses/BSD-3-Clause
|
||||
; *
|
||||
; ******************************************************************************
|
||||
; */
|
||||
|
||||
/*
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.arch armv7e-m
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
/*
|
||||
;<h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
;</h>
|
||||
*/
|
||||
.equ Stack_Size, 0x00002000
|
||||
|
||||
.section .stack
|
||||
.align 3
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
|
||||
/*
|
||||
;<h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
;</h>
|
||||
*/
|
||||
.equ Heap_Size, 0x00002000
|
||||
|
||||
.if Heap_Size != 0 /* Heap is provided */
|
||||
.section .heap
|
||||
.align 3
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.space Heap_Size
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
.endif
|
||||
|
||||
/*
|
||||
;<h> Interrupt vector table start.
|
||||
*/
|
||||
.section .vectors, "a", %progbits
|
||||
.align 2
|
||||
.type __Vectors, %object
|
||||
.globl __Vectors
|
||||
.globl __Vectors_End
|
||||
.globl __Vectors_Size
|
||||
__Vectors:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* -14 NMI Handler */
|
||||
.long HardFault_Handler /* -13 Hard Fault Handler */
|
||||
.long MemManage_Handler /* -12 MPU Fault Handler */
|
||||
.long BusFault_Handler /* -11 Bus Fault Handler */
|
||||
.long UsageFault_Handler /* -10 Usage Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* -5 SVCall Handler */
|
||||
.long DebugMon_Handler /* -4 Debug Monitor Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* -2 PendSV Handler */
|
||||
.long SysTick_Handler /* -1 SysTick Handler */
|
||||
|
||||
/* Interrupts */
|
||||
.long IRQ000_Handler
|
||||
.long IRQ001_Handler
|
||||
.long IRQ002_Handler
|
||||
.long IRQ003_Handler
|
||||
.long IRQ004_Handler
|
||||
.long IRQ005_Handler
|
||||
.long IRQ006_Handler
|
||||
.long IRQ007_Handler
|
||||
.long IRQ008_Handler
|
||||
.long IRQ009_Handler
|
||||
.long IRQ010_Handler
|
||||
.long IRQ011_Handler
|
||||
.long IRQ012_Handler
|
||||
.long IRQ013_Handler
|
||||
.long IRQ014_Handler
|
||||
.long IRQ015_Handler
|
||||
.long IRQ016_Handler
|
||||
.long IRQ017_Handler
|
||||
.long IRQ018_Handler
|
||||
.long IRQ019_Handler
|
||||
.long IRQ020_Handler
|
||||
.long IRQ021_Handler
|
||||
.long IRQ022_Handler
|
||||
.long IRQ023_Handler
|
||||
.long IRQ024_Handler
|
||||
.long IRQ025_Handler
|
||||
.long IRQ026_Handler
|
||||
.long IRQ027_Handler
|
||||
.long IRQ028_Handler
|
||||
.long IRQ029_Handler
|
||||
.long IRQ030_Handler
|
||||
.long IRQ031_Handler
|
||||
.long IRQ032_Handler
|
||||
.long IRQ033_Handler
|
||||
.long IRQ034_Handler
|
||||
.long IRQ035_Handler
|
||||
.long IRQ036_Handler
|
||||
.long IRQ037_Handler
|
||||
.long IRQ038_Handler
|
||||
.long IRQ039_Handler
|
||||
.long IRQ040_Handler
|
||||
.long IRQ041_Handler
|
||||
.long IRQ042_Handler
|
||||
.long IRQ043_Handler
|
||||
.long IRQ044_Handler
|
||||
.long IRQ045_Handler
|
||||
.long IRQ046_Handler
|
||||
.long IRQ047_Handler
|
||||
.long IRQ048_Handler
|
||||
.long IRQ049_Handler
|
||||
.long IRQ050_Handler
|
||||
.long IRQ051_Handler
|
||||
.long IRQ052_Handler
|
||||
.long IRQ053_Handler
|
||||
.long IRQ054_Handler
|
||||
.long IRQ055_Handler
|
||||
.long IRQ056_Handler
|
||||
.long IRQ057_Handler
|
||||
.long IRQ058_Handler
|
||||
.long IRQ059_Handler
|
||||
.long IRQ060_Handler
|
||||
.long IRQ061_Handler
|
||||
.long IRQ062_Handler
|
||||
.long IRQ063_Handler
|
||||
.long IRQ064_Handler
|
||||
.long IRQ065_Handler
|
||||
.long IRQ066_Handler
|
||||
.long IRQ067_Handler
|
||||
.long IRQ068_Handler
|
||||
.long IRQ069_Handler
|
||||
.long IRQ070_Handler
|
||||
.long IRQ071_Handler
|
||||
.long IRQ072_Handler
|
||||
.long IRQ073_Handler
|
||||
.long IRQ074_Handler
|
||||
.long IRQ075_Handler
|
||||
.long IRQ076_Handler
|
||||
.long IRQ077_Handler
|
||||
.long IRQ078_Handler
|
||||
.long IRQ079_Handler
|
||||
.long IRQ080_Handler
|
||||
.long IRQ081_Handler
|
||||
.long IRQ082_Handler
|
||||
.long IRQ083_Handler
|
||||
.long IRQ084_Handler
|
||||
.long IRQ085_Handler
|
||||
.long IRQ086_Handler
|
||||
.long IRQ087_Handler
|
||||
.long IRQ088_Handler
|
||||
.long IRQ089_Handler
|
||||
.long IRQ090_Handler
|
||||
.long IRQ091_Handler
|
||||
.long IRQ092_Handler
|
||||
.long IRQ093_Handler
|
||||
.long IRQ094_Handler
|
||||
.long IRQ095_Handler
|
||||
.long IRQ096_Handler
|
||||
.long IRQ097_Handler
|
||||
.long IRQ098_Handler
|
||||
.long IRQ099_Handler
|
||||
.long IRQ100_Handler
|
||||
.long IRQ101_Handler
|
||||
.long IRQ102_Handler
|
||||
.long IRQ103_Handler
|
||||
.long IRQ104_Handler
|
||||
.long IRQ105_Handler
|
||||
.long IRQ106_Handler
|
||||
.long IRQ107_Handler
|
||||
.long IRQ108_Handler
|
||||
.long IRQ109_Handler
|
||||
.long IRQ110_Handler
|
||||
.long IRQ111_Handler
|
||||
.long IRQ112_Handler
|
||||
.long IRQ113_Handler
|
||||
.long IRQ114_Handler
|
||||
.long IRQ115_Handler
|
||||
.long IRQ116_Handler
|
||||
.long IRQ117_Handler
|
||||
.long IRQ118_Handler
|
||||
.long IRQ119_Handler
|
||||
.long IRQ120_Handler
|
||||
.long IRQ121_Handler
|
||||
.long IRQ122_Handler
|
||||
.long IRQ123_Handler
|
||||
.long IRQ124_Handler
|
||||
.long IRQ125_Handler
|
||||
.long IRQ126_Handler
|
||||
.long IRQ127_Handler
|
||||
.long IRQ128_Handler
|
||||
.long IRQ129_Handler
|
||||
.long IRQ130_Handler
|
||||
.long IRQ131_Handler
|
||||
.long IRQ132_Handler
|
||||
.long IRQ133_Handler
|
||||
.long IRQ134_Handler
|
||||
.long IRQ135_Handler
|
||||
.long IRQ136_Handler
|
||||
.long IRQ137_Handler
|
||||
.long IRQ138_Handler
|
||||
.long IRQ139_Handler
|
||||
.long IRQ140_Handler
|
||||
.long IRQ141_Handler
|
||||
.long IRQ142_Handler
|
||||
.long IRQ143_Handler
|
||||
__Vectors_End:
|
||||
.equ __Vectors_Size, __Vectors_End - __Vectors
|
||||
.size __Vectors, . - __Vectors
|
||||
/*
|
||||
;<h> Interrupt vector table end.
|
||||
*/
|
||||
|
||||
/*
|
||||
;<h> Reset handler start.
|
||||
*/
|
||||
.section .text.Reset_Handler
|
||||
.align 2
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
.globl Reset_Handler
|
||||
Reset_Handler:
|
||||
/* Single section scheme.
|
||||
*
|
||||
* The ranges of copy from/to are specified by following symbols
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to
|
||||
* __data_end__: VMA of end of the section to copy to
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
/* Copy data from read only memory to RAM. */
|
||||
CopyData:
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
CopyLoop:
|
||||
cmp r2, r3
|
||||
ittt lt
|
||||
ldrlt r0, [r1], #4
|
||||
strlt r0, [r2], #4
|
||||
blt CopyLoop
|
||||
|
||||
CopyData1:
|
||||
ldr r1, =__etext_ret_ram
|
||||
ldr r2, =__data_start_ret_ram__
|
||||
ldr r3, =__data_end_ret_ram__
|
||||
CopyLoop1:
|
||||
cmp r2, r3
|
||||
ittt lt
|
||||
ldrlt r0, [r1], #4
|
||||
strlt r0, [r2], #4
|
||||
blt CopyLoop1
|
||||
|
||||
/* This part of work usually is done in C library startup code.
|
||||
* Otherwise, define this macro to enable it in this startup.
|
||||
*
|
||||
* There are two schemes too.
|
||||
* One can clear multiple BSS sections. Another can only clear one section.
|
||||
* The former is more size expensive than the latter.
|
||||
*
|
||||
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
|
||||
* Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
|
||||
*/
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
/* Clear BSS section. */
|
||||
ClearBss:
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
ClearLoop:
|
||||
cmp r1, r2
|
||||
itt lt
|
||||
strlt r0, [r1], #4
|
||||
blt ClearLoop
|
||||
|
||||
ClearBss1:
|
||||
ldr r1, =__bss_start_ret_ram__
|
||||
ldr r2, =__bss_end_ret_ram__
|
||||
|
||||
movs r0, 0
|
||||
ClearLoop1:
|
||||
cmp r1, r2
|
||||
itt lt
|
||||
strlt r0, [r1], #4
|
||||
blt ClearLoop1
|
||||
|
||||
SetSRAM3Wait:
|
||||
ldr r0, =0x40050804
|
||||
mov r1, #0x77
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =0x4005080C
|
||||
mov r1, #0x77
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =0x40050800
|
||||
mov r1, #0x1100
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =0x40050804
|
||||
mov r1, #0x76
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =0x4005080C
|
||||
mov r1, #0x76
|
||||
str r1, [r0]
|
||||
|
||||
/* Call the clock system initialization function. */
|
||||
bl SystemInit
|
||||
/* Call the application's entry point. */
|
||||
bl main
|
||||
bx lr
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
/*
|
||||
;<h> Reset handler end.
|
||||
*/
|
||||
|
||||
/*
|
||||
;<h> Default handler start.
|
||||
*/
|
||||
.section .text.Default_Handler, "ax", %progbits
|
||||
.align 2
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
/*
|
||||
;<h> Default handler end.
|
||||
*/
|
||||
|
||||
/* Macro to define default exception/interrupt handlers.
|
||||
* Default handler are weak symbols with an endless loop.
|
||||
* They can be overwritten by real handlers.
|
||||
*/
|
||||
.macro Set_Default_Handler Handler_Name
|
||||
.weak \Handler_Name
|
||||
.set \Handler_Name, Default_Handler
|
||||
.endm
|
||||
|
||||
/* Default exception/interrupt handler */
|
||||
|
||||
Set_Default_Handler NMI_Handler
|
||||
Set_Default_Handler HardFault_Handler
|
||||
Set_Default_Handler MemManage_Handler
|
||||
Set_Default_Handler BusFault_Handler
|
||||
Set_Default_Handler UsageFault_Handler
|
||||
Set_Default_Handler SVC_Handler
|
||||
Set_Default_Handler DebugMon_Handler
|
||||
Set_Default_Handler PendSV_Handler
|
||||
Set_Default_Handler SysTick_Handler
|
||||
|
||||
Set_Default_Handler IRQ000_Handler
|
||||
Set_Default_Handler IRQ001_Handler
|
||||
Set_Default_Handler IRQ002_Handler
|
||||
Set_Default_Handler IRQ003_Handler
|
||||
Set_Default_Handler IRQ004_Handler
|
||||
Set_Default_Handler IRQ005_Handler
|
||||
Set_Default_Handler IRQ006_Handler
|
||||
Set_Default_Handler IRQ007_Handler
|
||||
Set_Default_Handler IRQ008_Handler
|
||||
Set_Default_Handler IRQ009_Handler
|
||||
Set_Default_Handler IRQ010_Handler
|
||||
Set_Default_Handler IRQ011_Handler
|
||||
Set_Default_Handler IRQ012_Handler
|
||||
Set_Default_Handler IRQ013_Handler
|
||||
Set_Default_Handler IRQ014_Handler
|
||||
Set_Default_Handler IRQ015_Handler
|
||||
Set_Default_Handler IRQ016_Handler
|
||||
Set_Default_Handler IRQ017_Handler
|
||||
Set_Default_Handler IRQ018_Handler
|
||||
Set_Default_Handler IRQ019_Handler
|
||||
Set_Default_Handler IRQ020_Handler
|
||||
Set_Default_Handler IRQ021_Handler
|
||||
Set_Default_Handler IRQ022_Handler
|
||||
Set_Default_Handler IRQ023_Handler
|
||||
Set_Default_Handler IRQ024_Handler
|
||||
Set_Default_Handler IRQ025_Handler
|
||||
Set_Default_Handler IRQ026_Handler
|
||||
Set_Default_Handler IRQ027_Handler
|
||||
Set_Default_Handler IRQ028_Handler
|
||||
Set_Default_Handler IRQ029_Handler
|
||||
Set_Default_Handler IRQ030_Handler
|
||||
Set_Default_Handler IRQ031_Handler
|
||||
Set_Default_Handler IRQ032_Handler
|
||||
Set_Default_Handler IRQ033_Handler
|
||||
Set_Default_Handler IRQ034_Handler
|
||||
Set_Default_Handler IRQ035_Handler
|
||||
Set_Default_Handler IRQ036_Handler
|
||||
Set_Default_Handler IRQ037_Handler
|
||||
Set_Default_Handler IRQ038_Handler
|
||||
Set_Default_Handler IRQ039_Handler
|
||||
Set_Default_Handler IRQ040_Handler
|
||||
Set_Default_Handler IRQ041_Handler
|
||||
Set_Default_Handler IRQ042_Handler
|
||||
Set_Default_Handler IRQ043_Handler
|
||||
Set_Default_Handler IRQ044_Handler
|
||||
Set_Default_Handler IRQ045_Handler
|
||||
Set_Default_Handler IRQ046_Handler
|
||||
Set_Default_Handler IRQ047_Handler
|
||||
Set_Default_Handler IRQ048_Handler
|
||||
Set_Default_Handler IRQ049_Handler
|
||||
Set_Default_Handler IRQ050_Handler
|
||||
Set_Default_Handler IRQ051_Handler
|
||||
Set_Default_Handler IRQ052_Handler
|
||||
Set_Default_Handler IRQ053_Handler
|
||||
Set_Default_Handler IRQ054_Handler
|
||||
Set_Default_Handler IRQ055_Handler
|
||||
Set_Default_Handler IRQ056_Handler
|
||||
Set_Default_Handler IRQ057_Handler
|
||||
Set_Default_Handler IRQ058_Handler
|
||||
Set_Default_Handler IRQ059_Handler
|
||||
Set_Default_Handler IRQ060_Handler
|
||||
Set_Default_Handler IRQ061_Handler
|
||||
Set_Default_Handler IRQ062_Handler
|
||||
Set_Default_Handler IRQ063_Handler
|
||||
Set_Default_Handler IRQ064_Handler
|
||||
Set_Default_Handler IRQ065_Handler
|
||||
Set_Default_Handler IRQ066_Handler
|
||||
Set_Default_Handler IRQ067_Handler
|
||||
Set_Default_Handler IRQ068_Handler
|
||||
Set_Default_Handler IRQ069_Handler
|
||||
Set_Default_Handler IRQ070_Handler
|
||||
Set_Default_Handler IRQ071_Handler
|
||||
Set_Default_Handler IRQ072_Handler
|
||||
Set_Default_Handler IRQ073_Handler
|
||||
Set_Default_Handler IRQ074_Handler
|
||||
Set_Default_Handler IRQ075_Handler
|
||||
Set_Default_Handler IRQ076_Handler
|
||||
Set_Default_Handler IRQ077_Handler
|
||||
Set_Default_Handler IRQ078_Handler
|
||||
Set_Default_Handler IRQ079_Handler
|
||||
Set_Default_Handler IRQ080_Handler
|
||||
Set_Default_Handler IRQ081_Handler
|
||||
Set_Default_Handler IRQ082_Handler
|
||||
Set_Default_Handler IRQ083_Handler
|
||||
Set_Default_Handler IRQ084_Handler
|
||||
Set_Default_Handler IRQ085_Handler
|
||||
Set_Default_Handler IRQ086_Handler
|
||||
Set_Default_Handler IRQ087_Handler
|
||||
Set_Default_Handler IRQ088_Handler
|
||||
Set_Default_Handler IRQ089_Handler
|
||||
Set_Default_Handler IRQ090_Handler
|
||||
Set_Default_Handler IRQ091_Handler
|
||||
Set_Default_Handler IRQ092_Handler
|
||||
Set_Default_Handler IRQ093_Handler
|
||||
Set_Default_Handler IRQ094_Handler
|
||||
Set_Default_Handler IRQ095_Handler
|
||||
Set_Default_Handler IRQ096_Handler
|
||||
Set_Default_Handler IRQ097_Handler
|
||||
Set_Default_Handler IRQ098_Handler
|
||||
Set_Default_Handler IRQ099_Handler
|
||||
Set_Default_Handler IRQ100_Handler
|
||||
Set_Default_Handler IRQ101_Handler
|
||||
Set_Default_Handler IRQ102_Handler
|
||||
Set_Default_Handler IRQ103_Handler
|
||||
Set_Default_Handler IRQ104_Handler
|
||||
Set_Default_Handler IRQ105_Handler
|
||||
Set_Default_Handler IRQ106_Handler
|
||||
Set_Default_Handler IRQ107_Handler
|
||||
Set_Default_Handler IRQ108_Handler
|
||||
Set_Default_Handler IRQ109_Handler
|
||||
Set_Default_Handler IRQ110_Handler
|
||||
Set_Default_Handler IRQ111_Handler
|
||||
Set_Default_Handler IRQ112_Handler
|
||||
Set_Default_Handler IRQ113_Handler
|
||||
Set_Default_Handler IRQ114_Handler
|
||||
Set_Default_Handler IRQ115_Handler
|
||||
Set_Default_Handler IRQ116_Handler
|
||||
Set_Default_Handler IRQ117_Handler
|
||||
Set_Default_Handler IRQ118_Handler
|
||||
Set_Default_Handler IRQ119_Handler
|
||||
Set_Default_Handler IRQ120_Handler
|
||||
Set_Default_Handler IRQ121_Handler
|
||||
Set_Default_Handler IRQ122_Handler
|
||||
Set_Default_Handler IRQ123_Handler
|
||||
Set_Default_Handler IRQ124_Handler
|
||||
Set_Default_Handler IRQ125_Handler
|
||||
Set_Default_Handler IRQ126_Handler
|
||||
Set_Default_Handler IRQ127_Handler
|
||||
Set_Default_Handler IRQ128_Handler
|
||||
Set_Default_Handler IRQ129_Handler
|
||||
Set_Default_Handler IRQ130_Handler
|
||||
Set_Default_Handler IRQ131_Handler
|
||||
Set_Default_Handler IRQ132_Handler
|
||||
Set_Default_Handler IRQ133_Handler
|
||||
Set_Default_Handler IRQ134_Handler
|
||||
Set_Default_Handler IRQ135_Handler
|
||||
Set_Default_Handler IRQ136_Handler
|
||||
Set_Default_Handler IRQ137_Handler
|
||||
Set_Default_Handler IRQ138_Handler
|
||||
Set_Default_Handler IRQ139_Handler
|
||||
Set_Default_Handler IRQ140_Handler
|
||||
Set_Default_Handler IRQ141_Handler
|
||||
Set_Default_Handler IRQ142_Handler
|
||||
Set_Default_Handler IRQ143_Handler
|
||||
|
||||
.end
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,16 @@
|
||||
setup()
|
||||
{
|
||||
;
|
||||
}
|
||||
|
||||
execUserPreload()
|
||||
{
|
||||
__message "----- Prepare hardware for Flashloader -----\n";
|
||||
setup();
|
||||
}
|
||||
execUserFlashInit() // Called by debugger before loading flash loader in RAM.
|
||||
{
|
||||
__message "----- Prepare hardware for Flashloader -----\n";
|
||||
setup();
|
||||
}
|
||||
|
||||
@@ -0,0 +1,16 @@
|
||||
setup()
|
||||
{
|
||||
;
|
||||
}
|
||||
|
||||
execUserPreload()
|
||||
{
|
||||
__message "----- Prepare hardware for Flashloader -----\n";
|
||||
setup();
|
||||
}
|
||||
execUserFlashInit() // Called by debugger before loading flash loader in RAM.
|
||||
{
|
||||
__message "----- Prepare hardware for Flashloader -----\n";
|
||||
setup();
|
||||
}
|
||||
|
||||
@@ -0,0 +1,56 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x1FFF8000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_IROM1_start__ = 0x1FFF8000;
|
||||
define symbol __ICFEDIT_region_IROM1_end__ = 0x1FFFFFFF;
|
||||
define symbol __ICFEDIT_region_IROM2_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_IROM2_end__ = 0x2001FFFF;
|
||||
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM1_start__ = 0x20020000;
|
||||
define symbol __ICFEDIT_region_IRAM1_end__ = 0x20026FFF;
|
||||
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
|
||||
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
|
||||
define symbol __ICFEDIT_region_IRAM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM3_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM4_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM4_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM5_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM5_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x100;
|
||||
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x100;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@@ -0,0 +1,50 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_IROM1_end__ = 0x0003FFFF;
|
||||
define symbol __ICFEDIT_region_IROM2_start__ = 0x03000C00;
|
||||
define symbol __ICFEDIT_region_IROM2_end__ = 0x03000FFB;
|
||||
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFF8000;
|
||||
define symbol __ICFEDIT_region_IRAM1_end__ = 0x20026FFF;
|
||||
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
|
||||
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
|
||||
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x400;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@@ -0,0 +1,50 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_IROM1_end__ = 0x0007FFFF;
|
||||
define symbol __ICFEDIT_region_IROM2_start__ = 0x03000C00;
|
||||
define symbol __ICFEDIT_region_IROM2_end__ = 0x03000FFB;
|
||||
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFF8000;
|
||||
define symbol __ICFEDIT_region_IRAM1_end__ = 0x20026FFF;
|
||||
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
|
||||
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
|
||||
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x400;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@@ -0,0 +1,995 @@
|
||||
;/**
|
||||
; ******************************************************************************
|
||||
; @file startup_hc32f460.s
|
||||
; @brief Startup for IAR.
|
||||
; verbatim
|
||||
; Change Logs:
|
||||
; Date Author Notes
|
||||
; 2022-03-31 CDT First version
|
||||
; endverbatim
|
||||
; *****************************************************************************
|
||||
; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
; *
|
||||
; * This software component is licensed by XHSC under BSD 3-Clause license
|
||||
; * (the "License"); You may not use this file except in compliance with the
|
||||
; * License. You may obtain a copy of the License at:
|
||||
; * opensource.org/licenses/BSD-3-Clause
|
||||
; *
|
||||
; ******************************************************************************
|
||||
; */
|
||||
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; Peripheral Interrupts
|
||||
DCD IRQ000_Handler
|
||||
DCD IRQ001_Handler
|
||||
DCD IRQ002_Handler
|
||||
DCD IRQ003_Handler
|
||||
DCD IRQ004_Handler
|
||||
DCD IRQ005_Handler
|
||||
DCD IRQ006_Handler
|
||||
DCD IRQ007_Handler
|
||||
DCD IRQ008_Handler
|
||||
DCD IRQ009_Handler
|
||||
DCD IRQ010_Handler
|
||||
DCD IRQ011_Handler
|
||||
DCD IRQ012_Handler
|
||||
DCD IRQ013_Handler
|
||||
DCD IRQ014_Handler
|
||||
DCD IRQ015_Handler
|
||||
DCD IRQ016_Handler
|
||||
DCD IRQ017_Handler
|
||||
DCD IRQ018_Handler
|
||||
DCD IRQ019_Handler
|
||||
DCD IRQ020_Handler
|
||||
DCD IRQ021_Handler
|
||||
DCD IRQ022_Handler
|
||||
DCD IRQ023_Handler
|
||||
DCD IRQ024_Handler
|
||||
DCD IRQ025_Handler
|
||||
DCD IRQ026_Handler
|
||||
DCD IRQ027_Handler
|
||||
DCD IRQ028_Handler
|
||||
DCD IRQ029_Handler
|
||||
DCD IRQ030_Handler
|
||||
DCD IRQ031_Handler
|
||||
DCD IRQ032_Handler
|
||||
DCD IRQ033_Handler
|
||||
DCD IRQ034_Handler
|
||||
DCD IRQ035_Handler
|
||||
DCD IRQ036_Handler
|
||||
DCD IRQ037_Handler
|
||||
DCD IRQ038_Handler
|
||||
DCD IRQ039_Handler
|
||||
DCD IRQ040_Handler
|
||||
DCD IRQ041_Handler
|
||||
DCD IRQ042_Handler
|
||||
DCD IRQ043_Handler
|
||||
DCD IRQ044_Handler
|
||||
DCD IRQ045_Handler
|
||||
DCD IRQ046_Handler
|
||||
DCD IRQ047_Handler
|
||||
DCD IRQ048_Handler
|
||||
DCD IRQ049_Handler
|
||||
DCD IRQ050_Handler
|
||||
DCD IRQ051_Handler
|
||||
DCD IRQ052_Handler
|
||||
DCD IRQ053_Handler
|
||||
DCD IRQ054_Handler
|
||||
DCD IRQ055_Handler
|
||||
DCD IRQ056_Handler
|
||||
DCD IRQ057_Handler
|
||||
DCD IRQ058_Handler
|
||||
DCD IRQ059_Handler
|
||||
DCD IRQ060_Handler
|
||||
DCD IRQ061_Handler
|
||||
DCD IRQ062_Handler
|
||||
DCD IRQ063_Handler
|
||||
DCD IRQ064_Handler
|
||||
DCD IRQ065_Handler
|
||||
DCD IRQ066_Handler
|
||||
DCD IRQ067_Handler
|
||||
DCD IRQ068_Handler
|
||||
DCD IRQ069_Handler
|
||||
DCD IRQ070_Handler
|
||||
DCD IRQ071_Handler
|
||||
DCD IRQ072_Handler
|
||||
DCD IRQ073_Handler
|
||||
DCD IRQ074_Handler
|
||||
DCD IRQ075_Handler
|
||||
DCD IRQ076_Handler
|
||||
DCD IRQ077_Handler
|
||||
DCD IRQ078_Handler
|
||||
DCD IRQ079_Handler
|
||||
DCD IRQ080_Handler
|
||||
DCD IRQ081_Handler
|
||||
DCD IRQ082_Handler
|
||||
DCD IRQ083_Handler
|
||||
DCD IRQ084_Handler
|
||||
DCD IRQ085_Handler
|
||||
DCD IRQ086_Handler
|
||||
DCD IRQ087_Handler
|
||||
DCD IRQ088_Handler
|
||||
DCD IRQ089_Handler
|
||||
DCD IRQ090_Handler
|
||||
DCD IRQ091_Handler
|
||||
DCD IRQ092_Handler
|
||||
DCD IRQ093_Handler
|
||||
DCD IRQ094_Handler
|
||||
DCD IRQ095_Handler
|
||||
DCD IRQ096_Handler
|
||||
DCD IRQ097_Handler
|
||||
DCD IRQ098_Handler
|
||||
DCD IRQ099_Handler
|
||||
DCD IRQ100_Handler
|
||||
DCD IRQ101_Handler
|
||||
DCD IRQ102_Handler
|
||||
DCD IRQ103_Handler
|
||||
DCD IRQ104_Handler
|
||||
DCD IRQ105_Handler
|
||||
DCD IRQ106_Handler
|
||||
DCD IRQ107_Handler
|
||||
DCD IRQ108_Handler
|
||||
DCD IRQ109_Handler
|
||||
DCD IRQ110_Handler
|
||||
DCD IRQ111_Handler
|
||||
DCD IRQ112_Handler
|
||||
DCD IRQ113_Handler
|
||||
DCD IRQ114_Handler
|
||||
DCD IRQ115_Handler
|
||||
DCD IRQ116_Handler
|
||||
DCD IRQ117_Handler
|
||||
DCD IRQ118_Handler
|
||||
DCD IRQ119_Handler
|
||||
DCD IRQ120_Handler
|
||||
DCD IRQ121_Handler
|
||||
DCD IRQ122_Handler
|
||||
DCD IRQ123_Handler
|
||||
DCD IRQ124_Handler
|
||||
DCD IRQ125_Handler
|
||||
DCD IRQ126_Handler
|
||||
DCD IRQ127_Handler
|
||||
DCD IRQ128_Handler
|
||||
DCD IRQ129_Handler
|
||||
DCD IRQ130_Handler
|
||||
DCD IRQ131_Handler
|
||||
DCD IRQ132_Handler
|
||||
DCD IRQ133_Handler
|
||||
DCD IRQ134_Handler
|
||||
DCD IRQ135_Handler
|
||||
DCD IRQ136_Handler
|
||||
DCD IRQ137_Handler
|
||||
DCD IRQ138_Handler
|
||||
DCD IRQ139_Handler
|
||||
DCD IRQ140_Handler
|
||||
DCD IRQ141_Handler
|
||||
DCD IRQ142_Handler
|
||||
DCD IRQ143_Handler
|
||||
|
||||
THUMB
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
;SetSRAM3Wait
|
||||
LDR R0, =0x40050804
|
||||
MOV R1, #0x77
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =0x4005080C
|
||||
MOV R1, #0x77
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =0x40050800
|
||||
MOV R1, #0x1100
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =0x40050804
|
||||
MOV R1, #0x76
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =0x4005080C
|
||||
MOV R1, #0x76
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK IRQ000_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ000_Handler
|
||||
B IRQ000_Handler
|
||||
|
||||
PUBWEAK IRQ001_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ001_Handler
|
||||
B IRQ001_Handler
|
||||
|
||||
PUBWEAK IRQ002_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ002_Handler
|
||||
B IRQ002_Handler
|
||||
|
||||
PUBWEAK IRQ003_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ003_Handler
|
||||
B IRQ003_Handler
|
||||
|
||||
PUBWEAK IRQ004_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ004_Handler
|
||||
B IRQ004_Handler
|
||||
|
||||
PUBWEAK IRQ005_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ005_Handler
|
||||
B IRQ005_Handler
|
||||
|
||||
PUBWEAK IRQ006_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ006_Handler
|
||||
B IRQ006_Handler
|
||||
|
||||
PUBWEAK IRQ007_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ007_Handler
|
||||
B IRQ007_Handler
|
||||
|
||||
PUBWEAK IRQ008_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ008_Handler
|
||||
B IRQ008_Handler
|
||||
|
||||
PUBWEAK IRQ009_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ009_Handler
|
||||
B IRQ009_Handler
|
||||
|
||||
PUBWEAK IRQ010_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ010_Handler
|
||||
B IRQ010_Handler
|
||||
|
||||
PUBWEAK IRQ011_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ011_Handler
|
||||
B IRQ011_Handler
|
||||
|
||||
PUBWEAK IRQ012_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ012_Handler
|
||||
B IRQ012_Handler
|
||||
|
||||
PUBWEAK IRQ013_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ013_Handler
|
||||
B IRQ013_Handler
|
||||
|
||||
PUBWEAK IRQ014_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ014_Handler
|
||||
B IRQ014_Handler
|
||||
|
||||
PUBWEAK IRQ015_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ015_Handler
|
||||
B IRQ015_Handler
|
||||
|
||||
PUBWEAK IRQ016_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ016_Handler
|
||||
B IRQ016_Handler
|
||||
|
||||
PUBWEAK IRQ017_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ017_Handler
|
||||
B IRQ017_Handler
|
||||
|
||||
PUBWEAK IRQ018_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ018_Handler
|
||||
B IRQ018_Handler
|
||||
|
||||
PUBWEAK IRQ019_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ019_Handler
|
||||
B IRQ019_Handler
|
||||
|
||||
PUBWEAK IRQ020_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ020_Handler
|
||||
B IRQ020_Handler
|
||||
|
||||
PUBWEAK IRQ021_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ021_Handler
|
||||
B IRQ021_Handler
|
||||
|
||||
PUBWEAK IRQ022_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ022_Handler
|
||||
B IRQ022_Handler
|
||||
|
||||
PUBWEAK IRQ023_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ023_Handler
|
||||
B IRQ023_Handler
|
||||
|
||||
PUBWEAK IRQ024_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ024_Handler
|
||||
B IRQ024_Handler
|
||||
|
||||
PUBWEAK IRQ025_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ025_Handler
|
||||
B IRQ025_Handler
|
||||
|
||||
PUBWEAK IRQ026_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ026_Handler
|
||||
B IRQ026_Handler
|
||||
|
||||
PUBWEAK IRQ027_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ027_Handler
|
||||
B IRQ027_Handler
|
||||
|
||||
PUBWEAK IRQ028_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ028_Handler
|
||||
B IRQ028_Handler
|
||||
|
||||
PUBWEAK IRQ029_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ029_Handler
|
||||
B IRQ029_Handler
|
||||
|
||||
PUBWEAK IRQ030_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ030_Handler
|
||||
B IRQ030_Handler
|
||||
|
||||
PUBWEAK IRQ031_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ031_Handler
|
||||
B IRQ031_Handler
|
||||
|
||||
PUBWEAK IRQ032_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ032_Handler
|
||||
B IRQ032_Handler
|
||||
|
||||
PUBWEAK IRQ033_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ033_Handler
|
||||
B IRQ033_Handler
|
||||
|
||||
PUBWEAK IRQ034_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ034_Handler
|
||||
B IRQ034_Handler
|
||||
|
||||
PUBWEAK IRQ035_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ035_Handler
|
||||
B IRQ035_Handler
|
||||
|
||||
PUBWEAK IRQ036_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ036_Handler
|
||||
B IRQ036_Handler
|
||||
|
||||
PUBWEAK IRQ037_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ037_Handler
|
||||
B IRQ037_Handler
|
||||
|
||||
PUBWEAK IRQ038_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ038_Handler
|
||||
B IRQ038_Handler
|
||||
|
||||
PUBWEAK IRQ039_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ039_Handler
|
||||
B IRQ039_Handler
|
||||
|
||||
PUBWEAK IRQ040_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ040_Handler
|
||||
B IRQ040_Handler
|
||||
|
||||
PUBWEAK IRQ041_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ041_Handler
|
||||
B IRQ041_Handler
|
||||
|
||||
PUBWEAK IRQ042_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ042_Handler
|
||||
B IRQ042_Handler
|
||||
|
||||
PUBWEAK IRQ043_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ043_Handler
|
||||
B IRQ043_Handler
|
||||
|
||||
PUBWEAK IRQ044_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ044_Handler
|
||||
B IRQ044_Handler
|
||||
|
||||
PUBWEAK IRQ045_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ045_Handler
|
||||
B IRQ045_Handler
|
||||
|
||||
PUBWEAK IRQ046_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ046_Handler
|
||||
B IRQ046_Handler
|
||||
|
||||
PUBWEAK IRQ047_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ047_Handler
|
||||
B IRQ047_Handler
|
||||
|
||||
PUBWEAK IRQ048_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ048_Handler
|
||||
B IRQ048_Handler
|
||||
|
||||
PUBWEAK IRQ049_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ049_Handler
|
||||
B IRQ049_Handler
|
||||
|
||||
PUBWEAK IRQ050_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ050_Handler
|
||||
B IRQ050_Handler
|
||||
|
||||
PUBWEAK IRQ051_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ051_Handler
|
||||
B IRQ051_Handler
|
||||
|
||||
PUBWEAK IRQ052_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ052_Handler
|
||||
B IRQ052_Handler
|
||||
|
||||
PUBWEAK IRQ053_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ053_Handler
|
||||
B IRQ053_Handler
|
||||
|
||||
PUBWEAK IRQ054_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ054_Handler
|
||||
B IRQ054_Handler
|
||||
|
||||
PUBWEAK IRQ055_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ055_Handler
|
||||
B IRQ055_Handler
|
||||
|
||||
PUBWEAK IRQ056_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ056_Handler
|
||||
B IRQ056_Handler
|
||||
|
||||
PUBWEAK IRQ057_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ057_Handler
|
||||
B IRQ057_Handler
|
||||
|
||||
PUBWEAK IRQ058_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ058_Handler
|
||||
B IRQ058_Handler
|
||||
|
||||
PUBWEAK IRQ059_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ059_Handler
|
||||
B IRQ059_Handler
|
||||
|
||||
PUBWEAK IRQ060_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ060_Handler
|
||||
B IRQ060_Handler
|
||||
|
||||
PUBWEAK IRQ061_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ061_Handler
|
||||
B IRQ061_Handler
|
||||
|
||||
PUBWEAK IRQ062_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ062_Handler
|
||||
B IRQ062_Handler
|
||||
|
||||
PUBWEAK IRQ063_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ063_Handler
|
||||
B IRQ063_Handler
|
||||
|
||||
PUBWEAK IRQ064_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ064_Handler
|
||||
B IRQ064_Handler
|
||||
|
||||
PUBWEAK IRQ065_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ065_Handler
|
||||
B IRQ065_Handler
|
||||
|
||||
PUBWEAK IRQ066_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ066_Handler
|
||||
B IRQ066_Handler
|
||||
|
||||
PUBWEAK IRQ067_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ067_Handler
|
||||
B IRQ067_Handler
|
||||
|
||||
PUBWEAK IRQ068_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ068_Handler
|
||||
B IRQ068_Handler
|
||||
|
||||
PUBWEAK IRQ069_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ069_Handler
|
||||
B IRQ069_Handler
|
||||
|
||||
PUBWEAK IRQ070_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ070_Handler
|
||||
B IRQ070_Handler
|
||||
|
||||
PUBWEAK IRQ071_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ071_Handler
|
||||
B IRQ071_Handler
|
||||
|
||||
PUBWEAK IRQ072_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ072_Handler
|
||||
B IRQ072_Handler
|
||||
|
||||
PUBWEAK IRQ073_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ073_Handler
|
||||
B IRQ073_Handler
|
||||
|
||||
PUBWEAK IRQ074_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ074_Handler
|
||||
B IRQ074_Handler
|
||||
|
||||
PUBWEAK IRQ075_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ075_Handler
|
||||
B IRQ075_Handler
|
||||
|
||||
PUBWEAK IRQ076_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ076_Handler
|
||||
B IRQ076_Handler
|
||||
|
||||
PUBWEAK IRQ077_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ077_Handler
|
||||
B IRQ077_Handler
|
||||
|
||||
PUBWEAK IRQ078_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ078_Handler
|
||||
B IRQ078_Handler
|
||||
|
||||
PUBWEAK IRQ079_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ079_Handler
|
||||
B IRQ079_Handler
|
||||
|
||||
PUBWEAK IRQ080_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ080_Handler
|
||||
B IRQ080_Handler
|
||||
|
||||
PUBWEAK IRQ081_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ081_Handler
|
||||
B IRQ081_Handler
|
||||
|
||||
PUBWEAK IRQ082_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ082_Handler
|
||||
B IRQ082_Handler
|
||||
|
||||
PUBWEAK IRQ083_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ083_Handler
|
||||
B IRQ083_Handler
|
||||
|
||||
PUBWEAK IRQ084_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ084_Handler
|
||||
B IRQ084_Handler
|
||||
|
||||
PUBWEAK IRQ085_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ085_Handler
|
||||
B IRQ085_Handler
|
||||
|
||||
PUBWEAK IRQ086_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ086_Handler
|
||||
B IRQ086_Handler
|
||||
|
||||
PUBWEAK IRQ087_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ087_Handler
|
||||
B IRQ087_Handler
|
||||
|
||||
PUBWEAK IRQ088_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ088_Handler
|
||||
B IRQ088_Handler
|
||||
|
||||
PUBWEAK IRQ089_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ089_Handler
|
||||
B IRQ089_Handler
|
||||
|
||||
PUBWEAK IRQ090_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ090_Handler
|
||||
B IRQ090_Handler
|
||||
|
||||
PUBWEAK IRQ091_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ091_Handler
|
||||
B IRQ091_Handler
|
||||
|
||||
PUBWEAK IRQ092_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ092_Handler
|
||||
B IRQ092_Handler
|
||||
|
||||
PUBWEAK IRQ093_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ093_Handler
|
||||
B IRQ093_Handler
|
||||
|
||||
PUBWEAK IRQ094_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ094_Handler
|
||||
B IRQ094_Handler
|
||||
|
||||
PUBWEAK IRQ095_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ095_Handler
|
||||
B IRQ095_Handler
|
||||
|
||||
PUBWEAK IRQ096_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ096_Handler
|
||||
B IRQ096_Handler
|
||||
|
||||
PUBWEAK IRQ097_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ097_Handler
|
||||
B IRQ097_Handler
|
||||
|
||||
PUBWEAK IRQ098_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ098_Handler
|
||||
B IRQ098_Handler
|
||||
|
||||
PUBWEAK IRQ099_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ099_Handler
|
||||
B IRQ099_Handler
|
||||
|
||||
PUBWEAK IRQ100_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ100_Handler
|
||||
B IRQ100_Handler
|
||||
|
||||
PUBWEAK IRQ101_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ101_Handler
|
||||
B IRQ101_Handler
|
||||
|
||||
PUBWEAK IRQ102_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ102_Handler
|
||||
B IRQ102_Handler
|
||||
|
||||
PUBWEAK IRQ103_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ103_Handler
|
||||
B IRQ103_Handler
|
||||
|
||||
PUBWEAK IRQ104_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ104_Handler
|
||||
B IRQ104_Handler
|
||||
|
||||
PUBWEAK IRQ105_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ105_Handler
|
||||
B IRQ105_Handler
|
||||
|
||||
PUBWEAK IRQ106_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ106_Handler
|
||||
B IRQ106_Handler
|
||||
|
||||
PUBWEAK IRQ107_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ107_Handler
|
||||
B IRQ107_Handler
|
||||
|
||||
PUBWEAK IRQ108_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ108_Handler
|
||||
B IRQ108_Handler
|
||||
|
||||
PUBWEAK IRQ109_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ109_Handler
|
||||
B IRQ109_Handler
|
||||
|
||||
PUBWEAK IRQ110_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ110_Handler
|
||||
B IRQ110_Handler
|
||||
|
||||
PUBWEAK IRQ111_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ111_Handler
|
||||
B IRQ111_Handler
|
||||
|
||||
PUBWEAK IRQ112_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ112_Handler
|
||||
B IRQ112_Handler
|
||||
|
||||
PUBWEAK IRQ113_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ113_Handler
|
||||
B IRQ113_Handler
|
||||
|
||||
PUBWEAK IRQ114_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ114_Handler
|
||||
B IRQ114_Handler
|
||||
|
||||
PUBWEAK IRQ115_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ115_Handler
|
||||
B IRQ115_Handler
|
||||
|
||||
PUBWEAK IRQ116_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ116_Handler
|
||||
B IRQ116_Handler
|
||||
|
||||
PUBWEAK IRQ117_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ117_Handler
|
||||
B IRQ117_Handler
|
||||
|
||||
PUBWEAK IRQ118_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ118_Handler
|
||||
B IRQ118_Handler
|
||||
|
||||
PUBWEAK IRQ119_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ119_Handler
|
||||
B IRQ119_Handler
|
||||
|
||||
PUBWEAK IRQ120_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ120_Handler
|
||||
B IRQ120_Handler
|
||||
|
||||
PUBWEAK IRQ121_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ121_Handler
|
||||
B IRQ121_Handler
|
||||
|
||||
PUBWEAK IRQ122_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ122_Handler
|
||||
B IRQ122_Handler
|
||||
|
||||
PUBWEAK IRQ123_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ123_Handler
|
||||
B IRQ123_Handler
|
||||
|
||||
PUBWEAK IRQ124_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ124_Handler
|
||||
B IRQ124_Handler
|
||||
|
||||
PUBWEAK IRQ125_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ125_Handler
|
||||
B IRQ125_Handler
|
||||
|
||||
PUBWEAK IRQ126_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ126_Handler
|
||||
B IRQ126_Handler
|
||||
|
||||
PUBWEAK IRQ127_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ127_Handler
|
||||
B IRQ127_Handler
|
||||
|
||||
PUBWEAK IRQ128_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ128_Handler
|
||||
B IRQ128_Handler
|
||||
|
||||
PUBWEAK IRQ129_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ129_Handler
|
||||
B IRQ129_Handler
|
||||
|
||||
PUBWEAK IRQ130_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ130_Handler
|
||||
B IRQ130_Handler
|
||||
|
||||
PUBWEAK IRQ131_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ131_Handler
|
||||
B IRQ131_Handler
|
||||
|
||||
PUBWEAK IRQ132_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ132_Handler
|
||||
B IRQ132_Handler
|
||||
|
||||
PUBWEAK IRQ133_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ133_Handler
|
||||
B IRQ133_Handler
|
||||
|
||||
PUBWEAK IRQ134_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ134_Handler
|
||||
B IRQ134_Handler
|
||||
|
||||
PUBWEAK IRQ135_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ135_Handler
|
||||
B IRQ135_Handler
|
||||
|
||||
PUBWEAK IRQ136_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ136_Handler
|
||||
B IRQ136_Handler
|
||||
|
||||
PUBWEAK IRQ137_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ137_Handler
|
||||
B IRQ137_Handler
|
||||
|
||||
PUBWEAK IRQ138_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ138_Handler
|
||||
B IRQ138_Handler
|
||||
|
||||
PUBWEAK IRQ139_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ139_Handler
|
||||
B IRQ139_Handler
|
||||
|
||||
PUBWEAK IRQ140_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ140_Handler
|
||||
B IRQ140_Handler
|
||||
|
||||
PUBWEAK IRQ141_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ141_Handler
|
||||
B IRQ141_Handler
|
||||
|
||||
PUBWEAK IRQ142_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ142_Handler
|
||||
B IRQ142_Handler
|
||||
|
||||
PUBWEAK IRQ143_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IRQ143_Handler
|
||||
B IRQ143_Handler
|
||||
|
||||
END
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,215 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file system_hc32f460.c
|
||||
* @brief This file provides two functions and two global variables to be called
|
||||
* from user application.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2022-10-31 CDT Delete the __low_level_init function of IAR and $Sub$$main function of MDK
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "system_hc32f460.h"
|
||||
|
||||
/**
|
||||
* @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F460_System
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup HC32F460_System_Local_Macros HC32F460 System Local Macros
|
||||
* @{
|
||||
*/
|
||||
#define HRC_16MHz_VALUE (16000000UL) /*!< Internal high speed RC freq. */
|
||||
#define HRC_20MHz_VALUE (20000000UL) /*!< Internal high speed RC freq. */
|
||||
/* HRC select */
|
||||
#define HRC_FREQ_MON() (*((volatile uint32_t *)(0x40010684UL)))
|
||||
|
||||
/* Vector Table base offset field */
|
||||
#ifndef VECT_TAB_OFFSET
|
||||
#define VECT_TAB_OFFSET (0x0UL) /*!< This value must be a multiple of 0x400. */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F460_System_Global_Variable
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!< System clock frequency (Core clock) */
|
||||
__NO_INIT uint32_t SystemCoreClock;
|
||||
/*!< High speed RC frequency (HCR clock) */
|
||||
__NO_INIT uint32_t HRC_VALUE;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F460_System_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system. Initialize the System and update
|
||||
* the SystemCoreClock variable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Configure the Vector Table relocation */
|
||||
|
||||
extern unsigned char Image$$ER_IROM1$$Base;
|
||||
|
||||
uint32_t rom_base =0u;
|
||||
|
||||
rom_base= (uint32_t)&Image$$ER_IROM1$$Base;
|
||||
|
||||
/* FPU settings */
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 20) | (3UL << 22)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
SystemCoreClockUpdate();
|
||||
#if defined (ROM_EXT_QSPI)
|
||||
SystemInit_QspiMem();
|
||||
#endif /* ROM_EXT_QSPI */
|
||||
|
||||
|
||||
SCB->VTOR = rom_base; /* Vector Table Relocation */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint8_t u8SysClkSrc;
|
||||
uint32_t plln;
|
||||
uint32_t pllp;
|
||||
uint32_t pllm;
|
||||
uint32_t u32PllSrcFreq;
|
||||
|
||||
/* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */
|
||||
if (1UL == (HRC_FREQ_MON() & 1UL)) {
|
||||
HRC_VALUE = HRC_16MHz_VALUE;
|
||||
} else {
|
||||
HRC_VALUE = HRC_20MHz_VALUE;
|
||||
}
|
||||
u8SysClkSrc = CM_CMU->CKSWR & CMU_CKSWR_CKSW;
|
||||
switch (u8SysClkSrc) {
|
||||
case 0x00U: /* use internal high speed RC */
|
||||
SystemCoreClock = HRC_VALUE;
|
||||
break;
|
||||
case 0x01U: /* use internal middle speed RC */
|
||||
SystemCoreClock = MRC_VALUE;
|
||||
break;
|
||||
case 0x02U: /* use internal low speed RC */
|
||||
SystemCoreClock = LRC_VALUE;
|
||||
break;
|
||||
case 0x03U: /* use external high speed OSC */
|
||||
SystemCoreClock = XTAL_VALUE;
|
||||
break;
|
||||
case 0x04U: /* use external low speed OSC */
|
||||
SystemCoreClock = XTAL32_VALUE;
|
||||
break;
|
||||
case 0x05U: /* use MPLL */
|
||||
/* PLLCLK = ((pllsrc / pllm) * plln) / pllp */
|
||||
plln = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLN) >> CMU_PLLCFGR_MPLLN_POS;
|
||||
pllp = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLP) >> CMU_PLLCFGR_MPLLP_POS;
|
||||
pllm = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLM) >> CMU_PLLCFGR_MPLLM_POS;
|
||||
if (0UL == (CM_CMU->PLLCFGR & CMU_PLLCFGR_PLLSRC)) { /* use external highspeed OSC as PLL source */
|
||||
u32PllSrcFreq = XTAL_VALUE;
|
||||
} else { /* use internal high RC as PLL source */
|
||||
u32PllSrcFreq = HRC_VALUE;
|
||||
}
|
||||
SystemCoreClock = u32PllSrcFreq / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined (ROM_EXT_QSPI)
|
||||
/**
|
||||
* @brief Initialize the QSPI memory.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__WEAKDEF void SystemInit_QspiMem(void)
|
||||
{
|
||||
/* QSPI configure */
|
||||
CM_GPIO->PWPR = 0xA501U;
|
||||
/* High driver */
|
||||
CM_GPIO->PCRC7 = 0x0120U;
|
||||
CM_GPIO->PCRC6 = 0x0120U;
|
||||
CM_GPIO->PCRD8 = 0x0120U;
|
||||
CM_GPIO->PCRD9 = 0x0120U;
|
||||
CM_GPIO->PCRD10 = 0x0120U;
|
||||
CM_GPIO->PCRD11 = 0x0120U;
|
||||
/* Set function */
|
||||
CM_GPIO->PFSRC7 = 0x07U;
|
||||
CM_GPIO->PFSRC6 = 0x07U;
|
||||
CM_GPIO->PFSRD8 = 0x07U;
|
||||
CM_GPIO->PFSRD9 = 0x07U;
|
||||
CM_GPIO->PFSRD10 = 0x07U;
|
||||
CM_GPIO->PFSRD11 = 0x07U;
|
||||
/* qspi configure */
|
||||
CM_PWC->FCG1 &= ~0x00000008UL;
|
||||
CM_QSPI->CR = 0x0002000D;
|
||||
CM_QSPI->CSCR = 0x00000001;
|
||||
CM_QSPI->FCR = 0x00008332;
|
||||
}
|
||||
#endif /* ROM_EXT_QSPI */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,517 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_common_tables.h
|
||||
* Description: Extern declaration for common tables
|
||||
*
|
||||
* $Date: 27. January 2017
|
||||
* $Revision: V.1.5.1
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_COMMON_TABLES_H
|
||||
#define _ARM_COMMON_TABLES_H
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
/* Double Precision Float CFFT twiddles */
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024)
|
||||
extern const uint16_t armBitRevTable[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_16)
|
||||
extern const uint64_t twiddleCoefF64_16[32];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_32)
|
||||
extern const uint64_t twiddleCoefF64_32[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_64)
|
||||
extern const uint64_t twiddleCoefF64_64[128];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_128)
|
||||
extern const uint64_t twiddleCoefF64_128[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_256)
|
||||
extern const uint64_t twiddleCoefF64_256[512];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_512)
|
||||
extern const uint64_t twiddleCoefF64_512[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_1024)
|
||||
extern const uint64_t twiddleCoefF64_1024[2048];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_2048)
|
||||
extern const uint64_t twiddleCoefF64_2048[4096];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_4096)
|
||||
extern const uint64_t twiddleCoefF64_4096[8192];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16)
|
||||
extern const float32_t twiddleCoef_16[32];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
|
||||
extern const float32_t twiddleCoef_32[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64)
|
||||
extern const float32_t twiddleCoef_64[128];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
|
||||
extern const float32_t twiddleCoef_128[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256)
|
||||
extern const float32_t twiddleCoef_256[512];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
|
||||
extern const float32_t twiddleCoef_512[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024)
|
||||
extern const float32_t twiddleCoef_1024[2048];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
|
||||
extern const float32_t twiddleCoef_2048[4096];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096)
|
||||
extern const float32_t twiddleCoef_4096[8192];
|
||||
#define twiddleCoef twiddleCoef_4096
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16)
|
||||
extern const q31_t twiddleCoef_16_q31[24];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
|
||||
extern const q31_t twiddleCoef_32_q31[48];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64)
|
||||
extern const q31_t twiddleCoef_64_q31[96];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
|
||||
extern const q31_t twiddleCoef_128_q31[192];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256)
|
||||
extern const q31_t twiddleCoef_256_q31[384];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
|
||||
extern const q31_t twiddleCoef_512_q31[768];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024)
|
||||
extern const q31_t twiddleCoef_1024_q31[1536];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
|
||||
extern const q31_t twiddleCoef_2048_q31[3072];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096)
|
||||
extern const q31_t twiddleCoef_4096_q31[6144];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16)
|
||||
extern const q15_t twiddleCoef_16_q15[24];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
|
||||
extern const q15_t twiddleCoef_32_q15[48];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64)
|
||||
extern const q15_t twiddleCoef_64_q15[96];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
|
||||
extern const q15_t twiddleCoef_128_q15[192];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256)
|
||||
extern const q15_t twiddleCoef_256_q15[384];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
|
||||
extern const q15_t twiddleCoef_512_q15[768];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024)
|
||||
extern const q15_t twiddleCoef_1024_q15[1536];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
|
||||
extern const q15_t twiddleCoef_2048_q15[3072];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096)
|
||||
extern const q15_t twiddleCoef_4096_q15[6144];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
/* Double Precision Float RFFT twiddles */
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32)
|
||||
extern const uint64_t twiddleCoefF64_rfft_32[32];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64)
|
||||
extern const uint64_t twiddleCoefF64_rfft_64[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128)
|
||||
extern const uint64_t twiddleCoefF64_rfft_128[128];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256)
|
||||
extern const uint64_t twiddleCoefF64_rfft_256[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512)
|
||||
extern const uint64_t twiddleCoefF64_rfft_512[512];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024)
|
||||
extern const uint64_t twiddleCoefF64_rfft_1024[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048)
|
||||
extern const uint64_t twiddleCoefF64_rfft_2048[2048];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096)
|
||||
extern const uint64_t twiddleCoefF64_rfft_4096[4096];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)
|
||||
extern const float32_t twiddleCoef_rfft_32[32];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)
|
||||
extern const float32_t twiddleCoef_rfft_64[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)
|
||||
extern const float32_t twiddleCoef_rfft_128[128];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)
|
||||
extern const float32_t twiddleCoef_rfft_256[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)
|
||||
extern const float32_t twiddleCoef_rfft_512[512];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)
|
||||
extern const float32_t twiddleCoef_rfft_1024[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)
|
||||
extern const float32_t twiddleCoef_rfft_2048[2048];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)
|
||||
extern const float32_t twiddleCoef_rfft_4096[4096];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
|
||||
/* Double precision floating-point bit reversal tables */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_16)
|
||||
#define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12)
|
||||
extern const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_32)
|
||||
#define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24)
|
||||
extern const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_64)
|
||||
#define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56)
|
||||
extern const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_128)
|
||||
#define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112)
|
||||
extern const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_256)
|
||||
#define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240)
|
||||
extern const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_512)
|
||||
#define ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480)
|
||||
extern const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_1024)
|
||||
#define ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992)
|
||||
extern const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_2048)
|
||||
#define ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
extern const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_4096)
|
||||
#define ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
extern const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
/* floating-point bit reversal tables */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16)
|
||||
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
|
||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32)
|
||||
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
|
||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64)
|
||||
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
|
||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128)
|
||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
|
||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256)
|
||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
|
||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512)
|
||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
|
||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024)
|
||||
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
|
||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048)
|
||||
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
|
||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096)
|
||||
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
|
||||
/* fixed-point bit reversal tables */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32)
|
||||
extern const float32_t realCoefA[8192];
|
||||
extern const float32_t realCoefB[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31)
|
||||
extern const q31_t realCoefAQ31[8192];
|
||||
extern const q31_t realCoefBQ31[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15)
|
||||
extern const q15_t realCoefAQ15[8192];
|
||||
extern const q15_t realCoefBQ15[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128)
|
||||
extern const float32_t Weights_128[256];
|
||||
extern const float32_t cos_factors_128[128];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512)
|
||||
extern const float32_t Weights_512[1024];
|
||||
extern const float32_t cos_factors_512[512];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048)
|
||||
extern const float32_t Weights_2048[4096];
|
||||
extern const float32_t cos_factors_2048[2048];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192)
|
||||
extern const float32_t Weights_8192[16384];
|
||||
extern const float32_t cos_factors_8192[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128)
|
||||
extern const q15_t WeightsQ15_128[256];
|
||||
extern const q15_t cos_factorsQ15_128[128];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512)
|
||||
extern const q15_t WeightsQ15_512[1024];
|
||||
extern const q15_t cos_factorsQ15_512[512];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048)
|
||||
extern const q15_t WeightsQ15_2048[4096];
|
||||
extern const q15_t cos_factorsQ15_2048[2048];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192)
|
||||
extern const q15_t WeightsQ15_8192[16384];
|
||||
extern const q15_t cos_factorsQ15_8192[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128)
|
||||
extern const q31_t WeightsQ31_128[256];
|
||||
extern const q31_t cos_factorsQ31_128[128];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512)
|
||||
extern const q31_t WeightsQ31_512[1024];
|
||||
extern const q31_t cos_factorsQ31_512[512];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048)
|
||||
extern const q31_t WeightsQ31_2048[4096];
|
||||
extern const q31_t cos_factorsQ31_2048[2048];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192)
|
||||
extern const q31_t WeightsQ31_8192[16384];
|
||||
extern const q31_t cos_factorsQ31_8192[8192];
|
||||
#endif
|
||||
|
||||
#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15)
|
||||
extern const q15_t armRecipTableQ15[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31)
|
||||
extern const q31_t armRecipTableQ31[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
/* Tables for Fast Math Sine and Cosine */
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32)
|
||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31)
|
||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15)
|
||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
#if defined(ARM_MATH_MVEI)
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE)
|
||||
extern const q31_t sqrtTable_Q31[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
#endif
|
||||
|
||||
#if defined(ARM_MATH_MVEI)
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE)
|
||||
extern const q15_t sqrtTable_Q15[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
#endif
|
||||
|
||||
#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */
|
||||
|
||||
#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
extern const float32_t exp_tab[8];
|
||||
extern const float32_t __logf_lut_f32[8];
|
||||
#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
|
||||
#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM))
|
||||
extern const unsigned char hwLUT[256];
|
||||
#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */
|
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */
|
||||
|
||||
@@ -0,0 +1,76 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs.h
|
||||
* Description: Constant structs that are initialized for user convenience.
|
||||
* For example, some can be given as arguments to the arm_cfft_f32() function.
|
||||
*
|
||||
* $Date: 27. January 2017
|
||||
* $Revision: V.1.5.1
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_H
|
||||
#define _ARM_CONST_STRUCTS_H
|
||||
|
||||
#include "arm_math.h"
|
||||
#include "arm_common_tables.h"
|
||||
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len16;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len32;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len64;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len128;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len256;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len512;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096;
|
||||
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,348 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_helium_utils.h
|
||||
* Description: Utility functions for Helium development
|
||||
*
|
||||
* $Date: 09. September 2019
|
||||
* $Revision: V.1.5.1
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_UTILS_HELIUM_H_
|
||||
#define _ARM_UTILS_HELIUM_H_
|
||||
|
||||
/***************************************
|
||||
|
||||
Definitions available for MVEF and MVEI
|
||||
|
||||
***************************************/
|
||||
#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)
|
||||
|
||||
#define INACTIVELANE 0 /* inactive lane content */
|
||||
|
||||
|
||||
#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) */
|
||||
|
||||
/***************************************
|
||||
|
||||
Definitions available for MVEF only
|
||||
|
||||
***************************************/
|
||||
#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF)
|
||||
|
||||
__STATIC_FORCEINLINE float32_t vecAddAcrossF32Mve(float32x4_t in)
|
||||
{
|
||||
float32_t acc;
|
||||
|
||||
acc = vgetq_lane(in, 0) + vgetq_lane(in, 1) +
|
||||
vgetq_lane(in, 2) + vgetq_lane(in, 3);
|
||||
|
||||
return acc;
|
||||
}
|
||||
|
||||
/* newton initial guess */
|
||||
#define INVSQRT_MAGIC_F32 0x5f3759df
|
||||
|
||||
#define INVSQRT_NEWTON_MVE_F32(invSqrt, xHalf, xStart)\
|
||||
{ \
|
||||
float32x4_t tmp; \
|
||||
\
|
||||
/* tmp = xhalf * x * x */ \
|
||||
tmp = vmulq(xStart, xStart); \
|
||||
tmp = vmulq(tmp, xHalf); \
|
||||
/* (1.5f - xhalf * x * x) */ \
|
||||
tmp = vsubq(vdupq_n_f32(1.5f), tmp); \
|
||||
/* x = x*(1.5f-xhalf*x*x); */ \
|
||||
invSqrt = vmulq(tmp, xStart); \
|
||||
}
|
||||
#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) */
|
||||
|
||||
/***************************************
|
||||
|
||||
Definitions available for MVEI only
|
||||
|
||||
***************************************/
|
||||
#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI)
|
||||
|
||||
|
||||
#include "arm_common_tables.h"
|
||||
|
||||
/* Following functions are used to transpose matrix in f32 and q31 cases */
|
||||
__STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve(
|
||||
uint32_t * pDataSrc,
|
||||
uint32_t * pDataDest)
|
||||
{
|
||||
static const uint32x4_t vecOffs = { 0, 2, 1, 3 };
|
||||
/*
|
||||
*
|
||||
* | 0 1 | => | 0 2 |
|
||||
* | 2 3 | | 1 3 |
|
||||
*
|
||||
*/
|
||||
uint32x4_t vecIn = vldrwq_u32((uint32_t const *)pDataSrc);
|
||||
vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs, vecIn);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve(
|
||||
uint32_t * pDataSrc,
|
||||
uint32_t * pDataDest)
|
||||
{
|
||||
const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
|
||||
const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
|
||||
/*
|
||||
*
|
||||
* | 0 1 2 | | 0 3 6 | 4 x 32 flattened version | 0 3 6 1 |
|
||||
* | 3 4 5 | => | 1 4 7 | => | 4 7 2 5 |
|
||||
* | 6 7 8 | | 2 5 8 | (row major) | 8 . . . |
|
||||
*
|
||||
*/
|
||||
uint32x4_t vecIn1 = vldrwq_u32((uint32_t const *) pDataSrc);
|
||||
uint32x4_t vecIn2 = vldrwq_u32((uint32_t const *) &pDataSrc[4]);
|
||||
|
||||
vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs1, vecIn1);
|
||||
vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs2, vecIn2);
|
||||
|
||||
pDataDest[8] = pDataSrc[8];
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint32_t * pDataDest)
|
||||
{
|
||||
/*
|
||||
* 4x4 Matrix transposition
|
||||
* is 4 x de-interleave operation
|
||||
*
|
||||
* 0 1 2 3 0 4 8 12
|
||||
* 4 5 6 7 1 5 9 13
|
||||
* 8 9 10 11 2 6 10 14
|
||||
* 12 13 14 15 3 7 11 15
|
||||
*/
|
||||
|
||||
uint32x4x4_t vecIn;
|
||||
|
||||
vecIn = vld4q((uint32_t const *) pDataSrc);
|
||||
vstrwq(pDataDest, vecIn.val[0]);
|
||||
pDataDest += 4;
|
||||
vstrwq(pDataDest, vecIn.val[1]);
|
||||
pDataDest += 4;
|
||||
vstrwq(pDataDest, vecIn.val[2]);
|
||||
pDataDest += 4;
|
||||
vstrwq(pDataDest, vecIn.val[3]);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve(
|
||||
uint16_t srcRows,
|
||||
uint16_t srcCols,
|
||||
uint32_t * pDataSrc,
|
||||
uint32_t * pDataDest)
|
||||
{
|
||||
uint32x4_t vecOffs;
|
||||
uint32_t i;
|
||||
uint32_t blkCnt;
|
||||
uint32_t const *pDataC;
|
||||
uint32_t *pDataDestR;
|
||||
uint32x4_t vecIn;
|
||||
|
||||
vecOffs = vidupq_u32((uint32_t)0, 1);
|
||||
vecOffs = vecOffs * srcCols;
|
||||
|
||||
i = srcCols;
|
||||
do
|
||||
{
|
||||
pDataC = (uint32_t const *) pDataSrc;
|
||||
pDataDestR = pDataDest;
|
||||
|
||||
blkCnt = srcRows >> 2;
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
|
||||
vstrwq(pDataDestR, vecIn);
|
||||
pDataDestR += 4;
|
||||
pDataC = pDataC + srcCols * 4;
|
||||
/*
|
||||
* Decrement the blockSize loop counter
|
||||
*/
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/*
|
||||
* tail
|
||||
*/
|
||||
blkCnt = srcRows & 3;
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
mve_pred16_t p0 = vctp32q(blkCnt);
|
||||
vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
|
||||
vstrwq_p(pDataDestR, vecIn, p0);
|
||||
}
|
||||
|
||||
pDataSrc += 1;
|
||||
pDataDest += srcRows;
|
||||
}
|
||||
while (--i);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE)
|
||||
__STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn)
|
||||
{
|
||||
q63x2_t vecTmpLL;
|
||||
q31x4_t vecTmp0, vecTmp1;
|
||||
q31_t scale;
|
||||
q63_t tmp64;
|
||||
q31x4_t vecNrm, vecDst, vecIdx, vecSignBits;
|
||||
|
||||
|
||||
vecSignBits = vclsq(vecIn);
|
||||
vecSignBits = vbicq(vecSignBits, 1);
|
||||
/*
|
||||
* in = in << no_of_sign_bits;
|
||||
*/
|
||||
vecNrm = vshlq(vecIn, vecSignBits);
|
||||
/*
|
||||
* index = in >> 24;
|
||||
*/
|
||||
vecIdx = vecNrm >> 24;
|
||||
vecIdx = vecIdx << 1;
|
||||
|
||||
vecTmp0 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, vecIdx);
|
||||
|
||||
vecIdx = vecIdx + 1;
|
||||
|
||||
vecTmp1 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, vecIdx);
|
||||
|
||||
vecTmp1 = vqrdmulhq(vecTmp1, vecNrm);
|
||||
vecTmp0 = vecTmp0 - vecTmp1;
|
||||
vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0);
|
||||
vecTmp1 = vqrdmulhq(vecNrm, vecTmp1);
|
||||
vecTmp1 = vdupq_n_s32(0x18000000) - vecTmp1;
|
||||
vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1);
|
||||
vecTmpLL = vmullbq_int(vecNrm, vecTmp0);
|
||||
|
||||
/*
|
||||
* scale elements 0, 2
|
||||
*/
|
||||
scale = 26 + (vecSignBits[0] >> 1);
|
||||
tmp64 = asrl(vecTmpLL[0], scale);
|
||||
vecDst[0] = (q31_t) tmp64;
|
||||
|
||||
scale = 26 + (vecSignBits[2] >> 1);
|
||||
tmp64 = asrl(vecTmpLL[1], scale);
|
||||
vecDst[2] = (q31_t) tmp64;
|
||||
|
||||
vecTmpLL = vmulltq_int(vecNrm, vecTmp0);
|
||||
|
||||
/*
|
||||
* scale elements 1, 3
|
||||
*/
|
||||
scale = 26 + (vecSignBits[1] >> 1);
|
||||
tmp64 = asrl(vecTmpLL[0], scale);
|
||||
vecDst[1] = (q31_t) tmp64;
|
||||
|
||||
scale = 26 + (vecSignBits[3] >> 1);
|
||||
tmp64 = asrl(vecTmpLL[1], scale);
|
||||
vecDst[3] = (q31_t) tmp64;
|
||||
/*
|
||||
* set negative values to 0
|
||||
*/
|
||||
vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s32(vecIn, 0));
|
||||
|
||||
return vecDst;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE)
|
||||
__STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn)
|
||||
{
|
||||
q31x4_t vecTmpLev, vecTmpLodd, vecSignL;
|
||||
q15x8_t vecTmp0, vecTmp1;
|
||||
q15x8_t vecNrm, vecDst, vecIdx, vecSignBits;
|
||||
|
||||
vecDst = vuninitializedq_s16();
|
||||
|
||||
vecSignBits = vclsq(vecIn);
|
||||
vecSignBits = vbicq(vecSignBits, 1);
|
||||
/*
|
||||
* in = in << no_of_sign_bits;
|
||||
*/
|
||||
vecNrm = vshlq(vecIn, vecSignBits);
|
||||
|
||||
vecIdx = vecNrm >> 8;
|
||||
vecIdx = vecIdx << 1;
|
||||
|
||||
vecTmp0 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, vecIdx);
|
||||
|
||||
vecIdx = vecIdx + 1;
|
||||
|
||||
vecTmp1 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, vecIdx);
|
||||
|
||||
vecTmp1 = vqrdmulhq(vecTmp1, vecNrm);
|
||||
vecTmp0 = vecTmp0 - vecTmp1;
|
||||
vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0);
|
||||
vecTmp1 = vqrdmulhq(vecNrm, vecTmp1);
|
||||
vecTmp1 = vdupq_n_s16(0x1800) - vecTmp1;
|
||||
vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1);
|
||||
|
||||
vecSignBits = vecSignBits >> 1;
|
||||
|
||||
vecTmpLev = vmullbq_int(vecNrm, vecTmp0);
|
||||
vecTmpLodd = vmulltq_int(vecNrm, vecTmp0);
|
||||
|
||||
vecTmp0 = vecSignBits + 10;
|
||||
/*
|
||||
* negate sign to apply register based vshl
|
||||
*/
|
||||
vecTmp0 = -vecTmp0;
|
||||
|
||||
/*
|
||||
* shift even elements
|
||||
*/
|
||||
vecSignL = vmovlbq(vecTmp0);
|
||||
vecTmpLev = vshlq(vecTmpLev, vecSignL);
|
||||
/*
|
||||
* shift odd elements
|
||||
*/
|
||||
vecSignL = vmovltq(vecTmp0);
|
||||
vecTmpLodd = vshlq(vecTmpLodd, vecSignL);
|
||||
/*
|
||||
* merge and narrow odd and even parts
|
||||
*/
|
||||
vecDst = vmovnbq_s32(vecDst, vecTmpLev);
|
||||
vecDst = vmovntq_s32(vecDst, vecTmpLodd);
|
||||
/*
|
||||
* set negative values to 0
|
||||
*/
|
||||
vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s16(vecIn, 0));
|
||||
|
||||
return vecDst;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) */
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,235 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_mve_tables.h
|
||||
* Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc
|
||||
* used for MVE implementation only
|
||||
*
|
||||
* $Date: 08. January 2020
|
||||
* $Revision: V1.7.0
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2020 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MVE_TABLES_H
|
||||
#define _ARM_MVE_TABLES_H
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2];
|
||||
extern float32_t rearranged_twiddle_stride1_16_f32[8];
|
||||
extern float32_t rearranged_twiddle_stride2_16_f32[8];
|
||||
extern float32_t rearranged_twiddle_stride3_16_f32[8];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3];
|
||||
extern float32_t rearranged_twiddle_stride1_64_f32[40];
|
||||
extern float32_t rearranged_twiddle_stride2_64_f32[40];
|
||||
extern float32_t rearranged_twiddle_stride3_64_f32[40];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4];
|
||||
extern float32_t rearranged_twiddle_stride1_256_f32[168];
|
||||
extern float32_t rearranged_twiddle_stride2_256_f32[168];
|
||||
extern float32_t rearranged_twiddle_stride3_256_f32[168];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5];
|
||||
extern float32_t rearranged_twiddle_stride1_1024_f32[680];
|
||||
extern float32_t rearranged_twiddle_stride2_1024_f32[680];
|
||||
extern float32_t rearranged_twiddle_stride3_1024_f32[680];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6];
|
||||
extern float32_t rearranged_twiddle_stride1_4096_f32[2728];
|
||||
extern float32_t rearranged_twiddle_stride2_4096_f32[2728];
|
||||
extern float32_t rearranged_twiddle_stride3_4096_f32[2728];
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
|
||||
|
||||
#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVEI)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2];
|
||||
extern q31_t rearranged_twiddle_stride1_16_q31[8];
|
||||
extern q31_t rearranged_twiddle_stride2_16_q31[8];
|
||||
extern q31_t rearranged_twiddle_stride3_16_q31[8];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3];
|
||||
extern q31_t rearranged_twiddle_stride1_64_q31[40];
|
||||
extern q31_t rearranged_twiddle_stride2_64_q31[40];
|
||||
extern q31_t rearranged_twiddle_stride3_64_q31[40];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4];
|
||||
extern q31_t rearranged_twiddle_stride1_256_q31[168];
|
||||
extern q31_t rearranged_twiddle_stride2_256_q31[168];
|
||||
extern q31_t rearranged_twiddle_stride3_256_q31[168];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5];
|
||||
extern q31_t rearranged_twiddle_stride1_1024_q31[680];
|
||||
extern q31_t rearranged_twiddle_stride2_1024_q31[680];
|
||||
extern q31_t rearranged_twiddle_stride3_1024_q31[680];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6];
|
||||
extern q31_t rearranged_twiddle_stride1_4096_q31[2728];
|
||||
extern q31_t rearranged_twiddle_stride2_4096_q31[2728];
|
||||
extern q31_t rearranged_twiddle_stride3_4096_q31[2728];
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
|
||||
|
||||
#endif /* defined(ARM_MATH_MVEI) */
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVEI)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2];
|
||||
extern q15_t rearranged_twiddle_stride1_16_q15[8];
|
||||
extern q15_t rearranged_twiddle_stride2_16_q15[8];
|
||||
extern q15_t rearranged_twiddle_stride3_16_q15[8];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3];
|
||||
extern q15_t rearranged_twiddle_stride1_64_q15[40];
|
||||
extern q15_t rearranged_twiddle_stride2_64_q15[40];
|
||||
extern q15_t rearranged_twiddle_stride3_64_q15[40];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4];
|
||||
extern q15_t rearranged_twiddle_stride1_256_q15[168];
|
||||
extern q15_t rearranged_twiddle_stride2_256_q15[168];
|
||||
extern q15_t rearranged_twiddle_stride3_256_q15[168];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5];
|
||||
extern q15_t rearranged_twiddle_stride1_1024_q15[680];
|
||||
extern q15_t rearranged_twiddle_stride2_1024_q15[680];
|
||||
extern q15_t rearranged_twiddle_stride3_1024_q15[680];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6];
|
||||
extern q15_t rearranged_twiddle_stride1_4096_q15[2728];
|
||||
extern q15_t rearranged_twiddle_stride2_4096_q15[2728];
|
||||
extern q15_t rearranged_twiddle_stride3_4096_q15[2728];
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
|
||||
|
||||
#endif /* defined(ARM_MATH_MVEI) */
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVEI)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
|
||||
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
|
||||
|
||||
#endif /* defined(ARM_MATH_MVEI) */
|
||||
|
||||
|
||||
|
||||
#endif /*_ARM_MVE_TABLES_H*/
|
||||
|
||||
@@ -0,0 +1,372 @@
|
||||
/******************************************************************************
|
||||
* @file arm_vec_math.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.7.0
|
||||
* @date 15. October 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_VEC_MATH_H
|
||||
#define _ARM_VEC_MATH_H
|
||||
|
||||
#include "arm_math.h"
|
||||
#include "arm_common_tables.h"
|
||||
#include "arm_helium_utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#define INV_NEWTON_INIT_F32 0x7EF127EA
|
||||
|
||||
static const float32_t __logf_rng_f32=0.693147180f;
|
||||
|
||||
|
||||
/* fast inverse approximation (3x newton) */
|
||||
__STATIC_INLINE f32x4_t vrecip_medprec_f32(
|
||||
f32x4_t x)
|
||||
{
|
||||
q31x4_t m;
|
||||
f32x4_t b;
|
||||
any32x4_t xinv;
|
||||
f32x4_t ax = vabsq(x);
|
||||
|
||||
xinv.f = ax;
|
||||
m = 0x3F800000 - (xinv.i & 0x7F800000);
|
||||
xinv.i = xinv.i + m;
|
||||
xinv.f = 1.41176471f - 0.47058824f * xinv.f;
|
||||
xinv.i = xinv.i + m;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f));
|
||||
|
||||
return xinv.f;
|
||||
}
|
||||
|
||||
/* fast inverse approximation (4x newton) */
|
||||
__STATIC_INLINE f32x4_t vrecip_hiprec_f32(
|
||||
f32x4_t x)
|
||||
{
|
||||
q31x4_t m;
|
||||
f32x4_t b;
|
||||
any32x4_t xinv;
|
||||
f32x4_t ax = vabsq(x);
|
||||
|
||||
xinv.f = ax;
|
||||
|
||||
m = 0x3F800000 - (xinv.i & 0x7F800000);
|
||||
xinv.i = xinv.i + m;
|
||||
xinv.f = 1.41176471f - 0.47058824f * xinv.f;
|
||||
xinv.i = xinv.i + m;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f));
|
||||
|
||||
return xinv.f;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vdiv_f32(
|
||||
f32x4_t num, f32x4_t den)
|
||||
{
|
||||
return vmulq(num, vrecip_hiprec_f32(den));
|
||||
}
|
||||
|
||||
/**
|
||||
@brief Single-precision taylor dev.
|
||||
@param[in] x f32 quad vector input
|
||||
@param[in] coeffs f32 quad vector coeffs
|
||||
@return destination f32 quad vector
|
||||
*/
|
||||
|
||||
__STATIC_INLINE f32x4_t vtaylor_polyq_f32(
|
||||
f32x4_t x,
|
||||
const float32_t * coeffs)
|
||||
{
|
||||
f32x4_t A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]);
|
||||
f32x4_t B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]);
|
||||
f32x4_t C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]);
|
||||
f32x4_t D = vfmasq(vdupq_n_f32(coeffs[7]), x, coeffs[3]);
|
||||
f32x4_t x2 = vmulq(x, x);
|
||||
f32x4_t x4 = vmulq(x2, x2);
|
||||
f32x4_t res = vfmaq(vfmaq_f32(A, B, x2), vfmaq_f32(C, D, x2), x4);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vmant_exp_f32(
|
||||
f32x4_t x,
|
||||
int32x4_t * e)
|
||||
{
|
||||
any32x4_t r;
|
||||
int32x4_t n;
|
||||
|
||||
r.f = x;
|
||||
n = r.i >> 23;
|
||||
n = n - 127;
|
||||
r.i = r.i - (n << 23);
|
||||
|
||||
*e = n;
|
||||
return r.f;
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn)
|
||||
{
|
||||
q31x4_t vecExpUnBiased;
|
||||
f32x4_t vecTmpFlt0, vecTmpFlt1;
|
||||
f32x4_t vecAcc0, vecAcc1, vecAcc2, vecAcc3;
|
||||
f32x4_t vecExpUnBiasedFlt;
|
||||
|
||||
/*
|
||||
* extract exponent
|
||||
*/
|
||||
vecTmpFlt1 = vmant_exp_f32(vecIn, &vecExpUnBiased);
|
||||
|
||||
vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1;
|
||||
/*
|
||||
* a = (__logf_lut_f32[4] * r.f) + (__logf_lut_f32[0]);
|
||||
*/
|
||||
vecAcc0 = vdupq_n_f32(__logf_lut_f32[0]);
|
||||
vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f32[4]);
|
||||
/*
|
||||
* b = (__logf_lut_f32[6] * r.f) + (__logf_lut_f32[2]);
|
||||
*/
|
||||
vecAcc1 = vdupq_n_f32(__logf_lut_f32[2]);
|
||||
vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f32[6]);
|
||||
/*
|
||||
* c = (__logf_lut_f32[5] * r.f) + (__logf_lut_f32[1]);
|
||||
*/
|
||||
vecAcc2 = vdupq_n_f32(__logf_lut_f32[1]);
|
||||
vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f32[5]);
|
||||
/*
|
||||
* d = (__logf_lut_f32[7] * r.f) + (__logf_lut_f32[3]);
|
||||
*/
|
||||
vecAcc3 = vdupq_n_f32(__logf_lut_f32[3]);
|
||||
vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f32[7]);
|
||||
/*
|
||||
* a = a + b * xx;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0);
|
||||
/*
|
||||
* c = c + d * xx;
|
||||
*/
|
||||
vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0);
|
||||
/*
|
||||
* xx = xx * xx;
|
||||
*/
|
||||
vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0;
|
||||
vecExpUnBiasedFlt = vcvtq_f32_s32(vecExpUnBiased);
|
||||
/*
|
||||
* r.f = a + c * xx;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0);
|
||||
/*
|
||||
* add exponent
|
||||
* r.f = r.f + ((float32_t) m) * __logf_rng_f32;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f32);
|
||||
// set log0 down to -inf
|
||||
vecAcc0 = vdupq_m(vecAcc0, -INFINITY, vcmpeqq(vecIn, 0.0f));
|
||||
return vecAcc0;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vexpq_f32(
|
||||
f32x4_t x)
|
||||
{
|
||||
// Perform range reduction [-log(2),log(2)]
|
||||
int32x4_t m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f));
|
||||
f32x4_t val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f));
|
||||
|
||||
// Polynomial Approximation
|
||||
f32x4_t poly = vtaylor_polyq_f32(val, exp_tab);
|
||||
|
||||
// Reconstruct
|
||||
poly = (f32x4_t) (vqaddq_s32((q31x4_t) (poly), vqshlq_n_s32(m, 23)));
|
||||
|
||||
poly = vdupq_m(poly, 0.0f, vcmpltq_n_s32(m, -126));
|
||||
return poly;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb)
|
||||
{
|
||||
f32x4_t r = x;
|
||||
nb--;
|
||||
while (nb > 0) {
|
||||
r = vmulq(r, x);
|
||||
nb--;
|
||||
}
|
||||
return (r);
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn)
|
||||
{
|
||||
f32x4_t vecSx, vecW, vecTmp;
|
||||
any32x4_t v;
|
||||
|
||||
vecSx = vabsq(vecIn);
|
||||
|
||||
v.f = vecIn;
|
||||
v.i = vsubq(vdupq_n_s32(INV_NEWTON_INIT_F32), v.i);
|
||||
|
||||
vecW = vmulq(vecSx, v.f);
|
||||
|
||||
// v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w)))))));
|
||||
vecTmp = vsubq(vdupq_n_f32(8.0f), vecW);
|
||||
vecTmp = vfmasq(vecW, vecTmp, -28.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, 56.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, -70.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, 56.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, -28.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, 8.0f);
|
||||
v.f = vmulq(v.f, vecTmp);
|
||||
|
||||
v.f = vdupq_m(v.f, INFINITY, vcmpeqq(vecIn, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
v.f = vnegq_m(v.f, v.f, vcmpltq(vecIn, 0.0f));
|
||||
return v.f;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vtanhq_f32(
|
||||
f32x4_t val)
|
||||
{
|
||||
f32x4_t x =
|
||||
vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f));
|
||||
f32x4_t exp2x = vexpq_f32(vmulq_n_f32(x, 2.f));
|
||||
f32x4_t num = vsubq_n_f32(exp2x, 1.f);
|
||||
f32x4_t den = vaddq_n_f32(exp2x, 1.f);
|
||||
f32x4_t tanh = vmulq_f32(num, vrecip_f32(den));
|
||||
return tanh;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vpowq_f32(
|
||||
f32x4_t val,
|
||||
f32x4_t n)
|
||||
{
|
||||
return vexpq_f32(vmulq_f32(n, vlogq_f32(val)));
|
||||
}
|
||||
|
||||
#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/
|
||||
|
||||
#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM))
|
||||
#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */
|
||||
|
||||
#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#include "NEMath.h"
|
||||
/**
|
||||
* @brief Vectorized integer exponentiation
|
||||
* @param[in] x value
|
||||
* @param[in] nb integer exponent >= 1
|
||||
* @return x^nb
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb)
|
||||
{
|
||||
float32x4_t r = x;
|
||||
nb --;
|
||||
while(nb > 0)
|
||||
{
|
||||
r = vmulq_f32(r , x);
|
||||
nb--;
|
||||
}
|
||||
return(r);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x)
|
||||
{
|
||||
float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN));
|
||||
float32x4_t e = vrsqrteq_f32(x1);
|
||||
e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
|
||||
e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
|
||||
return vmulq_f32(x, e);
|
||||
}
|
||||
|
||||
__STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec)
|
||||
{
|
||||
float32x4_t tempF;
|
||||
int32x4_t tempHI,tempLO;
|
||||
|
||||
tempLO = vmovl_s16(vget_low_s16(vec));
|
||||
tempF = vcvtq_n_f32_s32(tempLO,15);
|
||||
tempF = __arm_vec_sqrt_f32_neon(tempF);
|
||||
tempLO = vcvtq_n_s32_f32(tempF,15);
|
||||
|
||||
tempHI = vmovl_s16(vget_high_s16(vec));
|
||||
tempF = vcvtq_n_f32_s32(tempHI,15);
|
||||
tempF = __arm_vec_sqrt_f32_neon(tempF);
|
||||
tempHI = vcvtq_n_s32_f32(tempF,15);
|
||||
|
||||
return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI)));
|
||||
}
|
||||
|
||||
__STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec)
|
||||
{
|
||||
float32x4_t temp;
|
||||
|
||||
temp = vcvtq_n_f32_s32(vec,31);
|
||||
temp = __arm_vec_sqrt_f32_neon(temp);
|
||||
return(vcvtq_n_s32_f32(temp,31));
|
||||
}
|
||||
|
||||
#endif /* (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* _ARM_VEC_MATH_H */
|
||||
|
||||
/**
|
||||
*
|
||||
* End of file.
|
||||
*/
|
||||
@@ -0,0 +1,411 @@
|
||||
/******************************************************************************
|
||||
* @file cachel1_armv7.h
|
||||
* @brief CMSIS Level 1 Cache API for Armv7-M and later
|
||||
* @version V1.0.0
|
||||
* @date 03. March 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_CACHEL1_ARMV7_H
|
||||
#define ARM_CACHEL1_ARMV7_H
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_CacheFunctions Cache Functions
|
||||
\brief Functions that configure Instruction and Data cache.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Cache Size ID Register Macros */
|
||||
#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
|
||||
#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
|
||||
|
||||
#ifndef __SCB_DCACHE_LINE_SIZE
|
||||
#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
|
||||
#endif
|
||||
|
||||
#ifndef __SCB_ICACHE_LINE_SIZE
|
||||
#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
|
||||
#endif
|
||||
|
||||
/**
|
||||
\brief Enable I-Cache
|
||||
\details Turns on I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_EnableICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable I-Cache
|
||||
\details Turns off I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_DisableICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
|
||||
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Invalidate I-Cache
|
||||
\details Invalidates I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->ICIALLU = 0UL;
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief I-Cache Invalidate by address
|
||||
\details Invalidates I-Cache for the given address.
|
||||
I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
I-Cache memory blocks which are part of given address + given size are invalidated.
|
||||
\param[in] addr address
|
||||
\param[in] isize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
if ( isize > 0 ) {
|
||||
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_ICACHE_LINE_SIZE;
|
||||
op_size -= __SCB_ICACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable D-Cache
|
||||
\details Turns on D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_EnableDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
||||
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
__DSB();
|
||||
|
||||
SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable D-Cache
|
||||
\details Turns off D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean & invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||||
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Invalidate D-Cache
|
||||
\details Invalidates D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
||||
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clean D-Cache
|
||||
\details Cleans D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
|
||||
((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clean & Invalidate D-Cache
|
||||
\details Cleans and Invalidates D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean & invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||||
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Invalidate by address
|
||||
\details Invalidates D-Cache for the given address.
|
||||
D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are invalidated.
|
||||
\param[in] addr address
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Clean by address
|
||||
\details Cleans D-Cache for the given address
|
||||
D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are cleaned.
|
||||
\param[in] addr address
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Clean and Invalidate by address
|
||||
\details Cleans and invalidates D_Cache for the given address
|
||||
D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
|
||||
\param[in] addr address (aligned to 32-byte boundary)
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_CacheFunctions */
|
||||
|
||||
#endif /* ARM_CACHEL1_ARMV7_H */
|
||||
@@ -0,0 +1,885 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h
|
||||
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||
* @version V5.2.1
|
||||
* @date 26. March 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H
|
||||
#define __CMSIS_ARMCC_H
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler control architecture macros */
|
||||
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#endif
|
||||
|
||||
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||
/* __ARM_ARCH_8_1M_MAIN__ not applicable */
|
||||
|
||||
/* CMSIS compiler control DSP macros */
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __ARM_FEATURE_DSP 1
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler specific defines */
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static __inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE static __forceinline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __declspec(noreturn)
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#define __COMPILER_BARRIER() __memory_changed()
|
||||
#endif
|
||||
|
||||
/* ######################### Startup and Lowlevel Init ######################## */
|
||||
|
||||
#ifndef __PROGRAM_START
|
||||
#define __PROGRAM_START __main
|
||||
#endif
|
||||
|
||||
#ifndef __INITIAL_SP
|
||||
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
|
||||
#endif
|
||||
|
||||
#ifndef __STACK_LIMIT
|
||||
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE
|
||||
#define __VECTOR_TABLE __Vectors
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE_ATTRIBUTE
|
||||
#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
|
||||
#endif
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Enable IRQ Interrupts
|
||||
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __enable_irq(); */
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable IRQ Interrupts
|
||||
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/**
|
||||
\brief Get Control Register
|
||||
\details Returns the content of the Control Register.
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register
|
||||
\details Writes the given value to the Control Register.
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register
|
||||
\details Returns the content of the IPSR Register.
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register
|
||||
\details Returns the content of the APSR Register.
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register
|
||||
\details Returns the content of the xPSR Register.
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer
|
||||
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer
|
||||
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer
|
||||
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer
|
||||
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask
|
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask
|
||||
\details Assigns the given value to the Priority Mask Register.
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority
|
||||
\details Returns the current value of the Base Priority register.
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority
|
||||
\details Assigns the given value to the Base Priority register.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition
|
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask
|
||||
\details Returns the current value of the Fault Mask register.
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask
|
||||
\details Assigns the given value to the Fault Mask register.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#else
|
||||
(void)fpscr;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() __isb(0xF)
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() __dsb(0xF)
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() __dmb(0xF)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] op1 Value to rotate
|
||||
\param [in] op2 Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,283 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.1.0
|
||||
* @date 09. October 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6.6 LTM (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||
#include "cmsis_armclang_ltm.h"
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,968 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_iccarm.h
|
||||
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
|
||||
* @version V5.2.0
|
||||
* @date 28. January 2020
|
||||
******************************************************************************/
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2017-2019 IAR Systems
|
||||
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License")
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
|
||||
#ifndef __CMSIS_ICCARM_H__
|
||||
#define __CMSIS_ICCARM_H__
|
||||
|
||||
#ifndef __ICCARM__
|
||||
#error This file should only be compiled by ICCARM
|
||||
#endif
|
||||
|
||||
#pragma system_include
|
||||
|
||||
#define __IAR_FT _Pragma("inline=forced") __intrinsic
|
||||
|
||||
#if (__VER__ >= 8000000)
|
||||
#define __ICCARM_V8 1
|
||||
#else
|
||||
#define __ICCARM_V8 0
|
||||
#endif
|
||||
|
||||
#ifndef __ALIGNED
|
||||
#if __ICCARM_V8
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#elif (__VER__ >= 7080000)
|
||||
/* Needs IAR language extensions */
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#else
|
||||
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Define compiler macros for CPU architecture, used in CMSIS 5.
|
||||
*/
|
||||
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
|
||||
/* Macros already defined */
|
||||
#else
|
||||
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#elif defined(__ARM8M_BASELINE__)
|
||||
#define __ARM_ARCH_8M_BASE__ 1
|
||||
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
|
||||
#if __ARM_ARCH == 6
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#elif __ARM_ARCH == 7
|
||||
#if __ARM_FEATURE_DSP
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#else
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
#endif /* __ARM_ARCH */
|
||||
#endif /* __ARM_ARCH_PROFILE == 'M' */
|
||||
#endif
|
||||
|
||||
/* Alternativ core deduction for older ICCARM's */
|
||||
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
|
||||
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
|
||||
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
|
||||
#define __ARM_ARCH_8M_BASE__ 1
|
||||
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#else
|
||||
#error "Unknown target."
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
|
||||
#define __IAR_M0_FAMILY 1
|
||||
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
|
||||
#define __IAR_M0_FAMILY 1
|
||||
#else
|
||||
#define __IAR_M0_FAMILY 0
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
|
||||
#ifndef __NO_RETURN
|
||||
#if __ICCARM_V8
|
||||
#define __NO_RETURN __attribute__((__noreturn__))
|
||||
#else
|
||||
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED __packed
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED_STRUCT
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED_UNION
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __RESTRICT
|
||||
#if __ICCARM_V8
|
||||
#define __RESTRICT __restrict
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __RESTRICT restrict
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
|
||||
#ifndef __FORCEINLINE
|
||||
#define __FORCEINLINE _Pragma("inline=forced")
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint16_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
|
||||
{
|
||||
*(__packed uint16_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint32_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
|
||||
{
|
||||
*(__packed uint32_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__packed struct __iar_u32 { uint32_t v; };
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
|
||||
#endif
|
||||
|
||||
#ifndef __USED
|
||||
#if __ICCARM_V8
|
||||
#define __USED __attribute__((used))
|
||||
#else
|
||||
#define __USED _Pragma("__root")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#if __ICCARM_V8
|
||||
#define __WEAK __attribute__((weak))
|
||||
#else
|
||||
#define __WEAK _Pragma("__weak")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PROGRAM_START
|
||||
#define __PROGRAM_START __iar_program_start
|
||||
#endif
|
||||
|
||||
#ifndef __INITIAL_SP
|
||||
#define __INITIAL_SP CSTACK$$Limit
|
||||
#endif
|
||||
|
||||
#ifndef __STACK_LIMIT
|
||||
#define __STACK_LIMIT CSTACK$$Base
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE
|
||||
#define __VECTOR_TABLE __vector_table
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE_ATTRIBUTE
|
||||
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
|
||||
#endif
|
||||
|
||||
#ifndef __ICCARM_INTRINSICS_VERSION__
|
||||
#define __ICCARM_INTRINSICS_VERSION__ 0
|
||||
#endif
|
||||
|
||||
#if __ICCARM_INTRINSICS_VERSION__ == 2
|
||||
|
||||
#if defined(__CLZ)
|
||||
#undef __CLZ
|
||||
#endif
|
||||
#if defined(__REVSH)
|
||||
#undef __REVSH
|
||||
#endif
|
||||
#if defined(__RBIT)
|
||||
#undef __RBIT
|
||||
#endif
|
||||
#if defined(__SSAT)
|
||||
#undef __SSAT
|
||||
#endif
|
||||
#if defined(__USAT)
|
||||
#undef __USAT
|
||||
#endif
|
||||
|
||||
#include "iccarm_builtin.h"
|
||||
|
||||
#define __disable_fault_irq __iar_builtin_disable_fiq
|
||||
#define __disable_irq __iar_builtin_disable_interrupt
|
||||
#define __enable_fault_irq __iar_builtin_enable_fiq
|
||||
#define __enable_irq __iar_builtin_enable_interrupt
|
||||
#define __arm_rsr __iar_builtin_rsr
|
||||
#define __arm_wsr __iar_builtin_wsr
|
||||
|
||||
|
||||
#define __get_APSR() (__arm_rsr("APSR"))
|
||||
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
|
||||
#define __get_CONTROL() (__arm_rsr("CONTROL"))
|
||||
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
|
||||
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
#define __get_FPSCR() (__arm_rsr("FPSCR"))
|
||||
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
|
||||
#else
|
||||
#define __get_FPSCR() ( 0 )
|
||||
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||
#endif
|
||||
|
||||
#define __get_IPSR() (__arm_rsr("IPSR"))
|
||||
#define __get_MSP() (__arm_rsr("MSP"))
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __get_MSPLIM() (0U)
|
||||
#else
|
||||
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
|
||||
#endif
|
||||
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
|
||||
#define __get_PSP() (__arm_rsr("PSP"))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __get_PSPLIM() (0U)
|
||||
#else
|
||||
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
|
||||
#endif
|
||||
|
||||
#define __get_xPSR() (__arm_rsr("xPSR"))
|
||||
|
||||
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
|
||||
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
|
||||
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
|
||||
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
|
||||
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __set_MSPLIM(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
|
||||
#endif
|
||||
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
|
||||
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __set_PSPLIM(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
|
||||
#endif
|
||||
|
||||
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
|
||||
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
|
||||
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
|
||||
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
|
||||
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
|
||||
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
|
||||
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
|
||||
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
|
||||
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
|
||||
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
|
||||
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
|
||||
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
|
||||
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
|
||||
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __TZ_get_PSPLIM_NS() (0U)
|
||||
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
|
||||
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
|
||||
#endif
|
||||
|
||||
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
|
||||
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
|
||||
|
||||
#define __NOP __iar_builtin_no_operation
|
||||
|
||||
#define __CLZ __iar_builtin_CLZ
|
||||
#define __CLREX __iar_builtin_CLREX
|
||||
|
||||
#define __DMB __iar_builtin_DMB
|
||||
#define __DSB __iar_builtin_DSB
|
||||
#define __ISB __iar_builtin_ISB
|
||||
|
||||
#define __LDREXB __iar_builtin_LDREXB
|
||||
#define __LDREXH __iar_builtin_LDREXH
|
||||
#define __LDREXW __iar_builtin_LDREX
|
||||
|
||||
#define __RBIT __iar_builtin_RBIT
|
||||
#define __REV __iar_builtin_REV
|
||||
#define __REV16 __iar_builtin_REV16
|
||||
|
||||
__IAR_FT int16_t __REVSH(int16_t val)
|
||||
{
|
||||
return (int16_t) __iar_builtin_REVSH(val);
|
||||
}
|
||||
|
||||
#define __ROR __iar_builtin_ROR
|
||||
#define __RRX __iar_builtin_RRX
|
||||
|
||||
#define __SEV __iar_builtin_SEV
|
||||
|
||||
#if !__IAR_M0_FAMILY
|
||||
#define __SSAT __iar_builtin_SSAT
|
||||
#endif
|
||||
|
||||
#define __STREXB __iar_builtin_STREXB
|
||||
#define __STREXH __iar_builtin_STREXH
|
||||
#define __STREXW __iar_builtin_STREX
|
||||
|
||||
#if !__IAR_M0_FAMILY
|
||||
#define __USAT __iar_builtin_USAT
|
||||
#endif
|
||||
|
||||
#define __WFE __iar_builtin_WFE
|
||||
#define __WFI __iar_builtin_WFI
|
||||
|
||||
#if __ARM_MEDIA__
|
||||
#define __SADD8 __iar_builtin_SADD8
|
||||
#define __QADD8 __iar_builtin_QADD8
|
||||
#define __SHADD8 __iar_builtin_SHADD8
|
||||
#define __UADD8 __iar_builtin_UADD8
|
||||
#define __UQADD8 __iar_builtin_UQADD8
|
||||
#define __UHADD8 __iar_builtin_UHADD8
|
||||
#define __SSUB8 __iar_builtin_SSUB8
|
||||
#define __QSUB8 __iar_builtin_QSUB8
|
||||
#define __SHSUB8 __iar_builtin_SHSUB8
|
||||
#define __USUB8 __iar_builtin_USUB8
|
||||
#define __UQSUB8 __iar_builtin_UQSUB8
|
||||
#define __UHSUB8 __iar_builtin_UHSUB8
|
||||
#define __SADD16 __iar_builtin_SADD16
|
||||
#define __QADD16 __iar_builtin_QADD16
|
||||
#define __SHADD16 __iar_builtin_SHADD16
|
||||
#define __UADD16 __iar_builtin_UADD16
|
||||
#define __UQADD16 __iar_builtin_UQADD16
|
||||
#define __UHADD16 __iar_builtin_UHADD16
|
||||
#define __SSUB16 __iar_builtin_SSUB16
|
||||
#define __QSUB16 __iar_builtin_QSUB16
|
||||
#define __SHSUB16 __iar_builtin_SHSUB16
|
||||
#define __USUB16 __iar_builtin_USUB16
|
||||
#define __UQSUB16 __iar_builtin_UQSUB16
|
||||
#define __UHSUB16 __iar_builtin_UHSUB16
|
||||
#define __SASX __iar_builtin_SASX
|
||||
#define __QASX __iar_builtin_QASX
|
||||
#define __SHASX __iar_builtin_SHASX
|
||||
#define __UASX __iar_builtin_UASX
|
||||
#define __UQASX __iar_builtin_UQASX
|
||||
#define __UHASX __iar_builtin_UHASX
|
||||
#define __SSAX __iar_builtin_SSAX
|
||||
#define __QSAX __iar_builtin_QSAX
|
||||
#define __SHSAX __iar_builtin_SHSAX
|
||||
#define __USAX __iar_builtin_USAX
|
||||
#define __UQSAX __iar_builtin_UQSAX
|
||||
#define __UHSAX __iar_builtin_UHSAX
|
||||
#define __USAD8 __iar_builtin_USAD8
|
||||
#define __USADA8 __iar_builtin_USADA8
|
||||
#define __SSAT16 __iar_builtin_SSAT16
|
||||
#define __USAT16 __iar_builtin_USAT16
|
||||
#define __UXTB16 __iar_builtin_UXTB16
|
||||
#define __UXTAB16 __iar_builtin_UXTAB16
|
||||
#define __SXTB16 __iar_builtin_SXTB16
|
||||
#define __SXTAB16 __iar_builtin_SXTAB16
|
||||
#define __SMUAD __iar_builtin_SMUAD
|
||||
#define __SMUADX __iar_builtin_SMUADX
|
||||
#define __SMMLA __iar_builtin_SMMLA
|
||||
#define __SMLAD __iar_builtin_SMLAD
|
||||
#define __SMLADX __iar_builtin_SMLADX
|
||||
#define __SMLALD __iar_builtin_SMLALD
|
||||
#define __SMLALDX __iar_builtin_SMLALDX
|
||||
#define __SMUSD __iar_builtin_SMUSD
|
||||
#define __SMUSDX __iar_builtin_SMUSDX
|
||||
#define __SMLSD __iar_builtin_SMLSD
|
||||
#define __SMLSDX __iar_builtin_SMLSDX
|
||||
#define __SMLSLD __iar_builtin_SMLSLD
|
||||
#define __SMLSLDX __iar_builtin_SMLSLDX
|
||||
#define __SEL __iar_builtin_SEL
|
||||
#define __QADD __iar_builtin_QADD
|
||||
#define __QSUB __iar_builtin_QSUB
|
||||
#define __PKHBT __iar_builtin_PKHBT
|
||||
#define __PKHTB __iar_builtin_PKHTB
|
||||
#endif
|
||||
|
||||
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||
#define __CLZ __cmsis_iar_clz_not_active
|
||||
#define __SSAT __cmsis_iar_ssat_not_active
|
||||
#define __USAT __cmsis_iar_usat_not_active
|
||||
#define __RBIT __cmsis_iar_rbit_not_active
|
||||
#define __get_APSR __cmsis_iar_get_APSR_not_active
|
||||
#endif
|
||||
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
|
||||
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
|
||||
#endif
|
||||
|
||||
#ifdef __INTRINSICS_INCLUDED
|
||||
#error intrinsics.h is already included previously!
|
||||
#endif
|
||||
|
||||
#include <intrinsics.h>
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||
#undef __CLZ
|
||||
#undef __SSAT
|
||||
#undef __USAT
|
||||
#undef __RBIT
|
||||
#undef __get_APSR
|
||||
|
||||
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
|
||||
{
|
||||
if (data == 0U) { return 32U; }
|
||||
|
||||
uint32_t count = 0U;
|
||||
uint32_t mask = 0x80000000U;
|
||||
|
||||
while ((data & mask) == 0U)
|
||||
{
|
||||
count += 1U;
|
||||
mask = mask >> 1U;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
|
||||
{
|
||||
uint8_t sc = 31U;
|
||||
uint32_t r = v;
|
||||
for (v >>= 1U; v; v >>= 1U)
|
||||
{
|
||||
r <<= 1U;
|
||||
r |= v & 1U;
|
||||
sc--;
|
||||
}
|
||||
return (r << sc);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm("MRS %0,APSR" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||
#undef __get_FPSCR
|
||||
#undef __set_FPSCR
|
||||
#define __get_FPSCR() (0)
|
||||
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||
#endif
|
||||
|
||||
#pragma diag_suppress=Pe940
|
||||
#pragma diag_suppress=Pe177
|
||||
|
||||
#define __enable_irq __enable_interrupt
|
||||
#define __disable_irq __disable_interrupt
|
||||
#define __NOP __no_operation
|
||||
|
||||
#define __get_xPSR __get_PSR
|
||||
|
||||
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
|
||||
|
||||
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
|
||||
{
|
||||
return __LDREX((unsigned long *)ptr);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
|
||||
{
|
||||
return __STREX(value, (unsigned long *)ptr);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
__IAR_FT uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
|
||||
}
|
||||
|
||||
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
|
||||
}
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
__IAR_FT uint32_t __get_MSPLIM(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __set_MSPLIM(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __get_PSPLIM(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __set_PSPLIM(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_SP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,SP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR SP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||
|
||||
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||
|
||||
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
__ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
__ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
__ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
|
||||
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||
|
||||
#undef __IAR_FT
|
||||
#undef __IAR_M0_FAMILY
|
||||
#undef __ICCARM_V8
|
||||
|
||||
#pragma diag_default=Pe940
|
||||
#pragma diag_default=Pe177
|
||||
|
||||
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
|
||||
|
||||
#endif /* __CMSIS_ICCARM_H__ */
|
||||
@@ -0,0 +1,39 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.4
|
||||
* @date 23. July 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,952 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm0.h
|
||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||
* @version V5.0.8
|
||||
* @date 21. August 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0_H_GENERIC
|
||||
#define __CORE_CM0_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M0
|
||||
@{
|
||||
*/
|
||||
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS CM0 definitions */
|
||||
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_FP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM0_H_DEPENDANT
|
||||
#define __CORE_CM0_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0_REV
|
||||
#define __CM0_REV 0x0000U
|
||||
#warning "__CM0_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M0 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RESERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M0 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Core Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
|
||||
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||
#define __NVIC_GetPriorityGrouping() (0U)
|
||||
|
||||
/**
|
||||
\brief Enable Interrupt
|
||||
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
__COMPILER_BARRIER();
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__COMPILER_BARRIER();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status
|
||||
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt is not enabled.
|
||||
\return 1 Interrupt is enabled.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable Interrupt
|
||||
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
\note The priority cannot be set for every processor exception.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Encode Priority
|
||||
\details Encodes the priority for an interrupt with the given priority group,
|
||||
preemptive priority value, and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [in] SubPriority Subpriority value (starting from 0).
|
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
return (
|
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Decode Priority
|
||||
\details Decodes an interrupt priority value with a given priority group to
|
||||
preemptive priority value and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector
|
||||
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
Address 0 must be mapped to SRAM.
|
||||
\param [in] IRQn Interrupt number
|
||||
\param [in] vector Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
|
||||
*(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
|
||||
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Vector
|
||||
\details Reads an interrupt vector from interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
|
||||
return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
/* ########################## FPU functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||
\brief Function that provides FPU type.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief get FPU type
|
||||
\details returns the FPU type
|
||||
\returns
|
||||
- \b 0: No FPU
|
||||
- \b 1: Single precision FPU
|
||||
- \b 2: Double + Single precision FPU
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||
{
|
||||
return 0U; /* No FPU */
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,979 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm1.h
|
||||
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
|
||||
* @version V1.0.1
|
||||
* @date 12. November 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM1_H_GENERIC
|
||||
#define __CORE_CM1_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M1
|
||||
@{
|
||||
*/
|
||||
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS CM1 definitions */
|
||||
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (1U) /*!< Cortex-M Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_FP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM1_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM1_H_DEPENDANT
|
||||
#define __CORE_CM1_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM1_REV
|
||||
#define __CM1_REV 0x0100U
|
||||
#warning "__CM1_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M1 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
||||
\brief Type definitions for the System Control and ID Register not in the SCB
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control and ID Register not in the SCB.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RESERVED0[2U];
|
||||
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||
} SCnSCB_Type;
|
||||
|
||||
/* Auxiliary Control Register Definitions */
|
||||
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
|
||||
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
|
||||
|
||||
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
|
||||
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCnotSCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M1 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Core Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
|
||||
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||
#define __NVIC_GetPriorityGrouping() (0U)
|
||||
|
||||
/**
|
||||
\brief Enable Interrupt
|
||||
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
__COMPILER_BARRIER();
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__COMPILER_BARRIER();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status
|
||||
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt is not enabled.
|
||||
\return 1 Interrupt is enabled.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable Interrupt
|
||||
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
\note The priority cannot be set for every processor exception.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Encode Priority
|
||||
\details Encodes the priority for an interrupt with the given priority group,
|
||||
preemptive priority value, and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [in] SubPriority Subpriority value (starting from 0).
|
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
return (
|
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Decode Priority
|
||||
\details Decodes an interrupt priority value with a given priority group to
|
||||
preemptive priority value and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector
|
||||
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
Address 0 must be mapped to SRAM.
|
||||
\param [in] IRQn Interrupt number
|
||||
\param [in] vector Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||
/* ARM Application Note 321 states that the M1 does not require the architectural barrier */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Vector
|
||||
\details Reads an interrupt vector from interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
/* ########################## FPU functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||
\brief Function that provides FPU type.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief get FPU type
|
||||
\details returns the FPU type
|
||||
\returns
|
||||
- \b 0: No FPU
|
||||
- \b 1: Single precision FPU
|
||||
- \b 2: Double + Single precision FPU
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||
{
|
||||
return 0U; /* No FPU */
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM1_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,275 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.1.1
|
||||
* @date 10. February 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes
|
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
|
||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
(((MPU_RASR_ENABLE_Msk))))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory.
|
||||
* - TEX: 000b
|
||||
* - Shareable
|
||||
* - Non-cacheable
|
||||
* - Non-bufferable
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory.
|
||||
* - TEX: 000b (if shareable) or 010b (if non-shareable)
|
||||
* - Shareable or non-shareable
|
||||
* - Non-cacheable
|
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||
*
|
||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory.
|
||||
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||
* - Shareable or non-shareable
|
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||
*
|
||||
* \param OuterCp Configures the outer cache policy.
|
||||
* \param InnerCp Configures the inner cache policy.
|
||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,352 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv8.h
|
||||
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
|
||||
* @version V5.1.2
|
||||
* @date 10. February 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for normal memory (outer and inner)
|
||||
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
|
||||
|
||||
/** \brief Normal memory non-shareable */
|
||||
#define ARM_MPU_SH_NON (0U)
|
||||
|
||||
/** \brief Normal memory outer shareable */
|
||||
#define ARM_MPU_SH_OUTER (2U)
|
||||
|
||||
/** \brief Normal memory inner shareable */
|
||||
#define ARM_MPU_SH_INNER (3U)
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
(((BASE) & MPU_RBAR_BASE_Msk) | \
|
||||
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#if defined(MPU_RLAR_PXN_Pos)
|
||||
|
||||
/** \brief Region Limit Address Register with PXN value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
|
||||
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||
{
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RLAR = 0U;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RBAR = rbar;
|
||||
mpu->RLAR = rlar;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
mpu->RNR = rnr;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,337 @@
|
||||
/******************************************************************************
|
||||
* @file pmu_armv8.h
|
||||
* @brief CMSIS PMU API for Armv8.1-M PMU
|
||||
* @version V1.0.0
|
||||
* @date 24. March 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_PMU_ARMV8_H
|
||||
#define ARM_PMU_ARMV8_H
|
||||
|
||||
/**
|
||||
* \brief PMU Events
|
||||
* \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
|
||||
* */
|
||||
|
||||
#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
|
||||
#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
|
||||
#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
|
||||
#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */
|
||||
#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */
|
||||
#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */
|
||||
#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */
|
||||
#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */
|
||||
#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */
|
||||
#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */
|
||||
#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */
|
||||
#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */
|
||||
#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
|
||||
#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */
|
||||
#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */
|
||||
#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */
|
||||
#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */
|
||||
#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */
|
||||
#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */
|
||||
#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */
|
||||
#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */
|
||||
#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
|
||||
#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */
|
||||
#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */
|
||||
#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */
|
||||
#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */
|
||||
#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */
|
||||
#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */
|
||||
#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */
|
||||
#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */
|
||||
#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */
|
||||
#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */
|
||||
#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */
|
||||
#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */
|
||||
#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */
|
||||
#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */
|
||||
#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */
|
||||
#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */
|
||||
#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */
|
||||
#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */
|
||||
#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
|
||||
#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
|
||||
#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */
|
||||
#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */
|
||||
#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */
|
||||
#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */
|
||||
#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */
|
||||
#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */
|
||||
#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */
|
||||
#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */
|
||||
#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */
|
||||
#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */
|
||||
#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */
|
||||
#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */
|
||||
#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */
|
||||
#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */
|
||||
#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */
|
||||
#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */
|
||||
#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */
|
||||
#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */
|
||||
#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */
|
||||
#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */
|
||||
#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */
|
||||
#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */
|
||||
#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */
|
||||
|
||||
/** \brief PMU Functions */
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Enable(void);
|
||||
__STATIC_INLINE void ARM_PMU_Disable(void);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
|
||||
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
|
||||
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
|
||||
|
||||
/**
|
||||
\brief Enable the PMU
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Enable(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable the PMU
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Disable(void)
|
||||
{
|
||||
PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Set event to count for PMU eventer counter
|
||||
\param [in] num Event counter (0-30) to configure
|
||||
\param [in] type Event to count
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
|
||||
{
|
||||
PMU->EVTYPER[num] = type;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Reset cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Reset all event counters
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable counters
|
||||
\param [in] mask Counters to enable
|
||||
\note Enables one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
|
||||
{
|
||||
PMU->CNTENSET = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable counters
|
||||
\param [in] mask Counters to enable
|
||||
\note Disables one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
|
||||
{
|
||||
PMU->CNTENCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read cycle counter
|
||||
\return Cycle count
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
|
||||
{
|
||||
return PMU->CCNTR;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read event counter
|
||||
\param [in] num Event counter (0-30) to read
|
||||
\return Event count
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
|
||||
{
|
||||
return PMU->EVCNTR[num];
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read counter overflow status
|
||||
\return Counter overflow status bits for the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
|
||||
{
|
||||
return PMU->OVSSET;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Clear counter overflow status
|
||||
\param [in] mask Counter overflow status bits to clear
|
||||
\note Clears overflow status bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
|
||||
{
|
||||
PMU->OVSCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable counter overflow interrupt request
|
||||
\param [in] mask Counter overflow interrupt request bits to set
|
||||
\note Sets overflow interrupt request bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
|
||||
{
|
||||
PMU->INTENSET = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable counter overflow interrupt request
|
||||
\param [in] mask Counter overflow interrupt request bits to clear
|
||||
\note Clears overflow interrupt request bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
|
||||
{
|
||||
PMU->INTENCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Software increment event counter
|
||||
\param [in] mask Counters to increment
|
||||
\note Software increment bits for one or more event counters (0-30)
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
|
||||
{
|
||||
PMU->SWINC = mask;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,70 @@
|
||||
/******************************************************************************
|
||||
* @file tz_context.h
|
||||
* @brief Context Management for Armv8-M TrustZone
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef TZ_CONTEXT_H
|
||||
#define TZ_CONTEXT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t;
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
@@ -0,0 +1,160 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/** \file ddl_config.h
|
||||
**
|
||||
** A detailed description is available at
|
||||
** @link DdlConfigGroup Ddl Config description @endlink
|
||||
**
|
||||
** - 2021-04-16 CDT First version for Device Driver Library config.
|
||||
**
|
||||
******************************************************************************/
|
||||
#ifndef __DDL_CONFIG_H__
|
||||
#define __DDL_CONFIG_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \defgroup DdlConfigGroup Device Driver Library config(DDLCONFIG)
|
||||
**
|
||||
******************************************************************************/
|
||||
//@{
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/*! Chip module on-off define */
|
||||
#define DDL_ON (1u)
|
||||
#define DDL_OFF (0u)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief This is the list of modules to be used in the device driver library
|
||||
** Select the modules you need to use to DDL_ON.
|
||||
**
|
||||
** \note DDL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
|
||||
** properly.
|
||||
**
|
||||
** \note DDL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
|
||||
** Library.
|
||||
**
|
||||
** \note DDL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
|
||||
******************************************************************************/
|
||||
#define DDL_ICG_ENABLE (DDL_ON)
|
||||
#define DDL_UTILITY_ENABLE (DDL_ON)
|
||||
#define DDL_PRINT_ENABLE (DDL_OFF)
|
||||
|
||||
#define DDL_ADC_ENABLE (DDL_ON)
|
||||
#define DDL_AES_ENABLE (DDL_OFF)
|
||||
#define DDL_CAN_ENABLE (DDL_OFF)
|
||||
#define DDL_CLK_ENABLE (DDL_ON)
|
||||
#define DDL_CMP_ENABLE (DDL_OFF)
|
||||
#define DDL_CRC_ENABLE (DDL_OFF)
|
||||
#define DDL_DCU_ENABLE (DDL_OFF)
|
||||
#define DDL_DMAC_ENABLE (DDL_ON)
|
||||
#define DDL_EFM_ENABLE (DDL_ON)
|
||||
#define DDL_EMB_ENABLE (DDL_OFF)
|
||||
#define DDL_EVENT_PORT_ENABLE (DDL_OFF)
|
||||
#define DDL_EXINT_NMI_SWI_ENABLE (DDL_ON)
|
||||
#define DDL_GPIO_ENABLE (DDL_ON)
|
||||
#define DDL_HASH_ENABLE (DDL_OFF)
|
||||
#define DDL_I2C_ENABLE (DDL_OFF)
|
||||
#define DDL_I2S_ENABLE (DDL_OFF)
|
||||
#define DDL_INTERRUPTS_ENABLE (DDL_ON)
|
||||
#define DDL_INTERRUPTS_SHARE_ENABLE (DDL_OFF)
|
||||
#define DDL_KEYSCAN_ENABLE (DDL_OFF)
|
||||
#define DDL_MPU_ENABLE (DDL_OFF)
|
||||
#define DDL_OTS_ENABLE (DDL_OFF)
|
||||
#define DDL_PWC_ENABLE (DDL_ON)
|
||||
#define DDL_QSPI_ENABLE (DDL_OFF)
|
||||
#define DDL_RMU_ENABLE (DDL_OFF)
|
||||
#define DDL_RTC_ENABLE (DDL_ON)
|
||||
#define DDL_SDIOC_ENABLE (DDL_ON)
|
||||
#define DDL_SPI_ENABLE (DDL_ON)
|
||||
#define DDL_SRAM_ENABLE (DDL_ON)
|
||||
#define DDL_SWDT_ENABLE (DDL_ON)
|
||||
#define DDL_TIMER0_ENABLE (DDL_OFF)
|
||||
#define DDL_TIMER4_CNT_ENABLE (DDL_OFF)
|
||||
#define DDL_TIMER4_EMB_ENABLE (DDL_OFF)
|
||||
#define DDL_TIMER4_OCO_ENABLE (DDL_OFF)
|
||||
#define DDL_TIMER4_PWM_ENABLE (DDL_OFF)
|
||||
#define DDL_TIMER4_SEVT_ENABLE (DDL_OFF)
|
||||
#define DDL_TIMER6_ENABLE (DDL_OFF)
|
||||
#define DDL_TIMERA_ENABLE (DDL_OFF)
|
||||
#define DDL_TRNG_ENABLE (DDL_OFF)
|
||||
#define DDL_USART_ENABLE (DDL_ON)
|
||||
#define DDL_USBFS_ENABLE (DDL_OFF)
|
||||
#define DDL_WDT_ENABLE (DDL_OFF)
|
||||
|
||||
|
||||
/*! Midware module on-off define */
|
||||
#define MW_ON (1u)
|
||||
#define MW_OFF (0u)
|
||||
|
||||
/**
|
||||
*******************************************************************************
|
||||
** \brief This is the list of Midware modules to use
|
||||
** Select the modules you need to use to MW_ON.
|
||||
******************************************************************************/
|
||||
#define MW_FS_ENABLE (MW_OFF)
|
||||
#define MW_SD_CARD_ENABLE (MW_OFF)
|
||||
#define MW_W25QXX_ENABLE (MW_OFF)
|
||||
#define MW_WM8731_ENABLE (MW_OFF)
|
||||
|
||||
/* BSP on-off define */
|
||||
#define BSP_ON (1u)
|
||||
#define BSP_OFF (0u)
|
||||
|
||||
/**
|
||||
* @brief The following is a list of currently supported BSP boards.
|
||||
*/
|
||||
#define BSP_EV_HC32F460_LQFP100_V1 (1u)
|
||||
#define BSP_EV_HC32F460_LQFP100_V2 (2u)
|
||||
|
||||
/**
|
||||
* @brief The macro BSP_EV_HC32F460 is used to specify the BSP board currently
|
||||
* in use.
|
||||
* The value should be set to one of the list of currently supported BSP boards.
|
||||
* @note If there is no supported BSP board or the BSP function is not used,
|
||||
* the value needs to be set to BSP_EV_HC32F460.
|
||||
*/
|
||||
#define BSP_EV_HC32F460 (BSP_EV_HC32F460_LQFP100_V2)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
//@} // DdlConfigGroup
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DDL_CONFIG_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,317 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll.h
|
||||
* @brief This file contains HC32 Series Device Driver Library file call
|
||||
* management.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2023-01-15 CDT Modify version as 3.1.0
|
||||
2023-09-30 CDT Modify version as 3.2.0
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_H__
|
||||
#define __HC32_LL_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Global
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup LL_Global_Macros LL Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup Peripheral_Register_WP_Global_Macros Peripheral Register Write Protection Global Macros
|
||||
* @{
|
||||
*/
|
||||
#define LL_PERIPH_EFM (1UL << 0U)
|
||||
#define LL_PERIPH_FCG (1UL << 1U)
|
||||
#define LL_PERIPH_GPIO (1UL << 2U)
|
||||
#define LL_PERIPH_INTC (1UL << 3U)
|
||||
#define LL_PERIPH_LVD (1UL << 4U)
|
||||
#define LL_PERIPH_MPU (1UL << 5U)
|
||||
#define LL_PERIPH_PWC_CLK_RMU (1UL << 6U)
|
||||
#define LL_PERIPH_SRAM (1UL << 7U)
|
||||
#define LL_PERIPH_ALL (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_GPIO | LL_PERIPH_INTC | \
|
||||
LL_PERIPH_LVD | LL_PERIPH_MPU | LL_PERIPH_SRAM | LL_PERIPH_PWC_CLK_RMU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Defined use Device Driver Library */
|
||||
#if !defined (USE_DDL_DRIVER)
|
||||
/**
|
||||
* @brief Comment the line below if you will not use the Device Driver Library.
|
||||
* In this case, the application code will be based on direct access to
|
||||
* peripherals registers.
|
||||
*/
|
||||
/* #define USE_DDL_DRIVER */
|
||||
#endif /* USE_DDL_DRIVER */
|
||||
|
||||
/**
|
||||
* @defgroup HC32_Series_DDL_Release_Version HC32 Series DDL Release Version
|
||||
* @{
|
||||
*/
|
||||
#define HC32_DDL_REV_MAIN 0x03U /*!< [31:24] main version */
|
||||
#define HC32_DDL_REV_SUB1 0x02U /*!< [23:16] sub1 version */
|
||||
#define HC32_DDL_REV_SUB2 0x00U /*!< [15:8] sub2 version */
|
||||
#define HC32_DDL_REV_PATCH 0x00U /*!< [7:0] patch version */
|
||||
#define HC32_DDL_REV ((HC32_DDL_REV_MAIN << 24) | (HC32_DDL_REV_SUB1 << 16) | \
|
||||
(HC32_DDL_REV_SUB2 << 8 ) | (HC32_DDL_REV_PATCH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Use Device Driver Library */
|
||||
#if defined (USE_DDL_DRIVER)
|
||||
|
||||
/**
|
||||
* @brief Include peripheral module's header file
|
||||
*/
|
||||
#if (LL_ADC_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_adc.h"
|
||||
#endif /* LL_ADC_ENABLE */
|
||||
|
||||
#if (LL_AES_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_aes.h"
|
||||
#endif /* LL_AES_ENABLE */
|
||||
|
||||
#if (LL_AOS_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_aos.h"
|
||||
#endif /* LL_AOS_ENABLE */
|
||||
|
||||
#if (LL_CAN_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_can.h"
|
||||
#endif /* LL_CAN_ENABLE */
|
||||
|
||||
#if (LL_CLK_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_clk.h"
|
||||
#endif /* LL_CLK_ENABLE */
|
||||
|
||||
#if (LL_CMP_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_cmp.h"
|
||||
#endif /* LL_CMP_ENABLE */
|
||||
|
||||
#if (LL_CRC_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_crc.h"
|
||||
#endif /* LL_CRC_ENABLE */
|
||||
|
||||
#if (LL_DBGC_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_dbgc.h"
|
||||
#endif /* LL_DBGC_ENABLE */
|
||||
|
||||
#if (LL_DCU_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_dcu.h"
|
||||
#endif /* LL_DCU_ENABLE */
|
||||
|
||||
#if (LL_DMA_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_dma.h"
|
||||
#endif /* LL_DMA_ENABLE */
|
||||
|
||||
#if (LL_EFM_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_efm.h"
|
||||
#endif /* LL_EFM_ENABLE */
|
||||
|
||||
#if (LL_EMB_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_emb.h"
|
||||
#endif /* LL_EMB_ENABLE */
|
||||
|
||||
#if (LL_EVENT_PORT_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_event_port.h"
|
||||
#endif /* LL_EVENT_PORT_ENABLE */
|
||||
|
||||
#if (LL_FCG_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_fcg.h"
|
||||
#endif /* LL_FCG_ENABLE */
|
||||
|
||||
#if (LL_FCM_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_fcm.h"
|
||||
#endif /* LL_FCM_ENABLE */
|
||||
|
||||
#if (LL_GPIO_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_gpio.h"
|
||||
#endif /* LL_GPIO_ENABLE */
|
||||
|
||||
#if (LL_HASH_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_hash.h"
|
||||
#endif /* LL_HASH_ENABLE */
|
||||
|
||||
#if (LL_I2C_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_i2c.h"
|
||||
#endif /* LL_I2C_ENABLE */
|
||||
|
||||
#if (LL_I2S_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_i2s.h"
|
||||
#endif /* LL_I2S_ENABLE */
|
||||
|
||||
#if (LL_ICG_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_icg.h"
|
||||
#endif /* LL_ICG_ENABLE */
|
||||
|
||||
#if (LL_INTERRUPTS_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_interrupts.h"
|
||||
#endif /* LL_INTERRUPTS_ENABLE */
|
||||
|
||||
#if (LL_INTERRUPTS_SHARE_ENABLE == DDL_ON)
|
||||
#include "hc32f460_ll_interrupts_share.h"
|
||||
#endif /* LL_INTERRUPTS_ENABLE */
|
||||
|
||||
#if (LL_KEYSCAN_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_keyscan.h"
|
||||
#endif /* LL_KEYSCAN_ENABLE */
|
||||
|
||||
#if (LL_MPU_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_mpu.h"
|
||||
#endif /* LL_MPU_ENABLE */
|
||||
|
||||
#if (LL_OTS_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_ots.h"
|
||||
#endif /* LL_OTS_ENABLE */
|
||||
|
||||
#if (LL_PWC_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_pwc.h"
|
||||
#endif /* LL_PWC_ENABLE */
|
||||
|
||||
#if (LL_QSPI_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_qspi.h"
|
||||
#endif /* LL_QSPI_ENABLE */
|
||||
|
||||
#if (LL_RMU_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_rmu.h"
|
||||
#endif /* LL_RMU_ENABLE */
|
||||
|
||||
#if (LL_RTC_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_rtc.h"
|
||||
#endif /* LL_RTC_ENABLE */
|
||||
|
||||
#if (LL_SDIOC_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_sdioc.h"
|
||||
#endif /* LL_SDIOC_ENABLE */
|
||||
|
||||
#if (LL_SPI_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_spi.h"
|
||||
#endif /* LL_SPI_ENABLE */
|
||||
|
||||
#if (LL_SRAM_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_sram.h"
|
||||
#endif /* LL_SRAM_ENABLE */
|
||||
|
||||
#if (LL_SWDT_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_swdt.h"
|
||||
#endif /* LL_SWDT_ENABLE */
|
||||
|
||||
#if (LL_TMR0_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_tmr0.h"
|
||||
#endif /* LL_TMR0_ENABLE */
|
||||
|
||||
#if (LL_TMR4_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_tmr4.h"
|
||||
#endif /* LL_TMR4_ENABLE */
|
||||
|
||||
#if (LL_TMR6_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_tmr6.h"
|
||||
#endif /* LL_TMR6_ENABLE */
|
||||
|
||||
#if (LL_TMRA_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_tmra.h"
|
||||
#endif /* LL_TMRA_ENABLE */
|
||||
|
||||
#if (LL_TRNG_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_trng.h"
|
||||
#endif /* LL_TRNG_ENABLE */
|
||||
|
||||
#if (LL_USART_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_usart.h"
|
||||
#endif /* LL_USART_ENABLE */
|
||||
|
||||
#if (LL_UTILITY_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_utility.h"
|
||||
#endif /* LL_UTILITY_ENABLE */
|
||||
|
||||
#if (LL_USB_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_usb.h"
|
||||
#endif /* LL_USB_ENABLE */
|
||||
|
||||
#if (LL_WDT_ENABLE == DDL_ON)
|
||||
#include "hc32_ll_wdt.h"
|
||||
#endif /* LL_WDT_ENABLE */
|
||||
|
||||
#endif /* USE_DDL_DRIVER */
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup LL_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
void LL_PERIPH_WE(uint32_t u32Peripheral);
|
||||
void LL_PERIPH_WP(uint32_t u32Peripheral);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_DDL_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,499 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_adc.h
|
||||
* @brief This file contains all the functions prototypes of the ADC driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2022-10-31 CDT Modify macro group definition: ADC_Scan_Mode, ADC_Sync_Unit, ADC_Sync_Mode
|
||||
2023-06-30 CDT Modify typo
|
||||
API fixed: ADC_DeInit()
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_ADC_H__
|
||||
#define __HC32_LL_ADC_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_ADC_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup ADC_Global_Types ADC Global Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Structure definition of analog watchdog(AWD) configuration.
|
||||
*/
|
||||
typedef struct {
|
||||
uint16_t u16WatchdogMode; /*!< Specifies the ADC analog watchdog mode.
|
||||
This parameter can be a value of @ref ADC_AWD_Mode */
|
||||
uint16_t u16LowThreshold; /*!< Specifies the ADC analog watchdog Low threshold value. */
|
||||
uint16_t u16HighThreshold; /*!< Specifies the ADC analog watchdog High threshold value. */
|
||||
} stc_adc_awd_config_t;
|
||||
|
||||
/**
|
||||
* @brief Structure definition of ADC initialization.
|
||||
*/
|
||||
typedef struct {
|
||||
uint16_t u16ScanMode; /*!< Specifies the ADC scan convert mode.
|
||||
This parameter can be a value of @ref ADC_Scan_Mode */
|
||||
uint16_t u16Resolution; /*!< Specifies the ADC resolution.
|
||||
This parameter can be a value of @ref ADC_Resolution */
|
||||
uint16_t u16DataAlign; /*!< Specifies ADC data alignment.
|
||||
This parameter can be a value of @ref ADC_Data_Align */
|
||||
} stc_adc_init_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup ADC_Global_Macros ADC Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_Sequence ADC Sequence
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SEQ_A (0U) /*!< ADC sequence A. */
|
||||
#define ADC_SEQ_B (1U) /*!< ADC sequence B. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_Channel ADC Channel
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CH0 (0U) /*!< Default input pin: PA0 for ADC1, PA4 for ADC2. */
|
||||
#define ADC_CH1 (1U) /*!< Default input pin: PA1 for ADC1, PA5 for ADC2. */
|
||||
#define ADC_CH2 (2U) /*!< Default input pin: PA2 for ADC1, PA6 for ADC2. */
|
||||
#define ADC_CH3 (3U) /*!< Default input pin: PA3 for ADC1, PA7 for ADC2. */
|
||||
#define ADC_CH4 (4U) /*!< Default input pin: PA4 for ADC1, PB0 for ADC2. */
|
||||
#define ADC_CH5 (5U) /*!< Default input pin: PA5 for ADC1, PB1 for ADC2. */
|
||||
#define ADC_CH6 (6U) /*!< Default input pin: PA6 for ADC1, PC0 for ADC2. */
|
||||
#define ADC_CH7 (7U) /*!< Default input pin: PA7 for ADC1, PC1 for ADC2. */
|
||||
#define ADC_CH8 (8U) /*!< Default input pin: PB0 for ADC1, internal analog signal for ADC2. */
|
||||
#define ADC_CH9 (9U) /*!< Default input pin: PB1 for ADC1, NOT support ADC2. */
|
||||
#define ADC_CH10 (10U) /*!< Default input pin: PC0 for ADC1, NOT support ADC2. */
|
||||
#define ADC_CH11 (11U) /*!< Default input pin: PC1 for ADC1, NOT support ADC2. */
|
||||
#define ADC_CH12 (12U) /*!< Default input pin: PC2 for ADC1, NOT support ADC2. */
|
||||
#define ADC_CH13 (13U) /*!< Default input pin: PC3 for ADC1, NOT support ADC2. */
|
||||
#define ADC_CH14 (14U) /*!< Default input pin: PC4 for ADC1, NOT support ADC2. */
|
||||
#define ADC_CH15 (15U) /*!< Default input pin: PC5 for ADC1, NOT support ADC2. */
|
||||
#define ADC_CH16 (16U) /*!< ADC1 extended channel, input source is internal analog signal */
|
||||
|
||||
#define ADC1_EXT_CH (ADC_CH16) /*!< ADC1 extended channel, input source is internal analog signal:
|
||||
internal reference voltage or 8bit-DAC. */
|
||||
#define ADC2_EXT_CH (ADC_CH8) /*!< ADC2 extended channel, input source is internal analog signal:
|
||||
internal reference voltage or 8bit-DAC. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_Scan_Mode ADC Scan Convert Mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_MD_SEQA_SINGLESHOT (0x0U) /*!< Sequence A single shot. Sequence B is disabled. */
|
||||
#define ADC_MD_SEQA_CONT (0x1U << ADC_CR0_MS_POS) /*!< Sequence A continuous. Sequence B is disabled. */
|
||||
#define ADC_MD_SEQA_SEQB_SINGLESHOT (0x2U << ADC_CR0_MS_POS) /*!< Sequence A and B both single shot. */
|
||||
#define ADC_MD_SEQA_CONT_SEQB_SINGLESHOT (0x3U << ADC_CR0_MS_POS) /*!< Sequence A continuous and sequence B single shot. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_Resolution ADC Resolution
|
||||
* @{
|
||||
*/
|
||||
#define ADC_RESOLUTION_12BIT (0x0U) /*!< Resolution is 12 bit. */
|
||||
#define ADC_RESOLUTION_10BIT (ADC_CR0_ACCSEL_0) /*!< Resolution is 10 bit. */
|
||||
#define ADC_RESOLUTION_8BIT (ADC_CR0_ACCSEL_1) /*!< Resolution is 8 bit. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_Data_Align ADC Data Align
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DATAALIGN_RIGHT (0x0U) /*!< Right alignment of converted data. */
|
||||
#define ADC_DATAALIGN_LEFT (ADC_CR0_DFMT) /*!< Left alignment of converted data. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_Average_Count ADC Average Count
|
||||
* @{
|
||||
*/
|
||||
#define ADC_AVG_CNT2 (0x0U) /*!< 2 consecutive average conversions. */
|
||||
#define ADC_AVG_CNT4 (0x1U << ADC_CR0_AVCNT_POS) /*!< 4 consecutive average conversions. */
|
||||
#define ADC_AVG_CNT8 (0x2U << ADC_CR0_AVCNT_POS) /*!< 8 consecutive average conversions. */
|
||||
#define ADC_AVG_CNT16 (0x3U << ADC_CR0_AVCNT_POS) /*!< 16 consecutive average conversions. */
|
||||
#define ADC_AVG_CNT32 (0x4U << ADC_CR0_AVCNT_POS) /*!< 32 consecutive average conversions. */
|
||||
#define ADC_AVG_CNT64 (0x5U << ADC_CR0_AVCNT_POS) /*!< 64 consecutive average conversions. */
|
||||
#define ADC_AVG_CNT128 (0x6U << ADC_CR0_AVCNT_POS) /*!< 128 consecutive average conversions. */
|
||||
#define ADC_AVG_CNT256 (0x7U << ADC_CR0_AVCNT_POS) /*!< 256 consecutive average conversions. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_SeqA_Resume_Mode ADC Sequence A Resume Mode
|
||||
* @brief After interrupted by sequence B, sequence A continues to scan from the interrupt channel or the first channel.
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SEQA_RESUME_SCAN_CONT (0U) /*!< Scanning will continue from the interrupted channel. */
|
||||
#define ADC_SEQA_RESUME_SCAN_RESTART (ADC_CR1_RSCHSEL) /*!< Scanning will start from the first channel. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_Hard_Trigger_Sel ADC Hard Trigger Selection
|
||||
* @{
|
||||
*/
|
||||
#define ADC_HARDTRIG_ADTRG_PIN (0x0U) /*!< Selects the following edge of pin ADTRG as the trigger of ADC sequence. */
|
||||
#define ADC_HARDTRIG_EVT0 (ADC_TRGSR_TRGSELA_0) /*!< Selects an internal event as the trigger of ADC sequence.
|
||||
This event is specified by register ADCx_TRGSEL0(x=(null), 1, 2, 3). */
|
||||
#define ADC_HARDTRIG_EVT1 (ADC_TRGSR_TRGSELA_1) /*!< Selects an internal event as the trigger of ADC sequence.
|
||||
This event is specified by register ADCx_TRGSEL1(x=(null), 1, 2, 3). */
|
||||
#define ADC_HARDTRIG_EVT0_EVT1 (ADC_TRGSR_TRGSELA) /*!< Selects two internal events as the trigger of ADC sequence.
|
||||
The two events are specified by register ADCx_TRGSEL0 and register ADCx_TRGSEL1. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_Int_Type ADC Interrupt Type
|
||||
* @{
|
||||
*/
|
||||
#define ADC_INT_EOCA (ADC_ICR_EOCAIEN) /*!< Interrupt of the end of conversion of sequence A. */
|
||||
#define ADC_INT_EOCB (ADC_ICR_EOCBIEN) /*!< Interrupt of the end of conversion of sequence B. */
|
||||
#define ADC_INT_ALL (ADC_INT_EOCA | ADC_INT_EOCB)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_Status_Flag ADC Status Flag
|
||||
* @{
|
||||
*/
|
||||
#define ADC_FLAG_EOCA (ADC_ISR_EOCAF) /*!< Status flag of the end of conversion of sequence A. */
|
||||
#define ADC_FLAG_EOCB (ADC_ISR_EOCBF) /*!< Status flag of the end of conversion of sequence B. */
|
||||
#define ADC_FLAG_ALL (ADC_FLAG_EOCA | ADC_FLAG_EOCB)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_Sync_Unit ADC Synchronous Unit
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SYNC_ADC1_ADC2 (0U) /*!< ADC1 and ADC2 work synchronously. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_Sync_Mode ADC Synchronous Mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SYNC_SINGLE_DELAY_TRIG (0U) /*!< Single shot delayed trigger mode.
|
||||
When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has).
|
||||
All ADCs scan once. */
|
||||
#define ADC_SYNC_SINGLE_PARALLEL_TRIG (0x2U << ADC_SYNCCR_SYNCMD_POS) /*!< Single shot parallel trigger mode.
|
||||
When the trigger condition occurs, all ADCs start at the same time.
|
||||
All ADCs scan once. */
|
||||
#define ADC_SYNC_CYCLIC_DELAY_TRIG (0x4U << ADC_SYNCCR_SYNCMD_POS) /*!< Cyclic delayed trigger mode.
|
||||
When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has).
|
||||
All ADCs scan cyclicly(keep scanning till you stop them). */
|
||||
#define ADC_SYNC_CYCLIC_PARALLEL_TRIG (0x6U << ADC_SYNCCR_SYNCMD_POS) /*!< Single shot parallel trigger mode.
|
||||
When the trigger condition occurs, all ADCs start at the same time.
|
||||
All ADCs scan cyclicly(keep scanning till you stop them). */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_AWD_Unit ADC Analog Watchdog Unit
|
||||
* @{
|
||||
*/
|
||||
#define ADC_AWD0 (0U) /*!< ADC analog watchdog 0. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_AWD_Int_Type ADC AWD Interrupt Type
|
||||
* @{
|
||||
*/
|
||||
#define ADC_AWD_INT_SEQA (ADC_AWDCR_AWDSS_0) /*!< Interrupt of AWD sequence A. */
|
||||
#define ADC_AWD_INT_SEQB (ADC_AWDCR_AWDSS_1) /*!< Interrupt of AWD sequence B. */
|
||||
#define ADC_AWD_INT_ALL (ADC_AWDCR_AWDSS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_AWD_Mode ADC Analog Watchdog Mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_AWD_MD_CMP_OUT (0x0U) /*!< ADCValue > HighThreshold or ADCValue < LowThreshold */
|
||||
#define ADC_AWD_MD_CMP_IN (0x1U) /*!< LowThreshold < ADCValue < HighThreshold */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_AWD_Status_Flag ADC AWD Status Flag
|
||||
* @{
|
||||
*/
|
||||
#define ADC_AWD_FLAG_CH0 (1UL << ADC_CH0)
|
||||
#define ADC_AWD_FLAG_CH1 (1UL << ADC_CH1)
|
||||
#define ADC_AWD_FLAG_CH2 (1UL << ADC_CH2)
|
||||
#define ADC_AWD_FLAG_CH3 (1UL << ADC_CH3)
|
||||
#define ADC_AWD_FLAG_CH4 (1UL << ADC_CH4)
|
||||
#define ADC_AWD_FLAG_CH5 (1UL << ADC_CH5)
|
||||
#define ADC_AWD_FLAG_CH6 (1UL << ADC_CH6)
|
||||
#define ADC_AWD_FLAG_CH7 (1UL << ADC_CH7)
|
||||
#define ADC_AWD_FLAG_CH8 (1UL << ADC_CH8)
|
||||
#define ADC_AWD_FLAG_CH9 (1UL << ADC_CH9)
|
||||
#define ADC_AWD_FLAG_CH10 (1UL << ADC_CH10)
|
||||
#define ADC_AWD_FLAG_CH11 (1UL << ADC_CH11)
|
||||
#define ADC_AWD_FLAG_CH12 (1UL << ADC_CH12)
|
||||
#define ADC_AWD_FLAG_CH13 (1UL << ADC_CH13)
|
||||
#define ADC_AWD_FLAG_CH14 (1UL << ADC_CH14)
|
||||
#define ADC_AWD_FLAG_CH15 (1UL << ADC_CH15)
|
||||
#define ADC_AWD_FLAG_CH16 (1UL << ADC_CH16)
|
||||
#define ADC1_AWD_FLAG_ALL (0x1FFFFUL)
|
||||
#define ADC2_AWD_FLAG_ALL (0x1FFUL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_PGA_Unit ADC PGA Unit
|
||||
* @{
|
||||
*/
|
||||
#define ADC_PGA1 (0U) /*!< PGA1, belongs to ADC1. Input source can one of @ref ADC_PGA_Input_Src */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_PGA_Gain ADC PGA Gain Factor
|
||||
* @{
|
||||
*/
|
||||
#define ADC_PGA_GAIN_2 (0x0U) /*!< PGA gain factor is 2. */
|
||||
#define ADC_PGA_GAIN_2P133 (0x1U) /*!< PGA gain factor is 2.133. */
|
||||
#define ADC_PGA_GAIN_2P286 (0x2U) /*!< PGA gain factor is 2.286. */
|
||||
#define ADC_PGA_GAIN_2P667 (0x3U) /*!< PGA gain factor is 2.667. */
|
||||
#define ADC_PGA_GAIN_2P909 (0x4U) /*!< PGA gain factor is 2.909. */
|
||||
#define ADC_PGA_GAIN_3P2 (0x5U) /*!< PGA gain factor is 3.2. */
|
||||
#define ADC_PGA_GAIN_3P556 (0x6U) /*!< PGA gain factor is 2.556. */
|
||||
#define ADC_PGA_GAIN_4 (0x7U) /*!< PGA gain factor is 4. */
|
||||
#define ADC_PGA_GAIN_4P571 (0x8U) /*!< PGA gain factor is 4.571. */
|
||||
#define ADC_PGA_GAIN_5P333 (0x9U) /*!< PGA gain factor is 5.333. */
|
||||
#define ADC_PGA_GAIN_6P4 (0xAU) /*!< PGA gain factor is 6.4. */
|
||||
#define ADC_PGA_GAIN_8 (0xBU) /*!< PGA gain factor is 8. */
|
||||
#define ADC_PGA_GAIN_10P667 (0xCU) /*!< PGA gain factor is 10.667. */
|
||||
#define ADC_PGA_GAIN_16 (0xDU) /*!< PGA gain factor is 16. */
|
||||
#define ADC_PGA_GAIN_32 (0xEU) /*!< PGA gain factor is 32. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_PGA_VSS ADC PGA VSS
|
||||
* @{
|
||||
*/
|
||||
#define ADC_PGA_VSS_PGAVSS (0U) /*!< Use pin PGAx_VSS as the reference GND of PGAx. */
|
||||
#define ADC_PGA_VSS_AVSS (1U) /*!< Use AVSS as the reference GND of PGAx. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_PGA_Input_Src ADC PGA Input Source
|
||||
* @{
|
||||
*/
|
||||
#define ADC_PGA_PIN_ADC1_PA0 (ADC_PGAINSR0_PGAINSEL_0) /*!< ADC1 pin ADC1_IN0(PA0). */
|
||||
#define ADC_PGA_PIN_ADC1_PA1 (ADC_PGAINSR0_PGAINSEL_1) /*!< ADC1 pin ADC1_IN1(PA1). */
|
||||
#define ADC_PGA_PIN_ADC1_PA2 (ADC_PGAINSR0_PGAINSEL_2) /*!< ADC1 pin ADC1_IN2(PA2). */
|
||||
#define ADC_PGA_PIN_ADC1_PA3 (ADC_PGAINSR0_PGAINSEL_3) /*!< ADC1 pin ADC1_IN3(PA3). */
|
||||
#define ADC_PGA_PIN_ADC1_PA4 (ADC_PGAINSR0_PGAINSEL_4) /*!< ADC1 pin ADC12_IN4(PA4). */
|
||||
#define ADC_PGA_PIN_ADC1_PA5 (ADC_PGAINSR0_PGAINSEL_5) /*!< ADC1 pin ADC12_IN5(PA5). */
|
||||
#define ADC_PGA_PIN_ADC1_PA6 (ADC_PGAINSR0_PGAINSEL_6) /*!< ADC1 pin ADC12_IN6(PA6). */
|
||||
#define ADC_PGA_PIN_ADC1_PA7 (ADC_PGAINSR0_PGAINSEL_7) /*!< ADC1 pin ADC12_IN7(PA7). */
|
||||
#define ADC_PGA_8BIT_DAC (ADC_PGAINSR0_PGAINSEL_8) /*!< Internal 8bit-DAC to ADC1. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ADC_Remap_Pin ADC Remap Pin
|
||||
* @{
|
||||
*/
|
||||
#define ADC1_PIN_PA0 (0U) /*!< ADC1_IN0(PA0): default channel is ADC_CH0 of ADC1. */
|
||||
#define ADC1_PIN_PA1 (1U) /*!< ADC1_IN1(PA1): default channel is ADC_CH1 of ADC1. */
|
||||
#define ADC1_PIN_PA2 (2U) /*!< ADC1_IN2(PA2): default channel is ADC_CH2 of ADC1. */
|
||||
#define ADC1_PIN_PA3 (3U) /*!< ADC1_IN3(PA3): default channel is ADC_CH3 of ADC1. */
|
||||
#define ADC1_PIN_PA4 (4U) /*!< ADC12_IN4(PA4): default channel is ADC_CH4 of ADC1. */
|
||||
#define ADC1_PIN_PA5 (5U) /*!< ADC12_IN5(PA5): default channel is ADC_CH5 of ADC1. */
|
||||
#define ADC1_PIN_PA6 (6U) /*!< ADC12_IN6(PA6): default channel is ADC_CH6 of ADC1. */
|
||||
#define ADC1_PIN_PA7 (7U) /*!< ADC12_IN7(PA7): default channel is ADC_CH7 of ADC1. */
|
||||
#define ADC1_PIN_PB0 (8U) /*!< ADC12_IN8(PB0): default channel is ADC_CH8 of ADC1. */
|
||||
#define ADC1_PIN_PB1 (9U) /*!< ADC12_IN9(PB1): default channel is ADC_CH9 of ADC1. */
|
||||
#define ADC1_PIN_PC0 (10U) /*!< ADC12_IN10(PC0): default channel is ADC_CH10 of ADC1. */
|
||||
#define ADC1_PIN_PC1 (11U) /*!< ADC12_IN11(PC1): default channel is ADC_CH11 of ADC1. */
|
||||
#define ADC1_PIN_PC2 (12U) /*!< ADC1_IN12(PC2): default channel is ADC_CH12 of ADC1. */
|
||||
#define ADC1_PIN_PC3 (13U) /*!< ADC1_IN13(PC3): default channel is ADC_CH13 of ADC1. */
|
||||
#define ADC1_PIN_PC4 (14U) /*!< ADC1_IN14(PC4): default channel is ADC_CH14 of ADC1. */
|
||||
#define ADC1_PIN_PC5 (15U) /*!< ADC1_IN15(PC5): default channel is ADC_CH15 of ADC1. */
|
||||
|
||||
#define ADC2_PIN_PA4 (0U) /*!< ADC12_IN4(PA4): default channel is ADC_CH0 of ADC2 */
|
||||
#define ADC2_PIN_PA5 (1U) /*!< ADC12_IN5(PA5): default channel is ADC_CH1 of ADC2 */
|
||||
#define ADC2_PIN_PA6 (2U) /*!< ADC12_IN6(PA6): default channel is ADC_CH2 of ADC2 */
|
||||
#define ADC2_PIN_PA7 (3U) /*!< ADC12_IN7(PA7): default channel is ADC_CH3 of ADC2 */
|
||||
#define ADC2_PIN_PB0 (4U) /*!< ADC12_IN8(PB0): default channel is ADC_CH4 of ADC2 */
|
||||
#define ADC2_PIN_PB1 (5U) /*!< ADC12_IN9(PB1): default channel is ADC_CH5 of ADC2 */
|
||||
#define ADC2_PIN_PC0 (6U) /*!< ADC12_IN10(PC0): default channel is ADC_CH6 of ADC2 */
|
||||
#define ADC2_PIN_PC1 (7U) /*!< ADC12_IN11(PC1): default channel is ADC_CH7 of ADC2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup ADC_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
/*******************************************************************************
|
||||
Basic features
|
||||
******************************************************************************/
|
||||
int32_t ADC_Init(CM_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcAdcInit);
|
||||
int32_t ADC_DeInit(CM_ADC_TypeDef *ADCx);
|
||||
int32_t ADC_StructInit(stc_adc_init_t *pstcAdcInit);
|
||||
void ADC_ChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint8_t u8Ch, en_functional_state_t enNewState);
|
||||
void ADC_SetSampleTime(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8SampleTime);
|
||||
|
||||
/* Conversion data average calculation function. */
|
||||
void ADC_ConvDataAverageConfig(CM_ADC_TypeDef *ADCx, uint16_t u16AverageCount);
|
||||
void ADC_ConvDataAverageChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, en_functional_state_t enNewState);
|
||||
|
||||
void ADC_TriggerConfig(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint16_t u16TriggerSel);
|
||||
void ADC_TriggerCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enNewState);
|
||||
void ADC_IntCmd(CM_ADC_TypeDef *ADCx, uint8_t u8IntType, en_functional_state_t enNewState);
|
||||
void ADC_Start(CM_ADC_TypeDef *ADCx);
|
||||
void ADC_Stop(CM_ADC_TypeDef *ADCx);
|
||||
uint16_t ADC_GetValue(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch);
|
||||
en_flag_status_t ADC_GetStatus(const CM_ADC_TypeDef *ADCx, uint8_t u8Flag);
|
||||
void ADC_ClearStatus(CM_ADC_TypeDef *ADCx, uint8_t u8Flag);
|
||||
/*******************************************************************************
|
||||
Advanced features
|
||||
******************************************************************************/
|
||||
/* Channel remap. */
|
||||
void ADC_ChRemap(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8AdcPin);
|
||||
uint8_t ADC_GetChPin(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch);
|
||||
void ADC_ResetChMapping(CM_ADC_TypeDef *ADCx);
|
||||
|
||||
/* Sync mode. */
|
||||
void ADC_SyncModeConfig(uint16_t u16SyncUnit, uint16_t u16SyncMode, uint8_t u8TriggerDelay);
|
||||
void ADC_SyncModeCmd(en_functional_state_t enNewState);
|
||||
|
||||
/* Analog watchdog */
|
||||
int32_t ADC_AWD_Config(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch, const stc_adc_awd_config_t *pstcAwd);
|
||||
void ADC_AWD_SetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16WatchdogMode);
|
||||
uint16_t ADC_AWD_GetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit);
|
||||
void ADC_AWD_SetThreshold(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16LowThreshold, uint16_t u16HighThreshold);
|
||||
void ADC_AWD_SelectCh(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch);
|
||||
void ADC_AWD_DeselectCh(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch);
|
||||
void ADC_AWD_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, en_functional_state_t enNewState);
|
||||
void ADC_AWD_IntCmd(CM_ADC_TypeDef *ADCx, uint16_t u16IntType, en_functional_state_t enNewState);
|
||||
en_flag_status_t ADC_AWD_GetStatus(const CM_ADC_TypeDef *ADCx, uint32_t u32Flag);
|
||||
void ADC_AWD_ClearStatus(CM_ADC_TypeDef *ADCx, uint32_t u32Flag);
|
||||
|
||||
/* PGA */
|
||||
void ADC_PGA_Config(CM_ADC_TypeDef *ADCx, uint8_t u8PgaUnit, uint8_t u8Gain, uint8_t u8PgaVss);
|
||||
void ADC_PGA_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8PgaUnit, en_functional_state_t enNewState);
|
||||
void ADC_PGA_SelectInputSrc(CM_ADC_TypeDef *ADCx, uint16_t u16PgaInputSrc);
|
||||
void ADC_PGA_DeselectInputSrc(CM_ADC_TypeDef *ADCx);
|
||||
|
||||
void ADC_DataRegAutoClearCmd(CM_ADC_TypeDef *ADCx, en_functional_state_t enNewState);
|
||||
void ADC_SetSeqAResumeMode(CM_ADC_TypeDef *ADCx, uint16_t u16SeqAResumeMode);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_ADC_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_ADC_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,116 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_aes.h
|
||||
* @brief This file contains all the functions prototypes of the AES driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2023-06-30 CDT Add API AES_DeInit()
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_AES_H__
|
||||
#define __HC32_LL_AES_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_AES
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_AES_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup AES_Global_Macros AES Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup AES_Key_Size AES Key Size
|
||||
* @{
|
||||
*/
|
||||
#define AES_KEY_SIZE_16BYTE (16U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup AES_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
int32_t AES_Encrypt(const uint8_t *pu8Plaintext, uint32_t u32PlaintextSize,
|
||||
const uint8_t *pu8Key, uint8_t u8KeySize,
|
||||
uint8_t *pu8Ciphertext);
|
||||
|
||||
int32_t AES_Decrypt(const uint8_t *pu8Ciphertext, uint32_t u32CiphertextSize,
|
||||
const uint8_t *pu8Key, uint8_t u8KeySize,
|
||||
uint8_t *pu8Plaintext);
|
||||
|
||||
int32_t AES_DeInit(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_AES_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_AES_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,171 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_aos.h
|
||||
* @brief This file contains all the functions prototypes of the AOS driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2023-01-15 CDT Modified parameters name of API AOS_CommonTriggerCmd() and AOS_SetTriggerEventSrc()
|
||||
2023-09-30 CDT Modify for new head file
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_AOS_H__
|
||||
#define __HC32_LL_AOS_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_AOS
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_AOS_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup AOS_Global_Macros AOS Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup AOS_Target_Select AOS Target Select
|
||||
* @{
|
||||
*/
|
||||
#define AOS_DCU1 (uint32_t)(&CM_AOS->DCU_TRGSEL1)
|
||||
#define AOS_DCU2 (uint32_t)(&CM_AOS->DCU_TRGSEL2)
|
||||
#define AOS_DCU3 (uint32_t)(&CM_AOS->DCU_TRGSEL3)
|
||||
#define AOS_DCU4 (uint32_t)(&CM_AOS->DCU_TRGSEL4)
|
||||
#define AOS_DMA1_0 (uint32_t)(&CM_AOS->DMA1_TRGSEL0)
|
||||
#define AOS_DMA1_1 (uint32_t)(&CM_AOS->DMA1_TRGSEL1)
|
||||
#define AOS_DMA1_2 (uint32_t)(&CM_AOS->DMA1_TRGSEL2)
|
||||
#define AOS_DMA1_3 (uint32_t)(&CM_AOS->DMA1_TRGSEL3)
|
||||
#define AOS_DMA2_0 (uint32_t)(&CM_AOS->DMA2_TRGSEL0)
|
||||
#define AOS_DMA2_1 (uint32_t)(&CM_AOS->DMA2_TRGSEL1)
|
||||
#define AOS_DMA2_2 (uint32_t)(&CM_AOS->DMA2_TRGSEL2)
|
||||
#define AOS_DMA2_3 (uint32_t)(&CM_AOS->DMA2_TRGSEL3)
|
||||
#define AOS_DMA_RC (uint32_t)(&CM_AOS->DMA_RC_TRGSEL)
|
||||
#define AOS_TMR6_0 (uint32_t)(&CM_AOS->TMR6_TRGSEL0)
|
||||
#define AOS_TMR6_1 (uint32_t)(&CM_AOS->TMR6_TRGSEL1)
|
||||
#define AOS_TMR0 (uint32_t)(&CM_AOS->TMR0_TRGSEL)
|
||||
#define AOS_EVTPORT12 (uint32_t)(&CM_AOS->PEVNT_TRGSEL12)
|
||||
#define AOS_EVTPORT34 (uint32_t)(&CM_AOS->PEVNT_TRGSEL34)
|
||||
#define AOS_TMRA_0 (uint32_t)(&CM_AOS->TMRA_TRGSEL0)
|
||||
#define AOS_TMRA_1 (uint32_t)(&CM_AOS->TMRA_TRGSEL1)
|
||||
#define AOS_OTS (uint32_t)(&CM_AOS->OTS_TRGSEL)
|
||||
#define AOS_ADC1_0 (uint32_t)(&CM_AOS->ADC1_TRGSEL0)
|
||||
#define AOS_ADC1_1 (uint32_t)(&CM_AOS->ADC1_TRGSEL1)
|
||||
#define AOS_ADC2_0 (uint32_t)(&CM_AOS->ADC2_TRGSEL0)
|
||||
#define AOS_ADC2_1 (uint32_t)(&CM_AOS->ADC2_TRGSEL1)
|
||||
#define AOS_COMM_1 (uint32_t)(&CM_AOS->COMTRG1)
|
||||
#define AOS_COMM_2 (uint32_t)(&CM_AOS->COMTRG2)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup AOS_Common_Trigger_ID AOS Common Trigger ID
|
||||
* @{
|
||||
*/
|
||||
#define AOS_COMM_TRIG1 (1UL << 30U)
|
||||
#define AOS_COMM_TRIG2 (1UL << 31U)
|
||||
#define AOS_COMM_TRIG_MASK (AOS_COMM_TRIG1 | AOS_COMM_TRIG2)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup AOS_Trigger_Select_Mask AOS Trigger Select Mask
|
||||
* @{
|
||||
*/
|
||||
#define AOS_TRIG_SEL_MASK (0x1FFUL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup AOS_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief AOS software trigger.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void AOS_SW_Trigger(void)
|
||||
{
|
||||
WRITE_REG32(bCM_AOS->INTSFTTRG_b.STRG, SET);
|
||||
}
|
||||
|
||||
void AOS_CommonTriggerCmd(uint32_t u32Target, uint32_t u32CommonTrigger, en_functional_state_t enNewState);
|
||||
void AOS_SetTriggerEventSrc(uint32_t u32Target, en_event_src_t enSource);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_AOS_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_AOS_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,669 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_can.h
|
||||
* @brief This file contains all the functions prototypes of the CAN driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2022-10-31 CDT Deleted redundant comments
|
||||
Remove CAN_FLAG_RX_BUF_OVF from CAN_FLAG_CLR_ALL
|
||||
2023-06-30 CDT Added 3 APIs for local-reset
|
||||
Modify typo
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_CAN_H__
|
||||
#define __HC32_LL_CAN_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_CAN
|
||||
* @{
|
||||
*/
|
||||
#if (LL_CAN_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup CAN_Global_Types CAN Global Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief CAN bit time configuration structure.
|
||||
* @note 1. TQ = u32Prescaler / CANClock.
|
||||
* @note 2. Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ.
|
||||
* @note 3. Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2))
|
||||
* @note 4. See user manual of the target MCU and ISO11898-1 for more details.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32Prescaler; /*!< Specifies the prescaler of CAN clock, [1, 256]. */
|
||||
uint32_t u32TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
|
||||
u32TimeSeg1 Contains synchronization segment,
|
||||
propagation time segment and phase buffer segment 1. */
|
||||
uint32_t u32TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
|
||||
Phase buffer segment 2. */
|
||||
uint32_t u32SJW; /*!< Synchronization Jump Width.
|
||||
Specifies the maximum number of time quanta the CAN hardware
|
||||
is allowed to lengthen or shorten a bit to perform resynchronization. */
|
||||
} stc_can_bit_time_config_t;
|
||||
|
||||
/**
|
||||
* @brief CAN acceptance filter configuration structure.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32ID; /*!< Specifies the identifier(ID). 11 bits standard ID or 29 bits extended ID, depending on IDE. */
|
||||
uint32_t u32IDMask; /*!< Specifies the identifier(ID) mask. The mask bits of ID will be ignored by the acceptance filter. */
|
||||
uint32_t u32IDType; /*!< Specifies the identifier(ID) type. This parameter can be a value of @ref CAN_ID_Type */
|
||||
} stc_can_filter_config_t;
|
||||
|
||||
/**
|
||||
* @brief TTCAN configuration structure.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32RefMsgID; /*!< Reference message identifier. */
|
||||
uint32_t u32RefMsgIDE; /*!< Reference message identifier extension bit.
|
||||
'1' to set the ID which is specified by parameter 'u32RefMsgID' as an extended ID while
|
||||
'0' to set it as a standard ID. */
|
||||
uint8_t u8NTUPrescaler; /*!< Prescaler of NTU(network time unit). The source is the bit time which is defined by SBT.
|
||||
This parameter can be a value of @ref TTCAN_NTU_Prescaler */
|
||||
uint8_t u8TxBufMode; /*!< TTCAN Transmit Buffer Mode.
|
||||
This parameter can be a value of @ref TTCAN_Tx_Buf_Mode */
|
||||
uint16_t u16TriggerType; /*!< Trigger type of TTCAN.
|
||||
This parameter can be a value of @ref TTCAN_Trigger_Type */
|
||||
uint16_t u16TxEnableWindow; /*!< Tx_Enable window. Time period within which the transmission of a message may be started. Range is [1, 16] */
|
||||
uint16_t u16TxTriggerTime; /*!< Specifies for the referred message the time window of the matrix cycle at which it is to be transmitted. Range is [0, 65535] */
|
||||
uint16_t u16WatchTriggerTime; /*!< Time mark used to check whether the time since the last valid reference message has been too long. Range is [0, 65535] */
|
||||
} stc_can_ttc_config_t;
|
||||
|
||||
/**
|
||||
* @brief CAN initialization structure.
|
||||
*/
|
||||
typedef struct {
|
||||
stc_can_bit_time_config_t stcBitCfg; /*!< Bit time configuration of classical CAN bit. @ref stc_can_bit_time_config_t */
|
||||
stc_can_filter_config_t *pstcFilter; /*!< Pointer to a @ref stc_can_filter_config_t structure that
|
||||
contains the configuration informations for the acceptance filters. */
|
||||
uint16_t u16FilterSelect; /*!< Selects acceptance filters.
|
||||
This parameter can be values of @ref CAN_Acceptance_Filter */
|
||||
uint8_t u8WorkMode; /*!< Specifies the work mode of CAN.
|
||||
This parameter can be a value of @ref CAN_Work_Mode */
|
||||
uint8_t u8PTBSingleShotTx; /*!< Enable or disable single shot transmission of PTB.
|
||||
This parameter can be a value of @ref PTB_SingleShot_Tx_En */
|
||||
uint8_t u8STBSingleShotTx; /*!< Enable or disable single shot transmission of STB.
|
||||
This parameter can be a value of @ref STB_SingleShot_Tx_En */
|
||||
uint8_t u8STBPrioMode; /*!< Enable or disable the priority decision mode of STB.
|
||||
This parameter can be a value of @ref CAN_STB_Prio_Mode_En
|
||||
NOTE: A frame in the PTB has always the highest priority regardless of the ID. */
|
||||
uint8_t u8RxWarnLimit; /*!< Specifies receive buffer almost full warning limit. Rang is [1, 8].
|
||||
Each CAN unit has 8 receive buffers. When the number of received frames reaches
|
||||
the value specified by u8RxWarnLimit, register bit RTIF.RAFIF is set and the interrupt occurred
|
||||
if it was enabled. */
|
||||
uint8_t u8ErrorWarnLimit; /*!< Specifies programmable error warning limit. Range is [0, 15].
|
||||
Error warning limit = (u8ErrorWarnLimit + 1) * 8. */
|
||||
uint8_t u8RxAllFrame; /*!< Enable or disable receive all frames(includes frames with error).
|
||||
This parameter can be a value of @ref CAN_Rx_All_En */
|
||||
uint8_t u8RxOvfMode; /*!< Receive buffer overflow mode. In case of a full receive buffer when a new frame is received.
|
||||
This parameter can be a value of @ref CAN_Rx_Ovf_Mode */
|
||||
uint8_t u8SelfAck; /*!< Enable or disable self-acknowledge.
|
||||
This parameter can be a value of @ref CAN_Self_ACK_En */
|
||||
|
||||
stc_can_ttc_config_t *pstcCanTtc; /*!< Pointer to a TTCAN configuration structure. @ref stc_can_ttc_config_t
|
||||
Set it to NULL if not needed TTCAN. */
|
||||
} stc_can_init_t;
|
||||
|
||||
/**
|
||||
* @brief CAN error information structure.
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t u8ArbitrLostPos; /*!< Bit position in the frame where the arbitration has been lost. */
|
||||
uint8_t u8ErrorType; /*!< CAN error type. This parameter can be a value of @ref CAN_Err_Type */
|
||||
uint8_t u8RxErrorCount; /*!< Receive error count. */
|
||||
uint8_t u8TxErrorCount; /*!< Transmit error count. */
|
||||
} stc_can_error_info_t;
|
||||
|
||||
/**
|
||||
* @brief CAN TX frame data structure.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32ID; /*!< 11 bits standard ID or 29 bits extended ID, depending on IDE. */
|
||||
union {
|
||||
uint32_t u32Ctrl;
|
||||
struct {
|
||||
uint32_t DLC: 4; /*!< Data length code. Length of the data segment of data frame.
|
||||
It should be zero while the frame is remote frame.
|
||||
This parameter can be a value of @ref CAN_Data_Length_Code */
|
||||
uint32_t BRS: 1; /*!< Bit rate switch. */
|
||||
uint32_t FDF: 1; /*!< CAN FD frame. */
|
||||
uint32_t RTR: 1; /*!< Remote transmission request bit.
|
||||
It is used to distinguish between data frames and remote frames. */
|
||||
uint32_t IDE: 1; /*!< Identifier extension flag.
|
||||
It is used to distinguish between standard format and extended format.
|
||||
This parameter can be a 1 or 0. */
|
||||
uint32_t RSVD: 24; /*!< Reserved bits. */
|
||||
};
|
||||
};
|
||||
uint8_t au8Data[8U]; /*!< TX data payload. */
|
||||
} stc_can_tx_frame_t;
|
||||
|
||||
/**
|
||||
* @brief CAN RX frame data structure.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32ID; /*!< 11 bits standard ID or 29 bits extended ID, depending on IDE. */
|
||||
union {
|
||||
uint32_t u32Ctrl;
|
||||
struct {
|
||||
uint32_t DLC: 4; /*!< Data length code. Length of the data segment of data frame.
|
||||
It should be zero while the frame is remote frame.
|
||||
This parameter can be a value of @ref CAN_Data_Length_Code */
|
||||
uint32_t BRS: 1; /*!< Bit rate switch. */
|
||||
uint32_t FDF: 1; /*!< CAN FD frame. */
|
||||
uint32_t RTR: 1; /*!< Remote transmission request bit.
|
||||
It is used to distinguish between data frames and remote frames. */
|
||||
uint32_t IDE: 1; /*!< Identifier extension flag.
|
||||
It is used to distinguish between standard format and extended format.
|
||||
This parameter can be 1 or 0. */
|
||||
uint32_t RSVD: 4; /*!< Reserved bits. */
|
||||
uint32_t TX: 1; /*!< This bit is set to 1 when receiving self-transmitted data in loopback mode. */
|
||||
uint32_t ERRT: 3; /*!< Error type. */
|
||||
uint32_t CYCLE_TIME: 16; /*!< Cycle time of time-triggered communication(TTC). */
|
||||
};
|
||||
};
|
||||
uint8_t au8Data[8U]; /*!< RX data payload. */
|
||||
} stc_can_rx_frame_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup CAN_Global_Macros CAN Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Work_Mode CAN Work Mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_WORK_MD_NORMAL (0U) /*!< Normal work mode. */
|
||||
#define CAN_WORK_MD_SILENT (1U) /*!< Silent work mode. Prohibit data transmission. */
|
||||
#define CAN_WORK_MD_ILB (2U) /*!< Internal loop back mode, just for self-test while developing. */
|
||||
#define CAN_WORK_MD_ELB (3U) /*!< External loop back mode, just for self-test while developing. */
|
||||
#define CAN_WORK_MD_ELB_SILENT (4U) /*!< External loop back silent mode, just for self-test while developing.
|
||||
It is forbidden to respond to received frames and error frames,
|
||||
but data can be transmitted. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Tx_Buf_Type CAN Transmit Buffer Type
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TX_BUF_PTB (0U) /*!< Primary transmit buffer. */
|
||||
#define CAN_TX_BUF_STB (1U) /*!< Secondary transmit buffer. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Data_Length_Code CAN Data Length Code
|
||||
* @{
|
||||
*/
|
||||
#define CAN_DLC0 (0x0U) /*!< CAN2.0 and CAN FD: the size of data field is 0 bytes. */
|
||||
#define CAN_DLC1 (0x1U) /*!< CAN2.0 and CAN FD: the size of data field is 1 bytes. */
|
||||
#define CAN_DLC2 (0x2U) /*!< CAN2.0 and CAN FD: the size of data field is 2 bytes. */
|
||||
#define CAN_DLC3 (0x3U) /*!< CAN2.0 and CAN FD: the size of data field is 3 bytes. */
|
||||
#define CAN_DLC4 (0x4U) /*!< CAN2.0 and CAN FD: the size of data field is 4 bytes. */
|
||||
#define CAN_DLC5 (0x5U) /*!< CAN2.0 and CAN FD: the size of data field is 5 bytes. */
|
||||
#define CAN_DLC6 (0x6U) /*!< CAN2.0 and CAN FD: the size of data field is 6 bytes. */
|
||||
#define CAN_DLC7 (0x7U) /*!< CAN2.0 and CAN FD: the size of data field is 7 bytes. */
|
||||
#define CAN_DLC8 (0x8U) /*!< CAN2.0 and CAN FD: the size of data field is 8 bytes. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PTB_SingleShot_Tx_En PTB Single Shot Transmission Function Control
|
||||
* @{
|
||||
*/
|
||||
#define CAN_PTB_SINGLESHOT_TX_DISABLE (0x0U) /*!< Primary transmit buffer auto retransmit. */
|
||||
#define CAN_PTB_SINGLESHOT_TX_ENABLE (CAN_CFG_STAT_TPSS) /*!< Primary transmit buffer single short transmit. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STB_SingleShot_Tx_En STB Single Shot Transmission Function Control
|
||||
* @{
|
||||
*/
|
||||
#define CAN_STB_SINGLESHOT_TX_DISABLE (0x0U) /*!< Secondary transmit buffer auto retransmit. */
|
||||
#define CAN_STB_SINGLESHOT_TX_ENABLE (CAN_CFG_STAT_TSSS) /*!< Secondary transmit buffer single short transmit. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Tx_Request CAN Transmission Request
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TX_REQ_STB_ONE (CAN_TCMD_TSONE) /*!< Transmit one STB frame. */
|
||||
#define CAN_TX_REQ_STB_ALL (CAN_TCMD_TSALL) /*!< Transmit all STB frames. */
|
||||
#define CAN_TX_REQ_PTB (CAN_TCMD_TPE) /*!< Transmit PTB frame. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_STB_Prio_Mode_En CAN STB Priority Mode Function Control
|
||||
* @note A frame in the PTB has always the highest priority regardless of the ID.
|
||||
* @{
|
||||
*/
|
||||
#define CAN_STB_PRIO_MD_DISABLE (0x0U) /*!< The frame first in will first be transmitted. */
|
||||
#define CAN_STB_PRIO_MD_ENABLE (CAN_TCTRL_TSMODE) /*!< The frame with lower ID will first be transmitted. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Tx_Buf_Status CAN Transmit Buffer Status
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TX_BUF_EMPTY (0x0U) /*!< TTCAN is disabled(TTEN == 0): STB is empty.
|
||||
TTCAN is disabled(TTEN == 1) and transmit buffer is specified by TBPTR and TTPTR(TTTBM == 1):
|
||||
PTB and STB are both empty. */
|
||||
#define CAN_TX_BUF_NOT_MORE_THAN_HALF (0x1U) /*!< TTEN == 0: STB is less than or equal to half full;
|
||||
TTEN == 1 && TTTBM == 1: PTB and STB are neither empty. */
|
||||
#define CAN_TX_BUF_MORE_THAN_HALF (0x2U) /*!< TTEN == 0: STB is more than half full;
|
||||
TTEN == 1 && TTTBM == 1: reserved value. */
|
||||
#define CAN_TX_BUF_FULL (0x3U) /*!< TTEN == 0: STB is full;
|
||||
TTEN == 1 && TTTBM == 1: PTB and STB are both full. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Rx_Buf_Status CAN Receive Buffer Status
|
||||
* @{
|
||||
*/
|
||||
#define CAN_RX_BUF_EMPTY (0x0U) /*!< Receive buffer is empty. */
|
||||
#define CAN_RX_BUF_NOT_WARN (0x1U) /*!< Receive buffer is not empty, but is less than almost full warning limit. */
|
||||
#define CAN_RX_BUF_WARN (0x2U) /*!< Receive buffer is not full and not overflow, but is more than or equal to almost full warning limit. */
|
||||
#define CAN_RX_BUF_FULL (0x3U) /*!< Receive buffer is full. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Rx_All_En CAN Receive All Frames
|
||||
* @{
|
||||
*/
|
||||
#define CAN_RX_ALL_FRAME_DISABLE (0x0U) /*!< Only receives correct frames. */
|
||||
#define CAN_RX_ALL_FRAME_ENABLE (CAN_RCTRL_RBALL) /*!< Receives all frames, including frames with error. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Rx_Ovf_Mode CAN Receive Buffer Overflow Mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_RX_OVF_SAVE_NEW (0x0U) /*!< Saves the newly received data and the oldest frame will be overwritten. */
|
||||
#define CAN_RX_OVF_DISCARD_NEW (CAN_RCTRL_ROM) /*!< Discard the newly received data. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Self_ACK_En CAN Self-ACK Function Control
|
||||
* @{
|
||||
*/
|
||||
#define CAN_SELF_ACK_DISABLE (0x0U) /*!< Disable self-acknowledge. */
|
||||
#define CAN_SELF_ACK_ENABLE (CAN_RCTRL_SACK) /*!< Enable self-acknowledge. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Interrupt_Type CAN Interrupt Type
|
||||
* @{
|
||||
*/
|
||||
#define CAN_INT_ERR_INT (1UL << 1U) /*!< Register bit RTIE.EIE. The interrupt RTIF.EIF will be set if enabled by RTIE.EIE under the following conditions:
|
||||
The border of the error warning limit has been crossed in either direction by RECNT or TECNT or
|
||||
the BUSOFF bit has been changed in either direction. */
|
||||
#define CAN_INT_STB_TX (1UL << 2U) /*!< Register bit RTIE.TSIE. STB was transmitted. */
|
||||
#define CAN_INT_PTB_TX (1UL << 3U) /*!< Register bit RTIE.TPIE. PTB was transmitted. */
|
||||
#define CAN_INT_RX_BUF_WARN (1UL << 4U) /*!< Register bit RTIE.RAFIE. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. */
|
||||
#define CAN_INT_RX_BUF_FULL (1UL << 5U) /*!< Register bit RTIE.RFIE. The FIFO of receive buffer is full. */
|
||||
#define CAN_INT_RX_OVERRUN (1UL << 6U) /*!< Register bit RTIE.ROIE. Receive buffers are full and there is a further message to be stored. */
|
||||
#define CAN_INT_RX (1UL << 7U) /*!< Register bit RTIE.RIE. Received a valid data frame or remote frame. */
|
||||
#define CAN_INT_BUS_ERR (1UL << 9U) /*!< Register bit ERRINT.BEIE. Each of the error defined by EALCAP.KOER can cause bus-error interrupt. */
|
||||
#define CAN_INT_ARBITR_LOST (1UL << 11U) /*!< Register bit ERRINT.ALIE. Arbitration lost. */
|
||||
#define CAN_INT_ERR_PASSIVE (1UL << 13U) /*!< Register bit ERRINT.EPIE. A change from error-passive to error-active or error-active to error-passive has occurred. */
|
||||
|
||||
#define CAN_INT_ALL (CAN_INT_ERR_INT | \
|
||||
CAN_INT_STB_TX | \
|
||||
CAN_INT_PTB_TX | \
|
||||
CAN_INT_RX_BUF_WARN | \
|
||||
CAN_INT_RX_BUF_FULL | \
|
||||
CAN_INT_RX_OVERRUN | \
|
||||
CAN_INT_RX | \
|
||||
CAN_INT_BUS_ERR | \
|
||||
CAN_INT_ARBITR_LOST | \
|
||||
CAN_INT_ERR_PASSIVE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Status_Flag CAN Status Flag
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FLAG_BUS_OFF (1UL << 0U) /*!< Register bit CFG_STAT.BUSOFF. CAN bus off. */
|
||||
#define CAN_FLAG_TX_GOING (1UL << 1U) /*!< Register bit CFG_STAT.TACTIVE. CAN bus is transmitting. */
|
||||
#define CAN_FLAG_RX_GOING (1UL << 2U) /*!< Register bit CFG_STAT.RACTIVE. CAN bus is receiving. */
|
||||
#define CAN_FLAG_RX_BUF_OVF (1UL << 5U) /*!< Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one frame will be lost. */
|
||||
#define CAN_FLAG_TX_BUF_FULL (1UL << 8U) /*!< Register bit RTIE.TSFF. Transmit buffers are all full.
|
||||
TTCFG.TTEN == 0 or TCTRL.TTTEM == 0: ALL STB slots are filled.
|
||||
TTCFG.TTEN == 1 and TCTRL.TTTEM == 1: Transmit buffer that pointed by TBSLOT.TBPTR is filled.*/
|
||||
#define CAN_FLAG_TX_ABORTED (1UL << 16U) /*!< Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled. */
|
||||
#define CAN_FLAG_ERR_INT (1UL << 17U) /*!< Register bit RTIF.EIF. The interrupt RTIF.EIF will be set if enabled by RTIE.EIE under the following conditions:
|
||||
The border of the error warning limit has been crossed in either direction by RECNT or TECNT or
|
||||
the BUSOFF bit has been changed in either direction. */
|
||||
#define CAN_FLAG_STB_TX (1UL << 18U) /*!< Register bit RTIF.TSIF. STB was transmitted. */
|
||||
#define CAN_FLAG_PTB_TX (1UL << 19U) /*!< Register bit RTIF.TPIF. PTB was transmitted. */
|
||||
#define CAN_FLAG_RX_BUF_WARN (1UL << 20U) /*!< Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. */
|
||||
#define CAN_FLAG_RX_BUF_FULL (1UL << 21U) /*!< Register bit RTIF.RFIF. The FIFO of receive buffer is full. */
|
||||
#define CAN_FLAG_RX_OVERRUN (1UL << 22U) /*!< Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored. */
|
||||
#define CAN_FLAG_RX (1UL << 23U) /*!< Register bit RTIF.RIF. Received a valid data frame or remote frame. */
|
||||
#define CAN_FLAG_BUS_ERR (1UL << 24U) /*!< Register bit ERRINT.BEIF. Each of the error defined by EALCAP.KOER can make this flag set. */
|
||||
#define CAN_FLAG_ARBITR_LOST (1UL << 26U) /*!< Register bit ERRINT.ALIF. Arbitration lost. */
|
||||
#define CAN_FLAG_ERR_PASSIVE (1UL << 28U) /*!< Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred. */
|
||||
#define CAN_FLAG_ERR_PASSIVE_NODE (1UL << 30U) /*!< Register bit ERRINT.EPASS. The node is an error-passive node. */
|
||||
#define CAN_FLAG_TEC_REC_WARN (1UL << 31U) /*!< Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value. */
|
||||
|
||||
#define CAN_FLAG_ALL (CAN_FLAG_BUS_OFF | \
|
||||
CAN_FLAG_TX_GOING | \
|
||||
CAN_FLAG_RX_GOING | \
|
||||
CAN_FLAG_RX_BUF_OVF | \
|
||||
CAN_FLAG_TX_BUF_FULL | \
|
||||
CAN_FLAG_TX_ABORTED | \
|
||||
CAN_FLAG_ERR_INT | \
|
||||
CAN_FLAG_STB_TX | \
|
||||
CAN_FLAG_PTB_TX | \
|
||||
CAN_FLAG_RX_BUF_WARN | \
|
||||
CAN_FLAG_RX_BUF_FULL | \
|
||||
CAN_FLAG_RX_OVERRUN | \
|
||||
CAN_FLAG_RX | \
|
||||
CAN_FLAG_BUS_ERR | \
|
||||
CAN_FLAG_ARBITR_LOST | \
|
||||
CAN_FLAG_ERR_PASSIVE | \
|
||||
CAN_FLAG_ERR_PASSIVE_NODE | \
|
||||
CAN_FLAG_TEC_REC_WARN)
|
||||
|
||||
#define CAN_FLAG_CLR_ALL (CAN_FLAG_TX_ABORTED | \
|
||||
CAN_FLAG_ERR_INT | \
|
||||
CAN_FLAG_STB_TX | \
|
||||
CAN_FLAG_PTB_TX | \
|
||||
CAN_FLAG_RX_BUF_WARN | \
|
||||
CAN_FLAG_RX_BUF_FULL | \
|
||||
CAN_FLAG_RX_OVERRUN | \
|
||||
CAN_FLAG_RX | \
|
||||
CAN_FLAG_BUS_ERR | \
|
||||
CAN_FLAG_ARBITR_LOST | \
|
||||
CAN_FLAG_ERR_PASSIVE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_ID_Type CAN Identifier Type
|
||||
* @{
|
||||
*/
|
||||
#define CAN_ID_STD_EXT (0x0U) /*!< Acceptance filter accept frames with both standard ID and extended ID. */
|
||||
#define CAN_ID_STD (CAN_ACF_AIDEE) /*!< Acceptance filter accept frames with only standard ID. */
|
||||
#define CAN_ID_EXT (CAN_ACF_AIDEE | \
|
||||
CAN_ACF_AIDE) /*!< Acceptance filter accept frames with only extended ID. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Err_Type CAN Error Type
|
||||
* @{
|
||||
*/
|
||||
#define CAN_ERR_NONE (0U) /*!< No error. */
|
||||
#define CAN_ERR_BIT (0x1U) /*!< Error is bit error. */
|
||||
#define CAN_ERR_FORM (0x2U) /*!< Error is form error. */
|
||||
#define CAN_ERR_STUFF (0x3U) /*!< Error is stuff error. */
|
||||
#define CAN_ERR_ACK (0x4U) /*!< Error is ACK error. */
|
||||
#define CAN_ERR_CRC (0x5U) /*!< Error is CRC error. */
|
||||
#define CAN_ERR_OTHER (0x6U) /*!< Error is other error.
|
||||
Dominant bits after own error flag, received active Error Flag too long,
|
||||
dominant bit during Passive-Error-Flag after ACK error. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Acceptance_Filter CAN Acceptance Filter
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTER1 (CAN_ACFEN_AE_1) /*!< Acceptance filter 1 select bit. */
|
||||
#define CAN_FILTER2 (CAN_ACFEN_AE_2) /*!< Acceptance filter 2 select bit. */
|
||||
#define CAN_FILTER3 (CAN_ACFEN_AE_3) /*!< Acceptance filter 3 select bit. */
|
||||
#define CAN_FILTER4 (CAN_ACFEN_AE_4) /*!< Acceptance filter 4 select bit. */
|
||||
#define CAN_FILTER5 (CAN_ACFEN_AE_5) /*!< Acceptance filter 5 select bit. */
|
||||
#define CAN_FILTER6 (CAN_ACFEN_AE_6) /*!< Acceptance filter 6 select bit. */
|
||||
#define CAN_FILTER7 (CAN_ACFEN_AE_7) /*!< Acceptance filter 7 select bit. */
|
||||
#define CAN_FILTER8 (CAN_ACFEN_AE_8) /*!< Acceptance filter 8 select bit. */
|
||||
#define CAN_FILTER_ALL (0xFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TTCAN_Tx_Buf_Mode TTCAN Transmit Buffer Mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TTC_TX_BUF_MD_CAN (0x0U) /*!< Normal CAN mode. TTCAN transmit buffer depends on the priority mode of STB which is defined by @ref CAN_STB_Prio_Mode_En */
|
||||
#define CAN_TTC_TX_BUF_MD_TTCAN (CAN_TCTRL_TTTBM) /*!< Full TTCAN mode. TTCAN transmit buffer is pointed by TBSLOT.TBPTR(for data filling) and
|
||||
TRG_CFG.TTPTR(for data transmission). */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TTCAN_Tx_Buf_Sel TTCAN Transmit Buffer Selection
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TTC_TX_BUF_PTB (0x0U) /*!< Point to PTB. */
|
||||
#define CAN_TTC_TX_BUF_STB1 (0x1U) /*!< Point to STB slot 1. */
|
||||
#define CAN_TTC_TX_BUF_STB2 (0x2U) /*!< Point to STB slot 2. */
|
||||
#define CAN_TTC_TX_BUF_STB3 (0x3U) /*!< Point to STB slot 3. */
|
||||
#define CAN_TTC_TX_BUF_STB4 (0x4U) /*!< Point to STB slot 4. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TTCAN_Tx_Buf_Mark_State TTCAN Transmit Buffer Mark State
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TTC_TX_BUF_MARK_EMPTY (CAN_TBSLOT_TBE) /*!< Marks the transmit buffer selected by TBSLOT.TBPTR as "empty".
|
||||
TBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0.
|
||||
If a transmission from this slot is active, then TBE stays set as long as either the
|
||||
transmission completes or after a transmission error or arbitration loss the transmission
|
||||
is not active any more. If both TBF and TBE are set, then TBE wins. */
|
||||
#define CAN_TTC_TX_BUF_MARK_FILLED (CAN_TBSLOT_TBF) /*!< Marks the transmit buffer selected by TBSLOT.TBPTR as "filled".
|
||||
TBF is automatically reset to 0 as soon as the slot is marked as filled and RTIE.TSFF=1.
|
||||
If both TBF and TBE are set, then TBE wins. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TTCAN_Interrupt_Type TTCAN Interrupt Type
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TTC_INT_TIME_TRIG (CAN_TTCFG_TTIE) /*!< Time trigger interrupt. */
|
||||
#define CAN_TTC_INT_WATCH_TRIG (CAN_TTCFG_WTIE) /*!< Watch trigger interrupt. */
|
||||
#define CAN_TTC_INT_ALL (CAN_TTC_INT_TIME_TRIG | \
|
||||
CAN_TTC_INT_WATCH_TRIG)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TTCAN_Status_Flag TTCAN Status Flag
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TTC_FLAG_TIME_TRIG (CAN_TTCFG_TTIF) /*!< Time trigger interrupt flag. */
|
||||
#define CAN_TTC_FLAG_TRIG_ERR (CAN_TTCFG_TEIF) /*!< Trigger error interrupt flag. */
|
||||
#define CAN_TTC_FLAG_WATCH_TRIG (CAN_TTCFG_WTIF) /*!< Watch trigger interrupt flag. */
|
||||
|
||||
#define CAN_TTC_FLAG_ALL (CAN_TTC_FLAG_TIME_TRIG | \
|
||||
CAN_TTC_FLAG_TRIG_ERR | \
|
||||
CAN_TTC_FLAG_WATCH_TRIG)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TTCAN_NTU_Prescaler TTCAN Network Time Unit Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TTC_NTU_PRESCALER1 (0x0U) /*!< NTU is SBT bit time * 1. */
|
||||
#define CAN_TTC_NTU_PRESCALER2 (CAN_TTCFG_T_PRESC_0) /*!< NTU is SBT bit time * 2. */
|
||||
#define CAN_TTC_NTU_PRESCALER4 (CAN_TTCFG_T_PRESC_1) /*!< NTU is SBT bit time * 4. */
|
||||
#define CAN_TTC_NTU_PRESCALER8 (CAN_TTCFG_T_PRESC) /*!< NTU is SBT bit time * 8. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TTCAN_Trigger_Type TTCAN Trigger Type
|
||||
* @note Except for the immediate trigger, all triggers set TTIF if TTIE is enabled.
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TTC_TRIG_IMMED_TRIG (0x0U) /*!< Immediate trigger for immediate transmission. */
|
||||
#define CAN_TTC_TRIG_TIME_TRIG (CAN_TRG_CFG_TTYPE_0) /*!< Time trigger for receive triggers. */
|
||||
#define CAN_TTC_TRIG_SINGLESHOT_TX_TRIG (CAN_TRG_CFG_TTYPE_1) /*!< Single shot transmit trigger for exclusive time windows. */
|
||||
#define CAN_TTC_TRIG_TX_START_TRIG (CAN_TRG_CFG_TTYPE_1 | \
|
||||
CAN_TRG_CFG_TTYPE_0) /*!< Transmit start trigger for merged arbitrating time windows. */
|
||||
#define CAN_TTC_TRIG_TX_STOP_TRIG (CAN_TRG_CFG_TTYPE_2) /*!< Transmit stop trigger for merged arbitrating time windows. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup CAN_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
/* Classical CAN */
|
||||
int32_t CAN_Init(CM_CAN_TypeDef *CANx, const stc_can_init_t *pstcCanInit);
|
||||
int32_t CAN_StructInit(stc_can_init_t *pstcCanInit);
|
||||
void CAN_DeInit(CM_CAN_TypeDef *CANx);
|
||||
void CAN_IntCmd(CM_CAN_TypeDef *CANx, uint32_t u32IntType, en_functional_state_t enNewState);
|
||||
int32_t CAN_FillTxFrame(CM_CAN_TypeDef *CANx, uint8_t u8TxBufType, const stc_can_tx_frame_t *pstcTx);
|
||||
void CAN_StartTx(CM_CAN_TypeDef *CANx, uint8_t u8TxRequest);
|
||||
void CAN_AbortTx(CM_CAN_TypeDef *CANx, uint8_t u8TxBufType);
|
||||
int32_t CAN_GetRxFrame(CM_CAN_TypeDef *CANx, stc_can_rx_frame_t *pstcRx);
|
||||
|
||||
void CAN_EnterLocalReset(CM_CAN_TypeDef *CANx);
|
||||
void CAN_ExitLocalReset(CM_CAN_TypeDef *CANx);
|
||||
en_flag_status_t CAN_GetLocalResetStatus(CM_CAN_TypeDef *CANx);
|
||||
|
||||
en_flag_status_t CAN_GetStatus(const CM_CAN_TypeDef *CANx, uint32_t u32Flag);
|
||||
void CAN_ClearStatus(CM_CAN_TypeDef *CANx, uint32_t u32Flag);
|
||||
uint32_t CAN_GetStatusValue(const CM_CAN_TypeDef *CANx);
|
||||
int32_t CAN_GetErrorInfo(const CM_CAN_TypeDef *CANx, stc_can_error_info_t *pstcErr);
|
||||
uint8_t CAN_GetTxBufStatus(const CM_CAN_TypeDef *CANx);
|
||||
uint8_t CAN_GetRxBufStatus(const CM_CAN_TypeDef *CANx);
|
||||
void CAN_FilterCmd(CM_CAN_TypeDef *CANx, uint16_t u16FilterSelect, en_functional_state_t enNewState);
|
||||
void CAN_SetRxWarnLimit(CM_CAN_TypeDef *CANx, uint8_t u8RxWarnLimit);
|
||||
void CAN_SetErrorWarnLimit(CM_CAN_TypeDef *CANx, uint8_t u8ErrorWarnLimit);
|
||||
|
||||
/* TTCAN */
|
||||
int32_t CAN_TTC_StructInit(stc_can_ttc_config_t *pstcCanTtc);
|
||||
int32_t CAN_TTC_Config(CM_CAN_TypeDef *CANx, const stc_can_ttc_config_t *pstcCanTtc);
|
||||
void CAN_TTC_IntCmd(CM_CAN_TypeDef *CANx, uint8_t u8IntType, en_functional_state_t enNewState);
|
||||
void CAN_TTC_Cmd(CM_CAN_TypeDef *CANx, en_functional_state_t enNewState);
|
||||
|
||||
en_flag_status_t CAN_TTC_GetStatus(const CM_CAN_TypeDef *CANx, uint8_t u8Flag);
|
||||
void CAN_TTC_ClearStatus(CM_CAN_TypeDef *CANx, uint8_t u8Flag);
|
||||
uint8_t CAN_TTC_GetStatusValue(const CM_CAN_TypeDef *CANx);
|
||||
|
||||
void CAN_TTC_SetTriggerType(CM_CAN_TypeDef *CANx, uint16_t u16TriggerType);
|
||||
void CAN_TTC_SetTxEnableWindow(CM_CAN_TypeDef *CANx, uint16_t u16TxEnableWindow);
|
||||
void CAN_TTC_SetTxTriggerTime(CM_CAN_TypeDef *CANx, uint16_t u16TxTriggerTime);
|
||||
void CAN_TTC_SetWatchTriggerTime(CM_CAN_TypeDef *CANx, uint16_t u16WatchTriggerTime);
|
||||
|
||||
int32_t CAN_TTC_FillTxFrame(CM_CAN_TypeDef *CANx, uint8_t u8CANTTCTxBuf, const stc_can_tx_frame_t *pstcTx);
|
||||
|
||||
int32_t CAN_TTC_GetConfig(const CM_CAN_TypeDef *CANx, stc_can_ttc_config_t *pstcCanTtc);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_CAN_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_CAN_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,714 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_clk.h
|
||||
* @brief This file contains all the functions prototypes of the CLK driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2022-06-30 CDT Refine stc_clock_freq_t
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_CLK_H__
|
||||
#define __HC32_LL_CLK_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_CLK
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_CLK_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup CLK_Global_Types CLK Global Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief CLK XTAL configuration structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t u8State; /*!< The new state of the XTAL.
|
||||
This parameter can be a value of @ref CLK_XTAL_Config */
|
||||
uint8_t u8Drv; /*!< The XTAL drive ability.
|
||||
This parameter can be a value of @ref CLK_XTAL_Config */
|
||||
uint8_t u8Mode; /*!< The XTAL mode selection osc or exclk.
|
||||
This parameter can be a value of @ref CLK_XTAL_Config */
|
||||
uint8_t u8SuperDrv; /*!< The XTAL super drive on or off.
|
||||
This parameter can be a value of @ref CLK_XTAL_Config */
|
||||
uint8_t u8StableTime; /*!< The XTAL stable time selection.
|
||||
This parameter can be a value of @ref CLK_XTAL_Config */
|
||||
} stc_clock_xtal_init_t;
|
||||
|
||||
/**
|
||||
* @brief CLK XTAL fault detect configuration structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t u8State; /*!< Specifies the new state of XTALSTD.
|
||||
This parameter can be a value of @ref CLK_XTALSTD_Config */
|
||||
uint8_t u8Mode; /*!< Specifies the XTALSTD mode.
|
||||
This parameter can be a value of @ref CLK_XTALSTD_Config */
|
||||
uint8_t u8Int; /*!< Specifies the XTALSTD interrupt on or off.
|
||||
This parameter can be a value of @ref CLK_XTALSTD_Config */
|
||||
uint8_t u8Reset; /*!< Specifies the XTALSTD reset on or off.
|
||||
This parameter can be a value of @ref CLK_XTALSTD_Config */
|
||||
} stc_clock_xtalstd_init_t;
|
||||
|
||||
/**
|
||||
* @brief CLK XTAL32 configuration structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t u8State; /*!< Xtal32 new state,
|
||||
@ref CLK_XTAL32_Config for details */
|
||||
uint8_t u8Drv; /*!< Xtal32 drive capacity setting,
|
||||
@ref CLK_XTAL32_Config for details */
|
||||
uint8_t u8Filter; /*!< Xtal32 noise filter setting,
|
||||
@ref CLK_XTAL32_Config for details */
|
||||
} stc_clock_xtal32_init_t;
|
||||
|
||||
/**
|
||||
* @brief CLK clock frequency configuration structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
union {
|
||||
uint32_t SCFGR; /*!< clock frequency config register */
|
||||
struct {
|
||||
uint32_t PCLK0S : 3; /*!< PCLK0 */
|
||||
uint32_t resvd0 : 1; /*!< reserved */
|
||||
uint32_t PCLK1S : 3; /*!< PCLK1 */
|
||||
uint32_t resvd1 : 1; /*!< reserved */
|
||||
uint32_t PCLK2S : 3; /*!< PCLK2 */
|
||||
uint32_t resvd2 : 1; /*!< reserved */
|
||||
uint32_t PCLK3S : 3; /*!< PCLK3 */
|
||||
uint32_t resvd3 : 1; /*!< reserved */
|
||||
uint32_t PCLK4S : 3; /*!< PCLK4 */
|
||||
uint32_t resvd4 : 1; /*!< reserved */
|
||||
uint32_t EXCKS : 3; /*!< EXCLK */
|
||||
uint32_t resvd5 : 1; /*!< reserved */
|
||||
uint32_t HCLKS : 3; /*!< HCLK */
|
||||
uint32_t resvd6 : 5; /*!< reserved */
|
||||
} SCFGR_f;
|
||||
};
|
||||
} stc_clock_scale_t;
|
||||
|
||||
/**
|
||||
* @brief CLK PLL configuration structure definition
|
||||
* @note PLL for MPLL
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t u8PLLState; /*!< PLL new state, @ref CLK_PLL_Config for details */
|
||||
union {
|
||||
uint32_t PLLCFGR; /*!< PLL config register */
|
||||
struct {
|
||||
uint32_t PLLM : 5; /*!< PLL M divide */
|
||||
uint32_t resvd0 : 2; /*!< reserved */
|
||||
uint32_t PLLSRC : 1; /*!< PLL/PLLA source clock select */
|
||||
uint32_t PLLN : 9; /*!< PLL N multi */
|
||||
uint32_t resvd1 : 3; /*!< reserved */
|
||||
uint32_t PLLR : 4; /*!< PLL R divide */
|
||||
uint32_t PLLQ : 4; /*!< PLL Q divide */
|
||||
uint32_t PLLP : 4; /*!< PLL P divide */
|
||||
} PLLCFGR_f;
|
||||
};
|
||||
} stc_clock_pll_init_t;
|
||||
|
||||
/**
|
||||
* @brief CLK PLLx configuration structure definition
|
||||
* @note PLLx for UPLL while HC32F460,HC32F451,HC32F452
|
||||
* PLLx for PLLA while HC32F4A0
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t u8PLLState; /*!< PLLx new state, @ref CLK_PLLx_State for details */
|
||||
union {
|
||||
uint32_t PLLCFGR; /*!< PLLx config register */
|
||||
struct {
|
||||
uint32_t PLLM : 5; /*!< PLLx M divide */
|
||||
uint32_t resvd0 : 3; /*!< reserved */
|
||||
uint32_t PLLN : 9; /*!< PLLx N multi- */
|
||||
uint32_t resvd1 : 3; /*!< reserved */
|
||||
uint32_t PLLR : 4; /*!< PLLx R divide */
|
||||
uint32_t PLLQ : 4; /*!< PLLx Q divide */
|
||||
uint32_t PLLP : 4; /*!< PLLx P divide */
|
||||
} PLLCFGR_f;
|
||||
};
|
||||
} stc_clock_pllx_init_t;
|
||||
|
||||
/**
|
||||
* @brief CLK bus frequency structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32SysclkFreq; /*!< System clock frequency. */
|
||||
uint32_t u32HclkFreq; /*!< Hclk frequency. */
|
||||
uint32_t u32Pclk0Freq; /*!< Pclk0 frequency. */
|
||||
uint32_t u32Pclk1Freq; /*!< Pclk1 frequency. */
|
||||
uint32_t u32Pclk2Freq; /*!< Pclk2 frequency. */
|
||||
uint32_t u32Pclk3Freq; /*!< Pclk3 frequency. */
|
||||
uint32_t u32Pclk4Freq; /*!< Pclk4 frequency. */
|
||||
uint32_t u32ExclkFreq; /*!< Exclk frequency. */
|
||||
} stc_clock_freq_t;
|
||||
|
||||
/**
|
||||
* @brief CLK PLL clock frequency structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32PllVcin; /*!< PLL vcin clock frequency. */
|
||||
uint32_t u32PllVco; /*!< PLL vco clock frequency. */
|
||||
uint32_t u32PllP; /*!< PLLp clock frequency. */
|
||||
uint32_t u32PllQ; /*!< PLLq clock frequency. */
|
||||
uint32_t u32PllR; /*!< PLLr clock frequency. */
|
||||
uint32_t u32PllxVcin; /*!< pllx vcin clock frequency. */
|
||||
uint32_t u32PllxVco; /*!< pllx vco clock frequency. */
|
||||
uint32_t u32PllxP; /*!< pllxp clock frequency. */
|
||||
uint32_t u32PllxQ; /*!< pllxq clock frequency. */
|
||||
uint32_t u32PllxR; /*!< pllxr clock frequency. */
|
||||
} stc_pll_clock_freq_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup CLK_Global_Macros CLK Global Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @defgroup CLK_PLLx_State CLK PLLx State
|
||||
* @note PLLx for UPLL while HC32F460,HC32F451,HC32F452
|
||||
* PLLx for PLLA while HC32F4A0
|
||||
* @{
|
||||
*/
|
||||
#define CLK_PLLX_OFF (0x01U)
|
||||
#define CLK_PLLX_ON (0x00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_PLL_Config PLL Config
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief PLL function config.
|
||||
*/
|
||||
#define CLK_PLL_OFF (0x01U)
|
||||
#define CLK_PLL_ON (0x00U)
|
||||
|
||||
/**
|
||||
* @brief PLL source clock selection.
|
||||
*/
|
||||
#define CLK_PLL_SRC_XTAL (0x00UL)
|
||||
#define CLK_PLL_SRC_HRC (0x01UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_XTAL_Config XTAL Config
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief XTAL function config.
|
||||
*/
|
||||
#define CLK_XTAL_OFF (CMU_XTALCR_XTALSTP)
|
||||
#define CLK_XTAL_ON (0x00U)
|
||||
|
||||
/**
|
||||
* @brief XTAL driver ability
|
||||
* @note
|
||||
* @verbatim
|
||||
* High | Mid | Low | ULow |
|
||||
* [20~25] | [16~20) | (8~16) | [4~8] |
|
||||
* @endverbatim
|
||||
*/
|
||||
#define CLK_XTAL_DRV_HIGH (0x00U << CMU_XTALCFGR_XTALDRV_POS)
|
||||
#define CLK_XTAL_DRV_MID (0x01U << CMU_XTALCFGR_XTALDRV_POS)
|
||||
#define CLK_XTAL_DRV_LOW (0x02U << CMU_XTALCFGR_XTALDRV_POS)
|
||||
#define CLK_XTAL_DRV_ULOW (0x03U << CMU_XTALCFGR_XTALDRV_POS)
|
||||
|
||||
/**
|
||||
* @brief XTAL super drive on or off
|
||||
*/
|
||||
#define CLK_XTAL_SUPDRV_ON (CMU_XTALCFGR_SUPDRV)
|
||||
#define CLK_XTAL_SUPDRV_OFF (0x00U)
|
||||
|
||||
/**
|
||||
* @brief XTAL mode selection osc or exclk
|
||||
*/
|
||||
#define CLK_XTAL_MD_OSC (0x00U)
|
||||
#define CLK_XTAL_MD_EXCLK (CMU_XTALCFGR_XTALMS)
|
||||
|
||||
/**
|
||||
* @brief XTAL stable time selection.
|
||||
* @note a cycle of stable counter = a cycle of LRC divide by 8
|
||||
*/
|
||||
#define CLK_XTAL_STB_133US (0x01U) /*!< 35 stable count cycle, approx. 133us */
|
||||
#define CLK_XTAL_STB_255US (0x02U) /*!< 67 stable count cycle, approx. 255us */
|
||||
#define CLK_XTAL_STB_499US (0x03U) /*!< 131 stable count cycle, approx. 499us */
|
||||
#define CLK_XTAL_STB_988US (0x04U) /*!< 259 stable count cycle, approx. 988us */
|
||||
#define CLK_XTAL_STB_2MS (0x05U) /*!< 547 stable count cycle, approx. 2ms */
|
||||
#define CLK_XTAL_STB_4MS (0x06U) /*!< 1059 stable count cycle, approx. 4ms */
|
||||
#define CLK_XTAL_STB_8MS (0x07U) /*!< 2147 stable count cycle, approx. 8ms */
|
||||
#define CLK_XTAL_STB_16MS (0x08U) /*!< 4291 stable count cycle, approx. 16ms */
|
||||
#define CLK_XTAL_STB_31MS (0x09U) /*!< 8163 stable count cycle, approx. 32ms */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_XTALSTD_Config XTALSTD Config
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief XTAL error detection on or off
|
||||
*/
|
||||
#define CLK_XTALSTD_OFF (0x00U)
|
||||
#define CLK_XTALSTD_ON (CMU_XTALSTDCR_XTALSTDE)
|
||||
|
||||
/**
|
||||
* @brief XTALSTD mode selection
|
||||
*/
|
||||
#define CLK_XTALSTD_MD_RST (CMU_XTALSTDCR_XTALSTDRIS)
|
||||
#define CLK_XTALSTD_MD_INT (0x00U)
|
||||
|
||||
/**
|
||||
* @brief XTALSTD reset on or off
|
||||
*/
|
||||
#define CLK_XTALSTD_RST_OFF (0x00U)
|
||||
#define CLK_XTALSTD_RST_ON (CMU_XTALSTDCR_XTALSTDRE)
|
||||
|
||||
/**
|
||||
* @brief XTALSTD interrupt on or off
|
||||
*/
|
||||
#define CLK_XTALSTD_INT_OFF (0x00U)
|
||||
#define CLK_XTALSTD_INT_ON (CMU_XTALSTDCR_XTALSTDIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_XTAL32_Config XTAL32 Config
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief XTAL32 function config.
|
||||
*/
|
||||
#define CLK_XTAL32_OFF (CMU_XTAL32CR_XTAL32STP)
|
||||
#define CLK_XTAL32_ON (0x00U)
|
||||
|
||||
/**
|
||||
* @brief XTAL32 driver ability.
|
||||
*/
|
||||
#define CLK_XTAL32_DRV_MID (0x00U)
|
||||
#define CLK_XTAL32_DRV_HIGH (0x01U)
|
||||
|
||||
/**
|
||||
* @brief XTAL32 filtering selection.
|
||||
*/
|
||||
#define CLK_XTAL32_FILTER_ALL_MD (0x00U) /*!< Valid in run,stop,power down mode. */
|
||||
#define CLK_XTAL32_FILTER_RUN_MD (0x01U) /*!< Valid in run mode. */
|
||||
#define CLK_XTAL32_FILTER_OFF (0x03U) /*!< Invalid in run,stop,power down mode. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_HRC_Config HRC Config
|
||||
* @{
|
||||
*/
|
||||
#define CLK_HRC_OFF (CMU_HRCCR_HRCSTP)
|
||||
#define CLK_HRC_ON (0x00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_STB_Flag CLK Stable Flags
|
||||
* @{
|
||||
*/
|
||||
#define CLK_STB_FLAG_HRC (CMU_OSCSTBSR_HRCSTBF)
|
||||
#define CLK_STB_FLAG_XTAL (CMU_OSCSTBSR_XTALSTBF)
|
||||
#define CLK_STB_FLAG_PLL (CMU_OSCSTBSR_MPLLSTBF)
|
||||
#define CLK_STB_FLAG_PLLX (CMU_OSCSTBSR_UPLLSTBF)
|
||||
#define CLK_STB_FLAG_MASK (CMU_OSCSTBSR_HRCSTBF | CMU_OSCSTBSR_XTALSTBF | \
|
||||
CMU_OSCSTBSR_MPLLSTBF | CMU_OSCSTBSR_UPLLSTBF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_System_Clock_Source System Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define CLK_SYSCLK_SRC_HRC (0x00U)
|
||||
#define CLK_SYSCLK_SRC_MRC (0x01U)
|
||||
#define CLK_SYSCLK_SRC_LRC (0x02U)
|
||||
#define CLK_SYSCLK_SRC_XTAL (0x03U)
|
||||
#define CLK_SYSCLK_SRC_XTAL32 (0x04U)
|
||||
#define CLK_SYSCLK_SRC_PLL (0x05U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_Bus_Clock_Sel Clock Bus Clock Category Selection
|
||||
* @{
|
||||
*/
|
||||
#define CLK_BUS_PCLK0 (CMU_SCFGR_PCLK0S)
|
||||
#define CLK_BUS_PCLK1 (CMU_SCFGR_PCLK1S)
|
||||
#define CLK_BUS_PCLK2 (CMU_SCFGR_PCLK2S)
|
||||
#define CLK_BUS_PCLK3 (CMU_SCFGR_PCLK3S)
|
||||
#define CLK_BUS_PCLK4 (CMU_SCFGR_PCLK4S)
|
||||
#define CLK_BUS_EXCLK (CMU_SCFGR_EXCKS)
|
||||
#define CLK_BUS_HCLK (CMU_SCFGR_HCLKS)
|
||||
#define CLK_BUS_CLK_ALL (CLK_BUS_PCLK0 | CLK_BUS_PCLK1 | CLK_BUS_PCLK2 | CLK_BUS_PCLK3 | \
|
||||
CLK_BUS_PCLK4 | CLK_BUS_EXCLK | CLK_BUS_HCLK)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_Clock_Divider Clock Divider
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_System_Clock_Divider System Clock Divider
|
||||
* @{
|
||||
*/
|
||||
#define CLK_SYSCLK_DIV1 (0x00U)
|
||||
#define CLK_SYSCLK_DIV2 (0x01U)
|
||||
#define CLK_SYSCLK_DIV4 (0x02U)
|
||||
#define CLK_SYSCLK_DIV8 (0x03U)
|
||||
#define CLK_SYSCLK_DIV16 (0x04U)
|
||||
#define CLK_SYSCLK_DIV32 (0x05U)
|
||||
#define CLK_SYSCLK_DIV64 (0x06U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_HCLK_Divider CLK HCLK Divider
|
||||
* @{
|
||||
*/
|
||||
#define CLK_HCLK_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_HCLKS_POS)
|
||||
#define CLK_HCLK_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_HCLKS_POS)
|
||||
#define CLK_HCLK_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_HCLKS_POS)
|
||||
#define CLK_HCLK_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_HCLKS_POS)
|
||||
#define CLK_HCLK_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_HCLKS_POS)
|
||||
#define CLK_HCLK_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_HCLKS_POS)
|
||||
#define CLK_HCLK_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_HCLKS_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_PCLK1_Divider CLK PCLK1 Divider
|
||||
* @{
|
||||
*/
|
||||
#define CLK_PCLK1_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK1S_POS)
|
||||
#define CLK_PCLK1_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK1S_POS)
|
||||
#define CLK_PCLK1_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK1S_POS)
|
||||
#define CLK_PCLK1_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK1S_POS)
|
||||
#define CLK_PCLK1_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK1S_POS)
|
||||
#define CLK_PCLK1_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK1S_POS)
|
||||
#define CLK_PCLK1_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK1S_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_PCLK4_Divider CLK PCLK4 Divider
|
||||
* @{
|
||||
*/
|
||||
#define CLK_PCLK4_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK4S_POS)
|
||||
#define CLK_PCLK4_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK4S_POS)
|
||||
#define CLK_PCLK4_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK4S_POS)
|
||||
#define CLK_PCLK4_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK4S_POS)
|
||||
#define CLK_PCLK4_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK4S_POS)
|
||||
#define CLK_PCLK4_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK4S_POS)
|
||||
#define CLK_PCLK4_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK4S_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_PCLK3_Divider CLK PCLK3 Divider
|
||||
* @{
|
||||
*/
|
||||
#define CLK_PCLK3_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK3S_POS)
|
||||
#define CLK_PCLK3_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK3S_POS)
|
||||
#define CLK_PCLK3_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK3S_POS)
|
||||
#define CLK_PCLK3_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK3S_POS)
|
||||
#define CLK_PCLK3_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK3S_POS)
|
||||
#define CLK_PCLK3_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK3S_POS)
|
||||
#define CLK_PCLK3_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK3S_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_EXCLK_Divider CLK EXCLK Divider
|
||||
* @{
|
||||
*/
|
||||
#define CLK_EXCLK_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_EXCKS_POS)
|
||||
#define CLK_EXCLK_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_EXCKS_POS)
|
||||
#define CLK_EXCLK_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_EXCKS_POS)
|
||||
#define CLK_EXCLK_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_EXCKS_POS)
|
||||
#define CLK_EXCLK_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_EXCKS_POS)
|
||||
#define CLK_EXCLK_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_EXCKS_POS)
|
||||
#define CLK_EXCLK_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_EXCKS_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_PCLK2_Divider CLK PCLK2 Divider
|
||||
* @{
|
||||
*/
|
||||
#define CLK_PCLK2_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK2S_POS)
|
||||
#define CLK_PCLK2_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK2S_POS)
|
||||
#define CLK_PCLK2_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK2S_POS)
|
||||
#define CLK_PCLK2_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK2S_POS)
|
||||
#define CLK_PCLK2_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK2S_POS)
|
||||
#define CLK_PCLK2_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK2S_POS)
|
||||
#define CLK_PCLK2_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK2S_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_PCLK0_Divider CLK PCLK0 Divider
|
||||
* @{
|
||||
*/
|
||||
#define CLK_PCLK0_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK0S_POS)
|
||||
#define CLK_PCLK0_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK0S_POS)
|
||||
#define CLK_PCLK0_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK0S_POS)
|
||||
#define CLK_PCLK0_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK0S_POS)
|
||||
#define CLK_PCLK0_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK0S_POS)
|
||||
#define CLK_PCLK0_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK0S_POS)
|
||||
#define CLK_PCLK0_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK0S_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_USBCLK_Sel CLK USB Clock Selection
|
||||
* @{
|
||||
*/
|
||||
#define CLK_USBCLK_SYSCLK_DIV2 (0x02U << CMU_USBCKCFGR_USBCKS_POS)
|
||||
#define CLK_USBCLK_SYSCLK_DIV3 (0x03U << CMU_USBCKCFGR_USBCKS_POS)
|
||||
#define CLK_USBCLK_SYSCLK_DIV4 (0x04U << CMU_USBCKCFGR_USBCKS_POS)
|
||||
#define CLK_USBCLK_PLLP (0x08U << CMU_USBCKCFGR_USBCKS_POS)
|
||||
#define CLK_USBCLK_PLLQ (0x09U << CMU_USBCKCFGR_USBCKS_POS)
|
||||
#define CLK_USBCLK_PLLR (0x0AU << CMU_USBCKCFGR_USBCKS_POS)
|
||||
#define CLK_USBCLK_PLLXP (0x0BU << CMU_USBCKCFGR_USBCKS_POS)
|
||||
#define CLK_USBCLK_PLLXQ (0x0CU << CMU_USBCKCFGR_USBCKS_POS)
|
||||
#define CLK_USBCLK_PLLXR (0x0DU << CMU_USBCKCFGR_USBCKS_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_PERIPH_Sel CLK Peripheral Clock Selection
|
||||
* @note ADC,I2S,DAC,TRNG
|
||||
* @{
|
||||
*/
|
||||
/* PCLK2 is used for ADC clock, PCLK3 is used for I2S clock, PCLK4 is used for DAC/TRNG clock */
|
||||
#define CLK_PERIPHCLK_PCLK (0x0000U)
|
||||
#define CLK_PERIPHCLK_PLLP (0x0008U)
|
||||
#define CLK_PERIPHCLK_PLLQ (0x0009U)
|
||||
#define CLK_PERIPHCLK_PLLR (0x000AU)
|
||||
#define CLK_PERIPHCLK_PLLXP (0x000BU)
|
||||
#define CLK_PERIPHCLK_PLLXQ (0x000CU)
|
||||
#define CLK_PERIPHCLK_PLLXR (0x000DU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_I2S_Sel CLK I2S Channel Selection
|
||||
* @{
|
||||
*/
|
||||
#define CLK_I2S1 (0x00U)
|
||||
#define CLK_I2S2 (0x01U)
|
||||
#define CLK_I2S3 (0x02U)
|
||||
#define CLK_I2S4 (0x03U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_TPIU_Divider TPIU clock divider
|
||||
* @{
|
||||
*/
|
||||
#define CLK_TPIUCLK_DIV1 (0x00U)
|
||||
#define CLK_TPIUCLK_DIV2 (0x01U)
|
||||
#define CLK_TPIUCLK_DIV4 (0x02U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_MCO_Channel_Sel CLK MCO Channel Select
|
||||
* @{
|
||||
*/
|
||||
#define CLK_MCO1 (0x00U)
|
||||
#define CLK_MCO2 (0x01U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_MCO_Clock_Source CLK MCO Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define CLK_MCO_SRC_HRC (0x00U)
|
||||
#define CLK_MCO_SRC_MRC (0x01U)
|
||||
#define CLK_MCO_SRC_LRC (0x02U)
|
||||
#define CLK_MCO_SRC_XTAL (0x03U)
|
||||
#define CLK_MCO_SRC_XTAL32 (0x04U)
|
||||
#define CLK_MCO_SRC_PLLP (0x06U)
|
||||
#define CLK_MCO_SRC_PLLXP (0x07U)
|
||||
#define CLK_MCO_SRC_PLLQ (0x08U)
|
||||
#define CLK_MCO_SRC_PLLXQ (0x09U)
|
||||
#define CLK_MCO_SRC_HCLK (0x0BU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CLK_MCO_Clock_Prescaler CLK MCO Clock Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define CLK_MCO_DIV1 (0x00U << CMU_MCOCFGR_MCODIV_POS)
|
||||
#define CLK_MCO_DIV2 (0x01U << CMU_MCOCFGR_MCODIV_POS)
|
||||
#define CLK_MCO_DIV4 (0x02U << CMU_MCOCFGR_MCODIV_POS)
|
||||
#define CLK_MCO_DIV8 (0x03U << CMU_MCOCFGR_MCODIV_POS)
|
||||
#define CLK_MCO_DIV16 (0x04U << CMU_MCOCFGR_MCODIV_POS)
|
||||
#define CLK_MCO_DIV32 (0x05U << CMU_MCOCFGR_MCODIV_POS)
|
||||
#define CLK_MCO_DIV64 (0x06U << CMU_MCOCFGR_MCODIV_POS)
|
||||
#define CLK_MCO_DIV128 (0x07U << CMU_MCOCFGR_MCODIV_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup CLK_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
int32_t CLK_HrcCmd(en_functional_state_t enNewState);
|
||||
int32_t CLK_MrcCmd(en_functional_state_t enNewState);
|
||||
int32_t CLK_LrcCmd(en_functional_state_t enNewState);
|
||||
|
||||
void CLK_HrcTrim(int8_t i8TrimVal);
|
||||
void CLK_MrcTrim(int8_t i8TrimVal);
|
||||
void CLK_LrcTrim(int8_t i8TrimVal);
|
||||
|
||||
int32_t CLK_XtalStructInit(stc_clock_xtal_init_t *pstcXtalInit);
|
||||
int32_t CLK_XtalInit(const stc_clock_xtal_init_t *pstcXtalInit);
|
||||
int32_t CLK_XtalCmd(en_functional_state_t enNewState);
|
||||
|
||||
int32_t CLK_XtalStdStructInit(stc_clock_xtalstd_init_t *pstcXtalStdInit);
|
||||
int32_t CLK_XtalStdInit(const stc_clock_xtalstd_init_t *pstcXtalStdInit);
|
||||
void CLK_ClearXtalStdStatus(void);
|
||||
en_flag_status_t CLK_GetXtalStdStatus(void);
|
||||
|
||||
int32_t CLK_Xtal32StructInit(stc_clock_xtal32_init_t *pstcXtal32Init);
|
||||
int32_t CLK_Xtal32Init(const stc_clock_xtal32_init_t *pstcXtal32Init);
|
||||
int32_t CLK_Xtal32Cmd(en_functional_state_t enNewState);
|
||||
|
||||
void CLK_SetPLLSrc(uint32_t u32PllSrc);
|
||||
int32_t CLK_PLLStructInit(stc_clock_pll_init_t *pstcPLLInit);
|
||||
int32_t CLK_PLLInit(const stc_clock_pll_init_t *pstcPLLInit);
|
||||
int32_t CLK_PLLCmd(en_functional_state_t enNewState);
|
||||
int32_t CLK_GetPLLClockFreq(stc_pll_clock_freq_t *pstcPllClkFreq);
|
||||
int32_t CLK_PLLxStructInit(stc_clock_pllx_init_t *pstcPLLxInit);
|
||||
int32_t CLK_PLLxInit(const stc_clock_pllx_init_t *pstcPLLxInit);
|
||||
int32_t CLK_PLLxCmd(en_functional_state_t enNewState);
|
||||
|
||||
void CLK_MCOConfig(uint8_t u8Ch, uint8_t u8Src, uint8_t u8Div);
|
||||
void CLK_MCOCmd(uint8_t u8Ch, en_functional_state_t enNewState);
|
||||
|
||||
en_flag_status_t CLK_GetStableStatus(uint8_t u8Flag);
|
||||
void CLK_SetSysClockSrc(uint8_t u8Src);
|
||||
void CLK_SetClockDiv(uint32_t u32Clock, uint32_t u32Div);
|
||||
int32_t CLK_GetClockFreq(stc_clock_freq_t *pstcClockFreq);
|
||||
uint32_t CLK_GetBusClockFreq(uint32_t u32Clock);
|
||||
|
||||
void CLK_SetPeriClockSrc(uint16_t u16Src);
|
||||
void CLK_SetUSBClockSrc(uint8_t u8Src);
|
||||
void CLK_SetI2SClockSrc(uint8_t u8Unit, uint8_t u8Src);
|
||||
|
||||
void CLK_TpiuClockCmd(en_functional_state_t enNewState);
|
||||
void CLK_SetTpiuClockDiv(uint8_t u8Div);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_CLK_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_CLK_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,275 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_cmp.h
|
||||
* @brief This file contains all the functions prototypes of the CMP driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2022-06-30 CDT Modify macro define for API
|
||||
2023-01-15 CDT Code refine for scan function
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_CMP_H__
|
||||
#define __HC32_LL_CMP_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_CMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_CMP_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup CMP_Global_Types CMP Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CMP normal mode configuration structure
|
||||
*/
|
||||
typedef struct {
|
||||
uint16_t u16PositiveInput; /*!< Positive(compare voltage) input @ref CMP_Positive_Input_Select */
|
||||
uint16_t u16NegativeInput; /*!< Negative(Reference voltage) input @ref CMP_Negative_Input_Select */
|
||||
uint16_t u16OutPolarity; /*!< Output polarity select, @ref CMP_Out_Polarity_Select */
|
||||
uint16_t u16OutDetectEdge; /*!< Output detect edge, @ref CMP_Out_Detect_Edge_Select */
|
||||
uint16_t u16OutFilter; /*!< Output Filter, @ref CMP_Out_Filter */
|
||||
} stc_cmp_init_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @defgroup CMP_Global_Macros CMP Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define VISR_OFFSET (8U)
|
||||
|
||||
/**
|
||||
* @defgroup CMP_Positive_Input_Select CMP Positive(Compare) Voltage Input
|
||||
* @{
|
||||
*/
|
||||
#define CMP_POSITIVE_NONE (0x0U)
|
||||
/* Note:
|
||||
Normal mode:
|
||||
1) Select one positive input from the following values.
|
||||
Scan mode:
|
||||
2) Select any combination of the following values, but the XXX_PGAO/ XXX_PGAO_BP/ XXX_CMP1_INP4/ XXX_CMP3_INP4
|
||||
should not be valid at the same time.
|
||||
*/
|
||||
/* CMP1 */
|
||||
#define CMP1_POSITIVE_CMP1_INP1 (CMP_VLTSEL_CVSL_0) /*!< Pin CMP1_INP1 */
|
||||
#define CMP1_POSITIVE_CMP1_INP2 (CMP_VLTSEL_CVSL_1) /*!< Pin CMP1_INP2 */
|
||||
#define CMP1_POSITIVE_CMP1_INP3 (CMP_VLTSEL_CVSL_2) /*!< Pin CMP1_INP3 */
|
||||
#define CMP1_POSITIVE_PGAO (CMP_VLTSEL_CVSL_3 | CMP_VLTSEL_C4SL_0) /*!< Internal voltage PGAO */
|
||||
#define CMP1_POSITIVE_PGAO_BP (CMP_VLTSEL_CVSL_3 | CMP_VLTSEL_C4SL_1) /*!< Internal voltage PGAO_BP */
|
||||
#define CMP1_POSITIVE_CMP1_INP4 (CMP_VLTSEL_CVSL_3 | CMP_VLTSEL_C4SL_2) /*!< Pin CMP1_INP4 */
|
||||
/* CMP2 */
|
||||
#define CMP2_POSITIVE_CMP2_INP1 (CMP_VLTSEL_CVSL_0) /*!< Pin CMP2_INP1 */
|
||||
#define CMP2_POSITIVE_CMP2_INP2 (CMP_VLTSEL_CVSL_1) /*!< Pin CMP2_INP2 */
|
||||
#define CMP2_POSITIVE_CMP2_INP3 (CMP_VLTSEL_CVSL_2) /*!< Pin CMP2_INP3 */
|
||||
#define CMP2_POSITIVE_PGAO (CMP_VLTSEL_CVSL_3 | CMP_VLTSEL_C4SL_0) /*!< Internal voltage PGAO */
|
||||
#define CMP2_POSITIVE_PGAO_BP (CMP_VLTSEL_CVSL_3 | CMP_VLTSEL_C4SL_1) /*!< Internal voltage PGAO_BP */
|
||||
/* CMP3 */
|
||||
#define CMP3_POSITIVE_CMP3_INP1 (CMP_VLTSEL_CVSL_0) /*!< Pin CMP3_INP1 */
|
||||
#define CMP3_POSITIVE_CMP3_INP2 (CMP_VLTSEL_CVSL_1) /*!< Pin CMP3_INP2 */
|
||||
#define CMP3_POSITIVE_CMP3_INP3 (CMP_VLTSEL_CVSL_2) /*!< Pin CMP3_INP3 */
|
||||
#define CMP3_POSITIVE_CMP3_INP4 (CMP_VLTSEL_CVSL_3) /*!< Pin CMP3_INP4 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CMP_Scan_Inp_Status CMP Scan Function Positive In INP Source
|
||||
* @{
|
||||
*/
|
||||
#define CMP_SCAN_STAT_INP_NONE (0U)
|
||||
#define CMP_SCAN_STAT_INP1 (1U << CMP_OUTMON_CVST_POS)
|
||||
#define CMP_SCAN_STAT_INP2 (2U << CMP_OUTMON_CVST_POS)
|
||||
#define CMP_SCAN_STAT_INP3 (4U << CMP_OUTMON_CVST_POS)
|
||||
#define CMP_SCAN_STAT_INP4 (8U << CMP_OUTMON_CVST_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CMP_Negative_Input_Select CMP Negative(Reference) Voltage Input
|
||||
* @{
|
||||
*/
|
||||
#define CMP_NEGATIVE_NONE (0x0U)
|
||||
/* Negative input select table
|
||||
CMP1 CMP2 CMP3
|
||||
----------------------------------------------------
|
||||
INM1 CMP1_INM1 CMP2_INM1 CMP3_INM1
|
||||
INM2 CMP1_INM2 CMP2_INM2 CMP3_INM2
|
||||
INM3 DAC1 DAC2 DAC1
|
||||
INM4 VREF VREF DAC2
|
||||
*/
|
||||
#define CMP_NEGATIVE_INM1 (1U << CMP_VLTSEL_RVSL_POS)
|
||||
#define CMP_NEGATIVE_INM2 (2U << CMP_VLTSEL_RVSL_POS)
|
||||
#define CMP_NEGATIVE_INM3 (4U << CMP_VLTSEL_RVSL_POS)
|
||||
#define CMP_NEGATIVE_INM4 (8U << CMP_VLTSEL_RVSL_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CMP_Out_Polarity_Select CMP Output Polarity
|
||||
* @{
|
||||
*/
|
||||
#define CMP_OUT_INVT_OFF (0x0U) /*!< CMP output don't reverse */
|
||||
#define CMP_OUT_INVT_ON (CMP_CTRL_INV) /*!< CMP output level reverse */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CMP_Out_Detect_Edge_Select CMP Output Detect Edge
|
||||
* @{
|
||||
*/
|
||||
#define CMP_DETECT_EDGS_NONE (0U) /*!< Do not detect edge */
|
||||
#define CMP_DETECT_EDGS_RISING (1U << CMP_CTRL_EDGSL_POS) /*!< Detect rising edge */
|
||||
#define CMP_DETECT_EDGS_FALLING (2U << CMP_CTRL_EDGSL_POS) /*!< Detect falling edge */
|
||||
#define CMP_DETECT_EDGS_BOTH (3U << CMP_CTRL_EDGSL_POS) /*!< Detect rising and falling edges */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CMP_Out_Filter CMP Output Filter Configuration
|
||||
* @{
|
||||
*/
|
||||
#define CMP_OUT_FILTER_NONE (0U) /*!< Do not filter */
|
||||
#define CMP_OUT_FILTER_CLK (1U << CMP_CTRL_FLTSL_POS)
|
||||
#define CMP_OUT_FILTER_CLK_DIV2 (2U << CMP_CTRL_FLTSL_POS)
|
||||
#define CMP_OUT_FILTER_CLK_DIV4 (3U << CMP_CTRL_FLTSL_POS)
|
||||
#define CMP_OUT_FILTER_CLK_DIV8 (4U << CMP_CTRL_FLTSL_POS)
|
||||
#define CMP_OUT_FILTER_CLK_DIV16 (5U << CMP_CTRL_FLTSL_POS)
|
||||
#define CMP_OUT_FILTER_CLK_DIV32 (6U << CMP_CTRL_FLTSL_POS)
|
||||
#define CMP_OUT_FILTER_CLK_DIV64 (7U << CMP_CTRL_FLTSL_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CMP_8BitDAC_Adc_Ref_Switch CMP 8 bit DAC ADC Reference Voltage Switch
|
||||
* @{
|
||||
*/
|
||||
#define CMP_ADC_REF_VREF (CMPCR_RVADC_VREFSW)
|
||||
#define CMP_ADC_REF_DA2 (CMPCR_RVADC_DA2SW)
|
||||
#define CMP_ADC_REF_DA1 (CMPCR_RVADC_DA1SW)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CMP_8Bit_Dac_Ch CMP 8 bit DAC Channel
|
||||
* @{
|
||||
*/
|
||||
#define CMP_8BITDAC_CH1 (CMPCR_DACR_DA1EN)
|
||||
#define CMP_8BITDAC_CH2 (CMPCR_DACR_DA2EN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup CMP_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
int32_t CMP_StructInit(stc_cmp_init_t *pstcCmpInit);
|
||||
int32_t CMP_NormalModeInit(CM_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcCmpInit);
|
||||
void CMP_DeInit(CM_CMP_TypeDef *CMPx);
|
||||
|
||||
void CMP_FuncCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState);
|
||||
void CMP_IntCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState);
|
||||
void CMP_CompareOutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState);
|
||||
void CMP_PinVcoutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState);
|
||||
en_flag_status_t CMP_GetStatus(const CM_CMP_TypeDef *CMPx);
|
||||
void CMP_SetOutDetectEdge(CM_CMP_TypeDef *CMPx, uint8_t u8CmpEdges);
|
||||
void CMP_SetOutFilter(CM_CMP_TypeDef *CMPx, uint8_t u8CmpFilter);
|
||||
void CMP_SetOutPolarity(CM_CMP_TypeDef *CMPx, uint16_t u16CmpPolarity);
|
||||
void CMP_SetPositiveInput(CM_CMP_TypeDef *CMPx, uint16_t u16PositiveInput);
|
||||
void CMP_SetNegativeInput(CM_CMP_TypeDef *CMPx, uint16_t u16NegativeInput);
|
||||
|
||||
uint32_t CMP_GetScanInpSrc(CM_CMP_TypeDef *CMPx);
|
||||
int32_t CMP_ScanTimeConfig(CM_CMP_TypeDef *CMPx, uint16_t u16Stable, uint16_t u16Period);
|
||||
void CMP_ScanCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState);
|
||||
|
||||
void CMP_8BitDAC_Cmd(uint8_t u8Ch, en_functional_state_t enNewState);
|
||||
void CMP_8BitDAC_AdcRefCmd(uint16_t u16AdcRefSw, en_functional_state_t enNewState);
|
||||
|
||||
void CMP_8BitDAC_WriteData(uint8_t u8Ch, uint16_t u16DACData);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_CMP_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_CMP_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,203 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_crc.h
|
||||
* @brief This file contains all the functions prototypes of the CRC driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2023-06-30 CDT Reconstruct interface function relate to calculate CRC
|
||||
Modify return type of function CRC_DeInit
|
||||
2023-09-30 CDT Modify comment
|
||||
Delete and modify some of group/function relate to calculate CRC
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_CRC_H__
|
||||
#define __HC32_LL_CRC_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_CRC_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup CRC_Global_Types CRC Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CRC initialization structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32Protocol; /*!< Specifies CRC Protocol.
|
||||
This parameter can be a value of @ref CRC_Protocol_Control_Bit */
|
||||
uint32_t u32InitValue; /*!< Specifies initial CRC value.
|
||||
This parameter can be CRC_INIT_VALUE_DEFAULT @ref CRC_Init_Value_Default */
|
||||
uint32_t u32RefIn; /*!< Specifies CRC Retroflexion Input.
|
||||
This parameter can be a value of @ref CRC_Retroflexion_Input */
|
||||
uint32_t u32RefOut; /*!< Specifies CRC Retroflexion Output.
|
||||
This parameter can be a value of @ref CRC_Retroflexion_Output */
|
||||
uint32_t u32XorOut; /*!< Specifies CRC XOR Output.
|
||||
This parameter can be a value of @ref CRC_XOR_Output */
|
||||
} stc_crc_init_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup CRC_Global_Macros CRC Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CRC_Protocol_Control_Bit CRC Protocol Control Bit
|
||||
* @{
|
||||
*/
|
||||
#define CRC_CRC16 (0x0UL)
|
||||
#define CRC_CRC32 (CRC_CR_CR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CRC_DATA_Bit_Width CRC Data Bit Width
|
||||
* @{
|
||||
*/
|
||||
#define CRC_DATA_WIDTH_8BIT (1U)
|
||||
#define CRC_DATA_WIDTH_16BIT (2U)
|
||||
#define CRC_DATA_WIDTH_32BIT (4U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CRC_Init_Value_Default CRC Default Computation Initialization Value
|
||||
* @{
|
||||
*/
|
||||
#define CRC_INIT_VALUE_DEFAULT (0xFFFFFFFFUL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CRC_Retroflexion_Input CRC Retroflexion Input
|
||||
* @{
|
||||
*/
|
||||
#define CRC_REFIN_DISABLE (0x0UL)
|
||||
#define CRC_REFIN_ENABLE (CRC_CR_REFIN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CRC_Retroflexion_Output CRC Retroflexion Output
|
||||
* @{
|
||||
*/
|
||||
#define CRC_REFOUT_DISABLE (0x0UL)
|
||||
#define CRC_REFOUT_ENABLE (CRC_CR_REFOUT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CRC_XOR_Output CRC XOR Output
|
||||
* @{
|
||||
*/
|
||||
#define CRC_XOROUT_DISABLE (0x0UL)
|
||||
#define CRC_XOROUT_ENABLE (CRC_CR_XOROUT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup CRC_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
int32_t CRC_StructInit(stc_crc_init_t *pstcCrcInit);
|
||||
int32_t CRC_Init(const stc_crc_init_t *pstcCrcInit);
|
||||
int32_t CRC_DeInit(void);
|
||||
|
||||
en_flag_status_t CRC_GetResultStatus(void);
|
||||
|
||||
uint16_t CRC_CRC16_AccumulateData(uint8_t u8DataWidth, const void *pvData, uint32_t u32Len);
|
||||
uint16_t CRC_CRC16_Calculate(uint16_t u16InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len);
|
||||
en_flag_status_t CRC_CRC16_CheckData(uint16_t u16InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len, uint16_t u16ExpectValue);
|
||||
en_flag_status_t CRC_CRC16_GetCheckResult(uint16_t u16ExpectValue);
|
||||
|
||||
uint32_t CRC_CRC32_AccumulateData(uint8_t u8DataWidth, const void *pvData, uint32_t u32Len);
|
||||
uint32_t CRC_CRC32_Calculate(uint32_t u32InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len);
|
||||
en_flag_status_t CRC_CRC32_CheckData(uint32_t u32InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len, uint32_t u32ExpectValue);
|
||||
en_flag_status_t CRC_CRC32_GetCheckResult(uint32_t u32ExpectValue);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_CRC_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_CRC_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,175 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_dbgc.h
|
||||
* @brief This file contains all the functions prototypes of the DBGC driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2023-09-30 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_DBGC_H__
|
||||
#define __HC32_LL_DBGC_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_DBGC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_DBGC_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup DBGC_Global_Types DBGC Global Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief DBGC authenticate ID definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32AuthID0; /*!< auth ID 0. */
|
||||
uint32_t u32AuthID1; /*!< auth ID 1. */
|
||||
uint32_t u32AuthID2; /*!< auth ID 2. */
|
||||
} stc_dbgc_auth_id_t;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup DBGC_Global_Macros DBGC Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DBGC_MCU_Security_Flag DBGC MCU Security Status flag
|
||||
* @{
|
||||
*/
|
||||
#define DBGC_SECURITY_AUTH_SUCCESS (DBGC_MCUSTAT_AUTHFG) /*!< AUTHID register equal security password */
|
||||
#define DBGC_SECURITY_LOCK_LVL1 (DBGC_MCUSTAT_PRTLV1) /*!< Security lock level 1 */
|
||||
#define DBGC_SECURITY_LOCK_LVL2 (DBGC_MCUSTAT_PRTLV2) /*!< Security lock level 2 */
|
||||
#define DBGC_SECURITY_ALL (DBGC_MCUSTAT_AUTHFG | DBGC_MCUSTAT_PRTLV1 | DBGC_MCUSTAT_PRTLV2)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DBGC_Periph_Sel DBGC Periph Selection
|
||||
* @{
|
||||
*/
|
||||
#define DBGC_PERIPH_SWDT (DBGC_MCUSTPCTL_SWDTSTP)
|
||||
#define DBGC_PERIPH_WDT (DBGC_MCUSTPCTL_WDTSTP)
|
||||
#define DBGC_PERIPH_RTC (DBGC_MCUSTPCTL_RTCSTP)
|
||||
#define DBGC_PERIPH_TMR0_1 (DBGC_MCUSTPCTL_TMR01STP)
|
||||
#define DBGC_PERIPH_TMR0_2 (DBGC_MCUSTPCTL_TMR02STP)
|
||||
#define DBGC_PERIPH_TMR4_1 (DBGC_MCUSTPCTL_TMR41STP)
|
||||
#define DBGC_PERIPH_TMR4_2 (DBGC_MCUSTPCTL_TMR42STP)
|
||||
#define DBGC_PERIPH_TMR4_3 (DBGC_MCUSTPCTL_TMR43STP)
|
||||
#define DBGC_PERIPH_TMR6_1 (DBGC_MCUSTPCTL_TM61STP)
|
||||
#define DBGC_PERIPH_TMR6_2 (DBGC_MCUSTPCTL_TM62STP)
|
||||
#define DBGC_PERIPH_TMR6_3 (DBGC_MCUSTPCTL_TMR63STP)
|
||||
#define DBGC_PERIPH_TMRA_1 (DBGC_MCUSTPCTL_TMRA1STP)
|
||||
#define DBGC_PERIPH_TMRA_2 (DBGC_MCUSTPCTL_TMRA2STP)
|
||||
#define DBGC_PERIPH_TMRA_3 (DBGC_MCUSTPCTL_TMRA3STP)
|
||||
#define DBGC_PERIPH_TMRA_4 (DBGC_MCUSTPCTL_TMRA4STP)
|
||||
#define DBGC_PERIPH_TMRA_5 (DBGC_MCUSTPCTL_TMRA5STP)
|
||||
#define DBGC_PERIPH_TMRA_6 (DBGC_MCUSTPCTL_TMRA6STP)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DBGC_Periph2_Sel DBGC Periph2 Selection
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DBGC_Trace_Mode DBGC trace mode
|
||||
* @{
|
||||
*/
|
||||
#define DBGC_TRACE_ASYNC (0UL)
|
||||
#define DBGC_TRACE_SYNC_1BIT (DBGC_MCUTRACECTL_TRACEMODE_0)
|
||||
#define DBGC_TRACE_SYNC_2BIT (DBGC_MCUTRACECTL_TRACEMODE_1)
|
||||
#define DBGC_TRACE_SYNC_4BIT (DBGC_MCUTRACECTL_TRACEMODE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup DBGC_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
en_flag_status_t DBGC_GetSecurityStatus(uint32_t u32Flag);
|
||||
int32_t DBGC_FlashErase(uint32_t u32Timeout);
|
||||
void DBGC_GetAuthID(stc_dbgc_auth_id_t *pstcAuthID);
|
||||
void DBGC_PeriphCmd(uint32_t u32Periph, en_functional_state_t enNewState);
|
||||
void DBGC_TraceIoCmd(en_functional_state_t enNewState);
|
||||
void DBGC_TraceModeConfig(uint32_t u32TraceMode);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_DBGC_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_DBGC_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,268 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_dcu.h
|
||||
* @brief This file contains all the functions prototypes of the DCU(Data
|
||||
* Computing Unit) driver library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2022-06-30 CDT Modify macro group comments: DCU_Interrupt_Type
|
||||
2023-06-30 CDT Modify macro-definition according to RM:DCU_CTL_COMP_TRG->DCU_CTL_COMPTRG
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_DCU_H__
|
||||
#define __HC32_LL_DCU_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_DCU
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_DCU_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup DCU_Global_Types DCU Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DCU initialization structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32Mode; /*!< Specifies DCU operation.
|
||||
This parameter can be a value of @ref DCU_Mode */
|
||||
uint32_t u32DataWidth; /*!< Specifies DCU data width.
|
||||
This parameter can be a value of @ref DCU_Data_Width */
|
||||
} stc_dcu_init_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup DCU_Global_Macros DCU Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Data_Width DCU Data Width
|
||||
* @{
|
||||
*/
|
||||
#define DCU_DATA_WIDTH_8BIT (0UL) /*!< DCU data width: 8 bit */
|
||||
#define DCU_DATA_WIDTH_16BIT (DCU_CTL_DATASIZE_0) /*!< DCU data width: 16 bit */
|
||||
#define DCU_DATA_WIDTH_32BIT (DCU_CTL_DATASIZE_1) /*!< DCU data width: 32 bit */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Compare_Trigger_Condition DCU Compare Trigger Condition
|
||||
* @{
|
||||
*/
|
||||
#define DCU_CMP_TRIG_DATA0 (0UL) /*!< DCU compare triggered by DATA0 */
|
||||
#define DCU_CMP_TRIG_DATA0_DATA1_DATA2 (DCU_CTL_COMPTRG) /*!< DCU compare triggered by DATA0 or DATA1 or DATA2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Mode DCU Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCU_MD_INVD (0UL) /*!< DCU invalid */
|
||||
#define DCU_MD_ADD (1UL) /*!< DCU add operation */
|
||||
#define DCU_MD_SUB (2UL) /*!< DCU sub operation */
|
||||
#define DCU_MD_HW_ADD (3UL) /*!< DCU hardware trigger add */
|
||||
#define DCU_MD_HW_SUB (4UL) /*!< DCU hardware trigger sub */
|
||||
#define DCU_MD_CMP (5UL) /*!< DCU compare */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Flag DCU Flag
|
||||
* @{
|
||||
*/
|
||||
#define DCU_FLAG_CARRY (DCU_FLAG_FLAG_OP) /*!< DCU addition overflow or subtraction underflow flag */
|
||||
#define DCU_FLAG_DATA0_LT_DATA2 (DCU_FLAG_FLAG_LS2) /*!< DCU DATA0 < DATA2 flag */
|
||||
#define DCU_FLAG_DATA0_EQ_DATA2 (DCU_FLAG_FLAG_EQ2) /*!< DCU DATA0 = DATA2 flag */
|
||||
#define DCU_FLAG_DATA0_GT_DATA2 (DCU_FLAG_FLAG_GT2) /*!< DCU DATA0 > DATA2 flag */
|
||||
#define DCU_FLAG_DATA0_LT_DATA1 (DCU_FLAG_FLAG_LS1) /*!< DCU DATA0 < DATA1 flag */
|
||||
#define DCU_FLAG_DATA0_EQ_DATA1 (DCU_FLAG_FLAG_EQ1) /*!< DCU DATA0 = DATA1 flag */
|
||||
#define DCU_FLAG_DATA0_GT_DATA1 (DCU_FLAG_FLAG_GT1) /*!< DCU DATA0 > DATA1 flag */
|
||||
|
||||
#define DCU_FLAG_ALL (0x0000007FUL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Category DCU Category
|
||||
* @{
|
||||
*/
|
||||
#define DCU_CATEGORY_OP (0UL) /*!< DCU operation result(overflow/underflow) */
|
||||
#define DCU_CATEGORY_CMP_WIN (1UL) /*!< DCU comparison(window) */
|
||||
#define DCU_CATEGORY_CMP_NON_WIN (2UL) /*!< DCU comparison(non-window) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Interrupt_Type DCU Interrupt Type
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @defgroup DCU_Compare_Interrupt DCU Compare(Non-window) Interrupt
|
||||
* @note Interrupt type DCU_Compare_Interrupt is valid when only select DCU_CATEGORY_CMP_NON_WIN
|
||||
* @{
|
||||
*/
|
||||
#define DCU_INT_CMP_DATA0_LT_DATA2 (DCU_INTEVTSEL_SEL_LS2) /*!< DCU DATA0 < DATA2 interrupt */
|
||||
#define DCU_INT_CMP_DATA0_EQ_DATA2 (DCU_INTEVTSEL_SEL_EQ2) /*!< DCU DATA0 = DATA2 interrupt */
|
||||
#define DCU_INT_CMP_DATA0_GT_DATA2 (DCU_INTEVTSEL_SEL_GT2) /*!< DCU DATA0 > DATA2 interrupt */
|
||||
#define DCU_INT_CMP_DATA0_LT_DATA1 (DCU_INTEVTSEL_SEL_LS1) /*!< DCU DATA0 < DATA1 interrupt */
|
||||
#define DCU_INT_CMP_DATA0_EQ_DATA1 (DCU_INTEVTSEL_SEL_EQ1) /*!< DCU DATA0 = DATA1 interrupt */
|
||||
#define DCU_INT_CMP_DATA0_GT_DATA1 (DCU_INTEVTSEL_SEL_GT1) /*!< DCU DATA0 > DATA1 interrupt */
|
||||
#define DCU_INT_CMP_NON_WIN_ALL (DCU_INT_CMP_DATA0_LT_DATA2 | \
|
||||
DCU_INT_CMP_DATA0_EQ_DATA2 | \
|
||||
DCU_INT_CMP_DATA0_GT_DATA2 | \
|
||||
DCU_INT_CMP_DATA0_LT_DATA1 | \
|
||||
DCU_INT_CMP_DATA0_EQ_DATA1 | \
|
||||
DCU_INT_CMP_DATA0_GT_DATA1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Window_Compare_Interrupt DCU Window Compare Interrupt
|
||||
* @note Interrupt type DCU_Window_Compare_Interrupt is valid when only select DCU_CATEGORY_CMP_WIN
|
||||
* @{
|
||||
*/
|
||||
#define DCU_INT_CMP_WIN_INSIDE (DCU_INTEVTSEL_SEL_WIN_0) /*!< DCU comparison(DATA2 <= DATA0 <= DATA1) interrupt */
|
||||
#define DCU_INT_CMP_WIN_OUTSIDE (DCU_INTEVTSEL_SEL_WIN_1) /*!< DCU comparison(DATA0 < DATA2 & DATA0 > DATA1 ) interrupt */
|
||||
#define DCU_INT_CMP_WIN_ALL (DCU_INT_CMP_WIN_INSIDE | DCU_INT_CMP_WIN_OUTSIDE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Operation_Interrupt DCU Operation Interrupt
|
||||
* @note DCU_Window_Compare_Interrupt selection is valid when only select DCU_CATEGORY_OP
|
||||
* @{
|
||||
*/
|
||||
#define DCU_INT_OP_CARRY (DCU_INTEVTSEL_SEL_OP) /*!< DCU addition overflow or subtraction underflow interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Data_Register_Index DCU Data Register Index
|
||||
* @{
|
||||
*/
|
||||
#define DCU_DATA0_IDX (0UL) /*!< DCU DATA0 */
|
||||
#define DCU_DATA1_IDX (1UL) /*!< DCU DATA1 */
|
||||
#define DCU_DATA2_IDX (2UL) /*!< DCU DATA2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup DCU_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and configuration functions */
|
||||
int32_t DCU_Init(CM_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcDcuInit);
|
||||
int32_t DCU_StructInit(stc_dcu_init_t *pstcDcuInit);
|
||||
int32_t DCU_DeInit(CM_DCU_TypeDef *DCUx);
|
||||
|
||||
void DCU_SetMode(CM_DCU_TypeDef *DCUx, uint32_t u32Mode);
|
||||
void DCU_SetDataWidth(CM_DCU_TypeDef *DCUx, uint32_t u32DataWidth);
|
||||
void DCU_SetCompareCond(CM_DCU_TypeDef *DCUx, uint32_t u32Cond);
|
||||
|
||||
/* Interrupt and flag management functions */
|
||||
en_flag_status_t DCU_GetStatus(const CM_DCU_TypeDef *DCUx, uint32_t u32Flag);
|
||||
void DCU_ClearStatus(CM_DCU_TypeDef *DCUx, uint32_t u32Flag);
|
||||
void DCU_GlobalIntCmd(CM_DCU_TypeDef *DCUx, en_functional_state_t enNewState);
|
||||
void DCU_IntCmd(CM_DCU_TypeDef *DCUx, uint32_t u32IntCategory, uint32_t u32IntType, en_functional_state_t enNewState);
|
||||
|
||||
/* Read and write functions */
|
||||
uint8_t DCU_ReadData8(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex);
|
||||
void DCU_WriteData8(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint8_t u8Data);
|
||||
uint16_t DCU_ReadData16(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex);
|
||||
void DCU_WriteData16(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint16_t u16Data);
|
||||
uint32_t DCU_ReadData32(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex);
|
||||
void DCU_WriteData32(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint32_t u32Data);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_DCU_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_DCU_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,395 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_def.h
|
||||
* @brief This file contains LL common definitions: enumeration, macros and
|
||||
* structures definitions.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2023-01-15 CDT Implemented the definition of __NO_INIT for AC6 and ARM Compiler
|
||||
ARM Compiler suppress warning message: diag_1296
|
||||
2023-06-30 CDT Modify typo
|
||||
Add __NO_OPTIMIZE configuration item
|
||||
2023-09-30 CDT Add attribute for __RAM_FUNC definition
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_DEF_H__
|
||||
#define __HC32_LL_DEF_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Common
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup LL_Common_Global_Types LL Common Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Single precision floating point number (4 byte)
|
||||
*/
|
||||
typedef float float32_t;
|
||||
|
||||
/**
|
||||
* @brief Double precision floating point number (8 byte)
|
||||
*/
|
||||
typedef double float64_t;
|
||||
|
||||
/**
|
||||
* @brief Function pointer type to void/void function
|
||||
*/
|
||||
typedef void (*func_ptr_t)(void);
|
||||
|
||||
/**
|
||||
* @brief Functional state
|
||||
*/
|
||||
typedef enum {
|
||||
DISABLE = 0U,
|
||||
ENABLE = 1U,
|
||||
} en_functional_state_t;
|
||||
|
||||
/**
|
||||
* @brief Flag status
|
||||
*/
|
||||
typedef enum {
|
||||
RESET = 0U,
|
||||
SET = 1U,
|
||||
} en_flag_status_t, en_int_status_t;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup LL_Common_Global_Macros LL Common Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup Compiler_Macros Compiler Macros
|
||||
* @{
|
||||
*/
|
||||
#ifndef __UNUSED
|
||||
#define __UNUSED __attribute__((unused))
|
||||
#endif /* __UNUSED */
|
||||
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#ifndef __WEAKDEF
|
||||
#define __WEAKDEF __attribute__((weak))
|
||||
#endif /* __WEAKDEF */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN __attribute__((aligned(4)))
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#ifndef __NOINLINE
|
||||
#define __NOINLINE __attribute__((noinline))
|
||||
#endif /* __NOINLINE */
|
||||
/* RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module.
|
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
area of a module to a memory space in physical RAM. */
|
||||
#ifndef __RAM_FUNC
|
||||
#define __RAM_FUNC __attribute__((section("RAMCODE")))
|
||||
#endif /* __RAM_FUNC */
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__((section(".bss.noinit")))
|
||||
#endif /* __NO_INIT */
|
||||
#ifndef __NO_OPTIMIZE
|
||||
#define __NO_OPTIMIZE __attribute__((optnone))
|
||||
#endif /* __NO_OPTIMIZE */
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /*!< GNU Compiler */
|
||||
#ifndef __WEAKDEF
|
||||
#define __WEAKDEF __attribute__((weak))
|
||||
#endif /* __WEAKDEF */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN __attribute__((aligned (4)))
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#ifndef __NOINLINE
|
||||
#define __NOINLINE __attribute__((noinline))
|
||||
#endif /* __NOINLINE */
|
||||
#ifndef __RAM_FUNC
|
||||
#define __RAM_FUNC __attribute__((long_call, section(".ramfunc")))
|
||||
/* Usage: __RAM_FUNC void foo(void) */
|
||||
#endif /* __RAM_FUNC */
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__((section(".noinit")))
|
||||
#endif /* __NO_INIT */
|
||||
#ifndef __NO_OPTIMIZE
|
||||
#define __NO_OPTIMIZE __attribute__((optimize("O0")))
|
||||
#endif /* __NO_OPTIMIZE */
|
||||
#elif defined (__ICCARM__) /*!< IAR Compiler */
|
||||
#ifndef __WEAKDEF
|
||||
#define __WEAKDEF __weak
|
||||
#endif /* __WEAKDEF */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN _Pragma("data_alignment=4")
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#ifndef __NOINLINE
|
||||
#define __NOINLINE _Pragma("optimize = no_inline")
|
||||
#endif /* __NOINLINE */
|
||||
#ifndef __RAM_FUNC
|
||||
#define __RAM_FUNC __ramfunc
|
||||
#endif /* __RAM_FUNC */
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __no_init
|
||||
#endif /* __NO_INIT */
|
||||
#ifndef __NO_OPTIMIZE
|
||||
#define __NO_OPTIMIZE _Pragma("optimize=none")
|
||||
#endif /* __NO_OPTIMIZE */
|
||||
#elif defined (__CC_ARM) /*!< ARM Compiler */
|
||||
#ifndef __WEAKDEF
|
||||
#define __WEAKDEF __attribute__((weak))
|
||||
#endif /* __WEAKDEF */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#ifndef __NOINLINE
|
||||
#define __NOINLINE __attribute__((noinline))
|
||||
#endif /* __NOINLINE */
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__((section(".bss.noinit"), zero_init))
|
||||
#endif /* __NO_INIT */
|
||||
#ifndef __NO_OPTIMIZE
|
||||
#define __NO_OPTIMIZE
|
||||
#endif /* __NO_OPTIMIZE */
|
||||
/* RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module.
|
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
area of a module to a memory space in physical RAM. */
|
||||
#ifndef __RAM_FUNC
|
||||
#define __RAM_FUNC __attribute__((section("RAMCODE")))
|
||||
#endif /* __RAM_FUNC */
|
||||
/* Suppress warning message: extended constant initializer used */
|
||||
#pragma diag_suppress 1296
|
||||
#else
|
||||
#error "unsupported compiler!!"
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup Extend_Macros Extend Macros
|
||||
* @{
|
||||
*/
|
||||
/* Decimal to BCD */
|
||||
#define DEC2BCD(x) ((((x) / 10U) << 4U) + ((x) % 10U))
|
||||
|
||||
/* BCD to decimal */
|
||||
#define BCD2DEC(x) ((((x) >> 4U) * 10U) + ((x) & 0x0FU))
|
||||
|
||||
/* Returns the dimension of an array */
|
||||
#define ARRAY_SZ(x) ((sizeof(x)) / (sizeof((x)[0])))
|
||||
|
||||
/* Returns the minimum value out of two values */
|
||||
#define LL_MIN(x, y) ((x) < (y) ? (x) : (y))
|
||||
|
||||
/* Returns the maximum value out of two values */
|
||||
#define LL_MAX(x, y) ((x) > (y) ? (x) : (y))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup Check_Parameters_Validity Check Parameters Validity
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Check Functional State */
|
||||
#define IS_FUNCTIONAL_STATE(state) (((state) == DISABLE) || ((state) == ENABLE))
|
||||
|
||||
/**
|
||||
* @defgroup Check_Address_Align_Validity Check Address Align Validity
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADDR_ALIGN(addr, align) (0UL == (((uint32_t)(addr)) & (((uint32_t)(align)) - 1UL)))
|
||||
#define IS_ADDR_ALIGN_HALFWORD(addr) (0UL == (((uint32_t)(addr)) & 0x1UL))
|
||||
#define IS_ADDR_ALIGN_WORD(addr) (0UL == (((uint32_t)(addr)) & 0x3UL))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup Peripheral_Bit_Band Peripheral Bit Band
|
||||
* @{
|
||||
*/
|
||||
#define __PERIPH_BIT_BAND_BASE (0x42000000UL)
|
||||
#define __PERIPH_BASE (0x40000000UL)
|
||||
#define __REG_OFS(regAddr) ((regAddr) - __PERIPH_BASE)
|
||||
#define __BIT_BAND_ADDR(regAddr, pos) ((__REG_OFS(regAddr) << 5U) + ((uint32_t)(pos) << 2U) + __PERIPH_BIT_BAND_BASE)
|
||||
#define PERIPH_BIT_BAND(regAddr, pos) (*(__IO uint32_t *)__BIT_BAND_ADDR((regAddr), (pos)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup Generic_Error_Codes Generic Error Codes
|
||||
* @{
|
||||
*/
|
||||
#define LL_OK (0) /*!< No error */
|
||||
#define LL_ERR (-1) /*!< Non-specific error code */
|
||||
#define LL_ERR_UNINIT (-2) /*!< Module (or part of it) was not initialized properly */
|
||||
#define LL_ERR_INVD_PARAM (-3) /*!< Provided parameter is not valid */
|
||||
#define LL_ERR_INVD_MD (-4) /*!< Operation not allowed in current mode */
|
||||
#define LL_ERR_NOT_RDY (-5) /*!< A requested final state is not reached */
|
||||
#define LL_ERR_BUSY (-6) /*!< A conflicting or requested operation is still in progress */
|
||||
#define LL_ERR_ADDR_ALIGN (-7) /*!< Address alignment does not match */
|
||||
#define LL_ERR_TIMEOUT (-8) /*!< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) */
|
||||
#define LL_ERR_BUF_EMPTY (-9) /*!< Circular buffer can not be read because the buffer is empty */
|
||||
#define LL_ERR_BUF_FULL (-10) /*!< Circular buffer can not be written because the buffer is full */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup Chip_Module_Switch Chip Module Switch
|
||||
* @{
|
||||
*/
|
||||
#define DDL_ON (1U)
|
||||
#define DDL_OFF (0U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup Bit_Mask_Macros Bit Mask Macros
|
||||
* @{
|
||||
*/
|
||||
#define BIT_MASK_00 (1UL << 0U)
|
||||
#define BIT_MASK_01 (1UL << 1U)
|
||||
#define BIT_MASK_02 (1UL << 2U)
|
||||
#define BIT_MASK_03 (1UL << 3U)
|
||||
#define BIT_MASK_04 (1UL << 4U)
|
||||
#define BIT_MASK_05 (1UL << 5U)
|
||||
#define BIT_MASK_06 (1UL << 6U)
|
||||
#define BIT_MASK_07 (1UL << 7U)
|
||||
#define BIT_MASK_08 (1UL << 8U)
|
||||
#define BIT_MASK_09 (1UL << 9U)
|
||||
#define BIT_MASK_10 (1UL << 10U)
|
||||
#define BIT_MASK_11 (1UL << 11U)
|
||||
#define BIT_MASK_12 (1UL << 12U)
|
||||
#define BIT_MASK_13 (1UL << 13U)
|
||||
#define BIT_MASK_14 (1UL << 14U)
|
||||
#define BIT_MASK_15 (1UL << 15U)
|
||||
#define BIT_MASK_16 (1UL << 16U)
|
||||
#define BIT_MASK_17 (1UL << 17U)
|
||||
#define BIT_MASK_18 (1UL << 18U)
|
||||
#define BIT_MASK_19 (1UL << 19U)
|
||||
#define BIT_MASK_20 (1UL << 20U)
|
||||
#define BIT_MASK_21 (1UL << 21U)
|
||||
#define BIT_MASK_22 (1UL << 22U)
|
||||
#define BIT_MASK_23 (1UL << 23U)
|
||||
#define BIT_MASK_24 (1UL << 24U)
|
||||
#define BIT_MASK_25 (1UL << 25U)
|
||||
#define BIT_MASK_26 (1UL << 26U)
|
||||
#define BIT_MASK_27 (1UL << 27U)
|
||||
#define BIT_MASK_28 (1UL << 28U)
|
||||
#define BIT_MASK_29 (1UL << 29U)
|
||||
#define BIT_MASK_30 (1UL << 30U)
|
||||
#define BIT_MASK_31 (1UL << 31U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup Register_Macros Register Macros
|
||||
* @{
|
||||
*/
|
||||
#define RW_MEM8(addr) (*(volatile uint8_t *)(addr))
|
||||
#define RW_MEM16(addr) (*(volatile uint16_t *)(addr))
|
||||
#define RW_MEM32(addr) (*(volatile uint32_t *)(addr))
|
||||
|
||||
#define SET_REG_BIT(REG, BIT) ((REG) |= (BIT))
|
||||
#define SET_REG8_BIT(REG, BIT) ((REG) |= ((uint8_t)(BIT)))
|
||||
#define SET_REG16_BIT(REG, BIT) ((REG) |= ((uint16_t)(BIT)))
|
||||
#define SET_REG32_BIT(REG, BIT) ((REG) |= ((uint32_t)(BIT)))
|
||||
|
||||
#define CLR_REG_BIT(REG, BIT) ((REG) &= (~(BIT)))
|
||||
#define CLR_REG8_BIT(REG, BIT) ((REG) &= ((uint8_t)(~((uint8_t)(BIT)))))
|
||||
#define CLR_REG16_BIT(REG, BIT) ((REG) &= ((uint16_t)(~((uint16_t)(BIT)))))
|
||||
#define CLR_REG32_BIT(REG, BIT) ((REG) &= ((uint32_t)(~((uint32_t)(BIT)))))
|
||||
|
||||
#define READ_REG_BIT(REG, BIT) ((REG) & (BIT))
|
||||
#define READ_REG8_BIT(REG, BIT) ((REG) & ((uint8_t)(BIT)))
|
||||
#define READ_REG16_BIT(REG, BIT) ((REG) & ((uint16_t)(BIT)))
|
||||
#define READ_REG32_BIT(REG, BIT) ((REG) & ((uint32_t)(BIT)))
|
||||
|
||||
#define CLR_REG(REG) ((REG) = (0U))
|
||||
#define CLR_REG8(REG) ((REG) = ((uint8_t)(0U)))
|
||||
#define CLR_REG16(REG) ((REG) = ((uint16_t)(0U)))
|
||||
#define CLR_REG32(REG) ((REG) = ((uint32_t)(0UL)))
|
||||
|
||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||
#define WRITE_REG8(REG, VAL) ((REG) = ((uint8_t)(VAL)))
|
||||
#define WRITE_REG16(REG, VAL) ((REG) = ((uint16_t)(VAL)))
|
||||
#define WRITE_REG32(REG, VAL) ((REG) = ((uint32_t)(VAL)))
|
||||
|
||||
#define READ_REG(REG) (REG)
|
||||
#define READ_REG8(REG) (REG)
|
||||
#define READ_REG16(REG) (REG)
|
||||
#define READ_REG32(REG) (REG)
|
||||
|
||||
#define MODIFY_REG(REGS, CLRMASK, SETMASK) (WRITE_REG((REGS), (((READ_REG(REGS)) & (~(CLRMASK))) | ((SETMASK) & (CLRMASK)))))
|
||||
#define MODIFY_REG8(REGS, CLRMASK, SETMASK) (WRITE_REG8((REGS), (((READ_REG8((REGS))) & ((uint8_t)(~((uint8_t)(CLRMASK))))) | ((uint8_t)(SETMASK) & (uint8_t)(CLRMASK)))))
|
||||
#define MODIFY_REG16(REGS, CLRMASK, SETMASK) (WRITE_REG16((REGS), (((READ_REG16((REGS))) & ((uint16_t)(~((uint16_t)(CLRMASK))))) | ((uint16_t)(SETMASK) & (uint16_t)(CLRMASK)))))
|
||||
#define MODIFY_REG32(REGS, CLRMASK, SETMASK) (WRITE_REG32((REGS), (((READ_REG32((REGS))) & ((uint32_t)(~((uint32_t)(CLRMASK))))) | ((uint32_t)(SETMASK) & (uint32_t)(CLRMASK)))))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_DEF_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,541 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_dma.h
|
||||
* @brief This file contains all the functions prototypes of the DMA driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2023-06-30 CDT Add API DMA_SetDataWidth()
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_DMA_H__
|
||||
#define __HC32_LL_DMA_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_DMA_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup DMA_Global_Types DMA Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA basic configuration
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32IntEn; /*!< Specifies the DMA interrupt function.
|
||||
This parameter can be a value of @ref DMA_Int_Config */
|
||||
uint32_t u32SrcAddr; /*!< Specifies the DMA source address. */
|
||||
uint32_t u32DestAddr; /*!< Specifies the DMA destination address. */
|
||||
uint32_t u32DataWidth; /*!< Specifies the DMA transfer data width.
|
||||
This parameter can be a value of @ref DMA_DataWidth_Sel */
|
||||
uint32_t u32BlockSize; /*!< Specifies the DMA block size. */
|
||||
uint32_t u32TransCount; /*!< Specifies the DMA transfer count. */
|
||||
uint32_t u32SrcAddrInc; /*!< Specifies the source address increment mode.
|
||||
This parameter can be a value of @ref DMA_SrcAddr_Incremented_Mode */
|
||||
uint32_t u32DestAddrInc; /*!< Specifies the destination address increment mode.
|
||||
This parameter can be a value of @ref DMA_DesAddr_Incremented_Mode */
|
||||
} stc_dma_init_t;
|
||||
|
||||
/**
|
||||
* @brief DMA repeat mode configuration
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32Mode; /*!< Specifies the DMA source repeat function.
|
||||
This parameter can be a value of @ref DMA_Repeat_Config */
|
||||
uint32_t u32SrcCount; /*!< Specifies the DMA source repeat size. */
|
||||
uint32_t u32DestCount; /*!< Specifies the DMA destination repeat size. */
|
||||
} stc_dma_repeat_init_t;
|
||||
|
||||
/**
|
||||
* @brief DMA non-sequence mode configuration
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32Mode; /*!< Specifies the DMA source non-sequence function.
|
||||
This parameter can be a value of @ref DMA_NonSeq_Config */
|
||||
uint32_t u32SrcCount; /*!< Specifies the DMA source non-sequence function count. */
|
||||
uint32_t u32SrcOffset; /*!< Specifies the DMA source non-sequence function offset. */
|
||||
uint32_t u32DestCount; /*!< Specifies the DMA destination non-sequence function count. */
|
||||
uint32_t u32DestOffset; /*!< Specifies the DMA destination non-sequence function offset. */
|
||||
} stc_dma_nonseq_init_t;
|
||||
|
||||
/**
|
||||
* @brief DMA Link List Pointer (LLP) mode configuration
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32State; /*!< Specifies the DMA LLP function.
|
||||
This parameter can be a value of @ref DMA_Llp_En */
|
||||
uint32_t u32Mode; /*!< Specifies the DMA LLP auto or wait REQ.
|
||||
This parameter can be a value of @ref DMA_Llp_Mode */
|
||||
uint32_t u32Addr; /*!< Specifies the DMA list pointer address for LLP function. */
|
||||
} stc_dma_llp_init_t;
|
||||
|
||||
/**
|
||||
* @brief DMA re-config function configuration
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32CountMode; /*!< Specifies the DMA reconfig function count mode.
|
||||
This parameter can be a value of @ref DMA_Reconfig_Count_Sel */
|
||||
uint32_t u32DestAddrMode; /*!< Specifies the DMA reconfig function destination address mode.
|
||||
This parameter can be a value of @ref DMA_Reconfig_DestAddr_Sel */
|
||||
uint32_t u32SrcAddrMode; /*!< Specifies the DMA reconfig function source address mode.
|
||||
This parameter can be a value of @ref DMA_Reconfig_SrcAddr_Sel */
|
||||
} stc_dma_reconfig_init_t;
|
||||
|
||||
/**
|
||||
* @brief Dma LLP(linked list pointer) descriptor structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t SARx; /*!< LLP source address */
|
||||
uint32_t DARx; /*!< LLP destination address */
|
||||
uint32_t DTCTLx; /*!< LLP transfer count and block size */
|
||||
uint32_t RPTx; /*!< LLP source & destination repeat size */
|
||||
uint32_t SNSEQCTLx; /*!< LLP source non-seq count and offset */
|
||||
uint32_t DNSEQCTLx; /*!< LLP destination non-seq count and offset */
|
||||
uint32_t LLPx; /*!< LLP next list pointer */
|
||||
uint32_t CHCTLx; /*!< LLP channel control */
|
||||
} stc_dma_llp_descriptor_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup DMA_Global_Macros DMA Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_Channel_selection DMA Channel Position selection
|
||||
* @{
|
||||
*/
|
||||
#define DMA_CH0 (0x00U) /*!< DMA Channel 0 */
|
||||
#define DMA_CH1 (0x01U) /*!< DMA Channel 1 */
|
||||
#define DMA_CH2 (0x02U) /*!< DMA Channel 2 */
|
||||
#define DMA_CH3 (0x03U) /*!< DMA Channel 3 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_Mx_Channel_selection DMA Multiplex Channel selection
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MX_CH0 (0x01UL) /*!< DMA Channel 0 position */
|
||||
#define DMA_MX_CH1 (0x02UL) /*!< DMA Channel 1 position */
|
||||
#define DMA_MX_CH_ALL (DMA_CHEN_CHEN) /*!< DMA Channel mask position */
|
||||
#define DMA_MX_CH2 (0x04UL) /*!< DMA Channel 2 position */
|
||||
#define DMA_MX_CH3 (0x08UL) /*!< DMA Channel 3 position */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_Flag_Request_Err_Sel DMA request error flag selection
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FLAG_REQ_ERR_CH0 (DMA_INTSTAT0_REQERR_0) /*!< DMA request error flag CH.0 */
|
||||
#define DMA_FLAG_REQ_ERR_CH1 (DMA_INTSTAT0_REQERR_1) /*!< DMA request error flag CH.1 */
|
||||
#define DMA_FLAG_REQ_ERR_CH2 (DMA_INTSTAT0_REQERR_2) /*!< DMA request error flag CH.2 */
|
||||
#define DMA_FLAG_REQ_ERR_CH3 (DMA_INTSTAT0_REQERR_3) /*!< DMA request error flag CH.3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_Flag_Trans_Err_Sel DMA transfer error flag selection
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FLAG_TRANS_ERR_CH0 (DMA_INTSTAT0_TRNERR_0) /*!< DMA transfer error flag CH.0 */
|
||||
#define DMA_FLAG_TRANS_ERR_CH1 (DMA_INTSTAT0_TRNERR_1) /*!< DMA transfer error flag CH.1 */
|
||||
#define DMA_FLAG_TRANS_ERR_CH2 (DMA_INTSTAT0_TRNERR_2) /*!< DMA transfer error flag CH.2 */
|
||||
#define DMA_FLAG_TRANS_ERR_CH3 (DMA_INTSTAT0_TRNERR_3) /*!< DMA transfer error flag CH.3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_Flag_Btc_Sel DMA block transfer completed flag selection
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FLAG_BTC_CH0 (DMA_INTSTAT1_BTC_0) /*!< DMA block transfer completed flag CH.0 */
|
||||
#define DMA_FLAG_BTC_CH1 (DMA_INTSTAT1_BTC_1) /*!< DMA block transfer completed flag CH.1 */
|
||||
#define DMA_FLAG_BTC_CH2 (DMA_INTSTAT1_BTC_2) /*!< DMA block transfer completed flag CH.2 */
|
||||
#define DMA_FLAG_BTC_CH3 (DMA_INTSTAT1_BTC_3) /*!< DMA block transfer completed flag CH.3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_Flag_Tc_Sel DMA transfer completed flag selection
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FLAG_TC_CH0 (DMA_INTSTAT1_TC_0) /*!< DMA transfer completed flag CH.0 */
|
||||
#define DMA_FLAG_TC_CH1 (DMA_INTSTAT1_TC_1) /*!< DMA transfer completed flag CH.1 */
|
||||
#define DMA_FLAG_TC_CH2 (DMA_INTSTAT1_TC_2) /*!< DMA transfer completed flag CH.2 */
|
||||
#define DMA_FLAG_TC_CH3 (DMA_INTSTAT1_TC_3) /*!< DMA transfer completed flag CH.3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_Int_Request_Err_Sel DMA request error interrupt selection
|
||||
* @{
|
||||
*/
|
||||
#define DMA_INT_REQ_ERR_CH0 (DMA_INTMASK0_MSKREQERR_0) /*!< DMA request error interrupt CH.0 */
|
||||
#define DMA_INT_REQ_ERR_CH1 (DMA_INTMASK0_MSKREQERR_1) /*!< DMA request error interrupt CH.1 */
|
||||
#define DMA_INT_REQ_ERR_CH2 (DMA_INTMASK0_MSKREQERR_2) /*!< DMA request error interrupt CH.2 */
|
||||
#define DMA_INT_REQ_ERR_CH3 (DMA_INTMASK0_MSKREQERR_3) /*!< DMA request error interrupt CH.3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_Int_Trans_Err_Sel DMA transfer error interrupt selection
|
||||
* @{
|
||||
*/
|
||||
#define DMA_INT_TRANS_ERR_CH0 (DMA_INTMASK0_MSKTRNERR_0) /*!< DMA transfer error interrupt CH.0 */
|
||||
#define DMA_INT_TRANS_ERR_CH1 (DMA_INTMASK0_MSKTRNERR_1) /*!< DMA transfer error interrupt CH.1 */
|
||||
#define DMA_INT_TRANS_ERR_CH2 (DMA_INTMASK0_MSKTRNERR_2) /*!< DMA transfer error interrupt CH.2 */
|
||||
#define DMA_INT_TRANS_ERR_CH3 (DMA_INTMASK0_MSKTRNERR_3) /*!< DMA transfer error interrupt CH.3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_Int_Btc_Sel DMA block transfer completed interrupt selection
|
||||
* @{
|
||||
*/
|
||||
#define DMA_INT_BTC_CH0 (DMA_INTMASK1_MSKBTC_0) /*!< DMA block transfer completed interrupt CH.0 */
|
||||
#define DMA_INT_BTC_CH1 (DMA_INTMASK1_MSKBTC_1) /*!< DMA block transfer completed interrupt CH.1 */
|
||||
#define DMA_INT_BTC_CH2 (DMA_INTMASK1_MSKBTC_2) /*!< DMA block transfer completed interrupt CH.2 */
|
||||
#define DMA_INT_BTC_CH3 (DMA_INTMASK1_MSKBTC_3) /*!< DMA block transfer completed interrupt CH.3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_Int_Tc_Sel DMA transfer completed interrupt selection
|
||||
* @{
|
||||
*/
|
||||
#define DMA_INT_TC_CH0 (DMA_INTMASK1_MSKTC_0) /*!< DMA transfer completed interrupt CH.0 */
|
||||
#define DMA_INT_TC_CH1 (DMA_INTMASK1_MSKTC_1) /*!< DMA transfer completed interrupt CH.1 */
|
||||
#define DMA_INT_TC_CH2 (DMA_INTMASK1_MSKTC_2) /*!< DMA transfer completed interrupt CH.2 */
|
||||
#define DMA_INT_TC_CH3 (DMA_INTMASK1_MSKTC_3) /*!< DMA transfer completed interrupt CH.3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_FlagMsk_Sel DMA flag mask selection
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FLAG_ERR_MASK (DMA_INTSTAT0_TRNERR | DMA_INTSTAT0_REQERR) /*!< DMA error flag mask */
|
||||
#define DMA_FLAG_TRANS_MASK (DMA_INTSTAT1_TC | DMA_INTSTAT1_BTC) /*!< DMA transfer flag mask */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_IntMsk_Sel DMA interrupt mask selection
|
||||
* @{
|
||||
*/
|
||||
#define DMA_INT_ERR_MASK (DMA_INTMASK0_MSKREQERR | DMA_INTMASK0_MSKTRNERR) /*!< DMA error interrupt mask */
|
||||
#define DMA_INT_TRANS_MASK (DMA_INTMASK1_MSKTC | DMA_INTMASK1_MSKBTC) /*!< DMA transfer interrupt mask */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_Req_Status_Sel DMA request status
|
||||
* @{
|
||||
*/
|
||||
#define DMA_STAT_REQ_RECONFIG (DMA_REQSTAT_RCFGREQ) /*!< DMA request from reconfig */
|
||||
#define DMA_STAT_REQ_CH0 (DMA_REQSTAT_CHREQ_0) /*!< DMA request from CH.0 */
|
||||
#define DMA_STAT_REQ_CH1 (DMA_REQSTAT_CHREQ_1) /*!< DMA request from CH.1 */
|
||||
#define DMA_STAT_REQ_CH2 (DMA_REQSTAT_CHREQ_2) /*!< DMA request from CH.2 */
|
||||
#define DMA_STAT_REQ_CH3 (DMA_REQSTAT_CHREQ_3) /*!< DMA request from CH.3 */
|
||||
|
||||
#define DMA_STAT_REQ_MASK (DMA_REQSTAT_CHREQ | DMA_REQSTAT_RCFGREQ) /*!< DMA request mask */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_Trans_Status_Sel DMA transfer status
|
||||
* @{
|
||||
*/
|
||||
#define DMA_STAT_TRANS_CH0 (DMA_CHSTAT_CHACT_0) /*!< DMA transfer status of CH.0 */
|
||||
#define DMA_STAT_TRANS_CH1 (DMA_CHSTAT_CHACT_1) /*!< DMA transfer status of CH.1 */
|
||||
#define DMA_STAT_TRANS_CH2 (DMA_CHSTAT_CHACT_2) /*!< DMA transfer status of CH.2 */
|
||||
#define DMA_STAT_TRANS_CH3 (DMA_CHSTAT_CHACT_3) /*!< DMA transfer status of CH.3 */
|
||||
#define DMA_STAT_TRANS_DMA (DMA_CHSTAT_DMAACT) /*!< DMA transfer status of the DMA */
|
||||
#define DMA_STAT_TRANS_RECONFIG (DMA_CHSTAT_RCFGACT) /*!< DMA reconfig status */
|
||||
|
||||
#define DMA_STAT_TRANS_MASK (DMA_CHSTAT_DMAACT | DMA_CHSTAT_CHACT | DMA_CHSTAT_RCFGACT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_DataWidth_Sel DMA transfer data width
|
||||
* @{
|
||||
*/
|
||||
#define DMA_DATAWIDTH_8BIT (0x00000000UL) /*!< DMA transfer data width 8bit */
|
||||
#define DMA_DATAWIDTH_16BIT (DMA_CHCTL_HSIZE_0) /*!< DMA transfer data width 16bit */
|
||||
#define DMA_DATAWIDTH_32BIT (DMA_CHCTL_HSIZE_1) /*!< DMA transfer data width 32bit */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_Llp_En DMA LLP(linked list pinter) enable or disable
|
||||
* @{
|
||||
*/
|
||||
#define DMA_LLP_DISABLE (0x00000000UL) /*!< DMA linked list pinter disable */
|
||||
#define DMA_LLP_ENABLE (DMA_CHCTL_LLPEN) /*!< DMA linked list pinter enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_Llp_Mode DMA linked list pinter mode while transferring complete
|
||||
* @{
|
||||
*/
|
||||
#define DMA_LLP_WAIT (0x00000000UL) /*!< DMA Llp wait next request while transferring complete */
|
||||
#define DMA_LLP_RUN (DMA_CHCTL_LLPRUN) /*!< DMA Llp run right now while transferring complete */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_SrcAddr_Incremented_Mode DMA source address increment mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_SRC_ADDR_FIX (0x00000000UL) /*!< DMA source address fix */
|
||||
#define DMA_SRC_ADDR_INC (DMA_CHCTL_SINC_0) /*!< DMA source address increment */
|
||||
#define DMA_SRC_ADDR_DEC (DMA_CHCTL_SINC_1) /*!< DMA source address decrement */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_DesAddr_Incremented_Mode DMA destination address increment mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_DEST_ADDR_FIX (0x00000000UL) /*!< DMA destination address fix */
|
||||
#define DMA_DEST_ADDR_INC (DMA_CHCTL_DINC_0) /*!< DMA destination address increment */
|
||||
#define DMA_DEST_ADDR_DEC (DMA_CHCTL_DINC_1) /*!< DMA destination address decrement */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_Int_Config DMA interrupt function config
|
||||
* @{
|
||||
*/
|
||||
#define DMA_INT_ENABLE (DMA_CHCTL_IE) /*!< DMA interrupt enable */
|
||||
#define DMA_INT_DISABLE (0x00000000UL) /*!< DMA interrupt disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_Repeat_Config DMA repeat mode function config
|
||||
* @{
|
||||
*/
|
||||
#define DMA_RPT_NONE (0x00000000UL) /*!< DMA repeat disable */
|
||||
#define DMA_RPT_SRC (DMA_CHCTL_SRPTEN) /*!< DMA source repeat enable */
|
||||
#define DMA_RPT_DEST (DMA_CHCTL_DRPTEN) /*!< DMA destination repeat enable */
|
||||
#define DMA_RPT_BOTH (DMA_CHCTL_SRPTEN | DMA_CHCTL_DRPTEN) /*!< DMA source & destination repeat enable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_NonSeq_Config DMA non-sequence mode function config
|
||||
* @{
|
||||
*/
|
||||
#define DMA_NON_SEQ_NONE (0x00000000UL) /*!< DMA non-sequence disable */
|
||||
#define DMA_NON_SEQ_SRC (DMA_CHCTL_SNSEQEN) /*!< DMA source non-sequence enable */
|
||||
#define DMA_NON_SEQ_DEST (DMA_CHCTL_DNSEQEN) /*!< DMA destination non-sequence enable */
|
||||
#define DMA_NON_SEQ_BOTH (DMA_CHCTL_SNSEQEN | DMA_CHCTL_DNSEQEN) /*!< DMA source & destination non-sequence enable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_Reconfig_Count_Sel DMA reconfig count mode selection
|
||||
* @{
|
||||
*/
|
||||
#define DMA_RC_CNT_KEEP (0x00000000UL) /*!< Keep the original counting method */
|
||||
#define DMA_RC_CNT_SRC (DMA_RCFGCTL_CNTMD_0) /*!< Use source address counting method */
|
||||
#define DMA_RC_CNT_DEST (DMA_RCFGCTL_CNTMD_1) /*!< Use destination address counting method */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_Reconfig_DestAddr_Sel DMA reconfig destination address mode selection
|
||||
* @{
|
||||
*/
|
||||
#define DMA_RC_DEST_ADDR_KEEP (0x00000000UL) /*!< Destination address Keep the original mode */
|
||||
#define DMA_RC_DEST_ADDR_NS (DMA_RCFGCTL_DARMD_0) /*!< Destination address non-sequence */
|
||||
#define DMA_RC_DEST_ADDR_RPT (DMA_RCFGCTL_DARMD_1) /*!< Destination address repeat */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DMA_Reconfig_SrcAddr_Sel DMA reconfig source address mode selection
|
||||
* @{
|
||||
*/
|
||||
#define DMA_RC_SRC_ADDR_KEEP (0x00000000UL) /*!< Source address Keep the original mode */
|
||||
#define DMA_RC_SRC_ADDR_NS (DMA_RCFGCTL_SARMD_0) /*!< Source address non-sequence */
|
||||
#define DMA_RC_SRC_ADDR_RPT (DMA_RCFGCTL_SARMD_1) /*!< Source address repeat */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup DMA_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
void DMA_Cmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState);
|
||||
|
||||
void DMA_ErrIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32ErrInt, en_functional_state_t enNewState);
|
||||
en_flag_status_t DMA_GetErrStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag);
|
||||
void DMA_ClearErrStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag);
|
||||
|
||||
void DMA_TransCompleteIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32TransCompleteInt, en_functional_state_t enNewState);
|
||||
en_flag_status_t DMA_GetTransCompleteStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag);
|
||||
void DMA_ClearTransCompleteStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag);
|
||||
|
||||
int32_t DMA_ChCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState);
|
||||
|
||||
en_flag_status_t DMA_GetRequestStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status);
|
||||
en_flag_status_t DMA_GetTransStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status);
|
||||
|
||||
int32_t DMA_SetSrcAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr);
|
||||
int32_t DMA_SetDestAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr);
|
||||
int32_t DMA_SetTransCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Count);
|
||||
int32_t DMA_SetBlockSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size);
|
||||
int32_t DMA_SetDataWidth(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32DataWidth);
|
||||
|
||||
int32_t DMA_SetSrcRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size);
|
||||
int32_t DMA_SetDestRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size);
|
||||
int32_t DMA_SetNonSeqSrcCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count);
|
||||
int32_t DMA_SetNonSeqDestCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count);
|
||||
int32_t DMA_SetNonSeqSrcOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset);
|
||||
int32_t DMA_SetNonSeqDestOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset);
|
||||
|
||||
void DMA_SetLlpAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr);
|
||||
|
||||
int32_t DMA_StructInit(stc_dma_init_t *pstcDmaInit);
|
||||
int32_t DMA_Init(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_init_t *pstcDmaInit);
|
||||
void DMA_DeInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
|
||||
|
||||
int32_t DMA_RepeatStructInit(stc_dma_repeat_init_t *pstcDmaRepeatInit);
|
||||
int32_t DMA_RepeatInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_repeat_init_t *pstcDmaRepeatInit);
|
||||
|
||||
int32_t DMA_NonSeqStructInit(stc_dma_nonseq_init_t *pstcDmaNonSeqInit);
|
||||
int32_t DMA_NonSeqInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_nonseq_init_t *pstcDmaNonSeqInit);
|
||||
|
||||
int32_t DMA_LlpStructInit(stc_dma_llp_init_t *pstcDmaLlpInit);
|
||||
int32_t DMA_LlpInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_llp_init_t *pstcDmaLlpInit);
|
||||
|
||||
void DMA_LlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState);
|
||||
|
||||
int32_t DMA_ReconfigStructInit(stc_dma_reconfig_init_t *pstcDmaRCInit);
|
||||
int32_t DMA_ReconfigInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_reconfig_init_t *pstcDmaRCInit);
|
||||
void DMA_ReconfigCmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState);
|
||||
void DMA_ReconfigLlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState);
|
||||
|
||||
uint32_t DMA_GetSrcAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
|
||||
uint32_t DMA_GetDestAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
|
||||
uint32_t DMA_GetTransCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
|
||||
uint32_t DMA_GetBlockSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
|
||||
uint32_t DMA_GetSrcRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
|
||||
uint32_t DMA_GetDestRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
|
||||
uint32_t DMA_GetNonSeqSrcCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
|
||||
uint32_t DMA_GetNonSeqDestCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
|
||||
uint32_t DMA_GetNonSeqSrcOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
|
||||
uint32_t DMA_GetNonSeqDestOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_DMA_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_DMA_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,487 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_efm.h
|
||||
* @brief This file contains all the functions prototypes of the EFM driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2022-10-31 CDT Add Flash protect level define
|
||||
2023-01-15 CDT Code refine
|
||||
2023-09-30 CDT Add FLASH security addr define
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_EFM_H__
|
||||
#define __HC32_LL_EFM_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_EFM
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_EFM_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup EFM_Global_Types EFM Global Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief EFM unique ID definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32UniqueID0; /*!< unique ID 0. */
|
||||
uint32_t u32UniqueID1; /*!< unique ID 1. */
|
||||
uint32_t u32UniqueID2; /*!< unique ID 2. */
|
||||
} stc_efm_unique_id_t;
|
||||
|
||||
typedef struct {
|
||||
uint32_t u32State;
|
||||
uint32_t u32Addr;
|
||||
uint32_t u32Size;
|
||||
} stc_efm_remap_init_t;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup EFM_Global_Macros EFM Global Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @defgroup EFM_Address EFM Address Area
|
||||
* @{
|
||||
*/
|
||||
#define EFM_START_ADDR (0x00000000UL) /*!< Flash start address */
|
||||
|
||||
#define EFM_END_ADDR (0x0007FFFFUL) /*!< Flash end address */
|
||||
#define EFM_OTP_START_ADDR (0x03000C00UL) /*!< OTP start address */
|
||||
#define EFM_OTP_END_ADDR (0x03000FFBUL) /*!< OTP end address */
|
||||
#define EFM_OTP_LOCK_ADDR_START (0x03000FC0UL) /*!< OTP lock start address */
|
||||
#define EFM_OTP_LOCK_ADDR_END (0x03000FFCUL) /*!< OTP lock end address */
|
||||
#define EFM_SECURITY_START_ADDR (0x0317FFE0UL) /*!< Flash security start address */
|
||||
#define EFM_SECURITY_END_ADDR (0x0317FFFFUL) /*!< Flash security end address */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EFM_Chip_Sel EFM Chip Selection
|
||||
* @{
|
||||
*/
|
||||
#define EFM_CHIP_ALL (EFM_FSTP_FSTP)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EFM_Bus_Status EFM Bus Status
|
||||
* @{
|
||||
*/
|
||||
#define EFM_BUS_HOLD (0x0UL) /*!< Bus busy while flash program or erase */
|
||||
#define EFM_BUS_RELEASE (0x1UL) /*!< Bus release while flash program or erase */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EFM_Wait_Cycle EFM Wait Cycle
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EFM_WAIT_CYCLE0 (0U << EFM_FRMC_FLWT_POS) /*!< Don't insert read wait cycle */
|
||||
#define EFM_WAIT_CYCLE1 (1U << EFM_FRMC_FLWT_POS) /*!< Insert 1 read wait cycle */
|
||||
|
||||
#define EFM_WAIT_CYCLE2 (2U << EFM_FRMC_FLWT_POS) /*!< Insert 2 read wait cycles */
|
||||
#define EFM_WAIT_CYCLE3 (3U << EFM_FRMC_FLWT_POS) /*!< Insert 3 read wait cycles */
|
||||
#define EFM_WAIT_CYCLE4 (4U << EFM_FRMC_FLWT_POS) /*!< Insert 4 read wait cycles */
|
||||
#define EFM_WAIT_CYCLE5 (5U << EFM_FRMC_FLWT_POS) /*!< Insert 5 read wait cycles */
|
||||
#define EFM_WAIT_CYCLE6 (6U << EFM_FRMC_FLWT_POS) /*!< Insert 6 read wait cycles */
|
||||
#define EFM_WAIT_CYCLE7 (7U << EFM_FRMC_FLWT_POS) /*!< Insert 7 read wait cycles */
|
||||
#define EFM_WAIT_CYCLE8 (8U << EFM_FRMC_FLWT_POS) /*!< Insert 8 read wait cycles */
|
||||
#define EFM_WAIT_CYCLE9 (9U << EFM_FRMC_FLWT_POS) /*!< Insert 9 read wait cycles */
|
||||
#define EFM_WAIT_CYCLE10 (10U << EFM_FRMC_FLWT_POS) /*!< Insert 10 read wait cycles */
|
||||
#define EFM_WAIT_CYCLE11 (11U << EFM_FRMC_FLWT_POS) /*!< Insert 11 read wait cycles */
|
||||
#define EFM_WAIT_CYCLE12 (12U << EFM_FRMC_FLWT_POS) /*!< Insert 12 read wait cycles */
|
||||
#define EFM_WAIT_CYCLE13 (13U << EFM_FRMC_FLWT_POS) /*!< Insert 13 read wait cycles */
|
||||
#define EFM_WAIT_CYCLE14 (14U << EFM_FRMC_FLWT_POS) /*!< Insert 14 read wait cycles */
|
||||
#define EFM_WAIT_CYCLE15 (15U << EFM_FRMC_FLWT_POS) /*!< Insert 15 read wait cycles */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EFM_Swap_Address EFM Swap Address
|
||||
* @{
|
||||
*/
|
||||
#define EFM_SWAP_ADDR (0x0007FFDCUL)
|
||||
#define EFM_SWAP_DATA (0xFFFF4321UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EFM_OperateMode_Sel EFM Operate Mode Selection
|
||||
* @{
|
||||
*/
|
||||
#define EFM_MD_READONLY (0x0UL << EFM_FWMC_PEMOD_POS) /*!< Read only mode */
|
||||
#define EFM_MD_PGM_SINGLE (0x1UL << EFM_FWMC_PEMOD_POS) /*!< Program single mode */
|
||||
#define EFM_MD_PGM_READBACK (0x2UL << EFM_FWMC_PEMOD_POS) /*!< Program and read back mode */
|
||||
#define EFM_MD_PGM_SEQ (0x3UL << EFM_FWMC_PEMOD_POS) /*!< Program sequence mode */
|
||||
#define EFM_MD_ERASE_SECTOR (0x4UL << EFM_FWMC_PEMOD_POS) /*!< Sector erase mode */
|
||||
|
||||
#define EFM_MD_ERASE_ALL_CHIP (0x5UL << EFM_FWMC_PEMOD_POS) /*!< Chip erase mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EFM_Flag_Sel EFM Flag Selection
|
||||
* @{
|
||||
*/
|
||||
#define EFM_FLAG_PEWERR (EFM_FSR_PEWERR) /*!< EFM Programming/erase error flag. */
|
||||
#define EFM_FLAG_PGMISMTCH (EFM_FSR_PGMISMTCH) /*!< EFM Programming missing match error flag */
|
||||
#define EFM_FLAG_OPTEND (EFM_FSR_OPTEND) /*!< EFM End of operation flag. */
|
||||
#define EFM_FLAG_COLERR (EFM_FSR_COLERR) /*!< EFM Read collide error flag. */
|
||||
#define EFM_FLAG_PEPRTERR (EFM_FSR_PEPRTERR) /*!< EFM write protect address error flag */
|
||||
#define EFM_FLAG_RDY (EFM_FSR_RDY) /*!< EFM ready flag. */
|
||||
#define EFM_FLAG_PGSZERR (EFM_FSR_PGSZERR) /*!< EFM Programming/erase protect area error flag. */
|
||||
|
||||
#define EFM_FLAG_ALL (EFM_FLAG_PEWERR | EFM_FLAG_PGMISMTCH | EFM_FLAG_OPTEND | EFM_FLAG_PEPRTERR | \
|
||||
EFM_FLAG_COLERR | EFM_FLAG_PGSZERR | EFM_FLAG_RDY)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EFM_Interrupt_Sel EFM Interrupt Selection
|
||||
* @{
|
||||
*/
|
||||
#define EFM_INT_PEERR (EFM_FITE_PEERRITE) /*!< Program/erase error Interrupt source */
|
||||
#define EFM_INT_OPTEND (EFM_FITE_OPTENDITE) /*!< End of EFM operation Interrupt source */
|
||||
#define EFM_INT_COLERR (EFM_FITE_COLERRITE) /*!< Read collide error Interrupt source */
|
||||
|
||||
#define EFM_INT_ALL (EFM_FITE_PEERRITE | EFM_FITE_OPTENDITE | EFM_FITE_COLERRITE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EFM_Keys EFM Keys
|
||||
* @{
|
||||
*/
|
||||
#define EFM_REG_UNLOCK_KEY1 (0x0123UL)
|
||||
#define EFM_REG_UNLOCK_KEY2 (0x3210UL)
|
||||
#define EFM_REG_LOCK_KEY (0x0000UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EFM_Sector_Size EFM Sector Size
|
||||
* @{
|
||||
*/
|
||||
#define SECTOR_SIZE (0x2000UL)
|
||||
#define EFM_SECTOR_SIZE (0x2000UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EFM_Sector_Address EFM Sector Address
|
||||
* @{
|
||||
*/
|
||||
#define EFM_SECTOR_ADDR(x) (uint32_t)(SECTOR_SIZE * (x))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EFM_OTP_Base_Address EFM Otp Base Address
|
||||
* @{
|
||||
*/
|
||||
#define EFM_OTP_BASE1_ADDR (0x03000C00UL)
|
||||
#define EFM_OTP_BASE1_SIZE (0x40UL)
|
||||
#define EFM_OTP_BASE1_OFFSET (0UL)
|
||||
#define EFM_OTP_LOCK_ADDR (0x03000FC0UL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EFM_OTP_Address EFM Otp Address
|
||||
* @{
|
||||
*/
|
||||
#define EFM_OTP_BLOCK0 (EFM_OTP_BASE1_ADDR + ((0UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
|
||||
#define EFM_OTP_BLOCK1 (EFM_OTP_BASE1_ADDR + ((1UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
|
||||
#define EFM_OTP_BLOCK2 (EFM_OTP_BASE1_ADDR + ((2UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
|
||||
#define EFM_OTP_BLOCK3 (EFM_OTP_BASE1_ADDR + ((3UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
|
||||
#define EFM_OTP_BLOCK4 (EFM_OTP_BASE1_ADDR + ((4UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
|
||||
#define EFM_OTP_BLOCK5 (EFM_OTP_BASE1_ADDR + ((5UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
|
||||
#define EFM_OTP_BLOCK6 (EFM_OTP_BASE1_ADDR + ((6UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
|
||||
#define EFM_OTP_BLOCK7 (EFM_OTP_BASE1_ADDR + ((7UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
|
||||
#define EFM_OTP_BLOCK8 (EFM_OTP_BASE1_ADDR + ((8UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
|
||||
#define EFM_OTP_BLOCK9 (EFM_OTP_BASE1_ADDR + ((9UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
|
||||
#define EFM_OTP_BLOCK10 (EFM_OTP_BASE1_ADDR + ((10UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
|
||||
#define EFM_OTP_BLOCK11 (EFM_OTP_BASE1_ADDR + ((11UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
|
||||
#define EFM_OTP_BLOCK12 (EFM_OTP_BASE1_ADDR + ((12UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
|
||||
#define EFM_OTP_BLOCK13 (EFM_OTP_BASE1_ADDR + ((13UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
|
||||
#define EFM_OTP_BLOCK14 (EFM_OTP_BASE1_ADDR + ((14UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EFM_OTP_Lock_Address EFM Otp Lock_address
|
||||
* @note x at range of 0~14
|
||||
* @{
|
||||
*/
|
||||
#define EFM_OTP_BLOCK_LOCKADDR(x) (EFM_OTP_LOCK_ADDR + 0x04UL * (x)) /*!< OTP block x lock address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define EFM_REMAP_REG_LOCK_KEY (0x0000UL)
|
||||
#define EFM_REMAP_REG_UNLOCK_KEY1 (0x0123UL)
|
||||
#define EFM_REMAP_REG_UNLOCK_KEY2 (0x3210UL)
|
||||
|
||||
/**
|
||||
* @defgroup EFM_Remap_State EFM remap function state
|
||||
* @{
|
||||
*/
|
||||
#define EFM_REMAP_OFF (0UL)
|
||||
#define EFM_REMAP_ON (EFM_MMF_REMCR_EN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EFM_Remap_Size EFM remap size definition
|
||||
* @note refer to chip user manual for details size spec.
|
||||
* @{
|
||||
*/
|
||||
#define EFM_REMAP_4K (12UL)
|
||||
#define EFM_REMAP_8K (13UL)
|
||||
#define EFM_REMAP_16K (14UL)
|
||||
#define EFM_REMAP_32K (15UL)
|
||||
#define EFM_REMAP_64K (16UL)
|
||||
#define EFM_REMAP_128K (17UL)
|
||||
#define EFM_REMAP_256K (18UL)
|
||||
#define EFM_REMAP_512K (19UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EFM_Remap_Index EFM remap index
|
||||
* @{
|
||||
*/
|
||||
#define EFM_REMAP_IDX0 (0U)
|
||||
#define EFM_REMAP_IDX1 (1U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EFM_Remap_BaseAddr EFM remap base address
|
||||
* @{
|
||||
*/
|
||||
#define EFM_REMAP_BASE_ADDR0 (0x2000000UL)
|
||||
#define EFM_REMAP_BASE_ADDR1 (0x2080000UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EFM_Remap_Region EFM remap ROM/RAM region
|
||||
* @{
|
||||
*/
|
||||
#define EFM_REMAP_ROM_END_ADDR EFM_END_ADDR
|
||||
|
||||
#define EFM_REMAP_RAM_START_ADDR (0x1FFF8000UL)
|
||||
#define EFM_REMAP_RAM_END_ADDR (0x1FFFFFFFUL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EFM_Protect_Level EFM protect level
|
||||
* @{
|
||||
*/
|
||||
#define EFM_PROTECT_LEVEL1 (1U)
|
||||
#define EFM_PROTECT_LEVEL2 (2U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EFM_MCU_Status EFM protect level
|
||||
* @{
|
||||
*/
|
||||
#define EFM_MCU_PROTECT1_FREE (0U)
|
||||
#define EFM_MCU_PROTECT1_LOCK (1U)
|
||||
#define EFM_MCU_PROTECT1_UNLOCK (2U)
|
||||
#define EFM_MCU_PROTECT2_LOCK (4U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup EFM_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief EFM Protect Unlock.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
__STATIC_INLINE void EFM_REG_Unlock(void)
|
||||
{
|
||||
WRITE_REG32(CM_EFM->FAPRT, EFM_REG_UNLOCK_KEY1);
|
||||
WRITE_REG32(CM_EFM->FAPRT, EFM_REG_UNLOCK_KEY2);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EFM Protect Lock.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void EFM_REG_Lock(void)
|
||||
{
|
||||
WRITE_REG32(CM_EFM->FAPRT, EFM_REG_LOCK_KEY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EFM remap Unlock.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void EFM_REMAP_Unlock(void)
|
||||
{
|
||||
WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_UNLOCK_KEY1);
|
||||
WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_UNLOCK_KEY2);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EFM remap Lock.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void EFM_REMAP_Lock(void)
|
||||
{
|
||||
WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_LOCK_KEY);
|
||||
}
|
||||
|
||||
void EFM_Cmd(uint32_t u32Flash, en_functional_state_t enNewState);
|
||||
void EFM_FWMC_Cmd(en_functional_state_t enNewState);
|
||||
void EFM_SetBusStatus(uint32_t u32Status);
|
||||
void EFM_IntCmd(uint32_t u32EfmInt, en_functional_state_t enNewState);
|
||||
void EFM_ClearStatus(uint32_t u32Flag);
|
||||
int32_t EFM_SetWaitCycle(uint32_t u32WaitCycle);
|
||||
int32_t EFM_SetOperateMode(uint32_t u32Mode);
|
||||
int32_t EFM_ReadByte(uint32_t u32Addr, uint8_t *pu8ReadBuf, uint32_t u32ByteLen);
|
||||
int32_t EFM_Program(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len);
|
||||
int32_t EFM_ProgramWord(uint32_t u32Addr, uint32_t u32Data);
|
||||
int32_t EFM_ProgramWordReadBack(uint32_t u32Addr, uint32_t u32Data);
|
||||
int32_t EFM_SequenceProgram(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len);
|
||||
int32_t EFM_SectorErase(uint32_t u32Addr);
|
||||
int32_t EFM_ChipErase(uint8_t u8Chip);
|
||||
|
||||
en_flag_status_t EFM_GetAnyStatus(uint32_t u32Flag);
|
||||
en_flag_status_t EFM_GetStatus(uint32_t u32Flag);
|
||||
void EFM_GetUID(stc_efm_unique_id_t *pstcUID);
|
||||
|
||||
void EFM_DataCacheResetCmd(en_functional_state_t enNewState);
|
||||
void EFM_CacheCmd(en_functional_state_t enNewState);
|
||||
|
||||
void EFM_LowVoltageReadCmd(en_functional_state_t enNewState);
|
||||
int32_t EFM_SwapCmd(en_functional_state_t enNewState);
|
||||
en_flag_status_t EFM_GetSwapStatus(void);
|
||||
int32_t EFM_OTP_Lock(uint32_t u32Addr);
|
||||
|
||||
int32_t EFM_REMAP_StructInit(stc_efm_remap_init_t *pstcEfmRemapInit);
|
||||
int32_t EFM_REMAP_Init(uint8_t u8RemapIdx, stc_efm_remap_init_t *pstcEfmRemapInit);
|
||||
void EFM_REMAP_DeInit(void);
|
||||
void EFM_REMAP_Cmd(uint8_t u8RemapIdx, en_functional_state_t enNewState);
|
||||
void EFM_REMAP_SetAddr(uint8_t u8RemapIdx, uint32_t u32Addr);
|
||||
void EFM_REMAP_SetSize(uint8_t u8RemapIdx, uint32_t u32Size);
|
||||
|
||||
void EFM_LowVoltageCmd(en_functional_state_t enNewState);
|
||||
|
||||
void EFM_SetWindowProtectAddr(uint32_t u32StartAddr, uint32_t u32EndAddr);
|
||||
|
||||
void EFM_Protect_Enable(uint8_t u8Level);
|
||||
int32_t EFM_WriteSecurityCode(uint8_t *pu8Buf, uint32_t u32Len);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_EFM_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_EFM_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,394 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_emb.h
|
||||
* @brief This file contains all the functions prototypes of the EMB
|
||||
* (Emergency Brake) driver library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2022-06-30 CDT Modify structure comments:stc_emb_monitor_tmr_pwm_t
|
||||
2023-09-30 CDT Update EMB_CTL_CMPEN0~2 to EMB_CTL_CMPEN1~3
|
||||
Update EMB_INTEN_PORTINTEN to EMB_INTEN_PORTININTEN
|
||||
Update EMB_INTEN_PWMINTEN to EMB_INTEN_PWMSINTEN
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_EMB_H__
|
||||
#define __HC32_LL_EMB_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_EMB
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_EMB_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup EMB_Global_Types EMB Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief EMB monitor OSC failure configuration
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32OscState; /*!< Enable or disable EMB detect OSC failure function
|
||||
This parameter can be a value of @ref EMB_OSC_Selection */
|
||||
} stc_emb_monitor_osc_t;
|
||||
|
||||
/**
|
||||
* @brief EMB monitor EMB port configuration
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32PortState; /*!< Enable or disable EMB detect port in control function
|
||||
This parameter can be a value of @ref EMB_Port_Selection */
|
||||
uint32_t u32PortLevel; /*!< EMB detect port level
|
||||
This parameter can be a value of @ref EMB_Detect_Port_Level */
|
||||
uint32_t u32PortFilterDiv; /*!< EMB port filter division
|
||||
This parameter can be a value of @ref EMB_Port_Filter_Clock_Division */
|
||||
uint32_t u32PortFilterState; /*!< EMB port filter division
|
||||
This parameter can be a value of @ref EMB_Port_Filter_Selection */
|
||||
} stc_emb_monitor_port_config_t;
|
||||
|
||||
/**
|
||||
* @brief EMB monitor PWM configuration
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32PwmState; /*!< Enable or disable EMB detect timer same phase function
|
||||
This parameter can be a value of @ref EMB_Detect_PWM state. */
|
||||
uint32_t u32PwmLevel; /*!< Detect timer polarity level
|
||||
This parameter can be a value of @ref EMB_Detect_PWM level */
|
||||
} stc_emb_monitor_tmr_pwm_t;
|
||||
|
||||
/**
|
||||
* @brief EMB monitor port in configuration
|
||||
*/
|
||||
typedef struct {
|
||||
stc_emb_monitor_port_config_t stcPort1; /*!< EMB detect EMB port in function
|
||||
This parameter details refer @ref stc_emb_monitor_port_config_t structure */
|
||||
} stc_emb_monitor_port_t;
|
||||
|
||||
/**
|
||||
* @brief EMB monitor CMP configuration
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32Cmp1State; /*!< Enable or disable EMB detect CMP1 result function
|
||||
This parameter can be a value of @ref EMB_CMP_Selection */
|
||||
uint32_t u32Cmp2State; /*!< Enable or disable EMB detect CMP2 result function
|
||||
This parameter can be a value of @ref EMB_CMP_Selection */
|
||||
uint32_t u32Cmp3State; /*!< Enable or disable EMB detect CMP3 result function
|
||||
This parameter can be a value of @ref EMB_CMP_Selection */
|
||||
} stc_emb_monitor_cmp_t;
|
||||
|
||||
/**
|
||||
* @brief EMB monitor TMR4 configuration
|
||||
*/
|
||||
typedef struct {
|
||||
stc_emb_monitor_tmr_pwm_t stcTmr4PwmU; /*!< EMB detect TMR4 function
|
||||
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
|
||||
stc_emb_monitor_tmr_pwm_t stcTmr4PwmV; /*!< EMB detect TMR4 function
|
||||
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
|
||||
stc_emb_monitor_tmr_pwm_t stcTmr4PwmW; /*!< EMB detect TMR4 function
|
||||
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
|
||||
} stc_emb_monitor_tmr4_t;
|
||||
|
||||
/**
|
||||
* @brief EMB monitor TMR6 configuration
|
||||
*/
|
||||
typedef struct {
|
||||
stc_emb_monitor_tmr_pwm_t stcTmr6_1; /*!< EMB detect TMR6 function
|
||||
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
|
||||
stc_emb_monitor_tmr_pwm_t stcTmr6_2; /*!< EMB detect TMR6 function
|
||||
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
|
||||
stc_emb_monitor_tmr_pwm_t stcTmr6_3; /*!< EMB detect TMR6 function
|
||||
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
|
||||
} stc_emb_monitor_tmr6_t;
|
||||
|
||||
/**
|
||||
* @brief EMB control TMR4 initialization configuration
|
||||
*/
|
||||
typedef struct {
|
||||
stc_emb_monitor_cmp_t stcCmp; /*!< EMB detect CMP function
|
||||
This parameter details refer @ref stc_emb_monitor_cmp_t structure */
|
||||
stc_emb_monitor_osc_t stcOsc; /*!< EMB detect OSC function
|
||||
This parameter details refer @ref stc_emb_monitor_osc_t structure */
|
||||
stc_emb_monitor_port_t stcPort; /*!< EMB detect EMB port function
|
||||
This parameter details refer @ref stc_emb_monitor_port_t structure */
|
||||
stc_emb_monitor_tmr4_t stcTmr4; /*!< EMB detect TMR4 function
|
||||
This parameter details refer @ref stc_emb_monitor_tmr4_t structure */
|
||||
} stc_emb_tmr4_init_t;
|
||||
|
||||
/**
|
||||
* @brief EMB control TMR6 initialization configuration
|
||||
*/
|
||||
typedef struct {
|
||||
stc_emb_monitor_cmp_t stcCmp; /*!< EMB detect CMP function
|
||||
This parameter details refer @ref stc_emb_monitor_cmp_t structure */
|
||||
stc_emb_monitor_osc_t stcOsc; /*!< EMB detect OSC function
|
||||
This parameter details refer @ref stc_emb_monitor_osc_t structure */
|
||||
stc_emb_monitor_port_t stcPort; /*!< EMB detect EMB port function
|
||||
This parameter details refer @ref stc_emb_monitor_port_t structure */
|
||||
stc_emb_monitor_tmr6_t stcTmr6; /*!< EMB detect TMR6 function
|
||||
This parameter details refer @ref stc_emb_monitor_tmr6_t structure */
|
||||
} stc_emb_tmr6_init_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup EMB_Global_Macros EMB Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EMB_CMP_Selection EMB CMP Selection
|
||||
* @{
|
||||
*/
|
||||
#define EMB_CMP1_DISABLE (0UL)
|
||||
#define EMB_CMP2_DISABLE (0UL)
|
||||
#define EMB_CMP3_DISABLE (0UL)
|
||||
|
||||
#define EMB_CMP1_ENABLE (EMB_CTL_CMPEN1)
|
||||
#define EMB_CMP2_ENABLE (EMB_CTL_CMPEN2)
|
||||
#define EMB_CMP3_ENABLE (EMB_CTL_CMPEN3)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EMB_OSC_Selection EMB OSC Selection
|
||||
* @{
|
||||
*/
|
||||
#define EMB_OSC_DISABLE (0UL)
|
||||
#define EMB_OSC_ENABLE (EMB_CTL_OSCSTPEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EMB_Detect_PWM EMB Detect PWM
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @defgroup EMB_TMR4_PWM_Selection EMB TMR4 PWM Selection
|
||||
* @{
|
||||
*/
|
||||
#define EMB_TMR4_PWM_W_DISABLE (0UL)
|
||||
#define EMB_TMR4_PWM_V_DISABLE (0UL)
|
||||
#define EMB_TMR4_PWM_U_DISABLE (0UL)
|
||||
|
||||
#define EMB_TMR4_PWM_W_ENABLE (EMB_CTL_PWMSEN0)
|
||||
#define EMB_TMR4_PWM_V_ENABLE (EMB_CTL_PWMSEN1)
|
||||
#define EMB_TMR4_PWM_U_ENABLE (EMB_CTL_PWMSEN2)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EMB_Detect_TMR4_PWM_Level EMB Detect TMR4 PWM Level
|
||||
* @{
|
||||
*/
|
||||
#define EMB_DETECT_TMR4_PWM_W_BOTH_LOW (0UL)
|
||||
#define EMB_DETECT_TMR4_PWM_V_BOTH_LOW (0UL)
|
||||
#define EMB_DETECT_TMR4_PWM_U_BOTH_LOW (0UL)
|
||||
|
||||
#define EMB_DETECT_TMR4_PWM_W_BOTH_HIGH (EMB_PWMLV_PWMLV0)
|
||||
#define EMB_DETECT_TMR4_PWM_V_BOTH_HIGH (EMB_PWMLV_PWMLV1)
|
||||
#define EMB_DETECT_TMR4_PWM_U_BOTH_HIGH (EMB_PWMLV_PWMLV2)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EMB_TMR6_PWM_Selection EMB TMR6 PWM Selection
|
||||
* @{
|
||||
*/
|
||||
#define EMB_TMR6_1_PWM_DISABLE (0UL)
|
||||
#define EMB_TMR6_2_PWM_DISABLE (0UL)
|
||||
#define EMB_TMR6_3_PWM_DISABLE (0UL)
|
||||
|
||||
#define EMB_TMR6_1_PWM_ENABLE (EMB_CTL_PWMSEN0)
|
||||
#define EMB_TMR6_2_PWM_ENABLE (EMB_CTL_PWMSEN1)
|
||||
#define EMB_TMR6_3_PWM_ENABLE (EMB_CTL_PWMSEN2)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EMB_Detect_TMR6_PWM_Level EMB Detect TMR6 PWM Level
|
||||
* @{
|
||||
*/
|
||||
#define EMB_DETECT_TMR6_1_PWM_BOTH_LOW (0UL)
|
||||
#define EMB_DETECT_TMR6_2_PWM_BOTH_LOW (0UL)
|
||||
#define EMB_DETECT_TMR6_3_PWM_BOTH_LOW (0UL)
|
||||
|
||||
#define EMB_DETECT_TMR6_1_PWM_BOTH_HIGH (EMB_PWMLV_PWMLV0)
|
||||
#define EMB_DETECT_TMR6_2_PWM_BOTH_HIGH (EMB_PWMLV_PWMLV1)
|
||||
#define EMB_DETECT_TMR6_3_PWM_BOTH_HIGH (EMB_PWMLV_PWMLV2)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EMB_Port_Selection EMB Port Selection
|
||||
* @{
|
||||
*/
|
||||
#define EMB_PORT1_DISABLE (0UL)
|
||||
|
||||
#define EMB_PORT1_ENABLE (EMB_CTL_PORTINEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EMB_Detect_Port_Level EMB Detect Port Level
|
||||
* @{
|
||||
*/
|
||||
#define EMB_PORT1_DETECT_LVL_HIGH (0UL)
|
||||
|
||||
#define EMB_PORT1_DETECT_LVL_LOW (EMB_CTL_INVSEL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EMB_Port_Filter_Selection EMB Port Filter Selection
|
||||
* @{
|
||||
*/
|
||||
#define EMB_PORT1_FILTER_DISABLE (0UL)
|
||||
|
||||
#define EMB_PORT1_FILTER_ENABLE (EMB_CTL_NFEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EMB_Port_Filter_Clock_Division EMB Port Filter Clock Division
|
||||
* @{
|
||||
*/
|
||||
#define EMB_PORT1_FILTER_CLK_DIV1 (0UL << EMB_CTL_NFSEL_POS)
|
||||
#define EMB_PORT1_FILTER_CLK_DIV8 (1UL << EMB_CTL_NFSEL_POS)
|
||||
#define EMB_PORT1_FILTER_CLK_DIV32 (2UL << EMB_CTL_NFSEL_POS)
|
||||
#define EMB_PORT1_FILTER_CLK_DIV128 (3UL << EMB_CTL_NFSEL_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EMB_Flag_State EMB Flag State
|
||||
* @{
|
||||
*/
|
||||
#define EMB_FLAG_PWMS (EMB_STAT_PWMSF)
|
||||
#define EMB_FLAG_CMP (EMB_STAT_CMPF)
|
||||
#define EMB_FLAG_OSC (EMB_STAT_OSF)
|
||||
#define EMB_FLAG_PORT1 (EMB_STAT_PORTINF)
|
||||
#define EMB_STAT_PWMS (EMB_STAT_PWMST)
|
||||
#define EMB_STAT_PORT1 (EMB_STAT_PORTINST)
|
||||
#define EMB_FLAG_ALL (EMB_FLAG_PWMS | EMB_FLAG_CMP | EMB_FLAG_OSC | EMB_FLAG_PORT1 | \
|
||||
EMB_STAT_PWMS | EMB_STAT_PORT1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EMB_Interrupt EMB Interrupt
|
||||
* @{
|
||||
*/
|
||||
#define EMB_INT_PWMS (EMB_INTEN_PWMSINTEN)
|
||||
#define EMB_INT_CMP (EMB_INTEN_CMPINTEN)
|
||||
#define EMB_INT_OSC (EMB_INTEN_OSINTEN)
|
||||
#define EMB_INT_PORT1 (EMB_INTEN_PORTININTEN)
|
||||
#define EMB_INT_ALL (EMB_INT_PWMS | EMB_INT_CMP | EMB_INT_OSC | EMB_INT_PORT1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup EMB_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
int32_t EMB_TMR4_StructInit(stc_emb_tmr4_init_t *pstcEmbInit);
|
||||
int32_t EMB_TMR4_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr4_init_t *pstcEmbInit);
|
||||
|
||||
int32_t EMB_TMR6_StructInit(stc_emb_tmr6_init_t *pstcEmbInit);
|
||||
int32_t EMB_TMR6_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr6_init_t *pstcEmbInit);
|
||||
|
||||
void EMB_DeInit(CM_EMB_TypeDef *EMBx);
|
||||
void EMB_IntCmd(CM_EMB_TypeDef *EMBx, uint32_t u32IntType, en_functional_state_t enNewState);
|
||||
void EMB_ClearStatus(CM_EMB_TypeDef *EMBx, uint32_t u32Flag);
|
||||
en_flag_status_t EMB_GetStatus(const CM_EMB_TypeDef *EMBx, uint32_t u32Flag);
|
||||
void EMB_SWBrake(CM_EMB_TypeDef *EMBx, en_functional_state_t enNewState);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_EMB_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_EMB_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,233 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_event_port.h
|
||||
* @brief This file contains all the functions prototypes of the Event Port
|
||||
* driver library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_EVENT_PORT_H__
|
||||
#define __HC32_LL_EVENT_PORT_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_EVENT_PORT
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_EVENT_PORT_ENABLE == DDL_ON)
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup EP_Global_Types Event Port Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Event Pin Set and Reset enumeration
|
||||
*/
|
||||
typedef enum {
|
||||
EVT_PIN_RESET = 0U, /*!< Pin reset */
|
||||
EVT_PIN_SET = 1U /*!< Pin set */
|
||||
} en_ep_state_t;
|
||||
|
||||
typedef struct {
|
||||
uint32_t u32PinDir; /*!< Input/Output setting, @ref EP_PinDirection_Sel for details */
|
||||
en_ep_state_t enPinState; /*!< Corresponding pin initial state, @ref en_ep_state_t for details */
|
||||
uint32_t u32PinTriggerOps; /*!< Corresponding pin state after triggered, @ref EP_TriggerOps_Sel for details */
|
||||
uint32_t u32Edge; /*!< Event port trigger edge, @ref EP_Trigger_Sel for details */
|
||||
uint32_t u32Filter; /*!< Filter clock function setting, @ref EP_FilterClock_Sel for details */
|
||||
uint32_t u32FilterClock; /*!< Filter clock, ref@ EP_FilterClock_Div for details */
|
||||
} stc_ep_init_t;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup EP_Global_Macros Event Port Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EP_Port_source EP Port Source
|
||||
* @{
|
||||
*/
|
||||
#define EVT_PORT_1 (0U) /*!< Event port 1 */
|
||||
#define EVT_PORT_2 (1U) /*!< Event port 2 */
|
||||
#define EVT_PORT_3 (2U) /*!< Event port 3 */
|
||||
#define EVT_PORT_4 (3U) /*!< Event port 4 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EP_pins_define EP Pin Source
|
||||
* @{
|
||||
*/
|
||||
#define EVT_PIN_00 (0x0001U) /*!< Event port Pin 00 */
|
||||
#define EVT_PIN_01 (0x0002U) /*!< Event port Pin 01 */
|
||||
#define EVT_PIN_02 (0x0004U) /*!< Event port Pin 02 */
|
||||
#define EVT_PIN_03 (0x0008U) /*!< Event port Pin 03 */
|
||||
#define EVT_PIN_04 (0x0010U) /*!< Event port Pin 04 */
|
||||
#define EVT_PIN_05 (0x0020U) /*!< Event port Pin 05 */
|
||||
#define EVT_PIN_06 (0x0040U) /*!< Event port Pin 06 */
|
||||
#define EVT_PIN_07 (0x0080U) /*!< Event port Pin 07 */
|
||||
#define EVT_PIN_08 (0x0100U) /*!< Event port Pin 08 */
|
||||
#define EVT_PIN_09 (0x0200U) /*!< Event port Pin 09 */
|
||||
#define EVT_PIN_10 (0x0400U) /*!< Event port Pin 10 */
|
||||
#define EVT_PIN_11 (0x0800U) /*!< Event port Pin 11 */
|
||||
#define EVT_PIN_12 (0x1000U) /*!< Event port Pin 12 */
|
||||
#define EVT_PIN_13 (0x2000U) /*!< Event port Pin 13 */
|
||||
#define EVT_PIN_14 (0x4000U) /*!< Event port Pin 14 */
|
||||
#define EVT_PIN_15 (0x8000U) /*!< Event port Pin 15 */
|
||||
#define EVT_PIN_All (0xFFFFU) /*!< All event pins are selected */
|
||||
#define EVT_PIN_MASK (0xFFFFU) /*!< Event pin mask for assert test */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EP_PinDirection_Sel EP Pin Input/Output Direction Selection
|
||||
* @{
|
||||
*/
|
||||
#define EP_DIR_IN (0UL) /*!< EP input */
|
||||
#define EP_DIR_OUT (1UL) /*!< EP output */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EP_FilterClock_Sel Event Port Filter Function Selection
|
||||
* @{
|
||||
*/
|
||||
#define EP_FILTER_OFF (0UL) /*!< EP filter function OFF */
|
||||
|
||||
#define EP_FILTER_ON (1UL) /*!< EP filter function ON */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EP_FilterClock_Div Event Port Filter Sampling Clock Division Selection
|
||||
* @{
|
||||
*/
|
||||
#define EP_FCLK_DIV1 (0UL) /*!< PCLK as EP filter clock source */
|
||||
#define EP_FCLK_DIV8 (1UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div8 as EP filter clock source */
|
||||
#define EP_FCLK_DIV32 (2UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div32 as EP filter clock source */
|
||||
#define EP_FCLK_DIV64 (3UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div64 as EP filter clock source */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EP_Trigger_Sel Event Port Trigger Edge Selection
|
||||
* @{
|
||||
*/
|
||||
#define EP_TRIG_NONE (0UL) /*!< No Trigger by edge */
|
||||
#define EP_TRIG_FALLING (1UL) /*!< Trigger by falling edge */
|
||||
#define EP_TRIG_RISING (2UL) /*!< Trigger by rising edge */
|
||||
#define EP_TRIG_BOTH (3UL) /*!< Trigger by falling and rising edge */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EP_TriggerOps_Sel Event Port Operation
|
||||
* @{
|
||||
*/
|
||||
#define EP_OPS_NONE (0UL) /*!< Pin no action after triggered */
|
||||
#define EP_OPS_LOW (1UL) /*!< Pin ouput low after triggered */
|
||||
#define EP_OPS_HIGH (2UL) /*!< Pin ouput high after triggered */
|
||||
#define EP_OPS_TOGGLE (3UL) /*!< Pin toggle after triggered */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup EP_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
void EP_DeInit(void);
|
||||
int32_t EP_StructInit(stc_ep_init_t *pstcEventPortInit);
|
||||
|
||||
int32_t EP_Init(uint8_t u8EventPort, uint16_t u16EventPin, const stc_ep_init_t *pstcEventPortInit);
|
||||
int32_t EP_SetTriggerEdge(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Edge);
|
||||
int32_t EP_SetTriggerOps(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Ops);
|
||||
en_ep_state_t EP_ReadInputPins(uint8_t u8EventPort, uint16_t u16EventPin);
|
||||
uint16_t EP_ReadInputPort(uint8_t u8EventPort);
|
||||
en_ep_state_t EP_ReadOutputPins(uint8_t u8EventPort, uint16_t u16EventPin);
|
||||
uint16_t EP_ReadOutputPort(uint8_t u8EventPort);
|
||||
void EP_SetPins(uint8_t u8EventPort, uint16_t u16EventPin);
|
||||
void EP_ResetPins(uint8_t u8EventPort, uint16_t u16EventPin);
|
||||
void EP_SetDir(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Dir);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_EVENT_PORT_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_EVENT_PORT_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,203 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_fcg.h
|
||||
* @brief This file contains all the functions prototypes of the FCG driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_FCG_H__
|
||||
#define __HC32_LL_FCG_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_FCG
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_FCG_ENABLE == DDL_ON)
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup FCG_Global_Macros FCG Global Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @defgroup FCG_FCG0_Peripheral FCG FCG0 peripheral
|
||||
* @{
|
||||
*/
|
||||
#define FCG0_PERIPH_SRAMH (PWC_FCG0_SRAMH)
|
||||
#define FCG0_PERIPH_SRAM12 (PWC_FCG0_SRAM12)
|
||||
#define FCG0_PERIPH_SRAM3 (PWC_FCG0_SRAM3)
|
||||
#define FCG0_PERIPH_SRAMRET (PWC_FCG0_SRAMRET)
|
||||
#define FCG0_PERIPH_DMA1 (PWC_FCG0_DMA1)
|
||||
#define FCG0_PERIPH_DMA2 (PWC_FCG0_DMA2)
|
||||
#define FCG0_PERIPH_FCM (PWC_FCG0_FCM)
|
||||
#define FCG0_PERIPH_AOS (PWC_FCG0_AOS)
|
||||
#define FCG0_PERIPH_AES (PWC_FCG0_AES)
|
||||
#define FCG0_PERIPH_HASH (PWC_FCG0_HASH)
|
||||
#define FCG0_PERIPH_TRNG (PWC_FCG0_TRNG)
|
||||
#define FCG0_PERIPH_CRC (PWC_FCG0_CRC)
|
||||
#define FCG0_PERIPH_DCU1 (PWC_FCG0_DCU1)
|
||||
#define FCG0_PERIPH_DCU2 (PWC_FCG0_DCU2)
|
||||
#define FCG0_PERIPH_DCU3 (PWC_FCG0_DCU3)
|
||||
#define FCG0_PERIPH_DCU4 (PWC_FCG0_DCU4)
|
||||
#define FCG0_PERIPH_KEY (PWC_FCG0_KEY)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup FCG_FCG1_Peripheral FCG FCG1 peripheral
|
||||
* @{
|
||||
*/
|
||||
#define FCG1_PERIPH_CAN (PWC_FCG1_CAN)
|
||||
#define FCG1_PERIPH_QSPI (PWC_FCG1_QSPI)
|
||||
#define FCG1_PERIPH_I2C1 (PWC_FCG1_I2C1)
|
||||
#define FCG1_PERIPH_I2C2 (PWC_FCG1_I2C2)
|
||||
#define FCG1_PERIPH_I2C3 (PWC_FCG1_I2C3)
|
||||
#define FCG1_PERIPH_USBFS (PWC_FCG1_USBFS)
|
||||
#define FCG1_PERIPH_SDIOC1 (PWC_FCG1_SDIOC1)
|
||||
#define FCG1_PERIPH_SDIOC2 (PWC_FCG1_SDIOC2)
|
||||
#define FCG1_PERIPH_I2S1 (PWC_FCG1_I2S1)
|
||||
#define FCG1_PERIPH_I2S2 (PWC_FCG1_I2S2)
|
||||
#define FCG1_PERIPH_I2S3 (PWC_FCG1_I2S3)
|
||||
#define FCG1_PERIPH_I2S4 (PWC_FCG1_I2S4)
|
||||
#define FCG1_PERIPH_SPI1 (PWC_FCG1_SPI1)
|
||||
#define FCG1_PERIPH_SPI2 (PWC_FCG1_SPI2)
|
||||
#define FCG1_PERIPH_SPI3 (PWC_FCG1_SPI3)
|
||||
#define FCG1_PERIPH_SPI4 (PWC_FCG1_SPI4)
|
||||
#define FCG1_PERIPH_USART1 (PWC_FCG1_USART1)
|
||||
#define FCG1_PERIPH_USART2 (PWC_FCG1_USART2)
|
||||
#define FCG1_PERIPH_USART3 (PWC_FCG1_USART3)
|
||||
#define FCG1_PERIPH_USART4 (PWC_FCG1_USART4)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup FCG_FCG2_Peripheral FCG FCG2 peripheral
|
||||
* @{
|
||||
*/
|
||||
#define FCG2_PERIPH_TMR0_1 (PWC_FCG2_TIMER0_1)
|
||||
#define FCG2_PERIPH_TMR0_2 (PWC_FCG2_TIMER0_2)
|
||||
#define FCG2_PERIPH_TMRA_1 (PWC_FCG2_TIMERA_1)
|
||||
#define FCG2_PERIPH_TMRA_2 (PWC_FCG2_TIMERA_2)
|
||||
#define FCG2_PERIPH_TMRA_3 (PWC_FCG2_TIMERA_3)
|
||||
#define FCG2_PERIPH_TMRA_4 (PWC_FCG2_TIMERA_4)
|
||||
#define FCG2_PERIPH_TMRA_5 (PWC_FCG2_TIMERA_5)
|
||||
#define FCG2_PERIPH_TMRA_6 (PWC_FCG2_TIMERA_6)
|
||||
#define FCG2_PERIPH_TMR4_1 (PWC_FCG2_TIMER4_1)
|
||||
#define FCG2_PERIPH_TMR4_2 (PWC_FCG2_TIMER4_2)
|
||||
#define FCG2_PERIPH_TMR4_3 (PWC_FCG2_TIMER4_3)
|
||||
#define FCG2_PERIPH_EMB (PWC_FCG2_EMB)
|
||||
#define FCG2_PERIPH_TMR6_1 (PWC_FCG2_TIMER6_1)
|
||||
#define FCG2_PERIPH_TMR6_2 (PWC_FCG2_TIMER6_2)
|
||||
#define FCG2_PERIPH_TMR6_3 (PWC_FCG2_TIMER6_3)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup FCG_FCG3_Peripheral FCG FCG3 peripheral
|
||||
* @{
|
||||
*/
|
||||
#define FCG3_PERIPH_ADC1 (PWC_FCG3_ADC1)
|
||||
#define FCG3_PERIPH_ADC2 (PWC_FCG3_ADC2)
|
||||
#define FCG3_PERIPH_CMP (PWC_FCG3_CMP)
|
||||
#define FCG3_PERIPH_OTS (PWC_FCG3_OTS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup FCG_FCGx_Peripheral_Mask FCG FCGx Peripheral Mask
|
||||
* @{
|
||||
*/
|
||||
#define FCG_FCG0_PERIPH_MASK (0x8FF3C511UL)
|
||||
#define FCG_FCG1_PERIPH_MASK (0x0F0FFD79UL)
|
||||
#define FCG_FCG2_PERIPH_MASK (0x000787FFUL)
|
||||
#define FCG_FCG3_PERIPH_MASK (0x00001103UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup FCG_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void FCG_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState);
|
||||
|
||||
void FCG_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState);
|
||||
void FCG_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState);
|
||||
void FCG_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_FCG_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_FCG_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,293 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_fcm.h
|
||||
* @brief This file contains all the functions prototypes of the FCM driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2023-06-30 CDT Modify API FCM_DeInit()
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_FCM_H__
|
||||
#define __HC32_LL_FCM_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_FCM
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_FCM_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup FCM_Global_Types FCM Global Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief FCM Init structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint16_t u16LowerLimit; /*!< FCM lower limit value */
|
||||
uint16_t u16UpperLimit; /*!< FCM upper limit value */
|
||||
uint32_t u32TargetClock; /*!< FCM target clock source selection, @ref FCM_Target_Clock_Src */
|
||||
uint32_t u32TargetClockDiv; /*!< FCM target clock source division selection, @ref FCM_Target_Clock_Div */
|
||||
uint32_t u32ExtRefClockEnable; /*!< FCM external reference clock function config, @ref FCM_Ext_Ref_Clock_Config */
|
||||
uint32_t u32RefClockEdge; /*!< FCM reference clock trigger edge selection, @ref FCM_Ref_Clock_Edge */
|
||||
uint32_t u32DigitalFilter; /*!< FCM digital filter function config, @ref FCM_Digital_Filter_Config */
|
||||
uint32_t u32RefClock; /*!< FCM reference clock source selection, @ref FCM_Ref_Clock_Src */
|
||||
uint32_t u32RefClockDiv; /*!< FCM reference clock source division selection, @ref FCM_Ref_Clock_Div */
|
||||
uint32_t u32ExceptionType; /*!< FCM exception type select, @ref FCM_Exception_Type */
|
||||
} stc_fcm_init_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup FCM_Global_Macros FCM Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup FCM_Target_Clock_Src FCM Target Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define FCM_TARGET_CLK_XTAL (0x00UL << FCM_MCCR_MCKS_POS)
|
||||
#define FCM_TARGET_CLK_XTAL32 (0x01UL << FCM_MCCR_MCKS_POS)
|
||||
#define FCM_TARGET_CLK_HRC (0x02UL << FCM_MCCR_MCKS_POS)
|
||||
#define FCM_TARGET_CLK_LRC (0x03UL << FCM_MCCR_MCKS_POS)
|
||||
#define FCM_TARGET_CLK_SWDTLRC (0x04UL << FCM_MCCR_MCKS_POS)
|
||||
#define FCM_TARGET_CLK_PCLK1 (0x05UL << FCM_MCCR_MCKS_POS)
|
||||
#define FCM_TARGET_CLK_UPLLP (0x06UL << FCM_MCCR_MCKS_POS)
|
||||
#define FCM_TARGET_CLK_MRC (0x07UL << FCM_MCCR_MCKS_POS)
|
||||
#define FCM_TARGET_CLK_MPLLP (0x08UL << FCM_MCCR_MCKS_POS)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup FCM_Target_Clock_Div FCM Target Clock Division
|
||||
* @{
|
||||
*/
|
||||
#define FCM_TARGET_CLK_DIV1 (0x00UL << FCM_MCCR_MDIVS_POS)
|
||||
#define FCM_TARGET_CLK_DIV4 (0x01UL << FCM_MCCR_MDIVS_POS)
|
||||
#define FCM_TARGET_CLK_DIV8 (0x02UL << FCM_MCCR_MDIVS_POS)
|
||||
#define FCM_TARGET_CLK_DIV32 (0x03UL << FCM_MCCR_MDIVS_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup FCM_Ext_Ref_Clock_Config FCM External Reference Clock Config
|
||||
* @{
|
||||
*/
|
||||
#define FCM_EXT_REF_OFF (0x00UL)
|
||||
#define FCM_EXT_REF_ON (FCM_RCCR_EXREFE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup FCM_Ref_Clock_Edge FCM Reference Clock Edge
|
||||
* @{
|
||||
*/
|
||||
#define FCM_REF_CLK_RISING (0x00UL)
|
||||
#define FCM_REF_CLK_FALLING (FCM_RCCR_EDGES_0)
|
||||
#define FCM_REF_CLK_BOTH (FCM_RCCR_EDGES_1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup FCM_Digital_Filter_Config FCM Digital Filter Config
|
||||
* @{
|
||||
*/
|
||||
#define FCM_DIG_FILTER_OFF (0x00UL)
|
||||
#define FCM_DIG_FILTER_DIV1 (FCM_RCCR_DNFS_0)
|
||||
#define FCM_DIG_FILTER_DIV4 (FCM_RCCR_DNFS_1)
|
||||
#define FCM_DIG_FILTER_DIV16 (FCM_RCCR_DNFS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup FCM_Ref_Clock_Src FCM Reference Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define FCM_REF_CLK_EXTCLK (0x00UL << FCM_RCCR_RCKS_POS)
|
||||
#define FCM_REF_CLK_XTAL (0x10UL << FCM_RCCR_RCKS_POS)
|
||||
#define FCM_REF_CLK_XTAL32 (0x11UL << FCM_RCCR_RCKS_POS)
|
||||
#define FCM_REF_CLK_HRC (0x12UL << FCM_RCCR_RCKS_POS)
|
||||
#define FCM_REF_CLK_LRC (0x13UL << FCM_RCCR_RCKS_POS)
|
||||
#define FCM_REF_CLK_SWDTLRC (0x14UL << FCM_RCCR_RCKS_POS)
|
||||
#define FCM_REF_CLK_PCLK1 (0x15UL << FCM_RCCR_RCKS_POS)
|
||||
#define FCM_REF_CLK_UPLLP (0x16UL << FCM_RCCR_RCKS_POS)
|
||||
#define FCM_REF_CLK_MRC (0x17UL << FCM_RCCR_RCKS_POS)
|
||||
#define FCM_REF_CLK_MPLLP (0x18UL << FCM_RCCR_RCKS_POS)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup FCM_Ref_Clock_Div FCM Reference Clock Division
|
||||
* @{
|
||||
*/
|
||||
#define FCM_REF_CLK_DIV32 (0x00UL << FCM_RCCR_RDIVS_POS)
|
||||
#define FCM_REF_CLK_DIV128 (0x01UL << FCM_RCCR_RDIVS_POS)
|
||||
#define FCM_REF_CLK_DIV1024 (0x02UL << FCM_RCCR_RDIVS_POS)
|
||||
#define FCM_REF_CLK_DIV8192 (0x03UL << FCM_RCCR_RDIVS_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup FCM_Abnormal_Reset_Func FCM Abnormal Reset Function Config
|
||||
* @{
|
||||
*/
|
||||
#define FCM_ERR_RST_OFF (0x00UL)
|
||||
#define FCM_ERR_RST_ON (FCM_RIER_ERRE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup FCM_Exception_Type FCM Exception Type
|
||||
* @{
|
||||
*/
|
||||
#define FCM_EXP_TYPE_INT (0x00UL)
|
||||
#define FCM_EXP_TYPE_RST (FCM_RIER_ERRINTRS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup FCM_Int_Type FCM Interrupt Type
|
||||
* @{
|
||||
*/
|
||||
#define FCM_INT_OVF (FCM_RIER_OVFIE)
|
||||
#define FCM_INT_END (FCM_RIER_MENDIE)
|
||||
#define FCM_INT_ERR (FCM_RIER_ERRIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup FCM_Flag_Sel FCM Status Flag Selection
|
||||
* @{
|
||||
*/
|
||||
#define FCM_FLAG_ERR (FCM_SR_ERRF)
|
||||
#define FCM_FLAG_END (FCM_SR_MENDF)
|
||||
#define FCM_FLAG_OVF (FCM_SR_OVF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup FCM_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set FCM upper limit value.
|
||||
* @param u16Limit
|
||||
* @retval None.
|
||||
*/
|
||||
__STATIC_INLINE void FCM_SetUpperLimit(uint16_t u16Limit)
|
||||
{
|
||||
WRITE_REG32(CM_FCM->UVR, u16Limit);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set FCM lower limit value.
|
||||
* @param u16Limit
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void FCM_SetLowerLimit(uint16_t u16Limit)
|
||||
{
|
||||
WRITE_REG32(CM_FCM->LVR, u16Limit);
|
||||
}
|
||||
|
||||
int32_t FCM_Init(const stc_fcm_init_t *pstcFcmInit);
|
||||
int32_t FCM_StructInit(stc_fcm_init_t *pstcFcmInit);
|
||||
int32_t FCM_DeInit(void);
|
||||
uint16_t FCM_GetCountValue(void);
|
||||
void FCM_SetUpperLimit(uint16_t u16Limit);
|
||||
void FCM_SetLowerLimit(uint16_t u16Limit);
|
||||
void FCM_SetTargetClock(uint32_t u32ClockSrc, uint32_t u32Div);
|
||||
void FCM_SetRefClock(uint32_t u32ClockSrc, uint32_t u32Div);
|
||||
en_flag_status_t FCM_GetStatus(uint32_t u32Flag);
|
||||
void FCM_ClearStatus(uint32_t u32Flag);
|
||||
void FCM_ResetCmd(en_functional_state_t enNewState);
|
||||
void FCM_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState);
|
||||
void FCM_Cmd(en_functional_state_t enNewState);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_FCM_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_FCM_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,418 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_gpio.h
|
||||
* @brief This file contains all the functions prototypes of the GPIO driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2022-06-30 CDT Add API GPIO_AnalogCmd() and GPIO_ExIntCmd()
|
||||
2023-06-30 CDT Rename GPIO_ExIntCmd() as GPIO_ExtIntCmd
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_GPIO_H__
|
||||
#define __HC32_LL_GPIO_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_GPIO_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup GPIO_Global_Types GPIO Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief GPIO Pin Set and Reset enumeration
|
||||
*/
|
||||
typedef enum {
|
||||
PIN_RESET = 0U, /*!< Pin reset */
|
||||
PIN_SET = 1U /*!< Pin set */
|
||||
} en_pin_state_t;
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint16_t u16PinState; /*!< Set pin state to High or Low, @ref GPIO_PinState_Sel for details */
|
||||
uint16_t u16PinDir; /*!< Pin mode setting, @ref GPIO_PinDirection_Sel for details */
|
||||
uint16_t u16PinOutputType; /*!< Output type setting, @ref GPIO_PinOutType_Sel for details */
|
||||
uint16_t u16PinDrv; /*!< Pin drive capacity setting, @ref GPIO_PinDrv_Sel for details */
|
||||
uint16_t u16Latch; /*!< Pin latch setting, @ref GPIO_PinLatch_Sel for details */
|
||||
uint16_t u16PullUp; /*!< Internal pull-up resistor setting, @ref GPIO_PinPU_Sel for details */
|
||||
uint16_t u16Invert; /*!< Pin input/output invert setting, @ref GPIO_PinInvert_Sel for details */
|
||||
uint16_t u16ExtInt; /*!< External interrupt pin setting, @ref GPIO_PinExtInt_Sel for details */
|
||||
uint16_t u16PinAttr; /*!< Digital or analog attribute setting, @ref GPIO_PinMode_Sel for details */
|
||||
} stc_gpio_init_t;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup GPIO_Global_Macros GPIO Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup GPIO_Pins_Define GPIO Pin Source
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PIN_00 (0x0001U) /*!< Pin 00 selected */
|
||||
#define GPIO_PIN_01 (0x0002U) /*!< Pin 01 selected */
|
||||
#define GPIO_PIN_02 (0x0004U) /*!< Pin 02 selected */
|
||||
#define GPIO_PIN_03 (0x0008U) /*!< Pin 03 selected */
|
||||
#define GPIO_PIN_04 (0x0010U) /*!< Pin 04 selected */
|
||||
#define GPIO_PIN_05 (0x0020U) /*!< Pin 05 selected */
|
||||
#define GPIO_PIN_06 (0x0040U) /*!< Pin 06 selected */
|
||||
#define GPIO_PIN_07 (0x0080U) /*!< Pin 07 selected */
|
||||
#define GPIO_PIN_08 (0x0100U) /*!< Pin 08 selected */
|
||||
#define GPIO_PIN_09 (0x0200U) /*!< Pin 09 selected */
|
||||
#define GPIO_PIN_10 (0x0400U) /*!< Pin 10 selected */
|
||||
#define GPIO_PIN_11 (0x0800U) /*!< Pin 11 selected */
|
||||
#define GPIO_PIN_12 (0x1000U) /*!< Pin 12 selected */
|
||||
#define GPIO_PIN_13 (0x2000U) /*!< Pin 13 selected */
|
||||
#define GPIO_PIN_14 (0x4000U) /*!< Pin 14 selected */
|
||||
#define GPIO_PIN_15 (0x8000U) /*!< Pin 15 selected */
|
||||
#define GPIO_PIN_ALL (0xFFFFU) /*!< All pins selected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup GPIO_All_Pins_Define GPIO All Pin Definition for Each Product
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PIN_A_ALL (0xFFFFU) /*!< Pin A all*/
|
||||
#define GPIO_PIN_B_ALL (0xFFFFU) /*!< Pin B all*/
|
||||
#define GPIO_PIN_C_ALL (0xFFFFU) /*!< Pin C all*/
|
||||
#define GPIO_PIN_D_ALL (0xFFFFU) /*!< Pin D all*/
|
||||
#define GPIO_PIN_E_ALL (0xFFFFU) /*!< Pin E all*/
|
||||
#define GPIO_PIN_H_ALL (0x0007U) /*!< Pin H all*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup GPIO_Port_Source GPIO Port Source
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PORT_A (0x00U) /*!< Port A selected */
|
||||
#define GPIO_PORT_B (0x01U) /*!< Port B selected */
|
||||
#define GPIO_PORT_C (0x02U) /*!< Port C selected */
|
||||
#define GPIO_PORT_D (0x03U) /*!< Port D selected */
|
||||
#define GPIO_PORT_E (0x04U) /*!< Port E selected */
|
||||
#define GPIO_PORT_H (0x05U) /*!< Port H selected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup GPIO_Function_Sel GPIO Function Selection
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_FUNC_0 (0U)
|
||||
#define GPIO_FUNC_1 (1U)
|
||||
#define GPIO_FUNC_2 (2U)
|
||||
#define GPIO_FUNC_3 (3U)
|
||||
#define GPIO_FUNC_4 (4U)
|
||||
#define GPIO_FUNC_5 (5U)
|
||||
#define GPIO_FUNC_6 (6U)
|
||||
#define GPIO_FUNC_7 (7U)
|
||||
#define GPIO_FUNC_8 (8U)
|
||||
#define GPIO_FUNC_9 (9U)
|
||||
#define GPIO_FUNC_10 (10U)
|
||||
#define GPIO_FUNC_11 (11U)
|
||||
#define GPIO_FUNC_12 (12U)
|
||||
#define GPIO_FUNC_13 (13U)
|
||||
#define GPIO_FUNC_14 (14U)
|
||||
#define GPIO_FUNC_15 (15U)
|
||||
#define GPIO_FUNC_32 (32U)
|
||||
#define GPIO_FUNC_33 (33U)
|
||||
#define GPIO_FUNC_34 (34U)
|
||||
#define GPIO_FUNC_35 (35U)
|
||||
#define GPIO_FUNC_36 (36U)
|
||||
#define GPIO_FUNC_37 (37U)
|
||||
#define GPIO_FUNC_38 (38U)
|
||||
#define GPIO_FUNC_39 (39U)
|
||||
#define GPIO_FUNC_40 (40U)
|
||||
#define GPIO_FUNC_41 (41U)
|
||||
#define GPIO_FUNC_42 (42U)
|
||||
#define GPIO_FUNC_43 (43U)
|
||||
#define GPIO_FUNC_44 (44U)
|
||||
#define GPIO_FUNC_45 (45U)
|
||||
#define GPIO_FUNC_46 (46U)
|
||||
#define GPIO_FUNC_47 (47U)
|
||||
#define GPIO_FUNC_48 (48U)
|
||||
#define GPIO_FUNC_49 (49U)
|
||||
#define GPIO_FUNC_50 (50U)
|
||||
#define GPIO_FUNC_51 (51U)
|
||||
#define GPIO_FUNC_52 (52U)
|
||||
#define GPIO_FUNC_53 (53U)
|
||||
#define GPIO_FUNC_54 (54U)
|
||||
#define GPIO_FUNC_55 (55U)
|
||||
#define GPIO_FUNC_56 (56U)
|
||||
#define GPIO_FUNC_57 (57U)
|
||||
#define GPIO_FUNC_58 (58U)
|
||||
#define GPIO_FUNC_59 (59U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup GPIO_DebugPin_Sel GPIO Debug Pin Selection
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PIN_TCK (0x01U)
|
||||
#define GPIO_PIN_TMS (0x02U)
|
||||
#define GPIO_PIN_TDO (0x04U)
|
||||
#define GPIO_PIN_TDI (0x08U)
|
||||
#define GPIO_PIN_TRST (0x10U)
|
||||
#define GPIO_PIN_DEBUG_JTAG (0x1FU)
|
||||
#define GPIO_PIN_SWCLK (0x01U)
|
||||
#define GPIO_PIN_SWDIO (0x02U)
|
||||
#define GPIO_PIN_SWO (0x04U)
|
||||
#define GPIO_PIN_DEBUG_SWD (0x07U)
|
||||
#define GPIO_PIN_DEBUG (0x1FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup GPIO_ReadCycle_Sel GPIO Pin Read Wait Cycle Selection
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_RD_WAIT0 (0x00U << GPIO_PCCR_RDWT_POS)
|
||||
#define GPIO_RD_WAIT1 (0x01U << GPIO_PCCR_RDWT_POS)
|
||||
#define GPIO_RD_WAIT2 (0x02U << GPIO_PCCR_RDWT_POS)
|
||||
#define GPIO_RD_WAIT3 (0x03U << GPIO_PCCR_RDWT_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup GPIO_PinState_Sel GPIO Pin Output State Selection
|
||||
* @{
|
||||
*/
|
||||
#define PIN_STAT_RST (0U)
|
||||
#define PIN_STAT_SET (GPIO_PCR_POUT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup GPIO_PinDirection_Sel GPIO Pin Input/Output Direction Selection
|
||||
* @{
|
||||
*/
|
||||
#define PIN_DIR_IN (0U)
|
||||
#define PIN_DIR_OUT (GPIO_PCR_POUTE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup GPIO_PinOutType_Sel GPIO Pin Output Type Selection
|
||||
* @{
|
||||
*/
|
||||
#define PIN_OUT_TYPE_CMOS (0U)
|
||||
#define PIN_OUT_TYPE_NMOS (GPIO_PCR_NOD)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup GPIO_PinDrv_Sel GPIO Pin Drive Capacity Selection
|
||||
* @{
|
||||
*/
|
||||
#define PIN_LOW_DRV (0U)
|
||||
#define PIN_MID_DRV (GPIO_PCR_DRV_0)
|
||||
#define PIN_HIGH_DRV (GPIO_PCR_DRV_1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup GPIO_PinLatch_Sel GPIO Pin Output Latch Selection
|
||||
* @{
|
||||
*/
|
||||
#define PIN_LATCH_OFF (0U)
|
||||
#define PIN_LATCH_ON (GPIO_PCR_LTE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup GPIO_PinPU_Sel GPIO Pin Internal Pull-Up Resistor Selection
|
||||
* @{
|
||||
*/
|
||||
#define PIN_PU_OFF (0U)
|
||||
#define PIN_PU_ON (GPIO_PCR_PUU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup GPIO_PinInvert_Sel GPIO Pin I/O Invert Selection
|
||||
* @{
|
||||
*/
|
||||
#define PIN_INVT_OFF (0U)
|
||||
#define PIN_INVT_ON (GPIO_PCR_INVE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup GPIO_PinExtInt_Sel GPIO Pin External Interrupt Selection
|
||||
* @{
|
||||
*/
|
||||
#define PIN_EXTINT_OFF (0U)
|
||||
#define PIN_EXTINT_ON (GPIO_PCR_INTE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup GPIO_PinMode_Sel GPIO Pin Mode Selection
|
||||
* @{
|
||||
*/
|
||||
#define PIN_ATTR_DIGITAL (0U)
|
||||
#define PIN_ATTR_ANALOG (GPIO_PCR_DDIS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup GPIO_PinSubFuncSet_Sel GPIO Pin Sub-function Enable or Disable
|
||||
* @{
|
||||
*/
|
||||
#define PIN_SUBFUNC_DISABLE (0U)
|
||||
#define PIN_SUBFUNC_ENABLE (GPIO_PFSR_BFE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup GPIO_Register_Protect_Key GPIO Registers Protect Key
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_REG_LOCK_KEY (0xA500U)
|
||||
#define GPIO_REG_UNLOCK_KEY (0xA501U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup GPIO_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief GPIO lock. PSPCR, PCCR, PINAER, PCRxy, PFSRxy write disable
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void GPIO_REG_Lock(void)
|
||||
{
|
||||
WRITE_REG16(CM_GPIO->PWPR, GPIO_REG_LOCK_KEY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief GPIO unlock. PSPCR, PCCR, PINAER, PCRxy, PFSRxy write enable
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void GPIO_REG_Unlock(void)
|
||||
{
|
||||
WRITE_REG16(CM_GPIO->PWPR, GPIO_REG_UNLOCK_KEY);
|
||||
}
|
||||
|
||||
int32_t GPIO_Init(uint8_t u8Port, uint16_t u16Pin, const stc_gpio_init_t *pstcGpioInit);
|
||||
void GPIO_DeInit(void);
|
||||
int32_t GPIO_StructInit(stc_gpio_init_t *pstcGpioInit);
|
||||
void GPIO_SetDebugPort(uint8_t u8DebugPort, en_functional_state_t enNewState);
|
||||
void GPIO_SetFunc(uint8_t u8Port, uint16_t u16Pin, uint16_t u16Func);
|
||||
void GPIO_SubFuncCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState);
|
||||
void GPIO_SetSubFunc(uint8_t u8Func);
|
||||
void GPIO_SetReadWaitCycle(uint16_t u16ReadWait);
|
||||
void GPIO_InputMOSCmd(uint8_t u8Port, en_functional_state_t enNewState);
|
||||
void GPIO_OutputCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState);
|
||||
en_pin_state_t GPIO_ReadInputPins(uint8_t u8Port, uint16_t u16Pin);
|
||||
uint16_t GPIO_ReadInputPort(uint8_t u8Port);
|
||||
en_pin_state_t GPIO_ReadOutputPins(uint8_t u8Port, uint16_t u16Pin);
|
||||
uint16_t GPIO_ReadOutputPort(uint8_t u8Port);
|
||||
void GPIO_SetPins(uint8_t u8Port, uint16_t u16Pin);
|
||||
void GPIO_ResetPins(uint8_t u8Port, uint16_t u16Pin);
|
||||
void GPIO_WritePort(uint8_t u8Port, uint16_t u16PortVal);
|
||||
void GPIO_TogglePins(uint8_t u8Port, uint16_t u16Pin);
|
||||
void GPIO_ExtIntCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState);
|
||||
void GPIO_AnalogCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_GPIO_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_GPIO_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,95 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_hash.h
|
||||
* @brief This file contains all the functions prototypes of the HASH driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2023-06-30 CDT Add HASH_DeInit function
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_HASH_H__
|
||||
#define __HC32_LL_HASH_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_HASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_HASH_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HASH_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
int32_t HASH_DeInit(void);
|
||||
int32_t HASH_Calculate(const uint8_t *pu8SrcData, uint32_t u32SrcDataSize, uint8_t *pu8MsgDigest);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_HASH_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_HASH_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,327 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_i2c.h
|
||||
* @brief This file contains all the functions prototypes of the Inter-Integrated
|
||||
* Circuit(I2C) driver library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2022-06-30 CDT Add API I2C_SlaveAddrCmd()
|
||||
2023-09-30 CDT Modify typo
|
||||
Move macro define I2C_SRC_CLK to head file
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_I2C_H__
|
||||
#define __HC32_LL_I2C_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_I2C_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup I2C_Global_Types I2C Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief I2c configuration structure
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32ClockDiv; /*!< I2C clock division for i2c source clock */
|
||||
uint32_t u32Baudrate; /*!< I2C baudrate config */
|
||||
uint32_t u32SclTime; /*!< The SCL rising and falling time, count of T(i2c source clock after frequency divider) */
|
||||
} stc_i2c_init_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @defgroup I2C_Global_Macros I2C Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_SRC_CLK (SystemCoreClock >> ((CM_CMU->SCFGR & CMU_SCFGR_PCLK3S) >> CMU_SCFGR_PCLK3S_POS))
|
||||
|
||||
#define I2C_WIDTH_MAX_IMME (68UL)
|
||||
|
||||
/**
|
||||
* @defgroup I2C_Trans_Dir I2C Transfer Direction
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DIR_TX (0x0U)
|
||||
#define I2C_DIR_RX (0x1U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2C_Addr_Config I2C Address Configure
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ADDR_DISABLE (0U)
|
||||
#define I2C_ADDR_7BIT (I2C_SLR0_SLADDR0EN)
|
||||
#define I2C_ADDR_10BIT (I2C_SLR0_ADDRMOD0 | I2C_SLR0_SLADDR0EN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2C_Clock_Division I2C Clock Division
|
||||
* @{
|
||||
*/
|
||||
#define I2C_CLK_DIV1 (0UL) /*!< I2c source clock/1 */
|
||||
#define I2C_CLK_DIV2 (1UL) /*!< I2c source clock/2 */
|
||||
#define I2C_CLK_DIV4 (2UL) /*!< I2c source clock/4 */
|
||||
#define I2C_CLK_DIV8 (3UL) /*!< I2c source clock/8 */
|
||||
#define I2C_CLK_DIV16 (4UL) /*!< I2c source clock/16 */
|
||||
#define I2C_CLK_DIV32 (5UL) /*!< I2c source clock/32 */
|
||||
#define I2C_CLK_DIV64 (6UL) /*!< I2c source clock/64 */
|
||||
#define I2C_CLK_DIV128 (7UL) /*!< I2c source clock/128 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2C_Address_Num I2C Address Number
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ADDR0 (0UL)
|
||||
#define I2C_ADDR1 (1UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2C_Ack_Config I2C ACK Configure
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ACK (0UL) /*!< Send ACK after date receive */
|
||||
#define I2C_NACK (I2C_CR1_ACK) /*!< Send NACK after date received */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2C_Smbus_Match_Config I2C SMBUS Address Match Configure
|
||||
* @{
|
||||
*/
|
||||
#define I2C_SMBUS_MATCH_ALARM (I2C_CR1_SMBALRTEN)
|
||||
#define I2C_SMBUS_MATCH_DEFAULT (I2C_CR1_SMBDEFAULTEN)
|
||||
#define I2C_SMBUS_MATCH_HOST (I2C_CR1_SMBHOSTEN)
|
||||
#define I2C_SMBUS_MATCH_ALL (I2C_CR1_SMBALRTEN | I2C_CR1_SMBDEFAULTEN | I2C_CR1_SMBHOSTEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2C_Digital_Filter_Clock I2C Digital Filter Clock
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DIG_FILTER_CLK_DIV1 (0UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/1 */
|
||||
#define I2C_DIG_FILTER_CLK_DIV2 (1UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/2 */
|
||||
#define I2C_DIG_FILTER_CLK_DIV3 (2UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/3 */
|
||||
#define I2C_DIG_FILTER_CLK_DIV4 (3UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/4 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2C_Flag I2C Flag
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FLAG_START (I2C_SR_STARTF) /*!< Start condition detected */
|
||||
#define I2C_FLAG_MATCH_ADDR0 (I2C_SR_SLADDR0F) /*!< Address 0 detected */
|
||||
#define I2C_FLAG_MATCH_ADDR1 (I2C_SR_SLADDR1F) /*!< Address 1 detected */
|
||||
#define I2C_FLAG_TX_CPLT (I2C_SR_TENDF) /*!< Transfer end */
|
||||
#define I2C_FLAG_STOP (I2C_SR_STOPF) /*!< Stop condition detected */
|
||||
#define I2C_FLAG_RX_FULL (I2C_SR_RFULLF) /*!< Receive buffer full */
|
||||
#define I2C_FLAG_TX_EMPTY (I2C_SR_TEMPTYF) /*!< Transfer buffer empty */
|
||||
#define I2C_FLAG_ARBITRATE_FAIL (I2C_SR_ARLOF) /*!< Arbitration fails */
|
||||
#define I2C_FLAG_ACKR (I2C_SR_ACKRF) /*!< ACK status */
|
||||
#define I2C_FLAG_NACKF (I2C_SR_NACKF) /*!< NACK detected */
|
||||
#define I2C_FLAG_TMOUTF (I2C_SR_TMOUTF) /*!< Time out detected */
|
||||
#define I2C_FLAG_MASTER (I2C_SR_MSL) /*!< Master mode flag */
|
||||
#define I2C_FLAG_BUSY (I2C_SR_BUSY) /*!< Bus busy status */
|
||||
#define I2C_FLAG_TRA (I2C_SR_TRA) /*!< Transfer mode flag */
|
||||
#define I2C_FLAG_GENERAL_CALL (I2C_SR_GENCALLF) /*!< General call detected */
|
||||
#define I2C_FLAG_SMBUS_DEFAULT_MATCH (I2C_SR_SMBDEFAULTF) /*!< SMBUS default address detected */
|
||||
#define I2C_FLAG_SMBUS_HOST_MATCH (I2C_SR_SMBHOSTF) /*!< SMBUS host address detected */
|
||||
#define I2C_FLAG_SMBUS_ALARM_MATCH (I2C_SR_SMBALRTF) /*!< SMBUS alarm address detected */
|
||||
|
||||
#define I2C_FLAG_CLR_ALL (I2C_FLAG_START | I2C_FLAG_MATCH_ADDR0 | I2C_FLAG_MATCH_ADDR1 \
|
||||
| I2C_FLAG_TX_CPLT | I2C_FLAG_STOP | I2C_FLAG_RX_FULL | I2C_FLAG_TX_EMPTY \
|
||||
| I2C_FLAG_ARBITRATE_FAIL | I2C_FLAG_NACKF | I2C_FLAG_TMOUTF \
|
||||
| I2C_FLAG_GENERAL_CALL | I2C_FLAG_SMBUS_DEFAULT_MATCH \
|
||||
| I2C_FLAG_SMBUS_HOST_MATCH | I2C_FLAG_SMBUS_ALARM_MATCH)
|
||||
#define I2C_FLAG_ALL (I2C_FLAG_START | I2C_FLAG_MATCH_ADDR0 | I2C_FLAG_MATCH_ADDR1 | I2C_FLAG_TX_CPLT \
|
||||
| I2C_FLAG_STOP | I2C_FLAG_RX_FULL | I2C_FLAG_TX_EMPTY | I2C_FLAG_ARBITRATE_FAIL\
|
||||
| I2C_FLAG_ACKR | I2C_FLAG_NACKF | I2C_FLAG_TMOUTF | I2C_FLAG_MASTER \
|
||||
| I2C_FLAG_BUSY | I2C_FLAG_TRA | I2C_FLAG_GENERAL_CALL \
|
||||
| I2C_FLAG_SMBUS_DEFAULT_MATCH | I2C_FLAG_SMBUS_HOST_MATCH \
|
||||
| I2C_FLAG_SMBUS_ALARM_MATCH)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2C_Int_Flag I2C Interrupt Flag Bits
|
||||
* @{
|
||||
*/
|
||||
#define I2C_INT_START (I2C_CR2_STARTIE)
|
||||
#define I2C_INT_MATCH_ADDR0 (I2C_CR2_SLADDR0IE)
|
||||
#define I2C_INT_MATCH_ADDR1 (I2C_CR2_SLADDR1IE)
|
||||
#define I2C_INT_TX_CPLT (I2C_CR2_TENDIE)
|
||||
#define I2C_INT_STOP (I2C_CR2_STOPIE)
|
||||
#define I2C_INT_RX_FULL (I2C_CR2_RFULLIE)
|
||||
#define I2C_INT_TX_EMPTY (I2C_CR2_TEMPTYIE)
|
||||
#define I2C_INT_ARBITRATE_FAIL (I2C_CR2_ARLOIE)
|
||||
#define I2C_INT_NACK (I2C_CR2_NACKIE)
|
||||
#define I2C_INT_TMOUTIE (I2C_CR2_TMOUTIE)
|
||||
#define I2C_INT_GENERAL_CALL (I2C_CR2_GENCALLIE)
|
||||
#define I2C_INT_SMBUS_DEFAULT_MATCH (I2C_CR2_SMBDEFAULTIE)
|
||||
#define I2C_INT_SMBUS_HOST_MATCH (I2C_CR2_SMBHOSTIE)
|
||||
#define I2C_INT_SMBUS_ALARM_MATCH (I2C_CR2_SMBALRTIE)
|
||||
|
||||
#define I2C_INT_ALL (I2C_INT_START | I2C_INT_MATCH_ADDR0 | I2C_INT_MATCH_ADDR1 | I2C_INT_TX_CPLT \
|
||||
| I2C_INT_STOP | I2C_INT_RX_FULL | I2C_INT_TX_EMPTY | I2C_INT_ARBITRATE_FAIL \
|
||||
| I2C_INT_NACK | I2C_INT_TMOUTIE | I2C_INT_GENERAL_CALL \
|
||||
| I2C_INT_SMBUS_DEFAULT_MATCH | I2C_INT_SMBUS_HOST_MATCH \
|
||||
| I2C_INT_SMBUS_ALARM_MATCH)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup I2C_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and Configuration **********************************/
|
||||
int32_t I2C_StructInit(stc_i2c_init_t *pstcI2cInit);
|
||||
int32_t I2C_BaudrateConfig(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error);
|
||||
void I2C_DeInit(CM_I2C_TypeDef *I2Cx);
|
||||
int32_t I2C_Init(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error);
|
||||
void I2C_SlaveAddrConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32Addr);
|
||||
void I2C_SlaveAddrCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, en_functional_state_t enNewState);
|
||||
void I2C_Cmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
|
||||
void I2C_FastAckCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
|
||||
void I2C_BusWaitCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
|
||||
|
||||
void I2C_SmbusConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32SmbusConfig, en_functional_state_t enNewState);
|
||||
void I2C_SmbusCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
|
||||
|
||||
void I2C_DigitalFilterConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32FilterClock);
|
||||
void I2C_DigitalFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
|
||||
|
||||
void I2C_AnalogFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
|
||||
|
||||
void I2C_GeneralCallCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
|
||||
void I2C_SWResetCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
|
||||
void I2C_IntCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32IntType, en_functional_state_t enNewState);
|
||||
|
||||
/* Start/Restart/Stop ************************************************/
|
||||
void I2C_GenerateStart(CM_I2C_TypeDef *I2Cx);
|
||||
void I2C_GenerateRestart(CM_I2C_TypeDef *I2Cx);
|
||||
void I2C_GenerateStop(CM_I2C_TypeDef *I2Cx);
|
||||
|
||||
/* Status management *************************************************/
|
||||
en_flag_status_t I2C_GetStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag);
|
||||
void I2C_ClearStatus(CM_I2C_TypeDef *I2Cx, uint32_t u32Flag);
|
||||
|
||||
/* Data transfer *****************************************************/
|
||||
void I2C_WriteData(CM_I2C_TypeDef *I2Cx, uint8_t u8Data);
|
||||
uint8_t I2C_ReadData(const CM_I2C_TypeDef *I2Cx);
|
||||
void I2C_AckConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AckConfig);
|
||||
|
||||
/* Time out function *************************************************/
|
||||
void I2C_SCLHighTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutH);
|
||||
void I2C_SCLLowTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutL);
|
||||
void I2C_SCLHighTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
|
||||
void I2C_SCLLowTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
|
||||
void I2C_SCLTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
|
||||
|
||||
/* High level functions for reference ********************************/
|
||||
int32_t I2C_Start(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout);
|
||||
int32_t I2C_Restart(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout);
|
||||
int32_t I2C_TransAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout);
|
||||
int32_t I2C_Trans10BitAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout);
|
||||
int32_t I2C_TransData(CM_I2C_TypeDef *I2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout);
|
||||
int32_t I2C_ReceiveData(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout);
|
||||
int32_t I2C_MasterReceiveDataAndStop(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout);
|
||||
int32_t I2C_Stop(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout);
|
||||
int32_t I2C_WaitStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_I2C_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_I2C_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,342 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_i2s.h
|
||||
* @brief This file contains all the functions prototypes of the I2S driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_I2S_H__
|
||||
#define __HC32_LL_I2S_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_I2S
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_I2S_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup I2S_Global_Types I2S Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief I2S Init structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32ClockSrc; /*!< Specifies the clock source of I2S.
|
||||
This parameter can be a value of @ref I2S_Clock_Source */
|
||||
uint32_t u32Mode; /*!< Specifies the master/slave mode of I2S.
|
||||
This parameter can be a value of @ref I2S_Mode */
|
||||
uint32_t u32Protocol; /*!< Specifies the communication protocol of I2S.
|
||||
This parameter can be a value of @ref I2S_Protocol */
|
||||
uint32_t u32TransMode; /*!< Specifies the transmission mode for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Trans_Mode */
|
||||
uint32_t u32AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||
uint32_t u32ChWidth; /*!< Specifies the channel length for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Channel_Length */
|
||||
uint32_t u32DataWidth; /*!< Specifies the data length for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Data_Length */
|
||||
uint32_t u32MCKOutput; /*!< Specifies the validity of the MCK output for I2S.
|
||||
This parameter can be a value of @ref I2S_MCK_Output */
|
||||
uint32_t u32TransFIFOLevel; /*!< Specifies the level of transfer FIFO.
|
||||
This parameter can be a value of @ref I2S_Trans_Level */
|
||||
uint32_t u32ReceiveFIFOLevel; /*!< Specifies the level of receive FIFO.
|
||||
This parameter can be a value of @ref I2S_Receive_Level */
|
||||
} stc_i2s_init_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup I2S_Global_Macros I2S Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2S_External_Clock_Frequency I2S External Clock Frequency
|
||||
* @{
|
||||
*/
|
||||
#ifndef I2S_EXT_CLK_FREQ
|
||||
#define I2S_EXT_CLK_FREQ (12288000UL) /*!< Value of the external oscillator */
|
||||
#endif /* I2S_EXT_CLK_FREQ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2S_Clock_Source I2S Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define I2S_CLK_SRC_PLL (I2S_CTRL_I2SPLLSEL) /*!< Internal PLL Clock */
|
||||
#define I2S_CLK_SRC_EXT (I2S_CTRL_CLKSEL) /*!< External Clock */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2S_Mode I2S Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MD_MASTER (0UL) /*!< Master mode */
|
||||
#define I2S_MD_SLAVE (I2S_CTRL_WMS) /*!< Slave mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2S_Protocol I2S Communication Protocol
|
||||
* @{
|
||||
*/
|
||||
#define I2S_PROTOCOL_PHILLIPS (0UL) /*!< Phillips protocol */
|
||||
#define I2S_PROTOCOL_MSB (I2S_CFGR_I2SSTD_0) /*!< MSB justified protocol */
|
||||
#define I2S_PROTOCOL_LSB (I2S_CFGR_I2SSTD_1) /*!< LSB justified protocol */
|
||||
#define I2S_PROTOCOL_PCM_SHORT (I2S_CFGR_I2SSTD) /*!< PCM short-frame protocol */
|
||||
#define I2S_PROTOCOL_PCM_LONG (I2S_CFGR_I2SSTD | I2S_CFGR_PCMSYNC) /*!< PCM long-frame protocol */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2S_Trans_Mode I2S Transfer Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2S_TRANS_MD_HALF_DUPLEX_RX (0UL) /*!< Receive only and half duplex mode */
|
||||
#define I2S_TRANS_MD_HALF_DUPLEX_TX (I2S_CTRL_SDOE) /*!< Send only and half duplex mode */
|
||||
#define I2S_TRANS_MD_FULL_DUPLEX (I2S_CTRL_DUPLEX | I2S_CTRL_SDOE) /*!< Full duplex mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2S_Audio_Frequency I2S Audio Frequency
|
||||
* @{
|
||||
*/
|
||||
#define I2S_AUDIO_FREQ_192K (192000UL) /*!< FS = 192000Hz */
|
||||
#define I2S_AUDIO_FREQ_96K (96000UL) /*!< FS = 96000Hz */
|
||||
#define I2S_AUDIO_FREQ_48K (48000UL) /*!< FS = 48000Hz */
|
||||
#define I2S_AUDIO_FREQ_44K (44100UL) /*!< FS = 44100Hz */
|
||||
#define I2S_AUDIO_FREQ_32K (32000UL) /*!< FS = 32000Hz */
|
||||
#define I2S_AUDIO_FREQ_22K (22050UL) /*!< FS = 22050Hz */
|
||||
#define I2S_AUDIO_FREQ_16K (16000UL) /*!< FS = 16000Hz */
|
||||
#define I2S_AUDIO_FREQ_8K (8000UL) /*!< FS = 8000Hz */
|
||||
#define I2S_AUDIO_FREQ_DEFAULT (2UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2S_Channel_Length I2S Channel Length
|
||||
* @{
|
||||
*/
|
||||
#define I2S_CH_LEN_16BIT (0UL) /*!< Channel length is 16bits */
|
||||
#define I2S_CH_LEN_32BIT (I2S_CFGR_CHLEN) /*!< Channel length is 32bits */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2S_Data_Length I2S Data Length
|
||||
* @{
|
||||
*/
|
||||
#define I2S_DATA_LEN_16BIT (0UL) /*!< Transfer data length is 16bits */
|
||||
#define I2S_DATA_LEN_24BIT (I2S_CFGR_DATLEN_0) /*!< Transfer data length is 24bits */
|
||||
#define I2S_DATA_LEN_32BIT (I2S_CFGR_DATLEN_1) /*!< Transfer data length is 32bits */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2S_MCK_Output I2S MCK Output
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MCK_OUTPUT_DISABLE (0UL) /*!< Disable the drive clock(MCK) output */
|
||||
#define I2S_MCK_OUTPUT_ENABLE (I2S_CTRL_MCKOE) /*!< Enable the drive clock(MCK) output */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2S_Trans_Level I2S Transfer Level
|
||||
* @{
|
||||
*/
|
||||
#define I2S_TRANS_LVL0 (0x00UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 0 */
|
||||
#define I2S_TRANS_LVL1 (0x01UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 1 */
|
||||
#define I2S_TRANS_LVL2 (0x02UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 2 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2S_Receive_Level I2S Receive Level
|
||||
* @{
|
||||
*/
|
||||
#define I2S_RECEIVE_LVL0 (0x00UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 0 */
|
||||
#define I2S_RECEIVE_LVL1 (0x01UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 1 */
|
||||
#define I2S_RECEIVE_LVL2 (0x02UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 2 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2S_Com_Func I2S Communication Function
|
||||
* @{
|
||||
*/
|
||||
#define I2S_FUNC_TX (I2S_CTRL_TXE) /*!< Transfer function */
|
||||
#define I2S_FUNC_RX (I2S_CTRL_RXE) /*!< Receive function */
|
||||
#define I2S_FUNC_ALL (I2S_FUNC_TX | I2S_FUNC_RX)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2S_Reset_Type I2S Reset Type
|
||||
* @{
|
||||
*/
|
||||
#define I2S_RST_TYPE_CODEC (I2S_CTRL_CODECRC) /*!< Reset codec of I2S */
|
||||
#define I2S_RST_TYPE_FIFO (I2S_CTRL_FIFOR) /*!< Reset FIFO of I2S */
|
||||
|
||||
#define I2S_RST_TYPE_ALL (I2S_RST_TYPE_CODEC | I2S_RST_TYPE_FIFO)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2S_Interrupt I2S Interrupt
|
||||
* @{
|
||||
*/
|
||||
#define I2S_INT_TX (I2S_CTRL_TXIE) /*!< Transfer interrupt */
|
||||
#define I2S_INT_RX (I2S_CTRL_RXIE) /*!< Receive interrupt */
|
||||
#define I2S_INT_ERR (I2S_CTRL_EIE) /*!< Communication error interrupt */
|
||||
#define I2S_INT_ALL (I2S_INT_TX | I2S_INT_RX | I2S_INT_ERR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup I2S_Flag I2S Flag
|
||||
* @{
|
||||
*/
|
||||
#define I2S_FLAG_TX_ALARM (I2S_SR_TXBA) /*!< Transfer buffer alarm flag */
|
||||
#define I2S_FLAG_RX_ALARM (I2S_SR_RXBA) /*!< Receive buffer alarm flag */
|
||||
#define I2S_FLAG_TX_EMPTY (I2S_SR_TXBE) /*!< Transfer buffer empty flag */
|
||||
#define I2S_FLAG_TX_FULL (I2S_SR_TXBF) /*!< Transfer buffer full flag */
|
||||
#define I2S_FLAG_RX_EMPTY (I2S_SR_RXBE) /*!< Receive buffer empty flag */
|
||||
#define I2S_FLAG_RX_FULL (I2S_SR_RXBF) /*!< Receive buffer full flag */
|
||||
#define I2S_FLAG_TX_ERR (I2S_ER_TXERR << 16U) /*!< Transfer overflow or underflow flag */
|
||||
#define I2S_FLAG_RX_ERR (I2S_ER_RXERR << 16U) /*!< Receive overflow flag */
|
||||
#define I2S_FLAG_ALL (I2S_FLAG_TX_ALARM | I2S_FLAG_RX_ALARM | I2S_FLAG_TX_EMPTY | \
|
||||
I2S_FLAG_TX_FULL | I2S_FLAG_RX_EMPTY | I2S_FLAG_RX_FULL | \
|
||||
I2S_FLAG_TX_ERR | I2S_FLAG_RX_ERR)
|
||||
#define I2S_FLAG_CLR_ALL (I2S_FLAG_TX_ERR | I2S_FLAG_RX_ERR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup I2S_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and configuration functions */
|
||||
void I2S_DeInit(CM_I2S_TypeDef *I2Sx);
|
||||
int32_t I2S_Init(CM_I2S_TypeDef *I2Sx, const stc_i2s_init_t *pstcI2sInit);
|
||||
int32_t I2S_StructInit(stc_i2s_init_t *pstcI2sInit);
|
||||
void I2S_SWReset(CM_I2S_TypeDef *I2Sx, uint32_t u32Type);
|
||||
void I2S_SetTransMode(CM_I2S_TypeDef *I2Sx, uint32_t u32Mode);
|
||||
void I2S_SetTransFIFOLevel(CM_I2S_TypeDef *I2Sx, uint32_t u32Level);
|
||||
void I2S_SetReceiveFIFOLevel(CM_I2S_TypeDef *I2Sx, uint32_t u32Level);
|
||||
void I2S_SetProtocol(CM_I2S_TypeDef *I2Sx, uint32_t u32Protocol);
|
||||
int32_t I2S_SetAudioFreq(CM_I2S_TypeDef *I2Sx, uint32_t u32Freq);
|
||||
void I2S_MCKOutputCmd(CM_I2S_TypeDef *I2Sx, en_functional_state_t enNewState);
|
||||
void I2S_FuncCmd(CM_I2S_TypeDef *I2Sx, uint32_t u32Func, en_functional_state_t enNewState);
|
||||
|
||||
/* Transfer and receive data functions */
|
||||
void I2S_WriteData(CM_I2S_TypeDef *I2Sx, uint32_t u32Data);
|
||||
uint32_t I2S_ReadData(const CM_I2S_TypeDef *I2Sx);
|
||||
int32_t I2S_Trans(CM_I2S_TypeDef *I2Sx, const void *pvTxBuf, uint32_t u32Len, uint32_t u32Timeout);
|
||||
int32_t I2S_Receive(const CM_I2S_TypeDef *I2Sx, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout);
|
||||
int32_t I2S_TransReceive(CM_I2S_TypeDef *I2Sx, const void *pvTxBuf,
|
||||
void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout);
|
||||
|
||||
/* Interrupt and flag management functions */
|
||||
void I2S_IntCmd(CM_I2S_TypeDef *I2Sx, uint32_t u32IntType, en_functional_state_t enNewState);
|
||||
en_flag_status_t I2S_GetStatus(const CM_I2S_TypeDef *I2Sx, uint32_t u32Flag);
|
||||
void I2S_ClearStatus(CM_I2S_TypeDef *I2Sx, uint32_t u32Flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_I2S_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_I2S_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,469 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_icg.h
|
||||
* @brief This file contains all the Macro Definitions of the ICG driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_ICG_H__
|
||||
#define __HC32_LL_ICG_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_ICG
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_ICG_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup ICG_Global_Macros ICG Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_SWDT_Reset_State ICG SWDT Reset State
|
||||
* @{
|
||||
*/
|
||||
#define ICG_SWDT_RST_START (0UL) /*!< SWDT auto start after reset */
|
||||
#define ICG_SWDT_RST_STOP (ICG_ICG0_SWDTAUTS) /*!< SWDT stop after reset */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_SWDT_Exception_Type ICG SWDT Exception Type
|
||||
* @{
|
||||
*/
|
||||
#define ICG_SWDT_EXP_TYPE_INT (0UL) /*!< SWDT trigger interrupt */
|
||||
#define ICG_SWDT_EXP_TYPE_RST (ICG_ICG0_SWDTITS) /*!< SWDT trigger reset */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_SWDT_Count_Period ICG SWDT Count Period
|
||||
* @{
|
||||
*/
|
||||
#define ICG_SWDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */
|
||||
#define ICG_SWDT_CNT_PERIOD4096 (ICG_ICG0_SWDTPERI_0) /*!< 4096 clock cycle */
|
||||
#define ICG_SWDT_CNT_PERIOD16384 (ICG_ICG0_SWDTPERI_1) /*!< 16384 clock cycle */
|
||||
#define ICG_SWDT_CNT_PERIOD65536 (ICG_ICG0_SWDTPERI) /*!< 65536 clock cycle */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_SWDT_Clock_Division ICG SWDT Clock Division
|
||||
* @{
|
||||
*/
|
||||
#define ICG_SWDT_CLK_DIV1 (0UL) /*!< CLK */
|
||||
#define ICG_SWDT_CLK_DIV16 (0x04UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/16 */
|
||||
#define ICG_SWDT_CLK_DIV32 (0x05UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/32 */
|
||||
#define ICG_SWDT_CLK_DIV64 (0x06UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/64 */
|
||||
#define ICG_SWDT_CLK_DIV128 (0x07UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/128 */
|
||||
#define ICG_SWDT_CLK_DIV256 (0x08UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/256 */
|
||||
#define ICG_SWDT_CLK_DIV2048 (0x0BUL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/2048 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_SWDT_Refresh_Range ICG SWDT Refresh Range
|
||||
* @{
|
||||
*/
|
||||
#define ICG_SWDT_RANGE_0TO25PCT (0x01UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% */
|
||||
#define ICG_SWDT_RANGE_25TO50PCT (0x02UL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~50% */
|
||||
#define ICG_SWDT_RANGE_0TO50PCT (0x03UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~50% */
|
||||
#define ICG_SWDT_RANGE_50TO75PCT (0x04UL << ICG_ICG0_SWDTWDPT_POS) /*!< 50%~75% */
|
||||
#define ICG_SWDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 50%~75% */
|
||||
#define ICG_SWDT_RANGE_25TO75PCT (0x06UL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~75% */
|
||||
#define ICG_SWDT_RANGE_0TO75PCT (0x07UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~75% */
|
||||
#define ICG_SWDT_RANGE_75TO100PCT (0x08UL << ICG_ICG0_SWDTWDPT_POS) /*!< 75%~100% */
|
||||
#define ICG_SWDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 75%~100% */
|
||||
#define ICG_SWDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~50% & 75%~100% */
|
||||
#define ICG_SWDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~50% & 75%~100% */
|
||||
#define ICG_SWDT_RANGE_50TO100PCT (0x0CUL << ICG_ICG0_SWDTWDPT_POS) /*!< 50%~100% */
|
||||
#define ICG_SWDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 50%~100% */
|
||||
#define ICG_SWDT_RANGE_25TO100PCT (0x0EUL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~100% */
|
||||
#define ICG_SWDT_RANGE_0TO100PCT (0x0FUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~100% */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_SWDT_LPM_Count ICG SWDT Low Power Mode Count
|
||||
* @brief Counting control of SWDT in sleep/stop mode
|
||||
* @{
|
||||
*/
|
||||
#define ICG_SWDT_LPM_CNT_CONTINUE (0UL) /*!< Continue counting in sleep/stop mode */
|
||||
#define ICG_SWDT_LPM_CNT_STOP (ICG_ICG0_SWDTSLPOFF) /*!< Stop counting in sleep/stop mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_WDT_Reset_State ICG WDT Reset State
|
||||
* @{
|
||||
*/
|
||||
#define ICG_WDT_RST_START (0UL) /*!< WDT auto start after reset */
|
||||
#define ICG_WDT_RST_STOP (ICG_ICG0_WDTAUTS) /*!< WDT stop after reset */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_WDT_Exception_Type ICG WDT Exception Type
|
||||
* @{
|
||||
*/
|
||||
#define ICG_WDT_EXP_TYPE_INT (0UL) /*!< WDT trigger interrupt */
|
||||
#define ICG_WDT_EXP_TYPE_RST (ICG_ICG0_WDTITS) /*!< WDT trigger reset */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_WDT_Count_Period ICG WDT Count Period
|
||||
* @{
|
||||
*/
|
||||
#define REDEF_ICG_WDTPERI_POS ICG_ICG0_WDTPERI_POS
|
||||
|
||||
#define ICG_WDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */
|
||||
#define ICG_WDT_CNT_PERIOD4096 (0x01UL << REDEF_ICG_WDTPERI_POS) /*!< 4096 clock cycle */
|
||||
#define ICG_WDT_CNT_PERIOD16384 (0x02UL << REDEF_ICG_WDTPERI_POS) /*!< 16384 clock cycle */
|
||||
#define ICG_WDT_CNT_PERIOD65536 (0x03UL << REDEF_ICG_WDTPERI_POS) /*!< 65536 clock cycle */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_WDT_Clock_Division ICG WDT Clock Division
|
||||
* @{
|
||||
*/
|
||||
#define REDEF_ICG_WDTCKS_POS ICG_ICG0_WDTCKS_POS
|
||||
|
||||
#define ICG_WDT_CLK_DIV4 (0x02UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/4 */
|
||||
#define ICG_WDT_CLK_DIV64 (0x06UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/64 */
|
||||
#define ICG_WDT_CLK_DIV128 (0x07UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/128 */
|
||||
#define ICG_WDT_CLK_DIV256 (0x08UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/256 */
|
||||
#define ICG_WDT_CLK_DIV512 (0x09UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/512 */
|
||||
#define ICG_WDT_CLK_DIV1024 (0x0AUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/1024 */
|
||||
#define ICG_WDT_CLK_DIV2048 (0x0BUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/2048 */
|
||||
#define ICG_WDT_CLK_DIV8192 (0x0DUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/8192 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_WDT_Refresh_Range ICG WDT Refresh Range
|
||||
* @{
|
||||
*/
|
||||
#define REDEF_ICG_WDTWDPT_POS ICG_ICG0_WDTWDPT_POS
|
||||
|
||||
#define ICG_WDT_RANGE_0TO25PCT (0x01UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% */
|
||||
#define ICG_WDT_RANGE_25TO50PCT (0x02UL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~50% */
|
||||
#define ICG_WDT_RANGE_0TO50PCT (0x03UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~50% */
|
||||
#define ICG_WDT_RANGE_50TO75PCT (0x04UL << REDEF_ICG_WDTWDPT_POS) /*!< 50%~75% */
|
||||
#define ICG_WDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 50%~75% */
|
||||
#define ICG_WDT_RANGE_25TO75PCT (0x06UL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~75% */
|
||||
#define ICG_WDT_RANGE_0TO75PCT (0x07UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~75% */
|
||||
#define ICG_WDT_RANGE_75TO100PCT (0x08UL << REDEF_ICG_WDTWDPT_POS) /*!< 75%~100% */
|
||||
#define ICG_WDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 75%~100% */
|
||||
#define ICG_WDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~50% & 75%~100% */
|
||||
#define ICG_WDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~50% & 75%~100% */
|
||||
#define ICG_WDT_RANGE_50TO100PCT (0x0CUL << REDEF_ICG_WDTWDPT_POS) /*!< 50%~100% */
|
||||
#define ICG_WDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 50%~100% */
|
||||
#define ICG_WDT_RANGE_25TO100PCT (0x0EUL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~100% */
|
||||
#define ICG_WDT_RANGE_0TO100PCT (0x0FUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~100% */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_WDT_LPM_Count ICG WDT Low Power Mode Count
|
||||
* @brief Counting control of WDT in sleep mode
|
||||
* @{
|
||||
*/
|
||||
#define ICG_WDT_LPM_CNT_CONTINUE (0UL) /*!< Continue counting in sleep mode */
|
||||
#define ICG_WDT_LPM_CNT_STOP (ICG_ICG0_WDTSLPOFF) /*!< Stop counting in sleep mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_NMI_Pin_Filter_Clock_Division ICG NMI Pin Filter Clock Division
|
||||
* @{
|
||||
*/
|
||||
#define REDEF_ICG_NMIFCLK_POS ICG_ICG1_SMPCLK_POS
|
||||
|
||||
#define ICG_NMI_PIN_FILTER_CLK_DIV1 (0UL) /*!< CLK */
|
||||
#define ICG_NMI_PIN_FILTER_CLK_DIV8 (0x01UL << REDEF_ICG_NMIFCLK_POS) /*!< CLK/8 */
|
||||
#define ICG_NMI_PIN_FILTER_CLK_DIV32 (0x02UL << REDEF_ICG_NMIFCLK_POS) /*!< CLK/32 */
|
||||
#define ICG_NMI_PIN_FILTER_CLK_DIV64 (0x03UL << REDEF_ICG_NMIFCLK_POS) /*!< CLK/64 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_NMI_Pin_Filter ICG NMI Pin Filter
|
||||
* @{
|
||||
*/
|
||||
#define ICG_NMI_PIN_FILTER_DISABLE (0UL) /*!< Disable NMI Pin filter */
|
||||
#define ICG_NMI_PIN_FILTER_ENABLE (ICG_ICG1_NFEN) /*!< Enable NMI Pin filter */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_NMI_Pin_Trigger_Edge ICG NMI Pin Trigger Edge
|
||||
* @{
|
||||
*/
|
||||
#define ICG_NMI_PIN_TRIG_EDGE_FALLING (0UL) /*!< Falling edge trigger */
|
||||
#define ICG_NMI_PIN_TRIG_EDGE_RISING (ICG_ICG1_NMITRG) /*!< Rising edge trigger */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_NMI_Pin_Interrupt ICG NMI Pin Interrupt
|
||||
* @{
|
||||
*/
|
||||
#define ICG_NMI_PIN_INT_DISABLE (0UL) /*!< Disable NMI pin interrupt */
|
||||
#define ICG_NMI_PIN_INT_ENABLE (ICG_ICG1_NMIEN) /*!< Enable NMI pin interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_NMI_Pin_Reset_State ICG NMI Pin Reset State
|
||||
* @{
|
||||
*/
|
||||
#define ICG_NMI_PIN_RST_ENABLE (0UL) /*!< Enable NMI pin after reset */
|
||||
#define ICG_NMI_PIN_RST_DISABLE (ICG_ICG1_NMIICGEN) /*!< Disable NMI pin after reset */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_BOR_Voltage_Threshold ICG BOR Voltage Threshold
|
||||
* @{
|
||||
*/
|
||||
#define ICG_BOR_VOL_THRESHOLD_LVL0 (0UL) /*!< BOR voltage threshold 1.9V */
|
||||
#define ICG_BOR_VOL_THRESHOLD_LVL1 (ICG_ICG1_BOR_LEV_0) /*!< BOR voltage threshold 2.0V */
|
||||
#define ICG_BOR_VOL_THRESHOLD_LVL2 (ICG_ICG1_BOR_LEV_1) /*!< BOR voltage threshold 2.1V */
|
||||
#define ICG_BOR_VOL_THRESHOLD_LVL3 (ICG_ICG1_BOR_LEV) /*!< BOR voltage threshold 2.3V */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_BOR_Reset_State ICG BOR Reset State
|
||||
* @{
|
||||
*/
|
||||
#define ICG_BOR_RST_ENABLE (0UL) /*!< Enable BOR voltage detection after reset */
|
||||
#define ICG_BOR_RST_DISABLE (ICG_ICG1_BORDIS) /*!< Disable BOR voltage detection after reset */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_HRC_Frequency_Select ICG HRC Frequency Select
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ICG_HRC_20M (0UL) /*!< HRC = 20MHZ */
|
||||
#define ICG_HRC_16M (ICG_ICG1_HRCFREQSEL) /*!< HRC = 16MHZ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_HRC_Reset_State ICG HRC Reset State
|
||||
* @{
|
||||
*/
|
||||
#define ICG_HRC_RST_OSCILLATION (0UL) /*!< HRC Oscillation after reset */
|
||||
#define ICG_HRC_RST_STOP (ICG_ICG1_HRCSTOP) /*!< HRC stop after reset */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_Register_Configuration ICG Register Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_SWDT_Preload_Configuration ICG SWDT Preload Configuration
|
||||
* @{
|
||||
*/
|
||||
/* SWDT register config */
|
||||
#define ICG_RB_SWDT_AUTS (ICG_SWDT_RST_START)
|
||||
#define ICG_RB_SWDT_ITS (ICG_SWDT_EXP_TYPE_RST)
|
||||
#define ICG_RB_SWDT_PERI (ICG_SWDT_CNT_PERIOD16384)
|
||||
#define ICG_RB_SWDT_CKS (ICG_SWDT_CLK_DIV1)
|
||||
#define ICG_RB_SWDT_WDPT (ICG_SWDT_RANGE_0TO100PCT)
|
||||
#define ICG_RB_SWDT_SLTPOFF (ICG_SWDT_LPM_CNT_STOP)
|
||||
|
||||
/* SWDT register value */
|
||||
#define ICG_REG_SWDT_CONFIG (ICG_RB_SWDT_AUTS | ICG_RB_SWDT_ITS | ICG_RB_SWDT_PERI | \
|
||||
ICG_RB_SWDT_CKS | ICG_RB_SWDT_WDPT | ICG_RB_SWDT_SLTPOFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_WDT_Preload_Configuration ICG WDT Preload Configuration
|
||||
* @{
|
||||
*/
|
||||
/* WDT register config */
|
||||
#define ICG_RB_WDT_AUTS (ICG_WDT_RST_STOP)
|
||||
#define ICG_RB_WDT_ITS (ICG_WDT_EXP_TYPE_RST)
|
||||
#define ICG_RB_WDT_PERI (ICG_WDT_CNT_PERIOD65536)
|
||||
#define ICG_RB_WDT_CKS (ICG_WDT_CLK_DIV8192)
|
||||
#define ICG_RB_WDT_WDPT (ICG_WDT_RANGE_0TO100PCT)
|
||||
#define ICG_RB_WDT_SLTPOFF (ICG_WDT_LPM_CNT_STOP)
|
||||
|
||||
/* WDT register value */
|
||||
#define ICG_REG_WDT_CONFIG (ICG_RB_WDT_AUTS | ICG_RB_WDT_ITS | ICG_RB_WDT_PERI | \
|
||||
ICG_RB_WDT_CKS | ICG_RB_WDT_WDPT | ICG_RB_WDT_SLTPOFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_NMI_Pin_Preload_Configuration ICG NMI Pin Preload Configuration
|
||||
* @{
|
||||
*/
|
||||
/* NMI register config */
|
||||
#define ICG_RB_NMI_FCLK (ICG_NMI_PIN_FILTER_CLK_DIV64)
|
||||
#define ICG_RB_NMI_FEN (ICG_NMI_PIN_FILTER_ENABLE)
|
||||
#define ICG_RB_NMI_TRG (ICG_NMI_PIN_TRIG_EDGE_RISING)
|
||||
#define ICG_RB_NMI_EN (ICG_NMI_PIN_INT_ENABLE)
|
||||
#define ICG_RB_NMI_ICGEN (ICG_NMI_PIN_RST_DISABLE)
|
||||
|
||||
/* NMI register value */
|
||||
#define ICG_REG_NMI_CONFIG (ICG_RB_NMI_FCLK | ICG_RB_NMI_FEN | ICG_RB_NMI_TRG | \
|
||||
ICG_RB_NMI_EN | ICG_RB_NMI_ICGEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_BOR_Preload_Configuration ICG BOR Preload Configuration
|
||||
* @{
|
||||
*/
|
||||
/* BOR register config */
|
||||
#define ICG_RB_BOR_LEV (ICG_BOR_VOL_THRESHOLD_LVL3)
|
||||
#define ICG_RB_BOR_DIS (ICG_BOR_RST_DISABLE)
|
||||
|
||||
/* BOR register value */
|
||||
#define ICG_REG_BOR_CONFIG (ICG_RB_BOR_LEV | ICG_RB_BOR_DIS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_HRC_Preload_Configuration ICG HRC Preload Configuration
|
||||
* @{
|
||||
*/
|
||||
/* HRC register config */
|
||||
#define ICG_RB_HRC_FREQSEL (ICG_HRC_16M)
|
||||
#define ICG_RB_HRC_STOP (ICG_HRC_RST_OSCILLATION)
|
||||
|
||||
/* HRC register value */
|
||||
#define ICG_REG_HRC_CONFIG (ICG_RB_HRC_FREQSEL | ICG_RB_HRC_STOP)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ICG_Register_Value ICG Register Value
|
||||
* @{
|
||||
*/
|
||||
/* ICG register value */
|
||||
#ifndef ICG_REG_CFG0_CONST
|
||||
#define ICG_REG_CFG0_CONST (ICG_REG_WDT_CONFIG | ICG_REG_SWDT_CONFIG | 0xE000E000UL)
|
||||
#endif
|
||||
#ifndef ICG_REG_CFG1_CONST
|
||||
#define ICG_REG_CFG1_CONST (ICG_REG_NMI_CONFIG | ICG_REG_BOR_CONFIG | ICG_REG_HRC_CONFIG | 0x03F8FEFEUL)
|
||||
#endif
|
||||
/* ICG reserved value */
|
||||
#define ICG_REG_RESV_CONST (0xFFFFFFFFUL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
#endif /* LL_ICG_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_ICG_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,592 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_interrupts.h
|
||||
* @brief This file contains all the functions prototypes of the interrupt driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_INTERRUPTS_H__
|
||||
#define __HC32_LL_INTERRUPTS_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_INTERRUPTS
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_INTERRUPTS_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup INTC_Global_Types INTC Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Interrupt registration structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
en_int_src_t enIntSrc; /*!< Peripheral interrupt number, can be any value @ref en_int_src_t */
|
||||
IRQn_Type enIRQn; /*!< Peripheral IRQ type, can be INT000_IRQn~INT127_IRQn @ref IRQn_Type */
|
||||
func_ptr_t pfnCallback; /*!< Callback function for corresponding peripheral IRQ */
|
||||
} stc_irq_signin_config_t;
|
||||
|
||||
/**
|
||||
* @brief NMI initialize configuration structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32Src; /*!< NMI trigger source, @ref NMI_TriggerSrc_Sel for details */
|
||||
uint32_t u32Edge; /*!< NMI pin trigger edge, @ref NMI_Trigger_level_Sel for details */
|
||||
uint32_t u32Filter; /*!< NMI filter function setting, @ref NMI_FilterClock_Sel for details */
|
||||
uint32_t u32FilterClock; /*!< NMI filter clock division, @ref NMI_FilterClock_Div for details */
|
||||
} stc_nmi_init_t;
|
||||
|
||||
/**
|
||||
* @brief EXTINT initialize configuration structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32Filter; /*!< ExtInt filter (A) function setting, @ref EXTINT_FilterClock_Sel for details */
|
||||
uint32_t u32FilterClock; /*!< ExtInt filter (A) clock division, @ref EXTINT_FilterClock_Div for details */
|
||||
uint32_t u32Edge; /*!< ExtInt trigger edge, @ref EXTINT_Trigger_Sel for details */
|
||||
} stc_extint_init_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup INTC_Global_Macros INTC Global Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @defgroup INTC_Priority_Sel Interrupt Priority Level 00 ~ 15
|
||||
* @{
|
||||
*/
|
||||
#define DDL_IRQ_PRIO_00 (0U)
|
||||
#define DDL_IRQ_PRIO_01 (1U)
|
||||
#define DDL_IRQ_PRIO_02 (2U)
|
||||
#define DDL_IRQ_PRIO_03 (3U)
|
||||
#define DDL_IRQ_PRIO_04 (4U)
|
||||
#define DDL_IRQ_PRIO_05 (5U)
|
||||
#define DDL_IRQ_PRIO_06 (6U)
|
||||
#define DDL_IRQ_PRIO_07 (7U)
|
||||
#define DDL_IRQ_PRIO_08 (8U)
|
||||
#define DDL_IRQ_PRIO_09 (9U)
|
||||
#define DDL_IRQ_PRIO_10 (10U)
|
||||
#define DDL_IRQ_PRIO_11 (11U)
|
||||
#define DDL_IRQ_PRIO_12 (12U)
|
||||
#define DDL_IRQ_PRIO_13 (13U)
|
||||
#define DDL_IRQ_PRIO_14 (14U)
|
||||
#define DDL_IRQ_PRIO_15 (15U)
|
||||
|
||||
#define DDL_IRQ_PRIO_DEFAULT (DDL_IRQ_PRIO_15)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup NMI_TriggerSrc_Sel NMI Trigger Source Selection
|
||||
* @{
|
||||
*/
|
||||
#define NMI_SRC_PIN (INTC_NMIFR_NMIFR)
|
||||
#define NMI_SRC_SWDT (INTC_NMIFR_SWDTFR)
|
||||
#define NMI_SRC_LVD1 (INTC_NMIFR_PVD1FR)
|
||||
#define NMI_SRC_LVD2 (INTC_NMIFR_PVD2FR)
|
||||
#define NMI_SRC_XTAL (INTC_NMIFR_XTALSTPFR)
|
||||
#define NMI_SRC_SRAM_PARITY (INTC_NMIFR_REPFR)
|
||||
#define NMI_SRC_SRAM_ECC (INTC_NMIFR_RECCFR)
|
||||
#define NMI_SRC_BUS_ERR (INTC_NMIFR_BUSMFR)
|
||||
#define NMI_SRC_WDT (INTC_NMIFR_WDTFR)
|
||||
#define NMI_SRC_ALL (NMI_SRC_PIN | NMI_SRC_SWDT | NMI_SRC_LVD1 | \
|
||||
NMI_SRC_LVD2 | NMI_SRC_XTAL | NMI_SRC_BUS_ERR | \
|
||||
NMI_SRC_SRAM_PARITY | NMI_SRC_WDT | NMI_SRC_SRAM_ECC)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup NMI_Trigger_level_Sel NMI Pin Trigger Edge Selection
|
||||
* @{
|
||||
*/
|
||||
#define NMI_TRIG_FALLING (0UL)
|
||||
#define NMI_TRIG_RISING (INTC_NMICR_NMITRG)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup NMI_FilterClock_Sel NMI Pin Filter Selection
|
||||
* @{
|
||||
*/
|
||||
#define NMI_FILTER_OFF (0UL)
|
||||
#define NMI_FILTER_ON (INTC_NMICR_NFEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup NMI_FilterClock_Div NMI Pin Filter Sampling Clock Division Selection
|
||||
* @{
|
||||
*/
|
||||
#define NMI_FCLK_DIV1 (0UL << INTC_NMICR_NSMPCLK_POS)
|
||||
#define NMI_FCLK_DIV8 (1UL << INTC_NMICR_NSMPCLK_POS)
|
||||
#define NMI_FCLK_DIV32 (2UL << INTC_NMICR_NSMPCLK_POS)
|
||||
#define NMI_FCLK_DIV64 (3UL << INTC_NMICR_NSMPCLK_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXTINT_Channel_Sel External Interrupt Channel Selection
|
||||
* @{
|
||||
*/
|
||||
#define EXTINT_CH00 (1UL << 0U)
|
||||
#define EXTINT_CH01 (1UL << 1U)
|
||||
#define EXTINT_CH02 (1UL << 2U)
|
||||
#define EXTINT_CH03 (1UL << 3U)
|
||||
#define EXTINT_CH04 (1UL << 4U)
|
||||
#define EXTINT_CH05 (1UL << 5U)
|
||||
#define EXTINT_CH06 (1UL << 6U)
|
||||
#define EXTINT_CH07 (1UL << 7U)
|
||||
#define EXTINT_CH08 (1UL << 8U)
|
||||
#define EXTINT_CH09 (1UL << 9U)
|
||||
#define EXTINT_CH10 (1UL <<10U)
|
||||
#define EXTINT_CH11 (1UL <<11U)
|
||||
#define EXTINT_CH12 (1UL <<12U)
|
||||
#define EXTINT_CH13 (1UL <<13U)
|
||||
#define EXTINT_CH14 (1UL <<14U)
|
||||
#define EXTINT_CH15 (1UL <<15U)
|
||||
#define EXTINT_CH_ALL (EXTINT_CH00 | EXTINT_CH01 | EXTINT_CH02 | EXTINT_CH03 | \
|
||||
EXTINT_CH04 | EXTINT_CH05 | EXTINT_CH06 | EXTINT_CH07 | \
|
||||
EXTINT_CH08 | EXTINT_CH09 | EXTINT_CH10 | EXTINT_CH11 | \
|
||||
EXTINT_CH12 | EXTINT_CH13 | EXTINT_CH14 | EXTINT_CH15)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup INT_Channel_Sel Interrupt Channel Selection
|
||||
* @{
|
||||
*/
|
||||
#define INTC_INT0 INTC_IER_IER0
|
||||
#define INTC_INT1 INTC_IER_IER1
|
||||
#define INTC_INT2 INTC_IER_IER2
|
||||
#define INTC_INT3 INTC_IER_IER3
|
||||
#define INTC_INT4 INTC_IER_IER4
|
||||
#define INTC_INT5 INTC_IER_IER5
|
||||
#define INTC_INT6 INTC_IER_IER6
|
||||
#define INTC_INT7 INTC_IER_IER7
|
||||
#define INTC_INT8 INTC_IER_IER8
|
||||
#define INTC_INT9 INTC_IER_IER9
|
||||
#define INTC_INT10 INTC_IER_IER10
|
||||
#define INTC_INT11 INTC_IER_IER11
|
||||
#define INTC_INT12 INTC_IER_IER12
|
||||
#define INTC_INT13 INTC_IER_IER13
|
||||
#define INTC_INT14 INTC_IER_IER14
|
||||
#define INTC_INT15 INTC_IER_IER15
|
||||
#define INTC_INT16 INTC_IER_IER16
|
||||
#define INTC_INT17 INTC_IER_IER17
|
||||
#define INTC_INT18 INTC_IER_IER18
|
||||
#define INTC_INT19 INTC_IER_IER19
|
||||
#define INTC_INT20 INTC_IER_IER20
|
||||
#define INTC_INT21 INTC_IER_IER21
|
||||
#define INTC_INT22 INTC_IER_IER22
|
||||
#define INTC_INT23 INTC_IER_IER23
|
||||
#define INTC_INT24 INTC_IER_IER24
|
||||
#define INTC_INT25 INTC_IER_IER25
|
||||
#define INTC_INT26 INTC_IER_IER26
|
||||
#define INTC_INT27 INTC_IER_IER27
|
||||
#define INTC_INT28 INTC_IER_IER28
|
||||
#define INTC_INT29 INTC_IER_IER29
|
||||
#define INTC_INT30 INTC_IER_IER30
|
||||
#define INTC_INT31 INTC_IER_IER31
|
||||
#define INTC_INT_ALL (0xFFFFFFFFUL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup INTC_Event_Channel_Sel Event Channel Selection
|
||||
* @{
|
||||
*/
|
||||
#define INTC_EVT0 INTC_EVTER_EVTE0
|
||||
#define INTC_EVT1 INTC_EVTER_EVTE1
|
||||
#define INTC_EVT2 INTC_EVTER_EVTE2
|
||||
#define INTC_EVT3 INTC_EVTER_EVTE3
|
||||
#define INTC_EVT4 INTC_EVTER_EVTE4
|
||||
#define INTC_EVT5 INTC_EVTER_EVTE5
|
||||
#define INTC_EVT6 INTC_EVTER_EVTE6
|
||||
#define INTC_EVT7 INTC_EVTER_EVTE7
|
||||
#define INTC_EVT8 INTC_EVTER_EVTE8
|
||||
#define INTC_EVT9 INTC_EVTER_EVTE9
|
||||
#define INTC_EVT10 INTC_EVTER_EVTE10
|
||||
#define INTC_EVT11 INTC_EVTER_EVTE11
|
||||
#define INTC_EVT12 INTC_EVTER_EVTE12
|
||||
#define INTC_EVT13 INTC_EVTER_EVTE13
|
||||
#define INTC_EVT14 INTC_EVTER_EVTE14
|
||||
#define INTC_EVT15 INTC_EVTER_EVTE15
|
||||
#define INTC_EVT16 INTC_EVTER_EVTE16
|
||||
#define INTC_EVT17 INTC_EVTER_EVTE17
|
||||
#define INTC_EVT18 INTC_EVTER_EVTE18
|
||||
#define INTC_EVT19 INTC_EVTER_EVTE19
|
||||
#define INTC_EVT20 INTC_EVTER_EVTE20
|
||||
#define INTC_EVT21 INTC_EVTER_EVTE21
|
||||
#define INTC_EVT22 INTC_EVTER_EVTE22
|
||||
#define INTC_EVT23 INTC_EVTER_EVTE23
|
||||
#define INTC_EVT24 INTC_EVTER_EVTE24
|
||||
#define INTC_EVT25 INTC_EVTER_EVTE25
|
||||
#define INTC_EVT26 INTC_EVTER_EVTE26
|
||||
#define INTC_EVT27 INTC_EVTER_EVTE27
|
||||
#define INTC_EVT28 INTC_EVTER_EVTE28
|
||||
#define INTC_EVT29 INTC_EVTER_EVTE29
|
||||
#define INTC_EVT30 INTC_EVTER_EVTE30
|
||||
#define INTC_EVT31 INTC_EVTER_EVTE31
|
||||
#define INTC_EVT_ALL (0xFFFFFFFFUL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SWINT_Channel_Sel Software Interrupt Channel Selection
|
||||
* @{
|
||||
*/
|
||||
#define SWINT_CH00 INTC_SWIER_SWIE0
|
||||
#define SWINT_CH01 INTC_SWIER_SWIE1
|
||||
#define SWINT_CH02 INTC_SWIER_SWIE2
|
||||
#define SWINT_CH03 INTC_SWIER_SWIE3
|
||||
#define SWINT_CH04 INTC_SWIER_SWIE4
|
||||
#define SWINT_CH05 INTC_SWIER_SWIE5
|
||||
#define SWINT_CH06 INTC_SWIER_SWIE6
|
||||
#define SWINT_CH07 INTC_SWIER_SWIE7
|
||||
#define SWINT_CH08 INTC_SWIER_SWIE8
|
||||
#define SWINT_CH09 INTC_SWIER_SWIE9
|
||||
#define SWINT_CH10 INTC_SWIER_SWIE10
|
||||
#define SWINT_CH11 INTC_SWIER_SWIE11
|
||||
#define SWINT_CH12 INTC_SWIER_SWIE12
|
||||
#define SWINT_CH13 INTC_SWIER_SWIE13
|
||||
#define SWINT_CH14 INTC_SWIER_SWIE14
|
||||
#define SWINT_CH15 INTC_SWIER_SWIE15
|
||||
#define SWINT_CH16 INTC_SWIER_SWIE16
|
||||
#define SWINT_CH17 INTC_SWIER_SWIE17
|
||||
#define SWINT_CH18 INTC_SWIER_SWIE18
|
||||
#define SWINT_CH19 INTC_SWIER_SWIE19
|
||||
#define SWINT_CH20 INTC_SWIER_SWIE20
|
||||
#define SWINT_CH21 INTC_SWIER_SWIE21
|
||||
#define SWINT_CH22 INTC_SWIER_SWIE22
|
||||
#define SWINT_CH23 INTC_SWIER_SWIE23
|
||||
#define SWINT_CH24 INTC_SWIER_SWIE24
|
||||
#define SWINT_CH25 INTC_SWIER_SWIE25
|
||||
#define SWINT_CH26 INTC_SWIER_SWIE26
|
||||
#define SWINT_CH27 INTC_SWIER_SWIE27
|
||||
#define SWINT_CH28 INTC_SWIER_SWIE28
|
||||
#define SWINT_CH29 INTC_SWIER_SWIE29
|
||||
#define SWINT_CH30 INTC_SWIER_SWIE30
|
||||
#define SWINT_CH31 INTC_SWIER_SWIE31
|
||||
#define SWINT_ALL (0xFFFFFFFFUL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXTINT_FilterClock_Sel External Interrupt Filter A Function Selection
|
||||
* @{
|
||||
*/
|
||||
#define EXTINT_FILTER_OFF (0UL)
|
||||
#define EXTINT_FILTER_ON INTC_EIRQCR_EFEN
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXTINT_FilterClock_Div External Interrupt Filter A Sampling Clock Division Selection
|
||||
* @{
|
||||
*/
|
||||
#define EXTINT_FCLK_DIV1 (0UL)
|
||||
#define EXTINT_FCLK_DIV8 (INTC_EIRQCR_EISMPCLK_0)
|
||||
#define EXTINT_FCLK_DIV32 (INTC_EIRQCR_EISMPCLK_1)
|
||||
#define EXTINT_FCLK_DIV64 (INTC_EIRQCR_EISMPCLK)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXTINT_Trigger_Sel External Interrupt Trigger Edge Selection
|
||||
* @{
|
||||
*/
|
||||
#define EXTINT_TRIG_FALLING (0UL)
|
||||
#define EXTINT_TRIG_RISING INTC_EIRQCR_EIRQTRG_0
|
||||
#define EXTINT_TRIG_BOTH INTC_EIRQCR_EIRQTRG_1
|
||||
#define EXTINT_TRIG_LOW INTC_EIRQCR_EIRQTRG
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup INTC_Stop_Wakeup_Source_Sel Stop Mode Wakeup Source Selection
|
||||
* @{
|
||||
*/
|
||||
#define INTC_STOP_WKUP_EXTINT_CH0 INTC_WUPEN_EIRQWUEN_0
|
||||
#define INTC_STOP_WKUP_EXTINT_CH1 INTC_WUPEN_EIRQWUEN_1
|
||||
#define INTC_STOP_WKUP_EXTINT_CH2 INTC_WUPEN_EIRQWUEN_2
|
||||
#define INTC_STOP_WKUP_EXTINT_CH3 INTC_WUPEN_EIRQWUEN_3
|
||||
#define INTC_STOP_WKUP_EXTINT_CH4 INTC_WUPEN_EIRQWUEN_4
|
||||
#define INTC_STOP_WKUP_EXTINT_CH5 INTC_WUPEN_EIRQWUEN_5
|
||||
#define INTC_STOP_WKUP_EXTINT_CH6 INTC_WUPEN_EIRQWUEN_6
|
||||
#define INTC_STOP_WKUP_EXTINT_CH7 INTC_WUPEN_EIRQWUEN_7
|
||||
#define INTC_STOP_WKUP_EXTINT_CH8 INTC_WUPEN_EIRQWUEN_8
|
||||
#define INTC_STOP_WKUP_EXTINT_CH9 INTC_WUPEN_EIRQWUEN_9
|
||||
#define INTC_STOP_WKUP_EXTINT_CH10 INTC_WUPEN_EIRQWUEN_10
|
||||
#define INTC_STOP_WKUP_EXTINT_CH11 INTC_WUPEN_EIRQWUEN_11
|
||||
#define INTC_STOP_WKUP_EXTINT_CH12 INTC_WUPEN_EIRQWUEN_12
|
||||
#define INTC_STOP_WKUP_EXTINT_CH13 INTC_WUPEN_EIRQWUEN_13
|
||||
#define INTC_STOP_WKUP_EXTINT_CH14 INTC_WUPEN_EIRQWUEN_14
|
||||
#define INTC_STOP_WKUP_EXTINT_CH15 INTC_WUPEN_EIRQWUEN_15
|
||||
#define INTC_STOP_WKUP_SWDT INTC_WUPEN_SWDTWUEN
|
||||
#define INTC_STOP_WKUP_LVD1 INTC_WUPEN_PVD1WUEN
|
||||
#define INTC_STOP_WKUP_LVD2 INTC_WUPEN_PVD2WUEN
|
||||
#define INTC_STOP_WKUP_CMP INTC_WUPEN_CMPI0WUEN
|
||||
#define INTC_STOP_WKUP_WKTM INTC_WUPEN_WKTMWUEN
|
||||
#define INTC_STOP_WKUP_RTC_ALM INTC_WUPEN_RTCALMWUEN
|
||||
#define INTC_STOP_WKUP_RTC_PRD INTC_WUPEN_RTCPRDWUEN
|
||||
#define INTC_STOP_WKUP_TMR0_CMP INTC_WUPEN_TMR0WUEN
|
||||
#define INTC_STOP_WKUP_USART1_RX INTC_WUPEN_RXWUEN
|
||||
#define INTC_WUPEN_ALL (INTC_WUPEN_EIRQWUEN | INTC_WUPEN_SWDTWUEN | \
|
||||
INTC_WUPEN_PVD1WUEN | INTC_WUPEN_PVD2WUEN | \
|
||||
INTC_WUPEN_CMPI0WUEN | INTC_WUPEN_WKTMWUEN | \
|
||||
INTC_WUPEN_RTCALMWUEN | INTC_WUPEN_RTCPRDWUEN | \
|
||||
INTC_WUPEN_TMR0WUEN | INTC_WUPEN_RXWUEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup INTC_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
int32_t INTC_IrqSignIn(const stc_irq_signin_config_t *pstcIrqSignConfig);
|
||||
int32_t INTC_IrqSignOut(IRQn_Type enIRQn);
|
||||
void INTC_WakeupSrcCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewState);
|
||||
void INTC_EventCmd(uint32_t u32Event, en_functional_state_t enNewState);
|
||||
void INTC_IntCmd(uint32_t u32Int, en_functional_state_t enNewState);
|
||||
void INTC_SWIntInit(uint32_t u32Ch, const func_ptr_t pfnCallback, uint32_t u32Priority);
|
||||
void INTC_SWIntCmd(uint32_t u32SWInt, en_functional_state_t enNewState);
|
||||
|
||||
int32_t NMI_Init(const stc_nmi_init_t *pstcNmiInit);
|
||||
int32_t NMI_StructInit(stc_nmi_init_t *pstcNmiInit);
|
||||
en_flag_status_t NMI_GetNmiStatus(uint32_t u32Src);
|
||||
void NMI_NmiSrcCmd(uint32_t u32Src, en_functional_state_t enNewState);
|
||||
void NMI_ClearNmiStatus(uint32_t u32Src);
|
||||
|
||||
int32_t EXTINT_Init(uint32_t u32Ch, const stc_extint_init_t *pstcExtIntInit);
|
||||
int32_t EXTINT_StructInit(stc_extint_init_t *pstcExtIntInit);
|
||||
en_flag_status_t EXTINT_GetExtIntStatus(uint32_t u32ExtIntCh);
|
||||
void EXTINT_ClearExtIntStatus(uint32_t u32ExtIntCh);
|
||||
|
||||
void IRQ000_Handler(void);
|
||||
void IRQ001_Handler(void);
|
||||
void IRQ002_Handler(void);
|
||||
void IRQ003_Handler(void);
|
||||
void IRQ004_Handler(void);
|
||||
void IRQ005_Handler(void);
|
||||
void IRQ006_Handler(void);
|
||||
void IRQ007_Handler(void);
|
||||
|
||||
void IRQ008_Handler(void);
|
||||
void IRQ009_Handler(void);
|
||||
void IRQ010_Handler(void);
|
||||
void IRQ011_Handler(void);
|
||||
void IRQ012_Handler(void);
|
||||
void IRQ013_Handler(void);
|
||||
void IRQ014_Handler(void);
|
||||
void IRQ015_Handler(void);
|
||||
|
||||
void IRQ016_Handler(void);
|
||||
void IRQ017_Handler(void);
|
||||
void IRQ018_Handler(void);
|
||||
void IRQ019_Handler(void);
|
||||
void IRQ020_Handler(void);
|
||||
void IRQ021_Handler(void);
|
||||
void IRQ022_Handler(void);
|
||||
void IRQ023_Handler(void);
|
||||
|
||||
void IRQ024_Handler(void);
|
||||
void IRQ025_Handler(void);
|
||||
void IRQ026_Handler(void);
|
||||
void IRQ027_Handler(void);
|
||||
void IRQ028_Handler(void);
|
||||
void IRQ029_Handler(void);
|
||||
void IRQ030_Handler(void);
|
||||
void IRQ031_Handler(void);
|
||||
void IRQ032_Handler(void);
|
||||
void IRQ033_Handler(void);
|
||||
void IRQ034_Handler(void);
|
||||
void IRQ035_Handler(void);
|
||||
void IRQ036_Handler(void);
|
||||
void IRQ037_Handler(void);
|
||||
void IRQ038_Handler(void);
|
||||
void IRQ039_Handler(void);
|
||||
void IRQ040_Handler(void);
|
||||
void IRQ041_Handler(void);
|
||||
void IRQ042_Handler(void);
|
||||
void IRQ043_Handler(void);
|
||||
void IRQ044_Handler(void);
|
||||
void IRQ045_Handler(void);
|
||||
void IRQ046_Handler(void);
|
||||
void IRQ047_Handler(void);
|
||||
void IRQ048_Handler(void);
|
||||
void IRQ049_Handler(void);
|
||||
void IRQ050_Handler(void);
|
||||
void IRQ051_Handler(void);
|
||||
void IRQ052_Handler(void);
|
||||
void IRQ053_Handler(void);
|
||||
void IRQ054_Handler(void);
|
||||
void IRQ055_Handler(void);
|
||||
void IRQ056_Handler(void);
|
||||
void IRQ057_Handler(void);
|
||||
void IRQ058_Handler(void);
|
||||
void IRQ059_Handler(void);
|
||||
void IRQ060_Handler(void);
|
||||
void IRQ061_Handler(void);
|
||||
void IRQ062_Handler(void);
|
||||
void IRQ063_Handler(void);
|
||||
void IRQ064_Handler(void);
|
||||
void IRQ065_Handler(void);
|
||||
void IRQ066_Handler(void);
|
||||
void IRQ067_Handler(void);
|
||||
void IRQ068_Handler(void);
|
||||
void IRQ069_Handler(void);
|
||||
void IRQ070_Handler(void);
|
||||
void IRQ071_Handler(void);
|
||||
void IRQ072_Handler(void);
|
||||
void IRQ073_Handler(void);
|
||||
void IRQ074_Handler(void);
|
||||
void IRQ075_Handler(void);
|
||||
void IRQ076_Handler(void);
|
||||
void IRQ077_Handler(void);
|
||||
void IRQ078_Handler(void);
|
||||
void IRQ079_Handler(void);
|
||||
void IRQ080_Handler(void);
|
||||
void IRQ081_Handler(void);
|
||||
void IRQ082_Handler(void);
|
||||
void IRQ083_Handler(void);
|
||||
void IRQ084_Handler(void);
|
||||
void IRQ085_Handler(void);
|
||||
void IRQ086_Handler(void);
|
||||
void IRQ087_Handler(void);
|
||||
void IRQ088_Handler(void);
|
||||
void IRQ089_Handler(void);
|
||||
void IRQ090_Handler(void);
|
||||
void IRQ091_Handler(void);
|
||||
void IRQ092_Handler(void);
|
||||
void IRQ093_Handler(void);
|
||||
void IRQ094_Handler(void);
|
||||
void IRQ095_Handler(void);
|
||||
void IRQ096_Handler(void);
|
||||
void IRQ097_Handler(void);
|
||||
void IRQ098_Handler(void);
|
||||
void IRQ099_Handler(void);
|
||||
void IRQ100_Handler(void);
|
||||
void IRQ101_Handler(void);
|
||||
void IRQ102_Handler(void);
|
||||
void IRQ103_Handler(void);
|
||||
void IRQ104_Handler(void);
|
||||
void IRQ105_Handler(void);
|
||||
void IRQ106_Handler(void);
|
||||
void IRQ107_Handler(void);
|
||||
void IRQ108_Handler(void);
|
||||
void IRQ109_Handler(void);
|
||||
void IRQ110_Handler(void);
|
||||
void IRQ111_Handler(void);
|
||||
void IRQ112_Handler(void);
|
||||
void IRQ113_Handler(void);
|
||||
void IRQ114_Handler(void);
|
||||
void IRQ115_Handler(void);
|
||||
void IRQ116_Handler(void);
|
||||
void IRQ117_Handler(void);
|
||||
void IRQ118_Handler(void);
|
||||
void IRQ119_Handler(void);
|
||||
void IRQ120_Handler(void);
|
||||
void IRQ121_Handler(void);
|
||||
void IRQ122_Handler(void);
|
||||
void IRQ123_Handler(void);
|
||||
void IRQ124_Handler(void);
|
||||
void IRQ125_Handler(void);
|
||||
void IRQ126_Handler(void);
|
||||
void IRQ127_Handler(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_INTERRUPTS_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_INTERRUPTS_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,241 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_keyscan.h
|
||||
* @brief This file contains all the functions prototypes of the KEYSCAN driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2023-06-30 CDT Add function KEYSCAN_DeInit
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_KEYSCAN_H__
|
||||
#define __HC32_LL_KEYSCAN_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_KEYSCAN
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_KEYSCAN_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup KEYSCAN_Global_Types KEYSCAN Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief KEYSCAN configuration
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32HizCycle; /*!< Specifies the KEYSCAN Hiz cycles.
|
||||
This parameter can be a value of @ref KEYSCAN_Hiz_Cycle_Sel */
|
||||
|
||||
uint32_t u32LowCycle; /*!< Specifies the KEYSCAN low cycles.
|
||||
This parameter can be a value of @ref KEYSCAN_Low_Cycle_Sel */
|
||||
|
||||
uint32_t u32KeyClock; /*!< Specifies the KEYSCAN low cycles.
|
||||
This parameter can be a value of @ref KEYSCAN_Clock_Sel */
|
||||
|
||||
uint32_t u32KeyOut; /*!< Specifies the KEYSCAN low cycles.
|
||||
This parameter can be a value of @ref KEYSCAN_Keyout_Sel */
|
||||
|
||||
uint32_t u32KeyIn; /*!< Specifies the KEYSCAN low cycles.
|
||||
This parameter can be a value of @ref KEYSCAN_Keyin_Sel */
|
||||
} stc_keyscan_init_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup KEYSCAN_Global_Macros KEYSCAN Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup KEYSCAN_Hiz_Cycle_Sel KEYSCAN Hiz cycles during low ouput selection
|
||||
* @{
|
||||
*/
|
||||
#define KEYSCAN_HIZ_CYCLE_4 (0x00UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 4 cycles during low ouput */
|
||||
#define KEYSCAN_HIZ_CYCLE_8 (0x01UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 8 cycles during low ouput */
|
||||
#define KEYSCAN_HIZ_CYCLE_16 (0x02UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 16 cycles during low ouput */
|
||||
#define KEYSCAN_HIZ_CYCLE_32 (0x03UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 32 cycles during low ouput */
|
||||
#define KEYSCAN_HIZ_CYCLE_64 (0x04UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 64 cycles during low ouput */
|
||||
#define KEYSCAN_HIZ_CYCLE_256 (0x05UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 256 cycles during low ouput */
|
||||
#define KEYSCAN_HIZ_CYCLE_512 (0x06UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 512 cycles during low ouput */
|
||||
#define KEYSCAN_HIZ_CYCLE_1024 (0x07UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 1024 cycles during low ouput */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup KEYSCAN_Low_Cycle_Sel KEYSCAN low level output cycles selection
|
||||
* @{
|
||||
*/
|
||||
#define KEYSCAN_LOW_CYCLE_4 (0x02UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^2=4 cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_8 (0x03UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^3=8 cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_16 (0x04UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^4=16 cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_32 (0x05UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^5=32 cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_64 (0x06UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^6=64 cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_128 (0x07UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^7=128 cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_256 (0x08UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^8=256 cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_512 (0x09UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^9=512 cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_1K (0x0AUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^10=1K cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_2K (0x0BUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^11=2K cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_4K (0x0CUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^12=4K cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_8K (0x0DUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^13=8K cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_16K (0x0EUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^14=16K cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_32K (0x0FUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^15=32K cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_64K (0x10UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^16=64K cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_128K (0x11UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^17=128K cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_256K (0x12UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^18=256K cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_512K (0x13UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^19=512K cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_1M (0x14UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^20=1M cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_2M (0x15UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^21=2M cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_4M (0x16UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^22=4M cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_8M (0x17UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^23=8M cycles */
|
||||
#define KEYSCAN_LOW_CYCLE_16M (0x18UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^24=16M cycles */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup KEYSCAN_Clock_Sel KEYSCAN scan clock selection
|
||||
* @{
|
||||
*/
|
||||
#define KEYSCAN_CLK_HCLK (0x00UL) /*!< Use as HCLK KEYSCAN clock */
|
||||
#define KEYSCAN_CLK_LRC (KEYSCAN_SCR_CKSEL_0) /*!< Use as LRC KEYSCAN clock */
|
||||
#define KEYSCAN_CLK_XTAL32 (KEYSCAN_SCR_CKSEL_1) /*!< Use as XTAL32 KEYSCAN clock */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup KEYSCAN_Keyout_Sel KEYSCAN keyout pins selection
|
||||
* @{
|
||||
*/
|
||||
#define KEYSCAN_OUT_0T1 (0x01UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 1 are selected */
|
||||
#define KEYSCAN_OUT_0T2 (0x02UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 2 are selected */
|
||||
#define KEYSCAN_OUT_0T3 (0x03UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 3 are selected */
|
||||
#define KEYSCAN_OUT_0T4 (0x04UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 4 are selected */
|
||||
#define KEYSCAN_OUT_0T5 (0x05UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 5 are selected */
|
||||
#define KEYSCAN_OUT_0T6 (0x06UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 6 are selected */
|
||||
#define KEYSCAN_OUT_0T7 (0x07UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 7 are selected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup KEYSCAN_Keyin_Sel KEYSCAN keyin pins selection
|
||||
* @{
|
||||
*/
|
||||
#define KEYSCAN_IN_0 (1UL << 0U) /*!< KEYIN(EIRQ) 0 is selected */
|
||||
#define KEYSCAN_IN_1 (1UL << 1U) /*!< KEYIN(EIRQ) 1 is selected */
|
||||
#define KEYSCAN_IN_2 (1UL << 2U) /*!< KEYIN(EIRQ) 2 is selected */
|
||||
#define KEYSCAN_IN_3 (1UL << 3U) /*!< KEYIN(EIRQ) 3 is selected */
|
||||
#define KEYSCAN_IN_4 (1UL << 4U) /*!< KEYIN(EIRQ) 4 is selected */
|
||||
#define KEYSCAN_IN_5 (1UL << 5U) /*!< KEYIN(EIRQ) 5 is selected */
|
||||
#define KEYSCAN_IN_6 (1UL << 6U) /*!< KEYIN(EIRQ) 6 is selected */
|
||||
#define KEYSCAN_IN_7 (1UL << 7U) /*!< KEYIN(EIRQ) 7 is selected */
|
||||
#define KEYSCAN_IN_8 (1UL << 8U) /*!< KEYIN(EIRQ) 8 is selected */
|
||||
#define KEYSCAN_IN_9 (1UL << 9U) /*!< KEYIN(EIRQ) 9 is selected */
|
||||
#define KEYSCAN_IN_10 (1UL << 10U) /*!< KEYIN(EIRQ) 10 is selected */
|
||||
#define KEYSCAN_IN_11 (1UL << 11U) /*!< KEYIN(EIRQ) 11 is selected */
|
||||
#define KEYSCAN_IN_12 (1UL << 12U) /*!< KEYIN(EIRQ) 12 is selected */
|
||||
#define KEYSCAN_IN_13 (1UL << 13U) /*!< KEYIN(EIRQ) 13 is selected */
|
||||
#define KEYSCAN_IN_14 (1UL << 14U) /*!< KEYIN(EIRQ) 14 is selected */
|
||||
#define KEYSCAN_IN_15 (1UL << 15U) /*!< KEYIN(EIRQ) 15 is selected */
|
||||
#define KEYSCAN_IN_ALL (KEYSCAN_SCR_KEYINSEL) /*!< KEYIN(EIRQ) mask */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup KEYSCAN_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Get KEYOUT index.
|
||||
* @param None
|
||||
* @retval uint32_t: KEYOUT index 0~7.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t KEYSCAN_GetKeyoutIdx(void)
|
||||
{
|
||||
return READ_REG32_BIT(CM_KEYSCAN->SSR, KEYSCAN_SSR_INDEX);
|
||||
}
|
||||
|
||||
int32_t KEYSCAN_StructInit(stc_keyscan_init_t *pstcKeyscanInit);
|
||||
int32_t KEYSCAN_Init(const stc_keyscan_init_t *pstcKeyscanInit);
|
||||
void KEYSCAN_Cmd(en_functional_state_t enNewState);
|
||||
int32_t KEYSCAN_DeInit(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_KEYSCAN_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_KEYSCAN_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,384 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_mpu.h
|
||||
* @brief This file contains all the functions prototypes of the MPU driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_MPU_H__
|
||||
#define __HC32_LL_MPU_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_MPU
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_MPU_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup MPU_Global_Types MPU Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief MPU Unit configure structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32ExceptionType; /*!< Specifies the type of exception that occurs when the unit accesses a protected region.
|
||||
This parameter can be a value of @ref MPU_Exception_Type */
|
||||
uint32_t u32BackgroundWrite; /*!< Specifies the unit's write permission for the background space.
|
||||
This parameter can be a value of @ref MPU_Background_Write_Permission */
|
||||
uint32_t u32BackgroundRead; /*!< Specifies the unit's read permission for the background space
|
||||
This parameter can be a value of @ref MPU_Background_Read_Permission */
|
||||
} stc_mpu_unit_config_t;
|
||||
|
||||
/**
|
||||
* @brief MPU Init structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
stc_mpu_unit_config_t stcDma1; /*!< Configure storage protection unit of DMA1 */
|
||||
stc_mpu_unit_config_t stcDma2; /*!< Configure storage protection unit of DMA2 */
|
||||
stc_mpu_unit_config_t stcUsbFSDma; /*!< Configure storage protection unit of USBFS_DMA */
|
||||
} stc_mpu_init_t;
|
||||
|
||||
/**
|
||||
* @brief MPU Region Permission structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32RegionWrite; /*!< Specifies the unit's write permission for the region.
|
||||
This parameter can be a value of @ref MPU_Region_Write_Permission */
|
||||
uint32_t u32RegionRead; /*!< Specifies the unit's read permission for the region.
|
||||
This parameter can be a value of @ref MPU_Region_Read_Permission */
|
||||
} stc_mpu_region_permission_t;
|
||||
|
||||
/**
|
||||
* @brief MPU region initialization structure definition
|
||||
* @note The effective bits of the 'u32BaseAddr' are related to the 'u32Size' of the region,
|
||||
* and the low 'u32Size+1' bits are fixed at 0.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32BaseAddr; /*!< Specifies the base address of the region.
|
||||
This parameter can be a number between 0UL and 0xFFFFFFE0UL */
|
||||
uint32_t u32Size; /*!< Specifies the size of the region.
|
||||
This parameter can be a value of @ref MPU_Region_Size */
|
||||
stc_mpu_region_permission_t stcDma1; /*!< Specifies the DMA1 access permission for the region */
|
||||
stc_mpu_region_permission_t stcDma2; /*!< Specifies the DMA2 access permission for the region */
|
||||
stc_mpu_region_permission_t stcUsbFSDma; /*!< Specifies the USBFS_DMA access permission for the region */
|
||||
} stc_mpu_region_init_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup MPU_Global_Macros MPU Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup MPU_Unit_Type MPU Unit Type
|
||||
* @{
|
||||
*/
|
||||
#define MPU_UNIT_DMA2 (0x01UL) /*!< System DMA_2 MPU */
|
||||
#define MPU_UNIT_DMA1 (0x02UL) /*!< System DMA_1 MPU */
|
||||
#define MPU_UNIT_USBFS_DMA (0x04UL) /*!< USBFS_DMA MPU */
|
||||
#define MPU_UNIT_ALL (MPU_UNIT_DMA2 | MPU_UNIT_DMA1 | MPU_UNIT_USBFS_DMA)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup MPU_Region_Number MPU Region Number
|
||||
* @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'.
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NUM0 (0x00UL) /*!< MPU region number 0 */
|
||||
#define MPU_REGION_NUM1 (0x01UL) /*!< MPU region number 1 */
|
||||
#define MPU_REGION_NUM2 (0x02UL) /*!< MPU region number 2 */
|
||||
#define MPU_REGION_NUM3 (0x03UL) /*!< MPU region number 3 */
|
||||
#define MPU_REGION_NUM4 (0x04UL) /*!< MPU region number 4 */
|
||||
#define MPU_REGION_NUM5 (0x05UL) /*!< MPU region number 5 */
|
||||
#define MPU_REGION_NUM6 (0x06UL) /*!< MPU region number 6 */
|
||||
#define MPU_REGION_NUM7 (0x07UL) /*!< MPU region number 7 */
|
||||
#define MPU_REGION_NUM8 (0x08UL) /*!< MPU region number 8 */
|
||||
#define MPU_REGION_NUM9 (0x09UL) /*!< MPU region number 9 */
|
||||
#define MPU_REGION_NUM10 (0x0AUL) /*!< MPU region number 10 */
|
||||
#define MPU_REGION_NUM11 (0x0BUL) /*!< MPU region number 11 */
|
||||
#define MPU_REGION_NUM12 (0x0CUL) /*!< MPU region number 12 */
|
||||
#define MPU_REGION_NUM13 (0x0DUL) /*!< MPU region number 13 */
|
||||
#define MPU_REGION_NUM14 (0x0EUL) /*!< MPU region number 14 */
|
||||
#define MPU_REGION_NUM15 (0x0FUL) /*!< MPU region number 15 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup MPU_Background_Write_Permission MPU Background Write Permission
|
||||
* @{
|
||||
*/
|
||||
#define MPU_BACKGROUND_WR_DISABLE (MPU_CR_SMPU2BWP) /*!< Disable write the background space */
|
||||
#define MPU_BACKGROUND_WR_ENABLE (0UL) /*!< Enable write the background space */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup MPU_Background_Read_Permission MPU Background Read Permission
|
||||
* @{
|
||||
*/
|
||||
#define MPU_BACKGROUND_RD_DISABLE (MPU_CR_SMPU2BRP) /*!< Disable read the background space */
|
||||
#define MPU_BACKGROUND_RD_ENABLE (0UL) /*!< Enable read the background space */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup MPU_Exception_Type MPU Exception Type
|
||||
* @{
|
||||
*/
|
||||
#define MPU_EXP_TYPE_NONE (0UL) /*!< The host unit access protection regions will be ignored */
|
||||
#define MPU_EXP_TYPE_BUS_ERR (MPU_CR_SMPU2ACT_0) /*!< The host unit access protection regions will be ignored and a bus error will be triggered */
|
||||
#define MPU_EXP_TYPE_NMI (MPU_CR_SMPU2ACT_1) /*!< The host unit access protection regions will be ignored and a NMI interrupt will be triggered */
|
||||
#define MPU_EXP_TYPE_RST (MPU_CR_SMPU2ACT) /*!< The host unit access protection regions will trigger the reset */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup MPU_Region_Write_Permission MPU Region Write Permission
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_WR_DISABLE (MPU_RGCR_S2RGWP) /*!< Disable write the region */
|
||||
#define MPU_REGION_WR_ENABLE (0UL) /*!< Enable write the region */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup MPU_Region_Read_Permission MPU Region Read Permission
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_RD_DISABLE (MPU_RGCR_S2RGRP) /*!< Disable read the region */
|
||||
#define MPU_REGION_RD_ENABLE (0UL) /*!< Enable read the region */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup MPU_Region_Size MPU Region Size
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_SIZE_32BYTE (0x04UL) /*!< 32 Byte */
|
||||
#define MPU_REGION_SIZE_64BYTE (0x05UL) /*!< 64 Byte */
|
||||
#define MPU_REGION_SIZE_128BYTE (0x06UL) /*!< 126 Byte */
|
||||
#define MPU_REGION_SIZE_256BYTE (0x07UL) /*!< 256 Byte */
|
||||
#define MPU_REGION_SIZE_512BYTE (0x08UL) /*!< 512 Byte */
|
||||
#define MPU_REGION_SIZE_1KBYTE (0x09UL) /*!< 1K Byte */
|
||||
#define MPU_REGION_SIZE_2KBYTE (0x0AUL) /*!< 2K Byte */
|
||||
#define MPU_REGION_SIZE_4KBYTE (0x0BUL) /*!< 4K Byte */
|
||||
#define MPU_REGION_SIZE_8KBYTE (0x0CUL) /*!< 8K Byte */
|
||||
#define MPU_REGION_SIZE_16KBYTE (0x0DUL) /*!< 16K Byte */
|
||||
#define MPU_REGION_SIZE_32KBYTE (0x0EUL) /*!< 32K Byte */
|
||||
#define MPU_REGION_SIZE_64KBYTE (0x0FUL) /*!< 64K Byte */
|
||||
#define MPU_REGION_SIZE_128KBYTE (0x10UL) /*!< 128K Byte */
|
||||
#define MPU_REGION_SIZE_256KBYTE (0x11UL) /*!< 256K Byte */
|
||||
#define MPU_REGION_SIZE_512KBYTE (0x12UL) /*!< 512K Byte */
|
||||
#define MPU_REGION_SIZE_1MBYTE (0x13UL) /*!< 1M Byte */
|
||||
#define MPU_REGION_SIZE_2MBYTE (0x14UL) /*!< 2M Byte */
|
||||
#define MPU_REGION_SIZE_4MBYTE (0x15UL) /*!< 4M Byte */
|
||||
#define MPU_REGION_SIZE_8MBYTE (0x16UL) /*!< 8M Byte */
|
||||
#define MPU_REGION_SIZE_16MBYTE (0x17UL) /*!< 16M Byte */
|
||||
#define MPU_REGION_SIZE_32MBYTE (0x18UL) /*!< 32M Byte */
|
||||
#define MPU_REGION_SIZE_64MBYTE (0x19UL) /*!< 64M Byte */
|
||||
#define MPU_REGION_SIZE_128MBYTE (0x1AUL) /*!< 128M Byte */
|
||||
#define MPU_REGION_SIZE_256MBYTE (0x1BUL) /*!< 256M Byte */
|
||||
#define MPU_REGION_SIZE_512MBYTE (0x1CUL) /*!< 512M Byte */
|
||||
#define MPU_REGION_SIZE_1GBYTE (0x1DUL) /*!< 1G Byte */
|
||||
#define MPU_REGION_SIZE_2GBYTE (0x1EUL) /*!< 2G Byte */
|
||||
#define MPU_REGION_SIZE_4GBYTE (0x1FUL) /*!< 4G Byte */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup MPU_Flag MPU Flag
|
||||
* @{
|
||||
*/
|
||||
#define MPU_FLAG_SMPU1EAF (MPU_SR_SMPU1EAF) /*!< System DMA_1 error flag */
|
||||
#define MPU_FLAG_SMPU2EAF (MPU_SR_SMPU2EAF) /*!< System DMA_2 error flag */
|
||||
#define MPU_FLAG_FMPUEAF (MPU_SR_FMPUEAF) /*!< USBFS_DMA error flag */
|
||||
|
||||
#define MPU_FLAG_ALL (MPU_FLAG_SMPU1EAF | MPU_FLAG_SMPU2EAF | MPU_FLAG_FMPUEAF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup MPU_IP_Type MPU IP Type
|
||||
* @note IP access protection is not available in privileged mode.
|
||||
* @{
|
||||
*/
|
||||
#define MPU_IP_AES (MPU_IPPR_AESRDP) /*!< AES module */
|
||||
#define MPU_IP_HASH (MPU_IPPR_HASHRDP) /*!< HASH module */
|
||||
#define MPU_IP_TRNG (MPU_IPPR_TRNGRDP) /*!< TRNG module */
|
||||
#define MPU_IP_CRC (MPU_IPPR_CRCRDP) /*!< CRC module */
|
||||
#define MPU_IP_EFM (MPU_IPPR_EFMRDP) /*!< EFM module */
|
||||
#define MPU_IP_WDT (MPU_IPPR_WDTRDP) /*!< WDT module */
|
||||
#define MPU_IP_SWDT (MPU_IPPR_SWDTRDP) /*!< SWDT module */
|
||||
#define MPU_IP_BKSRAM (MPU_IPPR_BKSRAMRDP) /*!< BKSRAM module */
|
||||
#define MPU_IP_RTC (MPU_IPPR_RTCRDP) /*!< RTC module */
|
||||
#define MPU_IP_MPU (MPU_IPPR_DMPURDP) /*!< MPU module */
|
||||
#define MPU_IP_SRAMC (MPU_IPPR_SRAMCRDP) /*!< SRAMC module */
|
||||
#define MPU_IP_INTC (MPU_IPPR_INTCRDP) /*!< INTC module */
|
||||
#define MPU_IP_RMU_CMU_PWC (MPU_IPPR_SYSCRDP) /*!< RMU, CMU and PWC modules */
|
||||
#define MPU_IP_FCG (MPU_IPPR_MSTPRDP) /*!< PWR_FCG0/1/2/3 and PWR_FCG0PC registers */
|
||||
#define MPU_IP_ALL (MPU_IP_AES | MPU_IP_HASH | MPU_IP_TRNG | MPU_IP_CRC | \
|
||||
MPU_IP_EFM | MPU_IP_WDT | MPU_IP_SWDT | MPU_IP_BKSRAM | \
|
||||
MPU_IP_RTC | MPU_IP_MPU | MPU_IP_SRAMC | MPU_IP_INTC | \
|
||||
MPU_IP_FCG | MPU_IP_RMU_CMU_PWC)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup MPU_IP_Exception_Type MPU IP Exception Type
|
||||
* @{
|
||||
*/
|
||||
#define MPU_IP_EXP_TYPE_NONE (0UL) /*!< Access to the protected IP will be ignored */
|
||||
#define MPU_IP_EXP_TYPE_BUS_ERR (MPU_IPPR_BUSERRE) /*!< Access to the protected IP will trigger a bus error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup MPU_Register_Protect_Key INTC Registers Protect Key
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REG_LOCK_KEY (0x96A4UL)
|
||||
#define MPU_REG_UNLOCK_KEY (0x96A5UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup MPU_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief MPU write protect unlock.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void MPU_REG_Unlock(void)
|
||||
{
|
||||
WRITE_REG32(CM_MPU->WP, MPU_REG_UNLOCK_KEY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MPU write protect lock.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void MPU_REG_Lock(void)
|
||||
{
|
||||
WRITE_REG32(CM_MPU->WP, MPU_REG_LOCK_KEY);
|
||||
}
|
||||
|
||||
void MPU_REG_Unlock(void);
|
||||
void MPU_REG_Lock(void);
|
||||
|
||||
void MPU_DeInit(void);
|
||||
int32_t MPU_Init(const stc_mpu_init_t *pstcMpuInit);
|
||||
int32_t MPU_StructInit(stc_mpu_init_t *pstcMpuInit);
|
||||
void MPU_SetExceptionType(uint32_t u32Unit, uint32_t u32Type);
|
||||
void MPU_BackgroundWriteCmd(uint32_t u32Unit, en_functional_state_t enNewState);
|
||||
void MPU_BackgroundReadCmd(uint32_t u32Unit, en_functional_state_t enNewState);
|
||||
void MPU_UnitCmd(uint32_t u32Unit, en_functional_state_t enNewState);
|
||||
en_flag_status_t MPU_GetStatus(uint32_t u32Flag);
|
||||
void MPU_ClearStatus(uint32_t u32Flag);
|
||||
|
||||
int32_t MPU_RegionInit(uint32_t u32Num, const stc_mpu_region_init_t *pstcRegionInit);
|
||||
int32_t MPU_RegionStructInit(stc_mpu_region_init_t *pstcRegionInit);
|
||||
void MPU_SetRegionBaseAddr(uint32_t u32Num, uint32_t u32Addr);
|
||||
void MPU_SetRegionSize(uint32_t u32Num, uint32_t u32Size);
|
||||
void MPU_RegionWriteCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState);
|
||||
void MPU_RegionReadCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState);
|
||||
void MPU_RegionCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState);
|
||||
|
||||
void MPU_IP_SetExceptionType(uint32_t u32Type);
|
||||
void MPU_IP_WriteCmd(uint32_t u32Periph, en_functional_state_t enNewState);
|
||||
void MPU_IP_ReadCmd(uint32_t u32Periph, en_functional_state_t enNewState);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_MPU_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_MPU_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,189 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_ots.h
|
||||
* @brief This file contains all the functions prototypes of the OTS driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2023-06-30 CDT Modify API OTS_DeInit()
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_OTS_H__
|
||||
#define __HC32_LL_OTS_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_OTS
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_OTS_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup OTS_Global_Types OTS Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief OTS initialization structure.
|
||||
*/
|
||||
typedef struct {
|
||||
uint16_t u16ClockSrc; /*!< Specifies clock source for OTS.
|
||||
This parameter can be a value of @ref OTS_Clock_Source */
|
||||
uint16_t u16AutoOffEn; /*!< Enable or disable OTS automatic-off(after sampled temperature).
|
||||
This parameter can be a value of @ref OTS_Auto_Off_En */
|
||||
float32_t f32SlopeK; /*!< K: Temperature slope (calculated by calibration experiment).
|
||||
If you want to use the default parameters(slope K and offset M),
|
||||
specify both 'f32SlopeK' and 'f32OffsetM' as ZERO. */
|
||||
float32_t f32OffsetM; /*!< M: Temperature offset (calculated by calibration experiment).
|
||||
If you want to use the default parameters(slope K and offset M),
|
||||
specify both 'f32SlopeK' and 'f32OffsetM' as ZERO. */
|
||||
} stc_ots_init_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup OTS_Global_Macros OTS Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup OTS_Clock_Source OTS Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define OTS_CLK_XTAL (0x0U) /*!< Select XTAL as OTS clock. */
|
||||
#define OTS_CLK_HRC (OTS_CTL_OTSCK) /*!< Select HRC as OTS clock */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup OTS_Auto_Off_En OTS Automatic Off Function Control
|
||||
* @{
|
||||
*/
|
||||
#define OTS_AUTO_OFF_DISABLE (0x0U) /*!< OTS automatically turned off when sampled done. */
|
||||
#define OTS_AUTO_OFF_ENABLE (OTS_CTL_TSSTP) /*!< OTS is still on when sampled done. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup OTS_Param_Temp_Cond OTS Parameter Temperature Condition
|
||||
* @{
|
||||
*/
|
||||
#define OTS_PARAM_TEMP_COND_TN40 (0U) /*!< -40 degrees Celsius. */
|
||||
#define OTS_PARAM_TEMP_COND_T25 (1U) /*!< 25 degrees Celsius. */
|
||||
#define OTS_PARAM_TEMP_COND_T125 (2U) /*!< 125 degrees Celsius. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup OTS_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start OTS.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void OTS_Start(void)
|
||||
{
|
||||
WRITE_REG32(bCM_OTS->CTL_b.OTSST, 1U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop OTS.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void OTS_Stop(void)
|
||||
{
|
||||
WRITE_REG32(bCM_OTS->CTL_b.OTSST, 0U);
|
||||
}
|
||||
|
||||
int32_t OTS_Init(const stc_ots_init_t *pstcOTSInit);
|
||||
int32_t OTS_StructInit(stc_ots_init_t *pstcOTSInit);
|
||||
int32_t OTS_DeInit(void);
|
||||
|
||||
int32_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout);
|
||||
|
||||
void OTS_IntCmd(en_functional_state_t enNewState);
|
||||
|
||||
int32_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2,
|
||||
uint16_t *pu16Ecr, float32_t *pf32A,
|
||||
uint32_t u32Timeout);
|
||||
|
||||
float32_t OTS_CalculateTemp(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_OTS_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_OTS_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,634 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_pwc.h
|
||||
* @brief This file contains all the functions prototypes of the PWC driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2022-06-30 CDT Refine API PWC_STOP_Enter()
|
||||
2023-06-30 CDT Modify group PWC_Stop_Type
|
||||
2023-09-30 CDT Add function PWC_LVD_DeInit
|
||||
Modify the PWC_LVD_Detection_Voltage_Sel comment
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_PWC_H__
|
||||
#define __HC32_LL_PWC_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_PWC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_PWC_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup PWC_Global_Types PWC Global Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief PWC LVD Init
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32State; /*!< LVD function setting, @ref PWC_LVD_Config for details */
|
||||
uint32_t u32CompareOutputState; /*!< LVD compare output function setting, @ref PWC_LVD_CMP_Config for details */
|
||||
uint32_t u32ExceptionType; /*!< LVD interrupt or reset selection, @ref PWC_LVD_Exception_Type_Sel for details */
|
||||
uint32_t u32Filter; /*!< LVD digital filter function setting, @ref PWC_LVD_DF_Config for details */
|
||||
uint32_t u32FilterClock; /*!< LVD digital filter clock setting, @ref PWC_LVD_DFS_Clk_Sel for details */
|
||||
uint32_t u32ThresholdVoltage; /*!< LVD detect voltage setting, @ref PWC_LVD_Detection_Voltage_Sel for details */
|
||||
} stc_pwc_lvd_init_t;
|
||||
|
||||
/**
|
||||
* @brief PWC power down mode innit
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t u8Mode; /*!< Power down mode, @ref PWC_PDMode_Sel for details. */
|
||||
uint8_t u8IOState; /*!< IO state in power down mode, @ref PWC_PDMode_IO_Sel for details. */
|
||||
uint8_t u8VcapCtrl; /*!< Power down Wakeup time control, @ref PWC_PD_VCAP_Sel for details. */
|
||||
} stc_pwc_pd_mode_config_t;
|
||||
|
||||
/**
|
||||
* @brief PWC Stop mode Init
|
||||
*/
|
||||
typedef struct {
|
||||
uint16_t u16Clock; /*!< System clock setting after wake-up from stop mode,
|
||||
@ref PWC_STOP_CLK_Sel for details. */
|
||||
uint8_t u8StopDrv; /*!< Stop mode drive capacity,
|
||||
@ref PWC_STOP_DRV_Sel for details. */
|
||||
uint16_t u16FlashWait; /*!< Waiting flash stable after wake-up from stop mode,
|
||||
@ref PWC_STOP_Flash_Wait_Sel for details. */
|
||||
} stc_pwc_stop_mode_config_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup PWC_Global_Macros PWC Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_PDMode_Sel Power down mode selection
|
||||
* @{
|
||||
*/
|
||||
#define PWC_PD_MD1 (0x00U) /*!< Power down mode 1 */
|
||||
#define PWC_PD_MD2 (0x01U) /*!< Power down mode 2 */
|
||||
#define PWC_PD_MD3 (0x02U) /*!< Power down mode 3 */
|
||||
#define PWC_PD_MD4 (0x03U) /*!< Power down mode 4 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_PDMode_IO_Sel IO state config in Power down mode
|
||||
* @{
|
||||
*/
|
||||
#define PWC_PD_IO_KEEP1 (0x00U) /*!< IO state retain in PD mode and configurable after wakeup */
|
||||
#define PWC_PD_IO_KEEP2 (PWC_PWRC0_IORTN_0) /*!< IO state retain in PD mode and configurable after wakeup & set IORTN[1:0]=00b */
|
||||
#define PWC_PD_IO_HIZ (PWC_PWRC0_IORTN_1) /*!< IO state switch to HiZ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_PD_VCAP_Sel Wakeup speed config in Power down mode
|
||||
* @{
|
||||
*/
|
||||
#define PWC_PD_VCAP_0P1UF (0x00U) /*!< VCAP1/VCAP2 = 0.1uF x2 or 0.22uF x1 */
|
||||
#define PWC_PD_VCAP_0P047UF (0x01U) /*!< VCAP1/VCAP2 = 0.047uF x2 or 0.1uF x1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_STOP_DRV_Sel Drive capacity while enter stop mode
|
||||
* @{
|
||||
*/
|
||||
#define PWC_STOP_DRV_HIGH (0x00U) /*!< Enter stop mode from high speed mode */
|
||||
#define PWC_STOP_DRV_LOW (PWC_PWRC1_STPDAS) /*!< Enter stop mode from ultra low speed mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_STOP_CLK_Sel System clock setting after wake-up from stop mode
|
||||
* @{
|
||||
*/
|
||||
#define PWC_STOP_CLK_KEEP (0x00U) /*!< Keep System clock setting after wake-up from stop mode */
|
||||
#define PWC_STOP_CLK_MRC (PWC_STPMCR_CKSMRC) /*!< System clock switch to MRC after wake-up from stop mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_STOP_Flash_Wait_Sel Whether wait flash stable or not after wake-up from stop mode
|
||||
* @{
|
||||
*/
|
||||
#define PWC_STOP_FLASH_WAIT_ON (0x00U) /*!< Wait flash stable after wake-up from stop mode */
|
||||
#define PWC_STOP_FLASH_WAIT_OFF (PWC_STPMCR_FLNWT) /*!< Don't wait flash stable after wake-up from stop mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_Stop_Type PWC stop mode type.
|
||||
* @{
|
||||
*/
|
||||
#define PWC_STOP_WFI (0x00U) /*!< Enter stop mode by WFI, and wake-up by interrupt handle. */
|
||||
#define PWC_STOP_WFE_INT (0x01U) /*!< Enter stop mode by WFE, and wake-up by interrupt request. */
|
||||
#define PWC_STOP_WFE_EVT (0x02U) /*!< Enter stop mode by WFE, and wake-up by event. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_RAM_Config Operating mode for RAM Config
|
||||
* @{
|
||||
*/
|
||||
#define PWC_RAM_HIGH_SPEED (0x8043U) /*!< MCU operating under high frequency (lower than 240MHz) */
|
||||
#define PWC_RAM_ULOW_SPEED (0x9062U) /*!< MCU operating under ultra low frequency (lower than 8MHz) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_PD_Periph_Ram Peripheral ram to power down
|
||||
* @{
|
||||
*/
|
||||
#define PWC_RAM_PD_SRAM1 (PWC_RAMPC0_RAMPDC0)
|
||||
#define PWC_RAM_PD_SRAM2 (PWC_RAMPC0_RAMPDC1)
|
||||
#define PWC_RAM_PD_SRAM3 (PWC_RAMPC0_RAMPDC2)
|
||||
#define PWC_RAM_PD_SRAMH (PWC_RAMPC0_RAMPDC3)
|
||||
#define PWC_RAM_PD_USBFS (PWC_RAMPC0_RAMPDC4)
|
||||
#define PWC_RAM_PD_SDIO0 (PWC_RAMPC0_RAMPDC5)
|
||||
#define PWC_RAM_PD_SDIO1 (PWC_RAMPC0_RAMPDC6)
|
||||
#define PWC_RAM_PD_CACHE (PWC_RAMPC0_RAMPDC8)
|
||||
#define PWC_RAM_PD_CAN (PWC_RAMPC0_RAMPDC7)
|
||||
#define PWC_RAM_PD_ALL (0x1FFU)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_LVD_Channel PWC LVD channel
|
||||
* @{
|
||||
*/
|
||||
#define PWC_LVD_CH1 (0x00U)
|
||||
#define PWC_LVD_CH2 (0x01U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_LVD_Config PWC LVD Config
|
||||
* @{
|
||||
*/
|
||||
#define PWC_LVD_ON (PWC_PVDCR0_PVD1EN)
|
||||
#define PWC_LVD_OFF (0x00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_LVD_Exception_Type_Sel PWC LVD Exception Type Select
|
||||
* @{
|
||||
*/
|
||||
#define PWC_LVD_EXP_TYPE_NONE (0x00U)
|
||||
#define PWC_LVD_EXP_TYPE_INT (0x0101U)
|
||||
#define PWC_LVD_EXP_TYPE_NMI (0x0001U)
|
||||
#define PWC_LVD_EXP_TYPE_RST (PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_LVD_CMP_Config PWC LVD Compare Config
|
||||
* @{
|
||||
*/
|
||||
#define PWC_LVD_CMP_OFF (0x00U)
|
||||
#define PWC_LVD_CMP_ON (PWC_PVDCR1_PVD1CMPOE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_LVD_DF_Config LVD digital filter ON or OFF
|
||||
* @{
|
||||
*/
|
||||
#define PWC_LVD_FILTER_ON (0x00U)
|
||||
#define PWC_LVD_FILTER_OFF (0x01U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_LVD_DFS_Clk_Sel LVD digital filter sample ability
|
||||
* @note modified this value must when PWC_LVD_FILTER_OFF
|
||||
* @{
|
||||
*/
|
||||
#define PWC_LVD_FILTER_LRC_DIV4 (0x00UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 0.25 LRC cycle */
|
||||
#define PWC_LVD_FILTER_LRC_DIV2 (0x01UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 0.5 LRC cycle */
|
||||
#define PWC_LVD_FILTER_LRC_DIV1 (0x02UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 1 LRC cycle */
|
||||
#define PWC_LVD_FILTER_LRC_MUL2 (0x03UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 2 LRC cycles */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_LVD_Detection_Voltage_Sel PWC LVD Detection voltage
|
||||
* @{
|
||||
* @note
|
||||
* @verbatim
|
||||
* | LVL0 | LVL1 | LVL2 | LVL3 | LVL4 | LVL5 | LVL6 | LVL7 | EXVCC |
|
||||
* LVD1 | 2.00V | 2.10V | 2.30V | 2.55V | 2.65V | 2.75V | 2.85V | 2.95V | -- |
|
||||
* LVD2 | 2.10V | 2.30V | 2.55V | 2.65V | 2.75V | 2.85V | 2.95V | 1.10V | EXVCC |
|
||||
* @endverbatim
|
||||
*/
|
||||
#define PWC_LVD_THRESHOLD_LVL0 (0x00U)
|
||||
#define PWC_LVD_THRESHOLD_LVL1 (0x01U)
|
||||
#define PWC_LVD_THRESHOLD_LVL2 (0x02U)
|
||||
#define PWC_LVD_THRESHOLD_LVL3 (0x03U)
|
||||
#define PWC_LVD_THRESHOLD_LVL4 (0x04U)
|
||||
#define PWC_LVD_THRESHOLD_LVL5 (0x05U)
|
||||
#define PWC_LVD_THRESHOLD_LVL6 (0x06U)
|
||||
#define PWC_LVD_THRESHOLD_LVL7 (0x07U)
|
||||
#define PWC_LVD_EXTVCC (0x07U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_LVD_Flag LVD flag
|
||||
* @{
|
||||
*/
|
||||
#define PWC_LVD1_FLAG_DETECT (PWC_PVDDSR_PVD1DETFLG) /*!< VCC across VLVD1 */
|
||||
#define PWC_LVD2_FLAG_DETECT (PWC_PVDDSR_PVD2DETFLG) /*!< VCC across VLVD2 */
|
||||
#define PWC_LVD1_FLAG_MON (PWC_PVDDSR_PVD1MON) /*!< VCC > VLVD1 */
|
||||
#define PWC_LVD2_FLAG_MON (PWC_PVDDSR_PVD2MON) /*!< VCC > VLVD2 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_WKUP_Event_Sel Power down mode wakeup event selection
|
||||
* @{
|
||||
*/
|
||||
#define PWC_PD_WKUP0_POS (0U)
|
||||
#define PWC_PD_WKUP1_POS (8U)
|
||||
#define PWC_PD_WKUP2_POS (16U)
|
||||
#define PWC_PD_WKUP_WKUP00 (PWC_PDWKE0_WKE00 << PWC_PD_WKUP0_POS)
|
||||
#define PWC_PD_WKUP_WKUP01 (PWC_PDWKE0_WKE01 << PWC_PD_WKUP0_POS)
|
||||
#define PWC_PD_WKUP_WKUP02 (PWC_PDWKE0_WKE02 << PWC_PD_WKUP0_POS)
|
||||
#define PWC_PD_WKUP_WKUP03 (PWC_PDWKE0_WKE03 << PWC_PD_WKUP0_POS)
|
||||
#define PWC_PD_WKUP_WKUP10 (PWC_PDWKE0_WKE10 << PWC_PD_WKUP0_POS)
|
||||
#define PWC_PD_WKUP_WKUP11 (PWC_PDWKE0_WKE11 << PWC_PD_WKUP0_POS)
|
||||
#define PWC_PD_WKUP_WKUP12 (PWC_PDWKE0_WKE12 << PWC_PD_WKUP0_POS)
|
||||
#define PWC_PD_WKUP_WKUP13 (PWC_PDWKE0_WKE13 << PWC_PD_WKUP0_POS)
|
||||
#define PWC_PD_WKUP_WKUP20 (PWC_PDWKE1_WKE20 << PWC_PD_WKUP1_POS)
|
||||
#define PWC_PD_WKUP_WKUP21 (PWC_PDWKE1_WKE21 << PWC_PD_WKUP1_POS)
|
||||
#define PWC_PD_WKUP_WKUP22 (PWC_PDWKE1_WKE22 << PWC_PD_WKUP1_POS)
|
||||
#define PWC_PD_WKUP_WKUP23 (PWC_PDWKE1_WKE23 << PWC_PD_WKUP1_POS)
|
||||
#define PWC_PD_WKUP_WKUP30 (PWC_PDWKE1_WKE30 << PWC_PD_WKUP1_POS)
|
||||
#define PWC_PD_WKUP_WKUP31 (PWC_PDWKE1_WKE31 << PWC_PD_WKUP1_POS)
|
||||
#define PWC_PD_WKUP_WKUP32 (PWC_PDWKE1_WKE32 << PWC_PD_WKUP1_POS)
|
||||
#define PWC_PD_WKUP_WKUP33 (PWC_PDWKE1_WKE33 << PWC_PD_WKUP1_POS)
|
||||
#define PWC_PD_WKUP_LVD1 (PWC_PDWKE2_VD1WKE << PWC_PD_WKUP2_POS)
|
||||
#define PWC_PD_WKUP_LVD2 (PWC_PDWKE2_VD2WKE << PWC_PD_WKUP2_POS)
|
||||
#define PWC_PD_WKUP_NMI (PWC_PDWKE2_NMIWKE << PWC_PD_WKUP2_POS)
|
||||
#define PWC_PD_WKUP_RTCPRD (PWC_PDWKE2_RTCPRDWKE << PWC_PD_WKUP2_POS)
|
||||
#define PWC_PD_WKUP_RTCALM (PWC_PDWKE2_RTCALMWKE << PWC_PD_WKUP2_POS)
|
||||
#define PWC_PD_WKUP_WKTM (PWC_PDWKE2_WKTMWKE << PWC_PD_WKUP2_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_WKUP_Trigger_Event_Sel Power down mode wakeup event selection to set trigger edge.
|
||||
* @{
|
||||
*/
|
||||
#define PWC_PD_WKUP_TRIG_LVD1 (PWC_PDWKES_VD1EGS)
|
||||
#define PWC_PD_WKUP_TRIG_LVD2 (PWC_PDWKES_VD2EGS)
|
||||
#define PWC_PD_WKUP_TRIG_WKUP0 (PWC_PDWKES_WK0EGS)
|
||||
#define PWC_PD_WKUP_TRIG_WKUP1 (PWC_PDWKES_WK1EGS)
|
||||
#define PWC_PD_WKUP_TRIG_WKUP2 (PWC_PDWKES_WK2EGS)
|
||||
#define PWC_PD_WKUP_TRIG_WKUP3 (PWC_PDWKES_WK3EGS)
|
||||
|
||||
#define PWC_PD_WKUP_TRIG_NMI (PWC_PDWKES_NMIEGS)
|
||||
#define PWC_PD_WKUP_TRIG_ALL (PWC_PD_WKUP_TRIG_LVD1 | PWC_PD_WKUP_TRIG_LVD2 | PWC_PD_WKUP_TRIG_WKUP0 | \
|
||||
PWC_PD_WKUP_TRIG_WKUP1 | PWC_PD_WKUP_TRIG_WKUP2 | PWC_PD_WKUP_TRIG_WKUP3 | \
|
||||
PWC_PD_WKUP_TRIG_NMI)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_WKUP_Trigger_Edge_Sel Power down mode wakeup trigger edge selection
|
||||
* @{
|
||||
*/
|
||||
#define PWC_PD_WKUP_TRIG_FALLING (0x00U)
|
||||
#define PWC_PD_WKUP_TRIG_RISING (0x01U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_WKUP_Event_Flag_Sel Power down mode wakeup Event status selection
|
||||
* @{
|
||||
*/
|
||||
#define PWC_PD_WKUP_FLAG0_POS (0U)
|
||||
#define PWC_PD_WKUP_FLAG1_POS (8U)
|
||||
#define PWC_PD_WKUP_FLAG_WKUP0 (PWC_PDWKF0_PTWK0F << PWC_PD_WKUP_FLAG0_POS)
|
||||
#define PWC_PD_WKUP_FLAG_WKUP1 (PWC_PDWKF0_PTWK1F << PWC_PD_WKUP_FLAG0_POS)
|
||||
#define PWC_PD_WKUP_FLAG_WKUP2 (PWC_PDWKF0_PTWK2F << PWC_PD_WKUP_FLAG0_POS)
|
||||
#define PWC_PD_WKUP_FLAG_WKUP3 (PWC_PDWKF0_PTWK3F << PWC_PD_WKUP_FLAG0_POS)
|
||||
#define PWC_PD_WKUP_FLAG_LVD1 (PWC_PDWKF0_VD1WKF << PWC_PD_WKUP_FLAG0_POS)
|
||||
#define PWC_PD_WKUP_FLAG_LVD2 (PWC_PDWKF0_VD2WKF << PWC_PD_WKUP_FLAG0_POS)
|
||||
#define PWC_PD_WKUP_FLAG_NMI (PWC_PDWKF0_NMIWKF << PWC_PD_WKUP_FLAG0_POS)
|
||||
#define PWC_PD_WKUP_FLAG_RTCPRD (PWC_PDWKF1_RTCPRDWKF << PWC_PD_WKUP_FLAG1_POS)
|
||||
#define PWC_PD_WKUP_FLAG_RTCALM (PWC_PDWKF1_RTCALMWKF << PWC_PD_WKUP_FLAG1_POS)
|
||||
#define PWC_PD_WKUP_FLAG_WKTM (PWC_PDWKF1_WKTMWKF << PWC_PD_WKUP_FLAG1_POS)
|
||||
|
||||
#define PWC_PD_WKUP_FLAG_ALL (PWC_PD_WKUP_FLAG_WKUP0 | PWC_PD_WKUP_FLAG_WKUP1 | PWC_PD_WKUP_FLAG_WKUP2 | \
|
||||
PWC_PD_WKUP_FLAG_WKUP3 | PWC_PD_WKUP_FLAG_LVD1 | PWC_PD_WKUP_FLAG_LVD2 | \
|
||||
PWC_PD_WKUP_FLAG_NMI | PWC_PD_WKUP_FLAG_RTCPRD | PWC_PD_WKUP_FLAG_RTCALM | \
|
||||
PWC_PD_WKUP_FLAG_WKTM)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_Monitor_Power PWC Power Monitor voltage definition
|
||||
* @{
|
||||
*/
|
||||
#define PWC_PWR_MON_IREF (0x00U) /*!< Internal reference voltage */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_WKT_State PWC WKT State
|
||||
* @{
|
||||
*/
|
||||
#define PWC_WKT_OFF (0x00U)
|
||||
#define PWC_WKT_ON (PWC_WKTCR_WKTCE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_WKT_Clock_Source PWC WKT Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define PWC_WKT_CLK_SRC_64HZ ((0x00U << PWC_WKTCR_WKCKS_POS)) /*!< 64Hz Clock */
|
||||
#define PWC_WKT_CLK_SRC_XTAL32 ((0x01U << PWC_WKTCR_WKCKS_POS)) /*!< XTAL32 Clock */
|
||||
#define PWC_WKT_CLK_SRC_LRC ((0x02U << PWC_WKTCR_WKCKS_POS)) /*!< LRC Clock */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_Ldo_Sel PWC LDO Selection
|
||||
* @{
|
||||
*/
|
||||
#define PWC_LDO_HRC (PWC_PWRC1_VHRCSD)
|
||||
#define PWC_LDO_PLL (PWC_PWRC1_VPLLSD)
|
||||
#define PWC_LDO_MASK (PWC_LDO_HRC | PWC_LDO_PLL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PWC_REG_Write_Unlock_Code PWC register unlock code.
|
||||
* @brief Lock/unlock Code for each module
|
||||
* PWC_UNLOCK_CODE0:
|
||||
* Below registers are locked in CLK module.
|
||||
* XTALCFGR, XTALSTBCR, XTALCR, XTALSTDCR, XTALSTDSR, HRCTRM, HRCCR,
|
||||
* MRCTRM, MRCCR, PLLCFGR, PLLCR, UPLLCFGR, UPLLCR, OSCSTBSR, CKSWR,
|
||||
* SCFGR, USBCKCFGR, TPIUCKCFGR, MCO1CFGR, MCO2CFGR, XTAL32CR,
|
||||
* XTALC32CFGR, XTAL32NFR, LRCCR, LRCTRM.
|
||||
* PWC_UNLOCK_CODE1:
|
||||
* Below registers are locked in PWC module.
|
||||
* PWRC0, PWRC1, PWRC2, PWRC3, PDWKE0, PDWKE1, PDWKE2, PDWKES, PDWKF0,
|
||||
* PDWKF1, PWCMR, PWR_STPMCR, RAMPC0, RAMOPM.
|
||||
* Below registers are locked in CLK module.
|
||||
* PERICKSEL, I2SCKSEL,
|
||||
* Below register is locked in RMU module.
|
||||
* RSTF0
|
||||
* PWC_UNLOCK_CODE2:
|
||||
* Below registers are locked in PWC module.
|
||||
* PVDCR0, PVDCR1, PVDFCR, PVDLCR, PVDICR, PVDDSR
|
||||
* @{
|
||||
*/
|
||||
#define PWC_WRITE_ENABLE (0xA500U)
|
||||
#define PWC_UNLOCK_CODE0 (0xA501U)
|
||||
#define PWC_UNLOCK_CODE1 (0xA502U)
|
||||
#define PWC_UNLOCK_CODE2 (0xA508U)
|
||||
|
||||
/**
|
||||
* @brief PWC FCG0 Unlock/Lock code
|
||||
*/
|
||||
#define PWC_FCG0_REG_UNLOCK_KEY (0xA5A50001UL)
|
||||
#define PWC_FCG0_REG_LOCK_KEY (0xA5A50000UL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup PWC_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Lock PWC, CLK, RMU register.
|
||||
* @param [in] u16Module Lock code for each module.
|
||||
* @arg PWC_UNLOCK_CODE0
|
||||
* @arg PWC_UNLOCK_CODE1
|
||||
* @arg PWC_UNLOCK_CODE2
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void PWC_REG_Lock(uint16_t u16Module)
|
||||
{
|
||||
CM_PWC->FPRC = (PWC_WRITE_ENABLE | (uint16_t)((uint16_t)(~u16Module) & (CM_PWC->FPRC)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unlock PWC, CLK, RMU register.
|
||||
* @param [in] u16Module Unlock code for each module.
|
||||
* @arg PWC_UNLOCK_CODE0
|
||||
* @arg PWC_UNLOCK_CODE1
|
||||
* @arg PWC_UNLOCK_CODE2
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void PWC_REG_Unlock(uint16_t u16Module)
|
||||
{
|
||||
SET_REG16_BIT(CM_PWC->FPRC, u16Module);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Lock PWC_FCG0 register .
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void PWC_FCG0_REG_Lock(void)
|
||||
{
|
||||
WRITE_REG32(CM_PWC->FCG0PC, PWC_FCG0_REG_LOCK_KEY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unlock PWR_FCG0 register.
|
||||
* @param None
|
||||
* @retval None
|
||||
* @note Call this function before FCG_Fcg0PeriphClockCmd()
|
||||
*/
|
||||
__STATIC_INLINE void PWC_FCG0_REG_Unlock(void)
|
||||
{
|
||||
WRITE_REG32(CM_PWC->FCG0PC, PWC_FCG0_REG_UNLOCK_KEY);
|
||||
}
|
||||
|
||||
/* PWC PD Function */
|
||||
void PWC_PD_Enter(void);
|
||||
int32_t PWC_PD_StructInit(stc_pwc_pd_mode_config_t *pstcPDModeConfig);
|
||||
int32_t PWC_PD_Config(const stc_pwc_pd_mode_config_t *pstcPDModeConfig);
|
||||
void PWC_PD_WakeupCmd(uint32_t u32Event, en_functional_state_t enNewState);
|
||||
void PWC_PD_SetWakeupTriggerEdge(uint8_t u8Event, uint8_t u8TrigEdge);
|
||||
en_flag_status_t PWC_PD_GetWakeupStatus(uint16_t u16Flag);
|
||||
void PWC_PD_ClearWakeupStatus(uint16_t u16Flag);
|
||||
void PWC_PD_PeriphRamCmd(uint32_t u32PeriphRam, en_functional_state_t enNewState);
|
||||
void PWC_PD_VdrCmd(en_functional_state_t enNewState);
|
||||
|
||||
/* PWC WKTM Function */
|
||||
void PWC_WKT_Config(uint16_t u16ClkSrc, uint16_t u16CmpVal);
|
||||
void PWC_WKT_SetCompareValue(uint16_t u16CmpVal);
|
||||
uint16_t PWC_WKT_GetCompareValue(void);
|
||||
void PWC_WKT_Cmd(en_functional_state_t enNewState);
|
||||
en_flag_status_t PWC_WKT_GetStatus(void);
|
||||
void PWC_WKT_ClearStatus(void);
|
||||
|
||||
void PWC_RamModeConfig(uint16_t u16Mode);
|
||||
|
||||
/* PWC Sleep Function */
|
||||
void PWC_SLEEP_Enter(void);
|
||||
|
||||
/* PWC Stop Function */
|
||||
void PWC_STOP_Enter(uint8_t u8StopType);
|
||||
int32_t PWC_STOP_StructInit(stc_pwc_stop_mode_config_t *pstcStopConfig);
|
||||
int32_t PWC_STOP_Config(const stc_pwc_stop_mode_config_t *pstcStopConfig);
|
||||
void PWC_STOP_ClockSelect(uint8_t u8Clock);
|
||||
void PWC_STOP_NvicBackup(void);
|
||||
void PWC_STOP_NvicRecover(void);
|
||||
void PWC_STOP_ClockBackup(void);
|
||||
void PWC_STOP_ClockRecover(void);
|
||||
void PWC_STOP_IrqClockBackup(void);
|
||||
void PWC_STOP_IrqClockRecover(void);
|
||||
void PWC_STOP_SetDrv(uint8_t u8StopDrv);
|
||||
void PWC_STOP_FlashWaitCmd(en_functional_state_t enNewState);
|
||||
|
||||
/* PWC Speed Switch Function */
|
||||
int32_t PWC_HighSpeedToLowSpeed(void);
|
||||
int32_t PWC_LowSpeedToHighSpeed(void);
|
||||
int32_t PWC_HighSpeedToHighPerformance(void);
|
||||
int32_t PWC_HighPerformanceToHighSpeed(void);
|
||||
int32_t PWC_LowSpeedToHighPerformance(void);
|
||||
int32_t PWC_HighPerformanceToLowSpeed(void);
|
||||
|
||||
/* PWC LDO Function */
|
||||
void PWC_LDO_Cmd(uint16_t u16Ldo, en_functional_state_t enNewState);
|
||||
|
||||
/* PWC LVD/PVD Function */
|
||||
int32_t PWC_LVD_Init(uint8_t u8Ch, const stc_pwc_lvd_init_t *pstcLvdInit);
|
||||
void PWC_LVD_DeInit(uint8_t u8Ch);
|
||||
int32_t PWC_LVD_StructInit(stc_pwc_lvd_init_t *pstcLvdInit);
|
||||
void PWC_LVD_Cmd(uint8_t u8Ch, en_functional_state_t enNewState);
|
||||
void PWC_LVD_ExtInputCmd(en_functional_state_t enNewState);
|
||||
void PWC_LVD_CompareOutputCmd(uint8_t u8Ch, en_functional_state_t enNewState);
|
||||
void PWC_LVD_DigitalFilterCmd(uint8_t u8Ch, en_functional_state_t enNewState);
|
||||
void PWC_LVD_SetFilterClock(uint8_t u8Ch, uint32_t u32Clock);
|
||||
void PWC_LVD_SetThresholdVoltage(uint8_t u8Ch, uint32_t u32Voltage);
|
||||
void PWC_LVD_ClearStatus(uint8_t u8Flag);
|
||||
en_flag_status_t PWC_LVD_GetStatus(uint8_t u8Flag);
|
||||
|
||||
/* PWC Power Monitor Function */
|
||||
void PWC_PowerMonitorCmd(en_functional_state_t enNewState);
|
||||
|
||||
/* PWC RAM Function */
|
||||
|
||||
void PWC_XTAL32_PowerCmd(en_functional_state_t enNewState);
|
||||
void PWC_RetSram_PowerCmd(en_functional_state_t enNewState);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_PWC_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_PWC_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,446 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_qspi.h
|
||||
* @brief This file contains all the functions prototypes of the QSPI driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2023-09-30 CDT Modify return value type of QSPI_DeInit function
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_QSPI_H__
|
||||
#define __HC32_LL_QSPI_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_QSPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_QSPI_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup QSPI_Global_Types QSPI Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief QSPI initialization structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32ClockDiv; /*!< Specifies the clock division.
|
||||
This parameter can be a value of @ref QSPI_Clock_Division */
|
||||
uint32_t u32SpiMode; /*!< Specifies the SPI mode.
|
||||
This parameter can be a value of @ref QSPI_SPI_Mode */
|
||||
uint32_t u32PrefetchMode; /*!< Specifies the prefetch mode.
|
||||
This parameter can be a value of @ref QSPI_Prefetch_Mode */
|
||||
uint32_t u32ReadMode; /*!< Specifies the read mode.
|
||||
This parameter can be a value of @ref QSPI_Read_Mode */
|
||||
uint32_t u32DummyCycle; /*!< Specifies the number of dummy cycles.
|
||||
This parameter can be a value of @ref QSPI_Dummy_Cycle */
|
||||
uint32_t u32AddrWidth; /*!< Specifies the address width.
|
||||
This parameter can be a value of @ref QSPI_Addr_Width */
|
||||
uint32_t u32SetupTime; /*!< Specifies the advance time of QSSN setup.
|
||||
This parameter can be a value of @ref QSPI_QSSN_Setup_Time */
|
||||
uint32_t u32ReleaseTime; /*!< Specifies the delay time of QSSN release.
|
||||
This parameter can be a value of @ref QSPI_QSSN_Release_Time */
|
||||
uint32_t u32IntervalTime; /*!< Specifies the minimum interval time of QSSN.
|
||||
This parameter can be a value of @ref QSPI_QSSN_Interval_Time */
|
||||
} stc_qspi_init_t;
|
||||
|
||||
/**
|
||||
* @brief QSPI Custom read mode structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32InstrProtocol; /*!< Specifies the instruction stage protocol.
|
||||
This parameter can be a value of @ref QSPI_Instruction_Protocol */
|
||||
uint32_t u32AddrProtocol; /*!< Specifies the address stage protocol.
|
||||
This parameter can be a value of @ref QSPI_Addr_Protocol */
|
||||
uint32_t u32DataProtocol; /*!< Specifies the data stage protocol.
|
||||
This parameter can be a value of @ref QSPI_Data_Protocol */
|
||||
uint8_t u8InstrCode; /*!< Specifies the instruction code in custom read mode.
|
||||
This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF */
|
||||
} stc_qspi_custom_mode_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup QSPI_Global_Macros QSPI Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* QSPI memory mapping base and end address */
|
||||
#define QSPI_ROM_BASE (0x98000000UL)
|
||||
#define QSPI_ROM_END (0x9BFFFFFFUL)
|
||||
|
||||
/**
|
||||
* @defgroup QSPI_Clock_Division QSPI Clock Division
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_CLK_DIV2 (0x01UL << QSPI_CR_DIV_POS) /*!< Clock division by 2 */
|
||||
#define QSPI_CLK_DIV3 (0x02UL << QSPI_CR_DIV_POS) /*!< Clock division by 3 */
|
||||
#define QSPI_CLK_DIV4 (0x03UL << QSPI_CR_DIV_POS) /*!< Clock division by 4 */
|
||||
#define QSPI_CLK_DIV5 (0x04UL << QSPI_CR_DIV_POS) /*!< Clock division by 5 */
|
||||
#define QSPI_CLK_DIV6 (0x05UL << QSPI_CR_DIV_POS) /*!< Clock division by 6 */
|
||||
#define QSPI_CLK_DIV7 (0x06UL << QSPI_CR_DIV_POS) /*!< Clock division by 7 */
|
||||
#define QSPI_CLK_DIV8 (0x07UL << QSPI_CR_DIV_POS) /*!< Clock division by 8 */
|
||||
#define QSPI_CLK_DIV9 (0x08UL << QSPI_CR_DIV_POS) /*!< Clock division by 9 */
|
||||
#define QSPI_CLK_DIV10 (0x09UL << QSPI_CR_DIV_POS) /*!< Clock division by 10 */
|
||||
#define QSPI_CLK_DIV11 (0x0AUL << QSPI_CR_DIV_POS) /*!< Clock division by 11 */
|
||||
#define QSPI_CLK_DIV12 (0x0BUL << QSPI_CR_DIV_POS) /*!< Clock division by 12 */
|
||||
#define QSPI_CLK_DIV13 (0x0CUL << QSPI_CR_DIV_POS) /*!< Clock division by 13 */
|
||||
#define QSPI_CLK_DIV14 (0x0DUL << QSPI_CR_DIV_POS) /*!< Clock division by 14 */
|
||||
#define QSPI_CLK_DIV15 (0x0EUL << QSPI_CR_DIV_POS) /*!< Clock division by 15 */
|
||||
#define QSPI_CLK_DIV16 (0x0FUL << QSPI_CR_DIV_POS) /*!< Clock division by 16 */
|
||||
#define QSPI_CLK_DIV17 (0x10UL << QSPI_CR_DIV_POS) /*!< Clock division by 17 */
|
||||
#define QSPI_CLK_DIV18 (0x11UL << QSPI_CR_DIV_POS) /*!< Clock division by 18 */
|
||||
#define QSPI_CLK_DIV19 (0x12UL << QSPI_CR_DIV_POS) /*!< Clock division by 19 */
|
||||
#define QSPI_CLK_DIV20 (0x13UL << QSPI_CR_DIV_POS) /*!< Clock division by 20 */
|
||||
#define QSPI_CLK_DIV21 (0x14UL << QSPI_CR_DIV_POS) /*!< Clock division by 21 */
|
||||
#define QSPI_CLK_DIV22 (0x15UL << QSPI_CR_DIV_POS) /*!< Clock division by 22 */
|
||||
#define QSPI_CLK_DIV23 (0x16UL << QSPI_CR_DIV_POS) /*!< Clock division by 23 */
|
||||
#define QSPI_CLK_DIV24 (0x17UL << QSPI_CR_DIV_POS) /*!< Clock division by 24 */
|
||||
#define QSPI_CLK_DIV25 (0x18UL << QSPI_CR_DIV_POS) /*!< Clock division by 25 */
|
||||
#define QSPI_CLK_DIV26 (0x19UL << QSPI_CR_DIV_POS) /*!< Clock division by 26 */
|
||||
#define QSPI_CLK_DIV27 (0x1AUL << QSPI_CR_DIV_POS) /*!< Clock division by 27 */
|
||||
#define QSPI_CLK_DIV28 (0x1BUL << QSPI_CR_DIV_POS) /*!< Clock division by 28 */
|
||||
#define QSPI_CLK_DIV29 (0x1CUL << QSPI_CR_DIV_POS) /*!< Clock division by 29 */
|
||||
#define QSPI_CLK_DIV30 (0x1DUL << QSPI_CR_DIV_POS) /*!< Clock division by 30 */
|
||||
#define QSPI_CLK_DIV31 (0x1EUL << QSPI_CR_DIV_POS) /*!< Clock division by 31 */
|
||||
#define QSPI_CLK_DIV32 (0x1FUL << QSPI_CR_DIV_POS) /*!< Clock division by 32 */
|
||||
#define QSPI_CLK_DIV33 (0x20UL << QSPI_CR_DIV_POS) /*!< Clock division by 33 */
|
||||
#define QSPI_CLK_DIV34 (0x21UL << QSPI_CR_DIV_POS) /*!< Clock division by 34 */
|
||||
#define QSPI_CLK_DIV35 (0x22UL << QSPI_CR_DIV_POS) /*!< Clock division by 35 */
|
||||
#define QSPI_CLK_DIV36 (0x23UL << QSPI_CR_DIV_POS) /*!< Clock division by 36 */
|
||||
#define QSPI_CLK_DIV37 (0x24UL << QSPI_CR_DIV_POS) /*!< Clock division by 37 */
|
||||
#define QSPI_CLK_DIV38 (0x25UL << QSPI_CR_DIV_POS) /*!< Clock division by 38 */
|
||||
#define QSPI_CLK_DIV39 (0x26UL << QSPI_CR_DIV_POS) /*!< Clock division by 39 */
|
||||
#define QSPI_CLK_DIV40 (0x27UL << QSPI_CR_DIV_POS) /*!< Clock division by 40 */
|
||||
#define QSPI_CLK_DIV41 (0x28UL << QSPI_CR_DIV_POS) /*!< Clock division by 41 */
|
||||
#define QSPI_CLK_DIV42 (0x29UL << QSPI_CR_DIV_POS) /*!< Clock division by 42 */
|
||||
#define QSPI_CLK_DIV43 (0x2AUL << QSPI_CR_DIV_POS) /*!< Clock division by 43 */
|
||||
#define QSPI_CLK_DIV44 (0x2BUL << QSPI_CR_DIV_POS) /*!< Clock division by 44 */
|
||||
#define QSPI_CLK_DIV45 (0x2CUL << QSPI_CR_DIV_POS) /*!< Clock division by 45 */
|
||||
#define QSPI_CLK_DIV46 (0x2DUL << QSPI_CR_DIV_POS) /*!< Clock division by 46 */
|
||||
#define QSPI_CLK_DIV47 (0x2EUL << QSPI_CR_DIV_POS) /*!< Clock division by 47 */
|
||||
#define QSPI_CLK_DIV48 (0x2FUL << QSPI_CR_DIV_POS) /*!< Clock division by 48 */
|
||||
#define QSPI_CLK_DIV49 (0x30UL << QSPI_CR_DIV_POS) /*!< Clock division by 49 */
|
||||
#define QSPI_CLK_DIV50 (0x31UL << QSPI_CR_DIV_POS) /*!< Clock division by 50 */
|
||||
#define QSPI_CLK_DIV51 (0x32UL << QSPI_CR_DIV_POS) /*!< Clock division by 51 */
|
||||
#define QSPI_CLK_DIV52 (0x33UL << QSPI_CR_DIV_POS) /*!< Clock division by 52 */
|
||||
#define QSPI_CLK_DIV53 (0x34UL << QSPI_CR_DIV_POS) /*!< Clock division by 53 */
|
||||
#define QSPI_CLK_DIV54 (0x35UL << QSPI_CR_DIV_POS) /*!< Clock division by 54 */
|
||||
#define QSPI_CLK_DIV55 (0x36UL << QSPI_CR_DIV_POS) /*!< Clock division by 55 */
|
||||
#define QSPI_CLK_DIV56 (0x37UL << QSPI_CR_DIV_POS) /*!< Clock division by 56 */
|
||||
#define QSPI_CLK_DIV57 (0x38UL << QSPI_CR_DIV_POS) /*!< Clock division by 57 */
|
||||
#define QSPI_CLK_DIV58 (0x39UL << QSPI_CR_DIV_POS) /*!< Clock division by 58 */
|
||||
#define QSPI_CLK_DIV59 (0x3AUL << QSPI_CR_DIV_POS) /*!< Clock division by 59 */
|
||||
#define QSPI_CLK_DIV60 (0x3BUL << QSPI_CR_DIV_POS) /*!< Clock division by 60 */
|
||||
#define QSPI_CLK_DIV61 (0x3CUL << QSPI_CR_DIV_POS) /*!< Clock division by 61 */
|
||||
#define QSPI_CLK_DIV62 (0x3DUL << QSPI_CR_DIV_POS) /*!< Clock division by 62 */
|
||||
#define QSPI_CLK_DIV63 (0x3EUL << QSPI_CR_DIV_POS) /*!< Clock division by 63 */
|
||||
#define QSPI_CLK_DIV64 (0x3FUL << QSPI_CR_DIV_POS) /*!< Clock division by 64 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup QSPI_SPI_Mode QSPI SPI Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_SPI_MD0 (0UL) /*!< Selects SPI mode 0 */
|
||||
#define QSPI_SPI_MD3 (QSPI_CR_SPIMD3) /*!< Selects SPI mode 3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup QSPI_Prefetch_Mode QSPI Prefetch Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_PREFETCH_MD_INVD (0UL) /*!< Disable prefetch */
|
||||
#define QSPI_PREFETCH_MD_EDGE_STOP (QSPI_CR_PFE) /*!< Stop prefetch at the edge of byte */
|
||||
#define QSPI_PREFETCH_MD_IMMED_STOP (QSPI_CR_PFE | QSPI_CR_PFSAE) /*!< Stop prefetch at current position immediately */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup QSPI_Read_Mode QSPI Read Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_RD_MD_STD_RD (0UL) /*!< Standard read mode (no dummy cycles) */
|
||||
#define QSPI_RD_MD_FAST_RD (0x01UL << QSPI_CR_MDSEL_POS) /*!< Fast read mode (dummy cycles between address and data) */
|
||||
#define QSPI_RD_MD_DUAL_OUTPUT_FAST_RD (0x02UL << QSPI_CR_MDSEL_POS) /*!< Fast read dual output mode (data on 2 lines) */
|
||||
#define QSPI_RD_MD_DUAL_IO_FAST_RD (0x03UL << QSPI_CR_MDSEL_POS) /*!< Fast read dual I/O mode (address and data on 2 lines) */
|
||||
#define QSPI_RD_MD_QUAD_OUTPUT_FAST_RD (0x04UL << QSPI_CR_MDSEL_POS) /*!< Fast read quad output mode (data on 4 lines) */
|
||||
#define QSPI_RD_MD_QUAD_IO_FAST_RD (0x05UL << QSPI_CR_MDSEL_POS) /*!< Fast read quad I/O mode (address and data on 4 lines) */
|
||||
#define QSPI_RD_MD_CUSTOM_STANDARD_RD (0x06UL << QSPI_CR_MDSEL_POS) /*!< Custom standard read mode */
|
||||
#define QSPI_RD_MD_CUSTOM_FAST_RD (0x07UL << QSPI_CR_MDSEL_POS) /*!< Custom fast read mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup QSPI_Dummy_Cycle QSPI Dummy Cycle
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_DUMMY_CYCLE3 (0UL) /*!< Dummy cycle is 3 */
|
||||
#define QSPI_DUMMY_CYCLE4 (0x01UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 4 */
|
||||
#define QSPI_DUMMY_CYCLE5 (0x02UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 5 */
|
||||
#define QSPI_DUMMY_CYCLE6 (0x03UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 6 */
|
||||
#define QSPI_DUMMY_CYCLE7 (0x04UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 7 */
|
||||
#define QSPI_DUMMY_CYCLE8 (0x05UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 8 */
|
||||
#define QSPI_DUMMY_CYCLE9 (0x06UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 9 */
|
||||
#define QSPI_DUMMY_CYCLE10 (0x07UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 10 */
|
||||
#define QSPI_DUMMY_CYCLE11 (0x08UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 11 */
|
||||
#define QSPI_DUMMY_CYCLE12 (0x09UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 12 */
|
||||
#define QSPI_DUMMY_CYCLE13 (0x0AUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 13 */
|
||||
#define QSPI_DUMMY_CYCLE14 (0x0BUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 14 */
|
||||
#define QSPI_DUMMY_CYCLE15 (0x0CUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 15 */
|
||||
#define QSPI_DUMMY_CYCLE16 (0x0DUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 16 */
|
||||
#define QSPI_DUMMY_CYCLE17 (0x0EUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 15 */
|
||||
#define QSPI_DUMMY_CYCLE18 (0x0FUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 16 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup QSPI_Addr_Width QSPI Address Width
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_ADDR_WIDTH_8BIT (0x0U) /*!< QSPI address width is 8 bits */
|
||||
#define QSPI_ADDR_WIDTH_16BIT (QSPI_FCR_AWSL_0) /*!< QSPI address width is 16 bits */
|
||||
#define QSPI_ADDR_WIDTH_24BIT (QSPI_FCR_AWSL_1) /*!< QSPI address width is 24 bits */
|
||||
#define QSPI_ADDR_WIDTH_32BIT_INSTR_24BIT (QSPI_FCR_AWSL) /*!< QSPI address width is 32 bits and don't use 4-byte address read instruction code */
|
||||
#define QSPI_ADDR_WIDTH_32BIT_INSTR_32BIT (QSPI_FCR_AWSL | QSPI_FCR_FOUR_BIC) /*!< QSPI address width is 32 bits and use 4-byte address read instruction code */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup QSPI_QSSN_Setup_Time QSPI QSSN Setup Time
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_QSSN_SETUP_ADVANCE_QSCK0P5 (0UL) /*!< Output QSSN signal 0.5 QSCK before the first rising edge of QSCK */
|
||||
#define QSPI_QSSN_SETUP_ADVANCE_QSCK1P5 (QSPI_FCR_SSNLD) /*!< Output QSSN signal 1.5 QSCK before the first rising edge of QSCK */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup QSPI_QSSN_Release_Time QSPI QSSN Release Time
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_QSSN_RELEASE_DELAY_QSCK0P5 (0UL) /*!< Release QSSN signal 0.5 QSCK after the last rising edge of QSCK */
|
||||
#define QSPI_QSSN_RELEASE_DELAY_QSCK1P5 (QSPI_FCR_SSNHD) /*!< Release QSSN signal 1.5 QSCK after the last rising edge of QSCK */
|
||||
#define QSPI_QSSN_RELEASE_DELAY_QSCK32 (QSPI_CSCR_SSNW_0 << 8U) /*!< Release QSSN signal 32 QSCK after the last rising edge of QSCK */
|
||||
#define QSPI_QSSN_RELEASE_DELAY_QSCK128 (QSPI_CSCR_SSNW_1 << 8U) /*!< Release QSSN signal 128 QSCK after the last rising edge of QSCK */
|
||||
#define QSPI_QSSN_RELEASE_DELAY_INFINITE (QSPI_CSCR_SSNW << 8U) /*!< Never release QSSN signal after the last rising edge of QSCK */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup QSPI_QSSN_Interval_Time QSPI QSSN Interval Time
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_QSSN_INTERVAL_QSCK1 (0UL) /*!< Minimum interval time is 1 QSCK */
|
||||
#define QSPI_QSSN_INTERVAL_QSCK2 (0x01UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 2 QSCK */
|
||||
#define QSPI_QSSN_INTERVAL_QSCK3 (0x02UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 3 QSCK */
|
||||
#define QSPI_QSSN_INTERVAL_QSCK4 (0x03UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 4 QSCK */
|
||||
#define QSPI_QSSN_INTERVAL_QSCK5 (0x04UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 5 QSCK */
|
||||
#define QSPI_QSSN_INTERVAL_QSCK6 (0x05UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 6 QSCK */
|
||||
#define QSPI_QSSN_INTERVAL_QSCK7 (0x06UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 7 QSCK */
|
||||
#define QSPI_QSSN_INTERVAL_QSCK8 (0x07UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 8 QSCK */
|
||||
#define QSPI_QSSN_INTERVAL_QSCK9 (0x08UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 9 QSCK */
|
||||
#define QSPI_QSSN_INTERVAL_QSCK10 (0x09UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 10 QSCK */
|
||||
#define QSPI_QSSN_INTERVAL_QSCK11 (0x0AUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 11 QSCK */
|
||||
#define QSPI_QSSN_INTERVAL_QSCK12 (0x0BUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 12 QSCK */
|
||||
#define QSPI_QSSN_INTERVAL_QSCK13 (0x0CUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 13 QSCK */
|
||||
#define QSPI_QSSN_INTERVAL_QSCK14 (0x0DUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 14 QSCK */
|
||||
#define QSPI_QSSN_INTERVAL_QSCK15 (0x0EUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 15 QSCK */
|
||||
#define QSPI_QSSN_INTERVAL_QSCK16 (0x0FUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 16 QSCK */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup QSPI_Instruction_Protocol QSPI Instruction Protocol
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_INSTR_PROTOCOL_1LINE (0x0U) /*!< Instruction on 1 line */
|
||||
#define QSPI_INSTR_PROTOCOL_2LINE (QSPI_CR_IPRSL_0) /*!< Instruction on 2 lines */
|
||||
#define QSPI_INSTR_PROTOCOL_4LINE (QSPI_CR_IPRSL_1) /*!< Instruction on 4 lines */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup QSPI_Addr_Protocol QSPI Address Protocol
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_ADDR_PROTOCOL_1LINE (0x0U) /*!< Address on 1 line */
|
||||
#define QSPI_ADDR_PROTOCOL_2LINE (QSPI_CR_APRSL_0) /*!< Address on 2 lines */
|
||||
#define QSPI_ADDR_PROTOCOL_4LINE (QSPI_CR_APRSL_1) /*!< Address on 4 lines */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup QSPI_Data_Protocol QSPI Data Protocol
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_DATA_PROTOCOL_1LINE (0x0U) /*!< Data on 1 line */
|
||||
#define QSPI_DATA_PROTOCOL_2LINE (QSPI_CR_DPRSL_0) /*!< Data on 2 lines */
|
||||
#define QSPI_DATA_PROTOCOL_4LINE (QSPI_CR_DPRSL_1) /*!< Data on 4 lines */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup QSPI_WP_Pin_Level QSPI WP Pin Level
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_WP_PIN_LOW (0x0U) /*!< WP(QSIO2) pin output low */
|
||||
#define QSPI_WP_PIN_HIGH (QSPI_FCR_WPOL) /*!< WP(QSIO2) pin output high */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup QSPI_Status_Flag QSPI Status Flag
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_FLAG_DIRECT_COMM_BUSY (QSPI_SR_BUSY) /*!< Serial transfer being processed */
|
||||
#define QSPI_FLAG_XIP_MD (QSPI_SR_XIPF) /*!< XIP mode */
|
||||
#define QSPI_FLAG_ROM_ACCESS_ERR (QSPI_SR_RAER) /*!< ROM access detection status in direct communication mode */
|
||||
#define QSPI_FLAG_PREFETCH_BUF_FULL (QSPI_SR_PFFUL) /*!< Prefetch buffer is full */
|
||||
#define QSPI_FLAG_PREFETCH_STOP (QSPI_SR_PFAN) /*!< Prefetch function operating */
|
||||
|
||||
#define QSPI_FLAG_ALL (QSPI_FLAG_DIRECT_COMM_BUSY | QSPI_FLAG_XIP_MD | \
|
||||
QSPI_FLAG_ROM_ACCESS_ERR | QSPI_FLAG_PREFETCH_BUF_FULL | \
|
||||
QSPI_FLAG_PREFETCH_STOP)
|
||||
#define QSPI_FLAG_CLR_ALL (QSPI_FLAG_ROM_ACCESS_ERR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup QSPI_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write data in direct communication mode.
|
||||
* @param [in] u8Value Byte data.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void QSPI_WriteDirectCommValue(uint8_t u8Value)
|
||||
{
|
||||
WRITE_REG32(CM_QSPI->DCOM, u8Value);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read data in direct communication mode.
|
||||
* @param None
|
||||
* @retval uint8_t Byte data.
|
||||
*/
|
||||
__STATIC_INLINE uint8_t QSPI_ReadDirectCommValue(void)
|
||||
{
|
||||
return (uint8_t)CM_QSPI->DCOM;
|
||||
}
|
||||
|
||||
/* Initialization and configuration functions */
|
||||
int32_t QSPI_DeInit(void);
|
||||
int32_t QSPI_Init(const stc_qspi_init_t *pstcQspiInit);
|
||||
int32_t QSPI_StructInit(stc_qspi_init_t *pstcQspiInit);
|
||||
void QSPI_SetWpPinLevel(uint32_t u32Level);
|
||||
void QSPI_SetPrefetchMode(uint32_t u32Mode);
|
||||
void QSPI_SelectMemoryBlock(uint8_t u8Block);
|
||||
void QSPI_SetReadMode(uint32_t u32Mode);
|
||||
int32_t QSPI_CustomReadConfig(const stc_qspi_custom_mode_t *pstcCustomMode);
|
||||
void QSPI_XipModeCmd(uint8_t u8ModeCode, en_functional_state_t enNewState);
|
||||
|
||||
/* Transfer and receive data functions */
|
||||
void QSPI_EnterDirectCommMode(void);
|
||||
void QSPI_ExitDirectCommMode(void);
|
||||
void QSPI_WriteDirectCommValue(uint8_t u8Value);
|
||||
uint8_t QSPI_ReadDirectCommValue(void);
|
||||
|
||||
/* Interrupt and flag management functions */
|
||||
uint8_t QSPI_GetPrefetchBufSize(void);
|
||||
en_flag_status_t QSPI_GetStatus(uint32_t u32Flag);
|
||||
void QSPI_ClearStatus(uint32_t u32Flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_QSPI_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_QSPI_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,128 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_rmu.h
|
||||
* @brief This file contains all the functions prototypes of the RMU driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_RMU_H__
|
||||
#define __HC32_LL_RMU_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_RMU
|
||||
* @{
|
||||
*/
|
||||
#if (LL_RMU_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup RMU_Global_Macros RMU Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup RMU_ResetCause Rmu reset cause
|
||||
* @{
|
||||
*/
|
||||
#define RMU_FLAG_PWR_ON (RMU_RSTF0_PORF) /*!< Power on reset */
|
||||
#define RMU_FLAG_PIN (RMU_RSTF0_PINRF) /*!< Reset pin reset */
|
||||
#define RMU_FLAG_BROWN_OUT (RMU_RSTF0_BORF) /*!< Brown-out reset */
|
||||
#define RMU_FLAG_PVD1 (RMU_RSTF0_PVD1RF) /*!< Program voltage Detection 1 reset */
|
||||
#define RMU_FLAG_PVD2 (RMU_RSTF0_PVD2RF) /*!< Program voltage Detection 2 reset */
|
||||
#define RMU_FLAG_WDT (RMU_RSTF0_WDRF) /*!< Watchdog timer reset */
|
||||
#define RMU_FLAG_SWDT (RMU_RSTF0_SWDRF) /*!< Special watchdog timer reset */
|
||||
#define RMU_FLAG_PWR_DOWN (RMU_RSTF0_PDRF) /*!< Power down reset */
|
||||
#define RMU_FLAG_SW (RMU_RSTF0_SWRF) /*!< Software reset */
|
||||
#define RMU_FLAG_MPU_ERR (RMU_RSTF0_MPUERF) /*!< Mpu error reset */
|
||||
#define RMU_FLAG_RAM_PARITY_ERR (RMU_RSTF0_RAPERF) /*!< Ram parity error reset */
|
||||
#define RMU_FLAG_RAM_ECC (RMU_RSTF0_RAECRF) /*!< Ram ECC reset */
|
||||
#define RMU_FLAG_CLK_ERR (RMU_RSTF0_CKFERF) /*!< Clk frequency error reset */
|
||||
#define RMU_FLAG_XTAL_ERR (RMU_RSTF0_XTALERF) /*!< Xtal error reset */
|
||||
#define RMU_FLAG_MX (RMU_RSTF0_MULTIRF) /*!< Multiply reset cause */
|
||||
#define RMU_FLAG_ALL (RMU_FLAG_PWR_ON | RMU_FLAG_PIN | RMU_FLAG_BROWN_OUT | RMU_FLAG_PVD1 | \
|
||||
RMU_FLAG_PVD2 | RMU_FLAG_WDT | RMU_FLAG_SWDT | RMU_FLAG_PWR_DOWN | \
|
||||
RMU_FLAG_SW | RMU_FLAG_MPU_ERR | RMU_FLAG_RAM_PARITY_ERR | RMU_FLAG_RAM_ECC | \
|
||||
RMU_FLAG_CLK_ERR | RMU_FLAG_XTAL_ERR | RMU_FLAG_MX)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup RMU_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
en_flag_status_t RMU_GetStatus(uint32_t u32RmuResetCause);
|
||||
void RMU_ClearStatus(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_RMU_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_RMU_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
|
||||
@@ -0,0 +1,364 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_rtc.h
|
||||
* @brief This file contains all the functions prototypes of the RTC driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_RTC_H__
|
||||
#define __HC32_LL_RTC_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_RTC_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup RTC_Global_Types RTC Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief RTC Init structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t u8ClockSrc; /*!< Specifies the RTC clock source.
|
||||
This parameter can be a value of @ref RTC_Clock_Source */
|
||||
uint8_t u8HourFormat; /*!< Specifies the RTC hour format.
|
||||
This parameter can be a value of @ref RTC_Hour_Format */
|
||||
uint8_t u8IntPeriod; /*!< Specifies the RTC interrupt period.
|
||||
This parameter can be a value of @ref RTC_Interrupt_Period */
|
||||
uint8_t u8ClockCompen; /*!< Specifies the validity of RTC clock compensation.
|
||||
This parameter can be a value of @ref RTC_Clock_Compensation */
|
||||
uint8_t u8CompenMode; /*!< Specifies the mode of RTC clock compensation.
|
||||
This parameter can be a value of @ref RTC_Clock_Compensation_Mode */
|
||||
uint16_t u16CompenValue; /*!< Specifies the value of RTC clock compensation.
|
||||
This parameter can be a number between Min_Data = 0 and Max_Data = 0x1FF */
|
||||
} stc_rtc_init_t;
|
||||
|
||||
/**
|
||||
* @brief RTC Date structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t u8Year; /*!< Specifies the RTC Year.
|
||||
This parameter can be a number between Min_Data = 0 and Max_Data = 99 */
|
||||
uint8_t u8Month; /*!< Specifies the RTC Month (in Decimal format).
|
||||
This parameter can be a value of @ref RTC_Month */
|
||||
uint8_t u8Day; /*!< Specifies the RTC Day.
|
||||
This parameter can be a number between Min_Data = 1 and Max_Data = 31 */
|
||||
uint8_t u8Weekday; /*!< Specifies the RTC Weekday.
|
||||
This parameter can be a value of @ref RTC_Weekday */
|
||||
} stc_rtc_date_t;
|
||||
|
||||
/**
|
||||
* @brief RTC Time structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t u8Hour; /*!< Specifies the RTC Hour.
|
||||
This parameter can be a number between Min_Data = 1 and Max_Data = 12 if the RTC_HOUR_FMT_12H is selected.
|
||||
This parameter can be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HOUR_FMT_24H is selected */
|
||||
uint8_t u8Minute; /*!< Specifies the RTC Minute.
|
||||
This parameter can be a number between Min_Data = 0 and Max_Data = 59 */
|
||||
uint8_t u8Second; /*!< Specifies the RTC Second.
|
||||
This parameter can be a number between Min_Data = 0 and Max_Data = 59 */
|
||||
uint8_t u8AmPm; /*!< Specifies the RTC Am/Pm Time (in RTC_HOUR_FMT_12H mode).
|
||||
This parameter can be a value of @ref RTC_Hour12_AM_PM */
|
||||
} stc_rtc_time_t;
|
||||
|
||||
/**
|
||||
* @brief RTC Alarm structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t u8AlarmHour; /*!< Specifies the RTC Alarm Hour.
|
||||
This parameter can be a number between Min_Data = 1 and Max_Data = 12 if the RTC_HOUR_FMT_12H is selected.
|
||||
This parameter can be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HOUR_FMT_24H is selected */
|
||||
uint8_t u8AlarmMinute; /*!< Specifies the RTC Alarm Minute.
|
||||
This parameter can be a number between Min_Data = 0 and Max_Data = 59 */
|
||||
uint8_t u8AlarmWeekday; /*!< Specifies the RTC Alarm Weekday.
|
||||
This parameter can be a value of @ref RTC_Alarm_Weekday */
|
||||
uint8_t u8AlarmAmPm; /*!< Specifies the RTC Alarm Am/Pm Time (in RTC_HOUR_FMT_12H mode).
|
||||
This parameter can be a value of @ref RTC_Hour12_AM_PM */
|
||||
} stc_rtc_alarm_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup RTC_Global_Macros RTC Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup RTC_Data_Format RTC Data Format
|
||||
* @{
|
||||
*/
|
||||
#define RTC_DATA_FMT_DEC (0x00U) /*!< Decimal data format */
|
||||
#define RTC_DATA_FMT_BCD (0x01U) /*!< BCD data format */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup RTC_Decimal_BCD_Conversion RTC Decimal BCD Conversion
|
||||
* @{
|
||||
*/
|
||||
#define RTC_DEC2BCD(__DATA__) ((((__DATA__) / 10U) << 4U) + ((__DATA__) % 10U))
|
||||
#define RTC_BCD2DEC(__DATA__) ((((__DATA__) >> 4U) * 10U) + ((__DATA__) & 0x0FU))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup RTC_Clock_Source RTC Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RTC_CLK_SRC_XTAL32 (0U) /*!< XTAL32 Clock */
|
||||
#define RTC_CLK_SRC_LRC (RTC_CR3_RCKSEL | RTC_CR3_LRCEN) /*!< RTC LRC Clock */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup RTC_Hour_Format RTC Hour Format
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HOUR_FMT_12H (0U) /*!< 12 hour time system */
|
||||
#define RTC_HOUR_FMT_24H (RTC_CR1_AMPM) /*!< 24 hour time system */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup RTC_Interrupt_Period RTC Interrupt Period
|
||||
* @{
|
||||
*/
|
||||
#define RTC_INT_PERIOD_INVD (0U) /*!< Interrupt period invalid */
|
||||
#define RTC_INT_PERIOD_PER_HALF_SEC (0x01U << RTC_CR1_PRDS_POS) /*!< Interrupt period per half second */
|
||||
#define RTC_INT_PERIOD_PER_SEC (0x02U << RTC_CR1_PRDS_POS) /*!< Interrupt period per second */
|
||||
#define RTC_INT_PERIOD_PER_MINUTE (0x03U << RTC_CR1_PRDS_POS) /*!< Interrupt period per minute */
|
||||
#define RTC_INT_PERIOD_PER_HOUR (0x04U << RTC_CR1_PRDS_POS) /*!< Interrupt period per hour */
|
||||
#define RTC_INT_PERIOD_PER_DAY (0x05U << RTC_CR1_PRDS_POS) /*!< Interrupt period per day */
|
||||
#define RTC_INT_PERIOD_PER_MONTH (0x06U << RTC_CR1_PRDS_POS) /*!< Interrupt period per month */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup RTC_Clock_Compensation RTC Clock Compensation
|
||||
* @{
|
||||
*/
|
||||
#define RTC_CLK_COMPEN_DISABLE (0U)
|
||||
#define RTC_CLK_COMPEN_ENABLE (RTC_ERRCRH_COMPEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup RTC_Clock_Compensation_Mode RTC Clock Compensation Mode
|
||||
* @{
|
||||
*/
|
||||
#define RTC_CLK_COMPEN_MD_DISTRIBUTED (0U) /*!< Distributed compensation 1Hz output */
|
||||
#define RTC_CLK_COMPEN_MD_UNIFORM (RTC_CR1_ONEHZSEL) /*!< Uniform compensation 1Hz output */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup RTC_Hour12_AM_PM RTC Hour12 AM/PM
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HOUR_24H (0U) /*!< 24-hour format */
|
||||
#define RTC_HOUR_12H_AM (0U) /*!< AM in 12-hour */
|
||||
#define RTC_HOUR_12H_PM (RTC_HOUR_HOURD_1) /*!< PM in 12-hour */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup RTC_Month RTC Month
|
||||
* @{
|
||||
*/
|
||||
#define RTC_MONTH_JANUARY (0x01U)
|
||||
#define RTC_MONTH_FEBRUARY (0x02U)
|
||||
#define RTC_MONTH_MARCH (0x03U)
|
||||
#define RTC_MONTH_APRIL (0x04U)
|
||||
#define RTC_MONTH_MAY (0x05U)
|
||||
#define RTC_MONTH_JUNE (0x06U)
|
||||
#define RTC_MONTH_JULY (0x07U)
|
||||
#define RTC_MONTH_AUGUST (0x08U)
|
||||
#define RTC_MONTH_SEPTEMBER (0x09U)
|
||||
#define RTC_MONTH_OCTOBER (0x0AU)
|
||||
#define RTC_MONTH_NOVEMBER (0x0BU)
|
||||
#define RTC_MONTH_DECEMBER (0x0CU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup RTC_Weekday RTC Weekday
|
||||
* @{
|
||||
*/
|
||||
#define RTC_WEEKDAY_SUNDAY (0x00U)
|
||||
#define RTC_WEEKDAY_MONDAY (0x01U)
|
||||
#define RTC_WEEKDAY_TUESDAY (0x02U)
|
||||
#define RTC_WEEKDAY_WEDNESDAY (0x03U)
|
||||
#define RTC_WEEKDAY_THURSDAY (0x04U)
|
||||
#define RTC_WEEKDAY_FRIDAY (0x05U)
|
||||
#define RTC_WEEKDAY_SATURDAY (0x06U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup RTC_Alarm_Weekday RTC Alarm Weekday
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARM_WEEKDAY_SUNDAY (0x01U)
|
||||
#define RTC_ALARM_WEEKDAY_MONDAY (0x02U)
|
||||
#define RTC_ALARM_WEEKDAY_TUESDAY (0x04U)
|
||||
#define RTC_ALARM_WEEKDAY_WEDNESDAY (0x08U)
|
||||
#define RTC_ALARM_WEEKDAY_THURSDAY (0x10U)
|
||||
#define RTC_ALARM_WEEKDAY_FRIDAY (0x20U)
|
||||
#define RTC_ALARM_WEEKDAY_SATURDAY (0x40U)
|
||||
#define RTC_ALARM_WEEKDAY_EVERYDAY (0x7FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup RTC_Flag RTC Flag
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FLAG_RD_WR (RTC_CR2_RWEN) /*!< Read and write permission flag */
|
||||
#define RTC_FLAG_ALARM (RTC_CR2_ALMF) /*!< Alarm flag */
|
||||
#define RTC_FLAG_ALL (RTC_FLAG_RD_WR | RTC_FLAG_ALARM)
|
||||
#define RTC_FLAG_CLR_ALL (RTC_FLAG_ALARM)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup RTC_Interrupt RTC Interrupt
|
||||
* @{
|
||||
*/
|
||||
#define RTC_INT_PERIOD (RTC_CR2_PRDIE) /*!< Period interrupt */
|
||||
#define RTC_INT_ALARM (RTC_CR2_ALMIE) /*!< Alarm interrupt */
|
||||
#define RTC_INT_ALL (RTC_INT_PERIOD | RTC_INT_ALARM)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup RTC_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and configuration functions */
|
||||
int32_t RTC_DeInit(void);
|
||||
int32_t RTC_Init(const stc_rtc_init_t *pstcRtcInit);
|
||||
int32_t RTC_StructInit(stc_rtc_init_t *pstcRtcInit);
|
||||
int32_t RTC_EnterRwMode(void);
|
||||
int32_t RTC_ExitRwMode(void);
|
||||
|
||||
/* Control configuration */
|
||||
int32_t RTC_ConfirmLPMCond(void);
|
||||
void RTC_SetIntPeriod(uint8_t u8Period);
|
||||
void RTC_SetClockSrc(uint8_t u8Src);
|
||||
void RTC_SetClockCompenValue(uint16_t u16Value);
|
||||
en_functional_state_t RTC_GetCounterState(void);
|
||||
void RTC_Cmd(en_functional_state_t enNewState);
|
||||
void RTC_LrcCmd(en_functional_state_t enNewState);
|
||||
void RTC_OneHzOutputCmd(en_functional_state_t enNewState);
|
||||
void RTC_ClockCompenCmd(en_functional_state_t enNewState);
|
||||
|
||||
/* Date and time functions */
|
||||
int32_t RTC_SetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate);
|
||||
int32_t RTC_GetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate);
|
||||
int32_t RTC_SetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime);
|
||||
int32_t RTC_GetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime);
|
||||
|
||||
/* Alarm configuration functions */
|
||||
int32_t RTC_SetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm);
|
||||
int32_t RTC_GetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm);
|
||||
void RTC_AlarmCmd(en_functional_state_t enNewState);
|
||||
|
||||
/* Interrupt and flag management functions */
|
||||
void RTC_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState);
|
||||
en_flag_status_t RTC_GetStatus(uint32_t u32Flag);
|
||||
void RTC_ClearStatus(uint32_t u32Flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_RTC_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_RTC_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,892 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_sdioc.h
|
||||
* @brief This file contains all the functions prototypes of the SDIOC driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2023-09-30 CDT Modify typo
|
||||
Rename function SDMMC_ACMD41_SendOperatCond to SDMMC_ACMD41_SendOperateCond
|
||||
Rename function SDMMC_CMD1_SendOperatCond to SDMMC_CMD1_SendOperateCond
|
||||
Support CMD5/CMD52/CMD53
|
||||
Rename macro definition SDIOC_ACMD52_RW_DIRECT to SDIOC_CMD52_IO_RW_DIRECT
|
||||
Rename macro definition SDIOC_ACMD53_RW_EXTENDED to SDIOC_CMD53_IO_RW_EXTENDED
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_SDIOC_H__
|
||||
#define __HC32_LL_SDIOC_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_SDIOC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_SDIOC_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup SDIOC_Global_Types SDIOC Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SDIOC Init structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32Mode; /*!< Specifies the SDIOC work mode.
|
||||
This parameter can be a value of @ref SDIOC_Mode */
|
||||
uint8_t u8CardDetect; /*!< Specifies the SDIOC card detect way.
|
||||
This parameter can be a value of @ref SDIOC_Card_Detect_Way */
|
||||
uint8_t u8SpeedMode; /*!< Specifies the SDIOC speed mode.
|
||||
This parameter can be a value of @ref SDIOC_Speed_Mode */
|
||||
uint8_t u8BusWidth; /*!< Specifies the SDIOC bus width.
|
||||
This parameter can be a value of @ref SDIOC_Bus_Width */
|
||||
uint16_t u16ClockDiv; /*!< Specifies the SDIOC clock division.
|
||||
This parameter can be a value of @ref SDIOC_Clock_Division */
|
||||
} stc_sdioc_init_t;
|
||||
|
||||
/**
|
||||
* @brief SDIOC Command Configuration structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32Argument; /*!< Specifies the SDIOC command argument. */
|
||||
uint16_t u16CmdIndex; /*!< Specifies the SDIOC command index.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
|
||||
uint16_t u16CmdType; /*!< Specifies the SDIOC command type.
|
||||
This parameter can be a value of @ref SDIOC_Command_Type */
|
||||
uint16_t u16DataLine; /*!< Specifies whether SDIOC uses data lines in current command.
|
||||
This parameter can be a value of @ref SDIOC_Data_Line_Valid */
|
||||
uint16_t u16ResponseType; /*!< Specifies the SDIOC response type.
|
||||
This parameter can be a value of @ref SDIOC_Response_Type */
|
||||
} stc_sdioc_cmd_config_t;
|
||||
|
||||
/**
|
||||
* @brief SDIOC Data Configuration structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint16_t u16BlockSize; /*!< Specifies the SDIOC data block size.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 512 */
|
||||
uint16_t u16BlockCount; /*!< Specifies the SDIOC data block count.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF */
|
||||
uint16_t u16TransDir; /*!< Specifies the SDIOC data transfer direction.
|
||||
This parameter can be a value of @ref SDIOC_Transfer_Direction */
|
||||
uint16_t u16AutoCmd12; /*!< Specifies the validity of the SDIOC Auto Send CMD12.
|
||||
This parameter can be a value of @ref SDIOC_Auto_Send_CMD12 */
|
||||
uint16_t u16TransMode; /*!< Specifies the SDIOC data transfer mode.
|
||||
This parameter can be a value of @ref SDIOC_Transfer_Mode */
|
||||
uint8_t u16DataTimeout; /*!< Specifies the SDIOC data timeout time.
|
||||
This parameter can be a value of @ref SDIOC_Data_Timeout_Time */
|
||||
} stc_sdioc_data_config_t;
|
||||
|
||||
/**
|
||||
* @brief SDIO CMD52 arguments structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t u8FuncNum; /*!< Specifies the number of the function within the I/O card.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 7 */
|
||||
uint32_t u32RwFlag; /*!< Specifies the direction of the I/O operation.
|
||||
This parameter can be a value of @ref SDIO_CMD52_Arguments_RW_Flag */
|
||||
uint32_t u32RegAddr; /*!< Specifies the address of the byte of data inside of the selected function.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFF */
|
||||
uint32_t u32RawFlag; /*!< Specifies the direction of the I/O operation.
|
||||
This parameter can be a value of @ref SDIO_CMD52_Arguments_RAW_Flag */
|
||||
} stc_sdio_cmd52_arg_t;
|
||||
|
||||
/**
|
||||
* @brief SDIO CMD53 arguments structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t u8FuncNum; /*!< Specifies the number of the function within the I/O card.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 7 */
|
||||
uint32_t u32RwFlag; /*!< Specifies the direction of the I/O operation.
|
||||
This parameter can be a value of @ref SDIO_CMD53_Arguments_RW_Flag */
|
||||
uint32_t u32RegAddr; /*!< Specifies the address of the byte of data inside of the selected function.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFF */
|
||||
uint32_t u32OperateCode; /*!< Specifies the operation code.
|
||||
This parameter can be a value of @ref SDIO_CMD53_Arguments_Operate_Code */
|
||||
uint32_t u32BlockMode; /*!< Specifies the operation code.
|
||||
This parameter can be a value of @ref SDIO_CMD53_Arguments_Block_Mode */
|
||||
uint32_t u32Count; /*!< Specifies the byte/block count.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FF */
|
||||
} stc_sdio_cmd53_arg_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup SDIOC_Global_Macros SDIOC Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Mode SDIOC Mode
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_MD_SD (0x00UL) /*!< SDIOCx selects SD mode */
|
||||
#define SDIOC_MD_MMC (0x01UL) /*!< SDIOCx selects MMC mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Card_Detect_Way SDIOC Card Detect Way
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_CARD_DETECT_CD_PIN_LVL (0x00U) /*!< SDIOCx_CD(x=1~2) line is selected (for normal use) */
|
||||
#define SDIOC_CARD_DETECT_TEST_SIGNAL (SDIOC_HOSTCON_CDSS) /*!< The Card Detect Test Level is selected(for test purpose) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Card_Detect_Test_Level SDIOC Card Detect Test Level
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_CARD_DETECT_TEST_LVL_LOW (0x00U) /*!< Card identification test signal is low level (with device insertion) */
|
||||
#define SDIOC_CARD_DETECT_TEST_LVL_HIGH (SDIOC_HOSTCON_CDTL) /*!< Card identification test signal is high level (no device insertion) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Speed_Mode SDIOC Speed Mode
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_SPEED_MD_NORMAL (0x00U) /*!< Normal speed mode */
|
||||
#define SDIOC_SPEED_MD_HIGH (SDIOC_HOSTCON_HSEN) /*!< High speed mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Bus_Width SDIOC Bus Width
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_BUS_WIDTH_1BIT (0x00U) /*!< The Bus width is 1 bit */
|
||||
#define SDIOC_BUS_WIDTH_4BIT (SDIOC_HOSTCON_DW) /*!< The Bus width is 4 bit */
|
||||
#define SDIOC_BUS_WIDTH_8BIT (SDIOC_HOSTCON_EXDW) /*!< The Bus width is 8 bit */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Clock_Division SDIOC Clock Division
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_CLK_DIV1 (0x00U) /*!< CLK1/1 */
|
||||
#define SDIOC_CLK_DIV2 (SDIOC_CLKCON_FS_0) /*!< CLK1/2 */
|
||||
#define SDIOC_CLK_DIV4 (SDIOC_CLKCON_FS_1) /*!< CLK1/4 */
|
||||
#define SDIOC_CLK_DIV8 (SDIOC_CLKCON_FS_2) /*!< CLK1/8 */
|
||||
#define SDIOC_CLK_DIV16 (SDIOC_CLKCON_FS_3) /*!< CLK1/16 */
|
||||
#define SDIOC_CLK_DIV32 (SDIOC_CLKCON_FS_4) /*!< CLK1/32 */
|
||||
#define SDIOC_CLK_DIV64 (SDIOC_CLKCON_FS_5) /*!< CLK1/64 */
|
||||
#define SDIOC_CLK_DIV128 (SDIOC_CLKCON_FS_6) /*!< CLK1/128 */
|
||||
#define SDIOC_CLK_DIV256 (SDIOC_CLKCON_FS_7) /*!< CLK1/256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Command_Type SDIOC Command Type
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_CMD_TYPE_NORMAL (0x00U) /*!< Other commands */
|
||||
#define SDIOC_CMD_TYPE_SUSPEND (SDIOC_CMD_TYP_0) /*!< CMD52 for writing "Bus Suspend" in CCCR */
|
||||
#define SDIOC_CMD_TYPE_RESUME (SDIOC_CMD_TYP_1) /*!< CMD52 for writing "Function Select" in CCCR */
|
||||
#define SDIOC_CMD_TYPE_ABORT (SDIOC_CMD_TYP) /*!< CMD12, CMD52 for writing "I/O Abort" in CCCR */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Data_Line_Valid SDIOC Data Line Valid
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_DATA_LINE_DISABLE (0x00U) /*!< The current command uses only SDIOCx_CMD(x=1~2) command line */
|
||||
#define SDIOC_DATA_LINE_ENABLE (SDIOC_CMD_DAT) /*!< The current command requires the use of SDIOCx_Dy(x=1~2) data line */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Transfer_Direction SDIOC Transfer Direction
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_TRANS_DIR_TO_CARD (0x00U) /*!< Write (Host to Card) */
|
||||
#define SDIOC_TRANS_DIR_TO_HOST (SDIOC_TRANSMODE_DDIR) /*!< Read (Card to Host) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Auto_Send_CMD12 SDIOC Auto Send CMD12
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_AUTO_SEND_CMD12_DISABLE (0x00U) /*!< Do not send autocommands */
|
||||
#define SDIOC_AUTO_SEND_CMD12_ENABLE (SDIOC_TRANSMODE_ATCEN_0) /*!< CMD12 is automatically sent after multiple block transfers */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Transfer_Mode SDIOC Transfer Mode
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_TRANS_MD_SINGLE (0x00U) /*!< Single Block transfer */
|
||||
#define SDIOC_TRANS_MD_INFINITE (SDIOC_TRANSMODE_MULB) /*!< Infinite Block transfer */
|
||||
#define SDIOC_TRANS_MD_MULTI (SDIOC_TRANSMODE_MULB | SDIOC_TRANSMODE_BCE) /*!< Multiple Block transfer */
|
||||
#define SDIOC_TRANS_MD_STOP_MULTI (0x8000U | SDIOC_TRANS_MD_MULTI) /*!< Stop Multiple Block transfer */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Data_Timeout_Time SDIOC Data Timeout Time
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_DATA_TIMEOUT_CLK_2E13 (0x00U) /*!< Timeout time: CLK1*2^13 */
|
||||
#define SDIOC_DATA_TIMEOUT_CLK_2E14 (0x01U) /*!< Timeout time: CLK1*2^14 */
|
||||
#define SDIOC_DATA_TIMEOUT_CLK_2E15 (0x02U) /*!< Timeout time: CLK1*2^15 */
|
||||
#define SDIOC_DATA_TIMEOUT_CLK_2E16 (0x03U) /*!< Timeout time: CLK1*2^16 */
|
||||
#define SDIOC_DATA_TIMEOUT_CLK_2E17 (0x04U) /*!< Timeout time: CLK1*2^17 */
|
||||
#define SDIOC_DATA_TIMEOUT_CLK_2E18 (0x05U) /*!< Timeout time: CLK1*2^18 */
|
||||
#define SDIOC_DATA_TIMEOUT_CLK_2E19 (0x06U) /*!< Timeout time: CLK1*2^19 */
|
||||
#define SDIOC_DATA_TIMEOUT_CLK_2E20 (0x07U) /*!< Timeout time: CLK1*2^20 */
|
||||
#define SDIOC_DATA_TIMEOUT_CLK_2E21 (0x08U) /*!< Timeout time: CLK1*2^21 */
|
||||
#define SDIOC_DATA_TIMEOUT_CLK_2E22 (0x09U) /*!< Timeout time: CLK1*2^22 */
|
||||
#define SDIOC_DATA_TIMEOUT_CLK_2E23 (0x0AU) /*!< Timeout time: CLK1*2^23 */
|
||||
#define SDIOC_DATA_TIMEOUT_CLK_2E24 (0x0BU) /*!< Timeout time: CLK1*2^24 */
|
||||
#define SDIOC_DATA_TIMEOUT_CLK_2E25 (0x0CU) /*!< Timeout time: CLK1*2^25 */
|
||||
#define SDIOC_DATA_TIMEOUT_CLK_2E26 (0x0DU) /*!< Timeout time: CLK1*2^26 */
|
||||
#define SDIOC_DATA_TIMEOUT_CLK_2E27 (0x0EU) /*!< Timeout time: CLK1*2^27 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Response_Register SDIOC Response Register
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_RESP_REG_BIT0_31 (0x00U) /*!< Command Response Register 0-31bit */
|
||||
#define SDIOC_RESP_REG_BIT32_63 (0x04U) /*!< Command Response Register 32-63bit */
|
||||
#define SDIOC_RESP_REG_BIT64_95 (0x08U) /*!< Command Response Register 64-95bit */
|
||||
#define SDIOC_RESP_REG_BIT96_127 (0x0CU) /*!< Command Response Register 96-127bit */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Software_Reset_Type SDIOC Software Reset Type
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_SW_RST_DATA_LINE (SDIOC_SFTRST_RSTD) /*!< Only part of data circuit is reset */
|
||||
#define SDIOC_SW_RST_CMD_LINE (SDIOC_SFTRST_RSTC) /*!< Only part of command circuit is reset */
|
||||
#define SDIOC_SW_RST_ALL (SDIOC_SFTRST_RSTA) /*!< Reset the entire Host Controller except for the card detection circuit */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Output_Clock_Frequency SDIOC Output Clock Frequency
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_OUTPUT_CLK_FREQ_400K (400000UL) /*!< SDIOC clock: 400KHz */
|
||||
#define SDIOC_OUTPUT_CLK_FREQ_25M (25000000UL) /*!< SDIOC clock: 25MHz */
|
||||
#define SDIOC_OUTPUT_CLK_FREQ_26M (26000000UL) /*!< SDIOC clock: 26MHz */
|
||||
#define SDIOC_OUTPUT_CLK_FREQ_50M (50000000UL) /*!< SDIOC clock: 50MHz */
|
||||
#define SDIOC_OUTPUT_CLK_FREQ_52M (52000000UL) /*!< SDIOC clock: 52MHz */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Host_Flag SDIOC Host Flag
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_HOST_FLAG_CMDL (SDIOC_PSTAT_CMDL) /*!< CMD Line Level status */
|
||||
#define SDIOC_HOST_FLAG_DATL (SDIOC_PSTAT_DATL) /*!< DAT[3:0] Line Level status */
|
||||
#define SDIOC_HOST_FLAG_DATL_D0 (SDIOC_PSTAT_DATL_0) /*!< DAT[0] Line Level status */
|
||||
#define SDIOC_HOST_FLAG_DATL_D1 (SDIOC_PSTAT_DATL_1) /*!< DAT[1] Line Level status */
|
||||
#define SDIOC_HOST_FLAG_DATL_D2 (SDIOC_PSTAT_DATL_2) /*!< DAT[2] Line Level status */
|
||||
#define SDIOC_HOST_FLAG_DATL_D3 (SDIOC_PSTAT_DATL_3) /*!< DAT[3] Line Level status */
|
||||
#define SDIOC_HOST_FLAG_WPL (SDIOC_PSTAT_WPL) /*!< Write Protect Line Level status */
|
||||
#define SDIOC_HOST_FLAG_CDL (SDIOC_PSTAT_CDL) /*!< Card Detect Line Level status */
|
||||
#define SDIOC_HOST_FLAG_CSS (SDIOC_PSTAT_CSS) /*!< Device Stable Status */
|
||||
#define SDIOC_HOST_FLAG_CIN (SDIOC_PSTAT_CIN) /*!< Device Inserted status */
|
||||
#define SDIOC_HOST_FLAG_BRE (SDIOC_PSTAT_BRE) /*!< Data buffer full status */
|
||||
#define SDIOC_HOST_FLAG_BWE (SDIOC_PSTAT_BWE) /*!< Data buffer empty status */
|
||||
#define SDIOC_HOST_FLAG_RTA (SDIOC_PSTAT_RTA) /*!< Read operation status */
|
||||
#define SDIOC_HOST_FLAG_WTA (SDIOC_PSTAT_WTA) /*!< Write operation status */
|
||||
#define SDIOC_HOST_FLAG_DA (SDIOC_PSTAT_DA) /*!< DAT Line transfer status */
|
||||
#define SDIOC_HOST_FLAG_CID (SDIOC_PSTAT_CID) /*!< Command Inhibit with data status */
|
||||
#define SDIOC_HOST_FLAG_CIC (SDIOC_PSTAT_CIC) /*!< Command Inhibit status */
|
||||
#define SDIOC_HOST_FLAG_ALL (SDIOC_HOST_FLAG_CMDL | SDIOC_HOST_FLAG_DATL | SDIOC_HOST_FLAG_WPL | \
|
||||
SDIOC_HOST_FLAG_CDL | SDIOC_HOST_FLAG_CSS | SDIOC_HOST_FLAG_CIN | \
|
||||
SDIOC_HOST_FLAG_BRE | SDIOC_HOST_FLAG_BWE | SDIOC_HOST_FLAG_RTA | \
|
||||
SDIOC_HOST_FLAG_WTA | SDIOC_HOST_FLAG_DA | SDIOC_HOST_FLAG_CID | \
|
||||
SDIOC_HOST_FLAG_CIC)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Interrupt_Flag SDIOC Interrupt Flag
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_INT_FLAG_EI (SDIOC_NORINTST_EI) /*!< Error Interrupt Status */
|
||||
#define SDIOC_INT_FLAG_CINT (SDIOC_NORINTST_CINT) /*!< Card Interrupt status */
|
||||
#define SDIOC_INT_FLAG_CRM (SDIOC_NORINTST_CRM) /*!< Card Removal status */
|
||||
#define SDIOC_INT_FLAG_CIST (SDIOC_NORINTST_CIST) /*!< Card Insertion status */
|
||||
#define SDIOC_INT_FLAG_BRR (SDIOC_NORINTST_BRR) /*!< Buffer Read Ready status */
|
||||
#define SDIOC_INT_FLAG_BWR (SDIOC_NORINTST_BWR) /*!< Buffer Write Ready status */
|
||||
#define SDIOC_INT_FLAG_BGE (SDIOC_NORINTST_BGE) /*!< Block Gap Event status */
|
||||
#define SDIOC_INT_FLAG_TC (SDIOC_NORINTST_TC) /*!< Transfer Complete status */
|
||||
#define SDIOC_INT_FLAG_CC (SDIOC_NORINTST_CC) /*!< Command Complete status */
|
||||
#define SDIOC_INT_FLAG_ACE ((uint32_t)SDIOC_ERRINTST_ACE << 16U) /*!< Auto CMD12 Error Status */
|
||||
#define SDIOC_INT_FLAG_DEBE ((uint32_t)SDIOC_ERRINTST_DEBE << 16U) /*!< Data End Bit Error status */
|
||||
#define SDIOC_INT_FLAG_DCE ((uint32_t)SDIOC_ERRINTST_DCE << 16U) /*!< Data CRC Error status */
|
||||
#define SDIOC_INT_FLAG_DTOE ((uint32_t)SDIOC_ERRINTST_DTOE << 16U) /*!< Data Timeout Error status */
|
||||
#define SDIOC_INT_FLAG_CIE ((uint32_t)SDIOC_ERRINTST_CIE << 16U) /*!< Command Index Error status */
|
||||
#define SDIOC_INT_FLAG_CEBE ((uint32_t)SDIOC_ERRINTST_CEBE << 16U) /*!< Command End Bit Error status */
|
||||
#define SDIOC_INT_FLAG_CCE ((uint32_t)SDIOC_ERRINTST_CCE << 16U) /*!< Command CRC Error status */
|
||||
#define SDIOC_INT_FLAG_CTOE ((uint32_t)SDIOC_ERRINTST_CTOE << 16U) /*!< Command Timeout Error status */
|
||||
#define SDIOC_INT_STATIC_FLAGS (SDIOC_INT_FLAG_ACE | SDIOC_INT_FLAG_DEBE | SDIOC_INT_FLAG_DCE | \
|
||||
SDIOC_INT_FLAG_DTOE | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | \
|
||||
SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE | SDIOC_INT_FLAG_TC | \
|
||||
SDIOC_INT_FLAG_CC)
|
||||
#define SDIOC_NORMAL_INT_FLAG_ALL (SDIOC_INT_FLAG_EI | SDIOC_INT_FLAG_CINT | SDIOC_INT_FLAG_CRM | \
|
||||
SDIOC_INT_FLAG_CIST | SDIOC_INT_FLAG_BRR | SDIOC_INT_FLAG_BWR | \
|
||||
SDIOC_INT_FLAG_BGE | SDIOC_INT_FLAG_TC | SDIOC_INT_FLAG_CC)
|
||||
#define SDIOC_ERR_INT_FLAG_ALL (SDIOC_INT_FLAG_ACE | SDIOC_INT_FLAG_DEBE | SDIOC_INT_FLAG_DCE | \
|
||||
SDIOC_INT_FLAG_DTOE | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | \
|
||||
SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE)
|
||||
#define SDIOC_INT_FLAG_ALL (SDIOC_NORMAL_INT_FLAG_ALL | SDIOC_ERR_INT_FLAG_ALL)
|
||||
#define SDIOC_INT_FLAG_CLR_ALL (SDIOC_INT_FLAG_CRM | SDIOC_INT_FLAG_CIST | SDIOC_INT_FLAG_BRR | \
|
||||
SDIOC_INT_FLAG_BWR | SDIOC_INT_FLAG_BGE | SDIOC_INT_FLAG_TC | \
|
||||
SDIOC_INT_FLAG_CC | SDIOC_ERR_INT_FLAG_ALL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Interrupt SDIOC Interrupt
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_INT_CINTSEN (SDIOC_NORINTSGEN_CINTSEN) /*!< Card Interrupt */
|
||||
#define SDIOC_INT_CRMSEN (SDIOC_NORINTSGEN_CRMSEN) /*!< Card Removal Interrupt */
|
||||
#define SDIOC_INT_CISTSEN (SDIOC_NORINTSGEN_CISTSEN) /*!< Card Insertion Interrupt */
|
||||
#define SDIOC_INT_BRRSEN (SDIOC_NORINTSGEN_BRRSEN) /*!< Buffer Read Ready Interrupt */
|
||||
#define SDIOC_INT_BWRSEN (SDIOC_NORINTSGEN_BWRSEN) /*!< Buffer Write Ready Interrupt */
|
||||
#define SDIOC_INT_BGESEN (SDIOC_NORINTSGEN_BGESEN) /*!< Block Gap Event Interrupt */
|
||||
#define SDIOC_INT_TCSEN (SDIOC_NORINTSGEN_TCSEN) /*!< Transfer Complete Interrupt */
|
||||
#define SDIOC_INT_CCSEN (SDIOC_NORINTSGEN_CCSEN) /*!< Command Complete Interrupt */
|
||||
#define SDIOC_INT_ACESEN ((uint32_t)SDIOC_ERRINTSGEN_ACESEN << 16U) /*!< Auto CMD12 Error Interrupt */
|
||||
#define SDIOC_INT_DEBESEN ((uint32_t)SDIOC_ERRINTSGEN_DEBESEN << 16U) /*!< Data End Bit Error Interrupt */
|
||||
#define SDIOC_INT_DCESEN ((uint32_t)SDIOC_ERRINTSGEN_DCESEN << 16U) /*!< Data CRC Error Interrupt */
|
||||
#define SDIOC_INT_DTOESEN ((uint32_t)SDIOC_ERRINTSGEN_DTOESEN << 16U) /*!< Data Timeout Error Interrupt */
|
||||
#define SDIOC_INT_CIESEN ((uint32_t)SDIOC_ERRINTSGEN_CIESEN << 16U) /*!< Command Index Error Interrupt */
|
||||
#define SDIOC_INT_CEBESEN ((uint32_t)SDIOC_ERRINTSGEN_CEBESEN << 16U) /*!< Command End Bit Error Interrupt */
|
||||
#define SDIOC_INT_CCESEN ((uint32_t)SDIOC_ERRINTSGEN_CCESEN << 16U) /*!< Command CRC Error Interrupt */
|
||||
#define SDIOC_INT_CTOESEN ((uint32_t)SDIOC_ERRINTSGEN_CTOESEN << 16U) /*!< Command Timeout Error Interrupt */
|
||||
#define SDIOC_NORMAL_INT_ALL (SDIOC_INT_CINTSEN | SDIOC_INT_CRMSEN | SDIOC_INT_CISTSEN | \
|
||||
SDIOC_INT_BRRSEN | SDIOC_INT_BWRSEN | SDIOC_INT_BGESEN | \
|
||||
SDIOC_INT_TCSEN | SDIOC_INT_CCSEN)
|
||||
#define SDIOC_ERR_INT_ALL (SDIOC_INT_ACESEN | SDIOC_INT_DEBESEN | SDIOC_INT_DCESEN | \
|
||||
SDIOC_INT_DTOESEN | SDIOC_INT_CIESEN | SDIOC_INT_CEBESEN | \
|
||||
SDIOC_INT_CCESEN | SDIOC_INT_CTOESEN)
|
||||
#define SDIOC_INT_ALL (SDIOC_NORMAL_INT_ALL | SDIOC_ERR_INT_ALL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Auto_CMD_Error_Flag SDIOC Auto CMD Error Flag
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_AUTO_CMD_ERR_FLAG_CMDE (SDIOC_ATCERRST_CMDE) /*!< Command Not Issued By Auto CMD12 Error Status */
|
||||
#define SDIOC_AUTO_CMD_ERR_FLAG_IE (SDIOC_ATCERRST_IE) /*!< Auto CMD12 Index Error status */
|
||||
#define SDIOC_AUTO_CMD_ERR_FLAG_EBE (SDIOC_ATCERRST_EBE) /*!< Auto CMD12 End Bit Error status */
|
||||
#define SDIOC_AUTO_CMD_ERR_FLAG_CE (SDIOC_ATCERRST_CE) /*!< Auto CMD12 CRC Error status */
|
||||
#define SDIOC_AUTO_CMD_ERR_FLAG_TOE (SDIOC_ATCERRST_TOE) /*!< Auto CMD12 Timeout Error status */
|
||||
#define SDIOC_AUTO_CMD_ERR_FLAG_NE (SDIOC_ATCERRST_NE) /*!< Auto CMD12 Not Executed status */
|
||||
#define SDIOC_AUTO_CMD_ERR_FLAG_ALL (SDIOC_AUTO_CMD_ERR_FLAG_CMDE | SDIOC_AUTO_CMD_ERR_FLAG_IE | \
|
||||
SDIOC_AUTO_CMD_ERR_FLAG_EBE | SDIOC_AUTO_CMD_ERR_FLAG_CE | \
|
||||
SDIOC_AUTO_CMD_ERR_FLAG_TOE | SDIOC_AUTO_CMD_ERR_FLAG_NE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Force_Auto_CMD_Error SDIOC Force Auto CMD Error
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_FORCE_AUTO_CMD_ERR_FCMDE (SDIOC_FEA_FCMDE) /*!< Force Event for Command Not Issued By Auto CMD12 Error */
|
||||
#define SDIOC_FORCE_AUTO_CMD_ERR_FIE (SDIOC_FEA_FIE) /*!< Force Event for Auto CMD12 Index Error */
|
||||
#define SDIOC_FORCE_AUTO_CMD_ERR_FEBE (SDIOC_FEA_FEBE) /*!< Force Event for Auto CMD12 End Bit Error */
|
||||
#define SDIOC_FORCE_AUTO_CMD_ERR_FCE (SDIOC_FEA_FCE) /*!< Force Event for Auto CMD12 CRC Error */
|
||||
#define SDIOC_FORCE_AUTO_CMD_ERR_FTOE (SDIOC_FEA_FTOE) /*!< Force Event for Auto CMD12 Timeout Error */
|
||||
#define SDIOC_FORCE_AUTO_CMD_ERR_FNE (SDIOC_FEA_FNE) /*!< Force Event for Auto CMD12 Not Executed */
|
||||
#define SDIOC_FORCE_AUTO_CMD_ERR_ALL (SDIOC_FORCE_AUTO_CMD_ERR_FCMDE | SDIOC_FORCE_AUTO_CMD_ERR_FIE | \
|
||||
SDIOC_FORCE_AUTO_CMD_ERR_FEBE | SDIOC_FORCE_AUTO_CMD_ERR_FCE | \
|
||||
SDIOC_FORCE_AUTO_CMD_ERR_FTOE | SDIOC_FORCE_AUTO_CMD_ERR_FNE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Force_Error_Interrupt SDIOC Force Error Interrupt
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_FORCE_ERR_INT_FACE (SDIOC_FEE_FACE) /*!< Force Event for Auto CMD12 Error */
|
||||
#define SDIOC_FORCE_ERR_INT_FDEBE (SDIOC_FEE_FDEBE) /*!< Force Event for Data End Bit Error */
|
||||
#define SDIOC_FORCE_ERR_INT_FDCE (SDIOC_FEE_FDCE) /*!< Force Event for Data CRC Error */
|
||||
#define SDIOC_FORCE_ERR_INT_FDTOE (SDIOC_FEE_FDTOE) /*!< Force Event for Data Timeout Error */
|
||||
#define SDIOC_FORCE_ERR_INT_FCIE (SDIOC_FEE_FCIE) /*!< Force Event for Command Index Error */
|
||||
#define SDIOC_FORCE_ERR_INT_FCEBE (SDIOC_FEE_FCEBE) /*!< Force Event for Command End Bit Error */
|
||||
#define SDIOC_FORCE_ERR_INT_FCCE (SDIOC_FEE_FCCE) /*!< Force Event for Command CRC Error */
|
||||
#define SDIOC_FORCE_ERR_INT_FCTOE (SDIOC_FEE_FCTOE) /*!< Force Event for Command Timeout Error */
|
||||
#define SDIOC_FORCE_ERR_INT_ALL (SDIOC_FORCE_ERR_INT_FACE | SDIOC_FORCE_ERR_INT_FDEBE | \
|
||||
SDIOC_FORCE_ERR_INT_FDCE | SDIOC_FORCE_ERR_INT_FDTOE | \
|
||||
SDIOC_FORCE_ERR_INT_FCIE | SDIOC_FORCE_ERR_INT_FCEBE | \
|
||||
SDIOC_FORCE_ERR_INT_FCCE | SDIOC_FORCE_ERR_INT_FCTOE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Response_Type SDIOC Response Type
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_RESP_TYPE_NO (0x00U) /*!< No Response */
|
||||
#define SDIOC_RESP_TYPE_R2 (SDIOC_CMD_RESTYP_0) /*!< Command Response 2 */
|
||||
#define SDIOC_RESP_TYPE_R3_R4 (SDIOC_CMD_RESTYP_1) /*!< Command Response 3, 4 */
|
||||
#define SDIOC_RESP_TYPE_R1_R5_R6_R7 (SDIOC_CMD_RESTYP_1 | SDIOC_CMD_ICE | SDIOC_CMD_CCE) /*!< Command Response 1, 5, 6, 7 */
|
||||
#define SDIOC_RESP_TYPE_R1B_R5B (SDIOC_CMD_RESTYP | SDIOC_CMD_ICE | SDIOC_CMD_CCE) /*!< Command Response 1 and 5 with busy */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_Command SDIOC Command
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @defgroup SDIOC_SDMMC_CMD SDIOC SDMMC CMD
|
||||
* @{
|
||||
*/
|
||||
#define SDIOC_CMD0_GO_IDLE_STATE (0U) /*!< Resets the SD memory card. */
|
||||
#define SDIOC_CMD1_SEND_OP_COND (1U) /*!< Sends host capacity support information and activates the card's initialization process. */
|
||||
#define SDIOC_CMD2_ALL_SEND_CID (2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
|
||||
#define SDIOC_CMD3_SEND_RELATIVE_ADDR (3U) /*!< Asks the card to publish a new relative address (RCA). */
|
||||
#define SDIOC_CMD4_SET_DSR (4U) /*!< Programs the DSR of all cards. */
|
||||
#define SDIOC_CMD5_IO_SEND_OP_COND (5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its \
|
||||
operating condition register (OCR) content in the response on the CMD line. */
|
||||
#define SDIOC_CMD6_SWITCH_FUNC (6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
|
||||
#define SDIOC_CMD7_SELECT_DESELECT_CARD (7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
|
||||
#define SDIOC_CMD8_SEND_IF_COND (8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information \
|
||||
and asks the card whether card supports voltage. */
|
||||
#define SDIOC_CMD9_SEND_CSD (9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
|
||||
#define SDIOC_CMD10_SEND_CID (10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
|
||||
#define SDIOC_CMD11_READ_DAT_UNTIL_STOP (11U) /*!< SD card doesn't support it. */
|
||||
#define SDIOC_CMD12_STOP_TRANSMISSION (12U) /*!< Forces the card to stop transmission. */
|
||||
#define SDIOC_CMD13_SEND_STATUS (13U) /*!< Addressed card sends its status register. */
|
||||
#define SDIOC_CMD14_HS_BUSTEST_READ (14U) /*!< Reserved */
|
||||
#define SDIOC_CMD15_GO_INACTIVE_STATE (15U) /*!< Sends an addressed card into the inactive state. */
|
||||
#define SDIOC_CMD16_SET_BLOCKLEN (16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands(read, write). \
|
||||
Default block length is fixed to 512 Bytes. Not effective for SDHS and SDXC. */
|
||||
#define SDIOC_CMD17_READ_SINGLE_BLOCK (17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed \
|
||||
512 bytes in case of SDHC and SDXC. */
|
||||
#define SDIOC_CMD18_READ_MULTI_BLOCK (18U) /*!< Continuously transfers data blocks from card to host until interrupted by \
|
||||
STOP_TRANSMISSION command. */
|
||||
#define SDIOC_CMD19_HS_BUSTEST_WRITE (19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
|
||||
#define SDIOC_CMD20_WRITE_DAT_UNTIL_STOP (20U) /*!< Speed class control command. */
|
||||
#define SDIOC_CMD23_SET_BLOCK_COUNT (23U) /*!< Specify block count for CMD18 and CMD25. */
|
||||
#define SDIOC_CMD24_WRITE_SINGLE_BLOCK (24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed\
|
||||
512 bytes in case of SDHC and SDXC. */
|
||||
#define SDIOC_CMD25_WRITE_MULTI_BLOCK (25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
|
||||
#define SDIOC_CMD26_PROGRAM_CID (26U) /*!< Reserved for manufacturers. */
|
||||
#define SDIOC_CMD27_PROGRAM_CSD (27U) /*!< Programming of the programmable bits of the CSD. */
|
||||
#define SDIOC_CMD28_SET_WRITE_PROT (28U) /*!< Sets the write protection bit of the addressed group. */
|
||||
#define SDIOC_CMD29_CLR_WRITE_PROT (29U) /*!< Clears the write protection bit of the addressed group. */
|
||||
#define SDIOC_CMD30_SEND_WRITE_PROT (30U) /*!< Asks the card to send the status of the write protection bits. */
|
||||
#define SDIOC_CMD32_ERASE_WR_BLK_START (32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
|
||||
#define SDIOC_CMD33_ERASE_WR_BLK_END (33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
|
||||
#define SDIOC_CMD35_ERASE_GROUP_START (35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system \
|
||||
set by switch function command (CMD6). */
|
||||
#define SDIOC_CMD36_ERASE_GROUP_END (36U) /*!< Sets the address of the last write block of the continuous range to be erased. \
|
||||
Reserved for each command system set by switch function command (CMD6). */
|
||||
#define SDIOC_CMD38_ERASE (38U) /*!< Reserved for SD security applications. */
|
||||
#define SDIOC_CMD39_FAST_IO (39U) /*!< SD card doesn't support it (Reserved). */
|
||||
#define SDIOC_CMD40_GO_IRQ_STATE (40U) /*!< SD card doesn't support it (Reserved). */
|
||||
#define SDIOC_CMD42_LOCK_UNLOCK (42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by \
|
||||
the SET_BLOCK_LEN command. */
|
||||
#define SDIOC_CMD52_IO_RW_DIRECT (52U) /*!< For SD I/O card only, access a single I/O register. */
|
||||
#define SDIOC_CMD53_IO_RW_EXTENDED (53U) /*!< For SD I/O card only, access multiple I/O registers with a single command. */
|
||||
#define SDIOC_CMD55_APP_CMD (55U) /*!< Indicates to the card that the next command is an application specific command rather \
|
||||
than a standard command. */
|
||||
#define SDIOC_CMD56_GEN_CMD (56U) /*!< Used either to transfer a data block to the card or to get a data block from the card \
|
||||
for general purpose/application specific commands. */
|
||||
#define SDIOC_CMD64_NO_CMD (64U) /*!< No command */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIOC_SDMMC_ACMD SDIOC SDMMC ACMD
|
||||
* @{
|
||||
*/
|
||||
/* Following commands are SD Card Specific commands. SDIOC_CMD55_APP_CMD should be sent before sending these commands. */
|
||||
#define SDIOC_ACMD6_SET_BUS_WIDTH (6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus \
|
||||
widths are given in SCR register. */
|
||||
#define SDIOC_ACMD13_SD_STATUS (13U) /*!< (ACMD13) Sends the SD status. */
|
||||
#define SDIOC_ACMD22_SEND_NUM_WR_BLOCKS (22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with \
|
||||
32bit+CRC data block. */
|
||||
#define SDIOC_ACMD23_SET_WR_BLK_ERASE_COUNT (23U) /*!< Set the number of write blocks to be pre-erased before writing (to be used for faster \
|
||||
Multiple Block WR command). */
|
||||
#define SDIOC_ACMD41_SD_APP_OP_COND (41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to \
|
||||
send its operating condition register (OCR) content in the response on the CMD line. */
|
||||
#define SDIOC_ACMD42_SET_CLR_CARD_DETECT (42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
|
||||
#define SDIOC_ACMD51_SEND_SCR (51U) /*!< Reads the SD Configuration Register (SCR). */
|
||||
|
||||
#define SDIOC_ACMD43_GET_MKB (43U)
|
||||
#define SDIOC_ACMD44_GET_MID (44U)
|
||||
#define SDIOC_ACMD45_SET_CER_RN1 (45U)
|
||||
#define SDIOC_ACMD46_GET_CER_RN2 (46U)
|
||||
#define SDIOC_ACMD47_SET_CER_RES2 (47U)
|
||||
#define SDIOC_ACMD48_GET_CER_RES1 (48U)
|
||||
#define SDIOC_ACMD18_SECURE_READ_MULTI_BLOCK (18U)
|
||||
#define SDIOC_ACMD25_SECURE_WRITE_MULTI_BLOCK (25U)
|
||||
#define SDIOC_ACMD38_SECURE_ERASE (38U)
|
||||
#define SDIOC_ACMD49_CHANGE_SECURE_AREA (49U)
|
||||
#define SDIOC_ACMD48_SECURE_WRITE_MKB (48U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDMMC_Error_Code SDMMC Error Code
|
||||
* @{
|
||||
*/
|
||||
#define SDMMC_ERR_NONE (0x00000000UL) /*!< No error */
|
||||
#define SDMMC_ERR_ADDR_OUT_OF_RANGE (0x80000000UL) /*!< Error when addressed block is out of range */
|
||||
#define SDMMC_ERR_ADDR_MISALIGNED (0x40000000UL) /*!< Misaligned address */
|
||||
#define SDMMC_ERR_BLOCK_LEN_ERR (0x20000000UL) /*!< Transferred block length is not allowed for the card or the \
|
||||
number of transferred bytes does not match the block length */
|
||||
#define SDMMC_ERR_ERASE_SEQ_ERR (0x10000000UL) /*!< An error in the sequence of erase command occurs */
|
||||
#define SDMMC_ERR_BAD_ERASE_PARAM (0x08000000UL) /*!< An invalid selection for erase groups */
|
||||
#define SDMMC_ERR_WR_PROT_VIOLATION (0x04000000UL) /*!< Attempt to program a write protect block */
|
||||
#define SDMMC_ERR_LOCK_UNLOCK_FAILED (0x01000000UL) /*!< Sequence or password error has been detected in unlock command \
|
||||
or if there was an attempt to access a locked card */
|
||||
#define SDMMC_ERR_COM_CRC_FAILED (0x00800000UL) /*!< CRC check of the previous command failed */
|
||||
#define SDMMC_ERR_ILLEGAL_CMD (0x00400000UL) /*!< Command is not legal for the card state */
|
||||
#define SDMMC_ERR_CARD_ECC_FAILED (0x00200000UL) /*!< Card internal ECC was applied but failed to correct the data */
|
||||
#define SDMMC_ERR_CC_ERR (0x00100000UL) /*!< Internal card controller error */
|
||||
#define SDMMC_ERR_GENERAL_UNKNOWN_ERR (0x00080000UL) /*!< General or unknown error */
|
||||
#define SDMMC_ERR_STREAM_RD_UNDERRUN (0x00040000UL) /*!< The card could not sustain data reading in stream mode */
|
||||
#define SDMMC_ERR_STREAM_WR_OVERRUN (0x00020000UL) /*!< The card could not sustain data programming in stream mode */
|
||||
#define SDMMC_ERR_CID_CSD_OVERWRITE (0x00010000UL) /*!< CID/CSD overwrite error */
|
||||
#define SDMMC_ERR_WP_ERASE_SKIP (0x00008000UL) /*!< Only partial address space was erased */
|
||||
#define SDMMC_ERR_CARD_ECC_DISABLED (0x00004000UL) /*!< Command has been executed without using internal ECC */
|
||||
#define SDMMC_ERR_ERASE_RST (0x00002000UL) /*!< Erase sequence was cleared before executing because an out of \
|
||||
erase sequence command was received */
|
||||
#define SDMMC_ERR_CMD_AUTO_SEND (0x00001000UL) /*!< An error occurred in sending the command automatically */
|
||||
#define SDMMC_ERR_CMD_INDEX (0x00000800UL) /*!< The received response contains a command number error */
|
||||
#define SDMMC_ERR_CMD_STOP_BIT (0x00000400UL) /*!< Command line detects low level at stop bit */
|
||||
#define SDMMC_ERR_CMD_CRC_FAIL (0x00000200UL) /*!< Command response received (but CRC check failed) */
|
||||
#define SDMMC_ERR_CMD_TIMEOUT (0x00000100UL) /*!< Command response timeout */
|
||||
#define SDMMC_ERR_SWITCH_ERR (0x00000080UL) /*!< The card did not switch to the expected mode as requested by \
|
||||
the SWITCH command */
|
||||
#define SDMMC_ERR_DATA_STOP_BIT (0x00000040UL) /*!< Data line detects low level at stop bit */
|
||||
#define SDMMC_ERR_DATA_CRC_FAIL (0x00000020UL) /*!< Data block sent/received (CRC check failed) */
|
||||
#define SDMMC_ERR_DATA_TIMEOUT (0x00000010UL) /*!< Data timeout */
|
||||
#define SDMMC_ERR_AKE_SEQ_ERR (0x00000008UL) /*!< Error in sequence of authentication */
|
||||
#define SDMMC_ERR_INVD_VOLT (0x00000004UL) /*!< Error in case of invalid voltage range */
|
||||
#define SDMMC_ERR_REQ_NOT_APPLICABLE (0x00000002UL) /*!< Error when command request is not applicable */
|
||||
#define SDMMC_ERR_UNSUPPORT_FEATURE (0x00000001UL) /*!< Error when feature is unsupported */
|
||||
|
||||
#define SDMMC_ERR_BITS_MASK (0xFDFFE048UL) /*!< SD/MMC Error status bits mask */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDMMC_Card_Status_Bit SDMMC Card Status Bit
|
||||
* @{
|
||||
*/
|
||||
#define SDMMC_STATUS_CARD_IS_LOCKED_POS (24U)
|
||||
#define SDMMC_STATUS_CARD_IS_LOCKED (0x02000000UL) /*!< When set, signals that the card is locked by the host */
|
||||
#define SDMMC_STATUS_CURR_STATE_POS (9U)
|
||||
#define SDMMC_STATUS_CURR_STATE (0x00001E00UL) /*!< The state of the card when receiving the command */
|
||||
#define SDMMC_STATUS_RDY_FOR_DATA_POS (8U)
|
||||
#define SDMMC_STATUS_RDY_FOR_DATA (0x00000100UL) /*!< Corresponds to buffer empty signaling on the bus */
|
||||
#define SDMMC_STATUS_APP_CMD_POS (5U)
|
||||
#define SDMMC_STATUS_APP_CMD (0x00000020UL) /*!< The card will expect ACMD, or an indication that the command has been interpreted as ACMD */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDMMC_SCR_Register SDMMC SCR Register
|
||||
* @{
|
||||
*/
|
||||
#define SDMMC_SCR_PHY_SPEC_VER_1P0 (0x00000000UL)
|
||||
#define SDMMC_SCR_PHY_SPEC_VER_1P1 (0x01000000UL)
|
||||
#define SDMMC_SCR_PHY_SPEC_VER_2P0 (0x02000000UL)
|
||||
#define SDMMC_SCR_BUS_WIDTH_4BIT (0x00040000UL)
|
||||
#define SDMMC_SCR_BUS_WIDTH_1BIT (0x00010000UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDMMC_OCR_Register SDMMC OCR Register
|
||||
* @{
|
||||
*/
|
||||
#define SDMMC_OCR_HIGH_CAPACITY (0x40000000UL)
|
||||
#define SDMMC_OCR_STD_CAPACITY (0x00000000UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDMMC_CSD_Register SDMMC CSD Register
|
||||
* @{
|
||||
*/
|
||||
/* Command Class supported */
|
||||
#define SDMMC_CSD_SUPPORT_CLASS5_ERASE (0x00000020UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDMMC_Common_Parameter SDMMC Common Parameter
|
||||
* @{
|
||||
*/
|
||||
#define SDMMC_DATA_TIMEOUT (0x0000FFFFUL)
|
||||
#define SDMMC_MAX_VOLT_TRIAL (0x0000FFFFUL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDMMC_IO_Command_Arguments SDMMC IO Command Arguments
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @defgroup SDIO_CMD52_Arguments SDIO CMD52 Arguments
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @defgroup SDIO_CMD52_Arguments_RW_Flag SDIO CMD52 Arguments RW_Flag
|
||||
* @{
|
||||
*/
|
||||
#define SDIO_CMD52_ARG_RD (0UL << 31)
|
||||
#define SDIO_CMD52_ARG_WR (1UL << 31)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIO_CMD52_Arguments_RAW_Flag SDIO CMD52 Arguments RAW Flag
|
||||
* @{
|
||||
*/
|
||||
#define SDIO_CMD52_ARG_RAW_FLAG_0 (0UL << 27)
|
||||
#define SDIO_CMD52_ARG_RAW_FLAG_1 (1UL << 27)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIO_CMD53_Arguments SDIO CMD53 Arguments
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @defgroup SDIO_CMD53_Arguments_RW_Flag SDIO CMD53 Arguments RW_Flag
|
||||
* @{
|
||||
*/
|
||||
#define SDIO_CMD53_ARG_RD (0UL << 31)
|
||||
#define SDIO_CMD53_ARG_WR (1UL << 31)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIO_CMD53_Arguments_Block_Mode SDIO CMD53 Arguments Block Mode
|
||||
* @{
|
||||
*/
|
||||
#define SDIO_CMD53_ARG_TRANS_MD_BYTE (0UL << 27)
|
||||
#define SDIO_CMD53_ARG_TRANS_MD_BLOCK (1UL << 27)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SDIO_CMD53_Arguments_Operate_Code SDIO CMD53 Arguments Operate Code
|
||||
* @{
|
||||
*/
|
||||
#define SDIO_CMD53_ARG_OP_CODE_ADDR_FIX (0UL << 26)
|
||||
#define SDIO_CMD53_ARG_OP_CODE_ADDR_INC (1UL << 26)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup SDIOC_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
int32_t SDIOC_DeInit(CM_SDIOC_TypeDef *SDIOCx);
|
||||
int32_t SDIOC_Init(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_init_t *pstcSdiocInit);
|
||||
int32_t SDIOC_StructInit(stc_sdioc_init_t *pstcSdiocInit);
|
||||
int32_t SDIOC_SWReset(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Type);
|
||||
void SDIOC_PowerCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState);
|
||||
en_functional_state_t SDIOC_GetPowerState(const CM_SDIOC_TypeDef *SDIOCx);
|
||||
uint32_t SDIOC_GetMode(const CM_SDIOC_TypeDef *SDIOCx);
|
||||
void SDIOC_ClockCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState);
|
||||
void SDIOC_SetClockDiv(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Div);
|
||||
int32_t SDIOC_GetOptimumClockDiv(uint32_t u32ClockFreq, uint16_t *pu16Div);
|
||||
int32_t SDIOC_VerifyClockDiv(uint32_t u32Mode, uint8_t u8SpeedMode, uint16_t u16ClockDiv);
|
||||
en_flag_status_t SDIOC_GetInsertStatus(const CM_SDIOC_TypeDef *SDIOCx);
|
||||
void SDIOC_SetSpeedMode(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8SpeedMode);
|
||||
void SDIOC_SetBusWidth(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8BusWidth);
|
||||
void SDIOC_SetCardDetectSrc(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Src);
|
||||
void SDIOC_SetCardDetectTestLevel(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Level);
|
||||
|
||||
int32_t SDIOC_SendCommand(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_cmd_config_t *pstcCmdConfig);
|
||||
int32_t SDIOC_CommandStructInit(stc_sdioc_cmd_config_t *pstcCmdConfig);
|
||||
int32_t SDIOC_GetResponse(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Reg, uint32_t *pu32Value);
|
||||
int32_t SDIOC_ConfigData(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_data_config_t *pstcDataConfig);
|
||||
int32_t SDIOC_DataStructInit(stc_sdioc_data_config_t *pstcDataConfig);
|
||||
int32_t SDIOC_ReadBuffer(CM_SDIOC_TypeDef *SDIOCx, uint8_t au8Data[], uint32_t u32Len);
|
||||
int32_t SDIOC_WriteBuffer(CM_SDIOC_TypeDef *SDIOCx, const uint8_t au8Data[], uint32_t u32Len);
|
||||
|
||||
void SDIOC_BlockGapStopCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState);
|
||||
void SDIOC_RestartTrans(CM_SDIOC_TypeDef *SDIOCx);
|
||||
void SDIOC_ReadWaitCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState);
|
||||
void SDIOC_BlockGapIntCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState);
|
||||
|
||||
void SDIOC_IntCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType, en_functional_state_t enNewState);
|
||||
en_functional_state_t SDIOC_GetIntEnableState(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType);
|
||||
void SDIOC_IntStatusCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType, en_functional_state_t enNewState);
|
||||
en_flag_status_t SDIOC_GetIntStatus(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag);
|
||||
void SDIOC_ClearIntStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag);
|
||||
en_flag_status_t SDIOC_GetHostStatus(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag);
|
||||
en_flag_status_t SDIOC_GetAutoCmdErrorStatus(const CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Flag);
|
||||
void SDIOC_ForceAutoCmdErrorEvent(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Event);
|
||||
void SDIOC_ForceErrorIntEvent(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Event);
|
||||
|
||||
/* SDMMC Commands management functions */
|
||||
int32_t SDMMC_CMD0_GoIdleState(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD2_AllSendCID(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD3_SendRelativeAddr(CM_SDIOC_TypeDef *SDIOCx, uint16_t *pu16RCA, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD6_SwitchFunc(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD7_SelectDeselectCard(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD8_SendInterfaceCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD9_SendCSD(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD12_StopTrans(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD13_SendStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD16_SetBlockLength(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32BlockLen, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD17_ReadSingleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD18_ReadMultipleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD24_WriteSingleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD25_WriteMultipleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD32_EraseBlockStartAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD33_EraseBlockEndAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD38_Erase(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD55_AppCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus);
|
||||
|
||||
int32_t SDMMC_ACMD6_SetBusWidth(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32BusWidth, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_ACMD13_SendStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_ACMD41_SendOperateCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_ACMD51_SendSCR(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus);
|
||||
|
||||
int32_t SDMMC_CMD1_SendOperateCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD35_EraseGroupStartAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD36_EraseGroupEndAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrStatus);
|
||||
|
||||
int32_t SDMMC_CMD5_IOSendOperateCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD52_IORwDirect(CM_SDIOC_TypeDef *SDIOCx, const stc_sdio_cmd52_arg_t *pstcCmdArg,
|
||||
uint8_t u8In, uint8_t *pu8Out, uint32_t *pu32ErrStatus);
|
||||
int32_t SDMMC_CMD53_IORwExtended(CM_SDIOC_TypeDef *SDIOCx, const stc_sdio_cmd53_arg_t *pstcCmdArg,
|
||||
uint32_t *pu32ErrStatus);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_SDIOC_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_SDIOC_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,457 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_spi.h
|
||||
* @brief This file contains all the functions prototypes of the SPI driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2023-06-30 CDT Add SPI_SetSckPolarity,SPI_SetSckPhase functions
|
||||
Add group SPI_SCK_Polarity_Define, SPI_SCK_Phase_Define
|
||||
Modify return type of fuction SPI_DeInit
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_SPI_H__
|
||||
#define __HC32_LL_SPI_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_SPI_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup SPI_Global_Types SPI Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Structure definition of SPI initialization.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32WireMode; /*!< SPI wire mode, 3 wire mode or 4 wire mode.
|
||||
This parameter can be a value of @ref SPI_Wire_Mode_Define */
|
||||
uint32_t u32TransMode; /*!< SPI transfer mode, send only or full duplex.
|
||||
This parameter can be a value of @ref SPI_Trans_Mode_Define */
|
||||
uint32_t u32MasterSlave; /*!< SPI master/slave mode.
|
||||
This parameter can be a value of @ref SPI_Master_Slave_Mode_Define */
|
||||
uint32_t u32ModeFaultDetect; /*!< SPI mode fault detect command.
|
||||
This parameter can be a value of @ref SPI_Mode_Fault_Detect_Command_Define */
|
||||
uint32_t u32Parity; /*!< SPI parity check selection.
|
||||
This parameter can be a value of @ref SPI_Parity_Check_Define */
|
||||
uint32_t u32SpiMode; /*!< SPI mode.
|
||||
This parameter can be a value of @ref SPI_Mode_Define */
|
||||
uint32_t u32BaudRatePrescaler; /*!< SPI baud rate prescaler.
|
||||
This parameter can be a value of @ref SPI_Baud_Rate_Prescaler_Define */
|
||||
uint32_t u32DataBits; /*!< SPI data bits, 4 bits ~ 32 bits.
|
||||
This parameter can be a value of @ref SPI_Data_Size_Define */
|
||||
uint32_t u32FirstBit; /*!< MSB first or LSB first.
|
||||
This parameter can be a value of @ref SPI_First_Bit_Define */
|
||||
uint32_t u32SuspendMode; /*!< SPI communication suspend function.
|
||||
This parameter can be a value of @ref SPI_Com_Suspend_Func_Define */
|
||||
uint32_t u32FrameLevel; /*!< SPI frame level, SPI_1_FRAME ~ SPI_4_FRAME.
|
||||
This parameter can be a value of @ref SPI_Frame_Level_Define */
|
||||
} stc_spi_init_t;
|
||||
|
||||
/**
|
||||
* @brief Structure definition of SPI delay time configuration.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32IntervalDelay; /*!< SPI interval time delay (Next access delay time)
|
||||
This parameter can be a value of @ref SPI_Interval_Delay_Time_define */
|
||||
uint32_t u32ReleaseDelay; /*!< SPI release time delay (SCK invalid delay time)
|
||||
This parameter can be a value of @ref SPI_Release_Delay_Time_define */
|
||||
uint32_t u32SetupDelay; /*!< SPI Setup time delay (SCK valid delay time) define
|
||||
This parameter can be a value of @ref SPI_Setup_Delay_Time_define */
|
||||
} stc_spi_delay_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup SPI_Global_Macros SPI Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_Wire_Mode_Define SPI Wire Mode Define
|
||||
* @{
|
||||
*/
|
||||
#define SPI_4_WIRE (0UL)
|
||||
#define SPI_3_WIRE (SPI_CR1_SPIMDS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_Trans_Mode_Define SPI Transfer Mode Define
|
||||
* @{
|
||||
*/
|
||||
#define SPI_FULL_DUPLEX (0UL) /*!< Full duplex. */
|
||||
#define SPI_SEND_ONLY (SPI_CR1_TXMDS) /*!< Send only. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_Master_Slave_Mode_Define SPI Master Slave Mode Define
|
||||
* @{
|
||||
*/
|
||||
#define SPI_SLAVE (0UL)
|
||||
#define SPI_MASTER (SPI_CR1_MSTR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_Loopback_Selection_Define SPI Loopback Selection Define
|
||||
* @note Loopback mode is mainly used for parity self-diagnosis in 4-wire full-duplex mode.
|
||||
* @{
|
||||
*/
|
||||
#define SPI_LOOPBACK_INVD (0UL)
|
||||
#define SPI_LOOPBACK_MOSI_INVT (SPI_CR1_SPLPBK) /*!< MISO data is the inverse of the data output by MOSI. */
|
||||
#define SPI_LOOPBACK_MOSI (SPI_CR1_SPLPBK2) /*!< MISO data is the data output by MOSI. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_Int_Type_Define SPI Interrupt Type Define
|
||||
* @{
|
||||
*/
|
||||
#define SPI_INT_ERR (SPI_CR1_EIE) /*!< Including overload, underload and parity error. */
|
||||
#define SPI_INT_TX_BUF_EMPTY (SPI_CR1_TXIE)
|
||||
#define SPI_INT_RX_BUF_FULL (SPI_CR1_RXIE)
|
||||
#define SPI_INT_IDLE (SPI_CR1_IDIE)
|
||||
#define SPI_IRQ_ALL (SPI_INT_ERR | SPI_INT_TX_BUF_EMPTY | SPI_INT_RX_BUF_FULL | SPI_INT_IDLE )
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_Mode_Fault_Detect_Command_Define SPI Mode Fault Detect Command Define
|
||||
* @{
|
||||
*/
|
||||
#define SPI_MD_FAULT_DETECT_DISABLE (0UL) /*!< Disable mode fault detection. */
|
||||
#define SPI_MD_FAULT_DETECT_ENABLE (SPI_CR1_MODFE) /*!< Enable mode fault detection. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_Parity_Check_Define SPI Parity Check Mode Define
|
||||
* @{
|
||||
*/
|
||||
#define SPI_PARITY_INVD (0UL) /*!< Parity check invalid. */
|
||||
#define SPI_PARITY_EVEN (SPI_CR1_PAE) /*!< Parity check selection even parity. */
|
||||
#define SPI_PARITY_ODD (SPI_CR1_PAE | SPI_CR1_PAOE) /*!< Parity check selection odd parity. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_SS_Pin_Define SPI SSx Define
|
||||
* @{
|
||||
*/
|
||||
#define SPI_PIN_SS0 (SPI_CFG1_SS0PV)
|
||||
#define SPI_PIN_SS1 (SPI_CFG1_SS1PV)
|
||||
#define SPI_PIN_SS2 (SPI_CFG1_SS2PV)
|
||||
#define SPI_PIN_SS3 (SPI_CFG1_SS3PV)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_Read_Target_Buf_Define SPI Read Data Register Target Buffer Define
|
||||
* @{
|
||||
*/
|
||||
#define SPI_RD_TARGET_RD_BUF (0UL) /*!< Read RX buffer. */
|
||||
#define SPI_RD_TARGET_WR_BUF (SPI_CFG1_SPRDTD) /*!< Read TX buffer. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_Frame_Level_Define SPI data frame level define, The Data in the SPI_DR register will be send to TX_BUFF
|
||||
* after enough data frame write to the SPI_DR
|
||||
* @{
|
||||
*/
|
||||
#define SPI_1_FRAME (0UL) /*!< Data 1 frame */
|
||||
#define SPI_2_FRAME (SPI_CFG1_FTHLV_0) /*!< Data 2 frame.*/
|
||||
#define SPI_3_FRAME (SPI_CFG1_FTHLV_1) /*!< Data 3 frame.*/
|
||||
#define SPI_4_FRAME (SPI_CFG1_FTHLV) /*!< Data 4 frame.*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_Interval_Delay_Time_define SPI Interval Time Delay (Next Access Delay Time) define
|
||||
* @{
|
||||
*/
|
||||
#define SPI_INTERVAL_TIME_1SCK (0UL << SPI_CFG1_MIDI_POS) /*!< 1 SCK + 2 PCLK1 */
|
||||
#define SPI_INTERVAL_TIME_2SCK (1UL << SPI_CFG1_MIDI_POS) /*!< 2 SCK + 2 PCLK1 */
|
||||
#define SPI_INTERVAL_TIME_3SCK (2UL << SPI_CFG1_MIDI_POS) /*!< 3 SCK + 2 PCLK1 */
|
||||
#define SPI_INTERVAL_TIME_4SCK (3UL << SPI_CFG1_MIDI_POS) /*!< 4 SCK + 2 PCLK1 */
|
||||
#define SPI_INTERVAL_TIME_5SCK (4UL << SPI_CFG1_MIDI_POS) /*!< 5 SCK + 2 PCLK1 */
|
||||
#define SPI_INTERVAL_TIME_6SCK (5UL << SPI_CFG1_MIDI_POS) /*!< 6 SCK + 2 PCLK1 */
|
||||
#define SPI_INTERVAL_TIME_7SCK (6UL << SPI_CFG1_MIDI_POS) /*!< 7 SCK + 2 PCLK1 */
|
||||
#define SPI_INTERVAL_TIME_8SCK (7UL << SPI_CFG1_MIDI_POS) /*!< 8 SCK + 2 PCLK1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_Release_Delay_Time_define SPI Release Time Delay (SCK Invalid Delay Time) Define
|
||||
* @{
|
||||
*/
|
||||
#define SPI_RELEASE_TIME_1SCK (0UL << SPI_CFG1_MSSDL_POS)
|
||||
#define SPI_RELEASE_TIME_2SCK (1UL << SPI_CFG1_MSSDL_POS)
|
||||
#define SPI_RELEASE_TIME_3SCK (2UL << SPI_CFG1_MSSDL_POS)
|
||||
#define SPI_RELEASE_TIME_4SCK (3UL << SPI_CFG1_MSSDL_POS)
|
||||
#define SPI_RELEASE_TIME_5SCK (4UL << SPI_CFG1_MSSDL_POS)
|
||||
#define SPI_RELEASE_TIME_6SCK (5UL << SPI_CFG1_MSSDL_POS)
|
||||
#define SPI_RELEASE_TIME_7SCK (6UL << SPI_CFG1_MSSDL_POS)
|
||||
#define SPI_RELEASE_TIME_8SCK (7UL << SPI_CFG1_MSSDL_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_Setup_Delay_Time_define SPI Setup Time Delay (SCK Valid Delay Time) Define
|
||||
* @{
|
||||
*/
|
||||
#define SPI_SETUP_TIME_1SCK (0UL << SPI_CFG1_MSSI_POS)
|
||||
#define SPI_SETUP_TIME_2SCK (1UL << SPI_CFG1_MSSI_POS)
|
||||
#define SPI_SETUP_TIME_3SCK (2UL << SPI_CFG1_MSSI_POS)
|
||||
#define SPI_SETUP_TIME_4SCK (3UL << SPI_CFG1_MSSI_POS)
|
||||
#define SPI_SETUP_TIME_5SCK (4UL << SPI_CFG1_MSSI_POS)
|
||||
#define SPI_SETUP_TIME_6SCK (5UL << SPI_CFG1_MSSI_POS)
|
||||
#define SPI_SETUP_TIME_7SCK (6UL << SPI_CFG1_MSSI_POS)
|
||||
#define SPI_SETUP_TIME_8SCK (7UL << SPI_CFG1_MSSI_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_Com_Suspend_Func_Define SPI Communication Suspend Function Define
|
||||
* @{
|
||||
*/
|
||||
#define SPI_COM_SUSP_FUNC_OFF (0UL)
|
||||
#define SPI_COM_SUSP_FUNC_ON (SPI_CR1_CSUSPE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_Mode_Define SPI Mode Define
|
||||
* @{
|
||||
*/
|
||||
#define SPI_MD_0 (0UL) /*!< SCK pin output low in idle state; \
|
||||
MOSI/MISO pin data valid in odd edge, \
|
||||
MOSI/MISO pin data change in even edge */
|
||||
#define SPI_MD_1 (SPI_CFG2_CPHA) /*!< SCK pin output low in idle state; \
|
||||
MOSI/MISO pin data valid in even edge, \
|
||||
MOSI/MISO pin data change in odd edge */
|
||||
#define SPI_MD_2 (SPI_CFG2_CPOL) /*!< SCK pin output high in idle state; \
|
||||
MOSI/MISO pin data valid in odd edge, \
|
||||
MOSI/MISO pin data change in even edge */
|
||||
#define SPI_MD_3 (SPI_CFG2_CPOL | SPI_CFG2_CPHA) /*!< SCK pin output high in idle state; \
|
||||
MOSI/MISO pin data valid in even edge, \
|
||||
MOSI/MISO pin data change in odd edge */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_SCK_Polarity_Define SPI SCK Polarity Define
|
||||
* @{
|
||||
*/
|
||||
#define SPI_SCK_POLARITY_LOW (0UL) /*!< SCK pin output low in idle state */
|
||||
#define SPI_SCK_POLARITY_HIGH (SPI_CFG2_CPOL) /*!< SCK pin output high in idle state */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_SCK_Phase_Define SPI SCK Phase Define
|
||||
* @{
|
||||
*/
|
||||
#define SPI_SCK_PHASE_ODD_EDGE_SAMPLE (0UL) /*!< MOSI/MISO pin data sample in odd edge, MOSI/MISO pin data change in even edge */
|
||||
#define SPI_SCK_PHASE_EVEN_EDGE_SAMPLE (SPI_CFG2_CPHA) /*!< MOSI/MISO pin data sample in even edge, MOSI/MISO pin data change in odd edge */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_Baud_Rate_Prescaler_Define SPI Baudrate Prescaler Define
|
||||
* @{
|
||||
*/
|
||||
#define SPI_BR_CLK_DIV2 (0UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 2. */
|
||||
#define SPI_BR_CLK_DIV4 (1UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 4. */
|
||||
#define SPI_BR_CLK_DIV8 (2UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 8. */
|
||||
#define SPI_BR_CLK_DIV16 (3UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 16. */
|
||||
#define SPI_BR_CLK_DIV32 (4UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 32. */
|
||||
#define SPI_BR_CLK_DIV64 (5UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 64. */
|
||||
#define SPI_BR_CLK_DIV128 (6UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 128. */
|
||||
#define SPI_BR_CLK_DIV256 (7UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 256. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_Data_Size_Define SPI Data Size Define
|
||||
* @{
|
||||
*/
|
||||
#define SPI_DATA_SIZE_4BIT (0UL << SPI_CFG2_DSIZE_POS)
|
||||
#define SPI_DATA_SIZE_5BIT (1UL << SPI_CFG2_DSIZE_POS)
|
||||
#define SPI_DATA_SIZE_6BIT (2UL << SPI_CFG2_DSIZE_POS)
|
||||
#define SPI_DATA_SIZE_7BIT (3UL << SPI_CFG2_DSIZE_POS)
|
||||
#define SPI_DATA_SIZE_8BIT (4UL << SPI_CFG2_DSIZE_POS)
|
||||
#define SPI_DATA_SIZE_9BIT (5UL << SPI_CFG2_DSIZE_POS)
|
||||
#define SPI_DATA_SIZE_10BIT (6UL << SPI_CFG2_DSIZE_POS)
|
||||
#define SPI_DATA_SIZE_11BIT (7UL << SPI_CFG2_DSIZE_POS)
|
||||
#define SPI_DATA_SIZE_12BIT (8UL << SPI_CFG2_DSIZE_POS)
|
||||
#define SPI_DATA_SIZE_13BIT (9UL << SPI_CFG2_DSIZE_POS)
|
||||
#define SPI_DATA_SIZE_14BIT (10UL << SPI_CFG2_DSIZE_POS)
|
||||
#define SPI_DATA_SIZE_15BIT (11UL << SPI_CFG2_DSIZE_POS)
|
||||
#define SPI_DATA_SIZE_16BIT (12UL << SPI_CFG2_DSIZE_POS)
|
||||
#define SPI_DATA_SIZE_20BIT (13UL << SPI_CFG2_DSIZE_POS)
|
||||
#define SPI_DATA_SIZE_24BIT (14UL << SPI_CFG2_DSIZE_POS)
|
||||
#define SPI_DATA_SIZE_32BIT (15UL << SPI_CFG2_DSIZE_POS)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_First_Bit_Define SPI First Bit Define
|
||||
* @{
|
||||
*/
|
||||
#define SPI_FIRST_MSB (0UL)
|
||||
#define SPI_FIRST_LSB (SPI_CFG2_LSBF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_State_Flag_Define SPI State Flag Define
|
||||
* @{
|
||||
*/
|
||||
#define SPI_FLAG_OVERLOAD (SPI_SR_OVRERF)
|
||||
#define SPI_FLAG_IDLE (SPI_SR_IDLNF)
|
||||
#define SPI_FLAG_MD_FAULT (SPI_SR_MODFERF)
|
||||
#define SPI_FLAG_PARITY_ERR (SPI_SR_PERF)
|
||||
#define SPI_FLAG_UNDERLOAD (SPI_SR_UDRERF)
|
||||
#define SPI_FLAG_TX_BUF_EMPTY (SPI_SR_TDEF) /*!< This flag is set when the data in the data register \
|
||||
is copied into the shift register, but the transmission \
|
||||
of the data bit may not have been completed. */
|
||||
#define SPI_FLAG_RX_BUF_FULL (SPI_SR_RDFF) /*!< Indicates that a data was received. */
|
||||
#define SPI_FLAG_CLR_ALL (SPI_FLAG_OVERLOAD | SPI_FLAG_MD_FAULT | SPI_FLAG_PARITY_ERR | SPI_FLAG_UNDERLOAD)
|
||||
#define SPI_FLAG_ALL (SPI_FLAG_OVERLOAD | SPI_FLAG_IDLE | SPI_FLAG_MD_FAULT | SPI_FLAG_PARITY_ERR | \
|
||||
SPI_FLAG_UNDERLOAD | SPI_FLAG_TX_BUF_EMPTY | SPI_FLAG_RX_BUF_FULL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup SPI_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
int32_t SPI_StructInit(stc_spi_init_t *pstcSpiInit);
|
||||
int32_t SPI_Init(CM_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInit);
|
||||
int32_t SPI_DeInit(CM_SPI_TypeDef *SPIx);
|
||||
|
||||
void SPI_IntCmd(CM_SPI_TypeDef *SPIx, uint32_t u32IntType, en_functional_state_t enNewState);
|
||||
void SPI_Cmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState);
|
||||
void SPI_WriteData(CM_SPI_TypeDef *SPIx, uint32_t u32Data);
|
||||
uint32_t SPI_ReadData(const CM_SPI_TypeDef *SPIx);
|
||||
|
||||
en_flag_status_t SPI_GetStatus(const CM_SPI_TypeDef *SPIx, uint32_t u32Flag);
|
||||
void SPI_ClearStatus(CM_SPI_TypeDef *SPIx, uint32_t u32Flag);
|
||||
void SPI_LoopbackModeConfig(CM_SPI_TypeDef *SPIx, uint32_t u32Mode);
|
||||
void SPI_ParityCheckCmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState);
|
||||
void SPI_SSValidLevelConfig(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin, en_functional_state_t enNewState);
|
||||
void SPI_SetSckPolarity(CM_SPI_TypeDef *SPIx, uint32_t u32Polarity);
|
||||
void SPI_SetSckPhase(CM_SPI_TypeDef *SPIx, uint32_t u32Phase);
|
||||
|
||||
int32_t SPI_DelayTimeConfig(CM_SPI_TypeDef *SPIx, const stc_spi_delay_t *pstcDelayConfig);
|
||||
void SPI_SSPinSelect(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin);
|
||||
void SPI_ReadBufConfig(CM_SPI_TypeDef *SPIx, uint32_t u32ReadBuf);
|
||||
int32_t SPI_DelayStructInit(stc_spi_delay_t *pstcDelayConfig);
|
||||
|
||||
int32_t SPI_Trans(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32TxLen, uint32_t u32Timeout);
|
||||
int32_t SPI_Receive(CM_SPI_TypeDef *SPIx, void *pvRxBuf, uint32_t u32RxLen, uint32_t u32Timeout);
|
||||
int32_t SPI_TransReceive(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_SPI_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_SPI_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,231 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_sram.h
|
||||
* @brief This file contains all the functions prototypes of the SRAM driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2022-10-31 CDT Deleted redundant comments
|
||||
2023-06-30 CDT Modify typo
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_SRAM_H__
|
||||
#define __HC32_LL_SRAM_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_SRAM
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_SRAM_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup SRAM_Global_Macros SRAM Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SRAM_Sel SRAM Selection
|
||||
* @{
|
||||
*/
|
||||
#define SRAM_SRAMH (1UL << 2U) /*!< SRAMH: 0x1FFF8000~0x1FFFFFFF, 32KB */
|
||||
#define SRAM_SRAM12 (1UL << 0U) /*!< SRAM1: 0x20000000~0x2000FFFF, 64KB
|
||||
SRAM2: 0x20010000~0x2001FFFF, 64KB */
|
||||
#define SRAM_SRAM3 (1UL << 1U) /*!< SRAM3: 0x20020000~0x20026FFF, 28KB */
|
||||
#define SRAM_SRAMR (1UL << 3U) /*!< Ret_SRAM: 0x200F0000~0x200F0FFF, 4KB */
|
||||
#define SRAM_SRAM_ALL (SRAM_SRAMH | SRAM_SRAM12 | SRAM_SRAM3 | SRAM_SRAMR)
|
||||
#define SRAM_ECC_SRAM3 (SRAM_SRAM3)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SRAM_Access_Wait_Cycle SRAM Access Wait Cycle
|
||||
* @{
|
||||
*/
|
||||
#define SRAM_WAIT_CYCLE0 (0U) /*!< Wait 0 CPU cycle. */
|
||||
#define SRAM_WAIT_CYCLE1 (1U) /*!< Wait 1 CPU cycle. */
|
||||
#define SRAM_WAIT_CYCLE2 (2U) /*!< Wait 2 CPU cycles. */
|
||||
#define SRAM_WAIT_CYCLE3 (3U) /*!< Wait 3 CPU cycles. */
|
||||
#define SRAM_WAIT_CYCLE4 (4U) /*!< Wait 4 CPU cycles. */
|
||||
#define SRAM_WAIT_CYCLE5 (5U) /*!< Wait 5 CPU cycles. */
|
||||
#define SRAM_WAIT_CYCLE6 (6U) /*!< Wait 6 CPU cycles. */
|
||||
#define SRAM_WAIT_CYCLE7 (7U) /*!< Wait 7 CPU cycles. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SRAM_Err_Mode SRAM Error Mode
|
||||
* @note Even-parity check error, ECC check error.
|
||||
* @{
|
||||
*/
|
||||
#define SRAM_ERR_MD_NMI (0UL) /*!< Non-maskable interrupt occurrence while check error occurs. */
|
||||
#define SRAM_ERR_MD_RST (1UL) /*!< System reset occurrence while check error occurs. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SRAM_ECC_Mode SRAM ECC Mode
|
||||
* @{
|
||||
*/
|
||||
#define SRAM_ECC_MD_INVD (0U) /*!< The ECC mode is invalid. */
|
||||
#define SRAM_ECC_MD1 (SRAMC_CKCR_ECCMOD_0) /*!< When 1-bit error occurs:
|
||||
ECC error corrects.
|
||||
No 1-bit-error status flag setting, no interrupt or reset.
|
||||
When 2-bit error occurs:
|
||||
ECC error detects.
|
||||
2-bit-error status flag sets and interrupt or reset occurs. */
|
||||
#define SRAM_ECC_MD2 (SRAMC_CKCR_ECCMOD_1) /*!< When 1-bit error occurs:
|
||||
ECC error corrects.
|
||||
1-bit-error status flag sets, no interrupt or reset.
|
||||
When 2-bit error occurs:
|
||||
ECC error detects.
|
||||
2-bit-error status flag sets and interrupt or reset occurs. */
|
||||
#define SRAM_ECC_MD3 (SRAMC_CKCR_ECCMOD) /*!< When 1-bit error occurs:
|
||||
ECC error corrects.
|
||||
1-bit-error status flag sets and interrupt or reset occurs.
|
||||
When 2-bit error occurs:
|
||||
ECC error detects.
|
||||
2-bit-error status flag sets and interrupt or reset occurs. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SRAM_Err_Status_Flag SRAM Error Status Flag
|
||||
* @{
|
||||
*/
|
||||
#define SRAM_FLAG_SRAM3_1ERR (SRAMC_CKSR_SRAM3_1ERR) /*!< SRAM3 ECC 1-bit error. */
|
||||
#define SRAM_FLAG_SRAM3_2ERR (SRAMC_CKSR_SRAM3_2ERR) /*!< SRAM3 ECC 2-bit error. */
|
||||
#define SRAM_FLAG_SRAM12_PYERR (SRAMC_CKSR_SRAM12_PYERR) /*!< SRAM12 parity error. */
|
||||
#define SRAM_FLAG_SRAMH_PYERR (SRAMC_CKSR_SRAMH_PYERR) /*!< SRAMH parity error. */
|
||||
#define SRAM_FLAG_SRAMR_PYERR (SRAMC_CKSR_SRAMR_PYERR) /*!< SRAMR parity error. */
|
||||
#define SRAM_FLAG_ALL (0x1FUL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SRAM_Reg_Protect_Key SRAM Register Protect Key
|
||||
* @{
|
||||
*/
|
||||
#define SRAM_REG_LOCK_KEY (0x76U)
|
||||
#define SRAM_REG_UNLOCK_KEY (0x77U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup SRAM_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Lock SRAM registers, write protect.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void SRAM_REG_Lock(void)
|
||||
{
|
||||
WRITE_REG32(CM_SRAMC->WTPR, SRAM_REG_LOCK_KEY);
|
||||
WRITE_REG32(CM_SRAMC->CKPR, SRAM_REG_LOCK_KEY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unlock SRAM registers, write enable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void SRAM_REG_Unlock(void)
|
||||
{
|
||||
WRITE_REG32(CM_SRAMC->WTPR, SRAM_REG_UNLOCK_KEY);
|
||||
WRITE_REG32(CM_SRAMC->CKPR, SRAM_REG_UNLOCK_KEY);
|
||||
}
|
||||
|
||||
void SRAM_Init(void);
|
||||
void SRAM_DeInit(void);
|
||||
|
||||
void SRAM_REG_Lock(void);
|
||||
void SRAM_REG_Unlock(void);
|
||||
|
||||
void SRAM_SetWaitCycle(uint32_t u32SramSel, uint32_t u32WriteCycle, uint32_t u32ReadCycle);
|
||||
void SRAM_SetEccMode(uint32_t u32SramSel, uint32_t u32EccMode);
|
||||
void SRAM_SetErrorMode(uint32_t u32SramSel, uint32_t u32ErrMode);
|
||||
|
||||
en_flag_status_t SRAM_GetStatus(uint32_t u32Flag);
|
||||
void SRAM_ClearStatus(uint32_t u32Flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_SRAM_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_SRAM_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,129 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_swdt.h
|
||||
* @brief This file contains all the functions prototypes of the SWDT driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_SWDT_H__
|
||||
#define __HC32_LL_SWDT_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_SWDT
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_SWDT_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup SWDT_Global_Macros SWDT Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SWDT_Flag SWDT Flag
|
||||
* @{
|
||||
*/
|
||||
#define SWDT_FLAG_UDF (SWDT_SR_UDF) /*!< Count underflow flag */
|
||||
#define SWDT_FLAG_REFRESH (SWDT_SR_REF) /*!< Refresh error flag */
|
||||
#define SWDT_FLAG_ALL (SWDT_SR_UDF | SWDT_SR_REF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup SWDT_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get SWDT count value.
|
||||
* @param None
|
||||
* @retval uint16_t Count value
|
||||
*/
|
||||
__STATIC_INLINE uint16_t SWDT_GetCountValue(void)
|
||||
{
|
||||
return (uint16_t)(READ_REG32(CM_SWDT->SR) & SWDT_SR_CNT);
|
||||
}
|
||||
|
||||
/* Initialization and configuration functions */
|
||||
void SWDT_FeedDog(void);
|
||||
uint16_t SWDT_GetCountValue(void);
|
||||
|
||||
/* Flags management functions */
|
||||
en_flag_status_t SWDT_GetStatus(uint32_t u32Flag);
|
||||
int32_t SWDT_ClearStatus(uint32_t u32Flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_SWDT_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_SWDT_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,225 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_tmr0.h
|
||||
* @brief This file contains all the functions prototypes of the TMR0 driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2023-06-30 CDT Modify typo
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_TMR0_H__
|
||||
#define __HC32_LL_TMR0_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_TMR0
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_TMR0_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup TMR0_Global_Types TMR0 Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief TMR0 initialization structure definition
|
||||
* @note The 'u32ClockDiv' is invalid when the value of 'u32ClockSrc' is "TMR0_CLK_SRC_SPEC_EVT".
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32ClockSrc; /*!< Specifies the clock source of TMR0 channel.
|
||||
This parameter can be a value of @ref TMR0_Clock_Source */
|
||||
uint32_t u32ClockDiv; /*!< Specifies the clock division of TMR0 channel.
|
||||
This parameter can be a value of @ref TMR0_Clock_Division */
|
||||
uint32_t u32Func; /*!< Specifies the function of TMR0 channel.
|
||||
This parameter can be a value of @ref TMR0_Function */
|
||||
uint16_t u16CompareValue; /*!< Specifies the compare value of TMR0 channel.
|
||||
This parameter can be a value of half-word */
|
||||
} stc_tmr0_init_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup TMR0_Global_Macros TMR0 Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR0_Channel TMR0 Channel
|
||||
* @{
|
||||
*/
|
||||
#define TMR0_CH_A (0UL)
|
||||
#define TMR0_CH_B (1UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR0_Clock_Source TMR0 Clock Source
|
||||
* @note In asynchronous clock, continuous operation of the BCONR register requires waiting for 3 asynchronous clocks.
|
||||
* @{
|
||||
*/
|
||||
#define TMR0_CLK_SRC_INTERN_CLK (0UL) /*!< Internal clock (Synchronous clock) */
|
||||
#define TMR0_CLK_SRC_SPEC_EVT (TMR0_BCONR_SYNCLKA) /*!< Specified event (Synchronous clock) */
|
||||
#define TMR0_CLK_SRC_LRC (TMR0_BCONR_SYNSA) /*!< LRC (Asynchronous clock) */
|
||||
#define TMR0_CLK_SRC_XTAL32 (TMR0_BCONR_ASYNCLKA | TMR0_BCONR_SYNSA) /*!< XTAL32 (Asynchronous clock) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR0_Clock_Division TMR0 Clock Division
|
||||
* @{
|
||||
*/
|
||||
#define TMR0_CLK_DIV1 (0UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK */
|
||||
#define TMR0_CLK_DIV2 (1UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/2 */
|
||||
#define TMR0_CLK_DIV4 (2UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/4 */
|
||||
#define TMR0_CLK_DIV8 (3UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/8 */
|
||||
#define TMR0_CLK_DIV16 (4UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/16 */
|
||||
#define TMR0_CLK_DIV32 (5UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/32 */
|
||||
#define TMR0_CLK_DIV64 (6UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/64 */
|
||||
#define TMR0_CLK_DIV128 (7UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/128 */
|
||||
#define TMR0_CLK_DIV256 (8UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/256 */
|
||||
#define TMR0_CLK_DIV512 (9UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/512 */
|
||||
#define TMR0_CLK_DIV1024 (10UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/1024 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR0_Function TMR0 Function
|
||||
* @{
|
||||
*/
|
||||
#define TMR0_FUNC_CMP (0UL) /*!< Output compare function */
|
||||
#define TMR0_FUNC_CAPT (TMR0_BCONR_CAPMDA | TMR0_BCONR_HICPA) /*!< Input capture function */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR0_Interrupt TMR0 Interrupt
|
||||
* @{
|
||||
*/
|
||||
#define TMR0_INT_CMP_A (TMR0_BCONR_INTENA)
|
||||
#define TMR0_INT_CMP_B (TMR0_BCONR_INTENB)
|
||||
#define TMR0_INT_ALL (TMR0_INT_CMP_A | TMR0_INT_CMP_B)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR0_FLAG TMR0 Flag
|
||||
* @{
|
||||
*/
|
||||
#define TMR0_FLAG_CMP_A (TMR0_STFLR_CMFA)
|
||||
#define TMR0_FLAG_CMP_B (TMR0_STFLR_CMFB)
|
||||
#define TMR0_FLAG_ALL (TMR0_FLAG_CMP_A | TMR0_FLAG_CMP_B)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup TMR0_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization functions */
|
||||
void TMR0_DeInit(CM_TMR0_TypeDef *TMR0x);
|
||||
int32_t TMR0_Init(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, const stc_tmr0_init_t *pstcTmr0Init);
|
||||
int32_t TMR0_StructInit(stc_tmr0_init_t *pstcTmr0Init);
|
||||
void TMR0_Start(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch);
|
||||
void TMR0_Stop(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch);
|
||||
|
||||
/* Control configuration functions */
|
||||
void TMR0_SetCountValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value);
|
||||
uint16_t TMR0_GetCountValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch);
|
||||
void TMR0_SetCompareValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value);
|
||||
uint16_t TMR0_GetCompareValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch);
|
||||
void TMR0_SetClockSrc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Src);
|
||||
void TMR0_SetClockDiv(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Div);
|
||||
void TMR0_SetFunc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Func);
|
||||
|
||||
/* Hardware trigger Functions */
|
||||
void TMR0_HWCaptureCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState);
|
||||
void TMR0_HWStartCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState);
|
||||
void TMR0_HWStopCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState);
|
||||
void TMR0_HWClearCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState);
|
||||
|
||||
/* Interrupt and flag management functions */
|
||||
void TMR0_IntCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32IntType, en_functional_state_t enNewState);
|
||||
en_flag_status_t TMR0_GetStatus(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag);
|
||||
void TMR0_ClearStatus(CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_TMR0_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_TMR0_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,787 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_tmr4.h
|
||||
* @brief This file contains all the functions prototypes of the TMR4
|
||||
* driver library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2022-10-31 CDT Update API parameter u16IntType to u32IntType
|
||||
2023-06-30 CDT Add the macros group @ref TMR4_OC_Output_Polarity
|
||||
Modify typo
|
||||
TMR4_OC_Buffer_Object group add macro-definition: TMR4_OC_BUF_NONE
|
||||
2023-09-30 CDT Modify API TMR4_DeInit
|
||||
Fix spell error about "response" that in function name
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_TMR4_H__
|
||||
#define __HC32_LL_TMR4_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_TMR4
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_TMR4_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup TMR4_Global_Types TMR4 Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief TMR4 Counter function initialization configuration
|
||||
* @note The TMR4 division(u16ClockDiv) is valid when clock source is the internal clock.
|
||||
*/
|
||||
typedef struct {
|
||||
uint16_t u16ClockSrc; /*!< TMR4 counter clock source.
|
||||
This parameter can be a value of @ref TMR4_Count_Clock_Source */
|
||||
uint16_t u16ClockDiv; /*!< TMR4 counter internal clock division.
|
||||
This parameter can be a value of @ref TMR4_Count_Clock_Division. */
|
||||
uint16_t u16CountMode; /*!< TMR4 counter mode.
|
||||
This parameter can be a value of @ref TMR4_Count_Mode */
|
||||
uint16_t u16PeriodValue; /*!< TMR4 counter period value.
|
||||
This parameter can be a value of half-word */
|
||||
} stc_tmr4_init_t;
|
||||
|
||||
/**
|
||||
* @brief The configuration of Output-Compare high channel(OUH/OVH/OWH)
|
||||
*/
|
||||
typedef union {
|
||||
uint16_t OCMRx; /*!< OCMRxH(x=U/V/W) register */
|
||||
|
||||
struct { /*!< OCMRxH(x=U/V/W) register struct field bit */
|
||||
uint16_t OCFDCH : 1; /*!< OCMRxh b0 High channel's OCF status when high channel match occurs at the condition that counter is counting down
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
|
||||
uint16_t OCFPKH : 1; /*!< OCMRxh b1 High channel's OCF status when high channel match occurs at the condition that counter count=Peak
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
|
||||
uint16_t OCFUCH : 1; /*!< OCMRxh b2 High channel's OCF status when high channel match occurs at the condition that counter is counting up
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
|
||||
uint16_t OCFZRH : 1; /*!< OCMRxh b3 High channel's OCF status when high channel match occurs at the condition that counter count=0x0000
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
|
||||
uint16_t OPDCH : 2; /*!< OCMRxh b5~b4 High channel's OP output status when high channel match occurs at the condition that counter is counting down
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
|
||||
uint16_t OPPKH : 2; /*!< OCMRxh b7~b6 High channel's OP output status when high channel match occurs at the condition that counter count=Peak
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
|
||||
uint16_t OPUCH : 2; /*!< OCMRxh b9~b8 High channel's OP output status when high channel match occurs at the condition that counter is counting up
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
|
||||
uint16_t OPZRH : 2; /*!< OCMRxh b11~b10 High channel's OP output status when high channel match occurs at the condition that counter count=0x0000
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
|
||||
uint16_t OPNPKH : 2; /*!< OCMRxh b13~b12 High channel's OP output status when high channel match doesn't occur at the condition that counter count=Peak
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
|
||||
uint16_t OPNZRH : 2; /*!< OCMRxh b15~b14 High channel's OP output status when high channel match doesn't occur at the condition that counter count=0x0000
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
|
||||
} OCMRx_f;
|
||||
} un_tmr4_oc_ocmrh_t;
|
||||
|
||||
/**
|
||||
* @brief The configuration of Output-Compare low channel(OUL/OVL/OWL)
|
||||
*/
|
||||
typedef union {
|
||||
uint32_t OCMRx; /*!< OCMRxL(x=U/V/W) register */
|
||||
|
||||
struct { /*!< OCMRxL(x=U/V/W) register struct field bit*/
|
||||
uint32_t OCFDCL : 1; /*!< OCMRxl b0 Low channel's OCF status when low channel match occurs at the condition that counter is counting down
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
|
||||
uint32_t OCFPKL : 1; /*!< OCMRxl b1 Low channel's OCF status when low channel match occurs at the condition that counter count=Peak
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
|
||||
uint32_t OCFUCL : 1; /*!< OCMRxl b2 Low channel's OCF status when low channel match occurs at the condition that counter is counting up
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
|
||||
uint32_t OCFZRL : 1; /*!< OCMRxl b3 Low channel's OCF status when low channel match occurs at the condition that counter count=0x0000
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
|
||||
uint32_t OPDCL : 2; /*!< OCMRxl b5~b4 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter is counting down
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
|
||||
uint32_t OPPKL : 2; /*!< OCMRxl b7~b6 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter count=Peak
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
|
||||
uint32_t OPUCL : 2; /*!< OCMRxl b9~b8 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter is counting up
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
|
||||
uint32_t OPZRL : 2; /*!< OCMRxl b11~b10 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter count=0x0000
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
|
||||
uint32_t OPNPKL : 2; /*!< OCMRxl b13~b12 Low channel's OP output status when high channel not match and low channel not match occurs at the condition that counter count=Peak
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
|
||||
uint32_t OPNZRL : 2; /*!< OCMRxl b15~b14 Low channel's OP output status when high channel not match and low channel not match occurs at the condition that counter count=0x0000
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
|
||||
uint32_t EOPNDCL : 2; /*!< OCMRxl b17~b16 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter is counting down
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
|
||||
uint32_t EOPNUCL : 2; /*!< OCMRxl b19~b18 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter is counting up
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
|
||||
uint32_t EOPDCL : 2; /*!< OCMRxl b21~b20 Low channel's OP output status when high channel and low channel match occurs at the condition that counter is counting down
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
|
||||
uint32_t EOPPKL : 2; /*!< OCMRxl b23~b22 Low channel's OP output status when high channel and low channel match occurs at the condition that counter count=Peak
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
|
||||
uint32_t EOPUCL : 2; /*!< OCMRxl b25~b24 Low channel's OP output status when high channel and low channel match occurs at the condition that counter is counting up
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
|
||||
uint32_t EOPZRL : 2; /*!< OCMRxl b27~b26 Low channel's OP output status when high channel and low channel match occurs at the condition that counter count=0x0000
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
|
||||
uint32_t EOPNPKL : 2; /*!< OCMRxl b29~b28 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter count=Peak
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
|
||||
uint32_t EOPNZRL : 2; /*!< OCMRxl b31~b30 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter count=0x0000
|
||||
This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
|
||||
} OCMRx_f;
|
||||
} un_tmr4_oc_ocmrl_t;
|
||||
|
||||
/**
|
||||
* @brief TMR4 Output-Compare(OC) initialization configuration
|
||||
*/
|
||||
typedef struct {
|
||||
uint16_t u16CompareValue; /*!< TMR4 OC compare match value.
|
||||
This parameter can be a value of half-word. */
|
||||
uint16_t u16OcInvalidPolarity; /*!< Port output polarity when OC is disabled.
|
||||
This parameter can be a value of @ref TMR4_OC_Invalid_Output_Polarity. */
|
||||
uint16_t u16CompareModeBufCond; /*!< Register OCMR buffer transfer condition.
|
||||
This parameter can be a value of @ref TMR4_OC_Buffer_Transfer_Condition. */
|
||||
uint16_t u16CompareValueBufCond; /*!< Register OCCR buffer transfer condition.
|
||||
This parameter can be a value of @ref TMR4_OC_Buffer_Transfer_Condition. */
|
||||
uint16_t u16BufLinkTransObject; /*!< Enable the specified object(OCMR/OCCR) register buffer linked transfer with the counter interrupt mask.
|
||||
This parameter can be a value of @ref TMR4_OC_Buffer_Object. */
|
||||
} stc_tmr4_oc_init_t;
|
||||
|
||||
/**
|
||||
* @brief TMR4 PWM initialization configuration
|
||||
* @note The clock division(u16ClockDiv) is valid when TMR4 clock source is the internal clock.
|
||||
*/
|
||||
typedef struct {
|
||||
uint16_t u16Mode; /*!< Select PWM mode
|
||||
This parameter can be a value of @ref TMR4_PWM_Mode */
|
||||
uint16_t u16ClockDiv; /*!< The internal clock division of PWM timer.
|
||||
This parameter can be a value of @ref TMR4_PWM_Clock_Division. */
|
||||
uint16_t u16Polarity; /*!< TMR4 PWM polarity
|
||||
This parameter can be a value of @ref TMR4_PWM_Polarity */
|
||||
} stc_tmr4_pwm_init_t;
|
||||
|
||||
/**
|
||||
* @brief TMR4 Special-Event(EVT) initialization configuration
|
||||
*/
|
||||
typedef struct {
|
||||
uint16_t u16Mode; /*!< TMR4 event mode
|
||||
This parameter can be a value of @ref TMR4_Event_Mode */
|
||||
uint16_t u16CompareValue; /*!< TMR4 event compare match value.
|
||||
This parameter can be a value of half-word */
|
||||
uint16_t u16OutputEvent; /*!< TMR4 event output event when match count compare condition.
|
||||
This parameter can be a value of @ref TMR4_Event_Output_Event */
|
||||
uint16_t u16MatchCond; /*!< Enable the specified count compare type with counter count to generate event.
|
||||
This parameter can be a value of @ref TMR4_Event_Match_Condition */
|
||||
} stc_tmr4_evt_init_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup TMR4_Global_Macros TMR4 Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_Counter_Macros TMR4 Counter Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_Count_Clock_Source TMR4 Count Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_CLK_SRC_INTERNCLK (0U)
|
||||
#define TMR4_CLK_SRC_EXTCLK (TMR4_CCSR_ECKEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_Count_Clock_Division TMR4 Count Clock Division
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_CLK_DIV1 (0U << TMR4_CCSR_CKDIV_POS) /*!< CLK */
|
||||
#define TMR4_CLK_DIV2 (1U << TMR4_CCSR_CKDIV_POS) /*!< CLK/2 */
|
||||
#define TMR4_CLK_DIV4 (2U << TMR4_CCSR_CKDIV_POS) /*!< CLK/4 */
|
||||
#define TMR4_CLK_DIV8 (3U << TMR4_CCSR_CKDIV_POS) /*!< CLK/8 */
|
||||
#define TMR4_CLK_DIV16 (4U << TMR4_CCSR_CKDIV_POS) /*!< CLK/16 */
|
||||
#define TMR4_CLK_DIV32 (5U << TMR4_CCSR_CKDIV_POS) /*!< CLK/32 */
|
||||
#define TMR4_CLK_DIV64 (6U << TMR4_CCSR_CKDIV_POS) /*!< CLK/64 */
|
||||
#define TMR4_CLK_DIV128 (7U << TMR4_CCSR_CKDIV_POS) /*!< CLK/128 */
|
||||
#define TMR4_CLK_DIV256 (8U << TMR4_CCSR_CKDIV_POS) /*!< CLK/256 */
|
||||
#define TMR4_CLK_DIV512 (9U << TMR4_CCSR_CKDIV_POS) /*!< CLK/512 */
|
||||
#define TMR4_CLK_DIV1024 (10U << TMR4_CCSR_CKDIV_POS) /*!< CLK/1024 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_Count_Mode TMR4 Count Mode
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_MD_SAWTOOTH (0U)
|
||||
#define TMR4_MD_TRIANGLE (TMR4_CCSR_MODE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_Flag TMR4 Flag
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_FLAG_CNT_PEAK ((uint32_t)TMR4_CCSR_IRQPF) /*!< Count peak flag */
|
||||
#define TMR4_FLAG_CNT_VALLEY ((uint32_t)TMR4_CCSR_IRQZF) /*!< Count valley flag */
|
||||
#define TMR4_FLAG_RELOAD_TMR_U (1UL << 0U) /*!< TMR4 PWM reload-timer flag - channel U */
|
||||
#define TMR4_FLAG_RELOAD_TMR_V (1UL << 4U) /*!< TMR4 PWM reload-timer flag - channel V */
|
||||
#define TMR4_FLAG_RELOAD_TMR_W (1UL << 8U) /*!< TMR4 PWM reload-timer flag - channel W */
|
||||
#define TMR4_FLAG_OC_CMP_UH (1UL << 16U) /*!< TMR4 output-compare compare flag - channel UH */
|
||||
#define TMR4_FLAG_OC_CMP_UL (1UL << 17U) /*!< TMR4 output-compare compare flag - channel UL */
|
||||
#define TMR4_FLAG_OC_CMP_VH (1UL << 18U) /*!< TMR4 output-compare compare flag - channel VH */
|
||||
#define TMR4_FLAG_OC_CMP_VL (1UL << 19U) /*!< TMR4 output-compare compare flag - channel VL */
|
||||
#define TMR4_FLAG_OC_CMP_WH (1UL << 20U) /*!< TMR4 output-compare compare flag - channel WH */
|
||||
#define TMR4_FLAG_OC_CMP_WL (1UL << 21U) /*!< TMR4 output-compare compare flag - channel WL */
|
||||
|
||||
#define TMR4_FLAG_ALL (TMR4_FLAG_CNT_PEAK | TMR4_FLAG_CNT_VALLEY | TMR4_FLAG_RELOAD_TMR_U | \
|
||||
TMR4_FLAG_RELOAD_TMR_V | TMR4_FLAG_RELOAD_TMR_W | TMR4_FLAG_OC_CMP_UH | \
|
||||
TMR4_FLAG_OC_CMP_UL | TMR4_FLAG_OC_CMP_VH | TMR4_FLAG_OC_CMP_VL | \
|
||||
TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_Interrupt TMR4 Interrupt
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_INT_CNT_PEAK ((uint32_t)TMR4_CCSR_IRQPEN) /*!< Count peak interrupt */
|
||||
#define TMR4_INT_CNT_VALLEY ((uint32_t)TMR4_CCSR_IRQZEN) /*!< Count valley interrupt */
|
||||
#define TMR4_INT_RELOAD_TMR_U (1UL << 0U) /*!< TMR4 PWM reload-timer interrupt - channel U */
|
||||
#define TMR4_INT_RELOAD_TMR_V (1UL << 1U) /*!< TMR4 PWM reload-timer interrupt - channel W */
|
||||
#define TMR4_INT_RELOAD_TMR_W (1UL << 2U) /*!< TMR4 PWM reload-timer interrupt - channel V */
|
||||
#define TMR4_INT_OC_CMP_UH (1UL << 16U) /*!< TMR4 output-compare compare interrupt - channel UH */
|
||||
#define TMR4_INT_OC_CMP_UL (1UL << 17U) /*!< TMR4 output-compare compare interrupt - channel UL */
|
||||
#define TMR4_INT_OC_CMP_VH (1UL << 18U) /*!< TMR4 output-compare compare interrupt - channel VH */
|
||||
#define TMR4_INT_OC_CMP_VL (1UL << 19U) /*!< TMR4 output-compare compare interrupt - channel VL */
|
||||
#define TMR4_INT_OC_CMP_WH (1UL << 20U) /*!< TMR4 output-compare compare interrupt - channel WH */
|
||||
#define TMR4_INT_OC_CMP_WL (1UL << 21U) /*!< TMR4 output-compare compare interrupt - channel WL */
|
||||
|
||||
#define TMR4_INT_ALL (TMR4_INT_CNT_PEAK | TMR4_INT_CNT_VALLEY | TMR4_INT_RELOAD_TMR_U | \
|
||||
TMR4_INT_RELOAD_TMR_V | TMR4_INT_RELOAD_TMR_W | TMR4_INT_OC_CMP_UH | \
|
||||
TMR4_INT_OC_CMP_UL | TMR4_INT_OC_CMP_VH | TMR4_INT_OC_CMP_VL | \
|
||||
TMR4_INT_OC_CMP_WH | TMR4_INT_OC_CMP_WL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_Count_Interrupt_Mask_Time TMR4 Count Interrupt Mask Time
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_INT_CNT_MASK0 (0U) /*!< Counter interrupt flag is always set(not masked) for counter count every time at "0x0000" or peak */
|
||||
#define TMR4_INT_CNT_MASK1 (1U) /*!< Counter interrupt flag is set once when counter counts 2 times at "0x0000" or peak (skipping 1 count) */
|
||||
#define TMR4_INT_CNT_MASK2 (2U) /*!< Counter interrupt flag is set once when counter counts 3 times at "0x0000" or peak (skipping 2 count) */
|
||||
#define TMR4_INT_CNT_MASK3 (3U) /*!< Counter interrupt flag is set once when counter counts 4 times at "0x0000" or peak (skipping 3 count) */
|
||||
#define TMR4_INT_CNT_MASK4 (4U) /*!< Counter interrupt flag is set once when counter counts 5 times at "0x0000" or peak (skipping 4 count) */
|
||||
#define TMR4_INT_CNT_MASK5 (5U) /*!< Counter interrupt flag is set once when counter counts 6 times at "0x0000" or peak (skipping 5 count) */
|
||||
#define TMR4_INT_CNT_MASK6 (6U) /*!< Counter interrupt flag is set once when counter counts 7 times at "0x0000" or peak (skipping 6 count) */
|
||||
#define TMR4_INT_CNT_MASK7 (7U) /*!< Counter interrupt flag is set once when counter counts 8 times at "0x0000" or peak (skipping 7 count) */
|
||||
#define TMR4_INT_CNT_MASK8 (8U) /*!< Counter interrupt flag is set once when counter counts 9 times at "0x0000" or peak (skipping 8 count) */
|
||||
#define TMR4_INT_CNT_MASK9 (9U) /*!< Counter interrupt flag is set once when counter counts 10 times at "0x0000" or peak (skipping 9 count) */
|
||||
#define TMR4_INT_CNT_MASK10 (10U) /*!< Counter interrupt flag is set once when counter counts 11 times at "0x0000" or peak (skipping 10 count) */
|
||||
#define TMR4_INT_CNT_MASK11 (11U) /*!< Counter interrupt flag is set once when counter counts 12 times at "0x0000" or peak (skipping 11 count) */
|
||||
#define TMR4_INT_CNT_MASK12 (12U) /*!< Counter interrupt flag is set once when counter counts 13 times at "0x0000" or peak (skipping 12 count) */
|
||||
#define TMR4_INT_CNT_MASK13 (13U) /*!< Counter interrupt flag is set once when counter counts 14 times at "0x0000" or peak (skipping 13 count) */
|
||||
#define TMR4_INT_CNT_MASK14 (14U) /*!< Counter interrupt flag is set once when counter counts 15 times at "0x0000" or peak (skipping 14 count) */
|
||||
#define TMR4_INT_CNT_MASK15 (15U) /*!< Counter interrupt flag is set once when counter counts 16 times at "0x0000" or peak (skipping 15 count) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_Output_Compare_Macros TMR4 Output-Compare Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_OC_Channel TMR4 OC Channel
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_OC_CH_UH (0UL) /*!< TMR4 OC channel:UH */
|
||||
#define TMR4_OC_CH_UL (1UL) /*!< TMR4 OC channel:UL */
|
||||
#define TMR4_OC_CH_VH (2UL) /*!< TMR4 OC channel:VH */
|
||||
#define TMR4_OC_CH_VL (3UL) /*!< TMR4 OC channel:VL */
|
||||
#define TMR4_OC_CH_WH (4UL) /*!< TMR4 OC channel:WH */
|
||||
#define TMR4_OC_CH_WL (5UL) /*!< TMR4 OC channel:WL */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_OC_Invalid_Output_Polarity TMR4 OC Invalid Output Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_OC_INVD_LOW (0U) /*!< TMR4 OC Output low level when OC is invalid */
|
||||
#define TMR4_OC_INVD_HIGH (TMR4_OCSR_OCPH) /*!< TMR4 OC Output high level when OC is invalid */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_OC_Output_Polarity TMR4 OC Output Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_OC_PORT_LOW (0U) /*!< TMR4 OC Output low level */
|
||||
#define TMR4_OC_PORT_HIGH (TMR4_OCSR_OCPH) /*!< TMR4 OC Output high level */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_OC_Buffer_Object TMR4 OC Buffer Object
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_OC_BUF_NONE (0x00U) /*!< Disable the buffer function of OCCR/OCMR */
|
||||
#define TMR4_OC_BUF_CMP_VALUE (0x01U) /*!< The register OCCR buffer function */
|
||||
#define TMR4_OC_BUF_CMP_MD (0x02U) /*!< The register OCMR buffer function */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_OC_Buffer_Transfer_Condition TMR4 OC OCCR Buffer Transfer Condition
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_OC_BUF_COND_IMMED (0U) /*!< Buffer transfer is made when writing to the OCCR/OCMR register. */
|
||||
#define TMR4_OC_BUF_COND_VALLEY (1U) /*!< Buffer transfer is made when counter count valley */
|
||||
#define TMR4_OC_BUF_COND_PEAK (2U) /*!< Buffer transfer is made when counter count peak */
|
||||
#define TMR4_OC_BUF_COND_PEAK_VALLEY (3U) /*!< Buffer transfer is made when counter count peak or valley */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_OC_Count_Match_OCF_State TMR4 OC Count Match OCF State
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_OC_OCF_HOLD (0U) /*!< Hold OCF when the TMR4 OC count match */
|
||||
#define TMR4_OC_OCF_SET (TMR4_OCMRH_OCFDCH) /*!< Set OCF when the TMR4 OC count match */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_OC_Count_Match_Output_Polarity TMR4 OC Count Match Output Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_OC_HOLD (0U) /*!< Hold output when the TMR4 OC count match */
|
||||
#define TMR4_OC_HIGH (1U) /*!< Output high when the TMR4 OC count match */
|
||||
#define TMR4_OC_LOW (2U) /*!< Output low when the TMR4 OC count match */
|
||||
#define TMR4_OC_INVT (3U) /*!< Invert output when the TMR4 OC count match */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_PWM_Macros TMR4 PWM Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_PWM_Channel TMR4 PWM Channel
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_PWM_CH_U (0UL) /*!< TMR4 PWM couple channel: U */
|
||||
#define TMR4_PWM_CH_V (1UL) /*!< TMR4 PWM couple channel: V */
|
||||
#define TMR4_PWM_CH_W (2UL) /*!< TMR4 PWM couple channel: W */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_PWM_Pin TMR4 PWM Pin
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_PWM_PIN_OUH (0UL) /*!< TMR4 PWM port: TIM4_<t>_OUH */
|
||||
#define TMR4_PWM_PIN_OUL (1UL) /*!< TMR4 PWM port: TIM4_<t>_OUL */
|
||||
#define TMR4_PWM_PIN_OVH (2UL) /*!< TMR4 PWM port: TIM4_<t>_OVH */
|
||||
#define TMR4_PWM_PIN_OVL (3UL) /*!< TMR4 PWM port: TIM4_<t>_OVL */
|
||||
#define TMR4_PWM_PIN_OWH (4UL) /*!< TMR4 PWM port: TIM4_<t>_OWH */
|
||||
#define TMR4_PWM_PIN_OWL (5UL) /*!< TMR4 PWM port: TIM4_<t>_OWL */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_PWM_Clock_Division TMR4 PWM Clock Division
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_PWM_CLK_DIV1 (0U) /*!< CLK */
|
||||
#define TMR4_PWM_CLK_DIV2 (1U << TMR4_POCR_DIVCK_POS) /*!< CLK/2 */
|
||||
#define TMR4_PWM_CLK_DIV4 (2U << TMR4_POCR_DIVCK_POS) /*!< CLK/8 */
|
||||
#define TMR4_PWM_CLK_DIV8 (3U << TMR4_POCR_DIVCK_POS) /*!< CLK/8 */
|
||||
#define TMR4_PWM_CLK_DIV16 (4U << TMR4_POCR_DIVCK_POS) /*!< CLK/16 */
|
||||
#define TMR4_PWM_CLK_DIV32 (5U << TMR4_POCR_DIVCK_POS) /*!< CLK/32 */
|
||||
#define TMR4_PWM_CLK_DIV64 (6U << TMR4_POCR_DIVCK_POS) /*!< CLK/64 */
|
||||
#define TMR4_PWM_CLK_DIV128 (7U << TMR4_POCR_DIVCK_POS) /*!< CLK/128 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_PWM_Mode TMR4 PWM Mode
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_PWM_MD_THROUGH (0U) /*!< Through mode */
|
||||
#define TMR4_PWM_MD_DEAD_TMR (TMR4_POCR_PWMMD_0) /*!< Dead timer mode */
|
||||
#define TMR4_PWM_MD_DEAD_TMR_FILTER (TMR4_POCR_PWMMD_1) /*!< Dead timer filter mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_PWM_Polarity TMR4 PWM Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_PWM_OXH_HOLD_OXL_HOLD (0U) /*!< Output PWML and PWMH signals without changing the level */
|
||||
#define TMR4_PWM_OXH_INVT_OXL_INVT (TMR4_POCR_LVLS_0) /*!< Output both PWML and PWMH signals reversed */
|
||||
#define TMR4_PWM_OXH_INVT_OXL_HOLD (TMR4_POCR_LVLS_1) /*!< Output the PWMH signal reversed, outputs the PWML signal without changing the level. */
|
||||
#define TMR4_PWM_OXH_HOLD_OXL_INVT (TMR4_POCR_LVLS) /*!< Output the PWMH signal without changing the level, Outputs the PWML signal reversed. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_PWM_Dead_Time_Register_Index TMR4 PWM Dead Time Register Index
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_PWM_PDAR_IDX (0UL) /*!< TMR4_PDARn(n=U/V/W) */
|
||||
#define TMR4_PWM_PDBR_IDX (1UL) /*!< TMR4_PDBRn(n=U/V/W) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_PWM_Abnormal_Pin_Status TMR4 PWM Abnormal Pin Status
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_PWM_ABNORMAL_PIN_NORMAL (0UL) /*!< TIM4_<t>_Oxy(x=U/V/W, y=H/L) output normal */
|
||||
#define TMR4_PWM_ABNORMAL_PIN_HIZ (1UL) /*!< TIM4_<t>_Oxy(x=U/V/W, y=H/L) to Hi-z */
|
||||
#define TMR4_PWM_ABNORMAL_PIN_LOW (2UL) /*!< TIM4_<t>_Oxy(x=U/V/W, y=H/L) output low level */
|
||||
#define TMR4_PWM_ABNORMAL_PIN_HIGH (3UL) /*!< TIM4_<t>_Oxy(x=U/V/W, y=H/L) output high level */
|
||||
#define TMR4_PWM_ABNORMAL_PIN_HOLD (4UL) /*!< TIM4_<t>_Oxy(x=U/V/W, y=H/L) output hold */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_Event_Macros TMR4 Event Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_Event_Channel TMR4 Event Channel
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_EVT_CH_UH (0UL) /*!< TMR4 EVT channel:UH */
|
||||
#define TMR4_EVT_CH_UL (1UL) /*!< TMR4 EVT channel:UL */
|
||||
#define TMR4_EVT_CH_VH (2UL) /*!< TMR4 EVT channel:VH */
|
||||
#define TMR4_EVT_CH_VL (3UL) /*!< TMR4 EVT channel:VL */
|
||||
#define TMR4_EVT_CH_WH (4UL) /*!< TMR4 EVT channel:WH */
|
||||
#define TMR4_EVT_CH_WL (5UL) /*!< TMR4 EVT channel:WL */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_Event_Match_Condition TMR4 Event Match Condition
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_EVT_MATCH_CNT_UP (TMR4_SCSR_UEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count up */
|
||||
#define TMR4_EVT_MATCH_CNT_DOWN (TMR4_SCSR_DEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count down */
|
||||
#define TMR4_EVT_MATCH_CNT_PEAK (TMR4_SCSR_PEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count peak */
|
||||
#define TMR4_EVT_MATCH_CNT_VALLEY (TMR4_SCSR_ZEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count valley */
|
||||
#define TMR4_EVT_MATCH_CNT_ALL (TMR4_EVT_MATCH_CNT_DOWN | TMR4_EVT_MATCH_CNT_UP | \
|
||||
TMR4_EVT_MATCH_CNT_PEAK | TMR4_EVT_MATCH_CNT_VALLEY)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_Event_Mask TMR4 Event Mask
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_EVT_MASK_PEAK (TMR4_SCMR_MPCE) /*!< Match with the count peak interrupt mask of the counter */
|
||||
#define TMR4_EVT_MASK_VALLEY (TMR4_SCMR_MZCE) /*!< Match with the count valley interrupt mask of the counter */
|
||||
#define TMR4_EVT_MASK_TYPE_ALL (TMR4_EVT_MASK_PEAK | TMR4_EVT_MASK_VALLEY)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_Event_Buffer_Transfer_Condition TMR4 Event Buffer Transfer Condition
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_EVT_BUF_COND_IMMED (0U) /*!< Register SCCR&SCMR buffer transfer when writing to the SCCR&SCMR register */
|
||||
#define TMR4_EVT_BUF_COND_VALLEY (TMR4_SCSR_BUFEN_0) /*!< Register SCCR&SCMR buffer transfer when counter count valley */
|
||||
#define TMR4_EVT_BUF_COND_PEAK (TMR4_SCSR_BUFEN_1) /*!< Register SCCR&SCMR buffer transfer when counter count peak */
|
||||
#define TMR4_EVT_BUF_COND_PEAK_VALLEY (TMR4_SCSR_BUFEN) /*!< Register SCCR&SCMR buffer transfer when counter count peak or valley */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_Event_Mode TMR4 Event Mode
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_EVT_MD_CMP (0U) /*!< TMR4 EVT compare mode */
|
||||
#define TMR4_EVT_MD_DELAY (TMR4_SCSR_EVTMS) /*!< TMR4 EVT delay mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_Event_Delay_Object TMR4 Event Delay Object
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_EVT_DELAY_OCCRXH (0U) /*!< TMR4 EVT delay object: OCCRxh(x=u/v/w) */
|
||||
#define TMR4_EVT_DELAY_OCCRXL (TMR4_SCSR_EVTDS) /*!< TMR4 EVT delay object: OCCRxl(x=u/v/w) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_Event_Mask_Times TMR4 Event Mask Times
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_EVT_MASK0 (0U << TMR4_SCMR_AMC_POS) /*!< Mask 0 time */
|
||||
#define TMR4_EVT_MASK1 (1U << TMR4_SCMR_AMC_POS) /*!< Mask 1 times */
|
||||
#define TMR4_EVT_MASK2 (2U << TMR4_SCMR_AMC_POS) /*!< Mask 2 times */
|
||||
#define TMR4_EVT_MASK3 (3U << TMR4_SCMR_AMC_POS) /*!< Mask 3 times */
|
||||
#define TMR4_EVT_MASK4 (4U << TMR4_SCMR_AMC_POS) /*!< Mask 4 times */
|
||||
#define TMR4_EVT_MASK5 (5U << TMR4_SCMR_AMC_POS) /*!< Mask 5 times */
|
||||
#define TMR4_EVT_MASK6 (6U << TMR4_SCMR_AMC_POS) /*!< Mask 6 times */
|
||||
#define TMR4_EVT_MASK7 (7U << TMR4_SCMR_AMC_POS) /*!< Mask 7 times */
|
||||
#define TMR4_EVT_MASK8 (8U << TMR4_SCMR_AMC_POS) /*!< Mask 8 times */
|
||||
#define TMR4_EVT_MASK9 (9U << TMR4_SCMR_AMC_POS) /*!< Mask 9 times */
|
||||
#define TMR4_EVT_MASK10 (10U << TMR4_SCMR_AMC_POS) /*!< Mask 10 times */
|
||||
#define TMR4_EVT_MASK11 (11U << TMR4_SCMR_AMC_POS) /*!< Mask 11 times */
|
||||
#define TMR4_EVT_MASK12 (12U << TMR4_SCMR_AMC_POS) /*!< Mask 12 times */
|
||||
#define TMR4_EVT_MASK13 (13U << TMR4_SCMR_AMC_POS) /*!< Mask 13 times */
|
||||
#define TMR4_EVT_MASK14 (14U << TMR4_SCMR_AMC_POS) /*!< Mask 14 times */
|
||||
#define TMR4_EVT_MASK15 (15U << TMR4_SCMR_AMC_POS) /*!< Mask 15 times */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_Event_Output_Event TMR4 Event Output Event
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_EVT_OUTPUT_EVT0 (0U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 0 */
|
||||
#define TMR4_EVT_OUTPUT_EVT1 (1U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 1 */
|
||||
#define TMR4_EVT_OUTPUT_EVT2 (2U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 2 */
|
||||
#define TMR4_EVT_OUTPUT_EVT3 (3U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 3 */
|
||||
#define TMR4_EVT_OUTPUT_EVT4 (4U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 4 */
|
||||
#define TMR4_EVT_OUTPUT_EVT5 (5U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 5 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR4_Event_Output_Signal TMR4 Event Output Signal
|
||||
* @{
|
||||
*/
|
||||
#define TMR4_EVT_OUTPUT_NONE (0U) /*!< Disable output event signal of TMR4 Special-EVT */
|
||||
#define TMR4_EVT_OUTPUT_EVT0_SIGNAL (1U) /*!< Output the specified event 0 signal of TMR4 Special-EVT */
|
||||
#define TMR4_EVT_OUTPUT_EVT1_SIGNAL (2U) /*!< Output the specified event 1 signal of TMR4 Special-EVT */
|
||||
#define TMR4_EVT_OUTPUT_EVT2_SIGNAL (3U) /*!< Output the specified event 2 signal of TMR4 Special-EVT */
|
||||
#define TMR4_EVT_OUTPUT_EVT3_SIGNAL (4U) /*!< Output the specified event 3 signal of TMR4 Special-EVT */
|
||||
#define TMR4_EVT_OUTPUT_EVT4_SIGNAL (5U) /*!< Output the specified event 4 signal of TMR4 Special-EVT */
|
||||
#define TMR4_EVT_OUTPUT_EVT5_SIGNAL (6U) /*!< Output the specified event 5 signal of TMR4 Special-EVT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup TMR4_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup TMR4_Counter_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and configuration TMR4 counter functions */
|
||||
int32_t TMR4_StructInit(stc_tmr4_init_t *pstcTmr4Init);
|
||||
int32_t TMR4_Init(CM_TMR4_TypeDef *TMR4x, const stc_tmr4_init_t *pstcTmr4Init);
|
||||
int32_t TMR4_DeInit(CM_TMR4_TypeDef *TMR4x);
|
||||
void TMR4_SetClockSrc(CM_TMR4_TypeDef *TMR4x, uint16_t u16Src);
|
||||
void TMR4_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint16_t u16Div);
|
||||
void TMR4_SetCountMode(CM_TMR4_TypeDef *TMR4x, uint16_t u16Mode);
|
||||
uint16_t TMR4_GetPeriodValue(const CM_TMR4_TypeDef *TMR4x);
|
||||
void TMR4_SetPeriodValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value);
|
||||
uint16_t TMR4_GetCountValue(const CM_TMR4_TypeDef *TMR4x);
|
||||
void TMR4_SetCountValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value);
|
||||
void TMR4_ClearCountValue(CM_TMR4_TypeDef *TMR4x);
|
||||
void TMR4_Start(CM_TMR4_TypeDef *TMR4x);
|
||||
void TMR4_Stop(CM_TMR4_TypeDef *TMR4x);
|
||||
void TMR4_ClearStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag);
|
||||
en_flag_status_t TMR4_GetStatus(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag);
|
||||
void TMR4_IntCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, en_functional_state_t enNewState);
|
||||
void TMR4_PeriodBufCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState);
|
||||
uint16_t TMR4_GetCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType);
|
||||
void TMR4_SetCountIntMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, uint16_t u16MaskTime);
|
||||
uint16_t TMR4_GetCurrentCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup TMR4_Output_Compare_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and configuration TMR4 Output-Compare functions */
|
||||
int32_t TMR4_OC_StructInit(stc_tmr4_oc_init_t *pstcTmr4OcInit);
|
||||
int32_t TMR4_OC_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_oc_init_t *pstcTmr4OcInit);
|
||||
void TMR4_OC_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
|
||||
uint16_t TMR4_OC_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
|
||||
void TMR4_OC_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value);
|
||||
void TMR4_OC_Cmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState);
|
||||
void TMR4_OC_ExtendControlCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState);
|
||||
void TMR4_OC_BufIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch,
|
||||
uint16_t u16Object, en_functional_state_t enNewState);
|
||||
uint16_t TMR4_OC_GetPolarity(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
|
||||
void TMR4_OC_SetOcInvalidPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity);
|
||||
void TMR4_OC_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object, uint16_t u16BufCond);
|
||||
uint16_t TMR4_OC_GetHighChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
|
||||
void TMR4_OC_SetHighChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrh_t unTmr4Ocmrh);
|
||||
uint32_t TMR4_OC_GetLowChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
|
||||
void TMR4_OC_SetLowChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrl_t unTmr4Ocmrl);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup TMR4_PWM_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and configuration TMR4 PWM functions */
|
||||
int32_t TMR4_PWM_StructInit(stc_tmr4_pwm_init_t *pstcTmr4PwmInit);
|
||||
int32_t TMR4_PWM_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_pwm_init_t *pstcTmr4PwmInit);
|
||||
void TMR4_PWM_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
|
||||
void TMR4_PWM_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Div);
|
||||
void TMR4_PWM_SetPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity);
|
||||
void TMR4_PWM_StartReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
|
||||
void TMR4_PWM_StopReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
|
||||
void TMR4_PWM_SetFilterCountValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value);
|
||||
void TMR4_PWM_SetDeadTimeValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex, uint16_t u16Value);
|
||||
uint16_t TMR4_PWM_GetDeadTimeValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex);
|
||||
void TMR4_PWM_SetAbnormalPinStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32PwmPin, uint32_t u32PinStatus);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup TMR4_Event_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and configuration TMR4 event functions */
|
||||
int32_t TMR4_EVT_StructInit(stc_tmr4_evt_init_t *pstcTmr4EventInit);
|
||||
int32_t TMR4_EVT_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_evt_init_t *pstcTmr4EventInit);
|
||||
void TMR4_EVT_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
|
||||
void TMR4_EVT_SetDelayObject(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object);
|
||||
void TMR4_EVT_SetMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16MaskTime);
|
||||
uint16_t TMR4_EVT_GetMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
|
||||
void TMR4_EVT_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value);
|
||||
uint16_t TMR4_EVT_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
|
||||
void TMR4_EVT_SetOutputEvent(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Event);
|
||||
void TMR4_EVT_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16BufCond);
|
||||
void TMR4_EVT_BufIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState);
|
||||
void TMR4_EVT_EventIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch,
|
||||
uint16_t u16MaskType, en_functional_state_t enNewState);
|
||||
void TMR4_EVT_MatchCondCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_TMR4_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_TMR4_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,795 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_tmr6.h
|
||||
* @brief This file contains all the functions prototypes of the TMR6 driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2023-01-15 CDT Modify structure stc_timer6_init_t to stc_tmr6_init_t
|
||||
Modify macro define for group TMR6_hardware_xxx_condition_Define
|
||||
Modify macro define for group TMR6_HW_Count_xx_Cond_Define
|
||||
Modify macro define for group TMR6_Valid_Period_Count_Cond_Define
|
||||
Modify API TMR6_SetFilterClockDiv()
|
||||
2023-06-30 CDT Modify for TMR6_Count_Mode_Define
|
||||
Delete union in stc_tmr6_init_t structure
|
||||
2023-09-30 CDT Add macro define for TMR6_Count_Dir_Status_Define
|
||||
Modify typo
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_TMR6_H__
|
||||
#define __HC32_LL_TMR6_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_TMR6
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_TMR6_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup TMR6_Global_Types TMR6 Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Timer6 count function structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t u8CountSrc; /*!< Specifies the count source @ref TMR6_Count_Src_Define */
|
||||
struct {
|
||||
uint32_t u32ClockDiv; /*!< Count clock division select, @ref TMR6_Count_Clock_Define */
|
||||
uint32_t u32CountMode; /*!< Count mode, @ref TMR6_Count_Mode_Define */
|
||||
uint32_t u32CountDir; /*!< Count direction, @ref TMR6_Count_Dir_Define */
|
||||
} sw_count;
|
||||
struct {
|
||||
uint32_t u32CountUpCond; /*!< Hardware count up condition. @ref TMR6_HW_Count_Up_Cond_Define */
|
||||
uint32_t u32CountDownCond; /*!< Hardware count down condition. @ref TMR6_HW_Count_Down_Cond_Define */
|
||||
} hw_count;
|
||||
uint32_t u32PeriodValue; /*!< The period reference value. (0x00 ~ 0xFFFF) or (0x00 ~ 0xFFFFFFFF) */
|
||||
} stc_tmr6_init_t;
|
||||
|
||||
/**
|
||||
* @brief Timer6 pwm output function structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32CompareValue; /*!< Range (0 ~ 0xFFFF) or (0 ~ 0xFFFFFFFF) */
|
||||
uint32_t u32StartPolarity; /*!< Pin polarity when count start @ref TMR6_Pin_Polarity_Define */
|
||||
uint32_t u32StopPolarity; /*!< Pin polarity when count stop @ref TMR6_Pin_Polarity_Define */
|
||||
uint32_t u32CompareMatchPolarity; /*! Pin polarity when compare register @ref TMR6_Pin_Polarity_Define */
|
||||
uint32_t u32PeriodMatchPolarity; /*! Pin polarity when period register @ref TMR6_Pin_Polarity_Define */
|
||||
uint32_t u32StartStopHold; /*! Pin polarity hold when count re-start or re-stop \
|
||||
@ref TMR6_Output_StaStp_Hold_Define */
|
||||
} stc_tmr6_pwm_init_t;
|
||||
|
||||
/**
|
||||
* @brief Timer6 buffer function configuration structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32BufNum; /*!< The buffer number, and this parameter can be a value of \
|
||||
@ref TMR6_Buf_Num_Define */
|
||||
uint32_t u32BufTransCond; /*!< The buffer send time, and this parameter can be a value of \
|
||||
@ref TMR6_Buf_Trans_Cond_Define */
|
||||
} stc_tmr6_buf_config_t;
|
||||
|
||||
/**
|
||||
* @brief Timer6 Valid period function configuration structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32CountCond; /*!< The count condition, and this parameter can be a value of \
|
||||
@ref TMR6_Valid_Period_Count_Cond_Define */
|
||||
uint32_t u32PeriodInterval; /*!< The interval of the valid period @ref TMR6_Valid_Period_Count_Define */
|
||||
} stc_tmr6_valid_period_config_t;
|
||||
|
||||
/**
|
||||
* @brief Timer6 EMB configuration structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32PinStatus; /*!< Pin output status when EMB event valid @ref TMR6_Emb_Pin_Status_Define */
|
||||
} stc_tmr6_emb_config_t;
|
||||
|
||||
/**
|
||||
* @brief Timer6 Dead time function configuration structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32EqualUpDown; /*!< Enable down count dead time register equal to up count DT register \
|
||||
@ref TMR6_Deadtime_Reg_Equal_Func_Define */
|
||||
uint32_t u32BufUp; /*!< Enable buffer transfer for up count dead time register (DTUBR-->DTUAR) \
|
||||
@ref TMR6_Deadtime_CountUp_Buf_Func_Define*/
|
||||
uint32_t u32BufDown; /*!< Enable buffer transfer for down count dead time register (DTDBR-->DTDAR) \
|
||||
@ref TMR6_Deadtime_CountDown_Buf_Func_Define*/
|
||||
} stc_tmr6_deadtime_config_t;
|
||||
|
||||
/**
|
||||
* @brief Timer6 Dead time function configuration structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32ZMaskCycle; /*!< Z phase input mask periods selection @ref TMR6_Zmask_Cycle_Define */
|
||||
uint32_t u32PosCountMaskFunc; /*!< As position count timer, clear function enable(TRUE) or disable(FALSE) during \
|
||||
the time of Z phase input mask @ref TMR6_Zmask_Pos_Unit_Clear_Func_Define */
|
||||
uint32_t u32RevoCountMaskFunc; /*!< As revolution count timer, the counter function enable(TRUE) or disable(FALSE) \
|
||||
during the time of Z phase input mask \
|
||||
@ref TMR6_Zmask_Revo_Unit_Count_Func_Define*/
|
||||
} stc_tmr6_zmask_config_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup TMR6_Global_Macros TMR6 Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Count_Src_Define TMR6 Count Source Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_CNT_SRC_SW (0U) /*!< Timer6 normal count function */
|
||||
#define TMR6_CNT_SRC_HW (1U) /*!< Timer6 hardware count function */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Stat_Flag_Define TMR6 Status Flag Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_FLAG_MATCH_A (TMR6_STFLR_CMAF) /*!< GCMAR match counter */
|
||||
#define TMR6_FLAG_MATCH_B (TMR6_STFLR_CMBF) /*!< GCMBR match counter */
|
||||
#define TMR6_FLAG_MATCH_C (TMR6_STFLR_CMCF) /*!< GCMCR match counter */
|
||||
#define TMR6_FLAG_MATCH_D (TMR6_STFLR_CMDF) /*!< GCMDR match counter */
|
||||
#define TMR6_FLAG_MATCH_E (TMR6_STFLR_CMEF) /*!< GCMER match counter */
|
||||
#define TMR6_FLAG_MATCH_F (TMR6_STFLR_CMFF) /*!< GCMFR match counter */
|
||||
#define TMR6_FLAG_OVF (TMR6_STFLR_OVFF) /*!< Sawtooth wave counter overflow, \
|
||||
Triangular wave peak point */
|
||||
#define TMR6_FLAG_UDF (TMR6_STFLR_UDFF) /*!< Sawtooth wave counter underflow, \
|
||||
Triangular wave valley point */
|
||||
#define TMR6_FLAG_DEAD_TIME_ERR (TMR6_STFLR_DTEF) /*!< Dead time error */
|
||||
#define TMR6_FLAG_UP_CNT_SPECIAL_MATCH_A (TMR6_STFLR_CMSAUF) /*!< SCMAR match counter when count-up */
|
||||
#define TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_A (TMR6_STFLR_CMSADF) /*!< SCMAR match counter when count-down */
|
||||
#define TMR6_FLAG_UP_CNT_SPECIAL_MATCH_B (TMR6_STFLR_CMSBUF) /*!< SCMBR match counter when count-up */
|
||||
#define TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_B (TMR6_STFLR_CMSBDF) /*!< SCMBR match counter when count-down */
|
||||
#define TMR6_FLAG_CNT_DIR (TMR6_STFLR_DIRF) /*!< Count direction flag */
|
||||
|
||||
#define TMR6_FLAG_CLR_ALL (0x00001EFFUL) /*!< Clear all flag */
|
||||
#define TMR6_FLAG_ALL (TMR6_FLAG_MATCH_A | TMR6_FLAG_MATCH_B | TMR6_FLAG_MATCH_C | \
|
||||
TMR6_FLAG_MATCH_D | TMR6_FLAG_MATCH_E | TMR6_FLAG_MATCH_F | \
|
||||
TMR6_FLAG_OVF | TMR6_FLAG_UDF | TMR6_FLAG_DEAD_TIME_ERR | \
|
||||
TMR6_FLAG_UP_CNT_SPECIAL_MATCH_A | TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_A | \
|
||||
TMR6_FLAG_UP_CNT_SPECIAL_MATCH_B | TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_B | \
|
||||
TMR6_FLAG_CNT_DIR)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Int_Flag_Define TMR6 Interrupt Flag Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_INT_MATCH_A (TMR6_ICONR_INTENA) /*!< GCMAR register matched */
|
||||
#define TMR6_INT_MATCH_B (TMR6_ICONR_INTENB) /*!< GCMBR register matched */
|
||||
#define TMR6_INT_MATCH_C (TMR6_ICONR_INTENC) /*!< GCMCR register matched */
|
||||
#define TMR6_INT_MATCH_D (TMR6_ICONR_INTEND) /*!< GCMDR register matched */
|
||||
#define TMR6_INT_MATCH_E (TMR6_ICONR_INTENE) /*!< GCMER register matched */
|
||||
#define TMR6_INT_MATCH_F (TMR6_ICONR_INTENF) /*!< GCMFR register matched */
|
||||
#define TMR6_INT_OVF (TMR6_ICONR_INTENOVF) /*!< Counter register overflow */
|
||||
#define TMR6_INT_UDF (TMR6_ICONR_INTENUDF) /*!< Counter register underflow */
|
||||
#define TMR6_INT_DEAD_TIME_ERR (TMR6_ICONR_INTENDTE) /*!< Dead time error */
|
||||
#define TMR6_INT_UP_CNT_SPECIAL_MATCH_A (TMR6_ICONR_INTENSAU) /*!< SCMAR register matched when count-up */
|
||||
#define TMR6_INT_DOWN_CNT_SPECIAL_MATCH_A (TMR6_ICONR_INTENSAD) /*!< SCMAR register matched when count-down */
|
||||
#define TMR6_INT_UP_CNT_SPECIAL_MATCH_B (TMR6_ICONR_INTENSBU) /*!< SCMBR register matched when count-up */
|
||||
#define TMR6_INT_DOWN_CNT_SPECIAL_MATCH_B (TMR6_ICONR_INTENSBD) /*!< SCMBR register matched when count-down */
|
||||
#define TMR6_INT_ALL (TMR6_INT_MATCH_A | TMR6_INT_MATCH_B | TMR6_INT_MATCH_C | TMR6_INT_MATCH_D |\
|
||||
TMR6_INT_MATCH_E | TMR6_INT_MATCH_F | TMR6_INT_OVF | TMR6_INT_UDF | \
|
||||
TMR6_INT_DEAD_TIME_ERR | TMR6_INT_UP_CNT_SPECIAL_MATCH_A | \
|
||||
TMR6_INT_DOWN_CNT_SPECIAL_MATCH_A | TMR6_INT_UP_CNT_SPECIAL_MATCH_B | \
|
||||
TMR6_INT_DOWN_CNT_SPECIAL_MATCH_B)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Period_Reg_Index_Define TMR6 Period Register Index Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_PERIOD_REG_A (0x00UL)
|
||||
#define TMR6_PERIOD_REG_B (0x01UL)
|
||||
#define TMR6_PERIOD_REG_C (0x02UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Compare_Reg_Index_Define TMR6 Compare Register Index Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_CMP_REG_A (0x00UL)
|
||||
#define TMR6_CMP_REG_B (0x01UL)
|
||||
#define TMR6_CMP_REG_C (0x02UL)
|
||||
#define TMR6_CMP_REG_D (0x03UL)
|
||||
#define TMR6_CMP_REG_E (0x04UL)
|
||||
#define TMR6_CMP_REG_F (0x05UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Count_Ch_Define TMR6 General/Special Compare Channel Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_CH_A (0x00UL)
|
||||
#define TMR6_CH_B (0x01UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Buf_Num_Define TMR6 Buffer Number Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_BUF_SINGLE (0x00UL)
|
||||
#define TMR6_BUF_DUAL (TMR6_BCONR_BSEA)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Buf_Trans_Cond_Define TMR6 Buffer Transfer Time Configuration Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_BUF_TRANS_INVD (0x00UL)
|
||||
#define TMR6_BUF_TRANS_OVF (0x00000004UL)
|
||||
#define TMR6_BUF_TRANS_UDF (0x00000008UL)
|
||||
#define TMR6_BUF_TRANS_OVF_UDF (0x0000000CUL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Valid_Period_Count_Cond_Define TMR6 Valid Period Function Count Condition Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_VALID_PERIOD_INVD (0x00UL) /*!< Valid period function off */
|
||||
#define TMR6_VALID_PERIOD_CNT_COND_VALLEY (TMR6_VPERR_PCNTE_0) /*!< Count when Sawtooth waveform overflow and underflow, \
|
||||
triangular wave valley */
|
||||
#define TMR6_VALID_PERIOD_CNT_COND_PEAK (TMR6_VPERR_PCNTE_1) /*!< Count when Sawtooth waveform overflow and underflow, \
|
||||
triangular wave peak */
|
||||
#define TMR6_VALID_PERIOD_CNT_COND_VALLEY_PEAK (TMR6_VPERR_PCNTE) /*!< Count when Sawtooth waveform overflow and underflow, \
|
||||
triangular wave valley and peak */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Valid_Period_Count_Define TMR6 Valid Period Function Count Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_VALID_PERIOD_CNT_INVD (0x00UL)
|
||||
#define TMR6_VALID_PERIOD_CNT1 (1UL << TMR6_VPERR_PCNTS_POS)
|
||||
#define TMR6_VALID_PERIOD_CNT2 (2UL << TMR6_VPERR_PCNTS_POS)
|
||||
#define TMR6_VALID_PERIOD_CNT3 (3UL << TMR6_VPERR_PCNTS_POS)
|
||||
#define TMR6_VALID_PERIOD_CNT4 (4UL << TMR6_VPERR_PCNTS_POS)
|
||||
#define TMR6_VALID_PERIOD_CNT5 (5UL << TMR6_VPERR_PCNTS_POS)
|
||||
#define TMR6_VALID_PERIOD_CNT6 (6UL << TMR6_VPERR_PCNTS_POS)
|
||||
#define TMR6_VALID_PERIOD_CNT7 (7UL << TMR6_VPERR_PCNTS_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_DeadTime_Reg_Define TMR6 Dead Time Register Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_DEADTIME_REG_UP_A (0x00U) /*!< Register DTUAR */
|
||||
#define TMR6_DEADTIME_REG_DOWN_A (0x01U) /*!< Register DTDAR */
|
||||
#define TMR6_DEADTIME_REG_UP_B (0x02U) /*!< Register DTUBR */
|
||||
#define TMR6_DEADTIME_REG_DOWN_B (0x03U) /*!< Register DTDBR */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Pin_Define TMR6 Input And Output Pin Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_IO_PWMA (0x00U) /*!< Pin TIM6_<t>_PWMA */
|
||||
#define TMR6_IO_PWMB (0x01U) /*!< Pin TIM6_<t>_PWMB */
|
||||
#define TMR6_INPUT_TRIGA (0x02U) /*!< Input pin TIM6_TRIGA */
|
||||
#define TMR6_INPUT_TRIGB (0x03U) /*!< Input pin TIM6_TRIGB */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Input_Filter_Clock TMR6 Input Pin Filter Clock Divider Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_FILTER_CLK_DIV1 (0x00U)
|
||||
#define TMR6_FILTER_CLK_DIV4 (0x01U)
|
||||
#define TMR6_FILTER_CLK_DIV16 (0x02U)
|
||||
#define TMR6_FILTER_CLK_DIV64 (0x03U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Pin_Mode_Define TMR6 Pin Function Mode Selection
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_PIN_CMP_OUTPUT (0x00UL)
|
||||
#define TMR6_PIN_CAPT_INPUT (TMR6_PCONR_CAPMDA)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Count_State_Define TMR6 Count State
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_STAT_START (0U) /*!< Count start */
|
||||
#define TMR6_STAT_STOP (1U) /*!< Count stop */
|
||||
#define TMR6_STAT_MATCH_CMP (2U) /*!< Count match compare register */
|
||||
#define TMR6_STAT_MATCH_PERIOD (3U) /*!< Count match period register */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Pin_Polarity_Define TMR6 Pin Output Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TMR6_PWM_LOW (0x00U)
|
||||
#define TMR6_PWM_HIGH (0x01U)
|
||||
#define TMR6_PWM_HOLD (0x02U)
|
||||
#define TMR6_PWM_INVT (0x03U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Output_StaStp_Hold_Define TMR6 Output Polarity Hold When Count Start And Stop
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_PWM_START_STOP_HOLD (TMR6_PCONR_STASTPSA)
|
||||
#define TMR6_PWM_START_STOP_CHANGE (0x00UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Emb_Pin_Status_Define TMR6 Pin Output Status When EMB Event Valid
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_EMB_PIN_NORMAL (0x00UL)
|
||||
#define TMR6_EMB_PIN_HIZ (TMR6_PCONR_EMBVALA_0)
|
||||
#define TMR6_EMB_PIN_LOW (TMR6_PCONR_EMBVALA_1)
|
||||
#define TMR6_EMB_PIN_HIGH (TMR6_PCONR_EMBVALA)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Deadtime_CountUp_Buf_Func_Define TMR6 Dead Time Buffer Function For Count Up Stage
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_DEADTIME_CNT_UP_BUF_OFF (0x00UL)
|
||||
#define TMR6_DEADTIME_CNT_UP_BUF_ON (TMR6_DCONR_DTBENU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Deadtime_CountDown_Buf_Func_Define TMR6 Dead Time Buffer Function For Count Down Stage
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_DEADTIME_CNT_DOWN_BUF_OFF (0x00UL)
|
||||
#define TMR6_DEADTIME_CNT_DOWN_BUF_ON (TMR6_DCONR_DTBEND)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Deadtime_Reg_Equal_Func_Define TMR6 Dead Time Function DTDAR Equal DTUAR
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_DEADTIME_EQUAL_OFF (0x00UL)
|
||||
#define TMR6_DEADTIME_EQUAL_ON (TMR6_DCONR_SEPA)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_SW_Sync_Unit_define TMR6 Software Synchronization Start/Stop/Clear/Update Unit Number Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_SW_SYNC_U1 (TMR6CR_SSTAR_SSTA1)
|
||||
#define TMR6_SW_SYNC_U2 (TMR6CR_SSTAR_SSTA2)
|
||||
#define TMR6_SW_SYNC_U3 (TMR6CR_SSTAR_SSTA3)
|
||||
#define TMR6_SW_SYNC_ALL (0x07UL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_hardware_start_condition_Define TMR6 Hardware Start Condition Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_START_COND_EVT0 (TMR6_HSTAR_HSTA0)
|
||||
#define TMR6_START_COND_EVT1 (TMR6_HSTAR_HSTA1)
|
||||
#define TMR6_START_COND_PWMA_RISING (TMR6_HSTAR_HSTA4)
|
||||
#define TMR6_START_COND_PWMA_FALLING (TMR6_HSTAR_HSTA5)
|
||||
#define TMR6_START_COND_PWMB_RISING (TMR6_HSTAR_HSTA6)
|
||||
#define TMR6_START_COND_PWMB_FALLING (TMR6_HSTAR_HSTA7)
|
||||
#define TMR6_START_COND_TRIGA_RISING (TMR6_HSTAR_HSTA8)
|
||||
#define TMR6_START_COND_TRIGA_FALLING (TMR6_HSTAR_HSTA9)
|
||||
#define TMR6_START_COND_TRIGB_RISING (TMR6_HSTAR_HSTA10)
|
||||
#define TMR6_START_COND_TRIGB_FALLING (TMR6_HSTAR_HSTA11)
|
||||
#define TMR6_START_COND_ALL (0x00000FF3UL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_hardware_stop_condition_Define TMR6 Hardware Stop Condition Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_STOP_COND_EVT0 (TMR6_HSTPR_HSTP0)
|
||||
#define TMR6_STOP_COND_EVT1 (TMR6_HSTPR_HSTP1)
|
||||
#define TMR6_STOP_COND_PWMA_RISING (TMR6_HSTPR_HSTP4)
|
||||
#define TMR6_STOP_COND_PWMA_FALLING (TMR6_HSTPR_HSTP5)
|
||||
#define TMR6_STOP_COND_PWMB_RISING (TMR6_HSTPR_HSTP6)
|
||||
#define TMR6_STOP_COND_PWMB_FALLING (TMR6_HSTPR_HSTP7)
|
||||
#define TMR6_STOP_COND_TRIGA_RISING (TMR6_HSTPR_HSTP8)
|
||||
#define TMR6_STOP_COND_TRIGA_FALLING (TMR6_HSTPR_HSTP9)
|
||||
#define TMR6_STOP_COND_TRIGB_RISING (TMR6_HSTPR_HSTP10)
|
||||
#define TMR6_STOP_COND_TRIGB_FALLING (TMR6_HSTPR_HSTP11)
|
||||
#define TMR6_STOP_COND_ALL (0x00000FF3UL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_hardware_clear_condition_Define TMR6 Hardware Clear Condition Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_CLR_COND_EVT0 (TMR6_HCLRR_HCLE0)
|
||||
#define TMR6_CLR_COND_EVT1 (TMR6_HCLRR_HCLE1)
|
||||
#define TMR6_CLR_COND_PWMA_RISING (TMR6_HCLRR_HCLE4)
|
||||
#define TMR6_CLR_COND_PWMA_FALLING (TMR6_HCLRR_HCLE5)
|
||||
#define TMR6_CLR_COND_PWMB_RISING (TMR6_HCLRR_HCLE6)
|
||||
#define TMR6_CLR_COND_PWMB_FALLING (TMR6_HCLRR_HCLE7)
|
||||
#define TMR6_CLR_COND_TRIGA_RISING (TMR6_HCLRR_HCLE8)
|
||||
#define TMR6_CLR_COND_TRIGA_FALLING (TMR6_HCLRR_HCLE9)
|
||||
#define TMR6_CLR_COND_TRIGB_RISING (TMR6_HCLRR_HCLE10)
|
||||
#define TMR6_CLR_COND_TRIGB_FALLING (TMR6_HCLRR_HCLE11)
|
||||
#define TMR6_CLR_COND_ALL (0x00000FF3UL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_hardware_capture_condition_Define TMR6 Hardware Capture Condition Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_CAPT_COND_EVT0 (TMR6_HCPAR_HCPA0)
|
||||
#define TMR6_CAPT_COND_EVT1 (TMR6_HCPAR_HCPA1)
|
||||
#define TMR6_CAPT_COND_PWMA_RISING (TMR6_HCPAR_HCPA4)
|
||||
#define TMR6_CAPT_COND_PWMA_FALLING (TMR6_HCPAR_HCPA5)
|
||||
#define TMR6_CAPT_COND_PWMB_RISING (TMR6_HCPAR_HCPA6)
|
||||
#define TMR6_CAPT_COND_PWMB_FALLING (TMR6_HCPAR_HCPA7)
|
||||
#define TMR6_CAPT_COND_TRIGA_RISING (TMR6_HCPAR_HCPA8)
|
||||
#define TMR6_CAPT_COND_TRIGA_FALLING (TMR6_HCPAR_HCPA9)
|
||||
#define TMR6_CAPT_COND_TRIGB_RISING (TMR6_HCPAR_HCPA10)
|
||||
#define TMR6_CAPT_COND_TRIGB_FALLING (TMR6_HCPAR_HCPA11)
|
||||
#define TMR6_CAPT_COND_ALL (0x00000FF3UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_HW_Count_Up_Cond_Define TMR6 Hardware Count Up Condition Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_CNT_UP_COND_INVD (0U)
|
||||
#define TMR6_CNT_UP_COND_PWMA_LOW_PWMB_RISING (TMR6_HCUPR_HCUP0)
|
||||
#define TMR6_CNT_UP_COND_PWMA_LOW_PWMB_FALLING (TMR6_HCUPR_HCUP1)
|
||||
#define TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING (TMR6_HCUPR_HCUP2)
|
||||
#define TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_FALLING (TMR6_HCUPR_HCUP3)
|
||||
#define TMR6_CNT_UP_COND_PWMB_LOW_PWMA_RISING (TMR6_HCUPR_HCUP4)
|
||||
#define TMR6_CNT_UP_COND_PWMB_LOW_PWMA_FALLING (TMR6_HCUPR_HCUP5)
|
||||
#define TMR6_CNT_UP_COND_PWMB_HIGH_PWMA_RISING (TMR6_HCUPR_HCUP6)
|
||||
#define TMR6_CNT_UP_COND_PWMB_HIGH_PWMA_FALLING (TMR6_HCUPR_HCUP7)
|
||||
#define TMR6_CNT_UP_COND_TRIGA_RISING (TMR6_HCUPR_HCUP8)
|
||||
#define TMR6_CNT_UP_COND_TRIGA_FALLING (TMR6_HCUPR_HCUP9)
|
||||
#define TMR6_CNT_UP_COND_TRIGB_RISING (TMR6_HCUPR_HCUP10)
|
||||
#define TMR6_CNT_UP_COND_TRIGB_FALLING (TMR6_HCUPR_HCUP11)
|
||||
#define TMR6_CNT_UP_COND_EVT0 (TMR6_HCUPR_HCUP16)
|
||||
#define TMR6_CNT_UP_COND_EVT1 (TMR6_HCUPR_HCUP17)
|
||||
#define TMR6_CNT_UP_COND_ALL (0x00030FFFUL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_HW_Count_Down_Cond_Define TMR6 Hardware Count Down Condition Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_CNT_DOWN_COND_INVD (0U)
|
||||
#define TMR6_CNT_DOWN_COND_PWMA_LOW_PWMB_RISING (TMR6_HCDOR_HCDO0)
|
||||
#define TMR6_CNT_DOWN_COND_PWMA_LOW_PWMB_FALLING (TMR6_HCDOR_HCDO1)
|
||||
#define TMR6_CNT_DOWN_COND_PWMA_HIGH_PWMB_RISING (TMR6_HCDOR_HCDO2)
|
||||
#define TMR6_CNT_DOWN_COND_PWMA_HIGH_PWMB_FALLING (TMR6_HCDOR_HCDO3)
|
||||
#define TMR6_CNT_DOWN_COND_PWMB_LOW_PWMA_RISING (TMR6_HCDOR_HCDO4)
|
||||
#define TMR6_CNT_DOWN_COND_PWMB_LOW_PWMA_FALLING (TMR6_HCDOR_HCDO5)
|
||||
#define TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING (TMR6_HCDOR_HCDO6)
|
||||
#define TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_FALLING (TMR6_HCDOR_HCDO7)
|
||||
#define TMR6_CNT_DOWN_COND_TRIGA_RISING (TMR6_HCDOR_HCDO8)
|
||||
#define TMR6_CNT_DOWN_COND_TRIGA_FALLING (TMR6_HCDOR_HCDO9)
|
||||
#define TMR6_CNT_DOWN_COND_TRIGB_RISING (TMR6_HCDOR_HCDO10)
|
||||
#define TMR6_CNT_DOWN_COND_TRIGB_FALLING (TMR6_HCDOR_HCDO11)
|
||||
#define TMR6_CNT_DOWN_COND_EVT0 (TMR6_HCDOR_HCDO16)
|
||||
#define TMR6_CNT_DOWN_COND_EVT1 (TMR6_HCDOR_HCDO17)
|
||||
#define TMR6_CNT_DOWN_COND_ALL (0x00030FFFUL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Count_Dir_Define TMR6 Base Counter Function Direction Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_CNT_UP (TMR6_GCONR_DIR)
|
||||
#define TMR6_CNT_DOWN (0x00UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Count_Dir_Status_Define TMR6 Count Direction Status Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_STAT_CNT_UP (TMR6_STFLR_DIRF)
|
||||
#define TMR6_STAT_CNT_DOWN (0x00UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Count_Mode_Define TMR6 Base Counter Function Mode Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_MD_SAWTOOTH (0x00UL)
|
||||
#define TMR6_MD_TRIANGLE_A (0x04UL << TMR6_GCONR_MODE_POS)
|
||||
#define TMR6_MD_TRIANGLE_B (0x05UL << TMR6_GCONR_MODE_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Count_Clock_Define TMR6 Base Counter Clock Source Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_CLK_DIV1 (0x00UL)
|
||||
#define TMR6_CLK_DIV2 (0x01UL << TMR6_GCONR_CKDIV_POS)
|
||||
#define TMR6_CLK_DIV4 (0x02UL << TMR6_GCONR_CKDIV_POS)
|
||||
#define TMR6_CLK_DIV8 (0x03UL << TMR6_GCONR_CKDIV_POS)
|
||||
#define TMR6_CLK_DIV16 (0x04UL << TMR6_GCONR_CKDIV_POS)
|
||||
#define TMR6_CLK_DIV64 (0x05UL << TMR6_GCONR_CKDIV_POS)
|
||||
#define TMR6_CLK_DIV256 (0x06UL << TMR6_GCONR_CKDIV_POS)
|
||||
#define TMR6_CLK_DIV1024 (0x07UL << TMR6_GCONR_CKDIV_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Zmask_Cycle_Define TMR6 Z Mask Input Function Mask Cycles Number Define
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_ZMASK_FUNC_INVD (0x00UL)
|
||||
#define TMR6_ZMASK_CYCLE_4 (TMR6_GCONR_ZMSKVAL_0)
|
||||
#define TMR6_ZMASK_CYCLE_8 (TMR6_GCONR_ZMSKVAL_1)
|
||||
#define TMR6_ZMASK_CYCLE_16 (TMR6_GCONR_ZMSKVAL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Zmask_Pos_Unit_Clear_Func_Define TMR6 Unit As Position Timer, Z Phase Input Mask Function Define For Clear Action
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_POS_CLR_ZMASK_FUNC_OFF (0x00UL)
|
||||
#define TMR6_POS_CLR_ZMASK_FUNC_ON (TMR6_GCONR_ZMSKPOS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMR6_Zmask_Revo_Unit_Count_Func_Define TMR6 Unit As Revolution Timer, Z Phase Input Mask Function Define For Count Action
|
||||
* @{
|
||||
*/
|
||||
#define TMR6_REVO_CNT_ZMASK_FUNC_OFF (0x00UL)
|
||||
#define TMR6_REVO_CNT_ZMASK_FUNC_ON (TMR6_GCONR_ZMSKREV)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup TMR6_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Get Software Sync start status
|
||||
* @param None
|
||||
* @retval uint32_t Data indicate the read status.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t TMR6_GetSWSyncStartStatus(void)
|
||||
{
|
||||
return READ_REG32(CM_TMR6CR->SSTAR);
|
||||
}
|
||||
|
||||
/* Base count */
|
||||
int32_t TMR6_StructInit(stc_tmr6_init_t *pstcTmr6Init);
|
||||
int32_t TMR6_Init(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_init_t *pstcTmr6Init);
|
||||
|
||||
void TMR6_SetCountMode(CM_TMR6_TypeDef *TMR6x, uint32_t u32Mode);
|
||||
void TMR6_SetCountDir(CM_TMR6_TypeDef *TMR6x, uint32_t u32Dir);
|
||||
uint32_t TMR6_GetCountDir(CM_TMR6_TypeDef *TMR6x);
|
||||
void TMR6_SetClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Div);
|
||||
|
||||
/* Hardware count */
|
||||
void TMR6_HWCountUpCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState);
|
||||
void TMR6_HWCountDownCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState);
|
||||
|
||||
/* PWM output */
|
||||
int32_t TMR6_PWM_StructInit(stc_tmr6_pwm_init_t *pstcPwmInit);
|
||||
int32_t TMR6_PWM_Init(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_pwm_init_t *pstcPwmInit);
|
||||
void TMR6_PWM_OutputCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState);
|
||||
void TMR6_PWM_SetPolarity(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32CountState, uint32_t u32Polarity);
|
||||
void TMR6_PWM_SetStartStopHold(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32HoldStatus);
|
||||
|
||||
/* Input capture */
|
||||
void TMR6_HWCaptureCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState);
|
||||
|
||||
/* Pin config */
|
||||
/* note: Please make sure that peripheral clock of CM_TMR6_1 is valid if The TRIGX pin is used.*/
|
||||
void TMR6_SetFilterClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, uint32_t u32Div);
|
||||
void TMR6_FilterCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, en_functional_state_t enNewState);
|
||||
void TMR6_SetFunc(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Func);
|
||||
|
||||
/* Universal */
|
||||
void TMR6_IntCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32IntType, en_functional_state_t enNewState);
|
||||
en_flag_status_t TMR6_GetStatus(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag);
|
||||
void TMR6_ClearStatus(CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag);
|
||||
uint32_t TMR6_GetPeriodNum(const CM_TMR6_TypeDef *TMR6x);
|
||||
void TMR6_DeInit(CM_TMR6_TypeDef *TMR6x);
|
||||
void TMR6_Start(CM_TMR6_TypeDef *TMR6x);
|
||||
void TMR6_Stop(CM_TMR6_TypeDef *TMR6x);
|
||||
|
||||
/* Register write */
|
||||
void TMR6_SetCountValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Value);
|
||||
void TMR6_SetPeriodValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value);
|
||||
void TMR6_SetCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value);
|
||||
void TMR6_SetSpecialCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value);
|
||||
void TMR6_SetDeadTimeValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value);
|
||||
|
||||
/* Register read */
|
||||
uint32_t TMR6_GetCountValue(const CM_TMR6_TypeDef *TMR6x);
|
||||
uint32_t TMR6_GetPeriodValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index);
|
||||
uint32_t TMR6_GetCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index);
|
||||
uint32_t TMR6_GetSpecialCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index);
|
||||
uint32_t TMR6_GetDeadTimeValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index);
|
||||
|
||||
/* Buffer function */
|
||||
void TMR6_SetGeneralBufNum(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32BufNum);
|
||||
void TMR6_SetPeriodBufNum(CM_TMR6_TypeDef *TMR6x, uint32_t u32BufNum);
|
||||
|
||||
int32_t TMR6_SpecialBufConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_buf_config_t *pstcBufConfig);
|
||||
void TMR6_GeneralBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState);
|
||||
void TMR6_SpecialBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState);
|
||||
void TMR6_PeriodBufCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
|
||||
|
||||
/* Extend function */
|
||||
int32_t TMR6_ValidPeriodConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_valid_period_config_t *pstcValidperiodConfig);
|
||||
void TMR6_ValidPeriodCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState);
|
||||
void TMR6_DeadTimeFuncCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
|
||||
int32_t TMR6_DeadTimeConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_deadtime_config_t *pstcDeadTimeConfig);
|
||||
int32_t TMR6_ZMaskConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_zmask_config_t *pstcZMaskConfig);
|
||||
int32_t TMR6_EMBConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_emb_config_t *pstcEmbConfig);
|
||||
int32_t TMR6_BufFuncStructInit(stc_tmr6_buf_config_t *pstcBufConfig);
|
||||
int32_t TMR6_ValidPeriodStructInit(stc_tmr6_valid_period_config_t *pstcValidperiodConfig);
|
||||
int32_t TMR6_EMBConfigStructInit(stc_tmr6_emb_config_t *pstcEmbConfig);
|
||||
int32_t TMR6_DeadTimeStructInit(stc_tmr6_deadtime_config_t *pstcDeadTimeConfig);
|
||||
int32_t TMR6_ZMaskConfigStructInit(stc_tmr6_zmask_config_t *pstcZMaskConfig);
|
||||
|
||||
/* Software synchronous control */
|
||||
void TMR6_SWSyncStart(uint32_t u32Unit);
|
||||
void TMR6_SWSyncStop(uint32_t u32Unit);
|
||||
void TMR6_SWSyncClear(uint32_t u32Unit);
|
||||
|
||||
/* Hardware control */
|
||||
void TMR6_HWStartCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState);
|
||||
void TMR6_HWStartCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
|
||||
void TMR6_HWStopCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState);
|
||||
void TMR6_HWStopCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
|
||||
void TMR6_HWClearCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState);
|
||||
void TMR6_HWClearCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_TMR6_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_TMR6_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,552 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_tmra.h
|
||||
* @brief This file contains all the functions prototypes of the TMRA(TimerA)
|
||||
* driver library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2022-10-31 CDT Comments optimization
|
||||
2023-06-30 CDT Modify typo
|
||||
Update about split 16bit register TMRA_BCSTR into two 8bit registers TMRA_BCSTRH and TMRA_BCSTRL
|
||||
Delete union in stc_tmra_init_t structure
|
||||
2023-09-30 CDT Modify some of member type of struct stc_tmra_init_t and relate fuction about these member
|
||||
Modify macro-definition value for group TMRA_Interrupt_Type/TMRA_Status_Flag
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_TMRA_H__
|
||||
#define __HC32_LL_TMRA_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_TMRA
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_TMRA_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup TMRA_Global_Types TMRA Global Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief TMRA initialization structure.
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t u8CountSrc; /*!< Specifies the count source of TMRA.
|
||||
This parameter can be a value of @ref TMRA_Count_Src */
|
||||
struct {
|
||||
uint8_t u8ClockDiv; /*!< Specifies the divider of software clock source.
|
||||
This parameter can be a value of @ref TMRA_Clock_Divider */
|
||||
uint8_t u8CountMode; /*!< Specifies count mode.
|
||||
This parameter can be a value of @ref TMRA_Count_Mode */
|
||||
uint8_t u8CountDir; /*!< Specifies count direction.
|
||||
This parameter can be a value of @ref TMRA_Count_Dir */
|
||||
} sw_count;
|
||||
struct {
|
||||
uint16_t u16CountUpCond; /*!< Hardware count up condition.
|
||||
This parameter can be a value of @ref TMRA_Hard_Count_Up_Condition */
|
||||
uint16_t u16CountDownCond; /*!< Hardware count down condition.
|
||||
This parameter can be a value of @ref TMRA_Hard_Count_Down_Condition */
|
||||
} hw_count;
|
||||
uint32_t u32PeriodValue; /*!< Specifies the period reference value.
|
||||
This parameter can be a number between 0U and 0xFFFFU, inclusive. */
|
||||
} stc_tmra_init_t;
|
||||
|
||||
/**
|
||||
* @brief TMRA PWM configuration structure.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32CompareValue; /*!< Specifies compare value of the TMRA channel.
|
||||
This parameter can be a number between:
|
||||
0UL and 0xFFFFFFFFUL for 32-bit TimerA units.
|
||||
0UL and 0xFFFFUL for 16-bit TimerA units. */
|
||||
uint16_t u16StartPolarity; /*!< Specifies the polarity when the counter start counting.
|
||||
This parameter can be a value of @ref TMRA_PWM_Polarity
|
||||
NOTE: CAN NOT be specified as TMRA_PWM_LOW or TMRA_PWM_HIGH when
|
||||
sw_count.u16ClockDiv of @ref stc_tmra_init_t is NOT specified
|
||||
as @ref TMRA_CLK_DIV1 */
|
||||
uint16_t u16StopPolarity; /*!< Specifies the polarity when the counter stop counting.
|
||||
This parameter can be a value of @ref TMRA_PWM_Polarity */
|
||||
uint16_t u16CompareMatchPolarity; /*!< Specifies the polarity when the counter matches the compare register.
|
||||
This parameter can be a value of @ref TMRA_PWM_Polarity */
|
||||
uint16_t u16PeriodMatchPolarity; /*!< Specifies the polarity when the counter matches the period register.
|
||||
This parameter can be a value of @ref TMRA_PWM_Polarity */
|
||||
} stc_tmra_pwm_init_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup TMRA_Global_Macros TMRA Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_Count_Src TMRA Count Source
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_CNT_SRC_SW (0U) /*!< Clock source is PCLK. */
|
||||
#define TMRA_CNT_SRC_HW (1U) /*!< Clock source is from external pin or peripheral event. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_Channel TMRA Channel
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_CH1 (0U) /*!< Channel 1 of TMRA. */
|
||||
#define TMRA_CH2 (1U) /*!< Channel 2 of TMRA. */
|
||||
#define TMRA_CH3 (2U) /*!< Channel 3 of TMRA. */
|
||||
#define TMRA_CH4 (3U) /*!< Channel 4 of TMRA. */
|
||||
#define TMRA_CH5 (4U) /*!< Channel 5 of TMRA. */
|
||||
#define TMRA_CH6 (5U) /*!< Channel 6 of TMRA. */
|
||||
#define TMRA_CH7 (6U) /*!< Channel 7 of TMRA. */
|
||||
#define TMRA_CH8 (7U) /*!< Channel 8 of TMRA. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_Count_Dir TMRA Count Direction
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_DIR_DOWN (0x0U) /*!< TMRA count down. */
|
||||
#define TMRA_DIR_UP (TMRA_BCSTRL_DIR) /*!< TMRA count up. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_Count_Mode TMRA Count Mode
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_MD_SAWTOOTH (0x0U) /*!< Count mode is sawtooth wave. */
|
||||
#define TMRA_MD_TRIANGLE (TMRA_BCSTRL_MODE) /*!< Count mode is triangle wave. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_Function_Mode TMRA TMRA Function Mode
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_FUNC_CMP (0x0U) /*!< Function mode of TMRA channel is ouput compare. */
|
||||
#define TMRA_FUNC_CAPT (TMRA_CCONR_CAPMD) /*!< Function mode of TMRA channel is input capture. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_Clock_Divider TMRA Clock Divider
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_CLK_DIV1 (0x0U) /*!< The clock source of TMRA is PCLK. */
|
||||
#define TMRA_CLK_DIV2 (0x1U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 2. */
|
||||
#define TMRA_CLK_DIV4 (0x2U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 4. */
|
||||
#define TMRA_CLK_DIV8 (0x3U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 8. */
|
||||
#define TMRA_CLK_DIV16 (0x4U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 16. */
|
||||
#define TMRA_CLK_DIV32 (0x5U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 32. */
|
||||
#define TMRA_CLK_DIV64 (0x6U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 64. */
|
||||
#define TMRA_CLK_DIV128 (0x7U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 128. */
|
||||
#define TMRA_CLK_DIV256 (0x8U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 256. */
|
||||
#define TMRA_CLK_DIV512 (0x9U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 512. */
|
||||
#define TMRA_CLK_DIV1024 (0xAU << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 1024. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_Filter_Pin TMRA Pin With Filter
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_PIN_TRIG (0U) /*!< Pin TIMA_<t>_TRIG. */
|
||||
#define TMRA_PIN_CLKA (1U) /*!< Pin TIMA_<t>_CLKA. */
|
||||
#define TMRA_PIN_CLKB (2U) /*!< Pin TIMA_<t>_CLKB. */
|
||||
#define TMRA_PIN_PWM1 (3U) /*!< Pin TIMA_<t>_PWM1. */
|
||||
#define TMRA_PIN_PWM2 (4U) /*!< Pin TIMA_<t>_PWM2. */
|
||||
#define TMRA_PIN_PWM3 (5U) /*!< Pin TIMA_<t>_PWM3. */
|
||||
#define TMRA_PIN_PWM4 (6U) /*!< Pin TIMA_<t>_PWM4. */
|
||||
#define TMRA_PIN_PWM5 (7U) /*!< Pin TIMA_<t>_PWM5. */
|
||||
#define TMRA_PIN_PWM6 (8U) /*!< Pin TIMA_<t>_PWM6. */
|
||||
#define TMRA_PIN_PWM7 (9U) /*!< Pin TIMA_<t>_PWM7. */
|
||||
#define TMRA_PIN_PWM8 (10U) /*!< Pin TIMA_<t>_PWM8. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_Hard_Count_Up_Condition TMRA Hardware Count Up Condition
|
||||
* @note Symmetric units: unit 1 and 2; unit 3 and 4; ...; unit 11 and 12.
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_CNT_UP_COND_INVD (0U) /*!< TMRA hardware count up condition is INVALID. */
|
||||
#define TMRA_CNT_UP_COND_CLKA_LOW_CLKB_RISING (TMRA_HCUPR_HCUP0) /*!< When CLKA is low, a rising edge is sampled on CLKB, the counter register counts up. */
|
||||
#define TMRA_CNT_UP_COND_CLKA_LOW_CLKB_FALLING (TMRA_HCUPR_HCUP1) /*!< When CLKA is low, a falling edge is sampled on CLKB, the counter register counts up. */
|
||||
#define TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING (TMRA_HCUPR_HCUP2) /*!< When CLKA is high, a rising edge is sampled on CLKB, the counter register counts up. */
|
||||
#define TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_FALLING (TMRA_HCUPR_HCUP3) /*!< When CLKA is high, a falling edge is sampled on CLKB, the counter register counts up. */
|
||||
#define TMRA_CNT_UP_COND_CLKB_LOW_CLKA_RISING (TMRA_HCUPR_HCUP4) /*!< When CLKB is low, a rising edge is sampled on CLKA, the counter register counts up. */
|
||||
#define TMRA_CNT_UP_COND_CLKB_LOW_CLKA_FALLING (TMRA_HCUPR_HCUP5) /*!< When CLKB is low, a falling edge is sampled on CLKA, the counter register counts up. */
|
||||
#define TMRA_CNT_UP_COND_CLKB_HIGH_CLKA_RISING (TMRA_HCUPR_HCUP6) /*!< When CLKB is high, a rising edge is sampled on CLKA, the counter register counts up. */
|
||||
#define TMRA_CNT_UP_COND_CLKB_HIGH_CLKA_FALLING (TMRA_HCUPR_HCUP7) /*!< When CLKB is high, a falling edge is sampled on CLKA, the counter register counts up. */
|
||||
#define TMRA_CNT_UP_COND_TRIG_RISING (TMRA_HCUPR_HCUP8) /*!< When a rising edge occurred on TRIG, the counter register counts up. */
|
||||
#define TMRA_CNT_UP_COND_TRIG_FALLING (TMRA_HCUPR_HCUP9) /*!< When a falling edge occurred on TRIG, the counter register counts up. */
|
||||
#define TMRA_CNT_UP_COND_EVT (TMRA_HCUPR_HCUP10) /*!< When the TMRA common trigger event occurred, the counter register counts up. */
|
||||
#define TMRA_CNT_UP_COND_SYM_OVF (TMRA_HCUPR_HCUP11) /*!< When the symmetric unit overflow, the counter register counts up. */
|
||||
#define TMRA_CNT_UP_COND_SYM_UDF (TMRA_HCUPR_HCUP12) /*!< When the symmetric unit underflow, the counter register counts up. */
|
||||
#define TMRA_CNT_UP_COND_ALL (0x1FFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_Hard_Count_Down_Condition TMRA Hardware Count Down Condition
|
||||
* @note Symmetric units: unit 1 and 2; unit 3 and 4; ...; unit 11 and 12.
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_CNT_DOWN_COND_INVD (0U) /*!< TMRA hardware count down condition is INVALID. */
|
||||
#define TMRA_CNT_DOWN_COND_CLKA_LOW_CLKB_RISING (TMRA_HCDOR_HCDO0) /*!< When CLKA is low, a rising edge is sampled on CLKB, the counter register counts down. */
|
||||
#define TMRA_CNT_DOWN_COND_CLKA_LOW_CLKB_FALLING (TMRA_HCDOR_HCDO1) /*!< When CLKA is low, a falling edge is sampled on CLKB, the counter register counts down. */
|
||||
#define TMRA_CNT_DOWN_COND_CLKA_HIGH_CLKB_RISING (TMRA_HCDOR_HCDO2) /*!< When CLKA is high, a rising edge is sampled on CLKB, the counter register counts down. */
|
||||
#define TMRA_CNT_DOWN_COND_CLKA_HIGH_CLKB_FALLING (TMRA_HCDOR_HCDO3) /*!< When CLKA is high, a falling edge is sampled on CLKB, the counter register counts down. */
|
||||
#define TMRA_CNT_DOWN_COND_CLKB_LOW_CLKA_RISING (TMRA_HCDOR_HCDO4) /*!< When CLKB is low, a rising edge is sampled on CLKA, the counter register counts down. */
|
||||
#define TMRA_CNT_DOWN_COND_CLKB_LOW_CLKA_FALLING (TMRA_HCDOR_HCDO5) /*!< When CLKB is low, a falling edge is sampled on CLKA, the counter register counts down. */
|
||||
#define TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING (TMRA_HCDOR_HCDO6) /*!< When CLKB is high, a rising edge is sampled on CLKA, the counter register counts down. */
|
||||
#define TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_FALLING (TMRA_HCDOR_HCDO7) /*!< When CLKB is high, a falling edge is sampled on CLKA, the counter register counts down. */
|
||||
#define TMRA_CNT_DOWN_COND_TRIG_RISING (TMRA_HCDOR_HCDO8) /*!< When a rising edge occurred on TRIG, the counter register counts down. */
|
||||
#define TMRA_CNT_DOWN_COND_TRIG_FALLING (TMRA_HCDOR_HCDO9) /*!< When a falling edge occurred on TRIG, the counter register counts down. */
|
||||
#define TMRA_CNT_DOWN_COND_EVT (TMRA_HCDOR_HCDO10) /*!< When the TMRA common trigger event occurred, the counter register counts down. */
|
||||
#define TMRA_CNT_DOWN_COND_SYM_OVF (TMRA_HCDOR_HCDO11) /*!< When the symmetric unit overflow, the counter register counts down. */
|
||||
#define TMRA_CNT_DOWN_COND_SYM_UDF (TMRA_HCDOR_HCDO12) /*!< When the symmetric unit underflow, the counter register counts down. */
|
||||
#define TMRA_CNT_DOWN_COND_ALL (0x1FFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_Interrupt_Type TMRA Interrupt Type
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_INT_OVF (1UL << 4U) /*!< The interrupt of counting overflow. */
|
||||
#define TMRA_INT_UDF (1UL << 5U) /*!< The interrupt of counting underflow. */
|
||||
#define TMRA_INT_CMP_CH1 (1UL << 16U) /*!< The interrupt of compare-match of channel 1. */
|
||||
#define TMRA_INT_CMP_CH2 (1UL << 17U) /*!< The interrupt of compare-match of channel 2. */
|
||||
#define TMRA_INT_CMP_CH3 (1UL << 18U) /*!< The interrupt of compare-match of channel 3. */
|
||||
#define TMRA_INT_CMP_CH4 (1UL << 19U) /*!< The interrupt of compare-match of channel 4. */
|
||||
#define TMRA_INT_CMP_CH5 (1UL << 20U) /*!< The interrupt of compare-match of channel 5. */
|
||||
#define TMRA_INT_CMP_CH6 (1UL << 21U) /*!< The interrupt of compare-match of channel 6. */
|
||||
#define TMRA_INT_CMP_CH7 (1UL << 22U) /*!< The interrupt of compare-match of channel 7. */
|
||||
#define TMRA_INT_CMP_CH8 (1UL << 23U) /*!< The interrupt of compare-match of channel 8. */
|
||||
#define TMRA_INT_ALL (0xFF0030UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_Event_Type TMRA Event Type
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_EVT_CMP_CH1 (TMRA_ECONR_ETEN1) /*!< The event of compare-match of channel 1. */
|
||||
#define TMRA_EVT_CMP_CH2 (TMRA_ECONR_ETEN2) /*!< The event of compare-match of channel 2. */
|
||||
#define TMRA_EVT_CMP_CH3 (TMRA_ECONR_ETEN3) /*!< The event of compare-match of channel 3. */
|
||||
#define TMRA_EVT_CMP_CH4 (TMRA_ECONR_ETEN4) /*!< The event of compare-match of channel 4. */
|
||||
#define TMRA_EVT_CMP_CH5 (TMRA_ECONR_ETEN5) /*!< The event of compare-match of channel 5. */
|
||||
#define TMRA_EVT_CMP_CH6 (TMRA_ECONR_ETEN6) /*!< The event of compare-match of channel 6. */
|
||||
#define TMRA_EVT_CMP_CH7 (TMRA_ECONR_ETEN7) /*!< The event of compare-match of channel 7. */
|
||||
#define TMRA_EVT_CMP_CH8 (TMRA_ECONR_ETEN8) /*!< The event of compare-match of channel 8. */
|
||||
#define TMRA_EVT_ALL (TMRA_EVT_CMP_CH1 | TMRA_EVT_CMP_CH2 | TMRA_EVT_CMP_CH3 | \
|
||||
TMRA_EVT_CMP_CH4 | TMRA_EVT_CMP_CH5 | TMRA_EVT_CMP_CH6 | \
|
||||
TMRA_EVT_CMP_CH7 | TMRA_EVT_CMP_CH8)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_Status_Flag TMRA Status Flag
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_FLAG_OVF (1UL << 6U) /*!< The flag of counting overflow. */
|
||||
#define TMRA_FLAG_UDF (1UL << 7U) /*!< The flag of counting underflow. */
|
||||
#define TMRA_FLAG_CMP_CH1 (1UL << 16U) /*!< The flag of compare-match of channel 1. */
|
||||
#define TMRA_FLAG_CMP_CH2 (1UL << 17U) /*!< The flag of compare-match of channel 2. */
|
||||
#define TMRA_FLAG_CMP_CH3 (1UL << 18U) /*!< The flag of compare-match of channel 3. */
|
||||
#define TMRA_FLAG_CMP_CH4 (1UL << 19U) /*!< The flag of compare-match of channel 4. */
|
||||
#define TMRA_FLAG_CMP_CH5 (1UL << 20U) /*!< The flag of compare-match of channel 5. */
|
||||
#define TMRA_FLAG_CMP_CH6 (1UL << 21U) /*!< The flag of compare-match of channel 6. */
|
||||
#define TMRA_FLAG_CMP_CH7 (1UL << 22U) /*!< The flag of compare-match of channel 7. */
|
||||
#define TMRA_FLAG_CMP_CH8 (1UL << 23U) /*!< The flag of compare-match of channel 8. */
|
||||
#define TMRA_FLAG_ALL (0xFF00C0UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_Capture_Cond TMRA Capture Condition
|
||||
* @note 'TMRA_CAPT_COND_TRIG_RISING' and 'TMRA_CAPT_COND_TRIG_FALLING' are only valid for channel 4.
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_CAPT_COND_INVD (0x0U) /*!< The condition of capture is INVALID. */
|
||||
#define TMRA_CAPT_COND_PWM_RISING (TMRA_CCONR_HICP0) /*!< The condition of capture is a rising edge is sampled on pin TIMA_<t>_PWMn. */
|
||||
#define TMRA_CAPT_COND_PWM_FALLING (TMRA_CCONR_HICP1) /*!< The condition of capture is a falling edge is sampled on pin TIMA_<t>_PWMn. */
|
||||
#define TMRA_CAPT_COND_EVT (TMRA_CCONR_HICP2) /*!< The condition of capture is the specified event occurred. */
|
||||
#define TMRA_CAPT_COND_TRIG_RISING (TMRA_CCONR_HICP3) /*!< The condition of capture is a rising edge is sampled on pin TIMA_<t>_TRIG.
|
||||
This condition is only valid for channel 4. */
|
||||
#define TMRA_CAPT_COND_TRIG_FALLING (TMRA_CCONR_HICP4) /*!< The condition of capture is a falling edge is sampled on pin TIMA_<t>_TRIG.
|
||||
This condition is only valid for channel 4. */
|
||||
#define TMRA_CAPT_COND_ALL (TMRA_CAPT_COND_PWM_RISING | TMRA_CAPT_COND_PWM_FALLING | \
|
||||
TMRA_CAPT_COND_EVT | TMRA_CAPT_COND_TRIG_RISING | \
|
||||
TMRA_CAPT_COND_TRIG_FALLING)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_Cmp_Value_Buf_Trans_Cond TMRA Compare Value Buffer Transmission Condition
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_BUF_TRANS_COND_OVF_UDF_CLR (0x0U) /*!< This configuration value applies to non-triangular wave counting mode.
|
||||
When counting overflow or underflow or counting register was cleared,
|
||||
transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */
|
||||
#define TMRA_BUF_TRANS_COND_PEAK (TMRA_BCONR_BSE0) /*!< In triangle wave count mode, when count reached peak,
|
||||
transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */
|
||||
#define TMRA_BUF_TRANS_COND_VALLEY (TMRA_BCONR_BSE1) /*!< In triangle wave count mode, when count reached valley,
|
||||
transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,.... */
|
||||
#define TMRA_BUF_TRANS_COND_PEAK_VALLEY (TMRA_BCONR_BSE1 | \
|
||||
TMRA_BCONR_BSE0) /*!< In triangle wave count mode, when count reached peak or valley,
|
||||
transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_Filter_Clock_Divider TMRA Filter Clock Divider
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_FILTER_CLK_DIV1 (0x0U) /*!< The filter clock is the clock of TimerA / 1 */
|
||||
#define TMRA_FILTER_CLK_DIV4 (0x1U) /*!< The filter clock is the clock of TimerA / 4 */
|
||||
#define TMRA_FILTER_CLK_DIV16 (0x2U) /*!< The filter clock is the clock of TimerA / 16 */
|
||||
#define TMRA_FILTER_CLK_DIV64 (0x3U) /*!< The filter clock is the clock of TimerA / 64 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_Counter_State TMRA Counter State
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_CNT_STAT_START (0U) /*!< Counter start counting. */
|
||||
#define TMRA_CNT_STAT_STOP (1U) /*!< Counter stop counting. */
|
||||
#define TMRA_CNT_STAT_MATCH_CMP (2U) /*!< Counter value matches the compare value. */
|
||||
#define TMRA_CNT_STAT_MATCH_PERIOD (3U) /*!< Counter value matches the period value. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_PWM_Polarity TMRA PWM Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_PWM_LOW (0x0U) /*!< PWM output low. */
|
||||
#define TMRA_PWM_HIGH (0x1U) /*!< PWM output high. */
|
||||
#define TMRA_PWM_HOLD (0x2U) /*!< PWM output holds the current polarity. */
|
||||
#define TMRA_PWM_INVT (0x3U) /*!< PWM output reverses the current polarity. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_PWM_Force_Polarity TMRA PWM Force Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_PWM_FORCE_INVD (0x0U) /*!< Force polarity is invalid. */
|
||||
#define TMRA_PWM_FORCE_LOW (TMRA_PCONR_FORC_1) /*!< Force the PWM output low at the beginning of the next cycle.
|
||||
The beginning of the next cycle: overflow position or underflow position
|
||||
of sawtooth wave; valley position of triangle wave. */
|
||||
#define TMRA_PWM_FORCE_HIGH (TMRA_PCONR_FORC) /*!< Force the PWM output high at the beginning of the next cycle.
|
||||
The beginning of the next cycle: overflow position or underflow position
|
||||
of sawtooth wave; valley position of triangle wave. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_Hardware_Start_Condition TMRA Hardware Start Condition
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_START_COND_INVD (0x0U) /*!< The condition of start is INVALID. */
|
||||
#define TMRA_START_COND_TRIG_RISING (TMRA_HCONR_HSTA0) /*!< 1. Sync start is invalid: The condition is that a rising edge is sampled on TRIG of the current TMRA unit.
|
||||
2. Sync start is valid: The condition is that a rising edge is sampled on TRIG of the symmetric TMRA unit. */
|
||||
#define TMRA_START_COND_TRIG_FALLING (TMRA_HCONR_HSTA1) /*!< 1. Sync start is invalid: The condition is that a falling edge is sampled on TRIG of the current TMRA unit.
|
||||
2. Sync start is valid: The condition is that a falling edge is sampled on TRIG of the symmetric TMRA unit. */
|
||||
#define TMRA_START_COND_EVT (TMRA_HCONR_HSTA2) /*!< The condition is that the TMRA common trigger event has occurred. */
|
||||
#define TMRA_START_COND_ALL (TMRA_START_COND_TRIG_RISING | TMRA_START_COND_TRIG_FALLING | \
|
||||
TMRA_START_COND_EVT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_Hardware_Stop_Condition TMRA Hardware Stop Condition
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_STOP_COND_INVD (0x0U) /*!< The condition of stop is INVALID. */
|
||||
#define TMRA_STOP_COND_TRIG_RISING (TMRA_HCONR_HSTP0) /*!< The condition is that a rising edge is sampled on pin TRIG of the current TMRA unit. */
|
||||
#define TMRA_STOP_COND_TRIG_FALLING (TMRA_HCONR_HSTP1) /*!< The condition is that a falling edge is sampled on pin TRIG of the current TMRA unit. */
|
||||
#define TMRA_STOP_COND_EVT (TMRA_HCONR_HSTP2) /*!< The condition is that the TMRA common trigger event has occurred. */
|
||||
#define TMRA_STOP_COND_ALL (TMRA_STOP_COND_TRIG_RISING | TMRA_STOP_COND_TRIG_FALLING | \
|
||||
TMRA_STOP_COND_EVT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TMRA_Hardware_Clear_Condition TMRA Hardware Clear Condition
|
||||
* @note Symmetric units: unit 1 and 2; unit 3 and 4; ... ; unit 11 and 12.
|
||||
* @{
|
||||
*/
|
||||
#define TMRA_CLR_COND_INVD (0x0U) /*!< The condition of clear is INVALID. */
|
||||
#define TMRA_CLR_COND_TRIG_RISING (TMRA_HCONR_HCLE0) /*!< The condition is that a rising edge is sampled on TRIG of the current TMRA unit. */
|
||||
#define TMRA_CLR_COND_TRIG_FALLING (TMRA_HCONR_HCLE1) /*!< The condition is that a falling edge is sampled on TRIG of the current TMRA unit. */
|
||||
#define TMRA_CLR_COND_EVT (TMRA_HCONR_HCLE2) /*!< The condition is that the TMRA common trigger event has occurred. */
|
||||
#define TMRA_CLR_COND_SYM_TRIG_RISING (TMRA_HCONR_HCLE3) /*!< The condition is that a rising edge is sampled on TRIG of the symmetric unit. */
|
||||
#define TMRA_CLR_COND_SYM_TRIG_FALLING (TMRA_HCONR_HCLE4) /*!< The condition is that a falling edge is sampled on TRIG of the symmetric unit. */
|
||||
#define TMRA_CLR_COND_PWM3_RISING (TMRA_HCONR_HCLE5) /*!< The condition is that a rising edge is sampled on PWM3 of the current TMRA unit. */
|
||||
#define TMRA_CLR_COND_PWM3_FALLING (TMRA_HCONR_HCLE6) /*!< The condition is that a falling edge is sampled on PWM3 of the current TMRA unit. */
|
||||
#define TMRA_CLR_COND_ALL (TMRA_CLR_COND_TRIG_RISING | TMRA_CLR_COND_TRIG_FALLING | \
|
||||
TMRA_CLR_COND_EVT| TMRA_CLR_COND_SYM_TRIG_RISING | \
|
||||
TMRA_CLR_COND_SYM_TRIG_FALLING | TMRA_CLR_COND_PWM3_RISING| \
|
||||
TMRA_CLR_COND_PWM3_FALLING)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup TMRA_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
/* Base count(use software clock PCLK/HCLK) */
|
||||
int32_t TMRA_Init(CM_TMRA_TypeDef *TMRAx, const stc_tmra_init_t *pstcTmraInit);
|
||||
int32_t TMRA_StructInit(stc_tmra_init_t *pstcTmraInit);
|
||||
void TMRA_SetCountMode(CM_TMRA_TypeDef *TMRAx, uint8_t u8Mode);
|
||||
void TMRA_SetCountDir(CM_TMRA_TypeDef *TMRAx, uint8_t u8Dir);
|
||||
void TMRA_SetClockDiv(CM_TMRA_TypeDef *TMRAx, uint8_t u8Div);
|
||||
|
||||
/* Hardware count */
|
||||
void TMRA_HWCountUpCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState);
|
||||
void TMRA_HWCountDownCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState);
|
||||
/* Set function mode */
|
||||
void TMRA_SetFunc(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Func);
|
||||
|
||||
/* Ouput compare */
|
||||
int32_t TMRA_PWM_Init(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, const stc_tmra_pwm_init_t *pstcPwmInit);
|
||||
int32_t TMRA_PWM_StructInit(stc_tmra_pwm_init_t *pstcPwmInit);
|
||||
void TMRA_PWM_OutputCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState);
|
||||
void TMRA_PWM_SetPolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint8_t u8CountState, uint16_t u16Polarity);
|
||||
void TMRA_PWM_SetForcePolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Polarity);
|
||||
/* Input capture */
|
||||
void TMRA_HWCaptureCondCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState);
|
||||
|
||||
/* Trigger: hardware trigger to start/stop/clear the counter */
|
||||
void TMRA_HWStartCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState);
|
||||
void TMRA_HWStopCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState);
|
||||
void TMRA_HWClearCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState);
|
||||
|
||||
/* Filter */
|
||||
void TMRA_SetFilterClockDiv(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, uint16_t u16Div);
|
||||
void TMRA_FilterCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, en_functional_state_t enNewState);
|
||||
|
||||
/* Global */
|
||||
void TMRA_DeInit(CM_TMRA_TypeDef *TMRAx);
|
||||
/* Counting direction, period value, counter value, compare value */
|
||||
uint8_t TMRA_GetCountDir(const CM_TMRA_TypeDef *TMRAx);
|
||||
|
||||
void TMRA_SetPeriodValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value);
|
||||
uint32_t TMRA_GetPeriodValue(const CM_TMRA_TypeDef *TMRAx);
|
||||
void TMRA_SetCountValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value);
|
||||
uint32_t TMRA_GetCountValue(const CM_TMRA_TypeDef *TMRAx);
|
||||
void TMRA_SetCompareValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint32_t u32Value);
|
||||
uint32_t TMRA_GetCompareValue(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch);
|
||||
|
||||
/* Sync start */
|
||||
void TMRA_SyncStartCmd(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState);
|
||||
|
||||
void TMRA_SetCompareBufCond(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond);
|
||||
void TMRA_CompareBufCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState);
|
||||
|
||||
en_flag_status_t TMRA_GetStatus(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag);
|
||||
void TMRA_ClearStatus(CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag);
|
||||
void TMRA_IntCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32IntType, en_functional_state_t enNewState);
|
||||
void TMRA_EventCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32EventType, en_functional_state_t enNewState);
|
||||
void TMRA_Start(CM_TMRA_TypeDef *TMRAx);
|
||||
void TMRA_Stop(CM_TMRA_TypeDef *TMRAx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_TMRA_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_TMRA_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,130 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_trng.h
|
||||
* @brief This file contains all the functions prototypes of the TRNG driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2023-06-30 CDT Add TRNG_Cmd,TRNG_DeInit functions
|
||||
API optimized for better random numbers: TRNG_GenerateRandom()
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_TRNG_H__
|
||||
#define __HC32_LL_TRNG_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_TRNG
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_TRNG_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @defgroup TRNG_Global_Macros TRNG Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TRNG_Reload_Init_Value TRNG Reload Initial Value
|
||||
* @{
|
||||
*/
|
||||
#define TRNG_RELOAD_INIT_VAL_ENABLE (TRNG_MR_LOAD) /* Enable reload new initial value. */
|
||||
#define TRNG_RELOAD_INIT_VAL_DISABLE (0x0U) /* Disable reload new initial value. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TRNG_Shift_Ctrl TRNG Shift Control
|
||||
* @{
|
||||
*/
|
||||
#define TRNG_SHIFT_CNT32 (0x3UL << TRNG_MR_CNT_POS) /* Shift 32 times when capturing random noise. */
|
||||
#define TRNG_SHIFT_CNT64 (0x4UL << TRNG_MR_CNT_POS) /* Shift 64 times when capturing random noise. */
|
||||
#define TRNG_SHIFT_CNT128 (0x5UL << TRNG_MR_CNT_POS) /* Shift 128 times when capturing random noise. */
|
||||
#define TRNG_SHIFT_CNT256 (0x6UL << TRNG_MR_CNT_POS) /* Shift 256 times when capturing random noise. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup TRNG_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
int32_t TRNG_DeInit(void);
|
||||
void TRNG_Init(uint32_t u32ShiftCount, uint32_t u32ReloadInitValueEn);
|
||||
int32_t TRNG_GenerateRandom(uint32_t *pu32Random, uint32_t u32RandomLen);
|
||||
|
||||
void TRNG_Start(void);
|
||||
void TRNG_Cmd(en_functional_state_t enNewState);
|
||||
int32_t TRNG_GetRandom(uint32_t *pu32Random, uint8_t u8RandomLen);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_TRNG_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_TRNG_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,422 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_usart.h
|
||||
* @brief This file contains all the functions prototypes of the USART(Universal
|
||||
* Synchronous/Asynchronous Receiver Transmitter) driver library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2023-06-30 CDT Modify typo
|
||||
Change macro-definition: USART_DR_MPID -> USART_TDR_MPID
|
||||
Modify USART_SetTransType parameter: u32Type -> u16Type
|
||||
Modify USART_SC_ETU_CLK128/256 value
|
||||
Modify return type of function USART_DeInit
|
||||
2023-09-30 CDT Remove u32StopBit param from stc_usart_smartcard_init_t structure
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_USART_H__
|
||||
#define __HC32_LL_USART_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_USART
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_USART_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup USART_Global_Types USART Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief clock synchronization mode initialization structure definition
|
||||
* @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32ClockSrc; /*!< Clock Source.
|
||||
This parameter can be a value of @ref USART_Clock_Source */
|
||||
uint32_t u32ClockDiv; /*!< Clock division.
|
||||
This parameter can be a value of @ref USART_Clock_Division. */
|
||||
uint32_t u32Baudrate; /*!< USART baudrate.
|
||||
This parameter is valid when clock source is the internal clock. */
|
||||
uint32_t u32FirstBit; /*!< Significant bit.
|
||||
This parameter can be a value of @ref USART_First_Bit */
|
||||
uint32_t u32HWFlowControl; /*!< Hardware flow control.
|
||||
This parameter can be a value of @ref USART_Hardware_Flow_Control */
|
||||
} stc_usart_clocksync_init_t;
|
||||
|
||||
/**
|
||||
* @brief UART multiple-processor initialization structure definition
|
||||
* @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32ClockSrc; /*!< Clock Source.
|
||||
This parameter can be a value of @ref USART_Clock_Source */
|
||||
uint32_t u32ClockDiv; /*!< Clock division.
|
||||
This parameter can be a value of @ref USART_Clock_Division. */
|
||||
uint32_t u32CKOutput; /*!< USART_CK output selection.
|
||||
This parameter can be a value of @ref USART_CK_Output_Selection. */
|
||||
uint32_t u32Baudrate; /*!< USART baudrate.
|
||||
This parameter is valid when clock source is the internal clock. */
|
||||
uint32_t u32DataWidth; /*!< Data width.
|
||||
This parameter can be a value of @ref USART_Data_Width_Bit */
|
||||
uint32_t u32StopBit; /*!< Stop Bits.
|
||||
This parameter can be a value of @ref USART_Stop_Bit */
|
||||
uint32_t u32OverSampleBit; /*!< Oversampling Bits.
|
||||
This parameter can be a value of @ref USART_Over_Sample_Bit */
|
||||
uint32_t u32FirstBit; /*!< Significant bit.
|
||||
This parameter can be a value of @ref USART_First_Bit */
|
||||
uint32_t u32StartBitPolarity; /*!< Start Bit Detect Polarity.
|
||||
This parameter can be a value of @ref USART_Start_Bit_Polarity */
|
||||
uint32_t u32HWFlowControl; /*!< Hardware flow control.
|
||||
This parameter can be a value of @ref USART_Hardware_Flow_Control */
|
||||
} stc_usart_multiprocessor_init_t;
|
||||
|
||||
/**
|
||||
* @brief UART mode initialization structure definition
|
||||
* @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32ClockSrc; /*!< Clock Source.
|
||||
This parameter can be a value of @ref USART_Clock_Source */
|
||||
uint32_t u32ClockDiv; /*!< Clock division.
|
||||
This parameter can be a value of @ref USART_Clock_Division. */
|
||||
uint32_t u32CKOutput; /*!< USART_CK output selection.
|
||||
This parameter can be a value of @ref USART_CK_Output_Selection. */
|
||||
uint32_t u32Baudrate; /*!< USART baudrate.
|
||||
This parameter is valid when clock source is the internal clock. */
|
||||
uint32_t u32DataWidth; /*!< Data width.
|
||||
This parameter can be a value of @ref USART_Data_Width_Bit */
|
||||
uint32_t u32StopBit; /*!< Stop Bits.
|
||||
This parameter can be a value of @ref USART_Stop_Bit */
|
||||
uint32_t u32Parity; /*!< Parity format.
|
||||
This parameter can be a value of @ref USART_Parity_Control */
|
||||
uint32_t u32OverSampleBit; /*!< Oversampling Bits.
|
||||
This parameter can be a value of @ref USART_Over_Sample_Bit */
|
||||
uint32_t u32FirstBit; /*!< Significant bit.
|
||||
This parameter can be a value of @ref USART_First_Bit */
|
||||
uint32_t u32StartBitPolarity; /*!< Start Bit Detect Polarity.
|
||||
This parameter can be a value of @ref USART_Start_Bit_Polarity */
|
||||
uint32_t u32HWFlowControl; /*!< Hardware flow control.
|
||||
This parameter can be a value of @ref USART_Hardware_Flow_Control */
|
||||
} stc_usart_uart_init_t;
|
||||
|
||||
/**
|
||||
* @brief Smartcard mode initialization structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32ClockDiv; /*!< Clock division. This parameter can be a value of @ref USART_Clock_Division.
|
||||
@note This parameter is valid when clock source is the internal clock. */
|
||||
uint32_t u32CKOutput; /*!< USART_CK output selection. This parameter can be a value of @ref USART_CK_Output_Selection.
|
||||
@note This parameter is valid when clock source is the internal clock. */
|
||||
uint32_t u32Baudrate; /*!< USART baudrate.
|
||||
This parameter is calculated according with smartcard default ETU and clock. */
|
||||
uint32_t u32FirstBit; /*!< Significant bit.
|
||||
This parameter can be a value of @ref USART_First_Bit */
|
||||
} stc_usart_smartcard_init_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup USART_Global_Macros USART Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup USART_Flag USART Flag
|
||||
* @{
|
||||
*/
|
||||
#define USART_FLAG_RX_FULL (USART_SR_RXNE) /*!< Receive data register not empty flag */
|
||||
#define USART_FLAG_OVERRUN (USART_SR_ORE) /*!< Overrun error flag */
|
||||
#define USART_FLAG_TX_CPLT (USART_SR_TC) /*!< Transmission complete flag */
|
||||
#define USART_FLAG_TX_EMPTY (USART_SR_TXE) /*!< Transmit data register empty flag */
|
||||
#define USART_FLAG_FRAME_ERR (USART_SR_FE) /*!< Framing error flag */
|
||||
#define USART_FLAG_PARITY_ERR (USART_SR_PE) /*!< Parity error flag */
|
||||
#define USART_FLAG_MX_PROCESSOR (USART_SR_MPB) /*!< Receive processor ID flag */
|
||||
#define USART_FLAG_RX_TIMEOUT (USART_SR_RTOF) /*!< Receive timeout flag */
|
||||
|
||||
#define USART_FLAG_ALL (USART_FLAG_RX_FULL | USART_FLAG_FRAME_ERR | USART_FLAG_TX_EMPTY | \
|
||||
USART_FLAG_OVERRUN | USART_FLAG_PARITY_ERR | USART_FLAG_RX_TIMEOUT | \
|
||||
USART_FLAG_TX_CPLT | USART_FLAG_MX_PROCESSOR )
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup USART_Transmission_Type USART Transmission Type
|
||||
* @{
|
||||
*/
|
||||
#define USART_TRANS_DATA (0UL)
|
||||
#define USART_TRANS_ID (USART_TDR_MPID)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup USART_Function USART Function
|
||||
* @{
|
||||
*/
|
||||
#define USART_TX (USART_CR1_TE) /*!< USART TX function */
|
||||
#define USART_RX (USART_CR1_RE) /*!< USART RX function */
|
||||
#define USART_INT_RX (USART_CR1_RIE) /*!< USART receive data register not empty && receive error interrupt */
|
||||
#define USART_INT_TX_CPLT (USART_CR1_TCIE) /*!< USART transmission complete interrupt */
|
||||
#define USART_INT_TX_EMPTY (USART_CR1_TXEIE) /*!< USART transmit data register empty interrupt */
|
||||
#define USART_RX_TIMEOUT (USART_CR1_RTOE) /*!< USART RX timeout function */
|
||||
#define USART_INT_RX_TIMEOUT (USART_CR1_RTOIE) /*!< USART RX timeout interrupt */
|
||||
|
||||
#define USART_FUNC_ALL (USART_TX | USART_RX | USART_INT_RX | USART_INT_TX_CPLT | USART_RX_TIMEOUT | \
|
||||
USART_INT_RX_TIMEOUT | USART_INT_TX_EMPTY)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup USART_Parity_Control USART Parity Control
|
||||
* @{
|
||||
*/
|
||||
#define USART_PARITY_NONE (0UL) /*!< Parity control disabled */
|
||||
#define USART_PARITY_EVEN (USART_CR1_PCE) /*!< Parity control enabled and Even Parity is selected */
|
||||
#define USART_PARITY_ODD (USART_CR1_PCE | \
|
||||
USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup USART_Data_Width_Bit USART Data Width Bit
|
||||
* @{
|
||||
*/
|
||||
#define USART_DATA_WIDTH_8BIT (0UL) /*!< 8 bits */
|
||||
#define USART_DATA_WIDTH_9BIT (USART_CR1_M) /*!< 9 bits */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup USART_Over_Sample_Bit USART Over Sample Bit
|
||||
* @{
|
||||
*/
|
||||
#define USART_OVER_SAMPLE_16BIT (0UL) /*!< Oversampling by 16 bits */
|
||||
#define USART_OVER_SAMPLE_8BIT (USART_CR1_OVER8) /*!< Oversampling by 8 bits */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup USART_First_Bit USART First Bit
|
||||
* @{
|
||||
*/
|
||||
#define USART_FIRST_BIT_LSB (0UL) /*!< LSB(Least Significant Bit) */
|
||||
#define USART_FIRST_BIT_MSB (USART_CR1_ML) /*!< MSB(Most Significant Bit) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup USART_Start_Bit_Polarity USART Start Bit Polarity
|
||||
* @{
|
||||
*/
|
||||
#define USART_START_BIT_LOW (0UL) /*!< Detect RX pin low level */
|
||||
#define USART_START_BIT_FALLING (USART_CR1_SBS) /*!< Detect RX pin falling edge */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup USART_Clock_Source USART Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define USART_CLK_SRC_INTERNCLK (0UL) /*!< Select internal clock source and don't output clock */
|
||||
#define USART_CLK_SRC_EXTCLK (USART_CR2_CLKC_1) /*!< Select external clock source. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup USART_CK_Output_Selection USART_CK Output Selection
|
||||
* @{
|
||||
*/
|
||||
#define USART_CK_OUTPUT_DISABLE (0UL) /*!< Disable USART_CK output */
|
||||
#define USART_CK_OUTPUT_ENABLE (USART_CR2_CLKC_0) /*!< Enable USART_CK output. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup USART_Stop_Bit USART Stop Bit
|
||||
* @{
|
||||
*/
|
||||
#define USART_STOPBIT_1BIT (0UL) /*!< 1 stop bit */
|
||||
#define USART_STOPBIT_2BIT (USART_CR2_STOP) /*!< 2 stop bit */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup USART_Hardware_Flow_Control USART Hardware Flow Control
|
||||
* @{
|
||||
*/
|
||||
#define USART_HW_FLOWCTRL_CTS (USART_CR3_CTSE) /*!< USART hardware flow control CTS mode */
|
||||
#define USART_HW_FLOWCTRL_RTS (USART_CR3_CTSE >> 1U) /*!< USART hardware flow control RTS mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup USART_Clock_Division USART Clock Division
|
||||
* @{
|
||||
*/
|
||||
#define USART_CLK_DIV1 (0UL) /*!< CLK */
|
||||
#define USART_CLK_DIV4 (1UL) /*!< CLK/4 */
|
||||
#define USART_CLK_DIV16 (2UL) /*!< CLK/16 */
|
||||
#define USART_CLK_DIV64 (3UL) /*!< CLK/64 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup USART_Max_Timeout USART Max Timeout
|
||||
* @{
|
||||
*/
|
||||
#define USART_MAX_TIMEOUT (0xFFFFFFFFUL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup USART_Smartcard_ETU_Clock USART Smartcard ETU Clock
|
||||
* @{
|
||||
*/
|
||||
#define USART_SC_ETU_CLK32 (0UL << USART_CR3_BCN_POS) /*!< 1 etu = 32/f */
|
||||
#define USART_SC_ETU_CLK64 (1UL << USART_CR3_BCN_POS) /*!< 1 etu = 64/f */
|
||||
#define USART_SC_ETU_CLK128 (3UL << USART_CR3_BCN_POS) /*!< 1 etu = 128/f */
|
||||
#define USART_SC_ETU_CLK256 (5UL << USART_CR3_BCN_POS) /*!< 1 etu = 256/f */
|
||||
#define USART_SC_ETU_CLK372 (6UL << USART_CR3_BCN_POS) /*!< 1 etu = 372/f */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup USART_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
int32_t USART_ClockSync_StructInit(stc_usart_clocksync_init_t *pstcClockSyncInit);
|
||||
int32_t USART_ClockSync_Init(CM_USART_TypeDef *USARTx,
|
||||
const stc_usart_clocksync_init_t *pstcClockSyncInit, float32_t *pf32Error);
|
||||
int32_t USART_MultiProcessor_StructInit(stc_usart_multiprocessor_init_t *pstcMultiProcessorInit);
|
||||
int32_t USART_MultiProcessor_Init(CM_USART_TypeDef *USARTx,
|
||||
const stc_usart_multiprocessor_init_t *pstcMultiProcessorInit, float32_t *pf32Error);
|
||||
int32_t USART_UART_StructInit(stc_usart_uart_init_t *pstcUartInit);
|
||||
int32_t USART_UART_Init(CM_USART_TypeDef *USARTx, const stc_usart_uart_init_t *pstcUartInit, float32_t *pf32Error);
|
||||
|
||||
int32_t USART_SmartCard_StructInit(stc_usart_smartcard_init_t *pstcSmartCardInit);
|
||||
int32_t USART_SmartCard_Init(CM_USART_TypeDef *USARTx,
|
||||
const stc_usart_smartcard_init_t *pstcSmartCardInit, float32_t *pf32Error);
|
||||
|
||||
int32_t USART_DeInit(CM_USART_TypeDef *USARTx);
|
||||
void USART_FuncCmd(CM_USART_TypeDef *USARTx, uint32_t u32Func, en_functional_state_t enNewState);
|
||||
en_flag_status_t USART_GetStatus(const CM_USART_TypeDef *USARTx, uint32_t u32Flag);
|
||||
void USART_ClearStatus(CM_USART_TypeDef *USARTx, uint32_t u32Flag);
|
||||
void USART_SetParity(CM_USART_TypeDef *USARTx, uint32_t u32Parity);
|
||||
void USART_SetFirstBit(CM_USART_TypeDef *USARTx, uint32_t u32FirstBit);
|
||||
void USART_SetStopBit(CM_USART_TypeDef *USARTx, uint32_t u32StopBit);
|
||||
void USART_SetDataWidth(CM_USART_TypeDef *USARTx, uint32_t u32DataWidth);
|
||||
void USART_SetOverSampleBit(CM_USART_TypeDef *USARTx, uint32_t u32OverSampleBit);
|
||||
void USART_SetStartBitPolarity(CM_USART_TypeDef *USARTx, uint32_t u32Polarity);
|
||||
void USART_SetTransType(CM_USART_TypeDef *USARTx, uint16_t u16Type);
|
||||
void USART_SetClockDiv(CM_USART_TypeDef *USARTx, uint32_t u32ClockDiv);
|
||||
uint32_t USART_GetClockDiv(const CM_USART_TypeDef *USARTx);
|
||||
void USART_SetClockSrc(CM_USART_TypeDef *USARTx, uint32_t u32ClockSrc);
|
||||
uint32_t USART_GetClockSrc(const CM_USART_TypeDef *USARTx);
|
||||
void USART_FilterCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState);
|
||||
void USART_SilenceCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState);
|
||||
void USART_SetHWFlowControl(CM_USART_TypeDef *USARTx, uint32_t u32HWFlowControl);
|
||||
uint16_t USART_ReadData(const CM_USART_TypeDef *USARTx);
|
||||
void USART_WriteData(CM_USART_TypeDef *USARTx, uint16_t u16Data);
|
||||
void USART_WriteID(CM_USART_TypeDef *USARTx, uint16_t u16ID);
|
||||
|
||||
int32_t USART_SetBaudrate(CM_USART_TypeDef *USARTx, uint32_t u32Baudrate, float32_t *pf32Error);
|
||||
|
||||
void USART_SmartCard_SetEtuClock(CM_USART_TypeDef *USARTx, uint32_t u32EtuClock);
|
||||
|
||||
int32_t USART_UART_Trans(CM_USART_TypeDef *USARTx, const void *pvBuf, uint32_t u32Len, uint32_t u32Timeout);
|
||||
int32_t USART_UART_Receive(const CM_USART_TypeDef *USARTx, void *pvBuf, uint32_t u32Len, uint32_t u32Timeout);
|
||||
int32_t USART_ClockSync_Trans(CM_USART_TypeDef *USARTx, const uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout);
|
||||
int32_t USART_ClockSync_Receive(CM_USART_TypeDef *USARTx, uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout);
|
||||
int32_t USART_ClockSync_TransReceive(CM_USART_TypeDef *USARTx, const uint8_t au8TxBuf[], uint8_t au8RxBuf[],
|
||||
uint32_t u32Len, uint32_t u32Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_USART_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_USART_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,687 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_usb.h
|
||||
* @brief A detailed description is available at hardware registers.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2022-06-30 CDT Add USB core ID select function
|
||||
Delete comment
|
||||
2023-06-30 CDT Modify typo
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_USB_H__
|
||||
#define __HC32_LL_USB_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_USB
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_USB_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
#define USB_MAX_TX_FIFOS (12U)
|
||||
#define USB_MAX_CH_NUM (USB_MAX_TX_FIFOS)
|
||||
#define USB_MAX_EP_NUM (6U)
|
||||
|
||||
/* USB Core ID define */
|
||||
#define USBFS_CORE_ID (0U)
|
||||
#define USBHS_CORE_ID (1U)
|
||||
|
||||
/* USB PHY type define for USBHS core */
|
||||
#define USBHS_PHY_EMBED (0U)
|
||||
#define USBHS_PHY_EXT (1U)
|
||||
|
||||
#define USB_MAX_EP0_SIZE (64U)
|
||||
/* working mode of the USB core */
|
||||
#define DEVICE_MODE (0U)
|
||||
#define HOST_MODE (1U)
|
||||
|
||||
/* Macro definations for device mode*/
|
||||
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << USBFS_DSTS_ENUMSPD_POS)
|
||||
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << USBFS_DSTS_ENUMSPD_POS)
|
||||
#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << USBFS_DSTS_ENUMSPD_POS)
|
||||
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << USBFS_DSTS_ENUMSPD_POS)
|
||||
|
||||
/* EP type */
|
||||
#define EP_TYPE_CTRL (0U)
|
||||
#define EP_TYPE_ISOC (1U)
|
||||
#define EP_TYPE_BULK (2U)
|
||||
#define EP_TYPE_INTR (3U)
|
||||
#define EP_TYPE_MSK (3U)
|
||||
|
||||
/* USB port speed */
|
||||
#define PRTSPD_FULL_SPEED (1U)
|
||||
#define PRTSPD_LOW_SPEED (2U)
|
||||
|
||||
/* PHY clock */
|
||||
#define HCFG_30_60_MHZ (0U)
|
||||
#define HCFG_48_MHZ (1U)
|
||||
#define HCFG_6_MHZ (2U)
|
||||
|
||||
#define USB_EP_TX_DIS (0x0000U)
|
||||
#define USB_EP_TX_STALL (0x0010U)
|
||||
#define USB_EP_TX_NAK (0x0020U)
|
||||
#define USB_EP_TX_VALID (0x0030U)
|
||||
|
||||
#define USB_EP_RX_DIS (0x0000U)
|
||||
#define USB_EP_RX_STALL (0x1000U)
|
||||
#define USB_EP_RX_NAK (0x2000U)
|
||||
#define USB_EP_RX_VALID (0x3000U)
|
||||
|
||||
#define USB_OK (0U)
|
||||
#define USB_ERROR (1U)
|
||||
|
||||
#define USB_FRAME_INTERVAL_80 (0UL << USBFS_DCFG_PFIVL_POS)
|
||||
#define USB_FRAME_INTERVAL_85 (1UL << USBFS_DCFG_PFIVL_POS)
|
||||
#define USB_FRAME_INTERVAL_90 (2UL << USBFS_DCFG_PFIVL_POS)
|
||||
#define USB_FRAME_INTERVAL_95 (3UL << USBFS_DCFG_PFIVL_POS)
|
||||
|
||||
#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \
|
||||
(uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))
|
||||
#define LOBYTE(x) ((uint8_t)((uint16_t)(x) & 0x00FFU))
|
||||
#define HIBYTE(x) ((uint8_t)(((uint16_t)(x) & 0xFF00U) >>8U))
|
||||
|
||||
#ifdef USB_INTERNAL_DMA_ENABLED
|
||||
#define __USB_ALIGN_END
|
||||
#if defined (__GNUC__) /* GNU Compiler */
|
||||
#define __USB_ALIGN_BEGIN __attribute__ ((aligned (4)))
|
||||
#elif defined (__CC_ARM) /* ARM Compiler */
|
||||
#define __USB_ALIGN_BEGIN __align(4)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __USB_ALIGN_BEGIN
|
||||
#elif defined (__TASKING__) /* TASKING Compiler */
|
||||
#define __USB_ALIGN_BEGIN __align(4)
|
||||
#endif
|
||||
#else
|
||||
#define __USB_ALIGN_BEGIN
|
||||
#define __USB_ALIGN_END
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
typedef struct {
|
||||
__IO uint32_t GVBUSCFG; /* VBUS Configuration Register 000h */
|
||||
uint32_t Reserved04; /* Reserved 004h */
|
||||
__IO uint32_t GAHBCFG; /* AHB Configuration Register 008h */
|
||||
__IO uint32_t GUSBCFG; /* USB Configuration Register 00Ch */
|
||||
__IO uint32_t GRSTCTL; /* Reset Register 010h */
|
||||
__IO uint32_t GINTSTS; /* Interrupt Register 014h */
|
||||
__IO uint32_t GINTMSK; /* Interrupt Mask Register 018h */
|
||||
__IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch */
|
||||
__IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h */
|
||||
__IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */
|
||||
__IO uint32_t HNPTXFSIZ; /* HNPTXFSIZ: Host Non-Periodic Transmit FIFO Size Register 028h
|
||||
DIEPTXF0: Device IN EP0 Transmit FIFO size register 028h */
|
||||
__IO uint32_t HNPTXSTS; /* Host Non Periodic Transmit FIFO/Queue Status Register 02Ch */
|
||||
uint32_t Reserved30[3]; /* Reserved 030h-038h */
|
||||
__IO uint32_t CID; /* User ID Register 03Ch */
|
||||
uint32_t Reserved40[5]; /* Reserved 040h-050h */
|
||||
__IO uint32_t GLPMCFG; /* Low Power Mode Configuration Register 054h */
|
||||
uint32_t Reserved58[42]; /* Reserved 058h-0FCh */
|
||||
__IO uint32_t HPTXFSIZ; /* Host Periodic Transmit FIFO Size Register 100h */
|
||||
__IO uint32_t DIEPTXF[USB_MAX_TX_FIFOS]; /* Device Periodic Transmit FIFO Size Register */
|
||||
} USB_CORE_GREGS;
|
||||
|
||||
typedef struct {
|
||||
__IO uint32_t DCFG; /* Device Configuration Register 800h */
|
||||
__IO uint32_t DCTL; /* Device Control Register 804h */
|
||||
__IO uint32_t DSTS; /* Device Status Register (RO) 808h */
|
||||
uint32_t Reserved0C; /* Reserved 80Ch */
|
||||
__IO uint32_t DIEPMSK; /* Device IN EP Common Interrupt Mask Register 810h */
|
||||
__IO uint32_t DOEPMSK; /* Device OUT EP Common Interrupt Mask Register 814h */
|
||||
__IO uint32_t DAINT; /* Device All EP Interrupt Register 818h */
|
||||
__IO uint32_t DAINTMSK; /* Device All EP Interrupt Mask Register 81Ch */
|
||||
uint32_t Reserved20[4]; /* Reserved 820h-82Ch */
|
||||
__IO uint32_t DTHRCTL; /* Device Threshold Control Register 830h */
|
||||
__IO uint32_t DIEPEMPMSK; /* Device IN EP FIFO Empty Interrupt Mask Register 834h */
|
||||
__IO uint32_t DEACHINT; /* Device Each EP Interrupt Register 838h */
|
||||
__IO uint32_t DEACHINTMSK; /* Device Each EP Interrupt Mask Register 83Ch */
|
||||
uint32_t Reserved40; /* Reserved 840h */
|
||||
__IO uint32_t DIEPEACHMSK1; /* Device IN EP1 Interrupt Mask Register 844h */
|
||||
uint32_t Reserved48[15]; /* Reserved 848-880h */
|
||||
__IO uint32_t DOEPEACHMSK1; /* Device OUT EP1 Interrupt Mask Register 884h */
|
||||
} USB_CORE_DREGS;
|
||||
|
||||
typedef struct {
|
||||
__IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
|
||||
uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
|
||||
__IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
|
||||
uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
|
||||
__IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
|
||||
__IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
|
||||
__IO uint32_t DTXFSTS; /* IN Endpoint Tx FIFO Status 900h + (ep_num * 20h) + 18h */
|
||||
uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
|
||||
} USB_CORE_INEPREGS;
|
||||
|
||||
typedef struct {
|
||||
__IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
|
||||
uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h */
|
||||
__IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
|
||||
uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch */
|
||||
__IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
|
||||
__IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
|
||||
uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
|
||||
} USB_CORE_OUTEPREGS;
|
||||
|
||||
typedef struct {
|
||||
__IO uint32_t HCFG; /* Host Configuration Register 400h*/
|
||||
__IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
|
||||
__IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
|
||||
uint32_t Reserved40C; /* Reserved 40Ch*/
|
||||
__IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
|
||||
__IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
|
||||
__IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
|
||||
} USB_CORE_HREGS;
|
||||
|
||||
typedef struct {
|
||||
__IO uint32_t HCCHAR;
|
||||
__IO uint32_t HCSPLT;
|
||||
__IO uint32_t HCINT;
|
||||
__IO uint32_t HCINTMSK;
|
||||
__IO uint32_t HCTSIZ;
|
||||
__IO uint32_t HCDMA;
|
||||
uint32_t Reserved[2];
|
||||
} USB_CORE_HC_REGS;
|
||||
|
||||
typedef struct { /* 000h */
|
||||
USB_CORE_GREGS *GREGS;
|
||||
USB_CORE_DREGS *DREGS;
|
||||
USB_CORE_HREGS *HREGS;
|
||||
USB_CORE_INEPREGS *INEP_REGS[USB_MAX_TX_FIFOS];
|
||||
USB_CORE_OUTEPREGS *OUTEP_REGS[USB_MAX_TX_FIFOS];
|
||||
USB_CORE_HC_REGS *HC_REGS[USB_MAX_TX_FIFOS];
|
||||
__IO uint32_t *HPRT;
|
||||
__IO uint32_t *DFIFO[USB_MAX_TX_FIFOS];
|
||||
__IO uint32_t *GCCTL;
|
||||
} LL_USB_TypeDef;
|
||||
|
||||
typedef struct {
|
||||
uint8_t host_chnum;
|
||||
uint8_t dev_epnum;
|
||||
uint8_t dmaen;
|
||||
uint8_t low_power;
|
||||
uint8_t phy_type;
|
||||
uint8_t core_type;
|
||||
} USB_CORE_BASIC_CFGS;
|
||||
|
||||
typedef struct {
|
||||
uint8_t dev_addr;
|
||||
uint8_t ep_idx;
|
||||
uint8_t is_epin;
|
||||
uint8_t ch_speed;
|
||||
uint8_t do_ping;
|
||||
uint8_t ep_type;
|
||||
uint16_t max_packet;
|
||||
uint8_t pid_type;
|
||||
uint8_t in_toggle;
|
||||
uint8_t out_toggle;
|
||||
/* transaction level variables*/
|
||||
uint32_t dma_addr;
|
||||
uint32_t xfer_len;
|
||||
uint32_t xfer_count;
|
||||
uint8_t *xfer_buff;
|
||||
} USB_HOST_CH;
|
||||
|
||||
typedef struct {
|
||||
uint8_t epidx;
|
||||
uint8_t ep_dir;
|
||||
uint8_t trans_type;
|
||||
uint8_t ep_stall;
|
||||
uint8_t data_pid_start;
|
||||
uint8_t datax_pid;
|
||||
uint16_t tx_fifo_num;
|
||||
uint32_t maxpacket;
|
||||
/* Transfer level variables */
|
||||
uint32_t rem_data_len;
|
||||
uint32_t total_data_len;
|
||||
uint32_t ctl_data_len;
|
||||
/* transaction level variables*/
|
||||
uint32_t dma_addr;
|
||||
uint32_t xfer_len;
|
||||
uint32_t xfer_count;
|
||||
uint8_t *xfer_buff;
|
||||
} USB_DEV_EP;
|
||||
|
||||
typedef struct {
|
||||
uint8_t u8CoreID; /* USBFS_CORE_ID or USBHS_CORE_ID */
|
||||
} stc_usb_port_identify;
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @addtogroup USB_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief get the current mode of the usb core from the corresponding register
|
||||
* @param [in] USBx usb instance
|
||||
* @retval current mode 1: host mode 0: device mode
|
||||
*/
|
||||
__STATIC_INLINE uint8_t usb_getcurmod(LL_USB_TypeDef *USBx)
|
||||
{
|
||||
if (0UL != READ_REG32_BIT(USBx->GREGS->GINTSTS, USBFS_GINTSTS_CMOD)) {
|
||||
return 1U;
|
||||
} else {
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the normal interrupts
|
||||
* @param [in] USBx usb instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void usb_normalinten(LL_USB_TypeDef *USBx)
|
||||
{
|
||||
WRITE_REG32(USBx->GREGS->GINTSTS, 0xBFFFFFFFUL);
|
||||
WRITE_REG32(USBx->GREGS->GINTMSK, USBFS_GINTMSK_WKUIM | USBFS_GINTMSK_USBSUSPM);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear all the pending device interrupt bits and mask the IN and OUT
|
||||
* endpoint interrupts.
|
||||
* @param [in] USBx usb instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void usb_clrandmskepint(LL_USB_TypeDef *USBx)
|
||||
{
|
||||
WRITE_REG32(USBx->DREGS->DIEPMSK, 0UL);
|
||||
WRITE_REG32(USBx->DREGS->DOEPMSK, 0UL);
|
||||
WRITE_REG32(USBx->DREGS->DAINT, 0xFFFFFFFFUL);
|
||||
WRITE_REG32(USBx->DREGS->DAINTMSK, 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief generate a device connect signal to the USB host
|
||||
* @param [in] USBx usb instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void usb_coreconn(LL_USB_TypeDef *USBx)
|
||||
{
|
||||
CLR_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_SDIS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief test of mode processing
|
||||
* @param [in] USBx usb instance
|
||||
* @param [in] reg Register write
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void usb_runtestmode(LL_USB_TypeDef *USBx, uint32_t reg)
|
||||
{
|
||||
WRITE_REG32(USBx->DREGS->DCTL, reg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the controller's Global interrupts in the AHB Configuration
|
||||
* registers.
|
||||
* @param [in] USBx usb instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void usb_ginten(LL_USB_TypeDef *USBx)
|
||||
{
|
||||
SET_REG32_BIT(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_GINTMSK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the controller's Global interrupt in the AHB Configuration
|
||||
* register.
|
||||
* @param [in] USBx usb instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void usb_gintdis(LL_USB_TypeDef *USBx)
|
||||
{
|
||||
CLR_REG32_BIT(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_GINTMSK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the Core Interrupt bits from the interrupt register not including
|
||||
* the bits that are masked.
|
||||
* @param [in] USBx usb instance
|
||||
* @retval status[32bits]
|
||||
*/
|
||||
__STATIC_INLINE uint32_t usb_getcoreintr(LL_USB_TypeDef *USBx)
|
||||
{
|
||||
uint32_t v;
|
||||
v = READ_REG32(USBx->GREGS->GINTSTS);
|
||||
v &= READ_REG32(USBx->GREGS->GINTMSK);
|
||||
return v;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the out endpoint interrupt bits from the all endpoint interrupt
|
||||
* register not including the bits masked.
|
||||
* @param [in] USBx usb instance
|
||||
* @retval The status that shows which OUT EP have interrupted.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t usb_getalloepintr(LL_USB_TypeDef *USBx)
|
||||
{
|
||||
uint32_t v;
|
||||
v = READ_REG32(USBx->DREGS->DAINT);
|
||||
v &= READ_REG32(USBx->DREGS->DAINTMSK);
|
||||
return ((v & 0xFFFF0000UL) >> 16U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the Device OUT EP Interrupt register(DOEPINT) not including the
|
||||
* interrupt bits that are masked.
|
||||
* @param [in] USBx usb instance
|
||||
* @param [in] epnum end point index
|
||||
* @retval all the interrupt bits on DOEPINTn while n = epnum
|
||||
*/
|
||||
__STATIC_INLINE uint32_t usb_getoepintbit(LL_USB_TypeDef *USBx, uint8_t epnum)
|
||||
{
|
||||
uint32_t v;
|
||||
v = READ_REG32(USBx->OUTEP_REGS[epnum]->DOEPINT);
|
||||
v &= READ_REG32(USBx->DREGS->DOEPMSK);
|
||||
return v;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the IN endpoint interrupt bits from the all endpoint interrupt
|
||||
* register not including the bits masked.
|
||||
* @param [in] USBx usb instance
|
||||
* @retval The status that shows which IN EP have interrupted.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t usb_getalliepintr(LL_USB_TypeDef *USBx)
|
||||
{
|
||||
uint32_t v;
|
||||
v = READ_REG32(USBx->DREGS->DAINT);
|
||||
v &= READ_REG32(USBx->DREGS->DAINTMSK);
|
||||
return (v & 0xFFFFUL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the device a new address.
|
||||
* @param [in] USBx usb instance
|
||||
* @param [in] address device address which will be set to the corresponding register.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void usb_devaddrset(LL_USB_TypeDef *USBx, uint8_t address)
|
||||
{
|
||||
MODIFY_REG32(USBx->DREGS->DCFG, USBFS_DCFG_DAD, (uint32_t)address << USBFS_DCFG_DAD_POS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the USB PHY.
|
||||
* @param [in] USBx usb instance
|
||||
* @param [in] PhyType USB phy, 1 select external ULPI PHY, 0 select internal FS PHY
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void usb_PhySelect(LL_USB_TypeDef *USBx, uint8_t PhyType)
|
||||
{
|
||||
if (USBHS_PHY_EXT == PhyType) {
|
||||
CLR_REG32_BIT(USBx->GREGS->GUSBCFG, USBFS_GUSBCFG_PHYSEL);
|
||||
//SET_REG32_BIT(USBx->GREGS->GUSBCFG, 1UL<<4);
|
||||
} else {
|
||||
SET_REG32_BIT(USBx->GREGS->GUSBCFG, USBFS_GUSBCFG_PHYSEL);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the USB device PHY.
|
||||
* @param [in] USBx usb instance
|
||||
* @param [in] PhyType USB phy, 1 select external ULPI PHY, 0 select internal FS PHY
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void usb_DevPhySelect(LL_USB_TypeDef *USBx, uint8_t PhyType)
|
||||
{
|
||||
if (1U == PhyType) {
|
||||
CLR_REG32_BIT(USBx->DREGS->DCFG, USBFS_DCFG_DSPD);
|
||||
} else {
|
||||
SET_REG32_BIT(USBx->DREGS->DCFG, USBFS_DCFG_DSPD);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB DMA function command.
|
||||
* @param [in] USBx usb instance
|
||||
* @param [in] DmaCmd USB DMA command status, 0 disable, 1 enable
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void usb_DmaCmd(LL_USB_TypeDef *USBx, uint8_t DmaCmd)
|
||||
{
|
||||
MODIFY_REG32(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_DMAEN, (uint32_t)DmaCmd << USBFS_GAHBCFG_DMAEN_POS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB burst length config.
|
||||
* @param [in] USBx usb instance
|
||||
* @param [in] len Burst length
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void usb_BurstLenConfig(LL_USB_TypeDef *USBx, uint8_t len)
|
||||
{
|
||||
MODIFY_REG32(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_HBSTLEN, (uint32_t)len << USBFS_GAHBCFG_HBSTLEN_POS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB frame interval config
|
||||
* @param [in] USBx usb instance
|
||||
* @param [in] interval Frame interval
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void usb_FrameIntervalConfig(LL_USB_TypeDef *USBx, uint8_t interval)
|
||||
{
|
||||
MODIFY_REG32(USBx->DREGS->DCFG, USBFS_DCFG_PFIVL, interval);
|
||||
}
|
||||
|
||||
#ifdef USE_HOST_MODE
|
||||
/**
|
||||
* @brief Read the register HPRT and reset the following bits.
|
||||
* @param [in] USBx usb instance
|
||||
* @retval value of HPRT
|
||||
*/
|
||||
//#define USBFS_HPRT_PRTOVRCURRCHNG (0x00000020UL)
|
||||
__STATIC_INLINE uint32_t usb_rdhprt(LL_USB_TypeDef *USBx)
|
||||
{
|
||||
return (READ_REG32(*USBx->HPRT) & ~(USBFS_HPRT_PENA | USBFS_HPRT_PCDET | USBFS_HPRT_PENCHNG));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Issues a ping token
|
||||
* @param [in] USBx usb instance
|
||||
* @param [in] hc_num the host channel index
|
||||
* @retval None
|
||||
*/
|
||||
//#define USBFS_HCTSIZ_DOPNG (0x80000000UL)
|
||||
__STATIC_INLINE void usb_pingtokenissue(LL_USB_TypeDef *USBx, uint8_t hc_num)
|
||||
{
|
||||
WRITE_REG32(USBx->HC_REGS[hc_num]->HCTSIZ, 1UL << USBFS_HCTSIZ_PKTCNT_POS);
|
||||
MODIFY_REG32(USBx->HC_REGS[hc_num]->HCCHAR, USBFS_HCCHAR_CHENA | USBFS_HCCHAR_CHDIS, USBFS_HCCHAR_CHENA);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function returns the frame number for sof packet
|
||||
* @param [in] USBx usb instance
|
||||
* @retval Frame number
|
||||
*/
|
||||
__STATIC_INLINE uint32_t usb_ifevenframe(LL_USB_TypeDef *USBx)
|
||||
{
|
||||
return ((READ_REG32(USBx->HREGS->HFNUM) + 1UL) & 0x1UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the FSLSPClkSel field of the HCFG register on the PHY type
|
||||
* @param [in] USBx usb instance
|
||||
* @param [in] freq clock frequency
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void usb_fslspclkselset(LL_USB_TypeDef *USBx, uint8_t freq)
|
||||
{
|
||||
MODIFY_REG32(USBx->HREGS->HCFG, USBFS_HCFG_FSLSPCS, (uint32_t)freq << USBFS_HCFG_FSLSPCS_POS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief suspend the port
|
||||
* @param [in] USBx usb instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void usb_prtsusp(LL_USB_TypeDef *USBx)
|
||||
{
|
||||
uint32_t u32hprt;
|
||||
u32hprt = usb_rdhprt(USBx);
|
||||
u32hprt |= USBFS_HPRT_PSUSP;
|
||||
u32hprt &= ~USBFS_HPRT_PRES;
|
||||
WRITE_REG32(*USBx->HPRT, u32hprt);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief control the enumeration speed of the core, this function make sure that
|
||||
* the maximum speed supperted by the connected device.
|
||||
* @param [in] USBx usb instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void usb_enumspeed(LL_USB_TypeDef *USBx)
|
||||
{
|
||||
CLR_REG32_BIT(USBx->HREGS->HCFG, USBFS_HCFG_FSLSS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set the TXFIFO and depth for non-periodic and periodic and RXFIFO size
|
||||
* @param [in] USBx usb instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void usb_sethostfifo(LL_USB_TypeDef *USBx, uint8_t u8CoreID)
|
||||
{
|
||||
if (USBFS_CORE_ID == u8CoreID) {
|
||||
#ifdef USB_FS_MODE
|
||||
/* USBFS Core*/
|
||||
WRITE_REG32(USBx->GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); /* set the RxFIFO Depth */
|
||||
/* non-periodic transmit RAM start address, set the non-periodic TxFIFO depth */
|
||||
WRITE_REG32(USBx->GREGS->HNPTXFSIZ,
|
||||
(RX_FIFO_FS_SIZE << USBFS_HNPTXFSIZ_NPTXFSA_POS)
|
||||
| (TXH_NP_FS_FIFOSIZ << USBFS_HNPTXFSIZ_NPTXFD_POS));
|
||||
/* set the host periodic TxFIFO start address, set the host periodic TxFIFO depth */
|
||||
WRITE_REG32(USBx->GREGS->HPTXFSIZ,
|
||||
((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ) << USBFS_HPTXFSIZ_PTXSA_POS)
|
||||
| (TXH_P_FS_FIFOSIZ << USBFS_HPTXFSIZ_PTXFD_POS));
|
||||
#endif
|
||||
} else {
|
||||
#ifdef USB_HS_MODE
|
||||
/* USBHS Core */
|
||||
WRITE_REG32(USBx->GREGS->GRXFSIZ, RX_FIFO_HS_SIZE);
|
||||
WRITE_REG32(USBx->GREGS->HNPTXFSIZ,
|
||||
(RX_FIFO_HS_SIZE << USBFS_HNPTXFSIZ_NPTXFSA_POS)
|
||||
| (TXH_NP_HS_FIFOSIZ << USBFS_HNPTXFSIZ_NPTXFD_POS));
|
||||
WRITE_REG32(USBx->GREGS->HPTXFSIZ,
|
||||
((RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ) << USBFS_HPTXFSIZ_PTXSA_POS)
|
||||
| (TXH_P_HS_FIFOSIZ << USBFS_HPTXFSIZ_PTXFD_POS));
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief reset the channel whose channel number is ch_idx
|
||||
* @param [in] USBx usb instance
|
||||
* @param [in] ch_idx channel number
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void usb_chrst(LL_USB_TypeDef *USBx, uint8_t ch_idx)
|
||||
{
|
||||
MODIFY_REG32(USBx->HC_REGS[ch_idx]->HCCHAR,
|
||||
USBFS_HCCHAR_CHENA | USBFS_HCCHAR_CHDIS | USBFS_HCCHAR_EPDIR,
|
||||
USBFS_HCCHAR_CHDIS);
|
||||
}
|
||||
#endif /* end of USE_HOST_MODE */
|
||||
|
||||
extern void usb_initusbcore(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs);
|
||||
extern void usb_setregaddr(LL_USB_TypeDef *USBx, stc_usb_port_identify *pstcPortIdentify, USB_CORE_BASIC_CFGS *basic_cfgs);
|
||||
extern void usb_rdpkt(LL_USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
|
||||
extern void usb_wrpkt(LL_USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t u8DmaEn);
|
||||
extern void usb_txfifoflush(LL_USB_TypeDef *USBx, uint32_t num);
|
||||
extern void usb_rxfifoflush(LL_USB_TypeDef *USBx);
|
||||
extern void usb_modeset(LL_USB_TypeDef *USBx, uint8_t mode);
|
||||
extern void usb_coresoftrst(LL_USB_TypeDef *USBx);
|
||||
|
||||
#ifdef USE_HOST_MODE
|
||||
extern void usb_hostmodeinit(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs);
|
||||
extern void usb_hostinten(LL_USB_TypeDef *USBx, uint8_t u8DmaEn);
|
||||
extern uint8_t usb_inithch(LL_USB_TypeDef *USBx, uint8_t hc_num, USB_HOST_CH *pCh, uint8_t u8DmaEn);
|
||||
extern void usb_hoststop(LL_USB_TypeDef *USBx, uint8_t u8ChNum);
|
||||
extern void usb_hchstop(LL_USB_TypeDef *USBx, uint8_t hc_num);
|
||||
extern uint8_t usb_hchtransbegin(LL_USB_TypeDef *USBx, uint8_t hc_num, USB_HOST_CH *pCh, uint8_t u8DmaEn);
|
||||
extern void usb_hprtrst(LL_USB_TypeDef *USBx);
|
||||
extern void usb_vbusctrl(LL_USB_TypeDef *USBx, uint8_t u8State);
|
||||
#endif
|
||||
|
||||
#ifdef USE_DEVICE_MODE
|
||||
extern void usb_devmodeinit(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs);
|
||||
extern void usb_devinten(LL_USB_TypeDef *USBx, uint8_t u8DmaEn);
|
||||
extern void usb_ep0activate(LL_USB_TypeDef *USBx);
|
||||
extern void usb_epactive(LL_USB_TypeDef *USBx, USB_DEV_EP *ep);
|
||||
extern void usb_epdeactive(LL_USB_TypeDef *USBx, USB_DEV_EP *ep);
|
||||
extern void usb_epntransbegin(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint8_t u8DmaEn);
|
||||
extern void usb_ep0transbegin(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint8_t u8DmaEn);
|
||||
extern void usb_setepstall(LL_USB_TypeDef *USBx, USB_DEV_EP *ep);
|
||||
extern void usb_clearepstall(LL_USB_TypeDef *USBx, USB_DEV_EP *ep);
|
||||
extern void usb_ep0revcfg(LL_USB_TypeDef *USBx, uint8_t u8DmaEn, uint8_t *u8RevBuf);
|
||||
extern void usb_remotewakeupen(LL_USB_TypeDef *USBx);
|
||||
extern void usb_epstatusset(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint32_t Status);
|
||||
extern uint32_t usb_epstatusget(LL_USB_TypeDef *USBx, USB_DEV_EP *ep);
|
||||
extern void usb_devepdis(LL_USB_TypeDef *USBx, uint8_t u8EpNum);
|
||||
extern void usb_ctrldevconnect(LL_USB_TypeDef *USBx, uint8_t link);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_USB_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_USB_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,131 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_utility.h
|
||||
* @brief This file contains all the functions prototypes of the DDL utility.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_UTILITY_H__
|
||||
#define __HC32_LL_UTILITY_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_UTILITY
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_UTILITY_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup UTILITY_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Imprecise delay */
|
||||
void DDL_DelayMS(uint32_t u32Count);
|
||||
void DDL_DelayUS(uint32_t u32Count);
|
||||
|
||||
/* Systick functions */
|
||||
int32_t SysTick_Init(uint32_t u32Freq);
|
||||
void SysTick_Delay(uint32_t u32Delay);
|
||||
void SysTick_IncTick(void);
|
||||
uint32_t SysTick_GetTick(void);
|
||||
void SysTick_Suspend(void);
|
||||
void SysTick_Resume(void);
|
||||
|
||||
#if (LL_PRINT_ENABLE == DDL_ON)
|
||||
int32_t LL_PrintfInit(void *vpDevice, uint32_t u32Param, int32_t (*pfnPreinit)(void *vpDevice, uint32_t u32Param));
|
||||
#endif
|
||||
|
||||
/* You can add your own assert functions by implement the function DDL_AssertHandler
|
||||
definition follow the function DDL_AssertHandler declaration */
|
||||
#ifdef __DEBUG
|
||||
#define DDL_ASSERT(x) \
|
||||
do { \
|
||||
((x) ? (void)0 : DDL_AssertHandler(__FILE__, __LINE__)); \
|
||||
} while (0)
|
||||
/* Exported function */
|
||||
void DDL_AssertHandler(const char *file, int line);
|
||||
#else
|
||||
#define DDL_ASSERT(x) ((void)0U)
|
||||
#endif /* __DEBUG */
|
||||
|
||||
#if (LL_PRINT_ENABLE == DDL_ON)
|
||||
#include <stdio.h>
|
||||
__WEAKDEF int32_t DDL_ConsoleOutputChar(char cData);
|
||||
|
||||
#define DDL_PrintfInit (void)LL_PrintfInit
|
||||
#define DDL_Printf (void)printf
|
||||
#else
|
||||
#define DDL_PrintfInit(vpDevice, u32Param, pfnPreinit)
|
||||
#define DDL_Printf(...)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_UTILITY_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_UTILITY_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,227 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ll_wdt.h
|
||||
* @brief This file contains all the functions prototypes of the WDT driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_LL_WDT_H__
|
||||
#define __HC32_LL_WDT_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_WDT
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_WDT_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup WDT_Global_Types WDT Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief WDT Init structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t u32CountPeriod; /*!< Specifies the counting period of WDT.
|
||||
This parameter can be a value of @ref WDT_Count_Period */
|
||||
uint32_t u32ClockDiv; /*!< Specifies the clock division factor of WDT.
|
||||
This parameter can be a value of @ref WDT_Clock_Division */
|
||||
uint32_t u32RefreshRange; /*!< Specifies the allow refresh range of WDT.
|
||||
This parameter can be a value of @ref WDT_Refresh_Range */
|
||||
uint32_t u32LPMCount; /*!< Specifies the count state in Low Power Mode (Sleep Mode).
|
||||
This parameter can be a value of @ref WDT_LPM_Count */
|
||||
uint32_t u32ExceptionType; /*!< Specifies the type of exception response for WDT.
|
||||
This parameter can be a value of @ref WDT_Exception_Type */
|
||||
} stc_wdt_init_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup WDT_Global_Macros WDT Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup WDT_Count_Period WDT Count Period
|
||||
* @{
|
||||
*/
|
||||
#define WDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */
|
||||
#define WDT_CNT_PERIOD4096 (WDT_CR_PERI_0) /*!< 4096 clock cycle */
|
||||
#define WDT_CNT_PERIOD16384 (WDT_CR_PERI_1) /*!< 16384 clock cycle */
|
||||
#define WDT_CNT_PERIOD65536 (WDT_CR_PERI) /*!< 65536 clock cycle */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup WDT_Clock_Division WDT Clock Division
|
||||
* @{
|
||||
*/
|
||||
#define WDT_CLK_DIV4 (0x02UL << WDT_CR_CKS_POS) /*!< PLCKx/4 */
|
||||
#define WDT_CLK_DIV64 (0x06UL << WDT_CR_CKS_POS) /*!< PLCKx/64 */
|
||||
#define WDT_CLK_DIV128 (0x07UL << WDT_CR_CKS_POS) /*!< PLCKx/128 */
|
||||
#define WDT_CLK_DIV256 (0x08UL << WDT_CR_CKS_POS) /*!< PLCKx/256 */
|
||||
#define WDT_CLK_DIV512 (0x09UL << WDT_CR_CKS_POS) /*!< PLCKx/512 */
|
||||
#define WDT_CLK_DIV1024 (0x0AUL << WDT_CR_CKS_POS) /*!< PLCKx/1024 */
|
||||
#define WDT_CLK_DIV2048 (0x0BUL << WDT_CR_CKS_POS) /*!< PLCKx/2048 */
|
||||
#define WDT_CLK_DIV8192 (0x0DUL << WDT_CR_CKS_POS) /*!< PLCKx/8192 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup WDT_Refresh_Range WDT Refresh Range
|
||||
* @{
|
||||
*/
|
||||
#define WDT_RANGE_0TO25PCT (0x01UL << WDT_CR_WDPT_POS) /*!< 0%~25% */
|
||||
#define WDT_RANGE_25TO50PCT (0x02UL << WDT_CR_WDPT_POS) /*!< 25%~50% */
|
||||
#define WDT_RANGE_0TO50PCT (0x03UL << WDT_CR_WDPT_POS) /*!< 0%~50% */
|
||||
#define WDT_RANGE_50TO75PCT (0x04UL << WDT_CR_WDPT_POS) /*!< 50%~75% */
|
||||
#define WDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << WDT_CR_WDPT_POS) /*!< 0%~25% & 50%~75% */
|
||||
#define WDT_RANGE_25TO75PCT (0x06UL << WDT_CR_WDPT_POS) /*!< 25%~75% */
|
||||
#define WDT_RANGE_0TO75PCT (0x07UL << WDT_CR_WDPT_POS) /*!< 0%~75% */
|
||||
#define WDT_RANGE_75TO100PCT (0x08UL << WDT_CR_WDPT_POS) /*!< 75%~100% */
|
||||
#define WDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << WDT_CR_WDPT_POS) /*!< 0%~25% & 75%~100% */
|
||||
#define WDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << WDT_CR_WDPT_POS) /*!< 25%~50% & 75%~100% */
|
||||
#define WDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << WDT_CR_WDPT_POS) /*!< 0%~50% & 75%~100% */
|
||||
#define WDT_RANGE_50TO100PCT (0x0CUL << WDT_CR_WDPT_POS) /*!< 50%~100% */
|
||||
#define WDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << WDT_CR_WDPT_POS) /*!< 0%~25% & 50%~100% */
|
||||
#define WDT_RANGE_25TO100PCT (0x0EUL << WDT_CR_WDPT_POS) /*!< 25%~100% */
|
||||
#define WDT_RANGE_0TO100PCT (0x0FUL << WDT_CR_WDPT_POS) /*!< 0%~100% */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup WDT_LPM_Count WDT Low Power Mode Count
|
||||
* @brief Counting control of WDT in sleep mode.
|
||||
* @{
|
||||
*/
|
||||
#define WDT_LPM_CNT_CONTINUE (0UL) /*!< Continue counting in sleep mode */
|
||||
#define WDT_LPM_CNT_STOP (WDT_CR_SLPOFF) /*!< Stop counting in sleep mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup WDT_Exception_Type WDT Exception Type
|
||||
* @brief Specifies the exception response when a refresh error or count overflow occurs.
|
||||
* @{
|
||||
*/
|
||||
#define WDT_EXP_TYPE_INT (0UL) /*!< WDT trigger interrupt */
|
||||
#define WDT_EXP_TYPE_RST (WDT_CR_ITS) /*!< WDT trigger reset */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup WDT_Flag WDT Flag
|
||||
* @{
|
||||
*/
|
||||
#define WDT_FLAG_UDF (WDT_SR_UDF) /*!< Count underflow flag */
|
||||
#define WDT_FLAG_REFRESH (WDT_SR_REF) /*!< Refresh error flag */
|
||||
#define WDT_FLAG_ALL (WDT_SR_UDF | WDT_SR_REF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup WDT_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get WDT count value.
|
||||
* @param None
|
||||
* @retval uint16_t Count value
|
||||
*/
|
||||
__STATIC_INLINE uint16_t WDT_GetCountValue(void)
|
||||
{
|
||||
return (uint16_t)(READ_REG32(CM_WDT->SR) & WDT_SR_CNT);
|
||||
}
|
||||
|
||||
/* Initialization and configuration functions */
|
||||
int32_t WDT_Init(const stc_wdt_init_t *pstcWdtInit);
|
||||
void WDT_FeedDog(void);
|
||||
uint16_t WDT_GetCountValue(void);
|
||||
|
||||
/* Flags management functions */
|
||||
en_flag_status_t WDT_GetStatus(uint32_t u32Flag);
|
||||
int32_t WDT_ClearStatus(uint32_t u32Flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_WDT_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_LL_WDT_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,351 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32f460_ll_interrupts_share.h
|
||||
* @brief This file contains all the functions prototypes of the interrupt driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
2022-10-31 CDT Rename I2Cx_Error_IrqHandler as I2Cx_EE_IrqHandler
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32F460_LL_INTERRUPTS_SHARE_H__
|
||||
#define __HC32F460_LL_INTERRUPTS_SHARE_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_ll_def.h"
|
||||
|
||||
#include "hc32f4xx.h"
|
||||
#include "hc32f4xx_conf.h"
|
||||
|
||||
/**
|
||||
* @addtogroup LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LL_HC32F460_SHARE_INTERRUPTS
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (LL_INTERRUPTS_SHARE_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup Share_Interrupts_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
int32_t INTC_ShareIrqCmd(en_int_src_t enIntSrc, en_functional_state_t enNewState);
|
||||
|
||||
void IRQ128_Handler(void);
|
||||
void IRQ129_Handler(void);
|
||||
void IRQ130_Handler(void);
|
||||
void IRQ131_Handler(void);
|
||||
void IRQ132_Handler(void);
|
||||
void IRQ136_Handler(void);
|
||||
void IRQ137_Handler(void);
|
||||
void IRQ138_Handler(void);
|
||||
void IRQ139_Handler(void);
|
||||
void IRQ140_Handler(void);
|
||||
void IRQ141_Handler(void);
|
||||
void IRQ142_Handler(void);
|
||||
void IRQ143_Handler(void);
|
||||
|
||||
void EXTINT00_IrqHandler(void);
|
||||
void EXTINT01_IrqHandler(void);
|
||||
void EXTINT02_IrqHandler(void);
|
||||
void EXTINT03_IrqHandler(void);
|
||||
void EXTINT04_IrqHandler(void);
|
||||
void EXTINT05_IrqHandler(void);
|
||||
void EXTINT06_IrqHandler(void);
|
||||
void EXTINT07_IrqHandler(void);
|
||||
void EXTINT08_IrqHandler(void);
|
||||
void EXTINT09_IrqHandler(void);
|
||||
void EXTINT10_IrqHandler(void);
|
||||
void EXTINT11_IrqHandler(void);
|
||||
void EXTINT12_IrqHandler(void);
|
||||
void EXTINT13_IrqHandler(void);
|
||||
void EXTINT14_IrqHandler(void);
|
||||
void EXTINT15_IrqHandler(void);
|
||||
|
||||
void DMA1_TC0_IrqHandler(void);
|
||||
void DMA1_TC1_IrqHandler(void);
|
||||
void DMA1_TC2_IrqHandler(void);
|
||||
void DMA1_TC3_IrqHandler(void);
|
||||
void DMA2_TC0_IrqHandler(void);
|
||||
void DMA2_TC1_IrqHandler(void);
|
||||
void DMA2_TC2_IrqHandler(void);
|
||||
void DMA2_TC3_IrqHandler(void);
|
||||
void DMA1_BTC0_IrqHandler(void);
|
||||
void DMA1_BTC1_IrqHandler(void);
|
||||
void DMA1_BTC2_IrqHandler(void);
|
||||
void DMA1_BTC3_IrqHandler(void);
|
||||
void DMA2_BTC0_IrqHandler(void);
|
||||
void DMA2_BTC1_IrqHandler(void);
|
||||
void DMA2_BTC2_IrqHandler(void);
|
||||
void DMA2_BTC3_IrqHandler(void);
|
||||
void DMA1_Error0_IrqHandler(void);
|
||||
void DMA1_Error1_IrqHandler(void);
|
||||
void DMA1_Error2_IrqHandler(void);
|
||||
void DMA1_Error3_IrqHandler(void);
|
||||
void DMA2_Error0_IrqHandler(void);
|
||||
void DMA2_Error1_IrqHandler(void);
|
||||
void DMA2_Error2_IrqHandler(void);
|
||||
void DMA2_Error3_IrqHandler(void);
|
||||
|
||||
void EFM_ProgramEraseError_IrqHandler(void);
|
||||
void EFM_ColError_IrqHandler(void);
|
||||
void EFM_OpEnd_IrqHandler(void);
|
||||
void QSPI_Error_IrqHandler(void);
|
||||
void DCU1_IrqHandler(void);
|
||||
void DCU2_IrqHandler(void);
|
||||
void DCU3_IrqHandler(void);
|
||||
void DCU4_IrqHandler(void);
|
||||
|
||||
void TMR0_1_CmpA_IrqHandler(void);
|
||||
void TMR0_1_CmpB_IrqHandler(void);
|
||||
void TMR0_2_CmpA_IrqHandler(void);
|
||||
void TMR0_2_CmpB_IrqHandler(void);
|
||||
|
||||
void CLK_XtalStop_IrqHandler(void);
|
||||
void PWC_WakeupTimer_IrqHandler(void);
|
||||
void SWDT_IrqHandler(void);
|
||||
void WDT_IrqHandler(void);
|
||||
|
||||
void TMR6_1_GCmpA_IrqHandler(void);
|
||||
void TMR6_1_GCmpB_IrqHandler(void);
|
||||
void TMR6_1_GCmpC_IrqHandler(void);
|
||||
void TMR6_1_GCmpD_IrqHandler(void);
|
||||
void TMR6_1_GCmpE_IrqHandler(void);
|
||||
void TMR6_1_GCmpF_IrqHandler(void);
|
||||
void TMR6_1_GOvf_IrqHandler(void);
|
||||
void TMR6_1_GUdf_IrqHandler(void);
|
||||
void TMR6_1_GDte_IrqHandler(void);
|
||||
void TMR6_1_SCmpA_IrqHandler(void);
|
||||
void TMR6_1_SCmpB_IrqHandler(void);
|
||||
|
||||
void TMR6_2_GCmpA_IrqHandler(void);
|
||||
void TMR6_2_GCmpB_IrqHandler(void);
|
||||
void TMR6_2_GCmpC_IrqHandler(void);
|
||||
void TMR6_2_GCmpD_IrqHandler(void);
|
||||
void TMR6_2_GCmpE_IrqHandler(void);
|
||||
void TMR6_2_GCmpF_IrqHandler(void);
|
||||
void TMR6_2_GOvf_IrqHandler(void);
|
||||
void TMR6_2_GUdf_IrqHandler(void);
|
||||
void TMR6_2_GDte_IrqHandler(void);
|
||||
void TMR6_2_SCmpA_IrqHandler(void);
|
||||
void TMR6_2_SCmpB_IrqHandler(void);
|
||||
|
||||
void TMR6_3_GCmpA_IrqHandler(void);
|
||||
void TMR6_3_GCmpB_IrqHandler(void);
|
||||
void TMR6_3_GCmpC_IrqHandler(void);
|
||||
void TMR6_3_GCmpD_IrqHandler(void);
|
||||
void TMR6_3_GCmpE_IrqHandler(void);
|
||||
void TMR6_3_GCmpF_IrqHandler(void);
|
||||
void TMR6_3_GOvf_IrqHandler(void);
|
||||
void TMR6_3_GUdf_IrqHandler(void);
|
||||
void TMR6_3_GDte_IrqHandler(void);
|
||||
void TMR6_3_SCmpA_IrqHandler(void);
|
||||
void TMR6_3_SCmpB_IrqHandler(void);
|
||||
|
||||
void TMRA_1_Ovf_IrqHandler(void);
|
||||
void TMRA_1_Udf_IrqHandler(void);
|
||||
void TMRA_1_Cmp_IrqHandler(void);
|
||||
void TMRA_2_Ovf_IrqHandler(void);
|
||||
void TMRA_2_Udf_IrqHandler(void);
|
||||
void TMRA_2_Cmp_IrqHandler(void);
|
||||
void TMRA_3_Ovf_IrqHandler(void);
|
||||
void TMRA_3_Udf_IrqHandler(void);
|
||||
void TMRA_3_Cmp_IrqHandler(void);
|
||||
void TMRA_4_Ovf_IrqHandler(void);
|
||||
void TMRA_4_Udf_IrqHandler(void);
|
||||
void TMRA_4_Cmp_IrqHandler(void);
|
||||
void TMRA_5_Ovf_IrqHandler(void);
|
||||
void TMRA_5_Udf_IrqHandler(void);
|
||||
void TMRA_5_Cmp_IrqHandler(void);
|
||||
void TMRA_6_Ovf_IrqHandler(void);
|
||||
void TMRA_6_Udf_IrqHandler(void);
|
||||
void TMRA_6_Cmp_IrqHandler(void);
|
||||
|
||||
void USBFS_Global_IrqHandler(void);
|
||||
|
||||
void USART1_RxError_IrqHandler(void);
|
||||
void USART1_RxFull_IrqHandler(void);
|
||||
void USART1_TxEmpty_IrqHandler(void);
|
||||
void USART1_TxComplete_IrqHandler(void);
|
||||
void USART1_RxTO_IrqHandler(void);
|
||||
void USART2_RxError_IrqHandler(void);
|
||||
void USART2_RxFull_IrqHandler(void);
|
||||
void USART2_TxEmpty_IrqHandler(void);
|
||||
void USART2_TxComplete_IrqHandler(void);
|
||||
void USART2_RxTO_IrqHandler(void);
|
||||
void USART3_RxError_IrqHandler(void);
|
||||
void USART3_RxFull_IrqHandler(void);
|
||||
void USART3_TxEmpty_IrqHandler(void);
|
||||
void USART3_TxComplete_IrqHandler(void);
|
||||
void USART3_RxTO_IrqHandler(void);
|
||||
void USART4_RxError_IrqHandler(void);
|
||||
void USART4_RxFull_IrqHandler(void);
|
||||
void USART4_TxEmpty_IrqHandler(void);
|
||||
void USART4_TxComplete_IrqHandler(void);
|
||||
void USART4_RxTO_IrqHandler(void);
|
||||
|
||||
void SPI1_RxFull_IrqHandler(void);
|
||||
void SPI1_TxEmpty_IrqHandler(void);
|
||||
void SPI1_Error_IrqHandler(void);
|
||||
void SPI1_Idle_IrqHandler(void);
|
||||
void SPI2_RxFull_IrqHandler(void);
|
||||
void SPI2_TxEmpty_IrqHandler(void);
|
||||
void SPI2_Error_IrqHandler(void);
|
||||
void SPI2_Idle_IrqHandler(void);
|
||||
void SPI3_RxFull_IrqHandler(void);
|
||||
void SPI3_TxEmpty_IrqHandler(void);
|
||||
void SPI3_Error_IrqHandler(void);
|
||||
void SPI3_Idle_IrqHandler(void);
|
||||
void SPI4_RxFull_IrqHandler(void);
|
||||
void SPI4_TxEmpty_IrqHandler(void);
|
||||
void SPI4_Error_IrqHandler(void);
|
||||
void SPI4_Idle_IrqHandler(void);
|
||||
|
||||
void TMR4_1_GCmpUH_IrqHandler(void);
|
||||
void TMR4_1_GCmpUL_IrqHandler(void);
|
||||
void TMR4_1_GCmpVH_IrqHandler(void);
|
||||
void TMR4_1_GCmpVL_IrqHandler(void);
|
||||
void TMR4_1_GCmpWH_IrqHandler(void);
|
||||
void TMR4_1_GCmpWL_IrqHandler(void);
|
||||
void TMR4_1_GOvf_IrqHandler(void);
|
||||
void TMR4_1_GUdf_IrqHandler(void);
|
||||
void TMR4_1_ReloadU_IrqHandler(void);
|
||||
void TMR4_1_ReloadV_IrqHandler(void);
|
||||
void TMR4_1_ReloadW_IrqHandler(void);
|
||||
void TMR4_2_GCmpUH_IrqHandler(void);
|
||||
void TMR4_2_GCmpUL_IrqHandler(void);
|
||||
void TMR4_2_GCmpVH_IrqHandler(void);
|
||||
void TMR4_2_GCmpVL_IrqHandler(void);
|
||||
void TMR4_2_GCmpWH_IrqHandler(void);
|
||||
void TMR4_2_GCmpWL_IrqHandler(void);
|
||||
void TMR4_2_GOvf_IrqHandler(void);
|
||||
void TMR4_2_GUdf_IrqHandler(void);
|
||||
void TMR4_2_ReloadU_IrqHandler(void);
|
||||
void TMR4_2_ReloadV_IrqHandler(void);
|
||||
void TMR4_2_ReloadW_IrqHandler(void);
|
||||
void TMR4_3_GCmpUH_IrqHandler(void);
|
||||
void TMR4_3_GCmpUL_IrqHandler(void);
|
||||
void TMR4_3_GCmpVH_IrqHandler(void);
|
||||
void TMR4_3_GCmpVL_IrqHandler(void);
|
||||
void TMR4_3_GCmpWH_IrqHandler(void);
|
||||
void TMR4_3_GCmpWL_IrqHandler(void);
|
||||
void TMR4_3_GOvf_IrqHandler(void);
|
||||
void TMR4_3_GUdf_IrqHandler(void);
|
||||
void TMR4_3_ReloadU_IrqHandler(void);
|
||||
void TMR4_3_ReloadV_IrqHandler(void);
|
||||
void TMR4_3_ReloadW_IrqHandler(void);
|
||||
|
||||
void EMB_GR0_IrqHandler(void);
|
||||
void EMB_GR1_IrqHandler(void);
|
||||
void EMB_GR2_IrqHandler(void);
|
||||
void EMB_GR3_IrqHandler(void);
|
||||
|
||||
void I2S1_Tx_IrqHandler(void);
|
||||
void I2S1_Rx_IrqHandler(void);
|
||||
void I2S1_Error_IrqHandler(void);
|
||||
void I2S2_Tx_IrqHandler(void);
|
||||
void I2S2_Rx_IrqHandler(void);
|
||||
void I2S2_Error_IrqHandler(void);
|
||||
void I2S3_Tx_IrqHandler(void);
|
||||
void I2S3_Rx_IrqHandler(void);
|
||||
void I2S3_Error_IrqHandler(void);
|
||||
void I2S4_Tx_IrqHandler(void);
|
||||
void I2S4_Rx_IrqHandler(void);
|
||||
void I2S4_Error_IrqHandler(void);
|
||||
|
||||
void I2C1_RxFull_IrqHandler(void);
|
||||
void I2C1_TxComplete_IrqHandler(void);
|
||||
void I2C1_TxEmpty_IrqHandler(void);
|
||||
void I2C1_EE_IrqHandler(void);
|
||||
void I2C2_RxFull_IrqHandler(void);
|
||||
void I2C2_TxComplete_IrqHandler(void);
|
||||
void I2C2_TxEmpty_IrqHandler(void);
|
||||
void I2C2_EE_IrqHandler(void);
|
||||
void I2C3_RxFull_IrqHandler(void);
|
||||
void I2C3_TxComplete_IrqHandler(void);
|
||||
void I2C3_TxEmpty_IrqHandler(void);
|
||||
void I2C3_EE_IrqHandler(void);
|
||||
|
||||
void PWC_LVD1_IrqHandler(void);
|
||||
void PWC_LVD2_IrqHandler(void);
|
||||
|
||||
void FCM_Error_IrqHandler(void);
|
||||
void FCM_End_IrqHandler(void);
|
||||
void FCM_Ovf_IrqHandler(void);
|
||||
|
||||
void ADC1_SeqA_IrqHandler(void);
|
||||
void ADC1_SeqB_IrqHandler(void);
|
||||
void ADC1_ChCmp_IrqHandler(void);
|
||||
void ADC1_SeqCmp_IrqHandler(void);
|
||||
void ADC2_SeqA_IrqHandler(void);
|
||||
void ADC2_SeqB_IrqHandler(void);
|
||||
void ADC2_ChCmp_IrqHandler(void);
|
||||
void ADC2_SeqCmp_IrqHandler(void);
|
||||
|
||||
void SDIOC1_IrqHandler(void);
|
||||
void SDIOC2_IrqHandler(void);
|
||||
|
||||
void CAN_IrqHandler(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LL_INTERRUPTS_SHARE_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32F4A0_LL_INTERRUPTS_SHARE_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user