初始版本
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;/**
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; ******************************************************************************
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; @file startup_hc32f460.s
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; @brief Startup for MDK.
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; verbatim
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; Change Logs:
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; Date Author Notes
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; 2022-03-31 CDT First version
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; 2024-11-08 CDT Added code of clear SRAMC status flags
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; endverbatim
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; *****************************************************************************
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; * Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved.
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; *
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; * This software component is licensed by XHSC under BSD 3-Clause license
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; * (the "License"); You may not use this file except in compliance with the
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; * License. You may obtain a copy of the License at:
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; * opensource.org/licenses/BSD-3-Clause
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; *
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; ******************************************************************************
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; */
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; Stack Configuration
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; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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Stack_Size EQU 0x00002000
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; Heap Configuration
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; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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Heap_Size EQU 0x00002000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; Peripheral Interrupts
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DCD IRQ000_Handler
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DCD IRQ001_Handler
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DCD IRQ002_Handler
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DCD IRQ003_Handler
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DCD IRQ004_Handler
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DCD IRQ005_Handler
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DCD IRQ006_Handler
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DCD IRQ007_Handler
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DCD IRQ008_Handler
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DCD IRQ009_Handler
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DCD IRQ010_Handler
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DCD IRQ011_Handler
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DCD IRQ012_Handler
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DCD IRQ013_Handler
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DCD IRQ014_Handler
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DCD IRQ015_Handler
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DCD IRQ016_Handler
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DCD IRQ017_Handler
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DCD IRQ018_Handler
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DCD IRQ019_Handler
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DCD IRQ020_Handler
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DCD IRQ021_Handler
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DCD IRQ022_Handler
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DCD IRQ023_Handler
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DCD IRQ024_Handler
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DCD IRQ025_Handler
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DCD IRQ026_Handler
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DCD IRQ027_Handler
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DCD IRQ028_Handler
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DCD IRQ029_Handler
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DCD IRQ030_Handler
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DCD IRQ031_Handler
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DCD IRQ032_Handler
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DCD IRQ033_Handler
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DCD IRQ034_Handler
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DCD IRQ035_Handler
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DCD IRQ036_Handler
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DCD IRQ037_Handler
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DCD IRQ038_Handler
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DCD IRQ039_Handler
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DCD IRQ040_Handler
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DCD IRQ041_Handler
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DCD IRQ042_Handler
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DCD IRQ043_Handler
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DCD IRQ044_Handler
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DCD IRQ045_Handler
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DCD IRQ046_Handler
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DCD IRQ047_Handler
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DCD IRQ048_Handler
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DCD IRQ049_Handler
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DCD IRQ050_Handler
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DCD IRQ051_Handler
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DCD IRQ052_Handler
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DCD IRQ053_Handler
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||||
DCD IRQ054_Handler
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||||
DCD IRQ055_Handler
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DCD IRQ056_Handler
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||||
DCD IRQ057_Handler
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DCD IRQ058_Handler
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||||
DCD IRQ059_Handler
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||||
DCD IRQ060_Handler
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||||
DCD IRQ061_Handler
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||||
DCD IRQ062_Handler
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||||
DCD IRQ063_Handler
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DCD IRQ064_Handler
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||||
DCD IRQ065_Handler
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||||
DCD IRQ066_Handler
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||||
DCD IRQ067_Handler
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||||
DCD IRQ068_Handler
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DCD IRQ069_Handler
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||||
DCD IRQ070_Handler
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DCD IRQ071_Handler
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DCD IRQ072_Handler
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DCD IRQ073_Handler
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DCD IRQ074_Handler
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DCD IRQ075_Handler
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DCD IRQ076_Handler
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DCD IRQ077_Handler
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DCD IRQ078_Handler
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DCD IRQ079_Handler
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DCD IRQ080_Handler
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DCD IRQ081_Handler
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DCD IRQ082_Handler
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DCD IRQ083_Handler
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DCD IRQ084_Handler
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DCD IRQ085_Handler
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DCD IRQ086_Handler
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DCD IRQ087_Handler
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DCD IRQ088_Handler
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DCD IRQ089_Handler
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DCD IRQ090_Handler
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DCD IRQ091_Handler
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DCD IRQ092_Handler
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DCD IRQ093_Handler
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DCD IRQ094_Handler
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DCD IRQ095_Handler
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DCD IRQ096_Handler
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DCD IRQ097_Handler
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DCD IRQ098_Handler
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||||
DCD IRQ099_Handler
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DCD IRQ100_Handler
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||||
DCD IRQ101_Handler
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DCD IRQ102_Handler
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||||
DCD IRQ103_Handler
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||||
DCD IRQ104_Handler
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||||
DCD IRQ105_Handler
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||||
DCD IRQ106_Handler
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||||
DCD IRQ107_Handler
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||||
DCD IRQ108_Handler
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||||
DCD IRQ109_Handler
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||||
DCD IRQ110_Handler
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||||
DCD IRQ111_Handler
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||||
DCD IRQ112_Handler
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||||
DCD IRQ113_Handler
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||||
DCD IRQ114_Handler
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||||
DCD IRQ115_Handler
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||||
DCD IRQ116_Handler
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||||
DCD IRQ117_Handler
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||||
DCD IRQ118_Handler
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||||
DCD IRQ119_Handler
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||||
DCD IRQ120_Handler
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||||
DCD IRQ121_Handler
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||||
DCD IRQ122_Handler
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||||
DCD IRQ123_Handler
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||||
DCD IRQ124_Handler
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||||
DCD IRQ125_Handler
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||||
DCD IRQ126_Handler
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||||
DCD IRQ127_Handler
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||||
DCD IRQ128_Handler
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||||
DCD IRQ129_Handler
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||||
DCD IRQ130_Handler
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||||
DCD IRQ131_Handler
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||||
DCD IRQ132_Handler
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||||
DCD IRQ133_Handler
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||||
DCD IRQ134_Handler
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||||
DCD IRQ135_Handler
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||||
DCD IRQ136_Handler
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||||
DCD IRQ137_Handler
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||||
DCD IRQ138_Handler
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||||
DCD IRQ139_Handler
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||||
DCD IRQ140_Handler
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||||
DCD IRQ141_Handler
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||||
DCD IRQ142_Handler
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||||
DCD IRQ143_Handler
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||||
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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;ClrSramSR
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LDR R0, =0x40050810
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LDR R1, =0x1F
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STR R1, [R0]
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;SetSRAM3Wait
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LDR R0, =0x40050804
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MOV R1, #0x77
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STR R1, [R0]
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LDR R0, =0x4005080C
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MOV R1, #0x77
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STR R1, [R0]
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LDR R0, =0x40050800
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MOV R1, #0x1100
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STR R1, [R0]
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LDR R0, =0x40050804
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MOV R1, #0x76
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STR R1, [R0]
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LDR R0, =0x4005080C
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MOV R1, #0x76
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STR R1, [R0]
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT IRQ000_Handler [WEAK]
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EXPORT IRQ001_Handler [WEAK]
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EXPORT IRQ002_Handler [WEAK]
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EXPORT IRQ003_Handler [WEAK]
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EXPORT IRQ004_Handler [WEAK]
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EXPORT IRQ005_Handler [WEAK]
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EXPORT IRQ006_Handler [WEAK]
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EXPORT IRQ007_Handler [WEAK]
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EXPORT IRQ008_Handler [WEAK]
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EXPORT IRQ009_Handler [WEAK]
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EXPORT IRQ010_Handler [WEAK]
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EXPORT IRQ011_Handler [WEAK]
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EXPORT IRQ012_Handler [WEAK]
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EXPORT IRQ013_Handler [WEAK]
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EXPORT IRQ014_Handler [WEAK]
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EXPORT IRQ015_Handler [WEAK]
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EXPORT IRQ016_Handler [WEAK]
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EXPORT IRQ017_Handler [WEAK]
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EXPORT IRQ018_Handler [WEAK]
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EXPORT IRQ019_Handler [WEAK]
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EXPORT IRQ020_Handler [WEAK]
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EXPORT IRQ021_Handler [WEAK]
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EXPORT IRQ022_Handler [WEAK]
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EXPORT IRQ023_Handler [WEAK]
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EXPORT IRQ024_Handler [WEAK]
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EXPORT IRQ025_Handler [WEAK]
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EXPORT IRQ026_Handler [WEAK]
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EXPORT IRQ027_Handler [WEAK]
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EXPORT IRQ028_Handler [WEAK]
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EXPORT IRQ029_Handler [WEAK]
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EXPORT IRQ030_Handler [WEAK]
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EXPORT IRQ031_Handler [WEAK]
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EXPORT IRQ032_Handler [WEAK]
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EXPORT IRQ033_Handler [WEAK]
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EXPORT IRQ034_Handler [WEAK]
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EXPORT IRQ035_Handler [WEAK]
|
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EXPORT IRQ036_Handler [WEAK]
|
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EXPORT IRQ037_Handler [WEAK]
|
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EXPORT IRQ038_Handler [WEAK]
|
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EXPORT IRQ039_Handler [WEAK]
|
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EXPORT IRQ040_Handler [WEAK]
|
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EXPORT IRQ041_Handler [WEAK]
|
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EXPORT IRQ042_Handler [WEAK]
|
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EXPORT IRQ043_Handler [WEAK]
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EXPORT IRQ044_Handler [WEAK]
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EXPORT IRQ045_Handler [WEAK]
|
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EXPORT IRQ046_Handler [WEAK]
|
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EXPORT IRQ047_Handler [WEAK]
|
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EXPORT IRQ048_Handler [WEAK]
|
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EXPORT IRQ049_Handler [WEAK]
|
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EXPORT IRQ050_Handler [WEAK]
|
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EXPORT IRQ051_Handler [WEAK]
|
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EXPORT IRQ052_Handler [WEAK]
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EXPORT IRQ053_Handler [WEAK]
|
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EXPORT IRQ054_Handler [WEAK]
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EXPORT IRQ055_Handler [WEAK]
|
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EXPORT IRQ056_Handler [WEAK]
|
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EXPORT IRQ057_Handler [WEAK]
|
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EXPORT IRQ058_Handler [WEAK]
|
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EXPORT IRQ059_Handler [WEAK]
|
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EXPORT IRQ060_Handler [WEAK]
|
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EXPORT IRQ061_Handler [WEAK]
|
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EXPORT IRQ062_Handler [WEAK]
|
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EXPORT IRQ063_Handler [WEAK]
|
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EXPORT IRQ064_Handler [WEAK]
|
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EXPORT IRQ065_Handler [WEAK]
|
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EXPORT IRQ066_Handler [WEAK]
|
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EXPORT IRQ067_Handler [WEAK]
|
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EXPORT IRQ068_Handler [WEAK]
|
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EXPORT IRQ069_Handler [WEAK]
|
||||
EXPORT IRQ070_Handler [WEAK]
|
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EXPORT IRQ071_Handler [WEAK]
|
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EXPORT IRQ072_Handler [WEAK]
|
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EXPORT IRQ073_Handler [WEAK]
|
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EXPORT IRQ074_Handler [WEAK]
|
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EXPORT IRQ075_Handler [WEAK]
|
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EXPORT IRQ076_Handler [WEAK]
|
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EXPORT IRQ077_Handler [WEAK]
|
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EXPORT IRQ078_Handler [WEAK]
|
||||
EXPORT IRQ079_Handler [WEAK]
|
||||
EXPORT IRQ080_Handler [WEAK]
|
||||
EXPORT IRQ081_Handler [WEAK]
|
||||
EXPORT IRQ082_Handler [WEAK]
|
||||
EXPORT IRQ083_Handler [WEAK]
|
||||
EXPORT IRQ084_Handler [WEAK]
|
||||
EXPORT IRQ085_Handler [WEAK]
|
||||
EXPORT IRQ086_Handler [WEAK]
|
||||
EXPORT IRQ087_Handler [WEAK]
|
||||
EXPORT IRQ088_Handler [WEAK]
|
||||
EXPORT IRQ089_Handler [WEAK]
|
||||
EXPORT IRQ090_Handler [WEAK]
|
||||
EXPORT IRQ091_Handler [WEAK]
|
||||
EXPORT IRQ092_Handler [WEAK]
|
||||
EXPORT IRQ093_Handler [WEAK]
|
||||
EXPORT IRQ094_Handler [WEAK]
|
||||
EXPORT IRQ095_Handler [WEAK]
|
||||
EXPORT IRQ096_Handler [WEAK]
|
||||
EXPORT IRQ097_Handler [WEAK]
|
||||
EXPORT IRQ098_Handler [WEAK]
|
||||
EXPORT IRQ099_Handler [WEAK]
|
||||
EXPORT IRQ100_Handler [WEAK]
|
||||
EXPORT IRQ101_Handler [WEAK]
|
||||
EXPORT IRQ102_Handler [WEAK]
|
||||
EXPORT IRQ103_Handler [WEAK]
|
||||
EXPORT IRQ104_Handler [WEAK]
|
||||
EXPORT IRQ105_Handler [WEAK]
|
||||
EXPORT IRQ106_Handler [WEAK]
|
||||
EXPORT IRQ107_Handler [WEAK]
|
||||
EXPORT IRQ108_Handler [WEAK]
|
||||
EXPORT IRQ109_Handler [WEAK]
|
||||
EXPORT IRQ110_Handler [WEAK]
|
||||
EXPORT IRQ111_Handler [WEAK]
|
||||
EXPORT IRQ112_Handler [WEAK]
|
||||
EXPORT IRQ113_Handler [WEAK]
|
||||
EXPORT IRQ114_Handler [WEAK]
|
||||
EXPORT IRQ115_Handler [WEAK]
|
||||
EXPORT IRQ116_Handler [WEAK]
|
||||
EXPORT IRQ117_Handler [WEAK]
|
||||
EXPORT IRQ118_Handler [WEAK]
|
||||
EXPORT IRQ119_Handler [WEAK]
|
||||
EXPORT IRQ120_Handler [WEAK]
|
||||
EXPORT IRQ121_Handler [WEAK]
|
||||
EXPORT IRQ122_Handler [WEAK]
|
||||
EXPORT IRQ123_Handler [WEAK]
|
||||
EXPORT IRQ124_Handler [WEAK]
|
||||
EXPORT IRQ125_Handler [WEAK]
|
||||
EXPORT IRQ126_Handler [WEAK]
|
||||
EXPORT IRQ127_Handler [WEAK]
|
||||
EXPORT IRQ128_Handler [WEAK]
|
||||
EXPORT IRQ129_Handler [WEAK]
|
||||
EXPORT IRQ130_Handler [WEAK]
|
||||
EXPORT IRQ131_Handler [WEAK]
|
||||
EXPORT IRQ132_Handler [WEAK]
|
||||
EXPORT IRQ133_Handler [WEAK]
|
||||
EXPORT IRQ134_Handler [WEAK]
|
||||
EXPORT IRQ135_Handler [WEAK]
|
||||
EXPORT IRQ136_Handler [WEAK]
|
||||
EXPORT IRQ137_Handler [WEAK]
|
||||
EXPORT IRQ138_Handler [WEAK]
|
||||
EXPORT IRQ139_Handler [WEAK]
|
||||
EXPORT IRQ140_Handler [WEAK]
|
||||
EXPORT IRQ141_Handler [WEAK]
|
||||
EXPORT IRQ142_Handler [WEAK]
|
||||
EXPORT IRQ143_Handler [WEAK]
|
||||
|
||||
IRQ000_Handler
|
||||
IRQ001_Handler
|
||||
IRQ002_Handler
|
||||
IRQ003_Handler
|
||||
IRQ004_Handler
|
||||
IRQ005_Handler
|
||||
IRQ006_Handler
|
||||
IRQ007_Handler
|
||||
IRQ008_Handler
|
||||
IRQ009_Handler
|
||||
IRQ010_Handler
|
||||
IRQ011_Handler
|
||||
IRQ012_Handler
|
||||
IRQ013_Handler
|
||||
IRQ014_Handler
|
||||
IRQ015_Handler
|
||||
IRQ016_Handler
|
||||
IRQ017_Handler
|
||||
IRQ018_Handler
|
||||
IRQ019_Handler
|
||||
IRQ020_Handler
|
||||
IRQ021_Handler
|
||||
IRQ022_Handler
|
||||
IRQ023_Handler
|
||||
IRQ024_Handler
|
||||
IRQ025_Handler
|
||||
IRQ026_Handler
|
||||
IRQ027_Handler
|
||||
IRQ028_Handler
|
||||
IRQ029_Handler
|
||||
IRQ030_Handler
|
||||
IRQ031_Handler
|
||||
IRQ032_Handler
|
||||
IRQ033_Handler
|
||||
IRQ034_Handler
|
||||
IRQ035_Handler
|
||||
IRQ036_Handler
|
||||
IRQ037_Handler
|
||||
IRQ038_Handler
|
||||
IRQ039_Handler
|
||||
IRQ040_Handler
|
||||
IRQ041_Handler
|
||||
IRQ042_Handler
|
||||
IRQ043_Handler
|
||||
IRQ044_Handler
|
||||
IRQ045_Handler
|
||||
IRQ046_Handler
|
||||
IRQ047_Handler
|
||||
IRQ048_Handler
|
||||
IRQ049_Handler
|
||||
IRQ050_Handler
|
||||
IRQ051_Handler
|
||||
IRQ052_Handler
|
||||
IRQ053_Handler
|
||||
IRQ054_Handler
|
||||
IRQ055_Handler
|
||||
IRQ056_Handler
|
||||
IRQ057_Handler
|
||||
IRQ058_Handler
|
||||
IRQ059_Handler
|
||||
IRQ060_Handler
|
||||
IRQ061_Handler
|
||||
IRQ062_Handler
|
||||
IRQ063_Handler
|
||||
IRQ064_Handler
|
||||
IRQ065_Handler
|
||||
IRQ066_Handler
|
||||
IRQ067_Handler
|
||||
IRQ068_Handler
|
||||
IRQ069_Handler
|
||||
IRQ070_Handler
|
||||
IRQ071_Handler
|
||||
IRQ072_Handler
|
||||
IRQ073_Handler
|
||||
IRQ074_Handler
|
||||
IRQ075_Handler
|
||||
IRQ076_Handler
|
||||
IRQ077_Handler
|
||||
IRQ078_Handler
|
||||
IRQ079_Handler
|
||||
IRQ080_Handler
|
||||
IRQ081_Handler
|
||||
IRQ082_Handler
|
||||
IRQ083_Handler
|
||||
IRQ084_Handler
|
||||
IRQ085_Handler
|
||||
IRQ086_Handler
|
||||
IRQ087_Handler
|
||||
IRQ088_Handler
|
||||
IRQ089_Handler
|
||||
IRQ090_Handler
|
||||
IRQ091_Handler
|
||||
IRQ092_Handler
|
||||
IRQ093_Handler
|
||||
IRQ094_Handler
|
||||
IRQ095_Handler
|
||||
IRQ096_Handler
|
||||
IRQ097_Handler
|
||||
IRQ098_Handler
|
||||
IRQ099_Handler
|
||||
IRQ100_Handler
|
||||
IRQ101_Handler
|
||||
IRQ102_Handler
|
||||
IRQ103_Handler
|
||||
IRQ104_Handler
|
||||
IRQ105_Handler
|
||||
IRQ106_Handler
|
||||
IRQ107_Handler
|
||||
IRQ108_Handler
|
||||
IRQ109_Handler
|
||||
IRQ110_Handler
|
||||
IRQ111_Handler
|
||||
IRQ112_Handler
|
||||
IRQ113_Handler
|
||||
IRQ114_Handler
|
||||
IRQ115_Handler
|
||||
IRQ116_Handler
|
||||
IRQ117_Handler
|
||||
IRQ118_Handler
|
||||
IRQ119_Handler
|
||||
IRQ120_Handler
|
||||
IRQ121_Handler
|
||||
IRQ122_Handler
|
||||
IRQ123_Handler
|
||||
IRQ124_Handler
|
||||
IRQ125_Handler
|
||||
IRQ126_Handler
|
||||
IRQ127_Handler
|
||||
IRQ128_Handler
|
||||
IRQ129_Handler
|
||||
IRQ130_Handler
|
||||
IRQ131_Handler
|
||||
IRQ132_Handler
|
||||
IRQ133_Handler
|
||||
IRQ134_Handler
|
||||
IRQ135_Handler
|
||||
IRQ136_Handler
|
||||
IRQ137_Handler
|
||||
IRQ138_Handler
|
||||
IRQ139_Handler
|
||||
IRQ140_Handler
|
||||
IRQ141_Handler
|
||||
IRQ142_Handler
|
||||
IRQ143_Handler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
@@ -0,0 +1,623 @@
|
||||
;/**
|
||||
; ******************************************************************************
|
||||
; @file startup_hc32f460.s
|
||||
; @brief Startup for MDK.
|
||||
; verbatim
|
||||
; Change Logs:
|
||||
; Date Author Notes
|
||||
; 2022-03-31 CDT First version
|
||||
; 2024-11-08 CDT Added code of clear SRAMC status flags
|
||||
; endverbatim
|
||||
; *****************************************************************************
|
||||
; * Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
; *
|
||||
; * This software component is licensed by XHSC under BSD 3-Clause license
|
||||
; * (the "License"); You may not use this file except in compliance with the
|
||||
; * License. You may obtain a copy of the License at:
|
||||
; * opensource.org/licenses/BSD-3-Clause
|
||||
; *
|
||||
; ******************************************************************************
|
||||
; */
|
||||
|
||||
; Stack Configuration
|
||||
; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
|
||||
Stack_Size EQU 0x00002000
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; Heap Configuration
|
||||
; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
|
||||
Heap_Size EQU 0x00002000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; Peripheral Interrupts
|
||||
DCD IRQ000_Handler
|
||||
DCD IRQ001_Handler
|
||||
DCD IRQ002_Handler
|
||||
DCD IRQ003_Handler
|
||||
DCD IRQ004_Handler
|
||||
DCD IRQ005_Handler
|
||||
DCD IRQ006_Handler
|
||||
DCD IRQ007_Handler
|
||||
DCD IRQ008_Handler
|
||||
DCD IRQ009_Handler
|
||||
DCD IRQ010_Handler
|
||||
DCD IRQ011_Handler
|
||||
DCD IRQ012_Handler
|
||||
DCD IRQ013_Handler
|
||||
DCD IRQ014_Handler
|
||||
DCD IRQ015_Handler
|
||||
DCD IRQ016_Handler
|
||||
DCD IRQ017_Handler
|
||||
DCD IRQ018_Handler
|
||||
DCD IRQ019_Handler
|
||||
DCD IRQ020_Handler
|
||||
DCD IRQ021_Handler
|
||||
DCD IRQ022_Handler
|
||||
DCD IRQ023_Handler
|
||||
DCD IRQ024_Handler
|
||||
DCD IRQ025_Handler
|
||||
DCD IRQ026_Handler
|
||||
DCD IRQ027_Handler
|
||||
DCD IRQ028_Handler
|
||||
DCD IRQ029_Handler
|
||||
DCD IRQ030_Handler
|
||||
DCD IRQ031_Handler
|
||||
DCD IRQ032_Handler
|
||||
DCD IRQ033_Handler
|
||||
DCD IRQ034_Handler
|
||||
DCD IRQ035_Handler
|
||||
DCD IRQ036_Handler
|
||||
DCD IRQ037_Handler
|
||||
DCD IRQ038_Handler
|
||||
DCD IRQ039_Handler
|
||||
DCD IRQ040_Handler
|
||||
DCD IRQ041_Handler
|
||||
DCD IRQ042_Handler
|
||||
DCD IRQ043_Handler
|
||||
DCD IRQ044_Handler
|
||||
DCD IRQ045_Handler
|
||||
DCD IRQ046_Handler
|
||||
DCD IRQ047_Handler
|
||||
DCD IRQ048_Handler
|
||||
DCD IRQ049_Handler
|
||||
DCD IRQ050_Handler
|
||||
DCD IRQ051_Handler
|
||||
DCD IRQ052_Handler
|
||||
DCD IRQ053_Handler
|
||||
DCD IRQ054_Handler
|
||||
DCD IRQ055_Handler
|
||||
DCD IRQ056_Handler
|
||||
DCD IRQ057_Handler
|
||||
DCD IRQ058_Handler
|
||||
DCD IRQ059_Handler
|
||||
DCD IRQ060_Handler
|
||||
DCD IRQ061_Handler
|
||||
DCD IRQ062_Handler
|
||||
DCD IRQ063_Handler
|
||||
DCD IRQ064_Handler
|
||||
DCD IRQ065_Handler
|
||||
DCD IRQ066_Handler
|
||||
DCD IRQ067_Handler
|
||||
DCD IRQ068_Handler
|
||||
DCD IRQ069_Handler
|
||||
DCD IRQ070_Handler
|
||||
DCD IRQ071_Handler
|
||||
DCD IRQ072_Handler
|
||||
DCD IRQ073_Handler
|
||||
DCD IRQ074_Handler
|
||||
DCD IRQ075_Handler
|
||||
DCD IRQ076_Handler
|
||||
DCD IRQ077_Handler
|
||||
DCD IRQ078_Handler
|
||||
DCD IRQ079_Handler
|
||||
DCD IRQ080_Handler
|
||||
DCD IRQ081_Handler
|
||||
DCD IRQ082_Handler
|
||||
DCD IRQ083_Handler
|
||||
DCD IRQ084_Handler
|
||||
DCD IRQ085_Handler
|
||||
DCD IRQ086_Handler
|
||||
DCD IRQ087_Handler
|
||||
DCD IRQ088_Handler
|
||||
DCD IRQ089_Handler
|
||||
DCD IRQ090_Handler
|
||||
DCD IRQ091_Handler
|
||||
DCD IRQ092_Handler
|
||||
DCD IRQ093_Handler
|
||||
DCD IRQ094_Handler
|
||||
DCD IRQ095_Handler
|
||||
DCD IRQ096_Handler
|
||||
DCD IRQ097_Handler
|
||||
DCD IRQ098_Handler
|
||||
DCD IRQ099_Handler
|
||||
DCD IRQ100_Handler
|
||||
DCD IRQ101_Handler
|
||||
DCD IRQ102_Handler
|
||||
DCD IRQ103_Handler
|
||||
DCD IRQ104_Handler
|
||||
DCD IRQ105_Handler
|
||||
DCD IRQ106_Handler
|
||||
DCD IRQ107_Handler
|
||||
DCD IRQ108_Handler
|
||||
DCD IRQ109_Handler
|
||||
DCD IRQ110_Handler
|
||||
DCD IRQ111_Handler
|
||||
DCD IRQ112_Handler
|
||||
DCD IRQ113_Handler
|
||||
DCD IRQ114_Handler
|
||||
DCD IRQ115_Handler
|
||||
DCD IRQ116_Handler
|
||||
DCD IRQ117_Handler
|
||||
DCD IRQ118_Handler
|
||||
DCD IRQ119_Handler
|
||||
DCD IRQ120_Handler
|
||||
DCD IRQ121_Handler
|
||||
DCD IRQ122_Handler
|
||||
DCD IRQ123_Handler
|
||||
DCD IRQ124_Handler
|
||||
DCD IRQ125_Handler
|
||||
DCD IRQ126_Handler
|
||||
DCD IRQ127_Handler
|
||||
DCD IRQ128_Handler
|
||||
DCD IRQ129_Handler
|
||||
DCD IRQ130_Handler
|
||||
DCD IRQ131_Handler
|
||||
DCD IRQ132_Handler
|
||||
DCD IRQ133_Handler
|
||||
DCD IRQ134_Handler
|
||||
DCD IRQ135_Handler
|
||||
DCD IRQ136_Handler
|
||||
DCD IRQ137_Handler
|
||||
DCD IRQ138_Handler
|
||||
DCD IRQ139_Handler
|
||||
DCD IRQ140_Handler
|
||||
DCD IRQ141_Handler
|
||||
DCD IRQ142_Handler
|
||||
DCD IRQ143_Handler
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
;ClrSramSR
|
||||
LDR R0, =0x40050810
|
||||
LDR R1, =0x1F
|
||||
STR R1, [R0]
|
||||
;SetSRAM3Wait
|
||||
LDR R0, =0x40050804
|
||||
MOV R1, #0x77
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =0x4005080C
|
||||
MOV R1, #0x77
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =0x40050800
|
||||
MOV R1, #0x1100
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =0x40050804
|
||||
MOV R1, #0x76
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =0x4005080C
|
||||
MOV R1, #0x76
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT IRQ000_Handler [WEAK]
|
||||
EXPORT IRQ001_Handler [WEAK]
|
||||
EXPORT IRQ002_Handler [WEAK]
|
||||
EXPORT IRQ003_Handler [WEAK]
|
||||
EXPORT IRQ004_Handler [WEAK]
|
||||
EXPORT IRQ005_Handler [WEAK]
|
||||
EXPORT IRQ006_Handler [WEAK]
|
||||
EXPORT IRQ007_Handler [WEAK]
|
||||
EXPORT IRQ008_Handler [WEAK]
|
||||
EXPORT IRQ009_Handler [WEAK]
|
||||
EXPORT IRQ010_Handler [WEAK]
|
||||
EXPORT IRQ011_Handler [WEAK]
|
||||
EXPORT IRQ012_Handler [WEAK]
|
||||
EXPORT IRQ013_Handler [WEAK]
|
||||
EXPORT IRQ014_Handler [WEAK]
|
||||
EXPORT IRQ015_Handler [WEAK]
|
||||
EXPORT IRQ016_Handler [WEAK]
|
||||
EXPORT IRQ017_Handler [WEAK]
|
||||
EXPORT IRQ018_Handler [WEAK]
|
||||
EXPORT IRQ019_Handler [WEAK]
|
||||
EXPORT IRQ020_Handler [WEAK]
|
||||
EXPORT IRQ021_Handler [WEAK]
|
||||
EXPORT IRQ022_Handler [WEAK]
|
||||
EXPORT IRQ023_Handler [WEAK]
|
||||
EXPORT IRQ024_Handler [WEAK]
|
||||
EXPORT IRQ025_Handler [WEAK]
|
||||
EXPORT IRQ026_Handler [WEAK]
|
||||
EXPORT IRQ027_Handler [WEAK]
|
||||
EXPORT IRQ028_Handler [WEAK]
|
||||
EXPORT IRQ029_Handler [WEAK]
|
||||
EXPORT IRQ030_Handler [WEAK]
|
||||
EXPORT IRQ031_Handler [WEAK]
|
||||
EXPORT IRQ032_Handler [WEAK]
|
||||
EXPORT IRQ033_Handler [WEAK]
|
||||
EXPORT IRQ034_Handler [WEAK]
|
||||
EXPORT IRQ035_Handler [WEAK]
|
||||
EXPORT IRQ036_Handler [WEAK]
|
||||
EXPORT IRQ037_Handler [WEAK]
|
||||
EXPORT IRQ038_Handler [WEAK]
|
||||
EXPORT IRQ039_Handler [WEAK]
|
||||
EXPORT IRQ040_Handler [WEAK]
|
||||
EXPORT IRQ041_Handler [WEAK]
|
||||
EXPORT IRQ042_Handler [WEAK]
|
||||
EXPORT IRQ043_Handler [WEAK]
|
||||
EXPORT IRQ044_Handler [WEAK]
|
||||
EXPORT IRQ045_Handler [WEAK]
|
||||
EXPORT IRQ046_Handler [WEAK]
|
||||
EXPORT IRQ047_Handler [WEAK]
|
||||
EXPORT IRQ048_Handler [WEAK]
|
||||
EXPORT IRQ049_Handler [WEAK]
|
||||
EXPORT IRQ050_Handler [WEAK]
|
||||
EXPORT IRQ051_Handler [WEAK]
|
||||
EXPORT IRQ052_Handler [WEAK]
|
||||
EXPORT IRQ053_Handler [WEAK]
|
||||
EXPORT IRQ054_Handler [WEAK]
|
||||
EXPORT IRQ055_Handler [WEAK]
|
||||
EXPORT IRQ056_Handler [WEAK]
|
||||
EXPORT IRQ057_Handler [WEAK]
|
||||
EXPORT IRQ058_Handler [WEAK]
|
||||
EXPORT IRQ059_Handler [WEAK]
|
||||
EXPORT IRQ060_Handler [WEAK]
|
||||
EXPORT IRQ061_Handler [WEAK]
|
||||
EXPORT IRQ062_Handler [WEAK]
|
||||
EXPORT IRQ063_Handler [WEAK]
|
||||
EXPORT IRQ064_Handler [WEAK]
|
||||
EXPORT IRQ065_Handler [WEAK]
|
||||
EXPORT IRQ066_Handler [WEAK]
|
||||
EXPORT IRQ067_Handler [WEAK]
|
||||
EXPORT IRQ068_Handler [WEAK]
|
||||
EXPORT IRQ069_Handler [WEAK]
|
||||
EXPORT IRQ070_Handler [WEAK]
|
||||
EXPORT IRQ071_Handler [WEAK]
|
||||
EXPORT IRQ072_Handler [WEAK]
|
||||
EXPORT IRQ073_Handler [WEAK]
|
||||
EXPORT IRQ074_Handler [WEAK]
|
||||
EXPORT IRQ075_Handler [WEAK]
|
||||
EXPORT IRQ076_Handler [WEAK]
|
||||
EXPORT IRQ077_Handler [WEAK]
|
||||
EXPORT IRQ078_Handler [WEAK]
|
||||
EXPORT IRQ079_Handler [WEAK]
|
||||
EXPORT IRQ080_Handler [WEAK]
|
||||
EXPORT IRQ081_Handler [WEAK]
|
||||
EXPORT IRQ082_Handler [WEAK]
|
||||
EXPORT IRQ083_Handler [WEAK]
|
||||
EXPORT IRQ084_Handler [WEAK]
|
||||
EXPORT IRQ085_Handler [WEAK]
|
||||
EXPORT IRQ086_Handler [WEAK]
|
||||
EXPORT IRQ087_Handler [WEAK]
|
||||
EXPORT IRQ088_Handler [WEAK]
|
||||
EXPORT IRQ089_Handler [WEAK]
|
||||
EXPORT IRQ090_Handler [WEAK]
|
||||
EXPORT IRQ091_Handler [WEAK]
|
||||
EXPORT IRQ092_Handler [WEAK]
|
||||
EXPORT IRQ093_Handler [WEAK]
|
||||
EXPORT IRQ094_Handler [WEAK]
|
||||
EXPORT IRQ095_Handler [WEAK]
|
||||
EXPORT IRQ096_Handler [WEAK]
|
||||
EXPORT IRQ097_Handler [WEAK]
|
||||
EXPORT IRQ098_Handler [WEAK]
|
||||
EXPORT IRQ099_Handler [WEAK]
|
||||
EXPORT IRQ100_Handler [WEAK]
|
||||
EXPORT IRQ101_Handler [WEAK]
|
||||
EXPORT IRQ102_Handler [WEAK]
|
||||
EXPORT IRQ103_Handler [WEAK]
|
||||
EXPORT IRQ104_Handler [WEAK]
|
||||
EXPORT IRQ105_Handler [WEAK]
|
||||
EXPORT IRQ106_Handler [WEAK]
|
||||
EXPORT IRQ107_Handler [WEAK]
|
||||
EXPORT IRQ108_Handler [WEAK]
|
||||
EXPORT IRQ109_Handler [WEAK]
|
||||
EXPORT IRQ110_Handler [WEAK]
|
||||
EXPORT IRQ111_Handler [WEAK]
|
||||
EXPORT IRQ112_Handler [WEAK]
|
||||
EXPORT IRQ113_Handler [WEAK]
|
||||
EXPORT IRQ114_Handler [WEAK]
|
||||
EXPORT IRQ115_Handler [WEAK]
|
||||
EXPORT IRQ116_Handler [WEAK]
|
||||
EXPORT IRQ117_Handler [WEAK]
|
||||
EXPORT IRQ118_Handler [WEAK]
|
||||
EXPORT IRQ119_Handler [WEAK]
|
||||
EXPORT IRQ120_Handler [WEAK]
|
||||
EXPORT IRQ121_Handler [WEAK]
|
||||
EXPORT IRQ122_Handler [WEAK]
|
||||
EXPORT IRQ123_Handler [WEAK]
|
||||
EXPORT IRQ124_Handler [WEAK]
|
||||
EXPORT IRQ125_Handler [WEAK]
|
||||
EXPORT IRQ126_Handler [WEAK]
|
||||
EXPORT IRQ127_Handler [WEAK]
|
||||
EXPORT IRQ128_Handler [WEAK]
|
||||
EXPORT IRQ129_Handler [WEAK]
|
||||
EXPORT IRQ130_Handler [WEAK]
|
||||
EXPORT IRQ131_Handler [WEAK]
|
||||
EXPORT IRQ132_Handler [WEAK]
|
||||
EXPORT IRQ133_Handler [WEAK]
|
||||
EXPORT IRQ134_Handler [WEAK]
|
||||
EXPORT IRQ135_Handler [WEAK]
|
||||
EXPORT IRQ136_Handler [WEAK]
|
||||
EXPORT IRQ137_Handler [WEAK]
|
||||
EXPORT IRQ138_Handler [WEAK]
|
||||
EXPORT IRQ139_Handler [WEAK]
|
||||
EXPORT IRQ140_Handler [WEAK]
|
||||
EXPORT IRQ141_Handler [WEAK]
|
||||
EXPORT IRQ142_Handler [WEAK]
|
||||
EXPORT IRQ143_Handler [WEAK]
|
||||
|
||||
IRQ000_Handler
|
||||
IRQ001_Handler
|
||||
IRQ002_Handler
|
||||
IRQ003_Handler
|
||||
IRQ004_Handler
|
||||
IRQ005_Handler
|
||||
IRQ006_Handler
|
||||
IRQ007_Handler
|
||||
IRQ008_Handler
|
||||
IRQ009_Handler
|
||||
IRQ010_Handler
|
||||
IRQ011_Handler
|
||||
IRQ012_Handler
|
||||
IRQ013_Handler
|
||||
IRQ014_Handler
|
||||
IRQ015_Handler
|
||||
IRQ016_Handler
|
||||
IRQ017_Handler
|
||||
IRQ018_Handler
|
||||
IRQ019_Handler
|
||||
IRQ020_Handler
|
||||
IRQ021_Handler
|
||||
IRQ022_Handler
|
||||
IRQ023_Handler
|
||||
IRQ024_Handler
|
||||
IRQ025_Handler
|
||||
IRQ026_Handler
|
||||
IRQ027_Handler
|
||||
IRQ028_Handler
|
||||
IRQ029_Handler
|
||||
IRQ030_Handler
|
||||
IRQ031_Handler
|
||||
IRQ032_Handler
|
||||
IRQ033_Handler
|
||||
IRQ034_Handler
|
||||
IRQ035_Handler
|
||||
IRQ036_Handler
|
||||
IRQ037_Handler
|
||||
IRQ038_Handler
|
||||
IRQ039_Handler
|
||||
IRQ040_Handler
|
||||
IRQ041_Handler
|
||||
IRQ042_Handler
|
||||
IRQ043_Handler
|
||||
IRQ044_Handler
|
||||
IRQ045_Handler
|
||||
IRQ046_Handler
|
||||
IRQ047_Handler
|
||||
IRQ048_Handler
|
||||
IRQ049_Handler
|
||||
IRQ050_Handler
|
||||
IRQ051_Handler
|
||||
IRQ052_Handler
|
||||
IRQ053_Handler
|
||||
IRQ054_Handler
|
||||
IRQ055_Handler
|
||||
IRQ056_Handler
|
||||
IRQ057_Handler
|
||||
IRQ058_Handler
|
||||
IRQ059_Handler
|
||||
IRQ060_Handler
|
||||
IRQ061_Handler
|
||||
IRQ062_Handler
|
||||
IRQ063_Handler
|
||||
IRQ064_Handler
|
||||
IRQ065_Handler
|
||||
IRQ066_Handler
|
||||
IRQ067_Handler
|
||||
IRQ068_Handler
|
||||
IRQ069_Handler
|
||||
IRQ070_Handler
|
||||
IRQ071_Handler
|
||||
IRQ072_Handler
|
||||
IRQ073_Handler
|
||||
IRQ074_Handler
|
||||
IRQ075_Handler
|
||||
IRQ076_Handler
|
||||
IRQ077_Handler
|
||||
IRQ078_Handler
|
||||
IRQ079_Handler
|
||||
IRQ080_Handler
|
||||
IRQ081_Handler
|
||||
IRQ082_Handler
|
||||
IRQ083_Handler
|
||||
IRQ084_Handler
|
||||
IRQ085_Handler
|
||||
IRQ086_Handler
|
||||
IRQ087_Handler
|
||||
IRQ088_Handler
|
||||
IRQ089_Handler
|
||||
IRQ090_Handler
|
||||
IRQ091_Handler
|
||||
IRQ092_Handler
|
||||
IRQ093_Handler
|
||||
IRQ094_Handler
|
||||
IRQ095_Handler
|
||||
IRQ096_Handler
|
||||
IRQ097_Handler
|
||||
IRQ098_Handler
|
||||
IRQ099_Handler
|
||||
IRQ100_Handler
|
||||
IRQ101_Handler
|
||||
IRQ102_Handler
|
||||
IRQ103_Handler
|
||||
IRQ104_Handler
|
||||
IRQ105_Handler
|
||||
IRQ106_Handler
|
||||
IRQ107_Handler
|
||||
IRQ108_Handler
|
||||
IRQ109_Handler
|
||||
IRQ110_Handler
|
||||
IRQ111_Handler
|
||||
IRQ112_Handler
|
||||
IRQ113_Handler
|
||||
IRQ114_Handler
|
||||
IRQ115_Handler
|
||||
IRQ116_Handler
|
||||
IRQ117_Handler
|
||||
IRQ118_Handler
|
||||
IRQ119_Handler
|
||||
IRQ120_Handler
|
||||
IRQ121_Handler
|
||||
IRQ122_Handler
|
||||
IRQ123_Handler
|
||||
IRQ124_Handler
|
||||
IRQ125_Handler
|
||||
IRQ126_Handler
|
||||
IRQ127_Handler
|
||||
IRQ128_Handler
|
||||
IRQ129_Handler
|
||||
IRQ130_Handler
|
||||
IRQ131_Handler
|
||||
IRQ132_Handler
|
||||
IRQ133_Handler
|
||||
IRQ134_Handler
|
||||
IRQ135_Handler
|
||||
IRQ136_Handler
|
||||
IRQ137_Handler
|
||||
IRQ138_Handler
|
||||
IRQ139_Handler
|
||||
IRQ140_Handler
|
||||
IRQ141_Handler
|
||||
IRQ142_Handler
|
||||
IRQ143_Handler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
@@ -0,0 +1,189 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file system_hc32f460.c
|
||||
* @brief This file provides two functions and two global variables to be called
|
||||
* from user application.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "system_hc32f460.h"
|
||||
#include "hc32f460.h"
|
||||
|
||||
/**
|
||||
* @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F460_System
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup HC32F460_System_Local_Macros HC32F460 System Local Macros
|
||||
* @{
|
||||
*/
|
||||
#define HRC_16MHz_VALUE (16000000UL) /*!< Internal high speed RC freq. */
|
||||
#define HRC_20MHz_VALUE (20000000UL) /*!< Internal high speed RC freq. */
|
||||
/* HRC select */
|
||||
#define HRC_FREQ_MON() (*((volatile uint32_t *)(0x40010684UL)))
|
||||
|
||||
/* Vector Table base offset field */
|
||||
#ifndef VECT_TAB_OFFSET
|
||||
#define VECT_TAB_OFFSET (0x0UL) /*!< This value must be a multiple of 0x400. */
|
||||
#endif
|
||||
/* Compiler Macros */
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__((section(".bss.noinit")))
|
||||
#endif /* __NO_INIT */
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /*!< GNU Compiler */
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__((section(".noinit")))
|
||||
#endif /* __NO_INIT */
|
||||
#elif defined (__ICCARM__) /*!< IAR Compiler */
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __no_init
|
||||
#endif /* __NO_INIT */
|
||||
#elif defined (__CC_ARM) /*!< ARM Compiler */
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__((section(".bss.noinit"), zero_init))
|
||||
#endif /* __NO_INIT */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F460_System_Global_Variable
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!< System clock frequency (Core clock) */
|
||||
__NO_INIT uint32_t SystemCoreClock;
|
||||
/*!< High speed RC frequency (HCR clock) */
|
||||
__NO_INIT uint32_t HRC_VALUE;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F460_System_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system. Initialize the System and update
|
||||
* the SystemCoreClock variable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings */
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 20) | (3UL << 22)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
SystemCoreClockUpdate();
|
||||
/* Configure the Vector Table relocation */
|
||||
SCB->VTOR = VECT_TAB_OFFSET; /* Vector Table Relocation */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint8_t u8SysClkSrc;
|
||||
uint32_t plln;
|
||||
uint32_t pllp;
|
||||
uint32_t pllm;
|
||||
uint32_t u32PllSrcFreq;
|
||||
|
||||
/* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */
|
||||
if (1UL == (HRC_FREQ_MON() & 1UL)) {
|
||||
HRC_VALUE = HRC_16MHz_VALUE;
|
||||
} else {
|
||||
HRC_VALUE = HRC_20MHz_VALUE;
|
||||
}
|
||||
u8SysClkSrc = CM_CMU->CKSWR & CMU_CKSWR_CKSW;
|
||||
switch (u8SysClkSrc) {
|
||||
case 0x00U: /* use internal high speed RC */
|
||||
SystemCoreClock = HRC_VALUE;
|
||||
break;
|
||||
case 0x01U: /* use internal middle speed RC */
|
||||
SystemCoreClock = MRC_VALUE;
|
||||
break;
|
||||
case 0x02U: /* use internal low speed RC */
|
||||
SystemCoreClock = LRC_VALUE;
|
||||
break;
|
||||
case 0x03U: /* use external high speed OSC */
|
||||
SystemCoreClock = XTAL_VALUE;
|
||||
break;
|
||||
case 0x04U: /* use external low speed OSC */
|
||||
SystemCoreClock = XTAL32_VALUE;
|
||||
break;
|
||||
case 0x05U: /* use MPLL */
|
||||
/* PLLCLK = ((pllsrc / pllm) * plln) / pllp */
|
||||
plln = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLN) >> CMU_PLLCFGR_MPLLN_POS;
|
||||
pllp = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLP) >> CMU_PLLCFGR_MPLLP_POS;
|
||||
pllm = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLM) >> CMU_PLLCFGR_MPLLM_POS;
|
||||
if (0UL == (CM_CMU->PLLCFGR & CMU_PLLCFGR_PLLSRC)) { /* use external highspeed OSC as PLL source */
|
||||
u32PllSrcFreq = XTAL_VALUE;
|
||||
} else { /* use internal high RC as PLL source */
|
||||
u32PllSrcFreq = HRC_VALUE;
|
||||
}
|
||||
SystemCoreClock = u32PllSrcFreq / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,189 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file system_hc32f460.c
|
||||
* @brief This file provides two functions and two global variables to be called
|
||||
* from user application.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "system_hc32f460.h"
|
||||
#include "hc32f460.h"
|
||||
|
||||
/**
|
||||
* @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F460_System
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup HC32F460_System_Local_Macros HC32F460 System Local Macros
|
||||
* @{
|
||||
*/
|
||||
#define HRC_16MHz_VALUE (16000000UL) /*!< Internal high speed RC freq. */
|
||||
#define HRC_20MHz_VALUE (20000000UL) /*!< Internal high speed RC freq. */
|
||||
/* HRC select */
|
||||
#define HRC_FREQ_MON() (*((volatile uint32_t *)(0x40010684UL)))
|
||||
|
||||
/* Vector Table base offset field */
|
||||
#ifndef VECT_TAB_OFFSET
|
||||
#define VECT_TAB_OFFSET (0x0UL) /*!< This value must be a multiple of 0x400. */
|
||||
#endif
|
||||
/* Compiler Macros */
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__((section(".bss.noinit")))
|
||||
#endif /* __NO_INIT */
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /*!< GNU Compiler */
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__((section(".noinit")))
|
||||
#endif /* __NO_INIT */
|
||||
#elif defined (__ICCARM__) /*!< IAR Compiler */
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __no_init
|
||||
#endif /* __NO_INIT */
|
||||
#elif defined (__CC_ARM) /*!< ARM Compiler */
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__((section(".bss.noinit"), zero_init))
|
||||
#endif /* __NO_INIT */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F460_System_Global_Variable
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!< System clock frequency (Core clock) */
|
||||
__NO_INIT uint32_t SystemCoreClock;
|
||||
/*!< High speed RC frequency (HCR clock) */
|
||||
__NO_INIT uint32_t HRC_VALUE;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F460_System_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system. Initialize the System and update
|
||||
* the SystemCoreClock variable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings */
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 20) | (3UL << 22)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
SystemCoreClockUpdate();
|
||||
/* Configure the Vector Table relocation */
|
||||
SCB->VTOR = VECT_TAB_OFFSET; /* Vector Table Relocation */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint8_t u8SysClkSrc;
|
||||
uint32_t plln;
|
||||
uint32_t pllp;
|
||||
uint32_t pllm;
|
||||
uint32_t u32PllSrcFreq;
|
||||
|
||||
/* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */
|
||||
if (1UL == (HRC_FREQ_MON() & 1UL)) {
|
||||
HRC_VALUE = HRC_16MHz_VALUE;
|
||||
} else {
|
||||
HRC_VALUE = HRC_20MHz_VALUE;
|
||||
}
|
||||
u8SysClkSrc = CM_CMU->CKSWR & CMU_CKSWR_CKSW;
|
||||
switch (u8SysClkSrc) {
|
||||
case 0x00U: /* use internal high speed RC */
|
||||
SystemCoreClock = HRC_VALUE;
|
||||
break;
|
||||
case 0x01U: /* use internal middle speed RC */
|
||||
SystemCoreClock = MRC_VALUE;
|
||||
break;
|
||||
case 0x02U: /* use internal low speed RC */
|
||||
SystemCoreClock = LRC_VALUE;
|
||||
break;
|
||||
case 0x03U: /* use external high speed OSC */
|
||||
SystemCoreClock = XTAL_VALUE;
|
||||
break;
|
||||
case 0x04U: /* use external low speed OSC */
|
||||
SystemCoreClock = XTAL32_VALUE;
|
||||
break;
|
||||
case 0x05U: /* use MPLL */
|
||||
/* PLLCLK = ((pllsrc / pllm) * plln) / pllp */
|
||||
plln = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLN) >> CMU_PLLCFGR_MPLLN_POS;
|
||||
pllp = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLP) >> CMU_PLLCFGR_MPLLP_POS;
|
||||
pllm = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLM) >> CMU_PLLCFGR_MPLLM_POS;
|
||||
if (0UL == (CM_CMU->PLLCFGR & CMU_PLLCFGR_PLLSRC)) { /* use external highspeed OSC as PLL source */
|
||||
u32PllSrcFreq = XTAL_VALUE;
|
||||
} else { /* use internal high RC as PLL source */
|
||||
u32PllSrcFreq = HRC_VALUE;
|
||||
}
|
||||
SystemCoreClock = u32PllSrcFreq / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,134 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file system_hc32f460.h
|
||||
* @brief This file contains all the functions prototypes of the HC32 System.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __SYSTEM_HC32F460_H__
|
||||
#define __SYSTEM_HC32F460_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <stdint.h>
|
||||
|
||||
/**
|
||||
* @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F460_System
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F460_System_Global_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F460_System_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#if !defined (MRC_VALUE)
|
||||
#define MRC_VALUE (8000000UL) /*!< Internal middle speed RC freq. */
|
||||
#endif
|
||||
|
||||
#if !defined (LRC_VALUE)
|
||||
#define LRC_VALUE (32768UL) /*!< Internal low speed RC freq. */
|
||||
#endif
|
||||
|
||||
#if !defined (SWDTLRC_VALUE)
|
||||
#define SWDTLRC_VALUE (10000UL) /*!< Internal SWDT low speed RC freq. */
|
||||
#endif
|
||||
|
||||
#if !defined (XTAL_VALUE)
|
||||
#define XTAL_VALUE (8000000UL) /*!< External high speed OSC freq. */
|
||||
#endif
|
||||
|
||||
#if !defined (XTAL32_VALUE)
|
||||
#define XTAL32_VALUE (32768UL) /*!< External low speed OSC freq. */
|
||||
#endif
|
||||
|
||||
#if !defined (HCLK_VALUE)
|
||||
#define HCLK_VALUE (SystemCoreClock >> ((CM_CMU->SCFGR & CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F460_System_Exported_Variable
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System clock frequency (Core clock) */
|
||||
extern uint32_t HRC_VALUE; /*!< HRC frequency */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F460_System_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void); /*!< Initialize the system */
|
||||
extern void SystemCoreClockUpdate(void); /*!< Update SystemCoreClock variable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_HC32F460_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,134 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file system_hc32f460.h
|
||||
* @brief This file contains all the functions prototypes of the HC32 System.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __SYSTEM_HC32F460_H__
|
||||
#define __SYSTEM_HC32F460_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <stdint.h>
|
||||
|
||||
/**
|
||||
* @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F460_System
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F460_System_Global_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F460_System_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#if !defined (MRC_VALUE)
|
||||
#define MRC_VALUE (8000000UL) /*!< Internal middle speed RC freq. */
|
||||
#endif
|
||||
|
||||
#if !defined (LRC_VALUE)
|
||||
#define LRC_VALUE (32768UL) /*!< Internal low speed RC freq. */
|
||||
#endif
|
||||
|
||||
#if !defined (SWDTLRC_VALUE)
|
||||
#define SWDTLRC_VALUE (10000UL) /*!< Internal SWDT low speed RC freq. */
|
||||
#endif
|
||||
|
||||
#if !defined (XTAL_VALUE)
|
||||
#define XTAL_VALUE (8000000UL) /*!< External high speed OSC freq. */
|
||||
#endif
|
||||
|
||||
#if !defined (XTAL32_VALUE)
|
||||
#define XTAL32_VALUE (32768UL) /*!< External low speed OSC freq. */
|
||||
#endif
|
||||
|
||||
#if !defined (HCLK_VALUE)
|
||||
#define HCLK_VALUE (SystemCoreClock >> ((CM_CMU->SCFGR & CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F460_System_Exported_Variable
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System clock frequency (Core clock) */
|
||||
extern uint32_t HRC_VALUE; /*!< HRC frequency */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F460_System_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void); /*!< Initialize the system */
|
||||
extern void SystemCoreClockUpdate(void); /*!< Update SystemCoreClock variable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_HC32F460_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,78 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::File System
|
||||
* Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: FS_Config.c
|
||||
* Purpose: File System Configuration
|
||||
* Rev.: V6.3.0
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>FAT File System
|
||||
// <i>Define FAT File System parameters
|
||||
|
||||
// <o>Number of open files <1-16>
|
||||
// <i>Define number of files that can be opened at the same time.
|
||||
// <i>Default: 4
|
||||
#define FAT_MAX_OPEN_FILES 4
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Embedded File System
|
||||
// <i>Define Embedded File System parameters
|
||||
|
||||
// <o>Number of open files <1-16>
|
||||
// <i>Define number of files that can be opened at the same time.
|
||||
// <i>Default: 4
|
||||
#define EFS_MAX_OPEN_FILES 4
|
||||
|
||||
// </h>
|
||||
|
||||
// <o>Initial Current Drive <0=>F0: <1=>F1:
|
||||
// <2=>M0: <3=>M1:
|
||||
// <4=>N0: <5=>N1:
|
||||
// <6=>R0: <9=>R1:
|
||||
// <7=>U0: <8=>U1:
|
||||
// <i>Set initial setting for current drive. Current drive is used for File System functions
|
||||
// <i>that are invoked with the "" string and can be altered anytime during run-time.
|
||||
#define FS_INITIAL_CDRIVE 2
|
||||
|
||||
#include "RTE_Components.h"
|
||||
|
||||
#ifdef RTE_FileSystem_Drive_RAM_0
|
||||
#include "FS_Config_RAM_0.h"
|
||||
#endif
|
||||
#ifdef RTE_FileSystem_Drive_RAM_1
|
||||
#include "FS_Config_RAM_1.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_FileSystem_Drive_NOR_0
|
||||
#include "FS_Config_NOR_0.h"
|
||||
#endif
|
||||
#ifdef RTE_FileSystem_Drive_NOR_1
|
||||
#include "FS_Config_NOR_1.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_FileSystem_Drive_NAND_0
|
||||
#include "FS_Config_NAND_0.h"
|
||||
#endif
|
||||
#ifdef RTE_FileSystem_Drive_NAND_1
|
||||
#include "FS_Config_NAND_1.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_FileSystem_Drive_MC_0
|
||||
#include "FS_Config_MC_0.h"
|
||||
#endif
|
||||
#ifdef RTE_FileSystem_Drive_MC_1
|
||||
#include "FS_Config_MC_1.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_FileSystem_Drive_USB_0
|
||||
#include "FS_Config_USB_0.h"
|
||||
#endif
|
||||
#ifdef RTE_FileSystem_Drive_USB_1
|
||||
#include "FS_Config_USB_1.h"
|
||||
#endif
|
||||
|
||||
#include "fs_config.h"
|
||||
@@ -0,0 +1,55 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::File System:Drive
|
||||
* Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: FS_Config_MC_0.h
|
||||
* Purpose: File System Configuration for Memory Card Drive
|
||||
* Rev.: V6.2.0
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>Memory Card Drive 0
|
||||
// <i>Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:"
|
||||
#define MC0_ENABLE 1
|
||||
|
||||
// <o>Connect to hardware via Driver_MCI# <0-255>
|
||||
// <i>Select driver control block for hardware interface
|
||||
#define MC0_MCI_DRIVER 0
|
||||
|
||||
// <o>Connect to hardware via Driver_SPI# <0-255>
|
||||
// <i>Select driver control block for hardware interface when in SPI mode
|
||||
#define MC0_SPI_DRIVER 0
|
||||
|
||||
// <o>Memory Card Interface Mode <0=>Native <1=>SPI
|
||||
// <i>Native uses a SD Bus with up to 8 data lines, CLK, and CMD
|
||||
// <i>SPI uses 2 data lines (MOSI and MISO), SCLK and CS
|
||||
#define MC0_SPI 0
|
||||
|
||||
// <o>Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
|
||||
// <8=>8 KB <16=>16 KB <32=>32 KB
|
||||
// <i>Drive Cache stores data sectors and may be increased to speed-up
|
||||
// <i>file read/write operations on this drive (default: 4 KB)
|
||||
#define MC0_CACHE_SIZE 4
|
||||
|
||||
// <e>Locate Drive Cache and Drive Buffer
|
||||
// <i>Some microcontrollers support DMA only in specific memory areas and
|
||||
// <i>require to locate the drive buffers at a fixed address.
|
||||
#define MC0_CACHE_RELOC 0
|
||||
|
||||
// <o>Base address <0x0000-0xFFFFFE00:0x200>
|
||||
// <i>Set buffer base address to RAM areas that support DMA with the drive.
|
||||
#define MC0_CACHE_ADDR 0x7FD00000
|
||||
|
||||
// </e>
|
||||
// <o>Filename Cache Size <0-1000000>
|
||||
// <i>Define number of cached file or directory names.
|
||||
// <i>48 bytes of RAM is required for each cached name.
|
||||
#define MC0_NAME_CACHE_SIZE 0
|
||||
|
||||
// <q>Use FAT Journal
|
||||
// <i>Protect File Allocation Table and Directory Entries for
|
||||
// <i>fail-safe operation.
|
||||
#define MC0_FAT_JOURNAL 0
|
||||
|
||||
// </h>
|
||||
@@ -0,0 +1,50 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::File System
|
||||
* Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: FS_Debug.c
|
||||
* Purpose: File System Debug Configuration
|
||||
* Rev.: V1.0.0
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <e>File System Debug
|
||||
// <i>Enable File System event recording
|
||||
#define FS_DEBUG_EVR_ENABLE 0
|
||||
|
||||
// <o>Core Management <0=>Off <1=>Errors <2=>Errors + API <3=>All
|
||||
// <i>Configure FsCore: Core Management event recording
|
||||
#define FS_DEBUG_EVR_CORE 1
|
||||
|
||||
// <o>FAT File System <0=>Off <1=>Errors <2=>Errors + API <3=>All
|
||||
// <i>Configure FsFAT: FAT File System event recording
|
||||
#define FS_DEBUG_EVR_FAT 1
|
||||
|
||||
// <o>EFS File System <0=>Off <1=>Errors <2=>Errors + API <3=>All
|
||||
// <i>Configure FsEFS: EFS File System event recording
|
||||
#define FS_DEBUG_EVR_EFS 1
|
||||
|
||||
// <o>I/O Control Interface <0=>Off <1=>Errors <2=>Errors + API <3=>All
|
||||
// <i>Configure FsIOC: I/O Control Interface event recording
|
||||
#define FS_DEBUG_EVR_IOC 1
|
||||
|
||||
// <o>NAND Flash Translation Layer <0=>Off <1=>Errors <2=>Errors + API <3=>All
|
||||
// <i>Configure FsNFTL: NAND Flash Translation Layer event recording
|
||||
#define FS_DEBUG_EVR_NFTL 1
|
||||
|
||||
// <o>NAND Device Interface <0=>Off <1=>Errors <2=>Errors + API <3=>All
|
||||
// <i>Configure FsNAND: NAND Device Interface event recording
|
||||
#define FS_DEBUG_EVR_NAND 1
|
||||
|
||||
// <o>Memory Card MCI <0=>Off <1=>Errors <2=>Errors + API <3=>All
|
||||
// <i>Configure FsMcMCI: Memory Card MCI event recording
|
||||
#define FS_DEBUG_EVR_MC_MCI 1
|
||||
|
||||
// <o>Memory Card SPI <0=>Off <1=>Errors <2=>Errors + API <3=>All
|
||||
// <i>Configure FsMcSPI: Memory Card SPI event recording
|
||||
#define FS_DEBUG_EVR_MC_SPI 1
|
||||
|
||||
// </e>
|
||||
|
||||
#include "fs_debug.h"
|
||||
@@ -0,0 +1,173 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::Network
|
||||
* Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: Net_Config.c
|
||||
* Purpose: Network Configuration
|
||||
* Rev.: V7.1.0
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>Network System Settings
|
||||
// <i>Global Network System definitions
|
||||
// <s.15>Local Host Name
|
||||
// <i>This is the name under which embedded host can be
|
||||
// <i>accessed on a local area network.
|
||||
// <i>Default: "my_host"
|
||||
#define NET_HOST_NAME "my_host"
|
||||
|
||||
// <o>Memory Pool Size <1536-262144:4>
|
||||
// <i>This is the size of a memory pool in bytes. Buffers for
|
||||
// <i>network packets are allocated from this memory pool.
|
||||
// <i>Default: 12000 bytes
|
||||
#define NET_MEM_POOL_SIZE 12000
|
||||
|
||||
// <q>Start System Services
|
||||
// <i>If enabled, the system will automatically start server services
|
||||
// <i>(HTTP, FTP, TFTP server, ...) when initializing the network system.
|
||||
// <i>Default: Enabled
|
||||
#define NET_START_SERVICE 1
|
||||
|
||||
// <h>OS Resource Settings
|
||||
// <i>These settings are used to optimize usage of OS resources.
|
||||
// <o>Core Thread Stack Size <512-65535:4>
|
||||
// <i>Default: 1024 bytes
|
||||
#define NET_THREAD_STACK_SIZE 1024
|
||||
|
||||
// Core Thread Priority
|
||||
#define NET_THREAD_PRIORITY osPriorityNormal
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
//------------- <<< end of configuration section >>> ---------------------------
|
||||
|
||||
#include "RTE_Components.h"
|
||||
|
||||
#ifdef RTE_Network_Interface_ETH_0
|
||||
#include "Net_Config_ETH_0.h"
|
||||
#endif
|
||||
#ifdef RTE_Network_Interface_ETH_1
|
||||
#include "Net_Config_ETH_1.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_Interface_WiFi_0
|
||||
#include "Net_Config_WiFi_0.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_Interface_WiFi_1
|
||||
#include "Net_Config_WiFi_1.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_Interface_PPP
|
||||
#include "Net_Config_PPP.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_Interface_SLIP
|
||||
#include "Net_Config_SLIP.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_Socket_UDP
|
||||
#include "Net_Config_UDP.h"
|
||||
#endif
|
||||
#ifdef RTE_Network_Socket_TCP
|
||||
#include "Net_Config_TCP.h"
|
||||
#endif
|
||||
#ifdef RTE_Network_Socket_BSD
|
||||
#include "Net_Config_BSD.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_Web_Server_RO
|
||||
#include "Net_Config_HTTP_Server.h"
|
||||
#endif
|
||||
#ifdef RTE_Network_Web_Server_FS
|
||||
#include "Net_Config_HTTP_Server.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_Telnet_Server
|
||||
#include "Net_Config_Telnet_Server.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_TFTP_Server
|
||||
#include "Net_Config_TFTP_Server.h"
|
||||
#endif
|
||||
#ifdef RTE_Network_TFTP_Client
|
||||
#include "Net_Config_TFTP_Client.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_FTP_Server
|
||||
#include "Net_Config_FTP_Server.h"
|
||||
#endif
|
||||
#ifdef RTE_Network_FTP_Client
|
||||
#include "Net_Config_FTP_Client.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_DNS_Client
|
||||
#include "Net_Config_DNS_Client.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_SMTP_Client
|
||||
#include "Net_Config_SMTP_Client.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_SNMP_Agent
|
||||
#include "Net_Config_SNMP_Agent.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_Network_SNTP_Client
|
||||
#include "Net_Config_SNTP_Client.h"
|
||||
#endif
|
||||
|
||||
#include "net_config.h"
|
||||
|
||||
/**
|
||||
\addtogroup net_genFunc
|
||||
@{
|
||||
*/
|
||||
/**
|
||||
\fn void net_sys_error (NET_ERROR error)
|
||||
\ingroup net_cores
|
||||
\brief Network system error handler.
|
||||
*/
|
||||
void net_sys_error (NET_ERROR error) {
|
||||
/* This function is called when a fatal error is encountered. */
|
||||
/* The normal program execution is not possible anymore. */
|
||||
|
||||
switch (error) {
|
||||
case NET_ERROR_MEM_ALLOC:
|
||||
/* Out of memory */
|
||||
break;
|
||||
|
||||
case NET_ERROR_MEM_FREE:
|
||||
/* Trying to release non existing memory block */
|
||||
break;
|
||||
|
||||
case NET_ERROR_MEM_CORRUPT:
|
||||
/* Memory Link pointer corrupted */
|
||||
/* More data written than the size of allocated memory block */
|
||||
break;
|
||||
|
||||
case NET_ERROR_CONFIG:
|
||||
/* Network configuration error detected */
|
||||
break;
|
||||
|
||||
case NET_ERROR_UDP_ALLOC:
|
||||
/* Out of UDP Sockets */
|
||||
break;
|
||||
|
||||
case NET_ERROR_TCP_ALLOC:
|
||||
/* Out of TCP Sockets */
|
||||
break;
|
||||
|
||||
case NET_ERROR_TCP_STATE:
|
||||
/* TCP State machine in undefined state */
|
||||
break;
|
||||
}
|
||||
|
||||
/* End-less loop */
|
||||
while (1);
|
||||
}
|
||||
/**
|
||||
@}
|
||||
*/
|
||||
@@ -0,0 +1,253 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::Network:Interface
|
||||
* Copyright (c) 2004-2020 Arm Limited (or its affiliates). All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: Net_Config_ETH_0.h
|
||||
* Purpose: Network Configuration for ETH Interface
|
||||
* Rev.: V7.3.0
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>Ethernet Network Interface 0
|
||||
#define ETH0_ENABLE 1
|
||||
|
||||
// <o>Connect to hardware via Driver_ETH# <0-255>
|
||||
// <i>Select driver control block for MAC and PHY interface
|
||||
#define ETH0_DRIVER 0
|
||||
|
||||
// <s.17>MAC Address
|
||||
// <i>Ethernet MAC Address in text representation
|
||||
// <i>Value FF-FF-FF-FF-FF-FF is not allowed,
|
||||
// <i>LSB of first byte must be 0 (an ethernet Multicast bit).
|
||||
// <i>Default: "1E-30-6C-A2-45-5E"
|
||||
#define ETH0_MAC_ADDR "1E-30-6C-A2-45-5E"
|
||||
|
||||
// <e>VLAN
|
||||
// <i>Enable or disable Virtual LAN
|
||||
#define ETH0_VLAN_ENABLE 0
|
||||
|
||||
// <o>VLAN Identifier <1-4093>
|
||||
// <i>A unique 12-bit numeric value
|
||||
// <i>Default: 1
|
||||
#define ETH0_VLAN_ID 1
|
||||
// </e>
|
||||
|
||||
// <e>IPv4
|
||||
// <i>Enable IPv4 Protocol for Network Interface
|
||||
#define ETH0_IP4_ENABLE 1
|
||||
|
||||
// <s.15>IP Address
|
||||
// <i>Static IPv4 Address in text representation
|
||||
// <i>Default: "192.168.0.100"
|
||||
#define ETH0_IP4_ADDR "192.168.0.100"
|
||||
|
||||
// <s.15>Subnet mask
|
||||
// <i>Local Subnet mask in text representation
|
||||
// <i>Default: "255.255.255.0"
|
||||
#define ETH0_IP4_MASK "255.255.255.0"
|
||||
|
||||
// <s.15>Default Gateway
|
||||
// <i>IP Address of Default Gateway in text representation
|
||||
// <i>Default: "192.168.0.254"
|
||||
#define ETH0_IP4_GATEWAY "192.168.0.254"
|
||||
|
||||
// <s.15>Primary DNS Server
|
||||
// <i>IP Address of Primary DNS Server in text representation
|
||||
// <i>Default: "8.8.8.8"
|
||||
#define ETH0_IP4_PRIMARY_DNS "8.8.8.8"
|
||||
|
||||
// <s.15>Secondary DNS Server
|
||||
// <i>IP Address of Secondary DNS Server in text representation
|
||||
// <i>Default: "8.8.4.4"
|
||||
#define ETH0_IP4_SECONDARY_DNS "8.8.4.4"
|
||||
|
||||
// <e>IP Fragmentation
|
||||
// <i>This option enables fragmentation of outgoing IP datagrams,
|
||||
// <i>and reassembling the fragments of incoming IP datagrams.
|
||||
// <i>Default: enabled
|
||||
#define ETH0_IP4_FRAG_ENABLE 1
|
||||
|
||||
// <o>MTU size <576-1500>
|
||||
// <i>Maximum Transmission Unit in bytes
|
||||
// <i>Default: 1500
|
||||
#define ETH0_IP4_MTU 1500
|
||||
// </e>
|
||||
|
||||
// <h>ARP Address Resolution
|
||||
// <i>ARP cache and node address resolver settings
|
||||
// <o>Cache Table size <5-100>
|
||||
// <i>Number of cached MAC/IP addresses
|
||||
// <i>Default: 10
|
||||
#define ETH0_ARP_TAB_SIZE 10
|
||||
|
||||
// <o>Cache Timeout in seconds <5-255>
|
||||
// <i>A timeout for cached hardware/IP addresses
|
||||
// <i>Default: 150
|
||||
#define ETH0_ARP_CACHE_TOUT 150
|
||||
|
||||
// <o>Number of Retries <0-20>
|
||||
// <i>Number of Retries to resolve an IP address
|
||||
// <i>before ARP module gives up
|
||||
// <i>Default: 4
|
||||
#define ETH0_ARP_MAX_RETRY 4
|
||||
|
||||
// <o>Resend Timeout in seconds <1-10>
|
||||
// <i>A timeout to resend the ARP Request
|
||||
// <i>Default: 2
|
||||
#define ETH0_ARP_RESEND_TOUT 2
|
||||
|
||||
// <q>Send Notification on Address changes
|
||||
// <i>When this option is enabled, the embedded host
|
||||
// <i>will send a Gratuitous ARP notification at startup,
|
||||
// <i>or when the device IP address has changed.
|
||||
// <i>Default: Disabled
|
||||
#define ETH0_ARP_NOTIFY 0
|
||||
// </h>
|
||||
|
||||
// <e>IGMP Group Management
|
||||
// <i>Enable or disable Internet Group Management Protocol
|
||||
#define ETH0_IGMP_ENABLE 0
|
||||
|
||||
// <o>Membership Table size <2-50>
|
||||
// <i>Number of Groups this host can join
|
||||
// <i>Default: 5
|
||||
#define ETH0_IGMP_TAB_SIZE 5
|
||||
// </e>
|
||||
|
||||
// <q>NetBIOS Name Service
|
||||
// <i>When this option is enabled, the embedded host can be
|
||||
// <i>accessed by its name on local LAN using NBNS protocol.
|
||||
#define ETH0_NBNS_ENABLE 1
|
||||
|
||||
// <e>Dynamic Host Configuration
|
||||
// <i>When this option is enabled, local IP address, Net Mask
|
||||
// <i>and Default Gateway are obtained automatically from
|
||||
// <i>the DHCP Server on local LAN.
|
||||
#define ETH0_DHCP_ENABLE 1
|
||||
|
||||
// <s.40>Vendor Class Identifier
|
||||
// <i>This value is optional. If specified, it is added
|
||||
// <i>to DHCP request message, identifying vendor type.
|
||||
// <i>Default: ""
|
||||
#define ETH0_DHCP_VCID ""
|
||||
|
||||
// <q>Bootfile Name
|
||||
// <i>This value is optional. If enabled, the Bootfile Name
|
||||
// <i>(option 67) is also requested from DHCP server.
|
||||
// <i>Default: disabled
|
||||
#define ETH0_DHCP_BOOTFILE 0
|
||||
|
||||
// <q>NTP Servers
|
||||
// <i>This value is optional. If enabled, a list of NTP Servers
|
||||
// <i>(option 42) is also requested from DHCP server.
|
||||
// <i>Default: disabled
|
||||
#define ETH0_DHCP_NTP_SERVERS 0
|
||||
// </e>
|
||||
|
||||
// Disable ICMP Echo response
|
||||
#define ETH0_ICMP_NO_ECHO 0
|
||||
// </e>
|
||||
|
||||
// <e>IPv6
|
||||
// <i>Enable IPv6 Protocol for Network Interface
|
||||
#define ETH0_IP6_ENABLE 1
|
||||
|
||||
// <s.40>IPv6 Address
|
||||
// <i>Static IPv6 Address in text representation
|
||||
// <i>Use unspecified address "::" when static
|
||||
// <i>IPv6 address is not used.
|
||||
// <i>Default: "fec0::2"
|
||||
#define ETH0_IP6_ADDR "fec0::2"
|
||||
|
||||
// <o>Subnet prefix-length <1-128>
|
||||
// <i>Number of bits that define network address
|
||||
// <i>Default: 64
|
||||
#define ETH0_IP6_PREFIX_LEN 64
|
||||
|
||||
// <s.40>Default Gateway
|
||||
// <i>Default Gateway IPv6 Address in text representation
|
||||
// <i>Default: "fec0::1"
|
||||
#define ETH0_IP6_GATEWAY "fec0::1"
|
||||
|
||||
// <s.40>Primary DNS Server
|
||||
// <i>Primary DNS Server IPv6 Address in text representation
|
||||
// <i>Default: "2001:4860:4860::8888"
|
||||
#define ETH0_IP6_PRIMARY_DNS "2001:4860:4860::8888"
|
||||
|
||||
// <s.40>Secondary DNS Server
|
||||
// <i>Secondary DNS Server IPv6 Address in text representation
|
||||
// <i>Default: "2001:4860:4860::8844"
|
||||
#define ETH0_IP6_SECONDARY_DNS "2001:4860:4860::8844"
|
||||
|
||||
// <h>Neighbor Discovery
|
||||
// <i>Neighbor cache and node address resolver settings
|
||||
// <o>Cache Table size <5-100>
|
||||
// <i>Number of cached node addresses
|
||||
// <i>Default: 5
|
||||
#define ETH0_NDP_TAB_SIZE 5
|
||||
|
||||
// <o>Cache Timeout in seconds <5-255>
|
||||
// <i>Timeout for cached node addresses
|
||||
// <i>Default: 150
|
||||
#define ETH0_NDP_CACHE_TOUT 150
|
||||
|
||||
// <o>Number of Retries <0-20>
|
||||
// <i>Number of retries to resolve an IP address
|
||||
// <i>before NDP module gives up
|
||||
// <i>Default: 4
|
||||
#define ETH0_NDP_MAX_RETRY 4
|
||||
|
||||
// <o>Resend Timeout in seconds <1-10>
|
||||
// <i>A timeout to resend Neighbor Solicitation
|
||||
// <i>Default: 2
|
||||
#define ETH0_NDP_RESEND_TOUT 2
|
||||
// </h>
|
||||
|
||||
// <e>Dynamic Host Configuration
|
||||
// <i>When this option is enabled, local IPv6 address is
|
||||
// <i>automatically configured.
|
||||
#define ETH0_DHCP6_ENABLE 1
|
||||
|
||||
// <o>DHCPv6 Client Mode <0=>Stateless Mode <1=>Statefull Mode
|
||||
// <i>Stateless DHCPv6 Client uses router advertisements
|
||||
// <i>for IPv6 address autoconfiguration (SLAAC).
|
||||
// <i>Statefull DHCPv6 Client connects to DHCPv6 server for a
|
||||
// <i>leased IPv6 address and DNS server IPv6 addresses.
|
||||
#define ETH0_DHCP6_MODE 1
|
||||
|
||||
// <e>Vendor Class Option
|
||||
// <i>If enabled, Vendor Class option is added to DHCPv6
|
||||
// <i>request message, identifying vendor type.
|
||||
// <i>Default: disabled
|
||||
#define ETH0_DHCP6_VCLASS_ENABLE 0
|
||||
|
||||
// <o>Enterprise ID
|
||||
// <i>Enterprise-number as registered with IANA.
|
||||
// <i>Default: 0 (Reserved)
|
||||
#define ETH0_DHCP6_VCLASS_EID 0
|
||||
|
||||
// <s.40>Vendor Class Data
|
||||
// <i>This string identifies vendor type.
|
||||
// <i>Default: ""
|
||||
#define ETH0_DHCP6_VCLASS_DATA ""
|
||||
// </e>
|
||||
// </e>
|
||||
|
||||
// Disable ICMP6 Echo response
|
||||
#define ETH0_ICMP6_NO_ECHO 0
|
||||
// </e>
|
||||
|
||||
// <h>OS Resource Settings
|
||||
// <i>These settings are used to optimize usage of OS resources.
|
||||
// <o>Interface Thread Stack Size <512-65535:4>
|
||||
// <i>Default: 512 bytes
|
||||
#define ETH0_THREAD_STACK_SIZE 512
|
||||
|
||||
// Interface Thread Priority
|
||||
#define ETH0_THREAD_PRIORITY osPriorityAboveNormal
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
//------------- <<< end of configuration section >>> ---------------------------
|
||||
@@ -0,0 +1,69 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::Network:Socket
|
||||
* Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: Net_Config_TCP.h
|
||||
* Purpose: Network Configuration for TCP Sockets
|
||||
* Rev.: V7.1.1
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>TCP Sockets
|
||||
#define TCP_ENABLE 1
|
||||
|
||||
// <o>Number of TCP Sockets <1-20>
|
||||
// <i>Number of available TCP sockets
|
||||
// <i>Default: 6
|
||||
#define TCP_NUM_SOCKS 6
|
||||
|
||||
// <o>Number of Retries <0-20>
|
||||
// <i>How many times TCP module will try to retransmit data
|
||||
// <i>before giving up. Increase this value for high-latency
|
||||
// <i>and low throughput networks.
|
||||
// <i>Default: 5
|
||||
#define TCP_MAX_RETRY 5
|
||||
|
||||
// <o>Retry Timeout in seconds <1-10>
|
||||
// <i>If data frame not acknowledged within this time frame,
|
||||
// <i>TCP module will try to resend the data again.
|
||||
// <i>Default: 4
|
||||
#define TCP_RETRY_TOUT 4
|
||||
|
||||
// <o>Default Connect Timeout in seconds <1-65535>
|
||||
// <i>If no TCP data frame has been exchanged during this time,
|
||||
// <i>the TCP connection is either closed or a keep-alive frame
|
||||
// <i>is sent to verify that the connection still exists.
|
||||
// <i>Default: 120
|
||||
#define TCP_DEFAULT_TOUT 120
|
||||
|
||||
// <o>Maximum Segment Size <536-1440>
|
||||
// <i>The Maximum Segment Size specifies the maximum
|
||||
// <i>number of bytes in the TCP segment's Data field.
|
||||
// <i>Default: 1440
|
||||
#define TCP_MAX_SEG_SIZE 1440
|
||||
|
||||
// <o>Receive Window Size <536-65535>
|
||||
// <i>Receive Window Size specifies the size of data,
|
||||
// <i>that the socket is able to buffer in flow-control mode.
|
||||
// <i>Default: 4320
|
||||
#define TCP_RECEIVE_WIN_SIZE 4320
|
||||
|
||||
// </h>
|
||||
|
||||
// TCP Initial Retransmit period in seconds
|
||||
#define TCP_INITIAL_RETRY_TOUT 1
|
||||
|
||||
// TCP SYN frame retransmit period in seconds
|
||||
#define TCP_SYN_RETRY_TOUT 2
|
||||
|
||||
// Number of retries to establish a connection
|
||||
#define TCP_CONNECT_RETRY 7
|
||||
|
||||
// Dynamic port start (default 49152)
|
||||
#define TCP_DYN_PORT_START 49152
|
||||
|
||||
// Dynamic port end (default 65535)
|
||||
#define TCP_DYN_PORT_END 65535
|
||||
|
||||
//------------- <<< end of configuration section >>> ---------------------------
|
||||
@@ -0,0 +1,90 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-05-24 the first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "bsp.h"
|
||||
|
||||
#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
|
||||
/*
|
||||
* Please modify RT_HEAP_SIZE if you enable RT_USING_HEAP
|
||||
* the RT_HEAP_SIZE max value = (sram size - ZI size), 1024 means 1024 bytes
|
||||
*/
|
||||
#define RT_HEAP_SIZE (32*1024)
|
||||
static rt_uint8_t rt_heap[RT_HEAP_SIZE];
|
||||
|
||||
RT_WEAK void *rt_heap_begin_get(void)
|
||||
{
|
||||
return rt_heap;
|
||||
}
|
||||
|
||||
RT_WEAK void *rt_heap_end_get(void)
|
||||
{
|
||||
return rt_heap + RT_HEAP_SIZE;
|
||||
}
|
||||
#endif
|
||||
|
||||
void rt_os_tick_callback(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void SysTick_IrqHandler(void)
|
||||
{
|
||||
rt_os_tick_callback();
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initial your board.
|
||||
*/
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
//#error "TODO 1: OS Tick Configuration."
|
||||
BSP_Init();
|
||||
/*
|
||||
* TODO 1: OS Tick Configuration
|
||||
* Enable the hardware timer and call the rt_os_tick_callback function
|
||||
* periodically with the frequency RT_TICK_PER_SECOND.
|
||||
*/
|
||||
|
||||
/* Call components board initial (use INIT_BOARD_EXPORT()) */
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
|
||||
rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get());
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef RT_USING_CONSOLE
|
||||
|
||||
static int uart_init(void)
|
||||
{
|
||||
//#error "TODO 2: Enable the hardware uart and config baudrate."
|
||||
DbgUart_Config(500000);
|
||||
return 0;
|
||||
}
|
||||
INIT_BOARD_EXPORT(uart_init);
|
||||
|
||||
void rt_hw_console_output(const char *str)
|
||||
{
|
||||
//#error "TODO 3: Output the string 'str' through the uart."
|
||||
rt_enter_critical();
|
||||
DebugUartSend((uint8_t *)str, strlen(str));
|
||||
rt_exit_critical();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,79 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-05-24 the first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
|
||||
/*
|
||||
* Please modify RT_HEAP_SIZE if you enable RT_USING_HEAP
|
||||
* the RT_HEAP_SIZE max value = (sram size - ZI size), 1024 means 1024 bytes
|
||||
*/
|
||||
#define RT_HEAP_SIZE (15*1024)
|
||||
static rt_uint8_t rt_heap[RT_HEAP_SIZE];
|
||||
|
||||
RT_WEAK void *rt_heap_begin_get(void)
|
||||
{
|
||||
return rt_heap;
|
||||
}
|
||||
|
||||
RT_WEAK void *rt_heap_end_get(void)
|
||||
{
|
||||
return rt_heap + RT_HEAP_SIZE;
|
||||
}
|
||||
#endif
|
||||
|
||||
void rt_os_tick_callback(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initial your board.
|
||||
*/
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
#error "TODO 1: OS Tick Configuration."
|
||||
/*
|
||||
* TODO 1: OS Tick Configuration
|
||||
* Enable the hardware timer and call the rt_os_tick_callback function
|
||||
* periodically with the frequency RT_TICK_PER_SECOND.
|
||||
*/
|
||||
|
||||
/* Call components board initial (use INIT_BOARD_EXPORT()) */
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
|
||||
rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get());
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef RT_USING_CONSOLE
|
||||
|
||||
static int uart_init(void)
|
||||
{
|
||||
#error "TODO 2: Enable the hardware uart and config baudrate."
|
||||
return 0;
|
||||
}
|
||||
INIT_BOARD_EXPORT(uart_init);
|
||||
|
||||
void rt_hw_console_output(const char *str)
|
||||
{
|
||||
#error "TODO 3: Output the string 'str' through the uart."
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,139 @@
|
||||
/* RT-Thread config file */
|
||||
|
||||
#ifndef __RTTHREAD_CFG_H__
|
||||
#define __RTTHREAD_CFG_H__
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h>Basic Configuration
|
||||
// <o>Maximal level of thread priority <8-256>
|
||||
// <i>Default: 32
|
||||
#define RT_THREAD_PRIORITY_MAX 16
|
||||
// <o>OS tick per second
|
||||
// <i>Default: 1000 (1ms)
|
||||
#define RT_TICK_PER_SECOND 1000
|
||||
// <o>Alignment size for CPU architecture data access
|
||||
// <i>Default: 4
|
||||
#define RT_ALIGN_SIZE 4
|
||||
// <o>the max length of object name<2-16>
|
||||
// <i>Default: 8
|
||||
#define RT_NAME_MAX 10
|
||||
// <c1>Using RT-Thread components initialization
|
||||
// <i>Using RT-Thread components initialization
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
// </c>
|
||||
|
||||
#define RT_USING_USER_MAIN
|
||||
|
||||
// <o>the stack size of main thread<1-4086>
|
||||
// <i>Default: 512
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 512
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Debug Configuration
|
||||
// <c1>enable kernel debug configuration
|
||||
// <i>Default: enable kernel debug configuration
|
||||
//#define RT_DEBUG
|
||||
// </c>
|
||||
// <o>enable components initialization debug configuration<0-1>
|
||||
// <i>Default: 0
|
||||
#define RT_DEBUG_INIT 0
|
||||
// <c1>thread stack over flow detect
|
||||
// <i> Diable Thread stack over flow detect
|
||||
//#define RT_USING_OVERFLOW_CHECK
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <h>Hook Configuration
|
||||
// <c1>using hook
|
||||
// <i>using hook
|
||||
//#define RT_USING_HOOK
|
||||
// </c>
|
||||
// <c1>using idle hook
|
||||
// <i>using idle hook
|
||||
//#define RT_USING_IDLE_HOOK
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <e>Software timers Configuration
|
||||
// <i> Enables user timers
|
||||
#define RT_USING_TIMER_SOFT 0
|
||||
#if RT_USING_TIMER_SOFT == 0
|
||||
#undef RT_USING_TIMER_SOFT
|
||||
#endif
|
||||
// <o>The priority level of timer thread <0-31>
|
||||
// <i>Default: 4
|
||||
#define RT_TIMER_THREAD_PRIO 4
|
||||
// <o>The stack size of timer thread <0-8192>
|
||||
// <i>Default: 512
|
||||
#define RT_TIMER_THREAD_STACK_SIZE 512
|
||||
// </e>
|
||||
|
||||
// <h>IPC(Inter-process communication) Configuration
|
||||
// <c1>Using Semaphore
|
||||
// <i>Using Semaphore
|
||||
#define RT_USING_SEMAPHORE
|
||||
// </c>
|
||||
// <c1>Using Mutex
|
||||
// <i>Using Mutex
|
||||
#define RT_USING_MUTEX
|
||||
// </c>
|
||||
// <c1>Using Event
|
||||
// <i>Using Event
|
||||
//#define RT_USING_EVENT
|
||||
// </c>
|
||||
// <c1>Using MailBox
|
||||
// <i>Using MailBox
|
||||
#define RT_USING_MAILBOX
|
||||
// </c>
|
||||
// <c1>Using Message Queue
|
||||
// <i>Using Message Queue
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <h>Memory Management Configuration
|
||||
// <c1>Memory Pool Management
|
||||
// <i>Memory Pool Management
|
||||
//#define RT_USING_MEMPOOL
|
||||
// </c>
|
||||
// <c1>Dynamic Heap Management(Algorithm: small memory )
|
||||
// <i>Dynamic Heap Management
|
||||
#define RT_USING_HEAP
|
||||
#define RT_USING_SMALL_MEM
|
||||
// </c>
|
||||
// <c1>using tiny size of memory
|
||||
// <i>using tiny size of memory
|
||||
//#define RT_USING_TINY_SIZE
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <h>Console Configuration
|
||||
// <c1>Using console
|
||||
// <i>Using console
|
||||
#define RT_USING_CONSOLE
|
||||
// </c>
|
||||
// <o>the buffer size of console <1-1024>
|
||||
// <i>the buffer size of console
|
||||
// <i>Default: 128 (128Byte)
|
||||
#define RT_CONSOLEBUF_SIZE 512
|
||||
// </h>
|
||||
|
||||
// <h>FinSH Configuration
|
||||
// <c1>include finsh config
|
||||
// <i>Select this choice if you using FinSH
|
||||
//#include "finsh_config.h"
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <h>Device Configuration
|
||||
// <c1>using device framework
|
||||
// <i>using device framework
|
||||
//#define RT_USING_DEVICE
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,139 @@
|
||||
/* RT-Thread config file */
|
||||
|
||||
#ifndef __RTTHREAD_CFG_H__
|
||||
#define __RTTHREAD_CFG_H__
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h>Basic Configuration
|
||||
// <o>Maximal level of thread priority <8-256>
|
||||
// <i>Default: 32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
// <o>OS tick per second
|
||||
// <i>Default: 1000 (1ms)
|
||||
#define RT_TICK_PER_SECOND 1000
|
||||
// <o>Alignment size for CPU architecture data access
|
||||
// <i>Default: 4
|
||||
#define RT_ALIGN_SIZE 4
|
||||
// <o>the max length of object name<2-16>
|
||||
// <i>Default: 8
|
||||
#define RT_NAME_MAX 8
|
||||
// <c1>Using RT-Thread components initialization
|
||||
// <i>Using RT-Thread components initialization
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
// </c>
|
||||
|
||||
#define RT_USING_USER_MAIN
|
||||
|
||||
// <o>the stack size of main thread<1-4086>
|
||||
// <i>Default: 512
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 256
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Debug Configuration
|
||||
// <c1>enable kernel debug configuration
|
||||
// <i>Default: enable kernel debug configuration
|
||||
//#define RT_DEBUG
|
||||
// </c>
|
||||
// <o>enable components initialization debug configuration<0-1>
|
||||
// <i>Default: 0
|
||||
#define RT_DEBUG_INIT 0
|
||||
// <c1>thread stack over flow detect
|
||||
// <i> Diable Thread stack over flow detect
|
||||
//#define RT_USING_OVERFLOW_CHECK
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <h>Hook Configuration
|
||||
// <c1>using hook
|
||||
// <i>using hook
|
||||
//#define RT_USING_HOOK
|
||||
// </c>
|
||||
// <c1>using idle hook
|
||||
// <i>using idle hook
|
||||
//#define RT_USING_IDLE_HOOK
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <e>Software timers Configuration
|
||||
// <i> Enables user timers
|
||||
#define RT_USING_TIMER_SOFT 0
|
||||
#if RT_USING_TIMER_SOFT == 0
|
||||
#undef RT_USING_TIMER_SOFT
|
||||
#endif
|
||||
// <o>The priority level of timer thread <0-31>
|
||||
// <i>Default: 4
|
||||
#define RT_TIMER_THREAD_PRIO 4
|
||||
// <o>The stack size of timer thread <0-8192>
|
||||
// <i>Default: 512
|
||||
#define RT_TIMER_THREAD_STACK_SIZE 512
|
||||
// </e>
|
||||
|
||||
// <h>IPC(Inter-process communication) Configuration
|
||||
// <c1>Using Semaphore
|
||||
// <i>Using Semaphore
|
||||
#define RT_USING_SEMAPHORE
|
||||
// </c>
|
||||
// <c1>Using Mutex
|
||||
// <i>Using Mutex
|
||||
//#define RT_USING_MUTEX
|
||||
// </c>
|
||||
// <c1>Using Event
|
||||
// <i>Using Event
|
||||
//#define RT_USING_EVENT
|
||||
// </c>
|
||||
// <c1>Using MailBox
|
||||
// <i>Using MailBox
|
||||
#define RT_USING_MAILBOX
|
||||
// </c>
|
||||
// <c1>Using Message Queue
|
||||
// <i>Using Message Queue
|
||||
//#define RT_USING_MESSAGEQUEUE
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <h>Memory Management Configuration
|
||||
// <c1>Memory Pool Management
|
||||
// <i>Memory Pool Management
|
||||
//#define RT_USING_MEMPOOL
|
||||
// </c>
|
||||
// <c1>Dynamic Heap Management(Algorithm: small memory )
|
||||
// <i>Dynamic Heap Management
|
||||
#define RT_USING_HEAP
|
||||
#define RT_USING_SMALL_MEM
|
||||
// </c>
|
||||
// <c1>using tiny size of memory
|
||||
// <i>using tiny size of memory
|
||||
//#define RT_USING_TINY_SIZE
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <h>Console Configuration
|
||||
// <c1>Using console
|
||||
// <i>Using console
|
||||
//#define RT_USING_CONSOLE
|
||||
// </c>
|
||||
// <o>the buffer size of console <1-1024>
|
||||
// <i>the buffer size of console
|
||||
// <i>Default: 128 (128Byte)
|
||||
#define RT_CONSOLEBUF_SIZE 256
|
||||
// </h>
|
||||
|
||||
// <h>FinSH Configuration
|
||||
// <c1>include finsh config
|
||||
// <i>Select this choice if you using FinSH
|
||||
//#include "finsh_config.h"
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <h>Device Configuration
|
||||
// <c1>using device framework
|
||||
// <i>using device framework
|
||||
//#define RT_USING_DEVICE
|
||||
// </c>
|
||||
// </h>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'BootLoader'
|
||||
* Target: 'Debug'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "HC32F460PETB.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'BootLoader'
|
||||
* Target: 'Release'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "HC32F460KETA.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'DigitalModule_4Ch'
|
||||
* Target: 'i2c_24c256_Debug'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "HC32F460PETB.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'DigitalModule_4Ch'
|
||||
* Target: 'i2c_24c256_Release'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "HC32F460PETB.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'DigitalModule_4Ch'
|
||||
* Target: 'template_Debug'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "HC32F460PETB.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
Reference in New Issue
Block a user