diff --git a/App/app_led.c b/App/app_led.c new file mode 100644 index 0000000..30a8acf --- /dev/null +++ b/App/app_led.c @@ -0,0 +1,46 @@ +#include "main.h" +#include "pt_ext.h" +#include "pt_task.h" +#include "hdl_led.h" +#include "app_led.h" + + +static volatile uint8_t led_status; + +void app_led_set_status(app_led_status_t status) +{ + led_status = status; +} + +int app_led_entry(struct pt *pt) +{ + PT_BEGIN(pt); + + hdl_led_init(); + + hdl_led_off(HDL_LED_ID_0); + + while (1){ + + PT_YIELD(pt); + + if(led_status == APP_LED_STATUS_UPDATE_RDY){ + + hdl_led_on(HDL_LED_ID_0); + PT_DELAY_MS(pt,20); + hdl_led_off(HDL_LED_ID_0); + PT_DELAY_MS(pt,500); + } + + if(led_status == APP_LED_STATUS_UPDATE_ING){ + + hdl_led_on(HDL_LED_ID_0); + PT_DELAY_MS(pt,50); + hdl_led_off(HDL_LED_ID_0); + PT_DELAY_MS(pt,50); + } + } + + PT_END(pt); +} +PT_TASK_APP_REG(app_led_entry); diff --git a/App/app_led.h b/App/app_led.h new file mode 100644 index 0000000..6687a0f --- /dev/null +++ b/App/app_led.h @@ -0,0 +1,12 @@ +#ifndef _APP_LED_H_ +#define _APP_LED_H_ +typedef enum{ + APP_LED_STATUS_IDEL, + APP_LED_STATUS_UPDATE_RDY, + APP_LED_STATUS_UPDATE_ING, +}app_led_status_t; + +extern void app_led_set_status(app_led_status_t status); + +#endif + diff --git a/App/app_update.c b/App/app_update.c new file mode 100644 index 0000000..5dc374d --- /dev/null +++ b/App/app_update.c @@ -0,0 +1,274 @@ +#include "main.h" +#include "pt_ext.h" +#include "pt_task.h" + +#include "dev_boot.h" +#include "dev_rs485.h" + +#include "ringbuffer.h" +#include "update_protocol.h" +#include "app_led.h" + +typedef struct { + boot_para_t Para; + +}BootLoader_t; + +static struct +{ + boot_para_t cfg; + uint32_t PackageRecvIndx; + uint32_t PackageRecvBytes; + uint8_t isNeedUpdate; + uint8_t isUpdateGoing; +} g_update; + +static struct +{ + uint8_t rb_pool[512]; + ring_buf_t rb; + + uint8_t frame[256]; + int frame_len; +} g_recive; + +static void send_bytes(uint8_t* pbuf, int len) +{ + dev_rs485_send(pbuf, len); +} + +static void rx_callback(uint8_t data) +{ + ring_buf_put(&g_recive.rb, &data, 1); +} + + +static void update_on_start( uint8_t* frame, int len, uint8_t* pload, int size) +{ + update_protocol_req_t* pReq = (void *)&frame[sizeof(update_protocol_hd_t)]; + + g_update.cfg.AppFlag = 0; + g_update.cfg.UpdateFlag = APP_UPDATE_FLAG; + g_update.cfg.Crc32Check = pReq->AppCrc32; + g_update.cfg.PackageNum = pReq->PackageNum; + g_update.cfg.AppSize = pReq->AppSize; + + dev_boot_write_param(g_update.cfg); + + g_update.PackageRecvIndx = 0; + g_update.PackageRecvBytes = 0; + + update_send_cmd(0x01, 1, 0); + + dev_boot_erase_app(); + + update_send_cmd(0x02, g_update.PackageRecvIndx, g_update.cfg.PackageNum); + +} + +static void update_on_download(uint8_t* frame, int len, uint8_t* pload, int size) +{ + update_protocol_rsp_t* pRsp =(void *)&frame[sizeof(update_protocol_hd_t)]; + + dev_boot_write_app(pRsp->PackageIndex * 200, pload, size); + + g_update.PackageRecvIndx ++; + + g_update.PackageRecvBytes += size; + + if (g_update.PackageRecvBytes == g_update.cfg.AppSize){ + + if ( dev_boot_check_app()) + { + uint32_t crc_rom = dev_boot_get_app_crc32(g_update.cfg.AppSize); + + if (crc_rom == g_update.cfg.Crc32Check) + { + g_update.cfg.AppFlag = 0; + g_update.cfg.UpdateFlag = 0; + g_update.cfg.PackageNum = 0; + + dev_boot_write_param(g_update.cfg); + + NVIC_SystemReset(); + } + } + }else{ + + update_send_cmd(0x02, g_update.PackageRecvIndx, g_update.cfg.PackageNum); + } +} + +static int update_cmd_process(uint8_t cmd, void* frame, int len, void* pload, int size) +{ + int res = 0; + + switch (cmd) + { + case 0x81:{ + + update_on_start(frame, len, pload, size); + + res = 1; + } + break; + + case 0x82: + { + update_on_download(frame, len, pload, size); + + res = 1; + + }break; + + default: + break; + + } + + return res; +} + + +static int read_frame(void) +{ + uint8_t dat = 0; + + int len = ring_buf_get(&g_recive.rb, &dat, 1); + + if (len > 0) + { + if (g_recive.frame_len < sizeof(g_recive.frame)) + { + g_recive.frame[ g_recive.frame_len] = dat; + g_recive.frame_len++; + } + + return 1; + } + else + { + + return 0; + } +} + +static int update_process(void* frame, int len) +{ + uint8_t cmd = 0; + + uint8_t user_data[256] = {0}; + + int user_data_len = 0; + + int res = update_unpack(frame, len, &cmd, user_data, &user_data_len); + + if(res ==0) + return -1; + + res = update_cmd_process(cmd,frame, len, user_data,user_data_len); + + if(res ==0){ + + return -2; + } + + return 0; +} + + +int app_update_entry(struct pt *pt) +{ + int len = 0; + + PT_BEGIN(pt); + + dev_boot_read_param(&g_update.cfg); + + if (g_update.cfg.UpdateFlag == APP_UPDATE_FLAG) + { + g_update.isNeedUpdate = 1; + } + else + { + g_update.isNeedUpdate = 1; + + if (dev_boot_check_app()) + { + uint32_t crc_rom = dev_boot_get_app_crc32(g_update.cfg.AppSize); + + if (crc_rom == g_update.cfg.Crc32Check) + { + + g_update.isNeedUpdate = 0; + + dev_boot_run_app(); + } + } + } + + if (g_update.isNeedUpdate) + { + ring_buf_init(&g_recive.rb, g_recive.rb_pool, sizeof(g_recive.rb_pool)); + + dev_rs485_init(); + + dev_rs485_rx_register(rx_callback); + + update_init(send_bytes); + + //²Á³ýAPP + if ((g_update.cfg.UpdateFlag == APP_UPDATE_FLAG) + && dev_boot_check_app() + ){ + dev_boot_erase_app(); + } +// uint8_t i[6] = {1,2,3,4,5,6}; +// while(1) +// { +// dev_rs485_send(i,6); +// } + + app_led_set_status( APP_LED_STATUS_UPDATE_RDY); + } + + while (1){ + + PT_YIELD(pt); + + len = read_frame(); + + if (len == 0){ + + PT_DELAY_MS(pt, 20); + + len = read_frame(); + + if (len == 0){ + + if (g_recive.frame_len > 0){ + + app_led_set_status( APP_LED_STATUS_UPDATE_ING); + + update_process( g_recive.frame ,g_recive.frame_len); + + g_recive.frame_len = 0; + + }else{ + + if(g_update.cfg.UpdateFlag == APP_UPDATE_FLAG && + + g_update.PackageRecvBytes < g_update.cfg.AppSize){ + + update_send_cmd(0x02, g_update.PackageRecvIndx, g_update.cfg.PackageNum ); + + + } + } + } + } + } + + PT_END(pt); +} +PT_TASK_APP_REG(app_update_entry); diff --git a/App/main.c b/App/main.c new file mode 100644 index 0000000..b7bc7cc --- /dev/null +++ b/App/main.c @@ -0,0 +1,54 @@ + +#include "main.h" + +#include "pt_ext.h" +#include "pt_task.h" +#include +#include + +#include "hdl_clk.h" + +/******************************************************************************* + * ÖжϷþÎñº¯Êý + ******************************************************************************/ +void SysTick_Handler(void) +{ + pt_ticks_inc(); + + __DSB(); +} + + + +void JDI_Disable(void) +{ + GPIO_REG_Unlock(); + GPIO_SetDebugPort( GPIO_PIN_TRST,DISABLE); + GPIO_SetDebugPort( GPIO_PIN_TDO, DISABLE); + GPIO_REG_Lock(); +} + +int32_t main(void) +{ + + JDI_Disable(); + + hdl_clk_init(); + + while (1) + { + SWDT_FeedDog(); + + pt_task_schedule(); + + pt_task_pm(); + } +} + + + + + + + + diff --git a/App/main.h b/App/main.h new file mode 100644 index 0000000..1f317ee --- /dev/null +++ b/App/main.h @@ -0,0 +1,8 @@ +#ifndef __MAIN__H +#define __MAIN__H + +#include "stdint.h" + +#endif + + diff --git a/HC32F460_BootLoader_项目架构和工作æµç¨‹åˆ†æž.md b/HC32F460_BootLoader_项目架构和工作æµç¨‹åˆ†æž.md new file mode 100644 index 0000000..228c8fd --- /dev/null +++ b/HC32F460_BootLoader_项目架构和工作æµç¨‹åˆ†æž.md @@ -0,0 +1,495 @@ +# HC32F460 BootLoader 项目架构和工作æµç¨‹åˆ†æž + +## 1. 项目概述 + +### 1.1 项目简介 +HC32F460 BootLoader是基于HC32F460微控制器的固件更新引导程åºï¼Œé‡‡ç”¨RT-Thread Nano 3.1.5实时æ“作系统框架，支æŒé€šè¿‡RS485接å£è¿›è¡Œè¿œç¨‹å›ºä»¶æ›´æ–°ã€‚ + +### 1.2 主è¦åŠŸèƒ½ +- **系统引导**：检测并å¯åŠ¨åº”ç”¨ç¨‹åº +- **固件更新**：支æŒè¿œç¨‹å›ºä»¶ä¸‹è½½å’Œæ›´æ–° +- **通信åè®®**：实现自定义的固件更新åè®® +- **错误处ç†**：æ供完整的更新æµç¨‹é”™è¯¯å¤„ç† + +## 2. ç³»ç»Ÿæž¶æž„åˆ†æž + +### 2.1 整体架构图 + +``` +┌─────────────────────────────────────────────┠+│ BootLoader系统架构 │ +├─────────────────────────────────────────────┤ +│ 应用层 (App/) │ +│ ┌─────────────┬─────────────┬─────────────┠│ +│ │ 主程åºæ¨¡å— │ æ›´æ–°ä»»åŠ¡æ¨¡å— â”‚ LED状æ€æ¨¡å— │ │ +│ │ (main.c) │ (app_update.c)│ (app_led.c) │ │ +│ └─────────────┴─────────────┴─────────────┘ │ +├─────────────────────────────────────────────┤ +│ 组件层 (components/) │ +│ ┌─────────────┬─────────────┠│ +│ │ å议处ç†æ¨¡å— │ çŽ¯å½¢ç¼“å†²åŒºæ¨¡å— â”‚ │ +│ │(update_protocol)│ (ringbuffer) │ │ +│ └─────────────┴─────────────┘ │ +├─────────────────────────────────────────────┤ +│ 驱动层 (device/) │ +│ ┌─────────────┬─────────────┠│ +│ │ Boot驱动 │ RS485驱动 │ │ +│ │ (dev_boot.c)│(dev_rs485.c)│ │ +│ └─────────────┴─────────────┘ │ +├─────────────────────────────────────────────┤ +│ 硬件抽象层 (hdl/) │ +│ ┌─────┬─────┬─────┬─────┬─────┬─────┬─────┠│ +│ │时钟 │Flashâ”‚ä¸²å£ â”‚SPI │PWM │LED │LCD │ │ +│ â”‚ç®¡ç† â”‚é©±åŠ¨ │驱动 │驱动 │驱动 │驱动 │驱动 │ │ +│ └─────┴─────┴─────┴─────┴─────┴─────┴─────┘ │ +└─────────────────────────────────────────────┘ +``` + +### 2.2 目录结构详解 + +``` +hc32f460_boot/ +├── App/ # 应用层 - 业务逻辑实现 +│ ├── main.c # 系统主程åºå…¥å£ +│ ├── app_led.c # LED状æ€æŒ‡ç¤ºæ¨¡å— +│ └── app_update.c # 固件更新核心逻辑 +├── Project/ # 项目é…ç½® - 编译和è¿è¡Œé…ç½® +│ └── RTE/RTOS/ # RT-Threadæ“作系统é…ç½® +├── components/ # 组件层 - é€šç”¨åŠŸèƒ½æ¨¡å— +│ ├── ringbuffer.c # 环形缓冲区实现 +│ └── update_protocol.c # æ›´æ–°åè®®å¤„ç† +├── device/ # 驱动层 - è®¾å¤‡é©±åŠ¨æŽ¥å£ +│ ├── dev_boot.c # Boot相关æ“作驱动 +│ └── dev_rs485.c # RS485通信驱动 +└── hdl/ # 硬件抽象层 - 底层硬件æ“作 + ├── hdl_clk.c # ç³»ç»Ÿæ—¶é’Ÿç®¡ç† + ├── hdl_flash.c # Flash存储器æ“作 + ├── hdl_usart.c # 串å£é€šä¿¡é©±åŠ¨ + └── ... # 其他外设驱动 +``` + +## 3. 核心模å—åˆ†æž + +### 3.1 主程åºæ¨¡å— (main.c) + +#### 3.1.1 系统åˆå§‹åŒ–æµç¨‹ + +```c +int32_t main(void) +{ + // 1. ç¦ç”¨è°ƒè¯•æŽ¥å£ + JDI_Disable(); + + // 2. åˆå§‹åŒ–系统时钟 + hdl_clk_init(); + + // 3. 主循环 - å程任务调度 + while (1) + { + // å–‚ç‹—æ“作 + SWDT_FeedDog(); + + // å程任务调度 + pt_task_schedule(); + + // 电æºç®¡ç† + pt_task_pm(); + } +} +``` + +#### 3.1.2 å程调度机制 + +```c +// å程任务调度器 +void pt_task_schedule(void) +{ + for (int i = 0; i < TASK_MAX_NUM; i++) { + if (g_task_list[i].enabled && g_task_list[i].entry) { + g_task_list[i].entry(g_task_list[i].param); + } + } +} +``` + +### 3.2 å›ºä»¶æ›´æ–°æ¨¡å— (app_update.c) + +#### 3.2.1 更新状æ€æœºè®¾è®¡ + +```c +// 更新状æ€å®šä¹‰ +typedef enum { + UPDATE_STATE_IDLE = 0, // ç©ºé—²çŠ¶æ€ + UPDATE_STATE_RECEIVING, // 接收数æ®çŠ¶æ€ + UPDATE_STATE_PROCESSING, // 处ç†æ•°æ®çŠ¶æ€ + UPDATE_STATE_WRITING, // 写入FlashçŠ¶æ€ + UPDATE_STATE_VERIFYING, // 验è¯çŠ¶æ€ + UPDATE_STATE_COMPLETED, // 完æˆçŠ¶æ€ + UPDATE_STATE_ERROR // é”™è¯¯çŠ¶æ€ +} update_state_t; +``` + +#### 3.2.2 核心数æ®ç»“æž„ + +```c +// 全局更新状æ€ç»“æž„ +static struct +{ + boot_para_t cfg; // Bootå‚æ•°é…ç½® + uint32_t PackageRecvIndx; // 当å‰æŽ¥æ”¶åŒ…索引 + uint32_t PackageRecvBytes; // 已接收字节数 + uint8_t isNeedUpdate; // 需è¦æ›´æ–°æ ‡å¿— + uint8_t isUpdateGoing; // 更新进行中标志 +} g_update; + +// 接收缓冲区结构 +static struct +{ + uint8_t rb_pool[512]; // 环形缓冲区池 + ring_buf_t rb; // 环形缓冲区实例 + uint8_t frame[256]; // 帧缓冲区 + int frame_len; // 帧长度 +} g_recive; +``` + +#### 3.2.3 更新任务入å£å‡½æ•° + +```c +int app_update_entry(struct pt *pt) +{ + PT_BEGIN(pt); + + // 1. 读å–Bootå‚æ•° + dev_boot_read_param(&g_update.cfg); + + // 2. 检查是å¦éœ€è¦æ›´æ–° + if (g_update.cfg.UpdateFlag == APP_UPDATE_FLAG) { + g_update.isNeedUpdate = 1; + } else { + // 检查应用程åºå®Œæ•´æ€§ + if (dev_boot_check_app()) { + uint32_t crc_rom = dev_boot_get_app_crc32(g_update.cfg.AppSize); + if (crc_rom == g_update.cfg.Crc32Check) { + g_update.isNeedUpdate = 0; + // å¯åŠ¨åº”ç”¨ç¨‹åº + dev_boot_run_app(); + } + } + } + + // 3. 如果需è¦æ›´æ–°ï¼Œåˆå§‹åŒ–通信 + if (g_update.isNeedUpdate) { + ring_buf_init(&g_recive.rb, g_recive.rb_pool, sizeof(g_recive.rb_pool)); + dev_rs485_init(); + dev_rs485_rx_register(rx_callback); + update_init(send_bytes); + + // 设置LED状æ€ä¸ºå‡†å¤‡æ›´æ–° + app_led_set_status(APP_LED_STATUS_UPDATE_RDY); + } + + // 4. 主处ç†å¾ªçŽ¯ + while (1) { + PT_YIELD(pt); + + // 处ç†æŽ¥æ”¶æ•°æ® + int len = read_frame(); + + if (len == 0) { + PT_DELAY_MS(pt, 20); + + len = read_frame(); + if (len == 0) { + if (g_recive.frame_len > 0) { + // 处ç†å®Œæ•´å¸§ + app_led_set_status(APP_LED_STATUS_UPDATE_ING); + update_process(g_recive.frame, g_recive.frame_len); + g_recive.frame_len = 0; + } else { + // å‘é€æ›´æ–°çŠ¶æ€è¯·æ±‚ + if (g_update.cfg.UpdateFlag == APP_UPDATE_FLAG && + g_update.PackageRecvBytes < g_update.cfg.AppSize) { + update_send_cmd(0x02, g_update.PackageRecvIndx, g_update.cfg.PackageNum); + } + } + } + } + } + + PT_END(pt); +} +``` + +### 3.3 å议处ç†æ¨¡å— (update_protocol.c) + +#### 3.3.1 åè®®å¸§æ ¼å¼ + +```c +// å议头结构 +typedef struct { + uint8_t Header; // 帧头 (0x7A) + uint8_t SlvAddr; // ä»Žæœºåœ°å€ + uint8_t Cmd; // 命令字 + uint8_t PayloadLen; // æ•°æ®é•¿åº¦ +} update_protocol_hd_t; + +// 更新请求数æ®ç»“æž„ +typedef struct { + uint16_t PackageNum; // 总包数 + uint32_t AppSize; // 应用程åºå¤§å° + uint32_t AppCrc32; // 应用程åºCRC32校验值 +} __attribute__ ((packed)) update_protocol_req_t; + +// 下载å“应数æ®ç»“æž„ +typedef struct { + uint16_t PackageIndex; // 包索引 + uint16_t PackageNum; // 总包数 + uint8_t DataLen; // æ•°æ®é•¿åº¦ +} __attribute__ ((packed)) update_protocol_rsp_t; +``` + +#### 3.3.2 CRC校验算法 + +```c +// Modbus CRC16校验算法 +uint16_t CRC_Modbus(uint16_t wBase, uint8_t* para, uint16_t length) +{ + uint16_t crc = 0xffff; + uint16_t index, i; + + for (index = 0; index < length; index++) { + crc ^= para[index]; + + for (i = 0; i < 8; i++) { + if (crc & 1) { + crc >>= 1; + crc ^= wBase; + } else { + crc >>= 1; + } + } + } + + return crc; +} +``` + +### 3.4 Booté©±åŠ¨æ¨¡å— (dev_boot.c) + +#### 3.4.1 Flash分区定义 + +```c +// Flash分区é…ç½® +#define FLASH_BINFO_BASE 0x00003000 // Bootå‚æ•°åŒºèµ·å§‹åœ°å€ +#define FLASH_BINFO_SIZE 0x00001000 // Bootå‚æ•°åŒºå¤§å° +#define FLASH_APP_BASE 0x00004000 // 应用程åºåŒºèµ·å§‹åœ°å€ +#define FLASH_APP_SIZE 0x00070000 // 应用程åºåŒºå¤§å° +#define FLASH_SECTOR_SIZE 0x00001000 // Flashæ‰‡åŒºå¤§å° +``` + +#### 3.4.2 应用程åºå¯åŠ¨æµç¨‹ + +```c +void dev_boot_run_app(void) +{ + volatile uint32_t JumpAddress; + func_ptr_t JumpToApplication; + uint32_t AppAddr = FLASH_APP_BASE; + + // 检查栈指针有效性 + uint32_t u32StackTop = *((__IO uint32_t*)AppAddr); + + if ((u32StackTop > SRAM_BASE) && (u32StackTop <= (SRAM_BASE + SRAM_SIZE))) { + // 获å–应用程åºå…¥å£åœ°å€ + JumpAddress = *(__IO uint32_t*)(AppAddr + 4); + JumpToApplication = (func_ptr_t)JumpAddress; + + // ç¦ç”¨ä¸­æ–­ + __disable_fiq(); + + // 设置主栈指针 + __set_MSP(*(__IO uint32_t*)AppAddr); + + // è·³è½¬åˆ°åº”ç”¨ç¨‹åº + JumpToApplication(); + } +} +``` + +## 4. 工作æµç¨‹åˆ†æž + +### 4.1 系统å¯åŠ¨æµç¨‹ + +```mermaid +flowchart TD + A[系统上电] --> B[硬件åˆå§‹åŒ–] + B --> C[读å–Bootå‚æ•°] + C --> D{应用程åºæœ‰æ•ˆ?} + D -->|是| E[å¯åŠ¨åº”用程åº] + D -->|å¦| F[进入BootLoader模å¼] + F --> G[åˆå§‹åŒ–通信接å£] + G --> H[等待更新命令] +``` + +### 4.2 固件更新æµç¨‹ + +```mermaid +flowchart TD + A[等待更新命令] --> B[接收更新开始命令] + B --> C[擦除应用程åºåŒº] + C --> D[接收数æ®åŒ…] + D --> E[写入Flash] + E --> F{所有包接收完æˆ?} + F -->|å¦| D + F -->|是| G[验è¯åº”用程åº] + G --> H{验è¯é€šè¿‡?} + H -->|是| I[系统å¤ä½] + H -->|å¦| J[报告错误] + J --> A +``` + +### 4.3 å议交互æµç¨‹ + +#### 4.3.1 更新开始命令交互 + +``` +主机å‘é€: +7A 01 81 06 [PackageNum(2)][AppSize(4)][AppCrc32(4)] [CRC16(2)] + +从机å“应: +7A 01 01 01 [Result(1)] [CRC16(2)] +``` + +#### 4.3.2 æ•°æ®ä¸‹è½½å‘½ä»¤äº¤äº’ + +``` +主机å‘é€: +7A 01 82 05 [PackageIndex(2)][PackageNum(2)][DataLen(1)] [Data(N)] [CRC16(2)] + +从机å“应: +7A 01 02 04 [PackageIndex(2)][PackageNum(2)] [CRC16(2)] +``` + +## 5. 关键技术特性 + +### 5.1 å程任务调度 + +**优势**: +- 内存å ç”¨å°ï¼Œé€‚åˆèµ„æºå—é™çŽ¯å¢ƒ +- 实现简å•ï¼Œä»£ç å¯è¯»æ€§å¥½ +- 无需å¤æ‚çš„ä¸Šä¸‹æ–‡åˆ‡æ¢ + +**å±€é™æ€§**: +- 缺ä¹ä¼˜å…ˆçº§è°ƒåº¦æœºåˆ¶ +- 实时性相对较差 +- 任务间å作需è¦æ‰‹åŠ¨ç®¡ç† + +### 5.2 安全机制 + +#### 5.2.1 CRC校验 +- 使用Modbus CRC16进行通信数æ®æ ¡éªŒ +- 应用程åºä½¿ç”¨CRC32è¿›è¡Œå®Œæ•´æ€§éªŒè¯ + +#### 5.2.2 Flashä¿æŠ¤ +- 写æ“作å‰è¿›è¡ŒFlashè§£é” +- æ“作完æˆåŽç«‹å³é”定Flash +- 支æŒæ‰‡åŒºçº§åˆ«çš„擦除ä¿æŠ¤ + +### 5.3 错误æ¢å¤æœºåˆ¶ + +#### 5.3.1 é€šä¿¡è¶…æ—¶å¤„ç† +```c +// 超时é‡ä¼ æœºåˆ¶ +if (g_update.cfg.UpdateFlag == APP_UPDATE_FLAG && + g_update.PackageRecvBytes < g_update.cfg.AppSize) { + update_send_cmd(0x02, g_update.PackageRecvIndx, g_update.cfg.PackageNum); +} +``` + +#### 5.3.2 应用程åºéªŒè¯ +```c +// 应用程åºå®Œæ•´æ€§æ£€æŸ¥ +uint8_t dev_boot_check_app(void) +{ + uint32_t AppAddr = FLASH_APP_BASE; + uint32_t u32StackTop = *((__IO uint32_t*)AppAddr); + + // 检查栈指针是å¦åœ¨æœ‰æ•ˆRAM范围内 + if ((u32StackTop > SRAM_BASE) && (u32StackTop <= (SRAM_BASE + SRAM_SIZE))) { + return 1; + } + return 0; +} +``` + +## 6. æ€§èƒ½æŒ‡æ ‡åˆ†æž + +### 6.1 内存使用情况 + +| 内存区域 | å¤§å° | 用途说明 | +|---------|------|----------| +| 代ç æ®µ | ~20KB | BootLoaderæ ¸å¿ƒä»£ç  | +| æ•°æ®æ®µ | ~4KB | 全局å˜é‡å’Œç¼“冲区 | +| 栈空间 | ~1KB | 任务栈空间 | +| 堆空间 | ~2KB | 动æ€å†…å­˜åˆ†é… | + +### 6.2 时间性能指标 + +| æ“作类型 | 典型时间 | å½±å“å› ç´  | +|---------|----------|----------| +| 系统å¯åŠ¨ | < 100ms | 硬件åˆå§‹åŒ–时间 | +| Flash擦除 | ~100ms/扇区 | Flash芯片特性 | +| æ•°æ®ç¼–程 | ~10μs/字节 | 编程算法效率 | +| åè®®å¤„ç† | < 10ms | æ•°æ®å¤„ç†å¤æ‚度 | + +### 6.3 å¯é æ€§æŒ‡æ ‡ + +| 指标类型 | 目标值 | å®žçŽ°æ–¹å¼ | +|---------|--------|----------| +| 通信误ç çŽ‡ | < 10â»â¶ | CRC校验机制 | +| æ›´æ–°æˆåŠŸçŽ‡ | > 99% | å®Œæ•´çš„é”™è¯¯å¤„ç† | +| 系统稳定性 | 7x24å°æ—¶ | 看门狗ä¿æŠ¤ | + +## 7. 扩展性和优化建议 + +### 7.1 架构优化建议 + +#### 7.1.1 任务调度改进 +```c +// 建议è¿ç§»åˆ°æ ‡å‡†RT-Thread任务调度 +rt_thread_t update_thread = rt_thread_create("update", + update_task_entry, + RT_NULL, + 512, 10, 20); +``` + +#### 7.1.2 内存管ç†ä¼˜åŒ– +```c +// å®žçŽ°å†…å­˜æ± ç®¡ç† +static rt_uint8_t mempool_pool[64 * 32]; +static struct rt_mempool mempool; +rt_mp_init(&mempool, "boot_mp", &mempool_pool[0], 64, 64*32, RT_IPC_FLAG_FIFO); +``` + +### 7.2 功能扩展建议 + +#### 7.2.1 支æŒå¤šç§æ›´æ–°æ–¹å¼ +- 增加USB DFUæ”¯æŒ +- 支æŒä»¥å¤ªç½‘æ›´æ–° +- 添加SDå¡æ›´æ–°åŠŸèƒ½ + +#### 7.2.2 增强安全性 +- 实现数字签åéªŒè¯ +- 支æŒåŠ å¯†ä¼ è¾“ +- 添加回滚ä¿æŠ¤æœºåˆ¶ + +## 8. 总结 + +HC32F460 BootLoader项目采用了清晰的模å—化架构设计，通过å程任务调度实现了高效的固件更新功能。项目具有以下特点： + +1. **架构清晰**：分层设计，模å—èŒè´£æ˜Žç¡® +2. **功能完整**：支æŒå®Œæ•´çš„固件更新æµç¨‹ +3. **å¯é æ€§é«˜**：多é‡å®‰å…¨ä¿æŠ¤å’Œé”™è¯¯æ¢å¤æœºåˆ¶ +4. **资æºä¼˜åŒ–**：内存使用效率高，适åˆåµŒå…¥å¼çŽ¯å¢ƒ + +通过本文档的分æžï¼Œå¯ä»¥ä¸ºé¡¹ç›®çš„åŽç»­ç»´æŠ¤ã€åŠŸèƒ½æ‰©å±•å’Œæ€§èƒ½ä¼˜åŒ–æ供全é¢çš„技术å‚考。 \ No newline at end of file diff --git a/Project/BootLoader.uvoptx b/Project/BootLoader.uvoptx new file mode 100644 index 0000000..6c318ac --- /dev/null +++ b/Project/BootLoader.uvoptx @@ -0,0 +1,1067 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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..\mcu\lib\src\hc32_ll_rmu.c + hc32_ll_rmu.c + 0 + 0 + + + 6 + 43 + 1 + 0 + 0 + 0 + ..\mcu\lib\src\hc32_ll_rtc.c + hc32_ll_rtc.c + 0 + 0 + + + 6 + 44 + 1 + 0 + 0 + 0 + ..\mcu\lib\src\hc32_ll_sdioc.c + hc32_ll_sdioc.c + 0 + 0 + + + 6 + 45 + 1 + 0 + 0 + 0 + ..\mcu\lib\src\hc32_ll_spi.c + hc32_ll_spi.c + 0 + 0 + + + 6 + 46 + 1 + 0 + 0 + 0 + ..\mcu\lib\src\hc32_ll_sram.c + hc32_ll_sram.c + 0 + 0 + + + 6 + 47 + 1 + 0 + 0 + 0 + ..\mcu\lib\src\hc32_ll_swdt.c + hc32_ll_swdt.c + 0 + 0 + + + 6 + 48 + 1 + 0 + 0 + 0 + ..\mcu\lib\src\hc32_ll_tmr0.c + hc32_ll_tmr0.c + 0 + 0 + + + 6 + 49 + 1 + 0 + 0 + 0 + ..\mcu\lib\src\hc32_ll_tmr4.c + hc32_ll_tmr4.c + 0 + 0 + + + 6 + 50 + 1 + 0 + 0 + 0 + ..\mcu\lib\src\hc32_ll_tmr6.c + hc32_ll_tmr6.c + 0 + 0 + + + 6 + 51 + 1 + 0 + 0 + 0 + ..\mcu\lib\src\hc32_ll_tmra.c + hc32_ll_tmra.c + 0 + 0 + + + 6 + 52 + 1 + 0 + 0 + 0 + ..\mcu\lib\src\hc32_ll_trng.c + hc32_ll_trng.c + 0 + 0 + + + 6 + 53 + 1 + 0 + 0 + 0 + ..\mcu\lib\src\hc32_ll_usart.c + hc32_ll_usart.c + 0 + 0 + + + 6 + 54 + 1 + 0 + 0 + 0 + ..\mcu\lib\src\hc32_ll_usb.c + hc32_ll_usb.c + 0 + 0 + + + 6 + 55 + 1 + 0 + 0 + 0 + ..\mcu\lib\src\hc32_ll_utility.c + hc32_ll_utility.c + 0 + 0 + + + 6 + 56 + 1 + 0 + 0 + 0 + ..\mcu\lib\src\hc32_ll_wdt.c + hc32_ll_wdt.c + 0 + 0 + + + 6 + 57 + 1 + 0 + 0 + 0 + ..\mcu\lib\src\hc32f460_ll_interrupts_share.c + hc32f460_ll_interrupts_share.c + 0 + 0 + + + + + mcu + 0 + 0 + 0 + 0 + + 7 + 58 + 1 + 0 + 0 + 0 + ..\mcu\cmsis\Device\HDSC\hc32f4xx\Source\system_hc32f460.c + system_hc32f460.c + 0 + 0 + + + 7 + 59 + 2 + 0 + 0 + 0 + ..\mcu\startup\startup_hc32f460.s + startup_hc32f460.s + 0 + 0 + + + + + Readme + 1 + 0 + 0 + 0 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/Project/BootLoader.uvprojx b/Project/BootLoader.uvprojx new file mode 100644 index 0000000..1082d1a --- /dev/null +++ b/Project/BootLoader.uvprojx @@ -0,0 +1,840 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Release + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::ARMCC + 0 + + + HC32F460KETA + HDSC + HDSC.HC32F460.1.0.12 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IRAM(0x1FFF8000,0x2F000) IRAM2(0x200F0000,0x1000) IROM(0x00000000,0x80000) IROM2(0x03000C00,0x003FC) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD1FFF8000 -FC1000 -FN2 -FF0HC32F460_512K -FS00 -FL080000 -FF1HC32F460_otp -FS13000C00 -FL13FC -FP0($$Device:HC32F460KETA$FlashARM\HC32F460_512K.FLM) -FP1($$Device:HC32F460KETA$FlashARM\HC32F460_otp.FLM)) + 0 + $$Device:HC32F460KETA$Device\Include\HC32F460KETA.h + + + + + + + + + + $$Device:HC32F460KETA$SVD\HC32F460KETA.svd + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\debug\ + boot + 1 + 0 + 1 + 1 + 1 + .\output\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin -o "$L@L.bin" "#L" + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 1 + 1 + 8 + 1 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fff8000 + 0x2f000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x3000c00 + 0x3fc + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fff8000 + 0x2f000 + + + 0 + 0x200f0000 + 0x1000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + --diag_suppress=186,66 + HC32F460,USE_DDL_DRIVER, + + ..\App;..\components;..\device;..\hdl;..\pthreads;..\mcu\lib\inc;..\mcu\common;..\mcu\cmsis\Include;..\mcu\cmsis\Device\HDSC\hc32f4xx\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x1FFF8000 + + i2c_24c256.sct + + + --keep=*Handler + + + + + + + + app + + + main.c + 1 + ..\App\main.c + + + app_update.c + 1 + ..\App\app_update.c + + + app_led.c + 1 + ..\App\app_led.c + + + + + device + + + dev_boot.c + 1 + ..\device\dev_boot.c + + + dev_rs485.c + 1 + ..\device\dev_rs485.c + + + + + hdl + + + hdl_clk.c + 1 + ..\hdl\hdl_clk.c + + + hdl_led.c + 1 + ..\hdl\hdl_led.c + + + hdl_usart.c + 1 + ..\hdl\hdl_usart.c + + + hdl_flash.c + 1 + ..\hdl\hdl_flash.c + + + + + components + + + ringbuffer.c + 1 + ..\components\ringbuffer.c + + + update_protocol.c + 1 + ..\components\update_protocol.c + + + + + ptthreads + + + pt_ext.c + 1 + ..\pthreads\pt_ext.c + + + pt_task.c + 1 + ..\pthreads\pt_task.c + + + pt_pm.c + 1 + ..\pthreads\pt_pm.c + + + + + mcu_lib + + + hc32_ll.c + 1 + ..\mcu\lib\src\hc32_ll.c + + + hc32_ll_adc.c + 1 + ..\mcu\lib\src\hc32_ll_adc.c + + + hc32_ll_aes.c + 1 + ..\mcu\lib\src\hc32_ll_aes.c + + + hc32_ll_aos.c + 1 + ..\mcu\lib\src\hc32_ll_aos.c + + + hc32_ll_can.c + 1 + ..\mcu\lib\src\hc32_ll_can.c + + + hc32_ll_clk.c + 1 + ..\mcu\lib\src\hc32_ll_clk.c + + + hc32_ll_cmp.c + 1 + ..\mcu\lib\src\hc32_ll_cmp.c + + + hc32_ll_crc.c + 1 + ..\mcu\lib\src\hc32_ll_crc.c + + + hc32_ll_dbgc.c + 1 + ..\mcu\lib\src\hc32_ll_dbgc.c + + + hc32_ll_dcu.c + 1 + ..\mcu\lib\src\hc32_ll_dcu.c + + + hc32_ll_dma.c + 1 + ..\mcu\lib\src\hc32_ll_dma.c + + + hc32_ll_efm.c + 1 + ..\mcu\lib\src\hc32_ll_efm.c + + + hc32_ll_emb.c + 1 + ..\mcu\lib\src\hc32_ll_emb.c + + + hc32_ll_event_port.c + 1 + ..\mcu\lib\src\hc32_ll_event_port.c + + + hc32_ll_fcg.c + 1 + ..\mcu\lib\src\hc32_ll_fcg.c + + + hc32_ll_fcm.c + 1 + ..\mcu\lib\src\hc32_ll_fcm.c + + + hc32_ll_gpio.c + 1 + ..\mcu\lib\src\hc32_ll_gpio.c + + + hc32_ll_hash.c + 1 + ..\mcu\lib\src\hc32_ll_hash.c + + + hc32_ll_i2c.c + 1 + ..\mcu\lib\src\hc32_ll_i2c.c + + + hc32_ll_i2s.c + 1 + ..\mcu\lib\src\hc32_ll_i2s.c + + + hc32_ll_icg.c + 1 + ..\mcu\lib\src\hc32_ll_icg.c + + + hc32_ll_interrupts.c + 1 + ..\mcu\lib\src\hc32_ll_interrupts.c + + + hc32_ll_keyscan.c + 1 + ..\mcu\lib\src\hc32_ll_keyscan.c + + + hc32_ll_mpu.c + 1 + ..\mcu\lib\src\hc32_ll_mpu.c + + + hc32_ll_ots.c + 1 + ..\mcu\lib\src\hc32_ll_ots.c + + + hc32_ll_pwc.c + 1 + ..\mcu\lib\src\hc32_ll_pwc.c + + + hc32_ll_qspi.c + 1 + ..\mcu\lib\src\hc32_ll_qspi.c + + + hc32_ll_rmu.c + 1 + ..\mcu\lib\src\hc32_ll_rmu.c + + + hc32_ll_rtc.c + 1 + ..\mcu\lib\src\hc32_ll_rtc.c + + + hc32_ll_sdioc.c + 1 + ..\mcu\lib\src\hc32_ll_sdioc.c + + + hc32_ll_spi.c + 1 + ..\mcu\lib\src\hc32_ll_spi.c + + + hc32_ll_sram.c + 1 + ..\mcu\lib\src\hc32_ll_sram.c + + + hc32_ll_swdt.c + 1 + ..\mcu\lib\src\hc32_ll_swdt.c + + + hc32_ll_tmr0.c + 1 + ..\mcu\lib\src\hc32_ll_tmr0.c + + + hc32_ll_tmr4.c + 1 + ..\mcu\lib\src\hc32_ll_tmr4.c + + + hc32_ll_tmr6.c + 1 + ..\mcu\lib\src\hc32_ll_tmr6.c + + + hc32_ll_tmra.c + 1 + ..\mcu\lib\src\hc32_ll_tmra.c + + + hc32_ll_trng.c + 1 + ..\mcu\lib\src\hc32_ll_trng.c + + + hc32_ll_usart.c + 1 + ..\mcu\lib\src\hc32_ll_usart.c + + + hc32_ll_usb.c + 1 + ..\mcu\lib\src\hc32_ll_usb.c + + + hc32_ll_utility.c + 1 + ..\mcu\lib\src\hc32_ll_utility.c + + + hc32_ll_wdt.c + 1 + ..\mcu\lib\src\hc32_ll_wdt.c + + + hc32f460_ll_interrupts_share.c + 1 + ..\mcu\lib\src\hc32f460_ll_interrupts_share.c + + + + + mcu + + + system_hc32f460.c + 1 + ..\mcu\cmsis\Device\HDSC\hc32f4xx\Source\system_hc32f460.c + + + startup_hc32f460.s + 2 + ..\mcu\startup\startup_hc32f460.s + + + + + Readme + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\HC32F460PETB\HC32F460PETB.h + + + + + + RTE\Device\HC32F460PETB\startup_hc32f460.s + + + + + + RTE\Device\HC32F460PETB\system_hc32f460.c + + + + + + RTE\Device\HC32F460PETB\system_hc32f460.h + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_MC_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\Network\Net_Config.c + + + + + + RTE\Network\Net_Config_ETH_0.h + + + + + + RTE\Network\Net_Config_TCP.h + + + + + + RTE\RTOS\board.c + + + + + + RTE\RTOS\rtconfig.h + + + + + + + + + + + GateWay + 0 + 1 + + + + + diff --git a/Project/EventRecorderStub.scvd b/Project/EventRecorderStub.scvd new file mode 100644 index 0000000..2956b29 --- /dev/null +++ b/Project/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/Project/JLinkSettings.ini b/Project/JLinkSettings.ini new file mode 100644 index 0000000..b06dcf5 --- /dev/null +++ b/Project/JLinkSettings.ini @@ -0,0 +1,35 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 1 +Device="Cortex-M4" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF diff --git a/Project/RTE/Device/HC32F460PETB/HC32F460PETB.h b/Project/RTE/Device/HC32F460PETB/HC32F460PETB.h new file mode 100644 index 0000000..a898c7c --- /dev/null +++ b/Project/RTE/Device/HC32F460PETB/HC32F460PETB.h @@ -0,0 +1,12351 @@ +/** + ******************************************************************************* + * @file HC32F460PETB.h + * @brief Headerfile for HC32F460PETB series MCU + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-01-15 CDT Modify headfile based on reference manual Rev1.5 + 2023-09-30 CDT Modify headfile based on reference manual Rev1.6 + Optimze for the unused bit definitions + 2024-11-08 CDT Modify CMP/DBGC/DCU/DMA/QSPI/TMR4/TMR6/I2C/I2S registers + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + **/ + +#ifndef __HC32F460PETB_H__ +#define __HC32F460PETB_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Configuration of the Cortex-M4 Processor and Core Peripherals + ******************************************************************************/ +#define __MPU_PRESENT 1 /*!< HC32F460PETB provides MPU */ +#define __VTOR_PRESENT 1 /*!< HC32F460PETB supported vector table registers */ +#define __NVIC_PRIO_BITS 4 /*!< HC32F460PETB uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/******************************************************************************* + * Interrupt Number Definition + ******************************************************************************/ +typedef enum { + NMI_IRQn = -14, /* Non Maskable */ + HardFault_IRQn = -13, /* Hard Fault */ + MemManageFault_IRQn = -12, /* MemManage Fault */ + BusFault_IRQn = -11, /* Bus Fault */ + UsageFault_IRQn = -10, /* Usage Fault */ + SVC_IRQn = -5, /* SVCall */ + DebugMonitor_IRQn = -4, /* DebugMonitor */ + PendSV_IRQn = -2, /* Pend SV */ + SysTick_IRQn = -1, /* System Tick */ + INT000_IRQn = 0, + INT001_IRQn = 1, + INT002_IRQn = 2, + INT003_IRQn = 3, + INT004_IRQn = 4, + INT005_IRQn = 5, + INT006_IRQn = 6, + INT007_IRQn = 7, + INT008_IRQn = 8, + INT009_IRQn = 9, + INT010_IRQn = 10, + INT011_IRQn = 11, + INT012_IRQn = 12, + INT013_IRQn = 13, + INT014_IRQn = 14, + INT015_IRQn = 15, + INT016_IRQn = 16, + INT017_IRQn = 17, + INT018_IRQn = 18, + INT019_IRQn = 19, + INT020_IRQn = 20, + INT021_IRQn = 21, + INT022_IRQn = 22, + INT023_IRQn = 23, + INT024_IRQn = 24, + INT025_IRQn = 25, + INT026_IRQn = 26, + INT027_IRQn = 27, + INT028_IRQn = 28, + INT029_IRQn = 29, + INT030_IRQn = 30, + INT031_IRQn = 31, + INT032_IRQn = 32, + INT033_IRQn = 33, + INT034_IRQn = 34, + INT035_IRQn = 35, + INT036_IRQn = 36, + INT037_IRQn = 37, + INT038_IRQn = 38, + INT039_IRQn = 39, + INT040_IRQn = 40, + INT041_IRQn = 41, + INT042_IRQn = 42, + INT043_IRQn = 43, + INT044_IRQn = 44, + INT045_IRQn = 45, + INT046_IRQn = 46, + INT047_IRQn = 47, + INT048_IRQn = 48, + INT049_IRQn = 49, + INT050_IRQn = 50, + INT051_IRQn = 51, + INT052_IRQn = 52, + INT053_IRQn = 53, + INT054_IRQn = 54, + INT055_IRQn = 55, + INT056_IRQn = 56, + INT057_IRQn = 57, + INT058_IRQn = 58, + INT059_IRQn = 59, + INT060_IRQn = 60, + INT061_IRQn = 61, + INT062_IRQn = 62, + INT063_IRQn = 63, + INT064_IRQn = 64, + INT065_IRQn = 65, + INT066_IRQn = 66, + INT067_IRQn = 67, + INT068_IRQn = 68, + INT069_IRQn = 69, + INT070_IRQn = 70, + INT071_IRQn = 71, + INT072_IRQn = 72, + INT073_IRQn = 73, + INT074_IRQn = 74, + INT075_IRQn = 75, + INT076_IRQn = 76, + INT077_IRQn = 77, + INT078_IRQn = 78, + INT079_IRQn = 79, + INT080_IRQn = 80, + INT081_IRQn = 81, + INT082_IRQn = 82, + INT083_IRQn = 83, + INT084_IRQn = 84, + INT085_IRQn = 85, + INT086_IRQn = 86, + INT087_IRQn = 87, + INT088_IRQn = 88, + INT089_IRQn = 89, + INT090_IRQn = 90, + INT091_IRQn = 91, + INT092_IRQn = 92, + INT093_IRQn = 93, + INT094_IRQn = 94, + INT095_IRQn = 95, + INT096_IRQn = 96, + INT097_IRQn = 97, + INT098_IRQn = 98, + INT099_IRQn = 99, + INT100_IRQn = 100, + INT101_IRQn = 101, + INT102_IRQn = 102, + INT103_IRQn = 103, + INT104_IRQn = 104, + INT105_IRQn = 105, + INT106_IRQn = 106, + INT107_IRQn = 107, + INT108_IRQn = 108, + INT109_IRQn = 109, + INT110_IRQn = 110, + INT111_IRQn = 111, + INT112_IRQn = 112, + INT113_IRQn = 113, + INT114_IRQn = 114, + INT115_IRQn = 115, + INT116_IRQn = 116, + INT117_IRQn = 117, + INT118_IRQn = 118, + INT119_IRQn = 119, + INT120_IRQn = 120, + INT121_IRQn = 121, + INT122_IRQn = 122, + INT123_IRQn = 123, + INT124_IRQn = 124, + INT125_IRQn = 125, + INT126_IRQn = 126, + INT127_IRQn = 127, + INT128_IRQn = 128, + INT129_IRQn = 129, + INT130_IRQn = 130, + INT131_IRQn = 131, + INT132_IRQn = 132, + INT133_IRQn = 133, + INT134_IRQn = 134, + INT135_IRQn = 135, + INT136_IRQn = 136, + INT137_IRQn = 137, + INT138_IRQn = 138, + INT139_IRQn = 139, + INT140_IRQn = 140, + INT141_IRQn = 141, + INT142_IRQn = 142, + INT143_IRQn = 143, + +} IRQn_Type; + +#include +#include + +/** + ******************************************************************************* + ** \brief Event number enumeration + ******************************************************************************/ +typedef enum { + EVT_SRC_SWI_IRQ0 = 0U, /* SWI_IRQ0 */ + EVT_SRC_SWI_IRQ1 = 1U, /* SWI_IRQ1 */ + EVT_SRC_SWI_IRQ2 = 2U, /* SWI_IRQ2 */ + EVT_SRC_SWI_IRQ3 = 3U, /* SWI_IRQ3 */ + EVT_SRC_SWI_IRQ4 = 4U, /* SWI_IRQ4 */ + EVT_SRC_SWI_IRQ5 = 5U, /* SWI_IRQ5 */ + EVT_SRC_SWI_IRQ6 = 6U, /* SWI_IRQ6 */ + EVT_SRC_SWI_IRQ7 = 7U, /* SWI_IRQ7 */ + EVT_SRC_SWI_IRQ8 = 8U, /* SWI_IRQ8 */ + EVT_SRC_SWI_IRQ9 = 9U, /* SWI_IRQ9 */ + EVT_SRC_SWI_IRQ10 = 10U, /* SWI_IRQ10 */ + EVT_SRC_SWI_IRQ11 = 11U, /* SWI_IRQ11 */ + EVT_SRC_SWI_IRQ12 = 12U, /* SWI_IRQ12 */ + EVT_SRC_SWI_IRQ13 = 13U, /* SWI_IRQ13 */ + EVT_SRC_SWI_IRQ14 = 14U, /* SWI_IRQ14 */ + EVT_SRC_SWI_IRQ15 = 15U, /* SWI_IRQ15 */ + EVT_SRC_SWI_IRQ16 = 16U, /* SWI_IRQ16 */ + EVT_SRC_SWI_IRQ17 = 17U, /* SWI_IRQ17 */ + EVT_SRC_SWI_IRQ18 = 18U, /* SWI_IRQ18 */ + EVT_SRC_SWI_IRQ19 = 19U, /* SWI_IRQ19 */ + EVT_SRC_SWI_IRQ20 = 20U, /* SWI_IRQ20 */ + EVT_SRC_SWI_IRQ21 = 21U, /* SWI_IRQ21 */ + EVT_SRC_SWI_IRQ22 = 22U, /* SWI_IRQ22 */ + EVT_SRC_SWI_IRQ23 = 23U, /* SWI_IRQ23 */ + EVT_SRC_SWI_IRQ24 = 24U, /* SWI_IRQ24 */ + EVT_SRC_SWI_IRQ25 = 25U, /* SWI_IRQ25 */ + EVT_SRC_SWI_IRQ26 = 26U, /* SWI_IRQ26 */ + EVT_SRC_SWI_IRQ27 = 27U, /* SWI_IRQ27 */ + EVT_SRC_SWI_IRQ28 = 28U, /* SWI_IRQ28 */ + EVT_SRC_SWI_IRQ29 = 29U, /* SWI_IRQ29 */ + EVT_SRC_SWI_IRQ30 = 30U, /* SWI_IRQ30 */ + EVT_SRC_SWI_IRQ31 = 31U, /* SWI_IRQ31 */ + + /* External Interrupt. */ + EVT_SRC_PORT_EIRQ0 = 0U, /* PORT_EIRQ0 */ + EVT_SRC_PORT_EIRQ1 = 1U, /* PORT_EIRQ1 */ + EVT_SRC_PORT_EIRQ2 = 2U, /* PORT_EIRQ2 */ + EVT_SRC_PORT_EIRQ3 = 3U, /* PORT_EIRQ3 */ + EVT_SRC_PORT_EIRQ4 = 4U, /* PORT_EIRQ4 */ + EVT_SRC_PORT_EIRQ5 = 5U, /* PORT_EIRQ5 */ + EVT_SRC_PORT_EIRQ6 = 6U, /* PORT_EIRQ6 */ + EVT_SRC_PORT_EIRQ7 = 7U, /* PORT_EIRQ7 */ + EVT_SRC_PORT_EIRQ8 = 8U, /* PORT_EIRQ8 */ + EVT_SRC_PORT_EIRQ9 = 9U, /* PORT_EIRQ9 */ + EVT_SRC_PORT_EIRQ10 = 10U, /* PORT_EIRQ10 */ + EVT_SRC_PORT_EIRQ11 = 11U, /* PORT_EIRQ11 */ + EVT_SRC_PORT_EIRQ12 = 12U, /* PORT_EIRQ12 */ + EVT_SRC_PORT_EIRQ13 = 13U, /* PORT_EIRQ13 */ + EVT_SRC_PORT_EIRQ14 = 14U, /* PORT_EIRQ14 */ + EVT_SRC_PORT_EIRQ15 = 15U, /* PORT_EIRQ15 */ + + /* DMAC */ + EVT_SRC_DMA1_TC0 = 32U, /* DMA1_TC0 */ + EVT_SRC_DMA1_TC1 = 33U, /* DMA1_TC1 */ + EVT_SRC_DMA1_TC2 = 34U, /* DMA1_TC2 */ + EVT_SRC_DMA1_TC3 = 35U, /* DMA1_TC3 */ + EVT_SRC_DMA2_TC0 = 36U, /* DMA2_TC0 */ + EVT_SRC_DMA2_TC1 = 37U, /* DMA2_TC1 */ + EVT_SRC_DMA2_TC2 = 38U, /* DMA2_TC2 */ + EVT_SRC_DMA2_TC3 = 39U, /* DMA2_TC3 */ + EVT_SRC_DMA1_BTC0 = 40U, /* DMA1_BTC0 */ + EVT_SRC_DMA1_BTC1 = 41U, /* DMA1_BTC1 */ + EVT_SRC_DMA1_BTC2 = 42U, /* DMA1_BTC2 */ + EVT_SRC_DMA1_BTC3 = 43U, /* DMA1_BTC3 */ + EVT_SRC_DMA2_BTC0 = 44U, /* DMA2_BTC0 */ + EVT_SRC_DMA2_BTC1 = 45U, /* DMA2_BTC1 */ + EVT_SRC_DMA2_BTC2 = 46U, /* DMA2_BTC2 */ + EVT_SRC_DMA2_BTC3 = 47U, /* DMA2_BTC3 */ + + /* EFM */ + EVT_SRC_EFM_OPTEND = 52U, /* EFM_OPTEND */ + + /* USB SOF */ + EVT_SRC_USBFS_SOF = 53U, /* USBFS_SOF */ + + /* DCU */ + EVT_SRC_DCU1 = 55U, /* DCU1 */ + EVT_SRC_DCU2 = 56U, /* DCU2 */ + EVT_SRC_DCU3 = 57U, /* DCU3 */ + EVT_SRC_DCU4 = 58U, /* DCU4 */ + + /* TIMER 0 */ + EVT_SRC_TMR0_1_CMP_A = 64U, /* TMR01_GCMA */ + EVT_SRC_TMR0_1_CMP_B = 65U, /* TMR01_GCMB */ + EVT_SRC_TMR0_2_CMP_A = 66U, /* TMR02_GCMA */ + EVT_SRC_TMR0_2_CMP_B = 67U, /* TMR02_GCMB */ + + /* RTC */ + EVT_SRC_RTC_ALM = 81U, /* RTC_ALM */ + EVT_SRC_RTC_PRD = 82U, /* RTC_PRD */ + + /* TIMER 6 */ + EVT_SRC_TMR6_1_GCMP_A = 96U, /* TMR61_GCMA */ + EVT_SRC_TMR6_1_GCMP_B = 97U, /* TMR61_GCMB */ + EVT_SRC_TMR6_1_GCMP_C = 98U, /* TMR61_GCMC */ + EVT_SRC_TMR6_1_GCMP_D = 99U, /* TMR61_GCMD */ + EVT_SRC_TMR6_1_GCMP_E = 100U, /* TMR61_GCME */ + EVT_SRC_TMR6_1_GCMP_F = 101U, /* TMR61_GCMF */ + EVT_SRC_TMR6_1_OVF = 102U, /* TMR61_GOVF */ + EVT_SRC_TMR6_1_UDF = 103U, /* TMR61_GUDF */ + EVT_SRC_TMR6_1_SCMP_A = 107U, /* TMR61_SCMA */ + EVT_SRC_TMR6_1_SCMP_B = 108U, /* TMR61_SCMB */ + EVT_SRC_TMR6_2_GCMP_A = 112U, /* TMR62_GCMA */ + EVT_SRC_TMR6_2_GCMP_B = 113U, /* TMR62_GCMB */ + EVT_SRC_TMR6_2_GCMP_C = 114U, /* TMR62_GCMC */ + EVT_SRC_TMR6_2_GCMP_D = 115U, /* TMR62_GCMD */ + EVT_SRC_TMR6_2_GCMP_E = 116U, /* TMR62_GCME */ + EVT_SRC_TMR6_2_GCMP_F = 117U, /* TMR62_GCMF */ + EVT_SRC_TMR6_2_OVF = 118U, /* TMR62_GOVF */ + EVT_SRC_TMR6_2_UDF = 119U, /* TMR62_GUDF */ + EVT_SRC_TMR6_2_SCMP_A = 123U, /* TMR62_SCMA */ + EVT_SRC_TMR6_2_SCMP_B = 124U, /* TMR62_SCMB */ + EVT_SRC_TMR6_3_GCMP_A = 128U, /* TMR63_GCMA */ + EVT_SRC_TMR6_3_GCMP_B = 129U, /* TMR63_GCMB */ + EVT_SRC_TMR6_3_GCMP_C = 130U, /* TMR63_GCMC */ + EVT_SRC_TMR6_3_GCMP_D = 131U, /* TMR63_GCMD */ + EVT_SRC_TMR6_3_GCMP_E = 132U, /* TMR63_GCME */ + EVT_SRC_TMR6_3_GCMP_F = 133U, /* TMR63_GCMF */ + EVT_SRC_TMR6_3_OVF = 134U, /* TMR63_GOVF */ + EVT_SRC_TMR6_3_UDF = 135U, /* TMR63_GUDF */ + EVT_SRC_TMR6_3_SCMP_A = 139U, /* TMR63_SCMA */ + EVT_SRC_TMR6_3_SCMP_B = 140U, /* TMR63_SCMB */ + + /* TIMER A */ + EVT_SRC_TMRA_1_OVF = 256U, /* TMRA1_OVF */ + EVT_SRC_TMRA_1_UDF = 257U, /* TMRA1_UDF */ + EVT_SRC_TMRA_1_CMP = 258U, /* TMRA1_CMP */ + EVT_SRC_TMRA_2_OVF = 259U, /* TMRA2_OVF */ + EVT_SRC_TMRA_2_UDF = 260U, /* TMRA2_UDF */ + EVT_SRC_TMRA_2_CMP = 261U, /* TMRA2_CMP */ + EVT_SRC_TMRA_3_OVF = 262U, /* TMRA3_OVF */ + EVT_SRC_TMRA_3_UDF = 263U, /* TMRA3_UDF */ + EVT_SRC_TMRA_3_CMP = 264U, /* TMRA3_CMP */ + EVT_SRC_TMRA_4_OVF = 265U, /* TMRA4_OVF */ + EVT_SRC_TMRA_4_UDF = 266U, /* TMRA4_UDF */ + EVT_SRC_TMRA_4_CMP = 267U, /* TMRA4_CMP */ + EVT_SRC_TMRA_5_OVF = 268U, /* TMRA5_OVF */ + EVT_SRC_TMRA_5_UDF = 269U, /* TMRA5_UDF */ + EVT_SRC_TMRA_5_CMP = 270U, /* TMRA5_CMP */ + EVT_SRC_TMRA_6_OVF = 272U, /* TMRA6_OVF */ + EVT_SRC_TMRA_6_UDF = 273U, /* TMRA6_UDF */ + EVT_SRC_TMRA_6_CMP = 274U, /* TMRA6_CMP */ + + /* USART */ + EVT_SRC_USART1_EI = 278U, /* USART1_EI */ + EVT_SRC_USART1_RI = 279U, /* USART1_RI */ + EVT_SRC_USART1_TI = 280U, /* USART1_TI */ + EVT_SRC_USART1_TCI = 281U, /* USART1_TCI */ + EVT_SRC_USART1_RTO = 282U, /* USART1_RTO */ + EVT_SRC_USART2_EI = 283U, /* USART2_EI */ + EVT_SRC_USART2_RI = 284U, /* USART2_RI */ + EVT_SRC_USART2_TI = 285U, /* USART2_TI */ + EVT_SRC_USART2_TCI = 286U, /* USART2_TCI */ + EVT_SRC_USART2_RTO = 287U, /* USART2_RTO */ + EVT_SRC_USART3_EI = 288U, /* USART3_EI */ + EVT_SRC_USART3_RI = 289U, /* USART3_RI */ + EVT_SRC_USART3_TI = 290U, /* USART3_TI */ + EVT_SRC_USART3_TCI = 291U, /* USART3_TCI */ + EVT_SRC_USART3_RTO = 292U, /* USART3_RTO */ + EVT_SRC_USART4_EI = 293U, /* USART4_EI */ + EVT_SRC_USART4_RI = 294U, /* USART4_RI */ + EVT_SRC_USART4_TI = 295U, /* USART4_TI */ + EVT_SRC_USART4_TCI = 296U, /* USART4_TCI */ + EVT_SRC_USART4_RTO = 297U, /* USART4_RTO */ + + /* SPI */ + EVT_SRC_SPI1_SPRI = 299U, /* SPI1_SPRI */ + EVT_SRC_SPI1_SPTI = 300U, /* SPI1_SPTI */ + EVT_SRC_SPI1_SPII = 301U, /* SPI1_SPII */ + EVT_SRC_SPI1_SPEI = 302U, /* SPI1_SPEI */ + EVT_SRC_SPI1_SPTEND = 303U, /* SPI1_SPTEND */ + EVT_SRC_SPI2_SPRI = 304U, /* SPI2_SPRI */ + EVT_SRC_SPI2_SPTI = 305U, /* SPI2_SPTI */ + EVT_SRC_SPI2_SPII = 306U, /* SPI2_SPII */ + EVT_SRC_SPI2_SPEI = 307U, /* SPI2_SPEI */ + EVT_SRC_SPI2_SPTEND = 308U, /* SPI2_SPTEND */ + EVT_SRC_SPI3_SPRI = 309U, /* SPI3_SPRI */ + EVT_SRC_SPI3_SPTI = 310U, /* SPI3_SPTI */ + EVT_SRC_SPI3_SPII = 311U, /* SPI3_SPII */ + EVT_SRC_SPI3_SPEI = 312U, /* SPI3_SPEI */ + EVT_SRC_SPI3_SPTEND = 313U, /* SPI3_SPTEND */ + EVT_SRC_SPI4_SPRI = 314U, /* SPI4_SPRI */ + EVT_SRC_SPI4_SPTI = 315U, /* SPI4_SPTI */ + EVT_SRC_SPI4_SPII = 316U, /* SPI4_SPII */ + EVT_SRC_SPI4_SPEI = 317U, /* SPI4_SPEI */ + EVT_SRC_SPI4_SPTEND = 318U, /* SPI4_SPTEND */ + + /* AOS */ + EVT_SRC_AOS_STRG = 319U, /* AOS_STRG */ + + /* TIMER 4 */ + EVT_SRC_TMR4_1_SCMP0 = 368U, /* TMR41_SCM0 */ + EVT_SRC_TMR4_1_SCMP1 = 369U, /* TMR41_SCM1 */ + EVT_SRC_TMR4_1_SCMP2 = 370U, /* TMR41_SCM2 */ + EVT_SRC_TMR4_1_SCMP3 = 371U, /* TMR41_SCM3 */ + EVT_SRC_TMR4_1_SCMP4 = 372U, /* TMR41_SCM4 */ + EVT_SRC_TMR4_1_SCMP5 = 373U, /* TMR41_SCM5 */ + EVT_SRC_TMR4_2_SCMP0 = 374U, /* TMR42_SCM0 */ + EVT_SRC_TMR4_2_SCMP1 = 375U, /* TMR42_SCM1 */ + EVT_SRC_TMR4_2_SCMP2 = 376U, /* TMR42_SCM2 */ + EVT_SRC_TMR4_2_SCMP3 = 377U, /* TMR42_SCM3 */ + EVT_SRC_TMR4_2_SCMP4 = 378U, /* TMR42_SCM4 */ + EVT_SRC_TMR4_2_SCMP5 = 379U, /* TMR42_SCM5 */ + EVT_SRC_TMR4_3_SCMP0 = 384U, /* TMR43_SCM0 */ + EVT_SRC_TMR4_3_SCMP1 = 385U, /* TMR43_SCM1 */ + EVT_SRC_TMR4_3_SCMP2 = 386U, /* TMR43_SCM2 */ + EVT_SRC_TMR4_3_SCMP3 = 387U, /* TMR43_SCM3 */ + EVT_SRC_TMR4_3_SCMP4 = 388U, /* TMR43_SCM4 */ + EVT_SRC_TMR4_3_SCMP5 = 389U, /* TMR43_SCM5 */ + + /* EVENT PORT */ + EVT_SRC_EVENT_PORT1 = 394U, /* EVENT_PORT1 */ + EVT_SRC_EVENT_PORT2 = 395U, /* EVENT_PORT2 */ + EVT_SRC_EVENT_PORT3 = 396U, /* EVENT_PORT3 */ + EVT_SRC_EVENT_PORT4 = 397U, /* EVENT_PORT4 */ + + /* I2S */ + EVT_SRC_I2S1_TXIRQOUT = 400U, /* I2S1_TXIRQOUT */ + EVT_SRC_I2S1_RXIRQOUT = 401U, /* I2S1_RXIRQOUT */ + EVT_SRC_I2S2_TXIRQOUT = 403U, /* I2S2_TXIRQOUT */ + EVT_SRC_I2S2_RXIRQOUT = 404U, /* I2S2_RXIRQOUT */ + EVT_SRC_I2S3_TXIRQOUT = 406U, /* I2S3_TXIRQOUT */ + EVT_SRC_I2S3_RXIRQOUT = 407U, /* I2S3_RXIRQOUT */ + EVT_SRC_I2S4_TXIRQOUT = 409U, /* I2S4_TXIRQOUT */ + EVT_SRC_I2S4_RXIRQOUT = 410U, /* I2S4_RXIRQOUT */ + + /* COMPARATOR */ + EVT_SRC_CMP1 = 416U, /* ACMP1 */ + EVT_SRC_CMP2 = 417U, /* ACMP1 */ + EVT_SRC_CMP3 = 418U, /* ACMP1 */ + + /* I2C */ + EVT_SRC_I2C1_RXI = 420U, /* I2C1_RXI */ + EVT_SRC_I2C1_TXI = 421U, /* I2C1_TXI */ + EVT_SRC_I2C1_TEI = 422U, /* I2C1_TEI */ + EVT_SRC_I2C1_EEI = 423U, /* I2C1_EEI */ + EVT_SRC_I2C2_RXI = 424U, /* I2C2_RXI */ + EVT_SRC_I2C2_TXI = 425U, /* I2C2_TXI */ + EVT_SRC_I2C2_TEI = 426U, /* I2C2_TEI */ + EVT_SRC_I2C2_EEI = 427U, /* I2C2_EEI */ + EVT_SRC_I2C3_RXI = 428U, /* I2C3_RXI */ + EVT_SRC_I2C3_TXI = 429U, /* I2C3_TXI */ + EVT_SRC_I2C3_TEI = 430U, /* I2C3_TEI */ + EVT_SRC_I2C3_EEI = 431U, /* I2C3_EEI */ + + /* LVD */ + EVT_SRC_LVD1 = 433U, /* LVD1 */ + EVT_SRC_LVD2 = 434U, /* LVD2 */ + + /* OTS */ + EVT_SRC_OTS = 435U, /* OTS */ + + /* WDT */ + EVT_SRC_WDT_REFUDF = 439U, /* WDT_REFUDF */ + + /* ADC */ + EVT_SRC_ADC1_EOCA = 448U, /* ADC1_EOCA */ + EVT_SRC_ADC1_EOCB = 449U, /* ADC1_EOCB */ + EVT_SRC_ADC1_CHCMP = 450U, /* ADC1_CHCMP */ + EVT_SRC_ADC1_SEQCMP = 451U, /* ADC1_SEQCMP */ + EVT_SRC_ADC2_EOCA = 452U, /* ADC2_EOCA */ + EVT_SRC_ADC2_EOCB = 453U, /* ADC2_EOCB */ + EVT_SRC_ADC2_CHCMP = 454U, /* ADC2_CHCMP */ + EVT_SRC_ADC2_SEQCMP = 455U, /* ADC2_SEQCMP */ + + /* TRNG */ + EVT_SRC_TRNG_END = 456U, /* TRNG_END */ + + /* SDIO */ + EVT_SRC_SDIOC1_DMAR = 480U, /* SDIOC1_DMAR */ + EVT_SRC_SDIOC1_DMAW = 481U, /* SDIOC1_DMAW */ + EVT_SRC_SDIOC2_DMAR = 483U, /* SDIOC2_DMAR */ + EVT_SRC_SDIOC2_DMAW = 484U, /* SDIOC2_DMAW */ + EVT_SRC_MAX = 511U, +} en_event_src_t; + +/** + ******************************************************************************* + ** \brief Interrupt number enumeration + ******************************************************************************/ +typedef enum { + INT_SRC_SWI_IRQ0 = 0U, /* SWI_IRQ0 */ + INT_SRC_SWI_IRQ1 = 1U, /* SWI_IRQ1 */ + INT_SRC_SWI_IRQ2 = 2U, /* SWI_IRQ2 */ + INT_SRC_SWI_IRQ3 = 3U, /* SWI_IRQ3 */ + INT_SRC_SWI_IRQ4 = 4U, /* SWI_IRQ4 */ + INT_SRC_SWI_IRQ5 = 5U, /* SWI_IRQ5 */ + INT_SRC_SWI_IRQ6 = 6U, /* SWI_IRQ6 */ + INT_SRC_SWI_IRQ7 = 7U, /* SWI_IRQ7 */ + INT_SRC_SWI_IRQ8 = 8U, /* SWI_IRQ8 */ + INT_SRC_SWI_IRQ9 = 9U, /* SWI_IRQ9 */ + INT_SRC_SWI_IRQ10 = 10U, /* SWI_IRQ10 */ + INT_SRC_SWI_IRQ11 = 11U, /* SWI_IRQ11 */ + INT_SRC_SWI_IRQ12 = 12U, /* SWI_IRQ12 */ + INT_SRC_SWI_IRQ13 = 13U, /* SWI_IRQ13 */ + INT_SRC_SWI_IRQ14 = 14U, /* SWI_IRQ14 */ + INT_SRC_SWI_IRQ15 = 15U, /* SWI_IRQ15 */ + INT_SRC_SWI_IRQ16 = 16U, /* SWI_IRQ16 */ + INT_SRC_SWI_IRQ17 = 17U, /* SWI_IRQ17 */ + INT_SRC_SWI_IRQ18 = 18U, /* SWI_IRQ18 */ + INT_SRC_SWI_IRQ19 = 19U, /* SWI_IRQ19 */ + INT_SRC_SWI_IRQ20 = 20U, /* SWI_IRQ20 */ + INT_SRC_SWI_IRQ21 = 21U, /* SWI_IRQ21 */ + INT_SRC_SWI_IRQ22 = 22U, /* SWI_IRQ22 */ + INT_SRC_SWI_IRQ23 = 23U, /* SWI_IRQ23 */ + INT_SRC_SWI_IRQ24 = 24U, /* SWI_IRQ24 */ + INT_SRC_SWI_IRQ25 = 25U, /* SWI_IRQ25 */ + INT_SRC_SWI_IRQ26 = 26U, /* SWI_IRQ26 */ + INT_SRC_SWI_IRQ27 = 27U, /* SWI_IRQ27 */ + INT_SRC_SWI_IRQ28 = 28U, /* SWI_IRQ28 */ + INT_SRC_SWI_IRQ29 = 29U, /* SWI_IRQ29 */ + INT_SRC_SWI_IRQ30 = 30U, /* SWI_IRQ30 */ + INT_SRC_SWI_IRQ31 = 31U, /* SWI_IRQ31 */ + + /* External Interrupt. */ + INT_SRC_PORT_EIRQ0 = 0U, /* PORT_EIRQ0 */ + INT_SRC_PORT_EIRQ1 = 1U, /* PORT_EIRQ1 */ + INT_SRC_PORT_EIRQ2 = 2U, /* PORT_EIRQ2 */ + INT_SRC_PORT_EIRQ3 = 3U, /* PORT_EIRQ3 */ + INT_SRC_PORT_EIRQ4 = 4U, /* PORT_EIRQ4 */ + INT_SRC_PORT_EIRQ5 = 5U, /* PORT_EIRQ5 */ + INT_SRC_PORT_EIRQ6 = 6U, /* PORT_EIRQ6 */ + INT_SRC_PORT_EIRQ7 = 7U, /* PORT_EIRQ7 */ + INT_SRC_PORT_EIRQ8 = 8U, /* PORT_EIRQ8 */ + INT_SRC_PORT_EIRQ9 = 9U, /* PORT_EIRQ9 */ + INT_SRC_PORT_EIRQ10 = 10U, /* PORT_EIRQ10 */ + INT_SRC_PORT_EIRQ11 = 11U, /* PORT_EIRQ11 */ + INT_SRC_PORT_EIRQ12 = 12U, /* PORT_EIRQ12 */ + INT_SRC_PORT_EIRQ13 = 13U, /* PORT_EIRQ13 */ + INT_SRC_PORT_EIRQ14 = 14U, /* PORT_EIRQ14 */ + INT_SRC_PORT_EIRQ15 = 15U, /* PORT_EIRQ15 */ + + /* DMAC */ + INT_SRC_DMA1_TC0 = 32U, /* DMA1_TC0 */ + INT_SRC_DMA1_TC1 = 33U, /* DMA1_TC1 */ + INT_SRC_DMA1_TC2 = 34U, /* DMA1_TC2 */ + INT_SRC_DMA1_TC3 = 35U, /* DMA1_TC3 */ + INT_SRC_DMA2_TC0 = 36U, /* DMA2_TC0 */ + INT_SRC_DMA2_TC1 = 37U, /* DMA2_TC1 */ + INT_SRC_DMA2_TC2 = 38U, /* DMA2_TC2 */ + INT_SRC_DMA2_TC3 = 39U, /* DMA2_TC3 */ + INT_SRC_DMA1_BTC0 = 40U, /* DMA1_BTC0 */ + INT_SRC_DMA1_BTC1 = 41U, /* DMA1_BTC1 */ + INT_SRC_DMA1_BTC2 = 42U, /* DMA1_BTC2 */ + INT_SRC_DMA1_BTC3 = 43U, /* DMA1_BTC3 */ + INT_SRC_DMA2_BTC0 = 44U, /* DMA2_BTC0 */ + INT_SRC_DMA2_BTC1 = 45U, /* DMA2_BTC1 */ + INT_SRC_DMA2_BTC2 = 46U, /* DMA2_BTC2 */ + INT_SRC_DMA2_BTC3 = 47U, /* DMA2_BTC3 */ + INT_SRC_DMA1_ERR = 48U, /* DMA1_ERR */ + INT_SRC_DMA2_ERR = 49U, /* DMA2_ERR */ + + /* EFM */ + INT_SRC_EFM_PEERR = 50U, /* EFM_PEERR */ + INT_SRC_EFM_COLERR = 51U, /* EFM_COLERR */ + INT_SRC_EFM_OPTEND = 52U, /* EFM_OPTEND */ + + /* QSPI */ + INT_SRC_QSPI_INTR = 54U, /* QSPI_INTR */ + + /* DCU */ + INT_SRC_DCU1 = 55U, /* DCU1 */ + INT_SRC_DCU2 = 56U, /* DCU2 */ + INT_SRC_DCU3 = 57U, /* DCU3 */ + INT_SRC_DCU4 = 58U, /* DCU4 */ + + /* TIMER 0 */ + INT_SRC_TMR0_1_CMP_A = 64U, /* TMR01_GCMA */ + INT_SRC_TMR0_1_CMP_B = 65U, /* TMR01_GCMB */ + INT_SRC_TMR0_2_CMP_A = 66U, /* TMR02_GCMA */ + INT_SRC_TMR0_2_CMP_B = 67U, /* TMR02_GCMB */ + + /* RTC */ + INT_SRC_RTC_ALM = 81U, /* RTC_ALM */ + INT_SRC_RTC_PRD = 82U, /* RTC_PRD */ + + /* XTAL32 stop */ + INT_SRC_XTAL32_STOP = 84U, /* XTAL32_STOP */ + + /* XTAL stop */ + INT_SRC_XTAL_STOP = 85U, /* XTAL_STOP */ + + /* wake-up timer */ + INT_SRC_WKTM_PRD = 86U, /* WKTM_PRD */ + + /* SWDT */ + INT_SRC_SWDT_REFUDF = 87U, /* SWDT_REFUDF */ + + /* TIMER 6 */ + INT_SRC_TMR6_1_GCMP_A = 96U, /* TMR61_GCMA */ + INT_SRC_TMR6_1_GCMP_B = 97U, /* TMR61_GCMB */ + INT_SRC_TMR6_1_GCMP_C = 98U, /* TMR61_GCMC */ + INT_SRC_TMR6_1_GCMP_D = 99U, /* TMR61_GCMD */ + INT_SRC_TMR6_1_GCMP_E = 100U, /* TMR61_GCME */ + INT_SRC_TMR6_1_GCMP_F = 101U, /* TMR61_GCMF */ + INT_SRC_TMR6_1_OVF = 102U, /* TMR61_GOVF */ + INT_SRC_TMR6_1_UDF = 103U, /* TMR61_GUDF */ + INT_SRC_TMR6_1_DTE = 104U, /* TMR61_GDTE */ + INT_SRC_TMR6_1_SCMP_A = 107U, /* TMR61_SCMA */ + INT_SRC_TMR6_1_SCMP_B = 108U, /* TMR61_SCMB */ + INT_SRC_TMR6_2_GCMP_A = 112U, /* TMR62_GCMA */ + INT_SRC_TMR6_2_GCMP_B = 113U, /* TMR62_GCMB */ + INT_SRC_TMR6_2_GCMP_C = 114U, /* TMR62_GCMC */ + INT_SRC_TMR6_2_GCMP_D = 115U, /* TMR62_GCMD */ + INT_SRC_TMR6_2_GCMP_E = 116U, /* TMR62_GCME */ + INT_SRC_TMR6_2_GCMP_F = 117U, /* TMR62_GCMF */ + INT_SRC_TMR6_2_OVF = 118U, /* TMR62_GOVF */ + INT_SRC_TMR6_2_UDF = 119U, /* TMR62_GUDF */ + INT_SRC_TMR6_2_DTE = 120U, /* TMR62_GDTE */ + INT_SRC_TMR6_2_SCMP_A = 123U, /* TMR62_SCMA */ + INT_SRC_TMR6_2_SCMP_B = 124U, /* TMR62_SCMB */ + INT_SRC_TMR6_3_GCMP_A = 128U, /* TMR63_GCMA */ + INT_SRC_TMR6_3_GCMP_B = 129U, /* TMR63_GCMB */ + INT_SRC_TMR6_3_GCMP_C = 130U, /* TMR63_GCMC */ + INT_SRC_TMR6_3_GCMP_D = 131U, /* TMR63_GCMD */ + INT_SRC_TMR6_3_GCMP_E = 132U, /* TMR63_GCME */ + INT_SRC_TMR6_3_GCMP_F = 133U, /* TMR63_GCMF */ + INT_SRC_TMR6_3_OVF = 134U, /* TMR63_GOVF */ + INT_SRC_TMR6_3_UDF = 135U, /* TMR63_GUDF */ + INT_SRC_TMR6_3_DTE = 136U, /* TMR63_GDTE */ + INT_SRC_TMR6_3_SCMP_A = 139U, /* TMR63_SCMA */ + INT_SRC_TMR6_3_SCMP_B = 140U, /* TMR63_SCMB */ + + /* TIMER A */ + INT_SRC_TMRA_1_OVF = 256U, /* TMRA1_OVF */ + INT_SRC_TMRA_1_UDF = 257U, /* TMRA1_UDF */ + INT_SRC_TMRA_1_CMP = 258U, /* TMRA1_CMP */ + INT_SRC_TMRA_2_OVF = 259U, /* TMRA2_OVF */ + INT_SRC_TMRA_2_UDF = 260U, /* TMRA2_UDF */ + INT_SRC_TMRA_2_CMP = 261U, /* TMRA2_CMP */ + INT_SRC_TMRA_3_OVF = 262U, /* TMRA3_OVF */ + INT_SRC_TMRA_3_UDF = 263U, /* TMRA3_UDF */ + INT_SRC_TMRA_3_CMP = 264U, /* TMRA3_CMP */ + INT_SRC_TMRA_4_OVF = 265U, /* TMRA4_OVF */ + INT_SRC_TMRA_4_UDF = 266U, /* TMRA4_UDF */ + INT_SRC_TMRA_4_CMP = 267U, /* TMRA4_CMP */ + INT_SRC_TMRA_5_OVF = 268U, /* TMRA5_OVF */ + INT_SRC_TMRA_5_UDF = 269U, /* TMRA5_UDF */ + INT_SRC_TMRA_5_CMP = 270U, /* TMRA5_CMP */ + INT_SRC_TMRA_6_OVF = 272U, /* TMRA6_OVF */ + INT_SRC_TMRA_6_UDF = 273U, /* TMRA6_UDF */ + INT_SRC_TMRA_6_CMP = 274U, /* TMRA6_CMP */ + + /* USB FS */ + INT_SRC_USBFS_GLB = 275U, /* USBFS_GLB */ + + /* USRAT */ + INT_SRC_USART1_EI = 278U, /* USART1_EI */ + INT_SRC_USART1_RI = 279U, /* USART1_RI */ + INT_SRC_USART1_TI = 280U, /* USART1_TI */ + INT_SRC_USART1_TCI = 281U, /* USART1_TCI */ + INT_SRC_USART1_RTO = 282U, /* USART1_RTO */ + INT_SRC_USART1_WUPI = 432U, /* USART1_WUPI */ + INT_SRC_USART2_EI = 283U, /* USART2_EI */ + INT_SRC_USART2_RI = 284U, /* USART2_RI */ + INT_SRC_USART2_TI = 285U, /* USART2_TI */ + INT_SRC_USART2_TCI = 286U, /* USART2_TCI */ + INT_SRC_USART2_RTO = 287U, /* USART2_RTO */ + INT_SRC_USART3_EI = 288U, /* USART3_EI */ + INT_SRC_USART3_RI = 289U, /* USART3_RI */ + INT_SRC_USART3_TI = 290U, /* USART3_TI */ + INT_SRC_USART3_TCI = 291U, /* USART3_TCI */ + INT_SRC_USART3_RTO = 292U, /* USART3_RTO */ + INT_SRC_USART4_EI = 293U, /* USART4_EI */ + INT_SRC_USART4_RI = 294U, /* USART4_RI */ + INT_SRC_USART4_TI = 295U, /* USART4_TI */ + INT_SRC_USART4_TCI = 296U, /* USART4_TCI */ + INT_SRC_USART4_RTO = 297U, /* USART4_RTO */ + + /* SPI */ + INT_SRC_SPI1_SPRI = 299U, /* SPI1_SPRI */ + INT_SRC_SPI1_SPTI = 300U, /* SPI1_SPTI */ + INT_SRC_SPI1_SPII = 301U, /* SPI1_SPII */ + INT_SRC_SPI1_SPEI = 302U, /* SPI1_SPEI */ + INT_SRC_SPI2_SPRI = 304U, /* SPI2_SPRI */ + INT_SRC_SPI2_SPTI = 305U, /* SPI2_SPTI */ + INT_SRC_SPI2_SPII = 306U, /* SPI2_SPII */ + INT_SRC_SPI2_SPEI = 307U, /* SPI2_SPEI */ + INT_SRC_SPI3_SPRI = 309U, /* SPI3_SPRI */ + INT_SRC_SPI3_SPTI = 310U, /* SPI3_SPTI */ + INT_SRC_SPI3_SPII = 311U, /* SPI3_SPII */ + INT_SRC_SPI3_SPEI = 312U, /* SPI3_SPEI */ + INT_SRC_SPI4_SPRI = 314U, /* SPI4_SPRI */ + INT_SRC_SPI4_SPTI = 315U, /* SPI4_SPTI */ + INT_SRC_SPI4_SPII = 316U, /* SPI4_SPII */ + INT_SRC_SPI4_SPEI = 317U, /* SPI4_SPEI */ + + /* TIMER 4 */ + INT_SRC_TMR4_1_GCMP_UH = 320U, /* TMR41_GCMUH */ + INT_SRC_TMR4_1_GCMP_UL = 321U, /* TMR41_GCMUL */ + INT_SRC_TMR4_1_GCMP_VH = 322U, /* TMR41_GCMVH */ + INT_SRC_TMR4_1_GCMP_VL = 323U, /* TMR41_GCMVL */ + INT_SRC_TMR4_1_GCMP_WH = 324U, /* TMR41_GCMWH */ + INT_SRC_TMR4_1_GCMP_WL = 325U, /* TMR41_GCMWL */ + INT_SRC_TMR4_1_OVF = 326U, /* TMR41_GOVF */ + INT_SRC_TMR4_1_UDF = 327U, /* TMR41_GUDF */ + INT_SRC_TMR4_1_RELOAD_U = 328U, /* TMR41_RLOU */ + INT_SRC_TMR4_1_RELOAD_V = 329U, /* TMR41_RLOV */ + INT_SRC_TMR4_1_RELOAD_W = 330U, /* TMR41_RLOW */ + INT_SRC_TMR4_2_GCMP_UH = 336U, /* TMR42_GCMUH */ + INT_SRC_TMR4_2_GCMP_UL = 337U, /* TMR42_GCMUL */ + INT_SRC_TMR4_2_GCMP_VH = 338U, /* TMR42_GCMVH */ + INT_SRC_TMR4_2_GCMP_VL = 339U, /* TMR42_GCMVL */ + INT_SRC_TMR4_2_GCMP_WH = 340U, /* TMR42_GCMWH */ + INT_SRC_TMR4_2_GCMP_WL = 341U, /* TMR42_GCMWL */ + INT_SRC_TMR4_2_OVF = 342U, /* TMR42_GOVF */ + INT_SRC_TMR4_2_UDF = 343U, /* TMR42_GUDF */ + INT_SRC_TMR4_2_RELOAD_U = 344U, /* TMR42_RLOU */ + INT_SRC_TMR4_2_RELOAD_V = 345U, /* TMR42_RLOV */ + INT_SRC_TMR4_2_RELOAD_W = 346U, /* TMR42_RLOW */ + INT_SRC_TMR4_3_GCMP_UH = 352U, /* TMR43_GCMUH */ + INT_SRC_TMR4_3_GCMP_UL = 353U, /* TMR43_GCMUL */ + INT_SRC_TMR4_3_GCMP_VH = 354U, /* TMR43_GCMVH */ + INT_SRC_TMR4_3_GCMP_VL = 355U, /* TMR43_GCMVL */ + INT_SRC_TMR4_3_GCMP_WH = 356U, /* TMR43_GCMWH */ + INT_SRC_TMR4_3_GCMP_WL = 357U, /* TMR43_GCMWL */ + INT_SRC_TMR4_3_OVF = 358U, /* TMR43_GOVF */ + INT_SRC_TMR4_3_UDF = 359U, /* TMR43_GUDF */ + INT_SRC_TMR4_3_RELOAD_U = 360U, /* TMR43_RLOU */ + INT_SRC_TMR4_3_RELOAD_V = 361U, /* TMR43_RLOV */ + INT_SRC_TMR4_3_RELOAD_W = 362U, /* TMR43_RLOW */ + + /* EMB */ + INT_SRC_EMB_GR0 = 390U, /* EMB_GR0 */ + INT_SRC_EMB_GR1 = 391U, /* EMB_GR1 */ + INT_SRC_EMB_GR2 = 392U, /* EMB_GR2 */ + INT_SRC_EMB_GR3 = 393U, /* EMB_GR3 */ + + /* EVENT PORT */ + INT_SRC_EVENT_PORT1 = 394U, /* EVENT_PORT1 */ + INT_SRC_EVENT_PORT2 = 395U, /* EVENT_PORT2 */ + INT_SRC_EVENT_PORT3 = 396U, /* EVENT_PORT3 */ + INT_SRC_EVENT_PORT4 = 397U, /* EVENT_PORT4 */ + + /* I2S */ + INT_SRC_I2S1_TXIRQOUT = 400U, /* I2S1_TXIRQOUT */ + INT_SRC_I2S1_RXIRQOUT = 401U, /* I2S1_RXIRQOUT */ + INT_SRC_I2S1_ERRIRQOUT = 402U, /* I2S1_ERRIRQOUT */ + INT_SRC_I2S2_TXIRQOUT = 403U, /* I2S2_TXIRQOUT */ + INT_SRC_I2S2_RXIRQOUT = 404U, /* I2S2_RXIRQOUT */ + INT_SRC_I2S2_ERRIRQOUT = 405U, /* I2S2_ERRIRQOUT */ + INT_SRC_I2S3_TXIRQOUT = 406U, /* I2S3_TXIRQOUT */ + INT_SRC_I2S3_RXIRQOUT = 407U, /* I2S3_RXIRQOUT */ + INT_SRC_I2S3_ERRIRQOUT = 408U, /* I2S3_ERRIRQOUT */ + INT_SRC_I2S4_TXIRQOUT = 409U, /* I2S4_TXIRQOUT */ + INT_SRC_I2S4_RXIRQOUT = 410U, /* I2S4_RXIRQOUT */ + INT_SRC_I2S4_ERRIRQOUT = 411U, /* I2S4_ERRIRQOUT */ + + /* COMPARATOR */ + INT_SRC_CMP1 = 416U, /* ACMP1 */ + INT_SRC_CMP2 = 417U, /* ACMP2 */ + INT_SRC_CMP3 = 418U, /* ACMP3 */ + + /* I2C */ + INT_SRC_I2C1_RXI = 420U, /* I2C1_RXI */ + INT_SRC_I2C1_TXI = 421U, /* I2C1_TXI */ + INT_SRC_I2C1_TEI = 422U, /* I2C1_TEI */ + INT_SRC_I2C1_EEI = 423U, /* I2C1_EEI */ + INT_SRC_I2C2_RXI = 424U, /* I2C2_RXI */ + INT_SRC_I2C2_TXI = 425U, /* I2C2_TXI */ + INT_SRC_I2C2_TEI = 426U, /* I2C2_TEI */ + INT_SRC_I2C2_EEI = 427U, /* I2C2_EEI */ + INT_SRC_I2C3_RXI = 428U, /* I2C3_RXI */ + INT_SRC_I2C3_TXI = 429U, /* I2C3_TXI */ + INT_SRC_I2C3_TEI = 430U, /* I2C3_TEI */ + INT_SRC_I2C3_EEI = 431U, /* I2C3_EEI */ + + /* LVD */ + INT_SRC_LVD1 = 433U, /* LVD1 */ + INT_SRC_LVD2 = 434U, /* LVD2 */ + + /* Temp. sensor */ + INT_SRC_OTS = 435U, /* OTS */ + + /* FCM */ + INT_SRC_FCMFERRI = 436U, /* FCMFERRI */ + INT_SRC_FCMMENDI = 437U, /* FCMMENDI */ + INT_SRC_FCMCOVFI = 438U, /* FCMCOVFI */ + + /* WDT */ + INT_SRC_WDT_REFUDF = 439U, /* WDT_REFUDF */ + + /* ADC */ + INT_SRC_ADC1_EOCA = 448U, /* ADC1_EOCA */ + INT_SRC_ADC1_EOCB = 449U, /* ADC1_EOCB */ + INT_SRC_ADC1_CHCMP = 450U, /* ADC1_CHCMP */ + INT_SRC_ADC1_SEQCMP = 451U, /* ADC1_SEQCMP */ + INT_SRC_ADC2_EOCA = 452U, /* ADC2_EOCA */ + INT_SRC_ADC2_EOCB = 453U, /* ADC2_EOCB */ + INT_SRC_ADC2_CHCMP = 454U, /* ADC2_CHCMP */ + INT_SRC_ADC2_SEQCMP = 455U, /* ADC2_SEQCMP */ + + /* TRNG */ + INT_SRC_TRNG_END = 456U, /* TRNG_END */ + + /* SDIOC */ + INT_SRC_SDIOC1_SD = 482U, /* SDIOC1_SD */ + INT_SRC_SDIOC2_SD = 485U, /* SDIOC2_SD */ + + /* CAN */ + INT_SRC_CAN_INT = 486U, /* CAN_INT */ + + INT_SRC_MAX = 511U, +} en_int_src_t; + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif +/** + * @brief ADC + */ +typedef struct { + __IO uint8_t STR; + uint8_t RESERVED0[1]; + __IO uint16_t CR0; + __IO uint16_t CR1; + uint8_t RESERVED1[4]; + __IO uint16_t TRGSR; + __IO uint32_t CHSELRA; + __IO uint32_t CHSELRB; + __IO uint32_t AVCHSELR; + uint8_t RESERVED2[8]; + __IO uint8_t SSTR0; + __IO uint8_t SSTR1; + __IO uint8_t SSTR2; + __IO uint8_t SSTR3; + __IO uint8_t SSTR4; + __IO uint8_t SSTR5; + __IO uint8_t SSTR6; + __IO uint8_t SSTR7; + __IO uint8_t SSTR8; + __IO uint8_t SSTR9; + __IO uint8_t SSTR10; + __IO uint8_t SSTR11; + __IO uint8_t SSTR12; + __IO uint8_t SSTR13; + __IO uint8_t SSTR14; + __IO uint8_t SSTR15; + __IO uint8_t SSTRL; + uint8_t RESERVED3[7]; + __IO uint16_t CHMUXR0; + __IO uint16_t CHMUXR1; + __IO uint16_t CHMUXR2; + __IO uint16_t CHMUXR3; + uint8_t RESERVED4[6]; + __IO uint8_t ISR; + __IO uint8_t ICR; + uint8_t RESERVED5[4]; + __IO uint16_t SYNCCR; + uint8_t RESERVED6[2]; + __I uint16_t DR0; + __I uint16_t DR1; + __I uint16_t DR2; + __I uint16_t DR3; + __I uint16_t DR4; + __I uint16_t DR5; + __I uint16_t DR6; + __I uint16_t DR7; + __I uint16_t DR8; + __I uint16_t DR9; + __I uint16_t DR10; + __I uint16_t DR11; + __I uint16_t DR12; + __I uint16_t DR13; + __I uint16_t DR14; + __I uint16_t DR15; + __I uint16_t DR16; + uint8_t RESERVED7[46]; + __IO uint16_t AWDCR; + uint8_t RESERVED8[2]; + __IO uint16_t AWDDR0; + __IO uint16_t AWDDR1; + uint8_t RESERVED9[4]; + __IO uint32_t AWDCHSR; + __IO uint32_t AWDSR; + uint8_t RESERVED10[12]; + __IO uint16_t PGACR; + __IO uint16_t PGAGSR; + uint8_t RESERVED11[8]; + __IO uint16_t PGAINSR0; + __IO uint16_t PGAINSR1; +} CM_ADC_TypeDef; + +/** + * @brief AES + */ +typedef struct { + __IO uint32_t CR; + uint8_t RESERVED0[12]; + __IO uint32_t DR0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t KR0; + __IO uint32_t KR1; + __IO uint32_t KR2; + __IO uint32_t KR3; +} CM_AES_TypeDef; + +/** + * @brief AOS + */ +typedef struct { + __O uint32_t INTSFTTRG; + __IO uint32_t DCU_TRGSEL1; + __IO uint32_t DCU_TRGSEL2; + __IO uint32_t DCU_TRGSEL3; + __IO uint32_t DCU_TRGSEL4; + __IO uint32_t DMA1_TRGSEL0; + __IO uint32_t DMA1_TRGSEL1; + __IO uint32_t DMA1_TRGSEL2; + __IO uint32_t DMA1_TRGSEL3; + __IO uint32_t DMA2_TRGSEL0; + __IO uint32_t DMA2_TRGSEL1; + __IO uint32_t DMA2_TRGSEL2; + __IO uint32_t DMA2_TRGSEL3; + __IO uint32_t DMA_RC_TRGSEL; + __IO uint32_t TMR6_TRGSEL0; + __IO uint32_t TMR6_TRGSEL1; + __IO uint32_t TMR0_TRGSEL; + __IO uint32_t PEVNT_TRGSEL12; + __IO uint32_t PEVNT_TRGSEL34; + __IO uint32_t TMRA_TRGSEL0; + __IO uint32_t TMRA_TRGSEL1; + __IO uint32_t OTS_TRGSEL; + __IO uint32_t ADC1_TRGSEL0; + __IO uint32_t ADC1_TRGSEL1; + __IO uint32_t ADC2_TRGSEL0; + __IO uint32_t ADC2_TRGSEL1; + __IO uint32_t COMTRG1; + __IO uint32_t COMTRG2; + uint8_t RESERVED0[144]; + __IO uint32_t PEVNTDIRR1; + __I uint32_t PEVNTIDR1; + __IO uint32_t PEVNTODR1; + __IO uint32_t PEVNTORR1; + __IO uint32_t PEVNTOSR1; + __IO uint32_t PEVNTRISR1; + __IO uint32_t PEVNTFALR1; + __IO uint32_t PEVNTDIRR2; + __I uint32_t PEVNTIDR2; + __IO uint32_t PEVNTODR2; + __IO uint32_t PEVNTORR2; + __IO uint32_t PEVNTOSR2; + __IO uint32_t PEVNTRISR2; + __IO uint32_t PEVNTFALR2; + __IO uint32_t PEVNTDIRR3; + __I uint32_t PEVNTIDR3; + __IO uint32_t PEVNTODR3; + __IO uint32_t PEVNTORR3; + __IO uint32_t PEVNTOSR3; + __IO uint32_t PEVNTRISR3; + __IO uint32_t PEVNTFALR3; + __IO uint32_t PEVNTDIRR4; + __I uint32_t PEVNTIDR4; + __IO uint32_t PEVNTODR4; + __IO uint32_t PEVNTORR4; + __IO uint32_t PEVNTOSR4; + __IO uint32_t PEVNTRISR4; + __IO uint32_t PEVNTFALR4; + __IO uint32_t PEVNTNFCR; +} CM_AOS_TypeDef; + +/** + * @brief CAN + */ +typedef struct { + __I uint32_t RBUF; + uint8_t RESERVED0[76]; + __IO uint32_t TBUF; + uint8_t RESERVED1[76]; + __IO uint8_t CFG_STAT; + __IO uint8_t TCMD; + __IO uint8_t TCTRL; + __IO uint8_t RCTRL; + __IO uint8_t RTIE; + __IO uint8_t RTIF; + __IO uint8_t ERRINT; + __IO uint8_t LIMIT; + __IO uint32_t SBT; + uint8_t RESERVED2[4]; + __I uint8_t EALCAP; + uint8_t RESERVED3[1]; + __IO uint8_t RECNT; + __IO uint8_t TECNT; + __IO uint8_t ACFCTRL; + uint8_t RESERVED4[1]; + __IO uint8_t ACFEN; + uint8_t RESERVED5[1]; + __IO uint32_t ACF; + uint8_t RESERVED6[2]; + __IO uint8_t TBSLOT; + __IO uint8_t TTCFG; + __IO uint32_t REF_MSG; + __IO uint16_t TRG_CFG; + __IO uint16_t TT_TRIG; + __IO uint16_t TT_WTRIG; +} CM_CAN_TypeDef; + +/** + * @brief CMP + */ +typedef struct { + __IO uint16_t CTRL; + __IO uint16_t VLTSEL; + __I uint16_t OUTMON; + __IO uint16_t CVSSTB; + __IO uint16_t CVSPRD; +} CM_CMP_TypeDef; + +/** + * @brief CMP_COMMON + */ +typedef struct { + uint8_t RESERVED0[256]; + __IO uint16_t DADR1; + __IO uint16_t DADR2; + uint8_t RESERVED1[4]; + __IO uint16_t DACR; + uint8_t RESERVED2[2]; + __IO uint16_t RVADC; +} CM_CMP_COMMON_TypeDef; + +/** + * @brief CMU + */ +typedef struct { + uint8_t RESERVED0[16]; + __IO uint16_t PERICKSEL; + __IO uint16_t I2SCKSEL; + uint8_t RESERVED1[12]; + __IO uint32_t SCFGR; + __IO uint8_t USBCKCFGR; + uint8_t RESERVED2[1]; + __IO uint8_t CKSWR; + uint8_t RESERVED3[3]; + __IO uint8_t PLLCR; + uint8_t RESERVED4[3]; + __IO uint8_t UPLLCR; + uint8_t RESERVED5[3]; + __IO uint8_t XTALCR; + uint8_t RESERVED6[3]; + __IO uint8_t HRCCR; + uint8_t RESERVED7[1]; + __IO uint8_t MRCCR; + uint8_t RESERVED8[3]; + __IO uint8_t OSCSTBSR; + __IO uint8_t MCO1CFGR; + __IO uint8_t MCO2CFGR; + __IO uint8_t TPIUCKCFGR; + __IO uint8_t XTALSTDCR; + __IO uint8_t XTALSTDSR; + uint8_t RESERVED9[31]; + __IO uint8_t MRCTRM; + __IO uint8_t HRCTRM; + uint8_t RESERVED10[63]; + __IO uint8_t XTALSTBCR; + uint8_t RESERVED11[93]; + __IO uint32_t PLLCFGR; + __IO uint32_t UPLLCFGR; + uint8_t RESERVED12[776]; + __IO uint8_t XTALCFGR; + uint8_t RESERVED13[15]; + __IO uint8_t XTAL32CR; + __IO uint8_t XTAL32CFGR; + uint8_t RESERVED14[3]; + __IO uint8_t XTAL32NFR; + uint8_t RESERVED15[1]; + __IO uint8_t LRCCR; + uint8_t RESERVED16[1]; + __IO uint8_t LRCTRM; +} CM_CMU_TypeDef; + +/** + * @brief CRC + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t RESLT; + uint8_t RESERVED0[4]; + __I uint32_t FLG; + uint8_t RESERVED1[112]; + __I uint32_t DAT0; + __I uint32_t DAT1; + __I uint32_t DAT2; + __I uint32_t DAT3; + __I uint32_t DAT4; + __I uint32_t DAT5; + __I uint32_t DAT6; + __I uint32_t DAT7; + __I uint32_t DAT8; + __I uint32_t DAT9; + __I uint32_t DAT10; + __I uint32_t DAT11; + __I uint32_t DAT12; + __I uint32_t DAT13; + __I uint32_t DAT14; + __I uint32_t DAT15; + __I uint32_t DAT16; + __I uint32_t DAT17; + __I uint32_t DAT18; + __I uint32_t DAT19; + __I uint32_t DAT20; + __I uint32_t DAT21; + __I uint32_t DAT22; + __I uint32_t DAT23; + __I uint32_t DAT24; + __I uint32_t DAT25; + __I uint32_t DAT26; + __I uint32_t DAT27; + __I uint32_t DAT28; + __I uint32_t DAT29; + __I uint32_t DAT30; + __I uint32_t DAT31; +} CM_CRC_TypeDef; + +/** + * @brief DBGC + */ +typedef struct { + uint8_t RESERVED0[28]; + __IO uint32_t MCUDBGSTAT; + __IO uint32_t MCUSTPCTL; + __IO uint32_t MCUTRACECTL; +} CM_DBGC_TypeDef; + +/** + * @brief DCU + */ +typedef struct { + __IO uint32_t CTL; + __O uint32_t FLAG; + __IO uint32_t DATA0; + __IO uint32_t DATA1; + __IO uint32_t DATA2; + __O uint32_t FLAGCLR; + __IO uint32_t INTEVTSEL; +} CM_DCU_TypeDef; + +/** + * @brief DMA + */ +typedef struct { + __IO uint32_t EN; + __I uint32_t INTSTAT0; + __I uint32_t INTSTAT1; + __IO uint32_t INTMASK0; + __IO uint32_t INTMASK1; + __O uint32_t INTCLR0; + __O uint32_t INTCLR1; + __IO uint32_t CHEN; + __I uint32_t REQSTAT; + __I uint32_t CHSTAT; + uint8_t RESERVED0[4]; + __IO uint32_t RCFGCTL; + __O uint32_t SWREQ; + uint8_t RESERVED1[12]; + __IO uint32_t SAR0; + __IO uint32_t DAR0; + __IO uint32_t DTCTL0; + union { + __IO uint32_t RPT0; + __IO uint32_t RPTB0; + }; + union { + __IO uint32_t SNSEQCTL0; + __IO uint32_t SNSEQCTLB0; + }; + union { + __IO uint32_t DNSEQCTL0; + __IO uint32_t DNSEQCTLB0; + }; + __IO uint32_t LLP0; + __IO uint32_t CHCTL0; + __I uint32_t MONSAR0; + __I uint32_t MONDAR0; + __I uint32_t MONDTCTL0; + __I uint32_t MONRPT0; + __I uint32_t MONSNSEQCTL0; + __I uint32_t MONDNSEQCTL0; + uint8_t RESERVED2[8]; + __IO uint32_t SAR1; + __IO uint32_t DAR1; + __IO uint32_t DTCTL1; + union { + __IO uint32_t RPT1; + __IO uint32_t RPTB1; + }; + union { + __IO uint32_t SNSEQCTL1; + __IO uint32_t SNSEQCTLB1; + }; + union { + __IO uint32_t DNSEQCTL1; + __IO uint32_t DNSEQCTLB1; + }; + __IO uint32_t LLP1; + __IO uint32_t CHCTL1; + __I uint32_t MONSAR1; + __I uint32_t MONDAR1; + __I uint32_t MONDTCTL1; + __I uint32_t MONRPT1; + __I uint32_t MONSNSEQCTL1; + __I uint32_t MONDNSEQCTL1; + uint8_t RESERVED3[8]; + __IO uint32_t SAR2; + __IO uint32_t DAR2; + __IO uint32_t DTCTL2; + union { + __IO uint32_t RPT2; + __IO uint32_t RPTB2; + }; + union { + __IO uint32_t SNSEQCTL2; + __IO uint32_t SNSEQCTLB2; + }; + union { + __IO uint32_t DNSEQCTL2; + __IO uint32_t DNSEQCTLB2; + }; + __IO uint32_t LLP2; + __IO uint32_t CHCTL2; + __I uint32_t MONSAR2; + __I uint32_t MONDAR2; + __I uint32_t MONDTCTL2; + __I uint32_t MONRPT2; + __I uint32_t MONSNSEQCTL2; + __I uint32_t MONDNSEQCTL2; + uint8_t RESERVED4[8]; + __IO uint32_t SAR3; + __IO uint32_t DAR3; + __IO uint32_t DTCTL3; + union { + __IO uint32_t RPT3; + __IO uint32_t RPTB3; + }; + union { + __IO uint32_t SNSEQCTL3; + __IO uint32_t SNSEQCTLB3; + }; + union { + __IO uint32_t DNSEQCTL3; + __IO uint32_t DNSEQCTLB3; + }; + __IO uint32_t LLP3; + __IO uint32_t CHCTL3; + __I uint32_t MONSAR3; + __I uint32_t MONDAR3; + __I uint32_t MONDTCTL3; + __I uint32_t MONRPT3; + __I uint32_t MONSNSEQCTL3; + __I uint32_t MONDNSEQCTL3; +} CM_DMA_TypeDef; + +/** + * @brief EFM + */ +typedef struct { + __IO uint32_t FAPRT; + __IO uint32_t FSTP; + __IO uint32_t FRMC; + __IO uint32_t FWMC; + __I uint32_t FSR; + __IO uint32_t FSCLR; + __IO uint32_t FITE; + __I uint32_t FSWP; + __IO uint32_t FPMTSW; + __IO uint32_t FPMTEW; + uint8_t RESERVED0[40]; + __I uint32_t UQID0; + __I uint32_t UQID1; + __I uint32_t UQID2; + uint8_t RESERVED1[164]; + __IO uint32_t MMF_REMPRT; + __IO uint32_t MMF_REMCR0; + __IO uint32_t MMF_REMCR1; +} CM_EFM_TypeDef; + +/** + * @brief EMB + */ +typedef struct { + __IO uint32_t CTL; + __IO uint32_t PWMLV; + __IO uint32_t SOE; + __I uint32_t STAT; + __O uint32_t STATCLR; + __IO uint32_t INTEN; +} CM_EMB_TypeDef; + +/** + * @brief FCM + */ +typedef struct { + __IO uint32_t LVR; + __IO uint32_t UVR; + __I uint32_t CNTR; + __IO uint32_t STR; + __IO uint32_t MCCR; + __IO uint32_t RCCR; + __IO uint32_t RIER; + __I uint32_t SR; + __O uint32_t CLR; +} CM_FCM_TypeDef; + +/** + * @brief GPIO + */ +typedef struct { + __I uint16_t PIDRA; + uint8_t RESERVED0[2]; + __IO uint16_t PODRA; + __IO uint16_t POERA; + __IO uint16_t POSRA; + __IO uint16_t PORRA; + __IO uint16_t POTRA; + uint8_t RESERVED1[2]; + __I uint16_t PIDRB; + uint8_t RESERVED2[2]; + __IO uint16_t PODRB; + __IO uint16_t POERB; + __IO uint16_t POSRB; + __IO uint16_t PORRB; + __IO uint16_t POTRB; + uint8_t RESERVED3[2]; + __I uint16_t PIDRC; + uint8_t RESERVED4[2]; + __IO uint16_t PODRC; + __IO uint16_t POERC; + __IO uint16_t POSRC; + __IO uint16_t PORRC; + __IO uint16_t POTRC; + uint8_t RESERVED5[2]; + __I uint16_t PIDRD; + uint8_t RESERVED6[2]; + __IO uint16_t PODRD; + __IO uint16_t POERD; + __IO uint16_t POSRD; + __IO uint16_t PORRD; + __IO uint16_t POTRD; + uint8_t RESERVED7[2]; + __I uint16_t PIDRE; + uint8_t RESERVED8[2]; + __IO uint16_t PODRE; + __IO uint16_t POERE; + __IO uint16_t POSRE; + __IO uint16_t PORRE; + __IO uint16_t POTRE; + uint8_t RESERVED9[2]; + __I uint16_t PIDRH; + uint8_t RESERVED10[2]; + __IO uint16_t PODRH; + __IO uint16_t POERH; + __IO uint16_t POSRH; + __IO uint16_t PORRH; + __IO uint16_t POTRH; + uint8_t RESERVED11[918]; + __IO uint16_t PSPCR; + uint8_t RESERVED12[2]; + __IO uint16_t PCCR; + __IO uint16_t PINAER; + __IO uint16_t PWPR; + uint8_t RESERVED13[2]; + __IO uint16_t PCRA0; + __IO uint16_t PFSRA0; + __IO uint16_t PCRA1; + __IO uint16_t PFSRA1; + __IO uint16_t PCRA2; + __IO uint16_t PFSRA2; + __IO uint16_t PCRA3; + __IO uint16_t PFSRA3; + __IO uint16_t PCRA4; + __IO uint16_t PFSRA4; + __IO uint16_t PCRA5; + __IO uint16_t PFSRA5; + __IO uint16_t PCRA6; + __IO uint16_t PFSRA6; + __IO uint16_t PCRA7; + __IO uint16_t PFSRA7; + __IO uint16_t PCRA8; + __IO uint16_t PFSRA8; + __IO uint16_t PCRA9; + __IO uint16_t PFSRA9; + __IO uint16_t PCRA10; + __IO uint16_t PFSRA10; + __IO uint16_t PCRA11; + __IO uint16_t PFSRA11; + __IO uint16_t PCRA12; + __IO uint16_t PFSRA12; + __IO uint16_t PCRA13; + __IO uint16_t PFSRA13; + __IO uint16_t PCRA14; + __IO uint16_t PFSRA14; + __IO uint16_t PCRA15; + __IO uint16_t PFSRA15; + __IO uint16_t PCRB0; + __IO uint16_t PFSRB0; + __IO uint16_t PCRB1; + __IO uint16_t PFSRB1; + __IO uint16_t PCRB2; + __IO uint16_t PFSRB2; + __IO uint16_t PCRB3; + __IO uint16_t PFSRB3; + __IO uint16_t PCRB4; + __IO uint16_t PFSRB4; + __IO uint16_t PCRB5; + __IO uint16_t PFSRB5; + __IO uint16_t PCRB6; + __IO uint16_t PFSRB6; + __IO uint16_t PCRB7; + __IO uint16_t PFSRB7; + __IO uint16_t PCRB8; + __IO uint16_t PFSRB8; + __IO uint16_t PCRB9; + __IO uint16_t PFSRB9; + __IO uint16_t PCRB10; + __IO uint16_t PFSRB10; + __IO uint16_t PCRB11; + __IO uint16_t PFSRB11; + __IO uint16_t PCRB12; + __IO uint16_t PFSRB12; + __IO uint16_t PCRB13; + __IO uint16_t PFSRB13; + __IO uint16_t PCRB14; + __IO uint16_t PFSRB14; + __IO uint16_t PCRB15; + __IO uint16_t PFSRB15; + __IO uint16_t PCRC0; + __IO uint16_t PFSRC0; + __IO uint16_t PCRC1; + __IO uint16_t PFSRC1; + __IO uint16_t PCRC2; + __IO uint16_t PFSRC2; + __IO uint16_t PCRC3; + __IO uint16_t PFSRC3; + __IO uint16_t PCRC4; + __IO uint16_t PFSRC4; + __IO uint16_t PCRC5; + __IO uint16_t PFSRC5; + __IO uint16_t PCRC6; + __IO uint16_t PFSRC6; + __IO uint16_t PCRC7; + __IO uint16_t PFSRC7; + __IO uint16_t PCRC8; + __IO uint16_t PFSRC8; + __IO uint16_t PCRC9; + __IO uint16_t PFSRC9; + __IO uint16_t PCRC10; + __IO uint16_t PFSRC10; + __IO uint16_t PCRC11; + __IO uint16_t PFSRC11; + __IO uint16_t PCRC12; + __IO uint16_t PFSRC12; + __IO uint16_t PCRC13; + __IO uint16_t PFSRC13; + __IO uint16_t PCRC14; + __IO uint16_t PFSRC14; + __IO uint16_t PCRC15; + __IO uint16_t PFSRC15; + __IO uint16_t PCRD0; + __IO uint16_t PFSRD0; + __IO uint16_t PCRD1; + __IO uint16_t PFSRD1; + __IO uint16_t PCRD2; + __IO uint16_t PFSRD2; + __IO uint16_t PCRD3; + __IO uint16_t PFSRD3; + __IO uint16_t PCRD4; + __IO uint16_t PFSRD4; + __IO uint16_t PCRD5; + __IO uint16_t PFSRD5; + __IO uint16_t PCRD6; + __IO uint16_t PFSRD6; + __IO uint16_t PCRD7; + __IO uint16_t PFSRD7; + __IO uint16_t PCRD8; + __IO uint16_t PFSRD8; + __IO uint16_t PCRD9; + __IO uint16_t PFSRD9; + __IO uint16_t PCRD10; + __IO uint16_t PFSRD10; + __IO uint16_t PCRD11; + __IO uint16_t PFSRD11; + __IO uint16_t PCRD12; + __IO uint16_t PFSRD12; + __IO uint16_t PCRD13; + __IO uint16_t PFSRD13; + __IO uint16_t PCRD14; + __IO uint16_t PFSRD14; + __IO uint16_t PCRD15; + __IO uint16_t PFSRD15; + __IO uint16_t PCRE0; + __IO uint16_t PFSRE0; + __IO uint16_t PCRE1; + __IO uint16_t PFSRE1; + __IO uint16_t PCRE2; + __IO uint16_t PFSRE2; + __IO uint16_t PCRE3; + __IO uint16_t PFSRE3; + __IO uint16_t PCRE4; + __IO uint16_t PFSRE4; + __IO uint16_t PCRE5; + __IO uint16_t PFSRE5; + __IO uint16_t PCRE6; + __IO uint16_t PFSRE6; + __IO uint16_t PCRE7; + __IO uint16_t PFSRE7; + __IO uint16_t PCRE8; + __IO uint16_t PFSRE8; + __IO uint16_t PCRE9; + __IO uint16_t PFSRE9; + __IO uint16_t PCRE10; + __IO uint16_t PFSRE10; + __IO uint16_t PCRE11; + __IO uint16_t PFSRE11; + __IO uint16_t PCRE12; + __IO uint16_t PFSRE12; + __IO uint16_t PCRE13; + __IO uint16_t PFSRE13; + __IO uint16_t PCRE14; + __IO uint16_t PFSRE14; + __IO uint16_t PCRE15; + __IO uint16_t PFSRE15; + __IO uint16_t PCRH0; + __IO uint16_t PFSRH0; + __IO uint16_t PCRH1; + __IO uint16_t PFSRH1; + __IO uint16_t PCRH2; + __IO uint16_t PFSRH2; +} CM_GPIO_TypeDef; + +/** + * @brief HASH + */ +typedef struct { + __IO uint32_t CR; + uint8_t RESERVED0[12]; + __IO uint32_t HR7; + __IO uint32_t HR6; + __IO uint32_t HR5; + __IO uint32_t HR4; + __IO uint32_t HR3; + __IO uint32_t HR2; + __IO uint32_t HR1; + __IO uint32_t HR0; + uint8_t RESERVED1[16]; + __IO uint32_t DR15; + __IO uint32_t DR14; + __IO uint32_t DR13; + __IO uint32_t DR12; + __IO uint32_t DR11; + __IO uint32_t DR10; + __IO uint32_t DR9; + __IO uint32_t DR8; + __IO uint32_t DR7; + __IO uint32_t DR6; + __IO uint32_t DR5; + __IO uint32_t DR4; + __IO uint32_t DR3; + __IO uint32_t DR2; + __IO uint32_t DR1; + __IO uint32_t DR0; +} CM_HASH_TypeDef; + +/** + * @brief I2C + */ +typedef struct { + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t CR3; + __IO uint32_t CR4; + __IO uint32_t SLR0; + __IO uint32_t SLR1; + __IO uint32_t SLTR; + __IO uint32_t SR; + __O uint32_t CLR; + __O uint8_t DTR; + uint8_t RESERVED0[3]; + __I uint8_t DRR; + uint8_t RESERVED1[3]; + __IO uint32_t CCR; + __IO uint32_t FLTR; +} CM_I2C_TypeDef; + +/** + * @brief I2S + */ +typedef struct { + __IO uint32_t CTRL; + __I uint32_t SR; + __IO uint32_t ER; + __IO uint32_t CFGR; + __O uint32_t TXBUF; + __I uint32_t RXBUF; + __IO uint32_t PR; +} CM_I2S_TypeDef; + +/** + * @brief ICG + */ +typedef struct { + __I uint32_t ICG0; + __I uint32_t ICG1; + __I uint32_t ICG2; + __I uint32_t ICG3; + __I uint32_t ICG4; + __I uint32_t ICG5; + __I uint32_t ICG6; + __I uint32_t ICG7; +} CM_ICG_TypeDef; + +/** + * @brief INTC + */ +typedef struct { + __IO uint32_t NMICR; + __IO uint32_t NMIENR; + __IO uint32_t NMIFR; + __IO uint32_t NMICFR; + __IO uint32_t EIRQCR0; + __IO uint32_t EIRQCR1; + __IO uint32_t EIRQCR2; + __IO uint32_t EIRQCR3; + __IO uint32_t EIRQCR4; + __IO uint32_t EIRQCR5; + __IO uint32_t EIRQCR6; + __IO uint32_t EIRQCR7; + __IO uint32_t EIRQCR8; + __IO uint32_t EIRQCR9; + __IO uint32_t EIRQCR10; + __IO uint32_t EIRQCR11; + __IO uint32_t EIRQCR12; + __IO uint32_t EIRQCR13; + __IO uint32_t EIRQCR14; + __IO uint32_t EIRQCR15; + __IO uint32_t WUPEN; + __IO uint32_t EIFR; + __IO uint32_t EIFCR; + __IO uint32_t SEL0; + __IO uint32_t SEL1; + __IO uint32_t SEL2; + __IO uint32_t SEL3; + __IO uint32_t SEL4; + __IO uint32_t SEL5; + __IO uint32_t SEL6; + __IO uint32_t SEL7; + __IO uint32_t SEL8; + __IO uint32_t SEL9; + __IO uint32_t SEL10; + __IO uint32_t SEL11; + __IO uint32_t SEL12; + __IO uint32_t SEL13; + __IO uint32_t SEL14; + __IO uint32_t SEL15; + __IO uint32_t SEL16; + __IO uint32_t SEL17; + __IO uint32_t SEL18; + __IO uint32_t SEL19; + __IO uint32_t SEL20; + __IO uint32_t SEL21; + __IO uint32_t SEL22; + __IO uint32_t SEL23; + __IO uint32_t SEL24; + __IO uint32_t SEL25; + __IO uint32_t SEL26; + __IO uint32_t SEL27; + __IO uint32_t SEL28; + __IO uint32_t SEL29; + __IO uint32_t SEL30; + __IO uint32_t SEL31; + __IO uint32_t SEL32; + __IO uint32_t SEL33; + __IO uint32_t SEL34; + __IO uint32_t SEL35; + __IO uint32_t SEL36; + __IO uint32_t SEL37; + __IO uint32_t SEL38; + __IO uint32_t SEL39; + __IO uint32_t SEL40; + __IO uint32_t SEL41; + __IO uint32_t SEL42; + __IO uint32_t SEL43; + __IO uint32_t SEL44; + __IO uint32_t SEL45; + __IO uint32_t SEL46; + __IO uint32_t SEL47; + __IO uint32_t SEL48; + __IO uint32_t SEL49; + __IO uint32_t SEL50; + __IO uint32_t SEL51; + __IO uint32_t SEL52; + __IO uint32_t SEL53; + __IO uint32_t SEL54; + __IO uint32_t SEL55; + __IO uint32_t SEL56; + __IO uint32_t SEL57; + __IO uint32_t SEL58; + __IO uint32_t SEL59; + __IO uint32_t SEL60; + __IO uint32_t SEL61; + __IO uint32_t SEL62; + __IO uint32_t SEL63; + __IO uint32_t SEL64; + __IO uint32_t SEL65; + __IO uint32_t SEL66; + __IO uint32_t SEL67; + __IO uint32_t SEL68; + __IO uint32_t SEL69; + __IO uint32_t SEL70; + __IO uint32_t SEL71; + __IO uint32_t SEL72; + __IO uint32_t SEL73; + __IO uint32_t SEL74; + __IO uint32_t SEL75; + __IO uint32_t SEL76; + __IO uint32_t SEL77; + __IO uint32_t SEL78; + __IO uint32_t SEL79; + __IO uint32_t SEL80; + __IO uint32_t SEL81; + __IO uint32_t SEL82; + __IO uint32_t SEL83; + __IO uint32_t SEL84; + __IO uint32_t SEL85; + __IO uint32_t SEL86; + __IO uint32_t SEL87; + __IO uint32_t SEL88; + __IO uint32_t SEL89; + __IO uint32_t SEL90; + __IO uint32_t SEL91; + __IO uint32_t SEL92; + __IO uint32_t SEL93; + __IO uint32_t SEL94; + __IO uint32_t SEL95; + __IO uint32_t SEL96; + __IO uint32_t SEL97; + __IO uint32_t SEL98; + __IO uint32_t SEL99; + __IO uint32_t SEL100; + __IO uint32_t SEL101; + __IO uint32_t SEL102; + __IO uint32_t SEL103; + __IO uint32_t SEL104; + __IO uint32_t SEL105; + __IO uint32_t SEL106; + __IO uint32_t SEL107; + __IO uint32_t SEL108; + __IO uint32_t SEL109; + __IO uint32_t SEL110; + __IO uint32_t SEL111; + __IO uint32_t SEL112; + __IO uint32_t SEL113; + __IO uint32_t SEL114; + __IO uint32_t SEL115; + __IO uint32_t SEL116; + __IO uint32_t SEL117; + __IO uint32_t SEL118; + __IO uint32_t SEL119; + __IO uint32_t SEL120; + __IO uint32_t SEL121; + __IO uint32_t SEL122; + __IO uint32_t SEL123; + __IO uint32_t SEL124; + __IO uint32_t SEL125; + __IO uint32_t SEL126; + __IO uint32_t SEL127; + __IO uint32_t VSSEL128; + __IO uint32_t VSSEL129; + __IO uint32_t VSSEL130; + __IO uint32_t VSSEL131; + __IO uint32_t VSSEL132; + __IO uint32_t VSSEL133; + __IO uint32_t VSSEL134; + __IO uint32_t VSSEL135; + __IO uint32_t VSSEL136; + __IO uint32_t VSSEL137; + __IO uint32_t VSSEL138; + __IO uint32_t VSSEL139; + __IO uint32_t VSSEL140; + __IO uint32_t VSSEL141; + __IO uint32_t VSSEL142; + __IO uint32_t VSSEL143; + __IO uint32_t SWIER; + __IO uint32_t EVTER; + __IO uint32_t IER; +} CM_INTC_TypeDef; + +/** + * @brief KEYSCAN + */ +typedef struct { + __IO uint32_t SCR; + __IO uint32_t SER; + __IO uint32_t SSR; +} CM_KEYSCAN_TypeDef; + +/** + * @brief MPU + */ +typedef struct { + __IO uint32_t RGD0; + __IO uint32_t RGD1; + __IO uint32_t RGD2; + __IO uint32_t RGD3; + __IO uint32_t RGD4; + __IO uint32_t RGD5; + __IO uint32_t RGD6; + __IO uint32_t RGD7; + __IO uint32_t RGD8; + __IO uint32_t RGD9; + __IO uint32_t RGD10; + __IO uint32_t RGD11; + __IO uint32_t RGD12; + __IO uint32_t RGD13; + __IO uint32_t RGD14; + __IO uint32_t RGD15; + __IO uint32_t RGCR0; + __IO uint32_t RGCR1; + __IO uint32_t RGCR2; + __IO uint32_t RGCR3; + __IO uint32_t RGCR4; + __IO uint32_t RGCR5; + __IO uint32_t RGCR6; + __IO uint32_t RGCR7; + __IO uint32_t RGCR8; + __IO uint32_t RGCR9; + __IO uint32_t RGCR10; + __IO uint32_t RGCR11; + __IO uint32_t RGCR12; + __IO uint32_t RGCR13; + __IO uint32_t RGCR14; + __IO uint32_t RGCR15; + __IO uint32_t CR; + __I uint32_t SR; + __O uint32_t ECLR; + __IO uint32_t WP; + uint8_t RESERVED0[16268]; + __IO uint32_t IPPR; +} CM_MPU_TypeDef; + +/** + * @brief OTS + */ +typedef struct { + __IO uint16_t CTL; + __IO uint16_t DR1; + __IO uint16_t DR2; + __IO uint16_t ECR; +} CM_OTS_TypeDef; + +/** + * @brief PERIC + */ +typedef struct { + __IO uint32_t USBFS_SYCTLREG; + __IO uint32_t SDIOC_SYCTLREG; +} CM_PERIC_TypeDef; + +/** + * @brief PWC + */ +typedef struct { + __IO uint32_t FCG0; + __IO uint32_t FCG1; + __IO uint32_t FCG2; + __IO uint32_t FCG3; + __IO uint32_t FCG0PC; + uint8_t RESERVED0[17388]; + __IO uint16_t WKTCR; + uint8_t RESERVED1[31754]; + __IO uint16_t STPMCR; + uint8_t RESERVED2[6]; + __IO uint32_t RAMPC0; + __IO uint16_t RAMOPM; + uint8_t RESERVED3[198]; + __IO uint8_t PVDICR; + __IO uint8_t PVDDSR; + uint8_t RESERVED4[796]; + __IO uint16_t FPRC; + __IO uint8_t PWRC0; + __IO uint8_t PWRC1; + __IO uint8_t PWRC2; + __IO uint8_t PWRC3; + __IO uint8_t PDWKE0; + __IO uint8_t PDWKE1; + __IO uint8_t PDWKE2; + __IO uint8_t PDWKES; + __IO uint8_t PDWKF0; + __IO uint8_t PDWKF1; + __IO uint8_t PWCMR; + uint8_t RESERVED5[4]; + __IO uint8_t MDSWCR; + uint8_t RESERVED6[2]; + __IO uint8_t PVDCR0; + __IO uint8_t PVDCR1; + __IO uint8_t PVDFCR; + __IO uint8_t PVDLCR; + uint8_t RESERVED7[21]; + __IO uint8_t XTAL32CS; +} CM_PWC_TypeDef; + +/** + * @brief QSPI + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t CSCR; + __IO uint32_t FCR; + __IO uint32_t SR; + __IO uint32_t DCOM; + __IO uint32_t CCMD; + __IO uint32_t XCMD; + uint8_t RESERVED0[8]; + __O uint32_t CLR; + uint8_t RESERVED1[2012]; + __IO uint32_t EXAR; +} CM_QSPI_TypeDef; + +/** + * @brief RMU + */ +typedef struct { + __IO uint16_t RSTF0; +} CM_RMU_TypeDef; + +/** + * @brief RTC + */ +typedef struct { + __IO uint8_t CR0; + uint8_t RESERVED0[3]; + __IO uint8_t CR1; + uint8_t RESERVED1[3]; + __IO uint8_t CR2; + uint8_t RESERVED2[3]; + __IO uint8_t CR3; + uint8_t RESERVED3[3]; + __IO uint8_t SEC; + uint8_t RESERVED4[3]; + __IO uint8_t MIN; + uint8_t RESERVED5[3]; + __IO uint8_t HOUR; + uint8_t RESERVED6[3]; + __IO uint8_t WEEK; + uint8_t RESERVED7[3]; + __IO uint8_t DAY; + uint8_t RESERVED8[3]; + __IO uint8_t MON; + uint8_t RESERVED9[3]; + __IO uint8_t YEAR; + uint8_t RESERVED10[3]; + __IO uint8_t ALMMIN; + uint8_t RESERVED11[3]; + __IO uint8_t ALMHOUR; + uint8_t RESERVED12[3]; + __IO uint8_t ALMWEEK; + uint8_t RESERVED13[3]; + __IO uint8_t ERRCRH; + uint8_t RESERVED14[3]; + __IO uint8_t ERRCRL; +} CM_RTC_TypeDef; + +/** + * @brief SDIOC + */ +typedef struct { + uint8_t RESERVED0[4]; + __IO uint16_t BLKSIZE; + __IO uint16_t BLKCNT; + __IO uint16_t ARG0; + __IO uint16_t ARG1; + __IO uint16_t TRANSMODE; + __IO uint16_t CMD; + __I uint16_t RESP0; + __I uint16_t RESP1; + __I uint16_t RESP2; + __I uint16_t RESP3; + __I uint16_t RESP4; + __I uint16_t RESP5; + __I uint16_t RESP6; + __I uint16_t RESP7; + __IO uint16_t BUF0; + __IO uint16_t BUF1; + __I uint32_t PSTAT; + __IO uint8_t HOSTCON; + __IO uint8_t PWRCON; + __IO uint8_t BLKGPCON; + uint8_t RESERVED1[1]; + __IO uint16_t CLKCON; + __IO uint8_t TOUTCON; + __IO uint8_t SFTRST; + __IO uint16_t NORINTST; + __IO uint16_t ERRINTST; + __IO uint16_t NORINTSTEN; + __IO uint16_t ERRINTSTEN; + __IO uint16_t NORINTSGEN; + __IO uint16_t ERRINTSGEN; + __I uint16_t ATCERRST; + uint8_t RESERVED2[18]; + __O uint16_t FEA; + __O uint16_t FEE; +} CM_SDIOC_TypeDef; + +/** + * @brief SPI + */ +typedef struct { + __IO uint32_t DR; + __IO uint32_t CR1; + uint8_t RESERVED0[4]; + __IO uint32_t CFG1; + uint8_t RESERVED1[4]; + __IO uint32_t SR; + __IO uint32_t CFG2; +} CM_SPI_TypeDef; + +/** + * @brief SRAMC + */ +typedef struct { + __IO uint32_t WTCR; + __IO uint32_t WTPR; + __IO uint32_t CKCR; + __IO uint32_t CKPR; + __IO uint32_t CKSR; +} CM_SRAMC_TypeDef; + +/** + * @brief SWDT + */ +typedef struct { + uint8_t RESERVED0[4]; + __IO uint32_t SR; + __IO uint32_t RR; +} CM_SWDT_TypeDef; + +/** + * @brief TMR0 + */ +typedef struct { + __IO uint32_t CNTAR; + __IO uint32_t CNTBR; + __IO uint32_t CMPAR; + __IO uint32_t CMPBR; + __IO uint32_t BCONR; + __IO uint32_t STFLR; +} CM_TMR0_TypeDef; + +/** + * @brief TMR4 + */ +typedef struct { + uint8_t RESERVED0[2]; + __IO uint16_t OCCRUH; + uint8_t RESERVED1[2]; + __IO uint16_t OCCRUL; + uint8_t RESERVED2[2]; + __IO uint16_t OCCRVH; + uint8_t RESERVED3[2]; + __IO uint16_t OCCRVL; + uint8_t RESERVED4[2]; + __IO uint16_t OCCRWH; + uint8_t RESERVED5[2]; + __IO uint16_t OCCRWL; + __IO uint16_t OCSRU; + __IO uint16_t OCERU; + __IO uint16_t OCSRV; + __IO uint16_t OCERV; + __IO uint16_t OCSRW; + __IO uint16_t OCERW; + __IO uint16_t OCMRUH; + uint8_t RESERVED6[2]; + __IO uint32_t OCMRUL; + __IO uint16_t OCMRVH; + uint8_t RESERVED7[2]; + __IO uint32_t OCMRVL; + __IO uint16_t OCMRWH; + uint8_t RESERVED8[2]; + __IO uint32_t OCMRWL; + uint8_t RESERVED9[6]; + __IO uint16_t CPSR; + uint8_t RESERVED10[2]; + __IO uint16_t CNTR; + __IO uint16_t CCSR; + __IO uint16_t CVPR; + uint8_t RESERVED11[54]; + __IO uint16_t PFSRU; + __IO uint16_t PDARU; + __IO uint16_t PDBRU; + uint8_t RESERVED12[2]; + __IO uint16_t PFSRV; + __IO uint16_t PDARV; + __IO uint16_t PDBRV; + uint8_t RESERVED13[2]; + __IO uint16_t PFSRW; + __IO uint16_t PDARW; + __IO uint16_t PDBRW; + __IO uint16_t POCRU; + uint8_t RESERVED14[2]; + __IO uint16_t POCRV; + uint8_t RESERVED15[2]; + __IO uint16_t POCRW; + uint8_t RESERVED16[2]; + __IO uint16_t RCSR; + uint8_t RESERVED17[12]; + __IO uint16_t SCCRUH; + uint8_t RESERVED18[2]; + __IO uint16_t SCCRUL; + uint8_t RESERVED19[2]; + __IO uint16_t SCCRVH; + uint8_t RESERVED20[2]; + __IO uint16_t SCCRVL; + uint8_t RESERVED21[2]; + __IO uint16_t SCCRWH; + uint8_t RESERVED22[2]; + __IO uint16_t SCCRWL; + __IO uint16_t SCSRUH; + __IO uint16_t SCMRUH; + __IO uint16_t SCSRUL; + __IO uint16_t SCMRUL; + __IO uint16_t SCSRVH; + __IO uint16_t SCMRVH; + __IO uint16_t SCSRVL; + __IO uint16_t SCMRVL; + __IO uint16_t SCSRWH; + __IO uint16_t SCMRWH; + __IO uint16_t SCSRWL; + __IO uint16_t SCMRWL; + uint8_t RESERVED23[16]; + __IO uint16_t ECSR; +} CM_TMR4_TypeDef; + +/** + * @brief TMR4_ECER + */ +typedef struct { + __IO uint32_t ECER1; + __IO uint32_t ECER2; + __IO uint32_t ECER3; +} CM_TMR4_ECER_TypeDef; + +/** + * @brief TMR6 + */ +typedef struct { + __IO uint32_t CNTER; + __IO uint32_t PERAR; + __IO uint32_t PERBR; + __IO uint32_t PERCR; + __IO uint32_t GCMAR; + __IO uint32_t GCMBR; + __IO uint32_t GCMCR; + __IO uint32_t GCMDR; + __IO uint32_t GCMER; + __IO uint32_t GCMFR; + __IO uint32_t SCMAR; + __IO uint32_t SCMBR; + __IO uint32_t SCMCR; + __IO uint32_t SCMDR; + __IO uint32_t SCMER; + __IO uint32_t SCMFR; + __IO uint32_t DTUAR; + __IO uint32_t DTDAR; + __IO uint32_t DTUBR; + __IO uint32_t DTDBR; + __IO uint32_t GCONR; + __IO uint32_t ICONR; + __IO uint32_t PCONR; + __IO uint32_t BCONR; + __IO uint32_t DCONR; + uint8_t RESERVED0[4]; + __IO uint32_t FCONR; + __IO uint32_t VPERR; + __IO uint32_t STFLR; + __IO uint32_t HSTAR; + __IO uint32_t HSTPR; + __IO uint32_t HCLRR; + __IO uint32_t HCPAR; + __IO uint32_t HCPBR; + __IO uint32_t HCUPR; + __IO uint32_t HCDOR; +} CM_TMR6_TypeDef; + +/** + * @brief TMR6_COMMON + */ +typedef struct { + uint8_t RESERVED0[244]; + __IO uint32_t SSTAR; + __IO uint32_t SSTPR; + __IO uint32_t SCLRR; +} CM_TMR6_COMMON_TypeDef; + +/** + * @brief TMRA + */ +typedef struct { + __IO uint16_t CNTER; + uint8_t RESERVED0[2]; + __IO uint16_t PERAR; + uint8_t RESERVED1[58]; + __IO uint16_t CMPAR1; + uint8_t RESERVED2[2]; + __IO uint16_t CMPAR2; + uint8_t RESERVED3[2]; + __IO uint16_t CMPAR3; + uint8_t RESERVED4[2]; + __IO uint16_t CMPAR4; + uint8_t RESERVED5[2]; + __IO uint16_t CMPAR5; + uint8_t RESERVED6[2]; + __IO uint16_t CMPAR6; + uint8_t RESERVED7[2]; + __IO uint16_t CMPAR7; + uint8_t RESERVED8[2]; + __IO uint16_t CMPAR8; + uint8_t RESERVED9[34]; + __IO uint8_t BCSTRL; + __IO uint8_t BCSTRH; + uint8_t RESERVED10[2]; + __IO uint16_t HCONR; + uint8_t RESERVED11[2]; + __IO uint16_t HCUPR; + uint8_t RESERVED12[2]; + __IO uint16_t HCDOR; + uint8_t RESERVED13[2]; + __IO uint16_t ICONR; + uint8_t RESERVED14[2]; + __IO uint16_t ECONR; + uint8_t RESERVED15[2]; + __IO uint16_t FCONR; + uint8_t RESERVED16[2]; + __IO uint16_t STFLR; + uint8_t RESERVED17[34]; + __IO uint16_t BCONR1; + uint8_t RESERVED18[6]; + __IO uint16_t BCONR2; + uint8_t RESERVED19[6]; + __IO uint16_t BCONR3; + uint8_t RESERVED20[6]; + __IO uint16_t BCONR4; + uint8_t RESERVED21[38]; + __IO uint16_t CCONR1; + uint8_t RESERVED22[2]; + __IO uint16_t CCONR2; + uint8_t RESERVED23[2]; + __IO uint16_t CCONR3; + uint8_t RESERVED24[2]; + __IO uint16_t CCONR4; + uint8_t RESERVED25[2]; + __IO uint16_t CCONR5; + uint8_t RESERVED26[2]; + __IO uint16_t CCONR6; + uint8_t RESERVED27[2]; + __IO uint16_t CCONR7; + uint8_t RESERVED28[2]; + __IO uint16_t CCONR8; + uint8_t RESERVED29[34]; + __IO uint16_t PCONR1; + uint8_t RESERVED30[2]; + __IO uint16_t PCONR2; + uint8_t RESERVED31[2]; + __IO uint16_t PCONR3; + uint8_t RESERVED32[2]; + __IO uint16_t PCONR4; + uint8_t RESERVED33[2]; + __IO uint16_t PCONR5; + uint8_t RESERVED34[2]; + __IO uint16_t PCONR6; + uint8_t RESERVED35[2]; + __IO uint16_t PCONR7; + uint8_t RESERVED36[2]; + __IO uint16_t PCONR8; +} CM_TMRA_TypeDef; + +/** + * @brief TRNG + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t MR; + uint8_t RESERVED0[4]; + __I uint32_t DR0; + __I uint32_t DR1; +} CM_TRNG_TypeDef; + +/** + * @brief USART + */ +typedef struct { + __I uint32_t SR; + __IO uint16_t TDR; + __I uint16_t RDR; + __IO uint32_t BRR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t CR3; + __IO uint32_t PR; +} CM_USART_TypeDef; + +/** + * @brief USBFS + */ +typedef struct { + __IO uint32_t GVBUSCFG; + uint8_t RESERVED0[4]; + __IO uint32_t GAHBCFG; + __IO uint32_t GUSBCFG; + __IO uint32_t GRSTCTL; + __IO uint32_t GINTSTS; + __IO uint32_t GINTMSK; + __I uint32_t GRXSTSR; + __I uint32_t GRXSTSP; + __IO uint32_t GRXFSIZ; + __IO uint32_t HNPTXFSIZ; + __I uint32_t HNPTXSTS; + uint8_t RESERVED1[12]; + __IO uint32_t CID; + uint8_t RESERVED2[192]; + __IO uint32_t HPTXFSIZ; + __IO uint32_t DIEPTXF1; + __IO uint32_t DIEPTXF2; + __IO uint32_t DIEPTXF3; + __IO uint32_t DIEPTXF4; + __IO uint32_t DIEPTXF5; + uint8_t RESERVED3[744]; + __IO uint32_t HCFG; + __IO uint32_t HFIR; + __I uint32_t HFNUM; + uint8_t RESERVED4[4]; + __I uint32_t HPTXSTS; + __I uint32_t HAINT; + __IO uint32_t HAINTMSK; + uint8_t RESERVED5[36]; + __IO uint32_t HPRT; + uint8_t RESERVED6[188]; + __IO uint32_t HCCHAR0; + uint8_t RESERVED7[4]; + __IO uint32_t HCINT0; + __IO uint32_t HCINTMSK0; + __IO uint32_t HCTSIZ0; + __IO uint32_t HCDMA0; + uint8_t RESERVED8[8]; + __IO uint32_t HCCHAR1; + uint8_t RESERVED9[4]; + __IO uint32_t HCINT1; + __IO uint32_t HCINTMSK1; + __IO uint32_t HCTSIZ1; + __IO uint32_t HCDMA1; + uint8_t RESERVED10[8]; + __IO uint32_t HCCHAR2; + uint8_t RESERVED11[4]; + __IO uint32_t HCINT2; + __IO uint32_t HCINTMSK2; + __IO uint32_t HCTSIZ2; + __IO uint32_t HCDMA2; + uint8_t RESERVED12[8]; + __IO uint32_t HCCHAR3; + uint8_t RESERVED13[4]; + __IO uint32_t HCINT3; + __IO uint32_t HCINTMSK3; + __IO uint32_t HCTSIZ3; + __IO uint32_t HCDMA3; + uint8_t RESERVED14[8]; + __IO uint32_t HCCHAR4; + uint8_t RESERVED15[4]; + __IO uint32_t HCINT4; + __IO uint32_t HCINTMSK4; + __IO uint32_t HCTSIZ4; + __IO uint32_t HCDMA4; + uint8_t RESERVED16[8]; + __IO uint32_t HCCHAR5; + uint8_t RESERVED17[4]; + __IO uint32_t HCINT5; + __IO uint32_t HCINTMSK5; + __IO uint32_t HCTSIZ5; + __IO uint32_t HCDMA5; + uint8_t RESERVED18[8]; + __IO uint32_t HCCHAR6; + uint8_t RESERVED19[4]; + __IO uint32_t HCINT6; + __IO uint32_t HCINTMSK6; + __IO uint32_t HCTSIZ6; + __IO uint32_t HCDMA6; + uint8_t RESERVED20[8]; + __IO uint32_t HCCHAR7; + uint8_t RESERVED21[4]; + __IO uint32_t HCINT7; + __IO uint32_t HCINTMSK7; + __IO uint32_t HCTSIZ7; + __IO uint32_t HCDMA7; + uint8_t RESERVED22[8]; + __IO uint32_t HCCHAR8; + uint8_t RESERVED23[4]; + __IO uint32_t HCINT8; + __IO uint32_t HCINTMSK8; + __IO uint32_t HCTSIZ8; + __IO uint32_t HCDMA8; + uint8_t RESERVED24[8]; + __IO uint32_t HCCHAR9; + uint8_t RESERVED25[4]; + __IO uint32_t HCINT9; + __IO uint32_t HCINTMSK9; + __IO uint32_t HCTSIZ9; + __IO uint32_t HCDMA9; + uint8_t RESERVED26[8]; + __IO uint32_t HCCHAR10; + uint8_t RESERVED27[4]; + __IO uint32_t HCINT10; + __IO uint32_t HCINTMSK10; + __IO uint32_t HCTSIZ10; + __IO uint32_t HCDMA10; + uint8_t RESERVED28[8]; + __IO uint32_t HCCHAR11; + uint8_t RESERVED29[4]; + __IO uint32_t HCINT11; + __IO uint32_t HCINTMSK11; + __IO uint32_t HCTSIZ11; + __IO uint32_t HCDMA11; + uint8_t RESERVED30[392]; + __IO uint32_t DCFG; + __IO uint32_t DCTL; + __I uint32_t DSTS; + uint8_t RESERVED31[4]; + __IO uint32_t DIEPMSK; + __IO uint32_t DOEPMSK; + __IO uint32_t DAINT; + __IO uint32_t DAINTMSK; + uint8_t RESERVED32[20]; + __IO uint32_t DIEPEMPMSK; + uint8_t RESERVED33[200]; + __IO uint32_t DIEPCTL0; + uint8_t RESERVED34[4]; + __IO uint32_t DIEPINT0; + uint8_t RESERVED35[4]; + __IO uint32_t DIEPTSIZ0; + __IO uint32_t DIEPDMA0; + __I uint32_t DTXFSTS0; + uint8_t RESERVED36[4]; + __IO uint32_t DIEPCTL1; + uint8_t RESERVED37[4]; + __IO uint32_t DIEPINT1; + uint8_t RESERVED38[4]; + __IO uint32_t DIEPTSIZ1; + __IO uint32_t DIEPDMA1; + __I uint32_t DTXFSTS1; + uint8_t RESERVED39[4]; + __IO uint32_t DIEPCTL2; + uint8_t RESERVED40[4]; + __IO uint32_t DIEPINT2; + uint8_t RESERVED41[4]; + __IO uint32_t DIEPTSIZ2; + __IO uint32_t DIEPDMA2; + __I uint32_t DTXFSTS2; + uint8_t RESERVED42[4]; + __IO uint32_t DIEPCTL3; + uint8_t RESERVED43[4]; + __IO uint32_t DIEPINT3; + uint8_t RESERVED44[4]; + __IO uint32_t DIEPTSIZ3; + __IO uint32_t DIEPDMA3; + __I uint32_t DTXFSTS3; + uint8_t RESERVED45[4]; + __IO uint32_t DIEPCTL4; + uint8_t RESERVED46[4]; + __IO uint32_t DIEPINT4; + uint8_t RESERVED47[4]; + __IO uint32_t DIEPTSIZ4; + __IO uint32_t DIEPDMA4; + __I uint32_t DTXFSTS4; + uint8_t RESERVED48[4]; + __IO uint32_t DIEPCTL5; + uint8_t RESERVED49[4]; + __IO uint32_t DIEPINT5; + uint8_t RESERVED50[4]; + __IO uint32_t DIEPTSIZ5; + __IO uint32_t DIEPDMA5; + __I uint32_t DTXFSTS5; + uint8_t RESERVED51[324]; + __IO uint32_t DOEPCTL0; + uint8_t RESERVED52[4]; + __IO uint32_t DOEPINT0; + uint8_t RESERVED53[4]; + __IO uint32_t DOEPTSIZ0; + __IO uint32_t DOEPDMA0; + uint8_t RESERVED54[8]; + __IO uint32_t DOEPCTL1; + uint8_t RESERVED55[4]; + __IO uint32_t DOEPINT1; + uint8_t RESERVED56[4]; + __IO uint32_t DOEPTSIZ1; + __IO uint32_t DOEPDMA1; + uint8_t RESERVED57[8]; + __IO uint32_t DOEPCTL2; + uint8_t RESERVED58[4]; + __IO uint32_t DOEPINT2; + uint8_t RESERVED59[4]; + __IO uint32_t DOEPTSIZ2; + __IO uint32_t DOEPDMA2; + uint8_t RESERVED60[8]; + __IO uint32_t DOEPCTL3; + uint8_t RESERVED61[4]; + __IO uint32_t DOEPINT3; + uint8_t RESERVED62[4]; + __IO uint32_t DOEPTSIZ3; + __IO uint32_t DOEPDMA3; + uint8_t RESERVED63[8]; + __IO uint32_t DOEPCTL4; + uint8_t RESERVED64[4]; + __IO uint32_t DOEPINT4; + uint8_t RESERVED65[4]; + __IO uint32_t DOEPTSIZ4; + __IO uint32_t DOEPDMA4; + uint8_t RESERVED66[8]; + __IO uint32_t DOEPCTL5; + uint8_t RESERVED67[4]; + __IO uint32_t DOEPINT5; + uint8_t RESERVED68[4]; + __IO uint32_t DOEPTSIZ5; + __IO uint32_t DOEPDMA5; + uint8_t RESERVED69[584]; + __IO uint32_t GCCTL; +} CM_USBFS_TypeDef; + +/** + * @brief WDT + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t SR; + __IO uint32_t RR; +} CM_WDT_TypeDef; + +/******************************************************************************/ +/* Memory Base Address */ +/******************************************************************************/ +#define EFM_BASE (0x00000000UL) /*!< EFM base address in the alias region */ +#define SRAM_BASE (0x1FFF8000UL) /*!< SRAM base address in the alias region */ +#define QSPI_BASE (0x98000000UL) /*!< QSPI base address in the alias region */ + +/******************************************************************************/ +/* Device Specific Peripheral Base Address */ +/******************************************************************************/ +#define CM_ADC1_BASE (0x40040000UL) +#define CM_ADC2_BASE (0x40040400UL) +#define CM_AES_BASE (0x40008000UL) +#define CM_AOS_BASE (0x40010800UL) +#define CM_CAN_BASE (0x40070400UL) +#define CM_CMP1_BASE (0x4004A000UL) +#define CM_CMP2_BASE (0x4004A010UL) +#define CM_CMP3_BASE (0x4004A020UL) +#define CM_CMP_COMMON_BASE (0x4004A000UL) +#define CM_CMU_BASE (0x40054000UL) +#define CM_CRC_BASE (0x40008C00UL) +#define CM_DBGC_BASE (0xE0042000UL) +#define CM_DCU1_BASE (0x40052000UL) +#define CM_DCU2_BASE (0x40052400UL) +#define CM_DCU3_BASE (0x40052800UL) +#define CM_DCU4_BASE (0x40052C00UL) +#define CM_DMA1_BASE (0x40053000UL) +#define CM_DMA2_BASE (0x40053400UL) +#define CM_EFM_BASE (0x40010400UL) +#define CM_EMB0_BASE (0x40017C00UL) +#define CM_EMB1_BASE (0x40017C20UL) +#define CM_EMB2_BASE (0x40017C40UL) +#define CM_EMB3_BASE (0x40017C60UL) +#define CM_FCM_BASE (0x40048400UL) +#define CM_GPIO_BASE (0x40053800UL) +#define CM_HASH_BASE (0x40008400UL) +#define CM_I2C1_BASE (0x4004E000UL) +#define CM_I2C2_BASE (0x4004E400UL) +#define CM_I2C3_BASE (0x4004E800UL) +#define CM_I2S1_BASE (0x4001E000UL) +#define CM_I2S2_BASE (0x4001E400UL) +#define CM_I2S3_BASE (0x40022000UL) +#define CM_I2S4_BASE (0x40022400UL) +#define CM_ICG_BASE (0x00000400UL) +#define CM_INTC_BASE (0x40051000UL) +#define CM_KEYSCAN_BASE (0x40050C00UL) +#define CM_MPU_BASE (0x40050000UL) +#define CM_OTS_BASE (0x4004A400UL) +#define CM_PERIC_BASE (0x40055400UL) +#define CM_PWC_BASE (0x40048000UL) +#define CM_QSPI_BASE (0x9C000000UL) +#define CM_RMU_BASE (0x400540C0UL) +#define CM_RTC_BASE (0x4004C000UL) +#define CM_SDIOC1_BASE (0x4006FC00UL) +#define CM_SDIOC2_BASE (0x40070000UL) +#define CM_SPI1_BASE (0x4001C000UL) +#define CM_SPI2_BASE (0x4001C400UL) +#define CM_SPI3_BASE (0x40020000UL) +#define CM_SPI4_BASE (0x40020400UL) +#define CM_SRAMC_BASE (0x40050800UL) +#define CM_SWDT_BASE (0x40049400UL) +#define CM_TMR0_1_BASE (0x40024000UL) +#define CM_TMR0_2_BASE (0x40024400UL) +#define CM_TMR4_1_BASE (0x40017000UL) +#define CM_TMR4_2_BASE (0x40024800UL) +#define CM_TMR4_3_BASE (0x40024C00UL) +#define CM_TMR4_ECER_BASE (0x40055408UL) +#define CM_TMR6_1_BASE (0x40018000UL) +#define CM_TMR6_2_BASE (0x40018400UL) +#define CM_TMR6_3_BASE (0x40018800UL) +#define CM_TMR6_COMMON_BASE (0x40018300UL) +#define CM_TMRA_1_BASE (0x40015000UL) +#define CM_TMRA_2_BASE (0x40015400UL) +#define CM_TMRA_3_BASE (0x40015800UL) +#define CM_TMRA_4_BASE (0x40015C00UL) +#define CM_TMRA_5_BASE (0x40016000UL) +#define CM_TMRA_6_BASE (0x40016400UL) +#define CM_TRNG_BASE (0x40041000UL) +#define CM_USART1_BASE (0x4001D000UL) +#define CM_USART2_BASE (0x4001D400UL) +#define CM_USART3_BASE (0x40021000UL) +#define CM_USART4_BASE (0x40021400UL) +#define CM_USBFS_BASE (0x400C0000UL) +#define CM_WDT_BASE (0x40049000UL) + +/******************************************************************************/ +/* Device Specific Peripheral declaration & memory map */ +/******************************************************************************/ +#define CM_ADC1 ((CM_ADC_TypeDef *)CM_ADC1_BASE) +#define CM_ADC2 ((CM_ADC_TypeDef *)CM_ADC2_BASE) +#define CM_AES ((CM_AES_TypeDef *)CM_AES_BASE) +#define CM_AOS ((CM_AOS_TypeDef *)CM_AOS_BASE) +#define CM_CAN ((CM_CAN_TypeDef *)CM_CAN_BASE) +#define CM_CMP1 ((CM_CMP_TypeDef *)CM_CMP1_BASE) +#define CM_CMP2 ((CM_CMP_TypeDef *)CM_CMP2_BASE) +#define CM_CMP3 ((CM_CMP_TypeDef *)CM_CMP3_BASE) +#define CM_CMP_COMMON ((CM_CMP_COMMON_TypeDef *)CM_CMP_COMMON_BASE) +#define CM_CMU ((CM_CMU_TypeDef *)CM_CMU_BASE) +#define CM_CRC ((CM_CRC_TypeDef *)CM_CRC_BASE) +#define CM_DBGC ((CM_DBGC_TypeDef *)CM_DBGC_BASE) +#define CM_DCU1 ((CM_DCU_TypeDef *)CM_DCU1_BASE) +#define CM_DCU2 ((CM_DCU_TypeDef *)CM_DCU2_BASE) +#define CM_DCU3 ((CM_DCU_TypeDef *)CM_DCU3_BASE) +#define CM_DCU4 ((CM_DCU_TypeDef *)CM_DCU4_BASE) +#define CM_DMA1 ((CM_DMA_TypeDef *)CM_DMA1_BASE) +#define CM_DMA2 ((CM_DMA_TypeDef *)CM_DMA2_BASE) +#define CM_EFM ((CM_EFM_TypeDef *)CM_EFM_BASE) +#define CM_EMB0 ((CM_EMB_TypeDef *)CM_EMB0_BASE) +#define CM_EMB1 ((CM_EMB_TypeDef *)CM_EMB1_BASE) +#define CM_EMB2 ((CM_EMB_TypeDef *)CM_EMB2_BASE) +#define CM_EMB3 ((CM_EMB_TypeDef *)CM_EMB3_BASE) +#define CM_FCM ((CM_FCM_TypeDef *)CM_FCM_BASE) +#define CM_GPIO ((CM_GPIO_TypeDef *)CM_GPIO_BASE) +#define CM_HASH ((CM_HASH_TypeDef *)CM_HASH_BASE) +#define CM_I2C1 ((CM_I2C_TypeDef *)CM_I2C1_BASE) +#define CM_I2C2 ((CM_I2C_TypeDef *)CM_I2C2_BASE) +#define CM_I2C3 ((CM_I2C_TypeDef *)CM_I2C3_BASE) +#define CM_I2S1 ((CM_I2S_TypeDef *)CM_I2S1_BASE) +#define CM_I2S2 ((CM_I2S_TypeDef *)CM_I2S2_BASE) +#define CM_I2S3 ((CM_I2S_TypeDef *)CM_I2S3_BASE) +#define CM_I2S4 ((CM_I2S_TypeDef *)CM_I2S4_BASE) +#define CM_ICG ((CM_ICG_TypeDef *)CM_ICG_BASE) +#define CM_INTC ((CM_INTC_TypeDef *)CM_INTC_BASE) +#define CM_KEYSCAN ((CM_KEYSCAN_TypeDef *)CM_KEYSCAN_BASE) +#define CM_MPU ((CM_MPU_TypeDef *)CM_MPU_BASE) +#define CM_OTS ((CM_OTS_TypeDef *)CM_OTS_BASE) +#define CM_PERIC ((CM_PERIC_TypeDef *)CM_PERIC_BASE) +#define CM_PWC ((CM_PWC_TypeDef *)CM_PWC_BASE) +#define CM_QSPI ((CM_QSPI_TypeDef *)CM_QSPI_BASE) +#define CM_RMU ((CM_RMU_TypeDef *)CM_RMU_BASE) +#define CM_RTC ((CM_RTC_TypeDef *)CM_RTC_BASE) +#define CM_SDIOC1 ((CM_SDIOC_TypeDef *)CM_SDIOC1_BASE) +#define CM_SDIOC2 ((CM_SDIOC_TypeDef *)CM_SDIOC2_BASE) +#define CM_SPI1 ((CM_SPI_TypeDef *)CM_SPI1_BASE) +#define CM_SPI2 ((CM_SPI_TypeDef *)CM_SPI2_BASE) +#define CM_SPI3 ((CM_SPI_TypeDef *)CM_SPI3_BASE) +#define CM_SPI4 ((CM_SPI_TypeDef *)CM_SPI4_BASE) +#define CM_SRAMC ((CM_SRAMC_TypeDef *)CM_SRAMC_BASE) +#define CM_SWDT ((CM_SWDT_TypeDef *)CM_SWDT_BASE) +#define CM_TMR0_1 ((CM_TMR0_TypeDef *)CM_TMR0_1_BASE) +#define CM_TMR0_2 ((CM_TMR0_TypeDef *)CM_TMR0_2_BASE) +#define CM_TMR4_1 ((CM_TMR4_TypeDef *)CM_TMR4_1_BASE) +#define CM_TMR4_2 ((CM_TMR4_TypeDef *)CM_TMR4_2_BASE) +#define CM_TMR4_3 ((CM_TMR4_TypeDef *)CM_TMR4_3_BASE) +#define CM_TMR4_ECER ((CM_TMR4_ECER_TypeDef *)CM_TMR4_ECER_BASE) +#define CM_TMR6_1 ((CM_TMR6_TypeDef *)CM_TMR6_1_BASE) +#define CM_TMR6_2 ((CM_TMR6_TypeDef *)CM_TMR6_2_BASE) +#define CM_TMR6_3 ((CM_TMR6_TypeDef *)CM_TMR6_3_BASE) +#define CM_TMR6_COMMON ((CM_TMR6_COMMON_TypeDef *)CM_TMR6_COMMON_BASE) +#define CM_TMRA_1 ((CM_TMRA_TypeDef *)CM_TMRA_1_BASE) +#define CM_TMRA_2 ((CM_TMRA_TypeDef *)CM_TMRA_2_BASE) +#define CM_TMRA_3 ((CM_TMRA_TypeDef *)CM_TMRA_3_BASE) +#define CM_TMRA_4 ((CM_TMRA_TypeDef *)CM_TMRA_4_BASE) +#define CM_TMRA_5 ((CM_TMRA_TypeDef *)CM_TMRA_5_BASE) +#define CM_TMRA_6 ((CM_TMRA_TypeDef *)CM_TMRA_6_BASE) +#define CM_TRNG ((CM_TRNG_TypeDef *)CM_TRNG_BASE) +#define CM_USART1 ((CM_USART_TypeDef *)CM_USART1_BASE) +#define CM_USART2 ((CM_USART_TypeDef *)CM_USART2_BASE) +#define CM_USART3 ((CM_USART_TypeDef *)CM_USART3_BASE) +#define CM_USART4 ((CM_USART_TypeDef *)CM_USART4_BASE) +#define CM_USBFS ((CM_USBFS_TypeDef *)CM_USBFS_BASE) +#define CM_WDT ((CM_WDT_TypeDef *)CM_WDT_BASE) + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************* + Bit definition for Peripheral ADC +*******************************************************************************/ +/* Bit definition for ADC_STR register */ +#define ADC_STR_STRT (0x01U) + +/* Bit definition for ADC_CR0 register */ +#define ADC_CR0_MS_POS (0U) +#define ADC_CR0_MS (0x0003U) +#define ADC_CR0_MS_0 (0x0001U) +#define ADC_CR0_MS_1 (0x0002U) +#define ADC_CR0_ACCSEL_POS (4U) +#define ADC_CR0_ACCSEL (0x0030U) +#define ADC_CR0_ACCSEL_0 (0x0010U) +#define ADC_CR0_ACCSEL_1 (0x0020U) +#define ADC_CR0_CLREN_POS (6U) +#define ADC_CR0_CLREN (0x0040U) +#define ADC_CR0_DFMT_POS (7U) +#define ADC_CR0_DFMT (0x0080U) +#define ADC_CR0_AVCNT_POS (8U) +#define ADC_CR0_AVCNT (0x0700U) + +/* Bit definition for ADC_CR1 register */ +#define ADC_CR1_RSCHSEL_POS (2U) +#define ADC_CR1_RSCHSEL (0x0004U) + +/* Bit definition for ADC_TRGSR register */ +#define ADC_TRGSR_TRGSELA_POS (0U) +#define ADC_TRGSR_TRGSELA (0x0003U) +#define ADC_TRGSR_TRGSELA_0 (0x0001U) +#define ADC_TRGSR_TRGSELA_1 (0x0002U) +#define ADC_TRGSR_TRGENA_POS (7U) +#define ADC_TRGSR_TRGENA (0x0080U) +#define ADC_TRGSR_TRGSELB_POS (8U) +#define ADC_TRGSR_TRGSELB (0x0300U) +#define ADC_TRGSR_TRGSELB_0 (0x0100U) +#define ADC_TRGSR_TRGSELB_1 (0x0200U) +#define ADC_TRGSR_TRGENB_POS (15U) +#define ADC_TRGSR_TRGENB (0x8000U) + +/* Bit definition for ADC_CHSELRA register */ +#define ADC_CHSELRA_CHSELA (0x0001FFFFUL) + +/* Bit definition for ADC_CHSELRB register */ +#define ADC_CHSELRB_CHSELB (0x0001FFFFUL) + +/* Bit definition for ADC_AVCHSELR register */ +#define ADC_AVCHSELR_AVCHSEL (0x0001FFFFUL) + +/* Bit definition for ADC_SSTR0 register */ +#define ADC_SSTR0 (0xFFU) + +/* Bit definition for ADC_SSTR1 register */ +#define ADC_SSTR1 (0xFFU) + +/* Bit definition for ADC_SSTR2 register */ +#define ADC_SSTR2 (0xFFU) + +/* Bit definition for ADC_SSTR3 register */ +#define ADC_SSTR3 (0xFFU) + +/* Bit definition for ADC_SSTR4 register */ +#define ADC_SSTR4 (0xFFU) + +/* Bit definition for ADC_SSTR5 register */ +#define ADC_SSTR5 (0xFFU) + +/* Bit definition for ADC_SSTR6 register */ +#define ADC_SSTR6 (0xFFU) + +/* Bit definition for ADC_SSTR7 register */ +#define ADC_SSTR7 (0xFFU) + +/* Bit definition for ADC_SSTR8 register */ +#define ADC_SSTR8 (0xFFU) + +/* Bit definition for ADC_SSTR9 register */ +#define ADC_SSTR9 (0xFFU) + +/* Bit definition for ADC_SSTR10 register */ +#define ADC_SSTR10 (0xFFU) + +/* Bit definition for ADC_SSTR11 register */ +#define ADC_SSTR11 (0xFFU) + +/* Bit definition for ADC_SSTR12 register */ +#define ADC_SSTR12 (0xFFU) + +/* Bit definition for ADC_SSTR13 register */ +#define ADC_SSTR13 (0xFFU) + +/* Bit definition for ADC_SSTR14 register */ +#define ADC_SSTR14 (0xFFU) + +/* Bit definition for ADC_SSTR15 register */ +#define ADC_SSTR15 (0xFFU) + +/* Bit definition for ADC_SSTRL register */ +#define ADC_SSTRL (0xFFU) + +/* Bit definition for ADC_CHMUXR0 register */ +#define ADC_CHMUXR0_CH00MUX_POS (0U) +#define ADC_CHMUXR0_CH00MUX (0x000FU) +#define ADC_CHMUXR0_CH01MUX_POS (4U) +#define ADC_CHMUXR0_CH01MUX (0x00F0U) +#define ADC_CHMUXR0_CH02MUX_POS (8U) +#define ADC_CHMUXR0_CH02MUX (0x0F00U) +#define ADC_CHMUXR0_CH03MUX_POS (12U) +#define ADC_CHMUXR0_CH03MUX (0xF000U) + +/* Bit definition for ADC_CHMUXR1 register */ +#define ADC_CHMUXR1_CH04MUX_POS (0U) +#define ADC_CHMUXR1_CH04MUX (0x000FU) +#define ADC_CHMUXR1_CH05MUX_POS (4U) +#define ADC_CHMUXR1_CH05MUX (0x00F0U) +#define ADC_CHMUXR1_CH06MUX_POS (8U) +#define ADC_CHMUXR1_CH06MUX (0x0F00U) +#define ADC_CHMUXR1_CH07MUX_POS (12U) +#define ADC_CHMUXR1_CH07MUX (0xF000U) + +/* Bit definition for ADC_CHMUXR2 register */ +#define ADC_CHMUXR2_CH08MUX_POS (0U) +#define ADC_CHMUXR2_CH08MUX (0x000FU) +#define ADC_CHMUXR2_CH09MUX_POS (4U) +#define ADC_CHMUXR2_CH09MUX (0x00F0U) +#define ADC_CHMUXR2_CH10MUX_POS (8U) +#define ADC_CHMUXR2_CH10MUX (0x0F00U) +#define ADC_CHMUXR2_CH11MUX_POS (12U) +#define ADC_CHMUXR2_CH11MUX (0xF000U) + +/* Bit definition for ADC_CHMUXR3 register */ +#define ADC_CHMUXR3_CH12MUX_POS (0U) +#define ADC_CHMUXR3_CH12MUX (0x000FU) +#define ADC_CHMUXR3_CH13MUX_POS (4U) +#define ADC_CHMUXR3_CH13MUX (0x00F0U) +#define ADC_CHMUXR3_CH14MUX_POS (8U) +#define ADC_CHMUXR3_CH14MUX (0x0F00U) +#define ADC_CHMUXR3_CH15MUX_POS (12U) +#define ADC_CHMUXR3_CH15MUX (0xF000U) + +/* Bit definition for ADC_ISR register */ +#define ADC_ISR_EOCAF_POS (0U) +#define ADC_ISR_EOCAF (0x01U) +#define ADC_ISR_EOCBF_POS (1U) +#define ADC_ISR_EOCBF (0x02U) + +/* Bit definition for ADC_ICR register */ +#define ADC_ICR_EOCAIEN_POS (0U) +#define ADC_ICR_EOCAIEN (0x01U) +#define ADC_ICR_EOCBIEN_POS (1U) +#define ADC_ICR_EOCBIEN (0x02U) + +/* Bit definition for ADC_SYNCCR register */ +#define ADC_SYNCCR_SYNCEN_POS (0U) +#define ADC_SYNCCR_SYNCEN (0x0001U) +#define ADC_SYNCCR_SYNCMD_POS (4U) +#define ADC_SYNCCR_SYNCMD (0x0070U) +#define ADC_SYNCCR_SYNCDLY_POS (8U) +#define ADC_SYNCCR_SYNCDLY (0xFF00U) + +/* Bit definition for ADC_DR0 register */ +#define ADC_DR0 (0xFFFFU) + +/* Bit definition for ADC_DR1 register */ +#define ADC_DR1 (0xFFFFU) + +/* Bit definition for ADC_DR2 register */ +#define ADC_DR2 (0xFFFFU) + +/* Bit definition for ADC_DR3 register */ +#define ADC_DR3 (0xFFFFU) + +/* Bit definition for ADC_DR4 register */ +#define ADC_DR4 (0xFFFFU) + +/* Bit definition for ADC_DR5 register */ +#define ADC_DR5 (0xFFFFU) + +/* Bit definition for ADC_DR6 register */ +#define ADC_DR6 (0xFFFFU) + +/* Bit definition for ADC_DR7 register */ +#define ADC_DR7 (0xFFFFU) + +/* Bit definition for ADC_DR8 register */ +#define ADC_DR8 (0xFFFFU) + +/* Bit definition for ADC_DR9 register */ +#define ADC_DR9 (0xFFFFU) + +/* Bit definition for ADC_DR10 register */ +#define ADC_DR10 (0xFFFFU) + +/* Bit definition for ADC_DR11 register */ +#define ADC_DR11 (0xFFFFU) + +/* Bit definition for ADC_DR12 register */ +#define ADC_DR12 (0xFFFFU) + +/* Bit definition for ADC_DR13 register */ +#define ADC_DR13 (0xFFFFU) + +/* Bit definition for ADC_DR14 register */ +#define ADC_DR14 (0xFFFFU) + +/* Bit definition for ADC_DR15 register */ +#define ADC_DR15 (0xFFFFU) + +/* Bit definition for ADC_DR16 register */ +#define ADC_DR16 (0xFFFFU) + +/* Bit definition for ADC_AWDCR register */ +#define ADC_AWDCR_AWDEN_POS (0U) +#define ADC_AWDCR_AWDEN (0x0001U) +#define ADC_AWDCR_AWDMD_POS (4U) +#define ADC_AWDCR_AWDMD (0x0010U) +#define ADC_AWDCR_AWDSS_POS (6U) +#define ADC_AWDCR_AWDSS (0x00C0U) +#define ADC_AWDCR_AWDSS_0 (0x0040U) +#define ADC_AWDCR_AWDSS_1 (0x0080U) +#define ADC_AWDCR_AWDIEN_POS (8U) +#define ADC_AWDCR_AWDIEN (0x0100U) + +/* Bit definition for ADC_AWDDR0 register */ +#define ADC_AWDDR0 (0xFFFFU) + +/* Bit definition for ADC_AWDDR1 register */ +#define ADC_AWDDR1 (0xFFFFU) + +/* Bit definition for ADC_AWDCHSR register */ +#define ADC_AWDCHSR_AWDCH (0x0001FFFFUL) + +/* Bit definition for ADC_AWDSR register */ +#define ADC_AWDSR_AWDF (0x0001FFFFUL) + +/* Bit definition for ADC_PGACR register */ +#define ADC_PGACR_PGACTL (0x000FU) + +/* Bit definition for ADC_PGAGSR register */ +#define ADC_PGAGSR_GAIN (0x000FU) + +/* Bit definition for ADC_PGAINSR0 register */ +#define ADC_PGAINSR0_PGAINSEL (0x01FFU) +#define ADC_PGAINSR0_PGAINSEL_0 (0x0001U) +#define ADC_PGAINSR0_PGAINSEL_1 (0x0002U) +#define ADC_PGAINSR0_PGAINSEL_2 (0x0004U) +#define ADC_PGAINSR0_PGAINSEL_3 (0x0008U) +#define ADC_PGAINSR0_PGAINSEL_4 (0x0010U) +#define ADC_PGAINSR0_PGAINSEL_5 (0x0020U) +#define ADC_PGAINSR0_PGAINSEL_6 (0x0040U) +#define ADC_PGAINSR0_PGAINSEL_7 (0x0080U) +#define ADC_PGAINSR0_PGAINSEL_8 (0x0100U) + +/* Bit definition for ADC_PGAINSR1 register */ +#define ADC_PGAINSR1_PGAVSSEN (0x0001U) + +/******************************************************************************* + Bit definition for Peripheral AES +*******************************************************************************/ +/* Bit definition for AES_CR register */ +#define AES_CR_START_POS (0U) +#define AES_CR_START (0x00000001UL) +#define AES_CR_MODE_POS (1U) +#define AES_CR_MODE (0x00000002UL) + +/* Bit definition for AES_DR0 register */ +#define AES_DR0 (0xFFFFFFFFUL) + +/* Bit definition for AES_DR1 register */ +#define AES_DR1 (0xFFFFFFFFUL) + +/* Bit definition for AES_DR2 register */ +#define AES_DR2 (0xFFFFFFFFUL) + +/* Bit definition for AES_DR3 register */ +#define AES_DR3 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR0 register */ +#define AES_KR0 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR1 register */ +#define AES_KR1 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR2 register */ +#define AES_KR2 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR3 register */ +#define AES_KR3 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral AOS +*******************************************************************************/ +/* Bit definition for AOS_INTSFTTRG register */ +#define AOS_INTSFTTRG_STRG (0x00000001UL) + +/* Bit definition for AOS_DCU_TRGSEL register */ +#define AOS_DCU_TRGSEL_TRGSEL_POS (0U) +#define AOS_DCU_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DCU_TRGSEL_COMEN_POS (30U) +#define AOS_DCU_TRGSEL_COMEN (0xC0000000UL) +#define AOS_DCU_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_DCU_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_DMA1_TRGSEL register */ +#define AOS_DMA1_TRGSEL_TRGSEL_POS (0U) +#define AOS_DMA1_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DMA1_TRGSEL_COMEN_POS (30U) +#define AOS_DMA1_TRGSEL_COMEN (0xC0000000UL) +#define AOS_DMA1_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_DMA1_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_DMA2_TRGSEL register */ +#define AOS_DMA2_TRGSEL_TRGSEL_POS (0U) +#define AOS_DMA2_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DMA2_TRGSEL_COMEN_POS (30U) +#define AOS_DMA2_TRGSEL_COMEN (0xC0000000UL) +#define AOS_DMA2_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_DMA2_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_DMA_RC_TRGSEL register */ +#define AOS_DMA_RC_TRGSEL_TRGSEL_POS (0U) +#define AOS_DMA_RC_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DMA_RC_TRGSEL_COMEN_POS (30U) +#define AOS_DMA_RC_TRGSEL_COMEN (0xC0000000UL) +#define AOS_DMA_RC_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_DMA_RC_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_TMR6_TRGSEL register */ +#define AOS_TMR6_TRGSEL_TRGSEL_POS (0U) +#define AOS_TMR6_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_TMR6_TRGSEL_COMEN_POS (30U) +#define AOS_TMR6_TRGSEL_COMEN (0xC0000000UL) +#define AOS_TMR6_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_TMR6_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_TMR0_TRGSEL register */ +#define AOS_TMR0_TRGSEL_TRGSEL_POS (0U) +#define AOS_TMR0_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_TMR0_TRGSEL_COMEN_POS (30U) +#define AOS_TMR0_TRGSEL_COMEN (0xC0000000UL) +#define AOS_TMR0_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_TMR0_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_PEVNT_TRGSEL register */ +#define AOS_PEVNT_TRGSEL_TRGSEL_POS (0U) +#define AOS_PEVNT_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_PEVNT_TRGSEL_COMEN_POS (30U) +#define AOS_PEVNT_TRGSEL_COMEN (0xC0000000UL) +#define AOS_PEVNT_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_PEVNT_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_TMRA_TRGSEL register */ +#define AOS_TMRA_TRGSEL_TRGSEL_POS (0U) +#define AOS_TMRA_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_TMRA_TRGSEL_COMEN_POS (30U) +#define AOS_TMRA_TRGSEL_COMEN (0xC0000000UL) +#define AOS_TMRA_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_TMRA_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_OTS_TRGSEL register */ +#define AOS_OTS_TRGSEL_TRGSEL_POS (0U) +#define AOS_OTS_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_OTS_TRGSEL_COMEN_POS (30U) +#define AOS_OTS_TRGSEL_COMEN (0xC0000000UL) +#define AOS_OTS_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_OTS_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_ADC1_TRGSEL register */ +#define AOS_ADC1_TRGSEL_TRGSEL_POS (0U) +#define AOS_ADC1_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_ADC1_TRGSEL_COMEN_POS (30U) +#define AOS_ADC1_TRGSEL_COMEN (0xC0000000UL) +#define AOS_ADC1_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_ADC1_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_ADC2_TRGSEL register */ +#define AOS_ADC2_TRGSEL_TRGSEL_POS (0U) +#define AOS_ADC2_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_ADC2_TRGSEL_COMEN_POS (30U) +#define AOS_ADC2_TRGSEL_COMEN (0xC0000000UL) +#define AOS_ADC2_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_ADC2_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_COMTRG1 register */ +#define AOS_COMTRG1_COMTRG (0x000001FFUL) + +/* Bit definition for AOS_COMTRG2 register */ +#define AOS_COMTRG2_COMTRG (0x000001FFUL) + +/* Bit definition for AOS_PEVNTDIRR register */ +#define AOS_PEVNTDIRR_PDIR (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTIDR register */ +#define AOS_PEVNTIDR_PIN (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTODR register */ +#define AOS_PEVNTODR_POUT (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTORR register */ +#define AOS_PEVNTORR_POR (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTOSR register */ +#define AOS_PEVNTOSR_POS (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTRISR register */ +#define AOS_PEVNTRISR_RIS (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTFALR register */ +#define AOS_PEVNTFALR_FAL (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTNFCR register */ +#define AOS_PEVNTNFCR_NFEN1_POS (0U) +#define AOS_PEVNTNFCR_NFEN1 (0x00000001UL) +#define AOS_PEVNTNFCR_DIVS1_POS (1U) +#define AOS_PEVNTNFCR_DIVS1 (0x00000006UL) +#define AOS_PEVNTNFCR_NFEN2_POS (8U) +#define AOS_PEVNTNFCR_NFEN2 (0x00000100UL) +#define AOS_PEVNTNFCR_DIVS2_POS (9U) +#define AOS_PEVNTNFCR_DIVS2 (0x00000600UL) +#define AOS_PEVNTNFCR_NFEN3_POS (16U) +#define AOS_PEVNTNFCR_NFEN3 (0x00010000UL) +#define AOS_PEVNTNFCR_DIVS3_POS (17U) +#define AOS_PEVNTNFCR_DIVS3 (0x00060000UL) +#define AOS_PEVNTNFCR_NFEN4_POS (24U) +#define AOS_PEVNTNFCR_NFEN4 (0x01000000UL) +#define AOS_PEVNTNFCR_DIVS4_POS (25U) +#define AOS_PEVNTNFCR_DIVS4 (0x06000000UL) + +/******************************************************************************* + Bit definition for Peripheral CAN +*******************************************************************************/ +/* Bit definition for CAN_RBUF register */ +#define CAN_RBUF (0xFFFFFFFFUL) + +/* Bit definition for CAN_TBUF register */ +#define CAN_TBUF (0xFFFFFFFFUL) + +/* Bit definition for CAN_CFG_STAT register */ +#define CAN_CFG_STAT_BUSOFF_POS (0U) +#define CAN_CFG_STAT_BUSOFF (0x01U) +#define CAN_CFG_STAT_TACTIVE_POS (1U) +#define CAN_CFG_STAT_TACTIVE (0x02U) +#define CAN_CFG_STAT_RACTIVE_POS (2U) +#define CAN_CFG_STAT_RACTIVE (0x04U) +#define CAN_CFG_STAT_TSSS_POS (3U) +#define CAN_CFG_STAT_TSSS (0x08U) +#define CAN_CFG_STAT_TPSS_POS (4U) +#define CAN_CFG_STAT_TPSS (0x10U) +#define CAN_CFG_STAT_LBMI_POS (5U) +#define CAN_CFG_STAT_LBMI (0x20U) +#define CAN_CFG_STAT_LBME_POS (6U) +#define CAN_CFG_STAT_LBME (0x40U) +#define CAN_CFG_STAT_RESET_POS (7U) +#define CAN_CFG_STAT_RESET (0x80U) + +/* Bit definition for CAN_TCMD register */ +#define CAN_TCMD_TSA_POS (0U) +#define CAN_TCMD_TSA (0x01U) +#define CAN_TCMD_TSALL_POS (1U) +#define CAN_TCMD_TSALL (0x02U) +#define CAN_TCMD_TSONE_POS (2U) +#define CAN_TCMD_TSONE (0x04U) +#define CAN_TCMD_TPA_POS (3U) +#define CAN_TCMD_TPA (0x08U) +#define CAN_TCMD_TPE_POS (4U) +#define CAN_TCMD_TPE (0x10U) +#define CAN_TCMD_LOM_POS (6U) +#define CAN_TCMD_LOM (0x40U) +#define CAN_TCMD_TBSEL_POS (7U) +#define CAN_TCMD_TBSEL (0x80U) + +/* Bit definition for CAN_TCTRL register */ +#define CAN_TCTRL_TSSTAT_POS (0U) +#define CAN_TCTRL_TSSTAT (0x03U) +#define CAN_TCTRL_TSSTAT_0 (0x01U) +#define CAN_TCTRL_TSSTAT_1 (0x02U) +#define CAN_TCTRL_TTTBM_POS (4U) +#define CAN_TCTRL_TTTBM (0x10U) +#define CAN_TCTRL_TSMODE_POS (5U) +#define CAN_TCTRL_TSMODE (0x20U) +#define CAN_TCTRL_TSNEXT_POS (6U) +#define CAN_TCTRL_TSNEXT (0x40U) + +/* Bit definition for CAN_RCTRL register */ +#define CAN_RCTRL_RSTAT_POS (0U) +#define CAN_RCTRL_RSTAT (0x03U) +#define CAN_RCTRL_RSTAT_0 (0x01U) +#define CAN_RCTRL_RSTAT_1 (0x02U) +#define CAN_RCTRL_RBALL_POS (3U) +#define CAN_RCTRL_RBALL (0x08U) +#define CAN_RCTRL_RREL_POS (4U) +#define CAN_RCTRL_RREL (0x10U) +#define CAN_RCTRL_ROV_POS (5U) +#define CAN_RCTRL_ROV (0x20U) +#define CAN_RCTRL_ROM_POS (6U) +#define CAN_RCTRL_ROM (0x40U) +#define CAN_RCTRL_SACK_POS (7U) +#define CAN_RCTRL_SACK (0x80U) + +/* Bit definition for CAN_RTIE register */ +#define CAN_RTIE_TSFF_POS (0U) +#define CAN_RTIE_TSFF (0x01U) +#define CAN_RTIE_EIE_POS (1U) +#define CAN_RTIE_EIE (0x02U) +#define CAN_RTIE_TSIE_POS (2U) +#define CAN_RTIE_TSIE (0x04U) +#define CAN_RTIE_TPIE_POS (3U) +#define CAN_RTIE_TPIE (0x08U) +#define CAN_RTIE_RAFIE_POS (4U) +#define CAN_RTIE_RAFIE (0x10U) +#define CAN_RTIE_RFIE_POS (5U) +#define CAN_RTIE_RFIE (0x20U) +#define CAN_RTIE_ROIE_POS (6U) +#define CAN_RTIE_ROIE (0x40U) +#define CAN_RTIE_RIE_POS (7U) +#define CAN_RTIE_RIE (0x80U) + +/* Bit definition for CAN_RTIF register */ +#define CAN_RTIF_AIF_POS (0U) +#define CAN_RTIF_AIF (0x01U) +#define CAN_RTIF_EIF_POS (1U) +#define CAN_RTIF_EIF (0x02U) +#define CAN_RTIF_TSIF_POS (2U) +#define CAN_RTIF_TSIF (0x04U) +#define CAN_RTIF_TPIF_POS (3U) +#define CAN_RTIF_TPIF (0x08U) +#define CAN_RTIF_RAFIF_POS (4U) +#define CAN_RTIF_RAFIF (0x10U) +#define CAN_RTIF_RFIF_POS (5U) +#define CAN_RTIF_RFIF (0x20U) +#define CAN_RTIF_ROIF_POS (6U) +#define CAN_RTIF_ROIF (0x40U) +#define CAN_RTIF_RIF_POS (7U) +#define CAN_RTIF_RIF (0x80U) + +/* Bit definition for CAN_ERRINT register */ +#define CAN_ERRINT_BEIF_POS (0U) +#define CAN_ERRINT_BEIF (0x01U) +#define CAN_ERRINT_BEIE_POS (1U) +#define CAN_ERRINT_BEIE (0x02U) +#define CAN_ERRINT_ALIF_POS (2U) +#define CAN_ERRINT_ALIF (0x04U) +#define CAN_ERRINT_ALIE_POS (3U) +#define CAN_ERRINT_ALIE (0x08U) +#define CAN_ERRINT_EPIF_POS (4U) +#define CAN_ERRINT_EPIF (0x10U) +#define CAN_ERRINT_EPIE_POS (5U) +#define CAN_ERRINT_EPIE (0x20U) +#define CAN_ERRINT_EPASS_POS (6U) +#define CAN_ERRINT_EPASS (0x40U) +#define CAN_ERRINT_EWARN_POS (7U) +#define CAN_ERRINT_EWARN (0x80U) + +/* Bit definition for CAN_LIMIT register */ +#define CAN_LIMIT_EWL_POS (0U) +#define CAN_LIMIT_EWL (0x0FU) +#define CAN_LIMIT_AFWL_POS (4U) +#define CAN_LIMIT_AFWL (0xF0U) + +/* Bit definition for CAN_SBT register */ +#define CAN_SBT_S_SEG_1_POS (0U) +#define CAN_SBT_S_SEG_1 (0x000000FFUL) +#define CAN_SBT_S_SEG_2_POS (8U) +#define CAN_SBT_S_SEG_2 (0x00007F00UL) +#define CAN_SBT_S_SJW_POS (16U) +#define CAN_SBT_S_SJW (0x007F0000UL) +#define CAN_SBT_S_PRESC_POS (24U) +#define CAN_SBT_S_PRESC (0xFF000000UL) + +/* Bit definition for CAN_EALCAP register */ +#define CAN_EALCAP_ALC_POS (0U) +#define CAN_EALCAP_ALC (0x1FU) +#define CAN_EALCAP_KOER_POS (5U) +#define CAN_EALCAP_KOER (0xE0U) + +/* Bit definition for CAN_RECNT register */ +#define CAN_RECNT (0xFFU) + +/* Bit definition for CAN_TECNT register */ +#define CAN_TECNT (0xFFU) + +/* Bit definition for CAN_ACFCTRL register */ +#define CAN_ACFCTRL_ACFADR_POS (0U) +#define CAN_ACFCTRL_ACFADR (0x0FU) +#define CAN_ACFCTRL_SELMASK_POS (5U) +#define CAN_ACFCTRL_SELMASK (0x20U) + +/* Bit definition for CAN_ACFEN register */ +#define CAN_ACFEN_AE_1_POS (0U) +#define CAN_ACFEN_AE_1 (0x01U) +#define CAN_ACFEN_AE_2_POS (1U) +#define CAN_ACFEN_AE_2 (0x02U) +#define CAN_ACFEN_AE_3_POS (2U) +#define CAN_ACFEN_AE_3 (0x04U) +#define CAN_ACFEN_AE_4_POS (3U) +#define CAN_ACFEN_AE_4 (0x08U) +#define CAN_ACFEN_AE_5_POS (4U) +#define CAN_ACFEN_AE_5 (0x10U) +#define CAN_ACFEN_AE_6_POS (5U) +#define CAN_ACFEN_AE_6 (0x20U) +#define CAN_ACFEN_AE_7_POS (6U) +#define CAN_ACFEN_AE_7 (0x40U) +#define CAN_ACFEN_AE_8_POS (7U) +#define CAN_ACFEN_AE_8 (0x80U) + +/* Bit definition for CAN_ACF register */ +#define CAN_ACF_ACODEORAMASK_POS (0U) +#define CAN_ACF_ACODEORAMASK (0x1FFFFFFFUL) +#define CAN_ACF_AIDE_POS (29U) +#define CAN_ACF_AIDE (0x20000000UL) +#define CAN_ACF_AIDEE_POS (30U) +#define CAN_ACF_AIDEE (0x40000000UL) + +/* Bit definition for CAN_TBSLOT register */ +#define CAN_TBSLOT_TBPTR_POS (0U) +#define CAN_TBSLOT_TBPTR (0x3FU) +#define CAN_TBSLOT_TBF_POS (6U) +#define CAN_TBSLOT_TBF (0x40U) +#define CAN_TBSLOT_TBE_POS (7U) +#define CAN_TBSLOT_TBE (0x80U) + +/* Bit definition for CAN_TTCFG register */ +#define CAN_TTCFG_TTEN_POS (0U) +#define CAN_TTCFG_TTEN (0x01U) +#define CAN_TTCFG_T_PRESC_POS (1U) +#define CAN_TTCFG_T_PRESC (0x06U) +#define CAN_TTCFG_T_PRESC_0 (0x02U) +#define CAN_TTCFG_T_PRESC_1 (0x04U) +#define CAN_TTCFG_TTIF_POS (3U) +#define CAN_TTCFG_TTIF (0x08U) +#define CAN_TTCFG_TTIE_POS (4U) +#define CAN_TTCFG_TTIE (0x10U) +#define CAN_TTCFG_TEIF_POS (5U) +#define CAN_TTCFG_TEIF (0x20U) +#define CAN_TTCFG_WTIF_POS (6U) +#define CAN_TTCFG_WTIF (0x40U) +#define CAN_TTCFG_WTIE_POS (7U) +#define CAN_TTCFG_WTIE (0x80U) + +/* Bit definition for CAN_REF_MSG register */ +#define CAN_REF_MSG_REF_ID_POS (0U) +#define CAN_REF_MSG_REF_ID (0x1FFFFFFFUL) +#define CAN_REF_MSG_REF_IDE_POS (31U) +#define CAN_REF_MSG_REF_IDE (0x80000000UL) + +/* Bit definition for CAN_TRG_CFG register */ +#define CAN_TRG_CFG_TTPTR_POS (0U) +#define CAN_TRG_CFG_TTPTR (0x003FU) +#define CAN_TRG_CFG_TTYPE_POS (8U) +#define CAN_TRG_CFG_TTYPE (0x0700U) +#define CAN_TRG_CFG_TTYPE_0 (0x0100U) +#define CAN_TRG_CFG_TTYPE_1 (0x0200U) +#define CAN_TRG_CFG_TTYPE_2 (0x0400U) +#define CAN_TRG_CFG_TEW_POS (12U) +#define CAN_TRG_CFG_TEW (0xF000U) + +/* Bit definition for CAN_TT_TRIG register */ +#define CAN_TT_TRIG (0xFFFFU) + +/* Bit definition for CAN_TT_WTRIG register */ +#define CAN_TT_WTRIG (0xFFFFU) + +/******************************************************************************* + Bit definition for Peripheral CMP +*******************************************************************************/ +/* Bit definition for CMP_CTRL register */ +#define CMP_CTRL_FLTSL_POS (0U) +#define CMP_CTRL_FLTSL (0x0007U) +#define CMP_CTRL_EDGSL_POS (5U) +#define CMP_CTRL_EDGSL (0x0060U) +#define CMP_CTRL_EDGSL_0 (0x0020U) +#define CMP_CTRL_EDGSL_1 (0x0040U) +#define CMP_CTRL_IEN_POS (7U) +#define CMP_CTRL_IEN (0x0080U) +#define CMP_CTRL_CVSEN_POS (8U) +#define CMP_CTRL_CVSEN (0x0100U) +#define CMP_CTRL_OUTEN_POS (12U) +#define CMP_CTRL_OUTEN (0x1000U) +#define CMP_CTRL_INV_POS (13U) +#define CMP_CTRL_INV (0x2000U) +#define CMP_CTRL_CMPOE_POS (14U) +#define CMP_CTRL_CMPOE (0x4000U) +#define CMP_CTRL_CMPON_POS (15U) +#define CMP_CTRL_CMPON (0x8000U) + +/* Bit definition for CMP_VLTSEL register */ +#define CMP_VLTSEL_RVSL_POS (0U) +#define CMP_VLTSEL_RVSL (0x000FU) +#define CMP_VLTSEL_RVSL_0 (0x0001U) +#define CMP_VLTSEL_RVSL_1 (0x0002U) +#define CMP_VLTSEL_RVSL_2 (0x0004U) +#define CMP_VLTSEL_RVSL_3 (0x0008U) +#define CMP_VLTSEL_CVSL_POS (8U) +#define CMP_VLTSEL_CVSL (0x0F00U) +#define CMP_VLTSEL_CVSL_0 (0x0100U) +#define CMP_VLTSEL_CVSL_1 (0x0200U) +#define CMP_VLTSEL_CVSL_2 (0x0400U) +#define CMP_VLTSEL_CVSL_3 (0x0800U) +#define CMP_VLTSEL_C4SL_POS (12U) +#define CMP_VLTSEL_C4SL (0x7000U) +#define CMP_VLTSEL_C4SL_0 (0x1000U) +#define CMP_VLTSEL_C4SL_1 (0x2000U) +#define CMP_VLTSEL_C4SL_2 (0x4000U) + +/* Bit definition for CMP_OUTMON register */ +#define CMP_OUTMON_OMON_POS (0U) +#define CMP_OUTMON_OMON (0x0001U) +#define CMP_OUTMON_CVST_POS (8U) +#define CMP_OUTMON_CVST (0x0F00U) + +/* Bit definition for CMP_CVSSTB register */ +#define CMP_CVSSTB_STB (0x000FU) + +/* Bit definition for CMP_CVSPRD register */ +#define CMP_CVSPRD_PRD (0x00FFU) + +/******************************************************************************* + Bit definition for Peripheral CMP_COMMON +*******************************************************************************/ +/* Bit definition for CMP_COMMON_DADR1 register */ +#define CMP_COMMON_DADR1_DATA (0x00FFU) + +/* Bit definition for CMP_COMMON_DADR2 register */ +#define CMP_COMMON_DADR2_DATA (0x00FFU) + +/* Bit definition for CMP_COMMON_DACR register */ +#define CMP_COMMON_DACR_DA1EN_POS (0U) +#define CMP_COMMON_DACR_DA1EN (0x0001U) +#define CMP_COMMON_DACR_DA2EN_POS (1U) +#define CMP_COMMON_DACR_DA2EN (0x0002U) + +/* Bit definition for CMP_COMMON_RVADC register */ +#define CMP_COMMON_RVADC_DA1SW_POS (0U) +#define CMP_COMMON_RVADC_DA1SW (0x0001U) +#define CMP_COMMON_RVADC_DA2SW_POS (1U) +#define CMP_COMMON_RVADC_DA2SW (0x0002U) +#define CMP_COMMON_RVADC_VREFSW_POS (4U) +#define CMP_COMMON_RVADC_VREFSW (0x0010U) +#define CMP_COMMON_RVADC_WPRT_POS (8U) +#define CMP_COMMON_RVADC_WPRT (0xFF00U) + +/******************************************************************************* + Bit definition for Peripheral CMU +*******************************************************************************/ +/* Bit definition for CMU_PERICKSEL register */ +#define CMU_PERICKSEL_PERICKSEL (0x000FU) + +/* Bit definition for CMU_I2SCKSEL register */ +#define CMU_I2SCKSEL_I2S1CKSEL_POS (0U) +#define CMU_I2SCKSEL_I2S1CKSEL (0x000FU) +#define CMU_I2SCKSEL_I2S2CKSEL_POS (4U) +#define CMU_I2SCKSEL_I2S2CKSEL (0x00F0U) +#define CMU_I2SCKSEL_I2S3CKSEL_POS (8U) +#define CMU_I2SCKSEL_I2S3CKSEL (0x0F00U) +#define CMU_I2SCKSEL_I2S4CKSEL_POS (12U) +#define CMU_I2SCKSEL_I2S4CKSEL (0xF000U) + +/* Bit definition for CMU_SCFGR register */ +#define CMU_SCFGR_PCLK0S_POS (0U) +#define CMU_SCFGR_PCLK0S (0x00000007UL) +#define CMU_SCFGR_PCLK1S_POS (4U) +#define CMU_SCFGR_PCLK1S (0x00000070UL) +#define CMU_SCFGR_PCLK2S_POS (8U) +#define CMU_SCFGR_PCLK2S (0x00000700UL) +#define CMU_SCFGR_PCLK3S_POS (12U) +#define CMU_SCFGR_PCLK3S (0x00007000UL) +#define CMU_SCFGR_PCLK4S_POS (16U) +#define CMU_SCFGR_PCLK4S (0x00070000UL) +#define CMU_SCFGR_EXCKS_POS (20U) +#define CMU_SCFGR_EXCKS (0x00700000UL) +#define CMU_SCFGR_HCLKS_POS (24U) +#define CMU_SCFGR_HCLKS (0x07000000UL) + +/* Bit definition for CMU_USBCKCFGR register */ +#define CMU_USBCKCFGR_USBCKS_POS (4U) +#define CMU_USBCKCFGR_USBCKS (0xF0U) + +/* Bit definition for CMU_CKSWR register */ +#define CMU_CKSWR_CKSW (0x07U) + +/* Bit definition for CMU_PLLCR register */ +#define CMU_PLLCR_MPLLOFF (0x01U) + +/* Bit definition for CMU_UPLLCR register */ +#define CMU_UPLLCR_UPLLOFF (0x01U) + +/* Bit definition for CMU_XTALCR register */ +#define CMU_XTALCR_XTALSTP (0x01U) + +/* Bit definition for CMU_HRCCR register */ +#define CMU_HRCCR_HRCSTP (0x01U) + +/* Bit definition for CMU_MRCCR register */ +#define CMU_MRCCR_MRCSTP (0x01U) + +/* Bit definition for CMU_OSCSTBSR register */ +#define CMU_OSCSTBSR_HRCSTBF_POS (0U) +#define CMU_OSCSTBSR_HRCSTBF (0x01U) +#define CMU_OSCSTBSR_XTALSTBF_POS (3U) +#define CMU_OSCSTBSR_XTALSTBF (0x08U) +#define CMU_OSCSTBSR_MPLLSTBF_POS (5U) +#define CMU_OSCSTBSR_MPLLSTBF (0x20U) +#define CMU_OSCSTBSR_UPLLSTBF_POS (6U) +#define CMU_OSCSTBSR_UPLLSTBF (0x40U) + +/* Bit definition for CMU_MCOCFGR register */ +#define CMU_MCOCFGR_MCOSEL_POS (0U) +#define CMU_MCOCFGR_MCOSEL (0x0FU) +#define CMU_MCOCFGR_MCODIV_POS (4U) +#define CMU_MCOCFGR_MCODIV (0x70U) +#define CMU_MCOCFGR_MCOEN_POS (7U) +#define CMU_MCOCFGR_MCOEN (0x80U) + +/* Bit definition for CMU_TPIUCKCFGR register */ +#define CMU_TPIUCKCFGR_TPIUCKS_POS (0U) +#define CMU_TPIUCKCFGR_TPIUCKS (0x03U) +#define CMU_TPIUCKCFGR_TPIUCKS_0 (0x01U) +#define CMU_TPIUCKCFGR_TPIUCKS_1 (0x02U) +#define CMU_TPIUCKCFGR_TPIUCKOE_POS (7U) +#define CMU_TPIUCKCFGR_TPIUCKOE (0x80U) + +/* Bit definition for CMU_XTALSTDCR register */ +#define CMU_XTALSTDCR_XTALSTDIE_POS (0U) +#define CMU_XTALSTDCR_XTALSTDIE (0x01U) +#define CMU_XTALSTDCR_XTALSTDRE_POS (1U) +#define CMU_XTALSTDCR_XTALSTDRE (0x02U) +#define CMU_XTALSTDCR_XTALSTDRIS_POS (2U) +#define CMU_XTALSTDCR_XTALSTDRIS (0x04U) +#define CMU_XTALSTDCR_XTALSTDE_POS (7U) +#define CMU_XTALSTDCR_XTALSTDE (0x80U) + +/* Bit definition for CMU_XTALSTDSR register */ +#define CMU_XTALSTDSR_XTALSTDF (0x01U) + +/* Bit definition for CMU_MRCTRM register */ +#define CMU_MRCTRM (0xFFU) + +/* Bit definition for CMU_HRCTRM register */ +#define CMU_HRCTRM (0xFFU) + +/* Bit definition for CMU_XTALSTBCR register */ +#define CMU_XTALSTBCR_XTALSTB (0x0FU) +#define CMU_XTALSTBCR_XTALSTB_0 (0x01U) +#define CMU_XTALSTBCR_XTALSTB_1 (0x02U) +#define CMU_XTALSTBCR_XTALSTB_2 (0x04U) +#define CMU_XTALSTBCR_XTALSTB_3 (0x08U) + +/* Bit definition for CMU_PLLCFGR register */ +#define CMU_PLLCFGR_MPLLM_POS (0U) +#define CMU_PLLCFGR_MPLLM (0x0000001FUL) +#define CMU_PLLCFGR_PLLSRC_POS (7U) +#define CMU_PLLCFGR_PLLSRC (0x00000080UL) +#define CMU_PLLCFGR_MPLLN_POS (8U) +#define CMU_PLLCFGR_MPLLN (0x0001FF00UL) +#define CMU_PLLCFGR_MPLLR_POS (20U) +#define CMU_PLLCFGR_MPLLR (0x00F00000UL) +#define CMU_PLLCFGR_MPLLQ_POS (24U) +#define CMU_PLLCFGR_MPLLQ (0x0F000000UL) +#define CMU_PLLCFGR_MPLLP_POS (28U) +#define CMU_PLLCFGR_MPLLP (0xF0000000UL) + +/* Bit definition for CMU_UPLLCFGR register */ +#define CMU_UPLLCFGR_UPLLM_POS (0U) +#define CMU_UPLLCFGR_UPLLM (0x0000001FUL) +#define CMU_UPLLCFGR_UPLLN_POS (8U) +#define CMU_UPLLCFGR_UPLLN (0x0001FF00UL) +#define CMU_UPLLCFGR_UPLLR_POS (20U) +#define CMU_UPLLCFGR_UPLLR (0x00F00000UL) +#define CMU_UPLLCFGR_UPLLQ_POS (24U) +#define CMU_UPLLCFGR_UPLLQ (0x0F000000UL) +#define CMU_UPLLCFGR_UPLLP_POS (28U) +#define CMU_UPLLCFGR_UPLLP (0xF0000000UL) + +/* Bit definition for CMU_XTALCFGR register */ +#define CMU_XTALCFGR_XTALDRV_POS (4U) +#define CMU_XTALCFGR_XTALDRV (0x30U) +#define CMU_XTALCFGR_XTALDRV_0 (0x10U) +#define CMU_XTALCFGR_XTALDRV_1 (0x20U) +#define CMU_XTALCFGR_XTALMS_POS (6U) +#define CMU_XTALCFGR_XTALMS (0x40U) +#define CMU_XTALCFGR_SUPDRV_POS (7U) +#define CMU_XTALCFGR_SUPDRV (0x80U) + +/* Bit definition for CMU_XTAL32CR register */ +#define CMU_XTAL32CR_XTAL32STP (0x01U) + +/* Bit definition for CMU_XTAL32CFGR register */ +#define CMU_XTAL32CFGR_XTAL32DRV (0x07U) +#define CMU_XTAL32CFGR_XTAL32DRV_0 (0x01U) +#define CMU_XTAL32CFGR_XTAL32DRV_1 (0x02U) +#define CMU_XTAL32CFGR_XTAL32DRV_2 (0x04U) + +/* Bit definition for CMU_XTAL32NFR register */ +#define CMU_XTAL32NFR_XTAL32NF (0x03U) +#define CMU_XTAL32NFR_XTAL32NF_0 (0x01U) +#define CMU_XTAL32NFR_XTAL32NF_1 (0x02U) + +/* Bit definition for CMU_LRCCR register */ +#define CMU_LRCCR_LRCSTP (0x01U) + +/* Bit definition for CMU_LRCTRM register */ +#define CMU_LRCTRM (0xFFU) + +/******************************************************************************* + Bit definition for Peripheral CRC +*******************************************************************************/ +/* Bit definition for CRC_CR register */ +#define CRC_CR_CR_POS (1U) +#define CRC_CR_CR (0x00000002UL) +#define CRC_CR_REFIN_POS (2U) +#define CRC_CR_REFIN (0x00000004UL) +#define CRC_CR_REFOUT_POS (3U) +#define CRC_CR_REFOUT (0x00000008UL) +#define CRC_CR_XOROUT_POS (4U) +#define CRC_CR_XOROUT (0x00000010UL) + +/* Bit definition for CRC_RESLT register */ +#define CRC_RESLT_CRC_REG_POS (0U) +#define CRC_RESLT_CRC_REG (0x0000FFFFUL) +#define CRC_RESLT_CRCFLAG_16_POS (16U) +#define CRC_RESLT_CRCFLAG_16 (0x00010000UL) + +/* Bit definition for CRC_FLG register */ +#define CRC_FLG_CRCFLAG_32 (0x00000001UL) + +/* Bit definition for CRC_DAT0 register */ +#define CRC_DAT0 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT1 register */ +#define CRC_DAT1 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT2 register */ +#define CRC_DAT2 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT3 register */ +#define CRC_DAT3 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT4 register */ +#define CRC_DAT4 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT5 register */ +#define CRC_DAT5 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT6 register */ +#define CRC_DAT6 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT7 register */ +#define CRC_DAT7 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT8 register */ +#define CRC_DAT8 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT9 register */ +#define CRC_DAT9 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT10 register */ +#define CRC_DAT10 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT11 register */ +#define CRC_DAT11 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT12 register */ +#define CRC_DAT12 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT13 register */ +#define CRC_DAT13 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT14 register */ +#define CRC_DAT14 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT15 register */ +#define CRC_DAT15 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT16 register */ +#define CRC_DAT16 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT17 register */ +#define CRC_DAT17 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT18 register */ +#define CRC_DAT18 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT19 register */ +#define CRC_DAT19 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT20 register */ +#define CRC_DAT20 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT21 register */ +#define CRC_DAT21 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT22 register */ +#define CRC_DAT22 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT23 register */ +#define CRC_DAT23 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT24 register */ +#define CRC_DAT24 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT25 register */ +#define CRC_DAT25 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT26 register */ +#define CRC_DAT26 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT27 register */ +#define CRC_DAT27 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT28 register */ +#define CRC_DAT28 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT29 register */ +#define CRC_DAT29 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT30 register */ +#define CRC_DAT30 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT31 register */ +#define CRC_DAT31 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral DBGC +*******************************************************************************/ +/* Bit definition for DBGC_MCUDBGSTAT register */ +#define DBGC_MCUDBGSTAT_CDBGPWRUPREQ_POS (0U) +#define DBGC_MCUDBGSTAT_CDBGPWRUPREQ (0x00000001UL) +#define DBGC_MCUDBGSTAT_CDBGPWRUPACK_POS (1U) +#define DBGC_MCUDBGSTAT_CDBGPWRUPACK (0x00000002UL) + +/* Bit definition for DBGC_MCUSTPCTL register */ +#define DBGC_MCUSTPCTL_SWDTSTP_POS (0U) +#define DBGC_MCUSTPCTL_SWDTSTP (0x00000001UL) +#define DBGC_MCUSTPCTL_WDTSTP_POS (1U) +#define DBGC_MCUSTPCTL_WDTSTP (0x00000002UL) +#define DBGC_MCUSTPCTL_RTCSTP_POS (2U) +#define DBGC_MCUSTPCTL_RTCSTP (0x00000004UL) +#define DBGC_MCUSTPCTL_TMR01STP_POS (14U) +#define DBGC_MCUSTPCTL_TMR01STP (0x00004000UL) +#define DBGC_MCUSTPCTL_TMR02STP_POS (15U) +#define DBGC_MCUSTPCTL_TMR02STP (0x00008000UL) +#define DBGC_MCUSTPCTL_TMR41STP_POS (20U) +#define DBGC_MCUSTPCTL_TMR41STP (0x00100000UL) +#define DBGC_MCUSTPCTL_TMR42STP_POS (21U) +#define DBGC_MCUSTPCTL_TMR42STP (0x00200000UL) +#define DBGC_MCUSTPCTL_TMR43STP_POS (22U) +#define DBGC_MCUSTPCTL_TMR43STP (0x00400000UL) +#define DBGC_MCUSTPCTL_TM61STP_POS (23U) +#define DBGC_MCUSTPCTL_TM61STP (0x00800000UL) +#define DBGC_MCUSTPCTL_TM62STP_POS (24U) +#define DBGC_MCUSTPCTL_TM62STP (0x01000000UL) +#define DBGC_MCUSTPCTL_TMR63STP_POS (25U) +#define DBGC_MCUSTPCTL_TMR63STP (0x02000000UL) +#define DBGC_MCUSTPCTL_TMRA1STP_POS (26U) +#define DBGC_MCUSTPCTL_TMRA1STP (0x04000000UL) +#define DBGC_MCUSTPCTL_TMRA2STP_POS (27U) +#define DBGC_MCUSTPCTL_TMRA2STP (0x08000000UL) +#define DBGC_MCUSTPCTL_TMRA3STP_POS (28U) +#define DBGC_MCUSTPCTL_TMRA3STP (0x10000000UL) +#define DBGC_MCUSTPCTL_TMRA4STP_POS (29U) +#define DBGC_MCUSTPCTL_TMRA4STP (0x20000000UL) +#define DBGC_MCUSTPCTL_TMRA5STP_POS (30U) +#define DBGC_MCUSTPCTL_TMRA5STP (0x40000000UL) +#define DBGC_MCUSTPCTL_TMRA6STP_POS (31U) +#define DBGC_MCUSTPCTL_TMRA6STP (0x80000000UL) + +/* Bit definition for DBGC_MCUTRACECTL register */ +#define DBGC_MCUTRACECTL_TRACEMODE_POS (0U) +#define DBGC_MCUTRACECTL_TRACEMODE (0x00000003UL) +#define DBGC_MCUTRACECTL_TRACEMODE_0 (0x00000001UL) +#define DBGC_MCUTRACECTL_TRACEMODE_1 (0x00000002UL) +#define DBGC_MCUTRACECTL_TRACEIOEN_POS (2U) +#define DBGC_MCUTRACECTL_TRACEIOEN (0x00000004UL) + +/******************************************************************************* + Bit definition for Peripheral DCU +*******************************************************************************/ +/* Bit definition for DCU_CTL register */ +#define DCU_CTL_MODE_POS (0U) +#define DCU_CTL_MODE (0x00000007UL) +#define DCU_CTL_DATASIZE_POS (3U) +#define DCU_CTL_DATASIZE (0x00000018UL) +#define DCU_CTL_DATASIZE_0 (0x00000008UL) +#define DCU_CTL_DATASIZE_1 (0x00000010UL) +#define DCU_CTL_COMPTRG_POS (8U) +#define DCU_CTL_COMPTRG (0x00000100UL) +#define DCU_CTL_INTEN_POS (31U) +#define DCU_CTL_INTEN (0x80000000UL) + +/* Bit definition for DCU_FLAG register */ +#define DCU_FLAG_FLAG_OP_POS (0U) +#define DCU_FLAG_FLAG_OP (0x00000001UL) +#define DCU_FLAG_FLAG_LS2_POS (1U) +#define DCU_FLAG_FLAG_LS2 (0x00000002UL) +#define DCU_FLAG_FLAG_EQ2_POS (2U) +#define DCU_FLAG_FLAG_EQ2 (0x00000004UL) +#define DCU_FLAG_FLAG_GT2_POS (3U) +#define DCU_FLAG_FLAG_GT2 (0x00000008UL) +#define DCU_FLAG_FLAG_LS1_POS (4U) +#define DCU_FLAG_FLAG_LS1 (0x00000010UL) +#define DCU_FLAG_FLAG_EQ1_POS (5U) +#define DCU_FLAG_FLAG_EQ1 (0x00000020UL) +#define DCU_FLAG_FLAG_GT1_POS (6U) +#define DCU_FLAG_FLAG_GT1 (0x00000040UL) + +/* Bit definition for DCU_DATA0 register */ +#define DCU_DATA0 (0xFFFFFFFFUL) + +/* Bit definition for DCU_DATA1 register */ +#define DCU_DATA1 (0xFFFFFFFFUL) + +/* Bit definition for DCU_DATA2 register */ +#define DCU_DATA2 (0xFFFFFFFFUL) + +/* Bit definition for DCU_FLAGCLR register */ +#define DCU_FLAGCLR_CLR_OP_POS (0U) +#define DCU_FLAGCLR_CLR_OP (0x00000001UL) +#define DCU_FLAGCLR_CLR_LS2_POS (1U) +#define DCU_FLAGCLR_CLR_LS2 (0x00000002UL) +#define DCU_FLAGCLR_CLR_EQ2_POS (2U) +#define DCU_FLAGCLR_CLR_EQ2 (0x00000004UL) +#define DCU_FLAGCLR_CLR_GT2_POS (3U) +#define DCU_FLAGCLR_CLR_GT2 (0x00000008UL) +#define DCU_FLAGCLR_CLR_LS1_POS (4U) +#define DCU_FLAGCLR_CLR_LS1 (0x00000010UL) +#define DCU_FLAGCLR_CLR_EQ1_POS (5U) +#define DCU_FLAGCLR_CLR_EQ1 (0x00000020UL) +#define DCU_FLAGCLR_CLR_GT1_POS (6U) +#define DCU_FLAGCLR_CLR_GT1 (0x00000040UL) + +/* Bit definition for DCU_INTEVTSEL register */ +#define DCU_INTEVTSEL_SEL_OP_POS (0U) +#define DCU_INTEVTSEL_SEL_OP (0x00000001UL) +#define DCU_INTEVTSEL_SEL_LS2_POS (1U) +#define DCU_INTEVTSEL_SEL_LS2 (0x00000002UL) +#define DCU_INTEVTSEL_SEL_EQ2_POS (2U) +#define DCU_INTEVTSEL_SEL_EQ2 (0x00000004UL) +#define DCU_INTEVTSEL_SEL_GT2_POS (3U) +#define DCU_INTEVTSEL_SEL_GT2 (0x00000008UL) +#define DCU_INTEVTSEL_SEL_LS1_POS (4U) +#define DCU_INTEVTSEL_SEL_LS1 (0x00000010UL) +#define DCU_INTEVTSEL_SEL_EQ1_POS (5U) +#define DCU_INTEVTSEL_SEL_EQ1 (0x00000020UL) +#define DCU_INTEVTSEL_SEL_GT1_POS (6U) +#define DCU_INTEVTSEL_SEL_GT1 (0x00000040UL) +#define DCU_INTEVTSEL_SEL_WIN_POS (7U) +#define DCU_INTEVTSEL_SEL_WIN (0x00000180UL) +#define DCU_INTEVTSEL_SEL_WIN_0 (0x00000080UL) +#define DCU_INTEVTSEL_SEL_WIN_1 (0x00000100UL) + +/******************************************************************************* + Bit definition for Peripheral DMA +*******************************************************************************/ +/* Bit definition for DMA_EN register */ +#define DMA_EN_EN (0x00000001UL) + +/* Bit definition for DMA_INTSTAT0 register */ +#define DMA_INTSTAT0_TRNERR_POS (0U) +#define DMA_INTSTAT0_TRNERR (0x0000000FUL) +#define DMA_INTSTAT0_TRNERR_0 (0x00000001UL) +#define DMA_INTSTAT0_TRNERR_1 (0x00000002UL) +#define DMA_INTSTAT0_TRNERR_2 (0x00000004UL) +#define DMA_INTSTAT0_TRNERR_3 (0x00000008UL) +#define DMA_INTSTAT0_REQERR_POS (16U) +#define DMA_INTSTAT0_REQERR (0x000F0000UL) +#define DMA_INTSTAT0_REQERR_0 (0x00010000UL) +#define DMA_INTSTAT0_REQERR_1 (0x00020000UL) +#define DMA_INTSTAT0_REQERR_2 (0x00040000UL) +#define DMA_INTSTAT0_REQERR_3 (0x00080000UL) + +/* Bit definition for DMA_INTSTAT1 register */ +#define DMA_INTSTAT1_TC_POS (0U) +#define DMA_INTSTAT1_TC (0x0000000FUL) +#define DMA_INTSTAT1_TC_0 (0x00000001UL) +#define DMA_INTSTAT1_TC_1 (0x00000002UL) +#define DMA_INTSTAT1_TC_2 (0x00000004UL) +#define DMA_INTSTAT1_TC_3 (0x00000008UL) +#define DMA_INTSTAT1_BTC_POS (16U) +#define DMA_INTSTAT1_BTC (0x000F0000UL) +#define DMA_INTSTAT1_BTC_0 (0x00010000UL) +#define DMA_INTSTAT1_BTC_1 (0x00020000UL) +#define DMA_INTSTAT1_BTC_2 (0x00040000UL) +#define DMA_INTSTAT1_BTC_3 (0x00080000UL) + +/* Bit definition for DMA_INTMASK0 register */ +#define DMA_INTMASK0_MSKTRNERR_POS (0U) +#define DMA_INTMASK0_MSKTRNERR (0x0000000FUL) +#define DMA_INTMASK0_MSKTRNERR_0 (0x00000001UL) +#define DMA_INTMASK0_MSKTRNERR_1 (0x00000002UL) +#define DMA_INTMASK0_MSKTRNERR_2 (0x00000004UL) +#define DMA_INTMASK0_MSKTRNERR_3 (0x00000008UL) +#define DMA_INTMASK0_MSKREQERR_POS (16U) +#define DMA_INTMASK0_MSKREQERR (0x000F0000UL) +#define DMA_INTMASK0_MSKREQERR_0 (0x00010000UL) +#define DMA_INTMASK0_MSKREQERR_1 (0x00020000UL) +#define DMA_INTMASK0_MSKREQERR_2 (0x00040000UL) +#define DMA_INTMASK0_MSKREQERR_3 (0x00080000UL) + +/* Bit definition for DMA_INTMASK1 register */ +#define DMA_INTMASK1_MSKTC_POS (0U) +#define DMA_INTMASK1_MSKTC (0x0000000FUL) +#define DMA_INTMASK1_MSKTC_0 (0x00000001UL) +#define DMA_INTMASK1_MSKTC_1 (0x00000002UL) +#define DMA_INTMASK1_MSKTC_2 (0x00000004UL) +#define DMA_INTMASK1_MSKTC_3 (0x00000008UL) +#define DMA_INTMASK1_MSKBTC_POS (16U) +#define DMA_INTMASK1_MSKBTC (0x000F0000UL) +#define DMA_INTMASK1_MSKBTC_0 (0x00010000UL) +#define DMA_INTMASK1_MSKBTC_1 (0x00020000UL) +#define DMA_INTMASK1_MSKBTC_2 (0x00040000UL) +#define DMA_INTMASK1_MSKBTC_3 (0x00080000UL) + +/* Bit definition for DMA_INTCLR0 register */ +#define DMA_INTCLR0_CLRTRNERR_POS (0U) +#define DMA_INTCLR0_CLRTRNERR (0x0000000FUL) +#define DMA_INTCLR0_CLRTRNERR_0 (0x00000001UL) +#define DMA_INTCLR0_CLRTRNERR_1 (0x00000002UL) +#define DMA_INTCLR0_CLRTRNERR_2 (0x00000004UL) +#define DMA_INTCLR0_CLRTRNERR_3 (0x00000008UL) +#define DMA_INTCLR0_CLRREQERR_POS (16U) +#define DMA_INTCLR0_CLRREQERR (0x000F0000UL) +#define DMA_INTCLR0_CLRREQERR_0 (0x00010000UL) +#define DMA_INTCLR0_CLRREQERR_1 (0x00020000UL) +#define DMA_INTCLR0_CLRREQERR_2 (0x00040000UL) +#define DMA_INTCLR0_CLRREQERR_3 (0x00080000UL) + +/* Bit definition for DMA_INTCLR1 register */ +#define DMA_INTCLR1_CLRTC_POS (0U) +#define DMA_INTCLR1_CLRTC (0x0000000FUL) +#define DMA_INTCLR1_CLRTC_0 (0x00000001UL) +#define DMA_INTCLR1_CLRTC_1 (0x00000002UL) +#define DMA_INTCLR1_CLRTC_2 (0x00000004UL) +#define DMA_INTCLR1_CLRTC_3 (0x00000008UL) +#define DMA_INTCLR1_CLRBTC_POS (16U) +#define DMA_INTCLR1_CLRBTC (0x000F0000UL) +#define DMA_INTCLR1_CLRBTC_0 (0x00010000UL) +#define DMA_INTCLR1_CLRBTC_1 (0x00020000UL) +#define DMA_INTCLR1_CLRBTC_2 (0x00040000UL) +#define DMA_INTCLR1_CLRBTC_3 (0x00080000UL) + +/* Bit definition for DMA_CHEN register */ +#define DMA_CHEN_CHEN (0x0000000FUL) +#define DMA_CHEN_CHEN_0 (0x00000001UL) +#define DMA_CHEN_CHEN_1 (0x00000002UL) +#define DMA_CHEN_CHEN_2 (0x00000004UL) +#define DMA_CHEN_CHEN_3 (0x00000008UL) + +/* Bit definition for DMA_REQSTAT register */ +#define DMA_REQSTAT_CHREQ_POS (0U) +#define DMA_REQSTAT_CHREQ (0x0000000FUL) +#define DMA_REQSTAT_CHREQ_0 (0x00000001UL) +#define DMA_REQSTAT_CHREQ_1 (0x00000002UL) +#define DMA_REQSTAT_CHREQ_2 (0x00000004UL) +#define DMA_REQSTAT_CHREQ_3 (0x00000008UL) +#define DMA_REQSTAT_RCFGREQ_POS (15U) +#define DMA_REQSTAT_RCFGREQ (0x00008000UL) + +/* Bit definition for DMA_CHSTAT register */ +#define DMA_CHSTAT_DMAACT_POS (0U) +#define DMA_CHSTAT_DMAACT (0x00000001UL) +#define DMA_CHSTAT_RCFGACT_POS (1U) +#define DMA_CHSTAT_RCFGACT (0x00000002UL) +#define DMA_CHSTAT_CHACT_POS (16U) +#define DMA_CHSTAT_CHACT (0x000F0000UL) +#define DMA_CHSTAT_CHACT_0 (0x00010000UL) +#define DMA_CHSTAT_CHACT_1 (0x00020000UL) +#define DMA_CHSTAT_CHACT_2 (0x00040000UL) +#define DMA_CHSTAT_CHACT_3 (0x00080000UL) + +/* Bit definition for DMA_RCFGCTL register */ +#define DMA_RCFGCTL_RCFGEN_POS (0U) +#define DMA_RCFGCTL_RCFGEN (0x00000001UL) +#define DMA_RCFGCTL_RCFGLLP_POS (1U) +#define DMA_RCFGCTL_RCFGLLP (0x00000002UL) +#define DMA_RCFGCTL_RCFGCHS_POS (8U) +#define DMA_RCFGCTL_RCFGCHS (0x00000F00UL) +#define DMA_RCFGCTL_RCFGCHS_0 (0x00000100UL) +#define DMA_RCFGCTL_RCFGCHS_1 (0x00000200UL) +#define DMA_RCFGCTL_RCFGCHS_2 (0x00000400UL) +#define DMA_RCFGCTL_RCFGCHS_3 (0x00000800UL) +#define DMA_RCFGCTL_SARMD_POS (16U) +#define DMA_RCFGCTL_SARMD (0x00030000UL) +#define DMA_RCFGCTL_SARMD_0 (0x00010000UL) +#define DMA_RCFGCTL_SARMD_1 (0x00020000UL) +#define DMA_RCFGCTL_DARMD_POS (18U) +#define DMA_RCFGCTL_DARMD (0x000C0000UL) +#define DMA_RCFGCTL_DARMD_0 (0x00040000UL) +#define DMA_RCFGCTL_DARMD_1 (0x00080000UL) +#define DMA_RCFGCTL_CNTMD_POS (20U) +#define DMA_RCFGCTL_CNTMD (0x00300000UL) +#define DMA_RCFGCTL_CNTMD_0 (0x00100000UL) +#define DMA_RCFGCTL_CNTMD_1 (0x00200000UL) + +/* Bit definition for DMA_SWREQ register */ +#define DMA_SWREQ_SWREQ_POS (0U) +#define DMA_SWREQ_SWREQ (0x000000FFUL) +#define DMA_SWREQ_SWREQ_0 (0x00000001UL) +#define DMA_SWREQ_SWREQ_1 (0x00000002UL) +#define DMA_SWREQ_SWREQ_2 (0x00000004UL) +#define DMA_SWREQ_SWREQ_3 (0x00000008UL) +#define DMA_SWREQ_SWREQ_4 (0x00000010UL) +#define DMA_SWREQ_SWREQ_5 (0x00000020UL) +#define DMA_SWREQ_SWREQ_6 (0x00000040UL) +#define DMA_SWREQ_SWREQ_7 (0x00000080UL) +#define DMA_SWREQ_SWRCFGREQ_POS (15U) +#define DMA_SWREQ_SWRCFGREQ (0x00008000UL) +#define DMA_SWREQ_SWREQWP_POS (16U) +#define DMA_SWREQ_SWREQWP (0x00FF0000UL) +#define DMA_SWREQ_SWRCFGWP_POS (24U) +#define DMA_SWREQ_SWRCFGWP (0xFF000000UL) + +/* Bit definition for DMA_SAR register */ +#define DMA_SAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_DAR register */ +#define DMA_DAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_DTCTL register */ +#define DMA_DTCTL_BLKSIZE_POS (0U) +#define DMA_DTCTL_BLKSIZE (0x000003FFUL) +#define DMA_DTCTL_CNT_POS (16U) +#define DMA_DTCTL_CNT (0xFFFF0000UL) + +/* Bit definition for DMA_RPT register */ +#define DMA_RPT_SRPT_POS (0U) +#define DMA_RPT_SRPT (0x000003FFUL) +#define DMA_RPT_DRPT_POS (16U) +#define DMA_RPT_DRPT (0x03FF0000UL) + +/* Bit definition for DMA_RPTB register */ +#define DMA_RPTB_SRPTB_POS (0U) +#define DMA_RPTB_SRPTB (0x000003FFUL) +#define DMA_RPTB_DRPTB_POS (16U) +#define DMA_RPTB_DRPTB (0x03FF0000UL) + +/* Bit definition for DMA_SNSEQCTL register */ +#define DMA_SNSEQCTL_SOFFSET_POS (0U) +#define DMA_SNSEQCTL_SOFFSET (0x000FFFFFUL) +#define DMA_SNSEQCTL_SNSCNT_POS (20U) +#define DMA_SNSEQCTL_SNSCNT (0xFFF00000UL) + +/* Bit definition for DMA_SNSEQCTLB register */ +#define DMA_SNSEQCTLB_SNSDIST_POS (0U) +#define DMA_SNSEQCTLB_SNSDIST (0x000FFFFFUL) +#define DMA_SNSEQCTLB_SNSCNTB_POS (20U) +#define DMA_SNSEQCTLB_SNSCNTB (0xFFF00000UL) + +/* Bit definition for DMA_DNSEQCTL register */ +#define DMA_DNSEQCTL_DOFFSET_POS (0U) +#define DMA_DNSEQCTL_DOFFSET (0x000FFFFFUL) +#define DMA_DNSEQCTL_DNSCNT_POS (20U) +#define DMA_DNSEQCTL_DNSCNT (0xFFF00000UL) + +/* Bit definition for DMA_DNSEQCTLB register */ +#define DMA_DNSEQCTLB_DNSDIST_POS (0U) +#define DMA_DNSEQCTLB_DNSDIST (0x000FFFFFUL) +#define DMA_DNSEQCTLB_DNSCNTB_POS (20U) +#define DMA_DNSEQCTLB_DNSCNTB (0xFFF00000UL) + +/* Bit definition for DMA_LLP register */ +#define DMA_LLP_LLP_POS (2U) +#define DMA_LLP_LLP (0xFFFFFFFCUL) + +/* Bit definition for DMA_CHCTL register */ +#define DMA_CHCTL_SINC_POS (0U) +#define DMA_CHCTL_SINC (0x00000003UL) +#define DMA_CHCTL_SINC_0 (0x00000001UL) +#define DMA_CHCTL_SINC_1 (0x00000002UL) +#define DMA_CHCTL_DINC_POS (2U) +#define DMA_CHCTL_DINC (0x0000000CUL) +#define DMA_CHCTL_DINC_0 (0x00000004UL) +#define DMA_CHCTL_DINC_1 (0x00000008UL) +#define DMA_CHCTL_SRPTEN_POS (4U) +#define DMA_CHCTL_SRPTEN (0x00000010UL) +#define DMA_CHCTL_DRPTEN_POS (5U) +#define DMA_CHCTL_DRPTEN (0x00000020UL) +#define DMA_CHCTL_SNSEQEN_POS (6U) +#define DMA_CHCTL_SNSEQEN (0x00000040UL) +#define DMA_CHCTL_DNSEQEN_POS (7U) +#define DMA_CHCTL_DNSEQEN (0x00000080UL) +#define DMA_CHCTL_HSIZE_POS (8U) +#define DMA_CHCTL_HSIZE (0x00000300UL) +#define DMA_CHCTL_HSIZE_0 (0x00000100UL) +#define DMA_CHCTL_HSIZE_1 (0x00000200UL) +#define DMA_CHCTL_LLPEN_POS (10U) +#define DMA_CHCTL_LLPEN (0x00000400UL) +#define DMA_CHCTL_LLPRUN_POS (11U) +#define DMA_CHCTL_LLPRUN (0x00000800UL) +#define DMA_CHCTL_IE_POS (12U) +#define DMA_CHCTL_IE (0x00001000UL) + +/* Bit definition for DMA_MONSAR register */ +#define DMA_MONSAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_MONDAR register */ +#define DMA_MONDAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_MONDTCTL register */ +#define DMA_MONDTCTL_BLKSIZE_POS (0U) +#define DMA_MONDTCTL_BLKSIZE (0x000003FFUL) +#define DMA_MONDTCTL_CNT_POS (16U) +#define DMA_MONDTCTL_CNT (0xFFFF0000UL) + +/* Bit definition for DMA_MONRPT register */ +#define DMA_MONRPT_SRPT_POS (0U) +#define DMA_MONRPT_SRPT (0x000003FFUL) +#define DMA_MONRPT_DRPT_POS (16U) +#define DMA_MONRPT_DRPT (0x03FF0000UL) + +/* Bit definition for DMA_MONSNSEQCTL register */ +#define DMA_MONSNSEQCTL_SOFFSET_POS (0U) +#define DMA_MONSNSEQCTL_SOFFSET (0x000FFFFFUL) +#define DMA_MONSNSEQCTL_SNSCNT_POS (20U) +#define DMA_MONSNSEQCTL_SNSCNT (0xFFF00000UL) + +/* Bit definition for DMA_MONDNSEQCTL register */ +#define DMA_MONDNSEQCTL_DOFFSET_POS (0U) +#define DMA_MONDNSEQCTL_DOFFSET (0x000FFFFFUL) +#define DMA_MONDNSEQCTL_DNSCNT_POS (20U) +#define DMA_MONDNSEQCTL_DNSCNT (0xFFF00000UL) + +/******************************************************************************* + Bit definition for Peripheral EFM +*******************************************************************************/ +/* Bit definition for EFM_FAPRT register */ +#define EFM_FAPRT_FAPRT (0x0000FFFFUL) + +/* Bit definition for EFM_FSTP register */ +#define EFM_FSTP_FSTP (0x00000001UL) + +/* Bit definition for EFM_FRMC register */ +#define EFM_FRMC_SLPMD_POS (0U) +#define EFM_FRMC_SLPMD (0x00000001UL) +#define EFM_FRMC_FLWT_POS (4U) +#define EFM_FRMC_FLWT (0x000000F0UL) +#define EFM_FRMC_LVM_POS (8U) +#define EFM_FRMC_LVM (0x00000100UL) +#define EFM_FRMC_CACHE_POS (16U) +#define EFM_FRMC_CACHE (0x00010000UL) +#define EFM_FRMC_CRST_POS (24U) +#define EFM_FRMC_CRST (0x01000000UL) + +/* Bit definition for EFM_FWMC register */ +#define EFM_FWMC_PEMODE_POS (0U) +#define EFM_FWMC_PEMODE (0x00000001UL) +#define EFM_FWMC_PEMOD_POS (4U) +#define EFM_FWMC_PEMOD (0x00000070UL) +#define EFM_FWMC_BUSHLDCTL_POS (8U) +#define EFM_FWMC_BUSHLDCTL (0x00000100UL) + +/* Bit definition for EFM_FSR register */ +#define EFM_FSR_PEWERR_POS (0U) +#define EFM_FSR_PEWERR (0x00000001UL) +#define EFM_FSR_PEPRTERR_POS (1U) +#define EFM_FSR_PEPRTERR (0x00000002UL) +#define EFM_FSR_PGSZERR_POS (2U) +#define EFM_FSR_PGSZERR (0x00000004UL) +#define EFM_FSR_PGMISMTCH_POS (3U) +#define EFM_FSR_PGMISMTCH (0x00000008UL) +#define EFM_FSR_OPTEND_POS (4U) +#define EFM_FSR_OPTEND (0x00000010UL) +#define EFM_FSR_COLERR_POS (5U) +#define EFM_FSR_COLERR (0x00000020UL) +#define EFM_FSR_RDY_POS (8U) +#define EFM_FSR_RDY (0x00000100UL) + +/* Bit definition for EFM_FSCLR register */ +#define EFM_FSCLR_PEWERRCLR_POS (0U) +#define EFM_FSCLR_PEWERRCLR (0x00000001UL) +#define EFM_FSCLR_PEPRTERRCLR_POS (1U) +#define EFM_FSCLR_PEPRTERRCLR (0x00000002UL) +#define EFM_FSCLR_PGSZERRCLR_POS (2U) +#define EFM_FSCLR_PGSZERRCLR (0x00000004UL) +#define EFM_FSCLR_PGMISMTCHCLR_POS (3U) +#define EFM_FSCLR_PGMISMTCHCLR (0x00000008UL) +#define EFM_FSCLR_OPTENDCLR_POS (4U) +#define EFM_FSCLR_OPTENDCLR (0x00000010UL) +#define EFM_FSCLR_COLERRCLR_POS (5U) +#define EFM_FSCLR_COLERRCLR (0x00000020UL) + +/* Bit definition for EFM_FITE register */ +#define EFM_FITE_PEERRITE_POS (0U) +#define EFM_FITE_PEERRITE (0x00000001UL) +#define EFM_FITE_OPTENDITE_POS (1U) +#define EFM_FITE_OPTENDITE (0x00000002UL) +#define EFM_FITE_COLERRITE_POS (2U) +#define EFM_FITE_COLERRITE (0x00000004UL) + +/* Bit definition for EFM_FSWP register */ +#define EFM_FSWP_FSWP (0x00000001UL) + +/* Bit definition for EFM_FPMTSW register */ +#define EFM_FPMTSW_FPMTSW (0x0007FFFFUL) + +/* Bit definition for EFM_FPMTEW register */ +#define EFM_FPMTEW_FPMTEW (0x0007FFFFUL) + +/* Bit definition for EFM_UQID0 register */ +#define EFM_UQID0 (0xFFFFFFFFUL) + +/* Bit definition for EFM_UQID1 register */ +#define EFM_UQID1 (0xFFFFFFFFUL) + +/* Bit definition for EFM_UQID2 register */ +#define EFM_UQID2 (0xFFFFFFFFUL) + +/* Bit definition for EFM_MMF_REMPRT register */ +#define EFM_MMF_REMPRT_REMPRT (0x0000FFFFUL) + +/* Bit definition for EFM_MMF_REMCR register */ +#define EFM_MMF_REMCR_RMSIZE_POS (0U) +#define EFM_MMF_REMCR_RMSIZE (0x0000001FUL) +#define EFM_MMF_REMCR_RMTADDR_POS (12U) +#define EFM_MMF_REMCR_RMTADDR (0x1FFFF000UL) +#define EFM_MMF_REMCR_EN_POS (31U) +#define EFM_MMF_REMCR_EN (0x80000000UL) + +/******************************************************************************* + Bit definition for Peripheral EMB +*******************************************************************************/ +/* Bit definition for EMB_CTL register */ +#define EMB_CTL_PORTINEN_POS (0U) +#define EMB_CTL_PORTINEN (0x00000001UL) +#define EMB_CTL_CMPEN1_POS (1U) +#define EMB_CTL_CMPEN1 (0x00000002UL) +#define EMB_CTL_CMPEN2_POS (2U) +#define EMB_CTL_CMPEN2 (0x00000004UL) +#define EMB_CTL_CMPEN3_POS (3U) +#define EMB_CTL_CMPEN3 (0x00000008UL) +#define EMB_CTL_OSCSTPEN_POS (5U) +#define EMB_CTL_OSCSTPEN (0x00000020UL) +#define EMB_CTL_PWMSEN0_POS (6U) +#define EMB_CTL_PWMSEN0 (0x00000040UL) +#define EMB_CTL_PWMSEN1_POS (7U) +#define EMB_CTL_PWMSEN1 (0x00000080UL) +#define EMB_CTL_PWMSEN2_POS (8U) +#define EMB_CTL_PWMSEN2 (0x00000100UL) +#define EMB_CTL_NFSEL_POS (28U) +#define EMB_CTL_NFSEL (0x30000000UL) +#define EMB_CTL_NFEN_POS (30U) +#define EMB_CTL_NFEN (0x40000000UL) +#define EMB_CTL_INVSEL_POS (31U) +#define EMB_CTL_INVSEL (0x80000000UL) + +/* Bit definition for EMB_PWMLV register */ +#define EMB_PWMLV_PWMLV0_POS (0U) +#define EMB_PWMLV_PWMLV0 (0x00000001UL) +#define EMB_PWMLV_PWMLV1_POS (1U) +#define EMB_PWMLV_PWMLV1 (0x00000002UL) +#define EMB_PWMLV_PWMLV2_POS (2U) +#define EMB_PWMLV_PWMLV2 (0x00000004UL) + +/* Bit definition for EMB_SOE register */ +#define EMB_SOE_SOE (0x00000001UL) + +/* Bit definition for EMB_STAT register */ +#define EMB_STAT_PORTINF_POS (0U) +#define EMB_STAT_PORTINF (0x00000001UL) +#define EMB_STAT_PWMSF_POS (1U) +#define EMB_STAT_PWMSF (0x00000002UL) +#define EMB_STAT_CMPF_POS (2U) +#define EMB_STAT_CMPF (0x00000004UL) +#define EMB_STAT_OSF_POS (3U) +#define EMB_STAT_OSF (0x00000008UL) +#define EMB_STAT_PORTINST_POS (4U) +#define EMB_STAT_PORTINST (0x00000010UL) +#define EMB_STAT_PWMST_POS (5U) +#define EMB_STAT_PWMST (0x00000020UL) + +/* Bit definition for EMB_STATCLR register */ +#define EMB_STATCLR_PORTINFCLR_POS (0U) +#define EMB_STATCLR_PORTINFCLR (0x00000001UL) +#define EMB_STATCLR_PWMSFCLR_POS (1U) +#define EMB_STATCLR_PWMSFCLR (0x00000002UL) +#define EMB_STATCLR_CMPFCLR_POS (2U) +#define EMB_STATCLR_CMPFCLR (0x00000004UL) +#define EMB_STATCLR_OSFCLR_POS (3U) +#define EMB_STATCLR_OSFCLR (0x00000008UL) + +/* Bit definition for EMB_INTEN register */ +#define EMB_INTEN_PORTININTEN_POS (0U) +#define EMB_INTEN_PORTININTEN (0x00000001UL) +#define EMB_INTEN_PWMSINTEN_POS (1U) +#define EMB_INTEN_PWMSINTEN (0x00000002UL) +#define EMB_INTEN_CMPINTEN_POS (2U) +#define EMB_INTEN_CMPINTEN (0x00000004UL) +#define EMB_INTEN_OSINTEN_POS (3U) +#define EMB_INTEN_OSINTEN (0x00000008UL) + +/******************************************************************************* + Bit definition for Peripheral FCM +*******************************************************************************/ +/* Bit definition for FCM_LVR register */ +#define FCM_LVR_LVR (0x0000FFFFUL) + +/* Bit definition for FCM_UVR register */ +#define FCM_UVR_UVR (0x0000FFFFUL) + +/* Bit definition for FCM_CNTR register */ +#define FCM_CNTR_CNTR (0x0000FFFFUL) + +/* Bit definition for FCM_STR register */ +#define FCM_STR_START (0x00000001UL) + +/* Bit definition for FCM_MCCR register */ +#define FCM_MCCR_MDIVS_POS (0U) +#define FCM_MCCR_MDIVS (0x00000003UL) +#define FCM_MCCR_MDIVS_0 (0x00000001UL) +#define FCM_MCCR_MDIVS_1 (0x00000002UL) +#define FCM_MCCR_MCKS_POS (4U) +#define FCM_MCCR_MCKS (0x000000F0UL) + +/* Bit definition for FCM_RCCR register */ +#define FCM_RCCR_RDIVS_POS (0U) +#define FCM_RCCR_RDIVS (0x00000003UL) +#define FCM_RCCR_RDIVS_0 (0x00000001UL) +#define FCM_RCCR_RDIVS_1 (0x00000002UL) +#define FCM_RCCR_RCKS_POS (3U) +#define FCM_RCCR_RCKS (0x00000078UL) +#define FCM_RCCR_INEXS_POS (7U) +#define FCM_RCCR_INEXS (0x00000080UL) +#define FCM_RCCR_DNFS_POS (8U) +#define FCM_RCCR_DNFS (0x00000300UL) +#define FCM_RCCR_DNFS_0 (0x00000100UL) +#define FCM_RCCR_DNFS_1 (0x00000200UL) +#define FCM_RCCR_EDGES_POS (12U) +#define FCM_RCCR_EDGES (0x00003000UL) +#define FCM_RCCR_EDGES_0 (0x00001000UL) +#define FCM_RCCR_EDGES_1 (0x00002000UL) +#define FCM_RCCR_EXREFE_POS (15U) +#define FCM_RCCR_EXREFE (0x00008000UL) + +/* Bit definition for FCM_RIER register */ +#define FCM_RIER_ERRIE_POS (0U) +#define FCM_RIER_ERRIE (0x00000001UL) +#define FCM_RIER_MENDIE_POS (1U) +#define FCM_RIER_MENDIE (0x00000002UL) +#define FCM_RIER_OVFIE_POS (2U) +#define FCM_RIER_OVFIE (0x00000004UL) +#define FCM_RIER_ERRINTRS_POS (4U) +#define FCM_RIER_ERRINTRS (0x00000010UL) +#define FCM_RIER_ERRE_POS (7U) +#define FCM_RIER_ERRE (0x00000080UL) + +/* Bit definition for FCM_SR register */ +#define FCM_SR_ERRF_POS (0U) +#define FCM_SR_ERRF (0x00000001UL) +#define FCM_SR_MENDF_POS (1U) +#define FCM_SR_MENDF (0x00000002UL) +#define FCM_SR_OVF_POS (2U) +#define FCM_SR_OVF (0x00000004UL) + +/* Bit definition for FCM_CLR register */ +#define FCM_CLR_ERRFCLR_POS (0U) +#define FCM_CLR_ERRFCLR (0x00000001UL) +#define FCM_CLR_MENDFCLR_POS (1U) +#define FCM_CLR_MENDFCLR (0x00000002UL) +#define FCM_CLR_OVFCLR_POS (2U) +#define FCM_CLR_OVFCLR (0x00000004UL) + +/******************************************************************************* + Bit definition for Peripheral GPIO +*******************************************************************************/ +/* Bit definition for GPIO_PIDR register */ +#define GPIO_PIDR_PIN00_POS (0U) +#define GPIO_PIDR_PIN00 (0x0001U) +#define GPIO_PIDR_PIN01_POS (1U) +#define GPIO_PIDR_PIN01 (0x0002U) +#define GPIO_PIDR_PIN02_POS (2U) +#define GPIO_PIDR_PIN02 (0x0004U) +#define GPIO_PIDR_PIN03_POS (3U) +#define GPIO_PIDR_PIN03 (0x0008U) +#define GPIO_PIDR_PIN04_POS (4U) +#define GPIO_PIDR_PIN04 (0x0010U) +#define GPIO_PIDR_PIN05_POS (5U) +#define GPIO_PIDR_PIN05 (0x0020U) +#define GPIO_PIDR_PIN06_POS (6U) +#define GPIO_PIDR_PIN06 (0x0040U) +#define GPIO_PIDR_PIN07_POS (7U) +#define GPIO_PIDR_PIN07 (0x0080U) +#define GPIO_PIDR_PIN08_POS (8U) +#define GPIO_PIDR_PIN08 (0x0100U) +#define GPIO_PIDR_PIN09_POS (9U) +#define GPIO_PIDR_PIN09 (0x0200U) +#define GPIO_PIDR_PIN10_POS (10U) +#define GPIO_PIDR_PIN10 (0x0400U) +#define GPIO_PIDR_PIN11_POS (11U) +#define GPIO_PIDR_PIN11 (0x0800U) +#define GPIO_PIDR_PIN12_POS (12U) +#define GPIO_PIDR_PIN12 (0x1000U) +#define GPIO_PIDR_PIN13_POS (13U) +#define GPIO_PIDR_PIN13 (0x2000U) +#define GPIO_PIDR_PIN14_POS (14U) +#define GPIO_PIDR_PIN14 (0x4000U) +#define GPIO_PIDR_PIN15_POS (15U) +#define GPIO_PIDR_PIN15 (0x8000U) + +/* Bit definition for GPIO_PODR register */ +#define GPIO_PODR_POUT00_POS (0U) +#define GPIO_PODR_POUT00 (0x0001U) +#define GPIO_PODR_POUT01_POS (1U) +#define GPIO_PODR_POUT01 (0x0002U) +#define GPIO_PODR_POUT02_POS (2U) +#define GPIO_PODR_POUT02 (0x0004U) +#define GPIO_PODR_POUT03_POS (3U) +#define GPIO_PODR_POUT03 (0x0008U) +#define GPIO_PODR_POUT04_POS (4U) +#define GPIO_PODR_POUT04 (0x0010U) +#define GPIO_PODR_POUT05_POS (5U) +#define GPIO_PODR_POUT05 (0x0020U) +#define GPIO_PODR_POUT06_POS (6U) +#define GPIO_PODR_POUT06 (0x0040U) +#define GPIO_PODR_POUT07_POS (7U) +#define GPIO_PODR_POUT07 (0x0080U) +#define GPIO_PODR_POUT08_POS (8U) +#define GPIO_PODR_POUT08 (0x0100U) +#define GPIO_PODR_POUT09_POS (9U) +#define GPIO_PODR_POUT09 (0x0200U) +#define GPIO_PODR_POUT10_POS (10U) +#define GPIO_PODR_POUT10 (0x0400U) +#define GPIO_PODR_POUT11_POS (11U) +#define GPIO_PODR_POUT11 (0x0800U) +#define GPIO_PODR_POUT12_POS (12U) +#define GPIO_PODR_POUT12 (0x1000U) +#define GPIO_PODR_POUT13_POS (13U) +#define GPIO_PODR_POUT13 (0x2000U) +#define GPIO_PODR_POUT14_POS (14U) +#define GPIO_PODR_POUT14 (0x4000U) +#define GPIO_PODR_POUT15_POS (15U) +#define GPIO_PODR_POUT15 (0x8000U) + +/* Bit definition for GPIO_POER register */ +#define GPIO_POER_POUTE00_POS (0U) +#define GPIO_POER_POUTE00 (0x0001U) +#define GPIO_POER_POUTE01_POS (1U) +#define GPIO_POER_POUTE01 (0x0002U) +#define GPIO_POER_POUTE02_POS (2U) +#define GPIO_POER_POUTE02 (0x0004U) +#define GPIO_POER_POUTE03_POS (3U) +#define GPIO_POER_POUTE03 (0x0008U) +#define GPIO_POER_POUTE04_POS (4U) +#define GPIO_POER_POUTE04 (0x0010U) +#define GPIO_POER_POUTE05_POS (5U) +#define GPIO_POER_POUTE05 (0x0020U) +#define GPIO_POER_POUTE06_POS (6U) +#define GPIO_POER_POUTE06 (0x0040U) +#define GPIO_POER_POUTE07_POS (7U) +#define GPIO_POER_POUTE07 (0x0080U) +#define GPIO_POER_POUTE08_POS (8U) +#define GPIO_POER_POUTE08 (0x0100U) +#define GPIO_POER_POUTE09_POS (9U) +#define GPIO_POER_POUTE09 (0x0200U) +#define GPIO_POER_POUTE10_POS (10U) +#define GPIO_POER_POUTE10 (0x0400U) +#define GPIO_POER_POUTE11_POS (11U) +#define GPIO_POER_POUTE11 (0x0800U) +#define GPIO_POER_POUTE12_POS (12U) +#define GPIO_POER_POUTE12 (0x1000U) +#define GPIO_POER_POUTE13_POS (13U) +#define GPIO_POER_POUTE13 (0x2000U) +#define GPIO_POER_POUTE14_POS (14U) +#define GPIO_POER_POUTE14 (0x4000U) +#define GPIO_POER_POUTE15_POS (15U) +#define GPIO_POER_POUTE15 (0x8000U) + +/* Bit definition for GPIO_POSR register */ +#define GPIO_POSR_POS00_POS (0U) +#define GPIO_POSR_POS00 (0x0001U) +#define GPIO_POSR_POS01_POS (1U) +#define GPIO_POSR_POS01 (0x0002U) +#define GPIO_POSR_POS02_POS (2U) +#define GPIO_POSR_POS02 (0x0004U) +#define GPIO_POSR_POS03_POS (3U) +#define GPIO_POSR_POS03 (0x0008U) +#define GPIO_POSR_POS04_POS (4U) +#define GPIO_POSR_POS04 (0x0010U) +#define GPIO_POSR_POS05_POS (5U) +#define GPIO_POSR_POS05 (0x0020U) +#define GPIO_POSR_POS06_POS (6U) +#define GPIO_POSR_POS06 (0x0040U) +#define GPIO_POSR_POS07_POS (7U) +#define GPIO_POSR_POS07 (0x0080U) +#define GPIO_POSR_POS08_POS (8U) +#define GPIO_POSR_POS08 (0x0100U) +#define GPIO_POSR_POS09_POS (9U) +#define GPIO_POSR_POS09 (0x0200U) +#define GPIO_POSR_POS10_POS (10U) +#define GPIO_POSR_POS10 (0x0400U) +#define GPIO_POSR_POS11_POS (11U) +#define GPIO_POSR_POS11 (0x0800U) +#define GPIO_POSR_POS12_POS (12U) +#define GPIO_POSR_POS12 (0x1000U) +#define GPIO_POSR_POS13_POS (13U) +#define GPIO_POSR_POS13 (0x2000U) +#define GPIO_POSR_POS14_POS (14U) +#define GPIO_POSR_POS14 (0x4000U) +#define GPIO_POSR_POS15_POS (15U) +#define GPIO_POSR_POS15 (0x8000U) + +/* Bit definition for GPIO_PORR register */ +#define GPIO_PORR_POR00_POS (0U) +#define GPIO_PORR_POR00 (0x0001U) +#define GPIO_PORR_POR01_POS (1U) +#define GPIO_PORR_POR01 (0x0002U) +#define GPIO_PORR_POR02_POS (2U) +#define GPIO_PORR_POR02 (0x0004U) +#define GPIO_PORR_POR03_POS (3U) +#define GPIO_PORR_POR03 (0x0008U) +#define GPIO_PORR_POR04_POS (4U) +#define GPIO_PORR_POR04 (0x0010U) +#define GPIO_PORR_POR05_POS (5U) +#define GPIO_PORR_POR05 (0x0020U) +#define GPIO_PORR_POR06_POS (6U) +#define GPIO_PORR_POR06 (0x0040U) +#define GPIO_PORR_POR07_POS (7U) +#define GPIO_PORR_POR07 (0x0080U) +#define GPIO_PORR_POR08_POS (8U) +#define GPIO_PORR_POR08 (0x0100U) +#define GPIO_PORR_POR09_POS (9U) +#define GPIO_PORR_POR09 (0x0200U) +#define GPIO_PORR_POR10_POS (10U) +#define GPIO_PORR_POR10 (0x0400U) +#define GPIO_PORR_POR11_POS (11U) +#define GPIO_PORR_POR11 (0x0800U) +#define GPIO_PORR_POR12_POS (12U) +#define GPIO_PORR_POR12 (0x1000U) +#define GPIO_PORR_POR13_POS (13U) +#define GPIO_PORR_POR13 (0x2000U) +#define GPIO_PORR_POR14_POS (14U) +#define GPIO_PORR_POR14 (0x4000U) +#define GPIO_PORR_POR15_POS (15U) +#define GPIO_PORR_POR15 (0x8000U) + +/* Bit definition for GPIO_POTR register */ +#define GPIO_POTR_POT00_POS (0U) +#define GPIO_POTR_POT00 (0x0001U) +#define GPIO_POTR_POT01_POS (1U) +#define GPIO_POTR_POT01 (0x0002U) +#define GPIO_POTR_POT02_POS (2U) +#define GPIO_POTR_POT02 (0x0004U) +#define GPIO_POTR_POT03_POS (3U) +#define GPIO_POTR_POT03 (0x0008U) +#define GPIO_POTR_POT04_POS (4U) +#define GPIO_POTR_POT04 (0x0010U) +#define GPIO_POTR_POT05_POS (5U) +#define GPIO_POTR_POT05 (0x0020U) +#define GPIO_POTR_POT06_POS (6U) +#define GPIO_POTR_POT06 (0x0040U) +#define GPIO_POTR_POT07_POS (7U) +#define GPIO_POTR_POT07 (0x0080U) +#define GPIO_POTR_POT08_POS (8U) +#define GPIO_POTR_POT08 (0x0100U) +#define GPIO_POTR_POT09_POS (9U) +#define GPIO_POTR_POT09 (0x0200U) +#define GPIO_POTR_POT10_POS (10U) +#define GPIO_POTR_POT10 (0x0400U) +#define GPIO_POTR_POT11_POS (11U) +#define GPIO_POTR_POT11 (0x0800U) +#define GPIO_POTR_POT12_POS (12U) +#define GPIO_POTR_POT12 (0x1000U) +#define GPIO_POTR_POT13_POS (13U) +#define GPIO_POTR_POT13 (0x2000U) +#define GPIO_POTR_POT14_POS (14U) +#define GPIO_POTR_POT14 (0x4000U) +#define GPIO_POTR_POT15_POS (15U) +#define GPIO_POTR_POT15 (0x8000U) + +/* Bit definition for GPIO_PIDRH register */ +#define GPIO_PIDRH_PIN00_POS (0U) +#define GPIO_PIDRH_PIN00 (0x0001U) +#define GPIO_PIDRH_PIN01_POS (1U) +#define GPIO_PIDRH_PIN01 (0x0002U) +#define GPIO_PIDRH_PIN02_POS (2U) +#define GPIO_PIDRH_PIN02 (0x0004U) + +/* Bit definition for GPIO_PODRH register */ +#define GPIO_PODRH_POUT00_POS (0U) +#define GPIO_PODRH_POUT00 (0x0001U) +#define GPIO_PODRH_POUT01_POS (1U) +#define GPIO_PODRH_POUT01 (0x0002U) +#define GPIO_PODRH_POUT02_POS (2U) +#define GPIO_PODRH_POUT02 (0x0004U) + +/* Bit definition for GPIO_POERH register */ +#define GPIO_POERH_POUTE00_POS (0U) +#define GPIO_POERH_POUTE00 (0x0001U) +#define GPIO_POERH_POUTE01_POS (1U) +#define GPIO_POERH_POUTE01 (0x0002U) +#define GPIO_POERH_POUTE02_POS (2U) +#define GPIO_POERH_POUTE02 (0x0004U) + +/* Bit definition for GPIO_POSRH register */ +#define GPIO_POSRH_POS00_POS (0U) +#define GPIO_POSRH_POS00 (0x0001U) +#define GPIO_POSRH_POS01_POS (1U) +#define GPIO_POSRH_POS01 (0x0002U) +#define GPIO_POSRH_POS02_POS (2U) +#define GPIO_POSRH_POS02 (0x0004U) + +/* Bit definition for GPIO_PORRH register */ +#define GPIO_PORRH_POR00_POS (0U) +#define GPIO_PORRH_POR00 (0x0001U) +#define GPIO_PORRH_POR01_POS (1U) +#define GPIO_PORRH_POR01 (0x0002U) +#define GPIO_PORRH_POR02_POS (2U) +#define GPIO_PORRH_POR02 (0x0004U) + +/* Bit definition for GPIO_POTRH register */ +#define GPIO_POTRH_POT00_POS (0U) +#define GPIO_POTRH_POT00 (0x0001U) +#define GPIO_POTRH_POT01_POS (1U) +#define GPIO_POTRH_POT01 (0x0002U) +#define GPIO_POTRH_POT02_POS (2U) +#define GPIO_POTRH_POT02 (0x0004U) + +/* Bit definition for GPIO_PSPCR register */ +#define GPIO_PSPCR_SPFE (0x001FU) +#define GPIO_PSPCR_SPFE_0 (0x0001U) +#define GPIO_PSPCR_SPFE_1 (0x0002U) +#define GPIO_PSPCR_SPFE_2 (0x0004U) +#define GPIO_PSPCR_SPFE_3 (0x0008U) +#define GPIO_PSPCR_SPFE_4 (0x0010U) + +/* Bit definition for GPIO_PCCR register */ +#define GPIO_PCCR_BFSEL_POS (0U) +#define GPIO_PCCR_BFSEL (0x000FU) +#define GPIO_PCCR_BFSEL_0 (0x0001U) +#define GPIO_PCCR_BFSEL_1 (0x0002U) +#define GPIO_PCCR_BFSEL_2 (0x0004U) +#define GPIO_PCCR_BFSEL_3 (0x0008U) +#define GPIO_PCCR_RDWT_POS (14U) +#define GPIO_PCCR_RDWT (0xC000U) +#define GPIO_PCCR_RDWT_0 (0x4000U) +#define GPIO_PCCR_RDWT_1 (0x8000U) + +/* Bit definition for GPIO_PINAER register */ +#define GPIO_PINAER_PINAE (0x003FU) +#define GPIO_PINAER_PINAE_0 (0x0001U) +#define GPIO_PINAER_PINAE_1 (0x0002U) +#define GPIO_PINAER_PINAE_2 (0x0004U) +#define GPIO_PINAER_PINAE_3 (0x0008U) +#define GPIO_PINAER_PINAE_4 (0x0010U) +#define GPIO_PINAER_PINAE_5 (0x0020U) + +/* Bit definition for GPIO_PWPR register */ +#define GPIO_PWPR_WE_POS (0U) +#define GPIO_PWPR_WE (0x0001U) +#define GPIO_PWPR_WP_POS (8U) +#define GPIO_PWPR_WP (0xFF00U) +#define GPIO_PWPR_WP_0 (0x0100U) +#define GPIO_PWPR_WP_1 (0x0200U) +#define GPIO_PWPR_WP_2 (0x0400U) +#define GPIO_PWPR_WP_3 (0x0800U) +#define GPIO_PWPR_WP_4 (0x1000U) +#define GPIO_PWPR_WP_5 (0x2000U) +#define GPIO_PWPR_WP_6 (0x4000U) +#define GPIO_PWPR_WP_7 (0x8000U) + +/* Bit definition for GPIO_PCR register */ +#define GPIO_PCR_POUT_POS (0U) +#define GPIO_PCR_POUT (0x0001U) +#define GPIO_PCR_POUTE_POS (1U) +#define GPIO_PCR_POUTE (0x0002U) +#define GPIO_PCR_NOD_POS (2U) +#define GPIO_PCR_NOD (0x0004U) +#define GPIO_PCR_DRV_POS (4U) +#define GPIO_PCR_DRV (0x0030U) +#define GPIO_PCR_DRV_0 (0x0010U) +#define GPIO_PCR_DRV_1 (0x0020U) +#define GPIO_PCR_PUU_POS (6U) +#define GPIO_PCR_PUU (0x0040U) +#define GPIO_PCR_PIN_POS (8U) +#define GPIO_PCR_PIN (0x0100U) +#define GPIO_PCR_INVE_POS (9U) +#define GPIO_PCR_INVE (0x0200U) +#define GPIO_PCR_INTE_POS (12U) +#define GPIO_PCR_INTE (0x1000U) +#define GPIO_PCR_LTE_POS (14U) +#define GPIO_PCR_LTE (0x4000U) +#define GPIO_PCR_DDIS_POS (15U) +#define GPIO_PCR_DDIS (0x8000U) + +/* Bit definition for GPIO_PFSR register */ +#define GPIO_PFSR_FSEL_POS (0U) +#define GPIO_PFSR_FSEL (0x003FU) +#define GPIO_PFSR_FSEL_0 (0x0001U) +#define GPIO_PFSR_FSEL_1 (0x0002U) +#define GPIO_PFSR_FSEL_2 (0x0004U) +#define GPIO_PFSR_FSEL_3 (0x0008U) +#define GPIO_PFSR_FSEL_4 (0x0010U) +#define GPIO_PFSR_FSEL_5 (0x0020U) +#define GPIO_PFSR_BFE_POS (8U) +#define GPIO_PFSR_BFE (0x0100U) + +/******************************************************************************* + Bit definition for Peripheral HASH +*******************************************************************************/ +/* Bit definition for HASH_CR register */ +#define HASH_CR_START_POS (0U) +#define HASH_CR_START (0x00000001UL) +#define HASH_CR_FST_GRP_POS (1U) +#define HASH_CR_FST_GRP (0x00000002UL) + +/* Bit definition for HASH_HR7 register */ +#define HASH_HR7 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR6 register */ +#define HASH_HR6 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR5 register */ +#define HASH_HR5 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR4 register */ +#define HASH_HR4 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR3 register */ +#define HASH_HR3 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR2 register */ +#define HASH_HR2 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR1 register */ +#define HASH_HR1 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR0 register */ +#define HASH_HR0 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR15 register */ +#define HASH_DR15 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR14 register */ +#define HASH_DR14 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR13 register */ +#define HASH_DR13 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR12 register */ +#define HASH_DR12 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR11 register */ +#define HASH_DR11 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR10 register */ +#define HASH_DR10 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR9 register */ +#define HASH_DR9 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR8 register */ +#define HASH_DR8 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR7 register */ +#define HASH_DR7 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR6 register */ +#define HASH_DR6 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR5 register */ +#define HASH_DR5 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR4 register */ +#define HASH_DR4 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR3 register */ +#define HASH_DR3 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR2 register */ +#define HASH_DR2 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR1 register */ +#define HASH_DR1 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR0 register */ +#define HASH_DR0 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral I2C +*******************************************************************************/ +/* Bit definition for I2C_CR1 register */ +#define I2C_CR1_PE_POS (0U) +#define I2C_CR1_PE (0x00000001UL) +#define I2C_CR1_SMBUS_POS (1U) +#define I2C_CR1_SMBUS (0x00000002UL) +#define I2C_CR1_SMBALRTEN_POS (2U) +#define I2C_CR1_SMBALRTEN (0x00000004UL) +#define I2C_CR1_SMBDEFAULTEN_POS (3U) +#define I2C_CR1_SMBDEFAULTEN (0x00000008UL) +#define I2C_CR1_SMBHOSTEN_POS (4U) +#define I2C_CR1_SMBHOSTEN (0x00000010UL) +#define I2C_CR1_GCEN_POS (6U) +#define I2C_CR1_GCEN (0x00000040UL) +#define I2C_CR1_RESTART_POS (7U) +#define I2C_CR1_RESTART (0x00000080UL) +#define I2C_CR1_START_POS (8U) +#define I2C_CR1_START (0x00000100UL) +#define I2C_CR1_STOP_POS (9U) +#define I2C_CR1_STOP (0x00000200UL) +#define I2C_CR1_ACK_POS (10U) +#define I2C_CR1_ACK (0x00000400UL) +#define I2C_CR1_SWRST_POS (15U) +#define I2C_CR1_SWRST (0x00008000UL) + +/* Bit definition for I2C_CR2 register */ +#define I2C_CR2_STARTIE_POS (0U) +#define I2C_CR2_STARTIE (0x00000001UL) +#define I2C_CR2_SLADDR0IE_POS (1U) +#define I2C_CR2_SLADDR0IE (0x00000002UL) +#define I2C_CR2_SLADDR1IE_POS (2U) +#define I2C_CR2_SLADDR1IE (0x00000004UL) +#define I2C_CR2_TENDIE_POS (3U) +#define I2C_CR2_TENDIE (0x00000008UL) +#define I2C_CR2_STOPIE_POS (4U) +#define I2C_CR2_STOPIE (0x00000010UL) +#define I2C_CR2_RFULLIE_POS (6U) +#define I2C_CR2_RFULLIE (0x00000040UL) +#define I2C_CR2_TEMPTYIE_POS (7U) +#define I2C_CR2_TEMPTYIE (0x00000080UL) +#define I2C_CR2_ARLOIE_POS (9U) +#define I2C_CR2_ARLOIE (0x00000200UL) +#define I2C_CR2_NACKIE_POS (12U) +#define I2C_CR2_NACKIE (0x00001000UL) +#define I2C_CR2_TMOUTIE_POS (14U) +#define I2C_CR2_TMOUTIE (0x00004000UL) +#define I2C_CR2_GENCALLIE_POS (20U) +#define I2C_CR2_GENCALLIE (0x00100000UL) +#define I2C_CR2_SMBDEFAULTIE_POS (21U) +#define I2C_CR2_SMBDEFAULTIE (0x00200000UL) +#define I2C_CR2_SMBHOSTIE_POS (22U) +#define I2C_CR2_SMBHOSTIE (0x00400000UL) +#define I2C_CR2_SMBALRTIE_POS (23U) +#define I2C_CR2_SMBALRTIE (0x00800000UL) + +/* Bit definition for I2C_CR3 register */ +#define I2C_CR3_TMOUTEN_POS (0U) +#define I2C_CR3_TMOUTEN (0x00000001UL) +#define I2C_CR3_LTMOUT_POS (1U) +#define I2C_CR3_LTMOUT (0x00000002UL) +#define I2C_CR3_HTMOUT_POS (2U) +#define I2C_CR3_HTMOUT (0x00000004UL) +#define I2C_CR3_FACKEN_POS (7U) +#define I2C_CR3_FACKEN (0x00000080UL) + +/* Bit definition for I2C_CR4 register */ +#define I2C_CR4_BUSWAIT_POS (10U) +#define I2C_CR4_BUSWAIT (0x00000400UL) + +/* Bit definition for I2C_SLR0 register */ +#define I2C_SLR0_SLADDR0_POS (0U) +#define I2C_SLR0_SLADDR0 (0x000003FFUL) +#define I2C_SLR0_SLADDR0EN_POS (12U) +#define I2C_SLR0_SLADDR0EN (0x00001000UL) +#define I2C_SLR0_ADDRMOD0_POS (15U) +#define I2C_SLR0_ADDRMOD0 (0x00008000UL) + +/* Bit definition for I2C_SLR1 register */ +#define I2C_SLR1_SLADDR1_POS (0U) +#define I2C_SLR1_SLADDR1 (0x000003FFUL) +#define I2C_SLR1_SLADDR1EN_POS (12U) +#define I2C_SLR1_SLADDR1EN (0x00001000UL) +#define I2C_SLR1_ADDRMOD1_POS (15U) +#define I2C_SLR1_ADDRMOD1 (0x00008000UL) + +/* Bit definition for I2C_SLTR register */ +#define I2C_SLTR_TOUTLOW_POS (0U) +#define I2C_SLTR_TOUTLOW (0x0000FFFFUL) +#define I2C_SLTR_TOUTHIGH_POS (16U) +#define I2C_SLTR_TOUTHIGH (0xFFFF0000UL) + +/* Bit definition for I2C_SR register */ +#define I2C_SR_STARTF_POS (0U) +#define I2C_SR_STARTF (0x00000001UL) +#define I2C_SR_SLADDR0F_POS (1U) +#define I2C_SR_SLADDR0F (0x00000002UL) +#define I2C_SR_SLADDR1F_POS (2U) +#define I2C_SR_SLADDR1F (0x00000004UL) +#define I2C_SR_TENDF_POS (3U) +#define I2C_SR_TENDF (0x00000008UL) +#define I2C_SR_STOPF_POS (4U) +#define I2C_SR_STOPF (0x00000010UL) +#define I2C_SR_RFULLF_POS (6U) +#define I2C_SR_RFULLF (0x00000040UL) +#define I2C_SR_TEMPTYF_POS (7U) +#define I2C_SR_TEMPTYF (0x00000080UL) +#define I2C_SR_ARLOF_POS (9U) +#define I2C_SR_ARLOF (0x00000200UL) +#define I2C_SR_ACKRF_POS (10U) +#define I2C_SR_ACKRF (0x00000400UL) +#define I2C_SR_NACKF_POS (12U) +#define I2C_SR_NACKF (0x00001000UL) +#define I2C_SR_TMOUTF_POS (14U) +#define I2C_SR_TMOUTF (0x00004000UL) +#define I2C_SR_MSL_POS (16U) +#define I2C_SR_MSL (0x00010000UL) +#define I2C_SR_BUSY_POS (17U) +#define I2C_SR_BUSY (0x00020000UL) +#define I2C_SR_TRA_POS (18U) +#define I2C_SR_TRA (0x00040000UL) +#define I2C_SR_GENCALLF_POS (20U) +#define I2C_SR_GENCALLF (0x00100000UL) +#define I2C_SR_SMBDEFAULTF_POS (21U) +#define I2C_SR_SMBDEFAULTF (0x00200000UL) +#define I2C_SR_SMBHOSTF_POS (22U) +#define I2C_SR_SMBHOSTF (0x00400000UL) +#define I2C_SR_SMBALRTF_POS (23U) +#define I2C_SR_SMBALRTF (0x00800000UL) + +/* Bit definition for I2C_CLR register */ +#define I2C_CLR_STARTFCLR_POS (0U) +#define I2C_CLR_STARTFCLR (0x00000001UL) +#define I2C_CLR_SLADDR0FCLR_POS (1U) +#define I2C_CLR_SLADDR0FCLR (0x00000002UL) +#define I2C_CLR_SLADDR1FCLR_POS (2U) +#define I2C_CLR_SLADDR1FCLR (0x00000004UL) +#define I2C_CLR_TENDFCLR_POS (3U) +#define I2C_CLR_TENDFCLR (0x00000008UL) +#define I2C_CLR_STOPFCLR_POS (4U) +#define I2C_CLR_STOPFCLR (0x00000010UL) +#define I2C_CLR_RFULLFCLR_POS (6U) +#define I2C_CLR_RFULLFCLR (0x00000040UL) +#define I2C_CLR_TEMPTYFCLR_POS (7U) +#define I2C_CLR_TEMPTYFCLR (0x00000080UL) +#define I2C_CLR_ARLOFCLR_POS (9U) +#define I2C_CLR_ARLOFCLR (0x00000200UL) +#define I2C_CLR_NACKFCLR_POS (12U) +#define I2C_CLR_NACKFCLR (0x00001000UL) +#define I2C_CLR_TMOUTFCLR_POS (14U) +#define I2C_CLR_TMOUTFCLR (0x00004000UL) +#define I2C_CLR_GENCALLFCLR_POS (20U) +#define I2C_CLR_GENCALLFCLR (0x00100000UL) +#define I2C_CLR_SMBDEFAULTFCLR_POS (21U) +#define I2C_CLR_SMBDEFAULTFCLR (0x00200000UL) +#define I2C_CLR_SMBHOSTFCLR_POS (22U) +#define I2C_CLR_SMBHOSTFCLR (0x00400000UL) +#define I2C_CLR_SMBALRTFCLR_POS (23U) +#define I2C_CLR_SMBALRTFCLR (0x00800000UL) + +/* Bit definition for I2C_DTR register */ +#define I2C_DTR_DT (0xFFU) + +/* Bit definition for I2C_DRR register */ +#define I2C_DRR_DR (0xFFU) + +/* Bit definition for I2C_CCR register */ +#define I2C_CCR_SLOWW_POS (0U) +#define I2C_CCR_SLOWW (0x0000001FUL) +#define I2C_CCR_SHIGHW_POS (8U) +#define I2C_CCR_SHIGHW (0x00001F00UL) +#define I2C_CCR_CKDIV_POS (16U) +#define I2C_CCR_CKDIV (0x00070000UL) + +/* Bit definition for I2C_FLTR register */ +#define I2C_FLTR_DNF_POS (0U) +#define I2C_FLTR_DNF (0x00000003UL) +#define I2C_FLTR_DNF_0 (0x00000001UL) +#define I2C_FLTR_DNF_1 (0x00000002UL) +#define I2C_FLTR_DNFEN_POS (4U) +#define I2C_FLTR_DNFEN (0x00000010UL) +#define I2C_FLTR_ANFEN_POS (5U) +#define I2C_FLTR_ANFEN (0x00000020UL) + +/******************************************************************************* + Bit definition for Peripheral I2S +*******************************************************************************/ +/* Bit definition for I2S_CTRL register */ +#define I2S_CTRL_TXE_POS (0U) +#define I2S_CTRL_TXE (0x00000001UL) +#define I2S_CTRL_TXIE_POS (1U) +#define I2S_CTRL_TXIE (0x00000002UL) +#define I2S_CTRL_RXE_POS (2U) +#define I2S_CTRL_RXE (0x00000004UL) +#define I2S_CTRL_RXIE_POS (3U) +#define I2S_CTRL_RXIE (0x00000008UL) +#define I2S_CTRL_EIE_POS (4U) +#define I2S_CTRL_EIE (0x00000010UL) +#define I2S_CTRL_WMS_POS (5U) +#define I2S_CTRL_WMS (0x00000020UL) +#define I2S_CTRL_ODD_POS (6U) +#define I2S_CTRL_ODD (0x00000040UL) +#define I2S_CTRL_MCKOE_POS (7U) +#define I2S_CTRL_MCKOE (0x00000080UL) +#define I2S_CTRL_TXBIRQWL_POS (8U) +#define I2S_CTRL_TXBIRQWL (0x00000700UL) +#define I2S_CTRL_RXBIRQWL_POS (12U) +#define I2S_CTRL_RXBIRQWL (0x00007000UL) +#define I2S_CTRL_FIFOR_POS (16U) +#define I2S_CTRL_FIFOR (0x00010000UL) +#define I2S_CTRL_I2SPLLSEL_POS (18U) +#define I2S_CTRL_I2SPLLSEL (0x00040000UL) +#define I2S_CTRL_SDOE_POS (19U) +#define I2S_CTRL_SDOE (0x00080000UL) +#define I2S_CTRL_LRCKOE_POS (20U) +#define I2S_CTRL_LRCKOE (0x00100000UL) +#define I2S_CTRL_CKOE_POS (21U) +#define I2S_CTRL_CKOE (0x00200000UL) +#define I2S_CTRL_DUPLEX_POS (22U) +#define I2S_CTRL_DUPLEX (0x00400000UL) +#define I2S_CTRL_CLKSEL_POS (23U) +#define I2S_CTRL_CLKSEL (0x00800000UL) + +/* Bit definition for I2S_SR register */ +#define I2S_SR_TXBA_POS (0U) +#define I2S_SR_TXBA (0x00000001UL) +#define I2S_SR_RXBA_POS (1U) +#define I2S_SR_RXBA (0x00000002UL) +#define I2S_SR_TXBE_POS (2U) +#define I2S_SR_TXBE (0x00000004UL) +#define I2S_SR_TXBF_POS (3U) +#define I2S_SR_TXBF (0x00000008UL) +#define I2S_SR_RXBE_POS (4U) +#define I2S_SR_RXBE (0x00000010UL) +#define I2S_SR_RXBF_POS (5U) +#define I2S_SR_RXBF (0x00000020UL) + +/* Bit definition for I2S_ER register */ +#define I2S_ER_TXERR_POS (0U) +#define I2S_ER_TXERR (0x00000001UL) +#define I2S_ER_RXERR_POS (1U) +#define I2S_ER_RXERR (0x00000002UL) + +/* Bit definition for I2S_CFGR register */ +#define I2S_CFGR_I2SSTD_POS (0U) +#define I2S_CFGR_I2SSTD (0x00000003UL) +#define I2S_CFGR_I2SSTD_0 (0x00000001UL) +#define I2S_CFGR_I2SSTD_1 (0x00000002UL) +#define I2S_CFGR_DATLEN_POS (2U) +#define I2S_CFGR_DATLEN (0x0000000CUL) +#define I2S_CFGR_DATLEN_0 (0x00000004UL) +#define I2S_CFGR_DATLEN_1 (0x00000008UL) +#define I2S_CFGR_CHLEN_POS (4U) +#define I2S_CFGR_CHLEN (0x00000010UL) +#define I2S_CFGR_PCMSYNC_POS (5U) +#define I2S_CFGR_PCMSYNC (0x00000020UL) + +/* Bit definition for I2S_TXBUF register */ +#define I2S_TXBUF (0xFFFFFFFFUL) + +/* Bit definition for I2S_RXBUF register */ +#define I2S_RXBUF (0xFFFFFFFFUL) + +/* Bit definition for I2S_PR register */ +#define I2S_PR_I2SDIV (0x000000FFUL) + +/******************************************************************************* + Bit definition for Peripheral ICG +*******************************************************************************/ +/* Bit definition for ICG_ICG0 register */ +#define ICG_ICG0_SWDTAUTS_POS (0U) +#define ICG_ICG0_SWDTAUTS (0x00000001UL) +#define ICG_ICG0_SWDTITS_POS (1U) +#define ICG_ICG0_SWDTITS (0x00000002UL) +#define ICG_ICG0_SWDTPERI_POS (2U) +#define ICG_ICG0_SWDTPERI (0x0000000CUL) +#define ICG_ICG0_SWDTPERI_0 (0x00000004UL) +#define ICG_ICG0_SWDTPERI_1 (0x00000008UL) +#define ICG_ICG0_SWDTCKS_POS (4U) +#define ICG_ICG0_SWDTCKS (0x000000F0UL) +#define ICG_ICG0_SWDTWDPT_POS (8U) +#define ICG_ICG0_SWDTWDPT (0x00000F00UL) +#define ICG_ICG0_SWDTSLPOFF_POS (12U) +#define ICG_ICG0_SWDTSLPOFF (0x00001000UL) +#define ICG_ICG0_WDTAUTS_POS (16U) +#define ICG_ICG0_WDTAUTS (0x00010000UL) +#define ICG_ICG0_WDTITS_POS (17U) +#define ICG_ICG0_WDTITS (0x00020000UL) +#define ICG_ICG0_WDTPERI_POS (18U) +#define ICG_ICG0_WDTPERI (0x000C0000UL) +#define ICG_ICG0_WDTPERI_0 (0x00040000UL) +#define ICG_ICG0_WDTPERI_1 (0x00080000UL) +#define ICG_ICG0_WDTCKS_POS (20U) +#define ICG_ICG0_WDTCKS (0x00F00000UL) +#define ICG_ICG0_WDTWDPT_POS (24U) +#define ICG_ICG0_WDTWDPT (0x0F000000UL) +#define ICG_ICG0_WDTSLPOFF_POS (28U) +#define ICG_ICG0_WDTSLPOFF (0x10000000UL) + +/* Bit definition for ICG_ICG1 register */ +#define ICG_ICG1_HRCFREQSEL_POS (0U) +#define ICG_ICG1_HRCFREQSEL (0x00000001UL) +#define ICG_ICG1_HRCSTOP_POS (8U) +#define ICG_ICG1_HRCSTOP (0x00000100UL) +#define ICG_ICG1_BOR_LEV_POS (16U) +#define ICG_ICG1_BOR_LEV (0x00030000UL) +#define ICG_ICG1_BOR_LEV_0 (0x00010000UL) +#define ICG_ICG1_BOR_LEV_1 (0x00020000UL) +#define ICG_ICG1_BORDIS_POS (18U) +#define ICG_ICG1_BORDIS (0x00040000UL) +#define ICG_ICG1_SMPCLK_POS (26U) +#define ICG_ICG1_SMPCLK (0x0C000000UL) +#define ICG_ICG1_SMPCLK_0 (0x04000000UL) +#define ICG_ICG1_SMPCLK_1 (0x08000000UL) +#define ICG_ICG1_NMITRG_POS (28U) +#define ICG_ICG1_NMITRG (0x10000000UL) +#define ICG_ICG1_NMIEN_POS (29U) +#define ICG_ICG1_NMIEN (0x20000000UL) +#define ICG_ICG1_NFEN_POS (30U) +#define ICG_ICG1_NFEN (0x40000000UL) +#define ICG_ICG1_NMIICGEN_POS (31U) +#define ICG_ICG1_NMIICGEN (0x80000000UL) + +/* Bit definition for ICG_ICG2 register */ +#define ICG_ICG2 (0xFFFFFFFFUL) + +/* Bit definition for ICG_ICG3 register */ +#define ICG_ICG3 (0xFFFFFFFFUL) + +/* Bit definition for ICG_ICG4 register */ +#define ICG_ICG4 (0xFFFFFFFFUL) + +/* Bit definition for ICG_ICG5 register */ +#define ICG_ICG5 (0xFFFFFFFFUL) + +/* Bit definition for ICG_ICG6 register */ +#define ICG_ICG6 (0xFFFFFFFFUL) + +/* Bit definition for ICG_ICG7 register */ +#define ICG_ICG7 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral INTC +*******************************************************************************/ +/* Bit definition for INTC_NMICR register */ +#define INTC_NMICR_NMITRG_POS (0U) +#define INTC_NMICR_NMITRG (0x00000001UL) +#define INTC_NMICR_NSMPCLK_POS (4U) +#define INTC_NMICR_NSMPCLK (0x00000030UL) +#define INTC_NMICR_NSMPCLK_0 (0x00000010UL) +#define INTC_NMICR_NSMPCLK_1 (0x00000020UL) +#define INTC_NMICR_NFEN_POS (7U) +#define INTC_NMICR_NFEN (0x00000080UL) + +/* Bit definition for INTC_NMIENR register */ +#define INTC_NMIENR_NMIENR_POS (0U) +#define INTC_NMIENR_NMIENR (0x00000001UL) +#define INTC_NMIENR_SWDTENR_POS (1U) +#define INTC_NMIENR_SWDTENR (0x00000002UL) +#define INTC_NMIENR_PVD1ENR_POS (2U) +#define INTC_NMIENR_PVD1ENR (0x00000004UL) +#define INTC_NMIENR_PVD2ENR_POS (3U) +#define INTC_NMIENR_PVD2ENR (0x00000008UL) +#define INTC_NMIENR_XTALSTPENR_POS (5U) +#define INTC_NMIENR_XTALSTPENR (0x00000020UL) +#define INTC_NMIENR_REPENR_POS (8U) +#define INTC_NMIENR_REPENR (0x00000100UL) +#define INTC_NMIENR_RECCENR_POS (9U) +#define INTC_NMIENR_RECCENR (0x00000200UL) +#define INTC_NMIENR_BUSMENR_POS (10U) +#define INTC_NMIENR_BUSMENR (0x00000400UL) +#define INTC_NMIENR_WDTENR_POS (11U) +#define INTC_NMIENR_WDTENR (0x00000800UL) + +/* Bit definition for INTC_NMIFR register */ +#define INTC_NMIFR_NMIFR_POS (0U) +#define INTC_NMIFR_NMIFR (0x00000001UL) +#define INTC_NMIFR_SWDTFR_POS (1U) +#define INTC_NMIFR_SWDTFR (0x00000002UL) +#define INTC_NMIFR_PVD1FR_POS (2U) +#define INTC_NMIFR_PVD1FR (0x00000004UL) +#define INTC_NMIFR_PVD2FR_POS (3U) +#define INTC_NMIFR_PVD2FR (0x00000008UL) +#define INTC_NMIFR_XTALSTPFR_POS (5U) +#define INTC_NMIFR_XTALSTPFR (0x00000020UL) +#define INTC_NMIFR_REPFR_POS (8U) +#define INTC_NMIFR_REPFR (0x00000100UL) +#define INTC_NMIFR_RECCFR_POS (9U) +#define INTC_NMIFR_RECCFR (0x00000200UL) +#define INTC_NMIFR_BUSMFR_POS (10U) +#define INTC_NMIFR_BUSMFR (0x00000400UL) +#define INTC_NMIFR_WDTFR_POS (11U) +#define INTC_NMIFR_WDTFR (0x00000800UL) + +/* Bit definition for INTC_NMICFR register */ +#define INTC_NMICFR_NMICFR_POS (0U) +#define INTC_NMICFR_NMICFR (0x00000001UL) +#define INTC_NMICFR_SWDTCFR_POS (1U) +#define INTC_NMICFR_SWDTCFR (0x00000002UL) +#define INTC_NMICFR_PVD1CFR_POS (2U) +#define INTC_NMICFR_PVD1CFR (0x00000004UL) +#define INTC_NMICFR_PVD2CFR_POS (3U) +#define INTC_NMICFR_PVD2CFR (0x00000008UL) +#define INTC_NMICFR_XTALSTPCFR_POS (5U) +#define INTC_NMICFR_XTALSTPCFR (0x00000020UL) +#define INTC_NMICFR_REPCFR_POS (8U) +#define INTC_NMICFR_REPCFR (0x00000100UL) +#define INTC_NMICFR_RECCCFR_POS (9U) +#define INTC_NMICFR_RECCCFR (0x00000200UL) +#define INTC_NMICFR_BUSMCFR_POS (10U) +#define INTC_NMICFR_BUSMCFR (0x00000400UL) +#define INTC_NMICFR_WDTCFR_POS (11U) +#define INTC_NMICFR_WDTCFR (0x00000800UL) + +/* Bit definition for INTC_EIRQCR register */ +#define INTC_EIRQCR_EIRQTRG_POS (0U) +#define INTC_EIRQCR_EIRQTRG (0x00000003UL) +#define INTC_EIRQCR_EIRQTRG_0 (0x00000001UL) +#define INTC_EIRQCR_EIRQTRG_1 (0x00000002UL) +#define INTC_EIRQCR_EISMPCLK_POS (4U) +#define INTC_EIRQCR_EISMPCLK (0x00000030UL) +#define INTC_EIRQCR_EISMPCLK_0 (0x00000010UL) +#define INTC_EIRQCR_EISMPCLK_1 (0x00000020UL) +#define INTC_EIRQCR_EFEN_POS (7U) +#define INTC_EIRQCR_EFEN (0x00000080UL) + +/* Bit definition for INTC_WUPEN register */ +#define INTC_WUPEN_EIRQWUEN_POS (0U) +#define INTC_WUPEN_EIRQWUEN (0x0000FFFFUL) +#define INTC_WUPEN_EIRQWUEN_0 (0x00000001UL) +#define INTC_WUPEN_EIRQWUEN_1 (0x00000002UL) +#define INTC_WUPEN_EIRQWUEN_2 (0x00000004UL) +#define INTC_WUPEN_EIRQWUEN_3 (0x00000008UL) +#define INTC_WUPEN_EIRQWUEN_4 (0x00000010UL) +#define INTC_WUPEN_EIRQWUEN_5 (0x00000020UL) +#define INTC_WUPEN_EIRQWUEN_6 (0x00000040UL) +#define INTC_WUPEN_EIRQWUEN_7 (0x00000080UL) +#define INTC_WUPEN_EIRQWUEN_8 (0x00000100UL) +#define INTC_WUPEN_EIRQWUEN_9 (0x00000200UL) +#define INTC_WUPEN_EIRQWUEN_10 (0x00000400UL) +#define INTC_WUPEN_EIRQWUEN_11 (0x00000800UL) +#define INTC_WUPEN_EIRQWUEN_12 (0x00001000UL) +#define INTC_WUPEN_EIRQWUEN_13 (0x00002000UL) +#define INTC_WUPEN_EIRQWUEN_14 (0x00004000UL) +#define INTC_WUPEN_EIRQWUEN_15 (0x00008000UL) +#define INTC_WUPEN_SWDTWUEN_POS (16U) +#define INTC_WUPEN_SWDTWUEN (0x00010000UL) +#define INTC_WUPEN_PVD1WUEN_POS (17U) +#define INTC_WUPEN_PVD1WUEN (0x00020000UL) +#define INTC_WUPEN_PVD2WUEN_POS (18U) +#define INTC_WUPEN_PVD2WUEN (0x00040000UL) +#define INTC_WUPEN_CMPI0WUEN_POS (19U) +#define INTC_WUPEN_CMPI0WUEN (0x00080000UL) +#define INTC_WUPEN_WKTMWUEN_POS (20U) +#define INTC_WUPEN_WKTMWUEN (0x00100000UL) +#define INTC_WUPEN_RTCALMWUEN_POS (21U) +#define INTC_WUPEN_RTCALMWUEN (0x00200000UL) +#define INTC_WUPEN_RTCPRDWUEN_POS (22U) +#define INTC_WUPEN_RTCPRDWUEN (0x00400000UL) +#define INTC_WUPEN_TMR0WUEN_POS (23U) +#define INTC_WUPEN_TMR0WUEN (0x00800000UL) +#define INTC_WUPEN_RXWUEN_POS (25U) +#define INTC_WUPEN_RXWUEN (0x02000000UL) + +/* Bit definition for INTC_EIFR register */ +#define INTC_EIFR_EIFR0_POS (0U) +#define INTC_EIFR_EIFR0 (0x00000001UL) +#define INTC_EIFR_EIFR1_POS (1U) +#define INTC_EIFR_EIFR1 (0x00000002UL) +#define INTC_EIFR_EIFR2_POS (2U) +#define INTC_EIFR_EIFR2 (0x00000004UL) +#define INTC_EIFR_EIFR3_POS (3U) +#define INTC_EIFR_EIFR3 (0x00000008UL) +#define INTC_EIFR_EIFR4_POS (4U) +#define INTC_EIFR_EIFR4 (0x00000010UL) +#define INTC_EIFR_EIFR5_POS (5U) +#define INTC_EIFR_EIFR5 (0x00000020UL) +#define INTC_EIFR_EIFR6_POS (6U) +#define INTC_EIFR_EIFR6 (0x00000040UL) +#define INTC_EIFR_EIFR7_POS (7U) +#define INTC_EIFR_EIFR7 (0x00000080UL) +#define INTC_EIFR_EIFR8_POS (8U) +#define INTC_EIFR_EIFR8 (0x00000100UL) +#define INTC_EIFR_EIFR9_POS (9U) +#define INTC_EIFR_EIFR9 (0x00000200UL) +#define INTC_EIFR_EIFR10_POS (10U) +#define INTC_EIFR_EIFR10 (0x00000400UL) +#define INTC_EIFR_EIFR11_POS (11U) +#define INTC_EIFR_EIFR11 (0x00000800UL) +#define INTC_EIFR_EIFR12_POS (12U) +#define INTC_EIFR_EIFR12 (0x00001000UL) +#define INTC_EIFR_EIFR13_POS (13U) +#define INTC_EIFR_EIFR13 (0x00002000UL) +#define INTC_EIFR_EIFR14_POS (14U) +#define INTC_EIFR_EIFR14 (0x00004000UL) +#define INTC_EIFR_EIFR15_POS (15U) +#define INTC_EIFR_EIFR15 (0x00008000UL) + +/* Bit definition for INTC_EIFCR register */ +#define INTC_EIFCR_EIFCR0_POS (0U) +#define INTC_EIFCR_EIFCR0 (0x00000001UL) +#define INTC_EIFCR_EIFCR1_POS (1U) +#define INTC_EIFCR_EIFCR1 (0x00000002UL) +#define INTC_EIFCR_EIFCR2_POS (2U) +#define INTC_EIFCR_EIFCR2 (0x00000004UL) +#define INTC_EIFCR_EIFCR3_POS (3U) +#define INTC_EIFCR_EIFCR3 (0x00000008UL) +#define INTC_EIFCR_EIFCR4_POS (4U) +#define INTC_EIFCR_EIFCR4 (0x00000010UL) +#define INTC_EIFCR_EIFCR5_POS (5U) +#define INTC_EIFCR_EIFCR5 (0x00000020UL) +#define INTC_EIFCR_EIFCR6_POS (6U) +#define INTC_EIFCR_EIFCR6 (0x00000040UL) +#define INTC_EIFCR_EIFCR7_POS (7U) +#define INTC_EIFCR_EIFCR7 (0x00000080UL) +#define INTC_EIFCR_EIFCR8_POS (8U) +#define INTC_EIFCR_EIFCR8 (0x00000100UL) +#define INTC_EIFCR_EIFCR9_POS (9U) +#define INTC_EIFCR_EIFCR9 (0x00000200UL) +#define INTC_EIFCR_EIFCR10_POS (10U) +#define INTC_EIFCR_EIFCR10 (0x00000400UL) +#define INTC_EIFCR_EIFCR11_POS (11U) +#define INTC_EIFCR_EIFCR11 (0x00000800UL) +#define INTC_EIFCR_EIFCR12_POS (12U) +#define INTC_EIFCR_EIFCR12 (0x00001000UL) +#define INTC_EIFCR_EIFCR13_POS (13U) +#define INTC_EIFCR_EIFCR13 (0x00002000UL) +#define INTC_EIFCR_EIFCR14_POS (14U) +#define INTC_EIFCR_EIFCR14 (0x00004000UL) +#define INTC_EIFCR_EIFCR15_POS (15U) +#define INTC_EIFCR_EIFCR15 (0x00008000UL) + +/* Bit definition for INTC_SEL register */ +#define INTC_SEL_INTSEL (0x000001FFUL) +#define INTC_SEL_INTSEL_0 (0x00000001UL) +#define INTC_SEL_INTSEL_1 (0x00000002UL) +#define INTC_SEL_INTSEL_2 (0x00000004UL) +#define INTC_SEL_INTSEL_3 (0x00000008UL) +#define INTC_SEL_INTSEL_4 (0x00000010UL) +#define INTC_SEL_INTSEL_5 (0x00000020UL) +#define INTC_SEL_INTSEL_6 (0x00000040UL) +#define INTC_SEL_INTSEL_7 (0x00000080UL) +#define INTC_SEL_INTSEL_8 (0x00000100UL) + +/* Bit definition for INTC_VSSEL register */ +#define INTC_VSSEL_VSEL0_POS (0U) +#define INTC_VSSEL_VSEL0 (0x00000001UL) +#define INTC_VSSEL_VSEL1_POS (1U) +#define INTC_VSSEL_VSEL1 (0x00000002UL) +#define INTC_VSSEL_VSEL2_POS (2U) +#define INTC_VSSEL_VSEL2 (0x00000004UL) +#define INTC_VSSEL_VSEL3_POS (3U) +#define INTC_VSSEL_VSEL3 (0x00000008UL) +#define INTC_VSSEL_VSEL4_POS (4U) +#define INTC_VSSEL_VSEL4 (0x00000010UL) +#define INTC_VSSEL_VSEL5_POS (5U) +#define INTC_VSSEL_VSEL5 (0x00000020UL) +#define INTC_VSSEL_VSEL6_POS (6U) +#define INTC_VSSEL_VSEL6 (0x00000040UL) +#define INTC_VSSEL_VSEL7_POS (7U) +#define INTC_VSSEL_VSEL7 (0x00000080UL) +#define INTC_VSSEL_VSEL8_POS (8U) +#define INTC_VSSEL_VSEL8 (0x00000100UL) +#define INTC_VSSEL_VSEL9_POS (9U) +#define INTC_VSSEL_VSEL9 (0x00000200UL) +#define INTC_VSSEL_VSEL10_POS (10U) +#define INTC_VSSEL_VSEL10 (0x00000400UL) +#define INTC_VSSEL_VSEL11_POS (11U) +#define INTC_VSSEL_VSEL11 (0x00000800UL) +#define INTC_VSSEL_VSEL12_POS (12U) +#define INTC_VSSEL_VSEL12 (0x00001000UL) +#define INTC_VSSEL_VSEL13_POS (13U) +#define INTC_VSSEL_VSEL13 (0x00002000UL) +#define INTC_VSSEL_VSEL14_POS (14U) +#define INTC_VSSEL_VSEL14 (0x00004000UL) +#define INTC_VSSEL_VSEL15_POS (15U) +#define INTC_VSSEL_VSEL15 (0x00008000UL) +#define INTC_VSSEL_VSEL16_POS (16U) +#define INTC_VSSEL_VSEL16 (0x00010000UL) +#define INTC_VSSEL_VSEL17_POS (17U) +#define INTC_VSSEL_VSEL17 (0x00020000UL) +#define INTC_VSSEL_VSEL18_POS (18U) +#define INTC_VSSEL_VSEL18 (0x00040000UL) +#define INTC_VSSEL_VSEL19_POS (19U) +#define INTC_VSSEL_VSEL19 (0x00080000UL) +#define INTC_VSSEL_VSEL20_POS (20U) +#define INTC_VSSEL_VSEL20 (0x00100000UL) +#define INTC_VSSEL_VSEL21_POS (21U) +#define INTC_VSSEL_VSEL21 (0x00200000UL) +#define INTC_VSSEL_VSEL22_POS (22U) +#define INTC_VSSEL_VSEL22 (0x00400000UL) +#define INTC_VSSEL_VSEL23_POS (23U) +#define INTC_VSSEL_VSEL23 (0x00800000UL) +#define INTC_VSSEL_VSEL24_POS (24U) +#define INTC_VSSEL_VSEL24 (0x01000000UL) +#define INTC_VSSEL_VSEL25_POS (25U) +#define INTC_VSSEL_VSEL25 (0x02000000UL) +#define INTC_VSSEL_VSEL26_POS (26U) +#define INTC_VSSEL_VSEL26 (0x04000000UL) +#define INTC_VSSEL_VSEL27_POS (27U) +#define INTC_VSSEL_VSEL27 (0x08000000UL) +#define INTC_VSSEL_VSEL28_POS (28U) +#define INTC_VSSEL_VSEL28 (0x10000000UL) +#define INTC_VSSEL_VSEL29_POS (29U) +#define INTC_VSSEL_VSEL29 (0x20000000UL) +#define INTC_VSSEL_VSEL30_POS (30U) +#define INTC_VSSEL_VSEL30 (0x40000000UL) +#define INTC_VSSEL_VSEL31_POS (31U) +#define INTC_VSSEL_VSEL31 (0x80000000UL) + +/* Bit definition for INTC_SWIER register */ +#define INTC_SWIER_SWIE0_POS (0U) +#define INTC_SWIER_SWIE0 (0x00000001UL) +#define INTC_SWIER_SWIE1_POS (1U) +#define INTC_SWIER_SWIE1 (0x00000002UL) +#define INTC_SWIER_SWIE2_POS (2U) +#define INTC_SWIER_SWIE2 (0x00000004UL) +#define INTC_SWIER_SWIE3_POS (3U) +#define INTC_SWIER_SWIE3 (0x00000008UL) +#define INTC_SWIER_SWIE4_POS (4U) +#define INTC_SWIER_SWIE4 (0x00000010UL) +#define INTC_SWIER_SWIE5_POS (5U) +#define INTC_SWIER_SWIE5 (0x00000020UL) +#define INTC_SWIER_SWIE6_POS (6U) +#define INTC_SWIER_SWIE6 (0x00000040UL) +#define INTC_SWIER_SWIE7_POS (7U) +#define INTC_SWIER_SWIE7 (0x00000080UL) +#define INTC_SWIER_SWIE8_POS (8U) +#define INTC_SWIER_SWIE8 (0x00000100UL) +#define INTC_SWIER_SWIE9_POS (9U) +#define INTC_SWIER_SWIE9 (0x00000200UL) +#define INTC_SWIER_SWIE10_POS (10U) +#define INTC_SWIER_SWIE10 (0x00000400UL) +#define INTC_SWIER_SWIE11_POS (11U) +#define INTC_SWIER_SWIE11 (0x00000800UL) +#define INTC_SWIER_SWIE12_POS (12U) +#define INTC_SWIER_SWIE12 (0x00001000UL) +#define INTC_SWIER_SWIE13_POS (13U) +#define INTC_SWIER_SWIE13 (0x00002000UL) +#define INTC_SWIER_SWIE14_POS (14U) +#define INTC_SWIER_SWIE14 (0x00004000UL) +#define INTC_SWIER_SWIE15_POS (15U) +#define INTC_SWIER_SWIE15 (0x00008000UL) +#define INTC_SWIER_SWIE16_POS (16U) +#define INTC_SWIER_SWIE16 (0x00010000UL) +#define INTC_SWIER_SWIE17_POS (17U) +#define INTC_SWIER_SWIE17 (0x00020000UL) +#define INTC_SWIER_SWIE18_POS (18U) +#define INTC_SWIER_SWIE18 (0x00040000UL) +#define INTC_SWIER_SWIE19_POS (19U) +#define INTC_SWIER_SWIE19 (0x00080000UL) +#define INTC_SWIER_SWIE20_POS (20U) +#define INTC_SWIER_SWIE20 (0x00100000UL) +#define INTC_SWIER_SWIE21_POS (21U) +#define INTC_SWIER_SWIE21 (0x00200000UL) +#define INTC_SWIER_SWIE22_POS (22U) +#define INTC_SWIER_SWIE22 (0x00400000UL) +#define INTC_SWIER_SWIE23_POS (23U) +#define INTC_SWIER_SWIE23 (0x00800000UL) +#define INTC_SWIER_SWIE24_POS (24U) +#define INTC_SWIER_SWIE24 (0x01000000UL) +#define INTC_SWIER_SWIE25_POS (25U) +#define INTC_SWIER_SWIE25 (0x02000000UL) +#define INTC_SWIER_SWIE26_POS (26U) +#define INTC_SWIER_SWIE26 (0x04000000UL) +#define INTC_SWIER_SWIE27_POS (27U) +#define INTC_SWIER_SWIE27 (0x08000000UL) +#define INTC_SWIER_SWIE28_POS (28U) +#define INTC_SWIER_SWIE28 (0x10000000UL) +#define INTC_SWIER_SWIE29_POS (29U) +#define INTC_SWIER_SWIE29 (0x20000000UL) +#define INTC_SWIER_SWIE30_POS (30U) +#define INTC_SWIER_SWIE30 (0x40000000UL) +#define INTC_SWIER_SWIE31_POS (31U) +#define INTC_SWIER_SWIE31 (0x80000000UL) + +/* Bit definition for INTC_EVTER register */ +#define INTC_EVTER_EVTE0_POS (0U) +#define INTC_EVTER_EVTE0 (0x00000001UL) +#define INTC_EVTER_EVTE1_POS (1U) +#define INTC_EVTER_EVTE1 (0x00000002UL) +#define INTC_EVTER_EVTE2_POS (2U) +#define INTC_EVTER_EVTE2 (0x00000004UL) +#define INTC_EVTER_EVTE3_POS (3U) +#define INTC_EVTER_EVTE3 (0x00000008UL) +#define INTC_EVTER_EVTE4_POS (4U) +#define INTC_EVTER_EVTE4 (0x00000010UL) +#define INTC_EVTER_EVTE5_POS (5U) +#define INTC_EVTER_EVTE5 (0x00000020UL) +#define INTC_EVTER_EVTE6_POS (6U) +#define INTC_EVTER_EVTE6 (0x00000040UL) +#define INTC_EVTER_EVTE7_POS (7U) +#define INTC_EVTER_EVTE7 (0x00000080UL) +#define INTC_EVTER_EVTE8_POS (8U) +#define INTC_EVTER_EVTE8 (0x00000100UL) +#define INTC_EVTER_EVTE9_POS (9U) +#define INTC_EVTER_EVTE9 (0x00000200UL) +#define INTC_EVTER_EVTE10_POS (10U) +#define INTC_EVTER_EVTE10 (0x00000400UL) +#define INTC_EVTER_EVTE11_POS (11U) +#define INTC_EVTER_EVTE11 (0x00000800UL) +#define INTC_EVTER_EVTE12_POS (12U) +#define INTC_EVTER_EVTE12 (0x00001000UL) +#define INTC_EVTER_EVTE13_POS (13U) +#define INTC_EVTER_EVTE13 (0x00002000UL) +#define INTC_EVTER_EVTE14_POS (14U) +#define INTC_EVTER_EVTE14 (0x00004000UL) +#define INTC_EVTER_EVTE15_POS (15U) +#define INTC_EVTER_EVTE15 (0x00008000UL) +#define INTC_EVTER_EVTE16_POS (16U) +#define INTC_EVTER_EVTE16 (0x00010000UL) +#define INTC_EVTER_EVTE17_POS (17U) +#define INTC_EVTER_EVTE17 (0x00020000UL) +#define INTC_EVTER_EVTE18_POS (18U) +#define INTC_EVTER_EVTE18 (0x00040000UL) +#define INTC_EVTER_EVTE19_POS (19U) +#define INTC_EVTER_EVTE19 (0x00080000UL) +#define INTC_EVTER_EVTE20_POS (20U) +#define INTC_EVTER_EVTE20 (0x00100000UL) +#define INTC_EVTER_EVTE21_POS (21U) +#define INTC_EVTER_EVTE21 (0x00200000UL) +#define INTC_EVTER_EVTE22_POS (22U) +#define INTC_EVTER_EVTE22 (0x00400000UL) +#define INTC_EVTER_EVTE23_POS (23U) +#define INTC_EVTER_EVTE23 (0x00800000UL) +#define INTC_EVTER_EVTE24_POS (24U) +#define INTC_EVTER_EVTE24 (0x01000000UL) +#define INTC_EVTER_EVTE25_POS (25U) +#define INTC_EVTER_EVTE25 (0x02000000UL) +#define INTC_EVTER_EVTE26_POS (26U) +#define INTC_EVTER_EVTE26 (0x04000000UL) +#define INTC_EVTER_EVTE27_POS (27U) +#define INTC_EVTER_EVTE27 (0x08000000UL) +#define INTC_EVTER_EVTE28_POS (28U) +#define INTC_EVTER_EVTE28 (0x10000000UL) +#define INTC_EVTER_EVTE29_POS (29U) +#define INTC_EVTER_EVTE29 (0x20000000UL) +#define INTC_EVTER_EVTE30_POS (30U) +#define INTC_EVTER_EVTE30 (0x40000000UL) +#define INTC_EVTER_EVTE31_POS (31U) +#define INTC_EVTER_EVTE31 (0x80000000UL) + +/* Bit definition for INTC_IER register */ +#define INTC_IER_IER0_POS (0U) +#define INTC_IER_IER0 (0x00000001UL) +#define INTC_IER_IER1_POS (1U) +#define INTC_IER_IER1 (0x00000002UL) +#define INTC_IER_IER2_POS (2U) +#define INTC_IER_IER2 (0x00000004UL) +#define INTC_IER_IER3_POS (3U) +#define INTC_IER_IER3 (0x00000008UL) +#define INTC_IER_IER4_POS (4U) +#define INTC_IER_IER4 (0x00000010UL) +#define INTC_IER_IER5_POS (5U) +#define INTC_IER_IER5 (0x00000020UL) +#define INTC_IER_IER6_POS (6U) +#define INTC_IER_IER6 (0x00000040UL) +#define INTC_IER_IER7_POS (7U) +#define INTC_IER_IER7 (0x00000080UL) +#define INTC_IER_IER8_POS (8U) +#define INTC_IER_IER8 (0x00000100UL) +#define INTC_IER_IER9_POS (9U) +#define INTC_IER_IER9 (0x00000200UL) +#define INTC_IER_IER10_POS (10U) +#define INTC_IER_IER10 (0x00000400UL) +#define INTC_IER_IER11_POS (11U) +#define INTC_IER_IER11 (0x00000800UL) +#define INTC_IER_IER12_POS (12U) +#define INTC_IER_IER12 (0x00001000UL) +#define INTC_IER_IER13_POS (13U) +#define INTC_IER_IER13 (0x00002000UL) +#define INTC_IER_IER14_POS (14U) +#define INTC_IER_IER14 (0x00004000UL) +#define INTC_IER_IER15_POS (15U) +#define INTC_IER_IER15 (0x00008000UL) +#define INTC_IER_IER16_POS (16U) +#define INTC_IER_IER16 (0x00010000UL) +#define INTC_IER_IER17_POS (17U) +#define INTC_IER_IER17 (0x00020000UL) +#define INTC_IER_IER18_POS (18U) +#define INTC_IER_IER18 (0x00040000UL) +#define INTC_IER_IER19_POS (19U) +#define INTC_IER_IER19 (0x00080000UL) +#define INTC_IER_IER20_POS (20U) +#define INTC_IER_IER20 (0x00100000UL) +#define INTC_IER_IER21_POS (21U) +#define INTC_IER_IER21 (0x00200000UL) +#define INTC_IER_IER22_POS (22U) +#define INTC_IER_IER22 (0x00400000UL) +#define INTC_IER_IER23_POS (23U) +#define INTC_IER_IER23 (0x00800000UL) +#define INTC_IER_IER24_POS (24U) +#define INTC_IER_IER24 (0x01000000UL) +#define INTC_IER_IER25_POS (25U) +#define INTC_IER_IER25 (0x02000000UL) +#define INTC_IER_IER26_POS (26U) +#define INTC_IER_IER26 (0x04000000UL) +#define INTC_IER_IER27_POS (27U) +#define INTC_IER_IER27 (0x08000000UL) +#define INTC_IER_IER28_POS (28U) +#define INTC_IER_IER28 (0x10000000UL) +#define INTC_IER_IER29_POS (29U) +#define INTC_IER_IER29 (0x20000000UL) +#define INTC_IER_IER30_POS (30U) +#define INTC_IER_IER30 (0x40000000UL) +#define INTC_IER_IER31_POS (31U) +#define INTC_IER_IER31 (0x80000000UL) + +/******************************************************************************* + Bit definition for Peripheral KEYSCAN +*******************************************************************************/ +/* Bit definition for KEYSCAN_SCR register */ +#define KEYSCAN_SCR_KEYINSEL_POS (0U) +#define KEYSCAN_SCR_KEYINSEL (0x0000FFFFUL) +#define KEYSCAN_SCR_KEYOUTSEL_POS (16U) +#define KEYSCAN_SCR_KEYOUTSEL (0x00070000UL) +#define KEYSCAN_SCR_CKSEL_POS (20U) +#define KEYSCAN_SCR_CKSEL (0x00300000UL) +#define KEYSCAN_SCR_CKSEL_0 (0x00100000UL) +#define KEYSCAN_SCR_CKSEL_1 (0x00200000UL) +#define KEYSCAN_SCR_T_LLEVEL_POS (24U) +#define KEYSCAN_SCR_T_LLEVEL (0x1F000000UL) +#define KEYSCAN_SCR_T_HIZ_POS (29U) +#define KEYSCAN_SCR_T_HIZ (0xE0000000UL) + +/* Bit definition for KEYSCAN_SER register */ +#define KEYSCAN_SER_SEN (0x00000001UL) + +/* Bit definition for KEYSCAN_SSR register */ +#define KEYSCAN_SSR_INDEX (0x00000007UL) + +/******************************************************************************* + Bit definition for Peripheral MPU +*******************************************************************************/ +/* Bit definition for MPU_RGD register */ +#define MPU_RGD_MPURGSIZE_POS (0U) +#define MPU_RGD_MPURGSIZE (0x0000001FUL) +#define MPU_RGD_MPURGADDR_POS (5U) +#define MPU_RGD_MPURGADDR (0xFFFFFFE0UL) + +/* Bit definition for MPU_RGCR register */ +#define MPU_RGCR_S2RGRP_POS (0U) +#define MPU_RGCR_S2RGRP (0x00000001UL) +#define MPU_RGCR_S2RGWP_POS (1U) +#define MPU_RGCR_S2RGWP (0x00000002UL) +#define MPU_RGCR_S2RGE_POS (7U) +#define MPU_RGCR_S2RGE (0x00000080UL) +#define MPU_RGCR_S1RGRP_POS (8U) +#define MPU_RGCR_S1RGRP (0x00000100UL) +#define MPU_RGCR_S1RGWP_POS (9U) +#define MPU_RGCR_S1RGWP (0x00000200UL) +#define MPU_RGCR_S1RGE_POS (15U) +#define MPU_RGCR_S1RGE (0x00008000UL) +#define MPU_RGCR_FRGRP_POS (16U) +#define MPU_RGCR_FRGRP (0x00010000UL) +#define MPU_RGCR_FRGWP_POS (17U) +#define MPU_RGCR_FRGWP (0x00020000UL) +#define MPU_RGCR_FRGE_POS (23U) +#define MPU_RGCR_FRGE (0x00800000UL) + +/* Bit definition for MPU_CR register */ +#define MPU_CR_SMPU2BRP_POS (0U) +#define MPU_CR_SMPU2BRP (0x00000001UL) +#define MPU_CR_SMPU2BWP_POS (1U) +#define MPU_CR_SMPU2BWP (0x00000002UL) +#define MPU_CR_SMPU2ACT_POS (2U) +#define MPU_CR_SMPU2ACT (0x0000000CUL) +#define MPU_CR_SMPU2ACT_0 (0x00000004UL) +#define MPU_CR_SMPU2ACT_1 (0x00000008UL) +#define MPU_CR_SMPU2E_POS (7U) +#define MPU_CR_SMPU2E (0x00000080UL) +#define MPU_CR_SMPU1BRP_POS (8U) +#define MPU_CR_SMPU1BRP (0x00000100UL) +#define MPU_CR_SMPU1BWP_POS (9U) +#define MPU_CR_SMPU1BWP (0x00000200UL) +#define MPU_CR_SMPU1ACT_POS (10U) +#define MPU_CR_SMPU1ACT (0x00000C00UL) +#define MPU_CR_SMPU1ACT_0 (0x00000400UL) +#define MPU_CR_SMPU1ACT_1 (0x00000800UL) +#define MPU_CR_SMPU1E_POS (15U) +#define MPU_CR_SMPU1E (0x00008000UL) +#define MPU_CR_FMPUBRP_POS (16U) +#define MPU_CR_FMPUBRP (0x00010000UL) +#define MPU_CR_FMPUBWP_POS (17U) +#define MPU_CR_FMPUBWP (0x00020000UL) +#define MPU_CR_FMPUACT_POS (18U) +#define MPU_CR_FMPUACT (0x000C0000UL) +#define MPU_CR_FMPUACT_0 (0x00040000UL) +#define MPU_CR_FMPUACT_1 (0x00080000UL) +#define MPU_CR_FMPUE_POS (23U) +#define MPU_CR_FMPUE (0x00800000UL) + +/* Bit definition for MPU_SR register */ +#define MPU_SR_SMPU2EAF_POS (0U) +#define MPU_SR_SMPU2EAF (0x00000001UL) +#define MPU_SR_SMPU1EAF_POS (8U) +#define MPU_SR_SMPU1EAF (0x00000100UL) +#define MPU_SR_FMPUEAF_POS (16U) +#define MPU_SR_FMPUEAF (0x00010000UL) + +/* Bit definition for MPU_ECLR register */ +#define MPU_ECLR_SMPU2ECLR_POS (0U) +#define MPU_ECLR_SMPU2ECLR (0x00000001UL) +#define MPU_ECLR_SMPU1ECLR_POS (8U) +#define MPU_ECLR_SMPU1ECLR (0x00000100UL) +#define MPU_ECLR_FMPUECLR_POS (16U) +#define MPU_ECLR_FMPUECLR (0x00010000UL) + +/* Bit definition for MPU_WP register */ +#define MPU_WP_MPUWE_POS (0U) +#define MPU_WP_MPUWE (0x00000001UL) +#define MPU_WP_WKEY_POS (1U) +#define MPU_WP_WKEY (0x0000FFFEUL) + +/* Bit definition for MPU_IPPR register */ +#define MPU_IPPR_AESRDP_POS (0U) +#define MPU_IPPR_AESRDP (0x00000001UL) +#define MPU_IPPR_AESWRP_POS (1U) +#define MPU_IPPR_AESWRP (0x00000002UL) +#define MPU_IPPR_HASHRDP_POS (2U) +#define MPU_IPPR_HASHRDP (0x00000004UL) +#define MPU_IPPR_HASHWRP_POS (3U) +#define MPU_IPPR_HASHWRP (0x00000008UL) +#define MPU_IPPR_TRNGRDP_POS (4U) +#define MPU_IPPR_TRNGRDP (0x00000010UL) +#define MPU_IPPR_TRNGWRP_POS (5U) +#define MPU_IPPR_TRNGWRP (0x00000020UL) +#define MPU_IPPR_CRCRDP_POS (6U) +#define MPU_IPPR_CRCRDP (0x00000040UL) +#define MPU_IPPR_CRCWRP_POS (7U) +#define MPU_IPPR_CRCWRP (0x00000080UL) +#define MPU_IPPR_EFMRDP_POS (8U) +#define MPU_IPPR_EFMRDP (0x00000100UL) +#define MPU_IPPR_EFMWRP_POS (9U) +#define MPU_IPPR_EFMWRP (0x00000200UL) +#define MPU_IPPR_WDTRDP_POS (12U) +#define MPU_IPPR_WDTRDP (0x00001000UL) +#define MPU_IPPR_WDTWRP_POS (13U) +#define MPU_IPPR_WDTWRP (0x00002000UL) +#define MPU_IPPR_SWDTRDP_POS (14U) +#define MPU_IPPR_SWDTRDP (0x00004000UL) +#define MPU_IPPR_SWDTWRP_POS (15U) +#define MPU_IPPR_SWDTWRP (0x00008000UL) +#define MPU_IPPR_BKSRAMRDP_POS (16U) +#define MPU_IPPR_BKSRAMRDP (0x00010000UL) +#define MPU_IPPR_BKSRAMWRP_POS (17U) +#define MPU_IPPR_BKSRAMWRP (0x00020000UL) +#define MPU_IPPR_RTCRDP_POS (18U) +#define MPU_IPPR_RTCRDP (0x00040000UL) +#define MPU_IPPR_RTCWRP_POS (19U) +#define MPU_IPPR_RTCWRP (0x00080000UL) +#define MPU_IPPR_DMPURDP_POS (20U) +#define MPU_IPPR_DMPURDP (0x00100000UL) +#define MPU_IPPR_DMPUWRP_POS (21U) +#define MPU_IPPR_DMPUWRP (0x00200000UL) +#define MPU_IPPR_SRAMCRDP_POS (22U) +#define MPU_IPPR_SRAMCRDP (0x00400000UL) +#define MPU_IPPR_SRAMCWRP_POS (23U) +#define MPU_IPPR_SRAMCWRP (0x00800000UL) +#define MPU_IPPR_INTCRDP_POS (24U) +#define MPU_IPPR_INTCRDP (0x01000000UL) +#define MPU_IPPR_INTCWRP_POS (25U) +#define MPU_IPPR_INTCWRP (0x02000000UL) +#define MPU_IPPR_SYSCRDP_POS (26U) +#define MPU_IPPR_SYSCRDP (0x04000000UL) +#define MPU_IPPR_SYSCWRP_POS (27U) +#define MPU_IPPR_SYSCWRP (0x08000000UL) +#define MPU_IPPR_MSTPRDP_POS (28U) +#define MPU_IPPR_MSTPRDP (0x10000000UL) +#define MPU_IPPR_MSTPWRP_POS (29U) +#define MPU_IPPR_MSTPWRP (0x20000000UL) +#define MPU_IPPR_BUSERRE_POS (31U) +#define MPU_IPPR_BUSERRE (0x80000000UL) + +/******************************************************************************* + Bit definition for Peripheral OTS +*******************************************************************************/ +/* Bit definition for OTS_CTL register */ +#define OTS_CTL_OTSST_POS (0U) +#define OTS_CTL_OTSST (0x0001U) +#define OTS_CTL_OTSCK_POS (1U) +#define OTS_CTL_OTSCK (0x0002U) +#define OTS_CTL_OTSIE_POS (2U) +#define OTS_CTL_OTSIE (0x0004U) +#define OTS_CTL_TSSTP_POS (3U) +#define OTS_CTL_TSSTP (0x0008U) + +/* Bit definition for OTS_DR1 register */ +#define OTS_DR1 (0xFFFFU) + +/* Bit definition for OTS_DR2 register */ +#define OTS_DR2 (0xFFFFU) + +/* Bit definition for OTS_ECR register */ +#define OTS_ECR (0xFFFFU) + +/******************************************************************************* + Bit definition for Peripheral PERIC +*******************************************************************************/ +/* Bit definition for PERIC_USBFS_SYCTLREG register */ +#define PERIC_USBFS_SYCTLREG_DFB_POS (0U) +#define PERIC_USBFS_SYCTLREG_DFB (0x00000001UL) +#define PERIC_USBFS_SYCTLREG_SOFEN_POS (1U) +#define PERIC_USBFS_SYCTLREG_SOFEN (0x00000002UL) + +/* Bit definition for PERIC_SDIOC_SYCTLREG register */ +#define PERIC_SDIOC_SYCTLREG_SELMMC1_POS (1U) +#define PERIC_SDIOC_SYCTLREG_SELMMC1 (0x00000002UL) +#define PERIC_SDIOC_SYCTLREG_SELMMC2_POS (3U) +#define PERIC_SDIOC_SYCTLREG_SELMMC2 (0x00000008UL) + +/******************************************************************************* + Bit definition for Peripheral PWC +*******************************************************************************/ +/* Bit definition for PWC_FCG0 register */ +#define PWC_FCG0_SRAMH_POS (0U) +#define PWC_FCG0_SRAMH (0x00000001UL) +#define PWC_FCG0_SRAM12_POS (4U) +#define PWC_FCG0_SRAM12 (0x00000010UL) +#define PWC_FCG0_SRAM3_POS (8U) +#define PWC_FCG0_SRAM3 (0x00000100UL) +#define PWC_FCG0_SRAMRET_POS (10U) +#define PWC_FCG0_SRAMRET (0x00000400UL) +#define PWC_FCG0_DMA1_POS (14U) +#define PWC_FCG0_DMA1 (0x00004000UL) +#define PWC_FCG0_DMA2_POS (15U) +#define PWC_FCG0_DMA2 (0x00008000UL) +#define PWC_FCG0_FCM_POS (16U) +#define PWC_FCG0_FCM (0x00010000UL) +#define PWC_FCG0_AOS_POS (17U) +#define PWC_FCG0_AOS (0x00020000UL) +#define PWC_FCG0_AES_POS (20U) +#define PWC_FCG0_AES (0x00100000UL) +#define PWC_FCG0_HASH_POS (21U) +#define PWC_FCG0_HASH (0x00200000UL) +#define PWC_FCG0_TRNG_POS (22U) +#define PWC_FCG0_TRNG (0x00400000UL) +#define PWC_FCG0_CRC_POS (23U) +#define PWC_FCG0_CRC (0x00800000UL) +#define PWC_FCG0_DCU1_POS (24U) +#define PWC_FCG0_DCU1 (0x01000000UL) +#define PWC_FCG0_DCU2_POS (25U) +#define PWC_FCG0_DCU2 (0x02000000UL) +#define PWC_FCG0_DCU3_POS (26U) +#define PWC_FCG0_DCU3 (0x04000000UL) +#define PWC_FCG0_DCU4_POS (27U) +#define PWC_FCG0_DCU4 (0x08000000UL) +#define PWC_FCG0_KEY_POS (31U) +#define PWC_FCG0_KEY (0x80000000UL) + +/* Bit definition for PWC_FCG1 register */ +#define PWC_FCG1_CAN_POS (0U) +#define PWC_FCG1_CAN (0x00000001UL) +#define PWC_FCG1_QSPI_POS (3U) +#define PWC_FCG1_QSPI (0x00000008UL) +#define PWC_FCG1_I2C1_POS (4U) +#define PWC_FCG1_I2C1 (0x00000010UL) +#define PWC_FCG1_I2C2_POS (5U) +#define PWC_FCG1_I2C2 (0x00000020UL) +#define PWC_FCG1_I2C3_POS (6U) +#define PWC_FCG1_I2C3 (0x00000040UL) +#define PWC_FCG1_USBFS_POS (8U) +#define PWC_FCG1_USBFS (0x00000100UL) +#define PWC_FCG1_SDIOC1_POS (10U) +#define PWC_FCG1_SDIOC1 (0x00000400UL) +#define PWC_FCG1_SDIOC2_POS (11U) +#define PWC_FCG1_SDIOC2 (0x00000800UL) +#define PWC_FCG1_I2S1_POS (12U) +#define PWC_FCG1_I2S1 (0x00001000UL) +#define PWC_FCG1_I2S2_POS (13U) +#define PWC_FCG1_I2S2 (0x00002000UL) +#define PWC_FCG1_I2S3_POS (14U) +#define PWC_FCG1_I2S3 (0x00004000UL) +#define PWC_FCG1_I2S4_POS (15U) +#define PWC_FCG1_I2S4 (0x00008000UL) +#define PWC_FCG1_SPI1_POS (16U) +#define PWC_FCG1_SPI1 (0x00010000UL) +#define PWC_FCG1_SPI2_POS (17U) +#define PWC_FCG1_SPI2 (0x00020000UL) +#define PWC_FCG1_SPI3_POS (18U) +#define PWC_FCG1_SPI3 (0x00040000UL) +#define PWC_FCG1_SPI4_POS (19U) +#define PWC_FCG1_SPI4 (0x00080000UL) +#define PWC_FCG1_USART1_POS (24U) +#define PWC_FCG1_USART1 (0x01000000UL) +#define PWC_FCG1_USART2_POS (25U) +#define PWC_FCG1_USART2 (0x02000000UL) +#define PWC_FCG1_USART3_POS (26U) +#define PWC_FCG1_USART3 (0x04000000UL) +#define PWC_FCG1_USART4_POS (27U) +#define PWC_FCG1_USART4 (0x08000000UL) + +/* Bit definition for PWC_FCG2 register */ +#define PWC_FCG2_TIMER0_1_POS (0U) +#define PWC_FCG2_TIMER0_1 (0x00000001UL) +#define PWC_FCG2_TIMER0_2_POS (1U) +#define PWC_FCG2_TIMER0_2 (0x00000002UL) +#define PWC_FCG2_TIMERA_1_POS (2U) +#define PWC_FCG2_TIMERA_1 (0x00000004UL) +#define PWC_FCG2_TIMERA_2_POS (3U) +#define PWC_FCG2_TIMERA_2 (0x00000008UL) +#define PWC_FCG2_TIMERA_3_POS (4U) +#define PWC_FCG2_TIMERA_3 (0x00000010UL) +#define PWC_FCG2_TIMERA_4_POS (5U) +#define PWC_FCG2_TIMERA_4 (0x00000020UL) +#define PWC_FCG2_TIMERA_5_POS (6U) +#define PWC_FCG2_TIMERA_5 (0x00000040UL) +#define PWC_FCG2_TIMERA_6_POS (7U) +#define PWC_FCG2_TIMERA_6 (0x00000080UL) +#define PWC_FCG2_TIMER4_1_POS (8U) +#define PWC_FCG2_TIMER4_1 (0x00000100UL) +#define PWC_FCG2_TIMER4_2_POS (9U) +#define PWC_FCG2_TIMER4_2 (0x00000200UL) +#define PWC_FCG2_TIMER4_3_POS (10U) +#define PWC_FCG2_TIMER4_3 (0x00000400UL) +#define PWC_FCG2_EMB_POS (15U) +#define PWC_FCG2_EMB (0x00008000UL) +#define PWC_FCG2_TIMER6_1_POS (16U) +#define PWC_FCG2_TIMER6_1 (0x00010000UL) +#define PWC_FCG2_TIMER6_2_POS (17U) +#define PWC_FCG2_TIMER6_2 (0x00020000UL) +#define PWC_FCG2_TIMER6_3_POS (18U) +#define PWC_FCG2_TIMER6_3 (0x00040000UL) + +/* Bit definition for PWC_FCG3 register */ +#define PWC_FCG3_ADC1_POS (0U) +#define PWC_FCG3_ADC1 (0x00000001UL) +#define PWC_FCG3_ADC2_POS (1U) +#define PWC_FCG3_ADC2 (0x00000002UL) +#define PWC_FCG3_CMP_POS (8U) +#define PWC_FCG3_CMP (0x00000100UL) +#define PWC_FCG3_OTS_POS (12U) +#define PWC_FCG3_OTS (0x00001000UL) + +/* Bit definition for PWC_FCG0PC register */ +#define PWC_FCG0PC_PRT0_POS (0U) +#define PWC_FCG0PC_PRT0 (0x00000001UL) +#define PWC_FCG0PC_FCG0PCWE_POS (16U) +#define PWC_FCG0PC_FCG0PCWE (0xFFFF0000UL) + +/* Bit definition for PWC_WKTCR register */ +#define PWC_WKTCR_WKTMCMP_POS (0U) +#define PWC_WKTCR_WKTMCMP (0x0FFFU) +#define PWC_WKTCR_WKOVF_POS (12U) +#define PWC_WKTCR_WKOVF (0x1000U) +#define PWC_WKTCR_WKCKS_POS (13U) +#define PWC_WKTCR_WKCKS (0x6000U) +#define PWC_WKTCR_WKCKS_0 (0x2000U) +#define PWC_WKTCR_WKCKS_1 (0x4000U) +#define PWC_WKTCR_WKTCE_POS (15U) +#define PWC_WKTCR_WKTCE (0x8000U) + +/* Bit definition for PWC_STPMCR register */ +#define PWC_STPMCR_FLNWT_POS (0U) +#define PWC_STPMCR_FLNWT (0x0001U) +#define PWC_STPMCR_CKSMRC_POS (1U) +#define PWC_STPMCR_CKSMRC (0x0002U) +#define PWC_STPMCR_STOP_POS (15U) +#define PWC_STPMCR_STOP (0x8000U) + +/* Bit definition for PWC_RAMPC0 register */ +#define PWC_RAMPC0_RAMPDC0_POS (0U) +#define PWC_RAMPC0_RAMPDC0 (0x00000001UL) +#define PWC_RAMPC0_RAMPDC1_POS (1U) +#define PWC_RAMPC0_RAMPDC1 (0x00000002UL) +#define PWC_RAMPC0_RAMPDC2_POS (2U) +#define PWC_RAMPC0_RAMPDC2 (0x00000004UL) +#define PWC_RAMPC0_RAMPDC3_POS (3U) +#define PWC_RAMPC0_RAMPDC3 (0x00000008UL) +#define PWC_RAMPC0_RAMPDC4_POS (4U) +#define PWC_RAMPC0_RAMPDC4 (0x00000010UL) +#define PWC_RAMPC0_RAMPDC5_POS (5U) +#define PWC_RAMPC0_RAMPDC5 (0x00000020UL) +#define PWC_RAMPC0_RAMPDC6_POS (6U) +#define PWC_RAMPC0_RAMPDC6 (0x00000040UL) +#define PWC_RAMPC0_RAMPDC7_POS (7U) +#define PWC_RAMPC0_RAMPDC7 (0x00000080UL) +#define PWC_RAMPC0_RAMPDC8_POS (8U) +#define PWC_RAMPC0_RAMPDC8 (0x00000100UL) + +/* Bit definition for PWC_RAMOPM register */ +#define PWC_RAMOPM (0xFFFFU) + +/* Bit definition for PWC_PVDICR register */ +#define PWC_PVDICR_PVD1NMIS_POS (0U) +#define PWC_PVDICR_PVD1NMIS (0x01U) +#define PWC_PVDICR_PVD2NMIS_POS (4U) +#define PWC_PVDICR_PVD2NMIS (0x10U) + +/* Bit definition for PWC_PVDDSR register */ +#define PWC_PVDDSR_PVD1MON_POS (0U) +#define PWC_PVDDSR_PVD1MON (0x01U) +#define PWC_PVDDSR_PVD1DETFLG_POS (1U) +#define PWC_PVDDSR_PVD1DETFLG (0x02U) +#define PWC_PVDDSR_PVD2MON_POS (4U) +#define PWC_PVDDSR_PVD2MON (0x10U) +#define PWC_PVDDSR_PVD2DETFLG_POS (5U) +#define PWC_PVDDSR_PVD2DETFLG (0x20U) + +/* Bit definition for PWC_FPRC register */ +#define PWC_FPRC_FPRCB0_POS (0U) +#define PWC_FPRC_FPRCB0 (0x0001U) +#define PWC_FPRC_FPRCB1_POS (1U) +#define PWC_FPRC_FPRCB1 (0x0002U) +#define PWC_FPRC_FPRCB2_POS (2U) +#define PWC_FPRC_FPRCB2 (0x0004U) +#define PWC_FPRC_FPRCB3_POS (3U) +#define PWC_FPRC_FPRCB3 (0x0008U) +#define PWC_FPRC_FPRCWE_POS (8U) +#define PWC_FPRC_FPRCWE (0xFF00U) + +/* Bit definition for PWC_PWRC0 register */ +#define PWC_PWRC0_PDMDS_POS (0U) +#define PWC_PWRC0_PDMDS (0x03U) +#define PWC_PWRC0_PDMDS_0 (0x01U) +#define PWC_PWRC0_PDMDS_1 (0x02U) +#define PWC_PWRC0_VVDRSD_POS (2U) +#define PWC_PWRC0_VVDRSD (0x04U) +#define PWC_PWRC0_RETRAMSD_POS (3U) +#define PWC_PWRC0_RETRAMSD (0x08U) +#define PWC_PWRC0_IORTN_POS (4U) +#define PWC_PWRC0_IORTN (0x30U) +#define PWC_PWRC0_IORTN_0 (0x10U) +#define PWC_PWRC0_IORTN_1 (0x20U) +#define PWC_PWRC0_PWDN_POS (7U) +#define PWC_PWRC0_PWDN (0x80U) + +/* Bit definition for PWC_PWRC1 register */ +#define PWC_PWRC1_VPLLSD_POS (0U) +#define PWC_PWRC1_VPLLSD (0x01U) +#define PWC_PWRC1_VHRCSD_POS (1U) +#define PWC_PWRC1_VHRCSD (0x02U) +#define PWC_PWRC1_STPDAS_POS (6U) +#define PWC_PWRC1_STPDAS (0xC0U) +#define PWC_PWRC1_STPDAS_0 (0x40U) +#define PWC_PWRC1_STPDAS_1 (0x80U) + +/* Bit definition for PWC_PWRC2 register */ +#define PWC_PWRC2_DDAS_POS (0U) +#define PWC_PWRC2_DDAS (0x0FU) +#define PWC_PWRC2_DDAS_0 (0x01U) +#define PWC_PWRC2_DDAS_1 (0x02U) +#define PWC_PWRC2_DDAS_2 (0x04U) +#define PWC_PWRC2_DDAS_3 (0x08U) +#define PWC_PWRC2_DVS_POS (4U) +#define PWC_PWRC2_DVS (0x30U) +#define PWC_PWRC2_DVS_0 (0x10U) +#define PWC_PWRC2_DVS_1 (0x20U) + +/* Bit definition for PWC_PWRC3 register */ +#define PWC_PWRC3_PDTS_POS (2U) +#define PWC_PWRC3_PDTS (0x04U) + +/* Bit definition for PWC_PDWKE0 register */ +#define PWC_PDWKE0_WKE00_POS (0U) +#define PWC_PDWKE0_WKE00 (0x01U) +#define PWC_PDWKE0_WKE01_POS (1U) +#define PWC_PDWKE0_WKE01 (0x02U) +#define PWC_PDWKE0_WKE02_POS (2U) +#define PWC_PDWKE0_WKE02 (0x04U) +#define PWC_PDWKE0_WKE03_POS (3U) +#define PWC_PDWKE0_WKE03 (0x08U) +#define PWC_PDWKE0_WKE10_POS (4U) +#define PWC_PDWKE0_WKE10 (0x10U) +#define PWC_PDWKE0_WKE11_POS (5U) +#define PWC_PDWKE0_WKE11 (0x20U) +#define PWC_PDWKE0_WKE12_POS (6U) +#define PWC_PDWKE0_WKE12 (0x40U) +#define PWC_PDWKE0_WKE13_POS (7U) +#define PWC_PDWKE0_WKE13 (0x80U) + +/* Bit definition for PWC_PDWKE1 register */ +#define PWC_PDWKE1_WKE20_POS (0U) +#define PWC_PDWKE1_WKE20 (0x01U) +#define PWC_PDWKE1_WKE21_POS (1U) +#define PWC_PDWKE1_WKE21 (0x02U) +#define PWC_PDWKE1_WKE22_POS (2U) +#define PWC_PDWKE1_WKE22 (0x04U) +#define PWC_PDWKE1_WKE23_POS (3U) +#define PWC_PDWKE1_WKE23 (0x08U) +#define PWC_PDWKE1_WKE30_POS (4U) +#define PWC_PDWKE1_WKE30 (0x10U) +#define PWC_PDWKE1_WKE31_POS (5U) +#define PWC_PDWKE1_WKE31 (0x20U) +#define PWC_PDWKE1_WKE32_POS (6U) +#define PWC_PDWKE1_WKE32 (0x40U) +#define PWC_PDWKE1_WKE33_POS (7U) +#define PWC_PDWKE1_WKE33 (0x80U) + +/* Bit definition for PWC_PDWKE2 register */ +#define PWC_PDWKE2_VD1WKE_POS (0U) +#define PWC_PDWKE2_VD1WKE (0x01U) +#define PWC_PDWKE2_VD2WKE_POS (1U) +#define PWC_PDWKE2_VD2WKE (0x02U) +#define PWC_PDWKE2_NMIWKE_POS (2U) +#define PWC_PDWKE2_NMIWKE (0x04U) +#define PWC_PDWKE2_RTCPRDWKE_POS (4U) +#define PWC_PDWKE2_RTCPRDWKE (0x10U) +#define PWC_PDWKE2_RTCALMWKE_POS (5U) +#define PWC_PDWKE2_RTCALMWKE (0x20U) +#define PWC_PDWKE2_WKTMWKE_POS (7U) +#define PWC_PDWKE2_WKTMWKE (0x80U) + +/* Bit definition for PWC_PDWKES register */ +#define PWC_PDWKES_WK0EGS_POS (0U) +#define PWC_PDWKES_WK0EGS (0x01U) +#define PWC_PDWKES_WK1EGS_POS (1U) +#define PWC_PDWKES_WK1EGS (0x02U) +#define PWC_PDWKES_WK2EGS_POS (2U) +#define PWC_PDWKES_WK2EGS (0x04U) +#define PWC_PDWKES_WK3EGS_POS (3U) +#define PWC_PDWKES_WK3EGS (0x08U) +#define PWC_PDWKES_VD1EGS_POS (4U) +#define PWC_PDWKES_VD1EGS (0x10U) +#define PWC_PDWKES_VD2EGS_POS (5U) +#define PWC_PDWKES_VD2EGS (0x20U) +#define PWC_PDWKES_NMIEGS_POS (6U) +#define PWC_PDWKES_NMIEGS (0x40U) + +/* Bit definition for PWC_PDWKF0 register */ +#define PWC_PDWKF0_PTWK0F_POS (0U) +#define PWC_PDWKF0_PTWK0F (0x01U) +#define PWC_PDWKF0_PTWK1F_POS (1U) +#define PWC_PDWKF0_PTWK1F (0x02U) +#define PWC_PDWKF0_PTWK2F_POS (2U) +#define PWC_PDWKF0_PTWK2F (0x04U) +#define PWC_PDWKF0_PTWK3F_POS (3U) +#define PWC_PDWKF0_PTWK3F (0x08U) +#define PWC_PDWKF0_VD1WKF_POS (4U) +#define PWC_PDWKF0_VD1WKF (0x10U) +#define PWC_PDWKF0_VD2WKF_POS (5U) +#define PWC_PDWKF0_VD2WKF (0x20U) +#define PWC_PDWKF0_NMIWKF_POS (6U) +#define PWC_PDWKF0_NMIWKF (0x40U) + +/* Bit definition for PWC_PDWKF1 register */ +#define PWC_PDWKF1_RTCPRDWKF_POS (4U) +#define PWC_PDWKF1_RTCPRDWKF (0x10U) +#define PWC_PDWKF1_RTCALMWKF_POS (5U) +#define PWC_PDWKF1_RTCALMWKF (0x20U) +#define PWC_PDWKF1_WKTMWKF_POS (7U) +#define PWC_PDWKF1_WKTMWKF (0x80U) + +/* Bit definition for PWC_PWCMR register */ +#define PWC_PWCMR_ADBUFE_POS (7U) +#define PWC_PWCMR_ADBUFE (0x80U) + +/* Bit definition for PWC_MDSWCR register */ +#define PWC_MDSWCR (0xFFU) + +/* Bit definition for PWC_PVDCR0 register */ +#define PWC_PVDCR0_EXVCCINEN_POS (0U) +#define PWC_PVDCR0_EXVCCINEN (0x01U) +#define PWC_PVDCR0_PVD1EN_POS (5U) +#define PWC_PVDCR0_PVD1EN (0x20U) +#define PWC_PVDCR0_PVD2EN_POS (6U) +#define PWC_PVDCR0_PVD2EN (0x40U) + +/* Bit definition for PWC_PVDCR1 register */ +#define PWC_PVDCR1_PVD1IRE_POS (0U) +#define PWC_PVDCR1_PVD1IRE (0x01U) +#define PWC_PVDCR1_PVD1IRS_POS (1U) +#define PWC_PVDCR1_PVD1IRS (0x02U) +#define PWC_PVDCR1_PVD1CMPOE_POS (2U) +#define PWC_PVDCR1_PVD1CMPOE (0x04U) +#define PWC_PVDCR1_PVD2IRE_POS (4U) +#define PWC_PVDCR1_PVD2IRE (0x10U) +#define PWC_PVDCR1_PVD2IRS_POS (5U) +#define PWC_PVDCR1_PVD2IRS (0x20U) +#define PWC_PVDCR1_PVD2CMPOE_POS (6U) +#define PWC_PVDCR1_PVD2CMPOE (0x40U) + +/* Bit definition for PWC_PVDFCR register */ +#define PWC_PVDFCR_PVD1NFDIS_POS (0U) +#define PWC_PVDFCR_PVD1NFDIS (0x01U) +#define PWC_PVDFCR_PVD1NFCKS_POS (1U) +#define PWC_PVDFCR_PVD1NFCKS (0x06U) +#define PWC_PVDFCR_PVD1NFCKS_0 (0x02U) +#define PWC_PVDFCR_PVD1NFCKS_1 (0x04U) +#define PWC_PVDFCR_PVD2NFDIS_POS (4U) +#define PWC_PVDFCR_PVD2NFDIS (0x10U) +#define PWC_PVDFCR_PVD2NFCKS_POS (5U) +#define PWC_PVDFCR_PVD2NFCKS (0x60U) +#define PWC_PVDFCR_PVD2NFCKS_0 (0x20U) +#define PWC_PVDFCR_PVD2NFCKS_1 (0x40U) + +/* Bit definition for PWC_PVDLCR register */ +#define PWC_PVDLCR_PVD1LVL_POS (0U) +#define PWC_PVDLCR_PVD1LVL (0x07U) +#define PWC_PVDLCR_PVD1LVL_0 (0x01U) +#define PWC_PVDLCR_PVD1LVL_1 (0x02U) +#define PWC_PVDLCR_PVD1LVL_2 (0x04U) +#define PWC_PVDLCR_PVD2LVL_POS (4U) +#define PWC_PVDLCR_PVD2LVL (0x70U) +#define PWC_PVDLCR_PVD2LVL_0 (0x10U) +#define PWC_PVDLCR_PVD2LVL_1 (0x20U) +#define PWC_PVDLCR_PVD2LVL_2 (0x40U) + +/* Bit definition for PWC_XTAL32CS register */ +#define PWC_XTAL32CS_CSDIS_POS (7U) +#define PWC_XTAL32CS_CSDIS (0x80U) + +/******************************************************************************* + Bit definition for Peripheral QSPI +*******************************************************************************/ +/* Bit definition for QSPI_CR register */ +#define QSPI_CR_MDSEL_POS (0U) +#define QSPI_CR_MDSEL (0x00000007UL) +#define QSPI_CR_PFE_POS (3U) +#define QSPI_CR_PFE (0x00000008UL) +#define QSPI_CR_PFSAE_POS (4U) +#define QSPI_CR_PFSAE (0x00000010UL) +#define QSPI_CR_DCOME_POS (5U) +#define QSPI_CR_DCOME (0x00000020UL) +#define QSPI_CR_XIPE_POS (6U) +#define QSPI_CR_XIPE (0x00000040UL) +#define QSPI_CR_SPIMD3_POS (7U) +#define QSPI_CR_SPIMD3 (0x00000080UL) +#define QSPI_CR_IPRSL_POS (8U) +#define QSPI_CR_IPRSL (0x00000300UL) +#define QSPI_CR_IPRSL_0 (0x00000100UL) +#define QSPI_CR_IPRSL_1 (0x00000200UL) +#define QSPI_CR_APRSL_POS (10U) +#define QSPI_CR_APRSL (0x00000C00UL) +#define QSPI_CR_APRSL_0 (0x00000400UL) +#define QSPI_CR_APRSL_1 (0x00000800UL) +#define QSPI_CR_DPRSL_POS (12U) +#define QSPI_CR_DPRSL (0x00003000UL) +#define QSPI_CR_DPRSL_0 (0x00001000UL) +#define QSPI_CR_DPRSL_1 (0x00002000UL) +#define QSPI_CR_DIV_POS (16U) +#define QSPI_CR_DIV (0x003F0000UL) + +/* Bit definition for QSPI_CSCR register */ +#define QSPI_CSCR_SSHW_POS (0U) +#define QSPI_CSCR_SSHW (0x0000000FUL) +#define QSPI_CSCR_SSNW_POS (4U) +#define QSPI_CSCR_SSNW (0x00000030UL) +#define QSPI_CSCR_SSNW_0 (0x00000010UL) +#define QSPI_CSCR_SSNW_1 (0x00000020UL) + +/* Bit definition for QSPI_FCR register */ +#define QSPI_FCR_AWSL_POS (0U) +#define QSPI_FCR_AWSL (0x00000003UL) +#define QSPI_FCR_AWSL_0 (0x00000001UL) +#define QSPI_FCR_AWSL_1 (0x00000002UL) +#define QSPI_FCR_FOUR_BIC_POS (2U) +#define QSPI_FCR_FOUR_BIC (0x00000004UL) +#define QSPI_FCR_SSNHD_POS (4U) +#define QSPI_FCR_SSNHD (0x00000010UL) +#define QSPI_FCR_SSNLD_POS (5U) +#define QSPI_FCR_SSNLD (0x00000020UL) +#define QSPI_FCR_WPOL_POS (6U) +#define QSPI_FCR_WPOL (0x00000040UL) +#define QSPI_FCR_DMCYCN_POS (8U) +#define QSPI_FCR_DMCYCN (0x00000F00UL) +#define QSPI_FCR_DUTY_POS (15U) +#define QSPI_FCR_DUTY (0x00008000UL) + +/* Bit definition for QSPI_SR register */ +#define QSPI_SR_BUSY_POS (0U) +#define QSPI_SR_BUSY (0x00000001UL) +#define QSPI_SR_XIPF_POS (6U) +#define QSPI_SR_XIPF (0x00000040UL) +#define QSPI_SR_RAER_POS (7U) +#define QSPI_SR_RAER (0x00000080UL) +#define QSPI_SR_PFNUM_POS (8U) +#define QSPI_SR_PFNUM (0x00001F00UL) +#define QSPI_SR_PFFUL_POS (14U) +#define QSPI_SR_PFFUL (0x00004000UL) +#define QSPI_SR_PFAN_POS (15U) +#define QSPI_SR_PFAN (0x00008000UL) + +/* Bit definition for QSPI_DCOM register */ +#define QSPI_DCOM_DCOM (0x000000FFUL) + +/* Bit definition for QSPI_CCMD register */ +#define QSPI_CCMD_RIC (0x000000FFUL) + +/* Bit definition for QSPI_XCMD register */ +#define QSPI_XCMD_XIPMC (0x000000FFUL) + +/* Bit definition for QSPI_CLR register */ +#define QSPI_CLR_RAERCLR_POS (7U) +#define QSPI_CLR_RAERCLR (0x00000080UL) + +/* Bit definition for QSPI_EXAR register */ +#define QSPI_EXAR_EXADR_POS (26U) +#define QSPI_EXAR_EXADR (0xFC000000UL) + +/******************************************************************************* + Bit definition for Peripheral RMU +*******************************************************************************/ +/* Bit definition for RMU_RSTF0 register */ +#define RMU_RSTF0_PORF_POS (0U) +#define RMU_RSTF0_PORF (0x0001U) +#define RMU_RSTF0_PINRF_POS (1U) +#define RMU_RSTF0_PINRF (0x0002U) +#define RMU_RSTF0_BORF_POS (2U) +#define RMU_RSTF0_BORF (0x0004U) +#define RMU_RSTF0_PVD1RF_POS (3U) +#define RMU_RSTF0_PVD1RF (0x0008U) +#define RMU_RSTF0_PVD2RF_POS (4U) +#define RMU_RSTF0_PVD2RF (0x0010U) +#define RMU_RSTF0_WDRF_POS (5U) +#define RMU_RSTF0_WDRF (0x0020U) +#define RMU_RSTF0_SWDRF_POS (6U) +#define RMU_RSTF0_SWDRF (0x0040U) +#define RMU_RSTF0_PDRF_POS (7U) +#define RMU_RSTF0_PDRF (0x0080U) +#define RMU_RSTF0_SWRF_POS (8U) +#define RMU_RSTF0_SWRF (0x0100U) +#define RMU_RSTF0_MPUERF_POS (9U) +#define RMU_RSTF0_MPUERF (0x0200U) +#define RMU_RSTF0_RAPERF_POS (10U) +#define RMU_RSTF0_RAPERF (0x0400U) +#define RMU_RSTF0_RAECRF_POS (11U) +#define RMU_RSTF0_RAECRF (0x0800U) +#define RMU_RSTF0_CKFERF_POS (12U) +#define RMU_RSTF0_CKFERF (0x1000U) +#define RMU_RSTF0_XTALERF_POS (13U) +#define RMU_RSTF0_XTALERF (0x2000U) +#define RMU_RSTF0_MULTIRF_POS (14U) +#define RMU_RSTF0_MULTIRF (0x4000U) +#define RMU_RSTF0_CLRF_POS (15U) +#define RMU_RSTF0_CLRF (0x8000U) + +/******************************************************************************* + Bit definition for Peripheral RTC +*******************************************************************************/ +/* Bit definition for RTC_CR0 register */ +#define RTC_CR0_RESET (0x01U) + +/* Bit definition for RTC_CR1 register */ +#define RTC_CR1_PRDS_POS (0U) +#define RTC_CR1_PRDS (0x07U) +#define RTC_CR1_AMPM_POS (3U) +#define RTC_CR1_AMPM (0x08U) +#define RTC_CR1_ALMFCLR_POS (4U) +#define RTC_CR1_ALMFCLR (0x10U) +#define RTC_CR1_ONEHZOE_POS (5U) +#define RTC_CR1_ONEHZOE (0x20U) +#define RTC_CR1_ONEHZSEL_POS (6U) +#define RTC_CR1_ONEHZSEL (0x40U) +#define RTC_CR1_START_POS (7U) +#define RTC_CR1_START (0x80U) + +/* Bit definition for RTC_CR2 register */ +#define RTC_CR2_RWREQ_POS (0U) +#define RTC_CR2_RWREQ (0x01U) +#define RTC_CR2_RWEN_POS (1U) +#define RTC_CR2_RWEN (0x02U) +#define RTC_CR2_ALMF_POS (3U) +#define RTC_CR2_ALMF (0x08U) +#define RTC_CR2_PRDIE_POS (5U) +#define RTC_CR2_PRDIE (0x20U) +#define RTC_CR2_ALMIE_POS (6U) +#define RTC_CR2_ALMIE (0x40U) +#define RTC_CR2_ALME_POS (7U) +#define RTC_CR2_ALME (0x80U) + +/* Bit definition for RTC_CR3 register */ +#define RTC_CR3_LRCEN_POS (4U) +#define RTC_CR3_LRCEN (0x10U) +#define RTC_CR3_RCKSEL_POS (7U) +#define RTC_CR3_RCKSEL (0x80U) + +/* Bit definition for RTC_SEC register */ +#define RTC_SEC_SECU_POS (0U) +#define RTC_SEC_SECU (0x0FU) +#define RTC_SEC_SECD_POS (4U) +#define RTC_SEC_SECD (0x70U) + +/* Bit definition for RTC_MIN register */ +#define RTC_MIN_MINU_POS (0U) +#define RTC_MIN_MINU (0x0FU) +#define RTC_MIN_MIND_POS (4U) +#define RTC_MIN_MIND (0x70U) + +/* Bit definition for RTC_HOUR register */ +#define RTC_HOUR_HOURU_POS (0U) +#define RTC_HOUR_HOURU (0x0FU) +#define RTC_HOUR_HOURU_0 (0x01U) +#define RTC_HOUR_HOURU_1 (0x02U) +#define RTC_HOUR_HOURU_2 (0x04U) +#define RTC_HOUR_HOURU_3 (0x08U) +#define RTC_HOUR_HOURD_POS (4U) +#define RTC_HOUR_HOURD (0x30U) +#define RTC_HOUR_HOURD_0 (0x10U) +#define RTC_HOUR_HOURD_1 (0x20U) + +/* Bit definition for RTC_WEEK register */ +#define RTC_WEEK_WEEK (0x07U) + +/* Bit definition for RTC_DAY register */ +#define RTC_DAY_DAYU_POS (0U) +#define RTC_DAY_DAYU (0x0FU) +#define RTC_DAY_DAYD_POS (4U) +#define RTC_DAY_DAYD (0x30U) + +/* Bit definition for RTC_MON register */ +#define RTC_MON_MON (0x1FU) + +/* Bit definition for RTC_YEAR register */ +#define RTC_YEAR_YEARU_POS (0U) +#define RTC_YEAR_YEARU (0x0FU) +#define RTC_YEAR_YEARD_POS (4U) +#define RTC_YEAR_YEARD (0xF0U) + +/* Bit definition for RTC_ALMMIN register */ +#define RTC_ALMMIN_ALMMINU_POS (0U) +#define RTC_ALMMIN_ALMMINU (0x0FU) +#define RTC_ALMMIN_ALMMIND_POS (4U) +#define RTC_ALMMIN_ALMMIND (0x70U) + +/* Bit definition for RTC_ALMHOUR register */ +#define RTC_ALMHOUR_ALMHOURU_POS (0U) +#define RTC_ALMHOUR_ALMHOURU (0x0FU) +#define RTC_ALMHOUR_ALMHOURD_POS (4U) +#define RTC_ALMHOUR_ALMHOURD (0x30U) +#define RTC_ALMHOUR_ALMHOURD_0 (0x10U) +#define RTC_ALMHOUR_ALMHOURD_1 (0x20U) + +/* Bit definition for RTC_ALMWEEK register */ +#define RTC_ALMWEEK_ALMWEEK (0x7FU) +#define RTC_ALMWEEK_ALMWEEK_0 (0x01U) +#define RTC_ALMWEEK_ALMWEEK_1 (0x02U) +#define RTC_ALMWEEK_ALMWEEK_2 (0x04U) +#define RTC_ALMWEEK_ALMWEEK_3 (0x08U) +#define RTC_ALMWEEK_ALMWEEK_4 (0x10U) +#define RTC_ALMWEEK_ALMWEEK_5 (0x20U) +#define RTC_ALMWEEK_ALMWEEK_6 (0x40U) + +/* Bit definition for RTC_ERRCRH register */ +#define RTC_ERRCRH_COMP8_POS (0U) +#define RTC_ERRCRH_COMP8 (0x01U) +#define RTC_ERRCRH_COMPEN_POS (7U) +#define RTC_ERRCRH_COMPEN (0x80U) + +/* Bit definition for RTC_ERRCRL register */ +#define RTC_ERRCRL_COMP (0xFFU) + +/******************************************************************************* + Bit definition for Peripheral SDIOC +*******************************************************************************/ +/* Bit definition for SDIOC_BLKSIZE register */ +#define SDIOC_BLKSIZE_TBS (0x0FFFU) + +/* Bit definition for SDIOC_BLKCNT register */ +#define SDIOC_BLKCNT (0xFFFFU) + +/* Bit definition for SDIOC_ARG0 register */ +#define SDIOC_ARG0 (0xFFFFU) + +/* Bit definition for SDIOC_ARG1 register */ +#define SDIOC_ARG1 (0xFFFFU) + +/* Bit definition for SDIOC_TRANSMODE register */ +#define SDIOC_TRANSMODE_BCE_POS (1U) +#define SDIOC_TRANSMODE_BCE (0x0002U) +#define SDIOC_TRANSMODE_ATCEN_POS (2U) +#define SDIOC_TRANSMODE_ATCEN (0x000CU) +#define SDIOC_TRANSMODE_ATCEN_0 (0x0004U) +#define SDIOC_TRANSMODE_ATCEN_1 (0x0008U) +#define SDIOC_TRANSMODE_DDIR_POS (4U) +#define SDIOC_TRANSMODE_DDIR (0x0010U) +#define SDIOC_TRANSMODE_MULB_POS (5U) +#define SDIOC_TRANSMODE_MULB (0x0020U) + +/* Bit definition for SDIOC_CMD register */ +#define SDIOC_CMD_RESTYP_POS (0U) +#define SDIOC_CMD_RESTYP (0x0003U) +#define SDIOC_CMD_RESTYP_0 (0x0001U) +#define SDIOC_CMD_RESTYP_1 (0x0002U) +#define SDIOC_CMD_CCE_POS (3U) +#define SDIOC_CMD_CCE (0x0008U) +#define SDIOC_CMD_ICE_POS (4U) +#define SDIOC_CMD_ICE (0x0010U) +#define SDIOC_CMD_DAT_POS (5U) +#define SDIOC_CMD_DAT (0x0020U) +#define SDIOC_CMD_TYP_POS (6U) +#define SDIOC_CMD_TYP (0x00C0U) +#define SDIOC_CMD_TYP_0 (0x0040U) +#define SDIOC_CMD_TYP_1 (0x0080U) +#define SDIOC_CMD_IDX_POS (8U) +#define SDIOC_CMD_IDX (0x3F00U) + +/* Bit definition for SDIOC_RESP0 register */ +#define SDIOC_RESP0 (0xFFFFU) + +/* Bit definition for SDIOC_RESP1 register */ +#define SDIOC_RESP1 (0xFFFFU) + +/* Bit definition for SDIOC_RESP2 register */ +#define SDIOC_RESP2 (0xFFFFU) + +/* Bit definition for SDIOC_RESP3 register */ +#define SDIOC_RESP3 (0xFFFFU) + +/* Bit definition for SDIOC_RESP4 register */ +#define SDIOC_RESP4 (0xFFFFU) + +/* Bit definition for SDIOC_RESP5 register */ +#define SDIOC_RESP5 (0xFFFFU) + +/* Bit definition for SDIOC_RESP6 register */ +#define SDIOC_RESP6 (0xFFFFU) + +/* Bit definition for SDIOC_RESP7 register */ +#define SDIOC_RESP7 (0xFFFFU) + +/* Bit definition for SDIOC_BUF0 register */ +#define SDIOC_BUF0 (0xFFFFU) + +/* Bit definition for SDIOC_BUF1 register */ +#define SDIOC_BUF1 (0xFFFFU) + +/* Bit definition for SDIOC_PSTAT register */ +#define SDIOC_PSTAT_CIC_POS (0U) +#define SDIOC_PSTAT_CIC (0x00000001UL) +#define SDIOC_PSTAT_CID_POS (1U) +#define SDIOC_PSTAT_CID (0x00000002UL) +#define SDIOC_PSTAT_DA_POS (2U) +#define SDIOC_PSTAT_DA (0x00000004UL) +#define SDIOC_PSTAT_WTA_POS (8U) +#define SDIOC_PSTAT_WTA (0x00000100UL) +#define SDIOC_PSTAT_RTA_POS (9U) +#define SDIOC_PSTAT_RTA (0x00000200UL) +#define SDIOC_PSTAT_BWE_POS (10U) +#define SDIOC_PSTAT_BWE (0x00000400UL) +#define SDIOC_PSTAT_BRE_POS (11U) +#define SDIOC_PSTAT_BRE (0x00000800UL) +#define SDIOC_PSTAT_CIN_POS (16U) +#define SDIOC_PSTAT_CIN (0x00010000UL) +#define SDIOC_PSTAT_CSS_POS (17U) +#define SDIOC_PSTAT_CSS (0x00020000UL) +#define SDIOC_PSTAT_CDL_POS (18U) +#define SDIOC_PSTAT_CDL (0x00040000UL) +#define SDIOC_PSTAT_WPL_POS (19U) +#define SDIOC_PSTAT_WPL (0x00080000UL) +#define SDIOC_PSTAT_DATL_POS (20U) +#define SDIOC_PSTAT_DATL (0x00F00000UL) +#define SDIOC_PSTAT_DATL_0 (0x00100000UL) +#define SDIOC_PSTAT_DATL_1 (0x00200000UL) +#define SDIOC_PSTAT_DATL_2 (0x00400000UL) +#define SDIOC_PSTAT_DATL_3 (0x00800000UL) +#define SDIOC_PSTAT_CMDL_POS (24U) +#define SDIOC_PSTAT_CMDL (0x01000000UL) + +/* Bit definition for SDIOC_HOSTCON register */ +#define SDIOC_HOSTCON_DW_POS (1U) +#define SDIOC_HOSTCON_DW (0x02U) +#define SDIOC_HOSTCON_HSEN_POS (2U) +#define SDIOC_HOSTCON_HSEN (0x04U) +#define SDIOC_HOSTCON_EXDW_POS (5U) +#define SDIOC_HOSTCON_EXDW (0x20U) +#define SDIOC_HOSTCON_CDTL_POS (6U) +#define SDIOC_HOSTCON_CDTL (0x40U) +#define SDIOC_HOSTCON_CDSS_POS (7U) +#define SDIOC_HOSTCON_CDSS (0x80U) + +/* Bit definition for SDIOC_PWRCON register */ +#define SDIOC_PWRCON_PWON (0x01U) + +/* Bit definition for SDIOC_BLKGPCON register */ +#define SDIOC_BLKGPCON_SABGR_POS (0U) +#define SDIOC_BLKGPCON_SABGR (0x01U) +#define SDIOC_BLKGPCON_CR_POS (1U) +#define SDIOC_BLKGPCON_CR (0x02U) +#define SDIOC_BLKGPCON_RWC_POS (2U) +#define SDIOC_BLKGPCON_RWC (0x04U) +#define SDIOC_BLKGPCON_IABG_POS (3U) +#define SDIOC_BLKGPCON_IABG (0x08U) + +/* Bit definition for SDIOC_CLKCON register */ +#define SDIOC_CLKCON_ICE_POS (0U) +#define SDIOC_CLKCON_ICE (0x0001U) +#define SDIOC_CLKCON_CE_POS (2U) +#define SDIOC_CLKCON_CE (0x0004U) +#define SDIOC_CLKCON_FS_POS (8U) +#define SDIOC_CLKCON_FS (0xFF00U) +#define SDIOC_CLKCON_FS_0 (0x0100U) +#define SDIOC_CLKCON_FS_1 (0x0200U) +#define SDIOC_CLKCON_FS_2 (0x0400U) +#define SDIOC_CLKCON_FS_3 (0x0800U) +#define SDIOC_CLKCON_FS_4 (0x1000U) +#define SDIOC_CLKCON_FS_5 (0x2000U) +#define SDIOC_CLKCON_FS_6 (0x4000U) +#define SDIOC_CLKCON_FS_7 (0x8000U) + +/* Bit definition for SDIOC_TOUTCON register */ +#define SDIOC_TOUTCON_DTO (0x0FU) + +/* Bit definition for SDIOC_SFTRST register */ +#define SDIOC_SFTRST_RSTA_POS (0U) +#define SDIOC_SFTRST_RSTA (0x01U) +#define SDIOC_SFTRST_RSTC_POS (1U) +#define SDIOC_SFTRST_RSTC (0x02U) +#define SDIOC_SFTRST_RSTD_POS (2U) +#define SDIOC_SFTRST_RSTD (0x04U) + +/* Bit definition for SDIOC_NORINTST register */ +#define SDIOC_NORINTST_CC_POS (0U) +#define SDIOC_NORINTST_CC (0x0001U) +#define SDIOC_NORINTST_TC_POS (1U) +#define SDIOC_NORINTST_TC (0x0002U) +#define SDIOC_NORINTST_BGE_POS (2U) +#define SDIOC_NORINTST_BGE (0x0004U) +#define SDIOC_NORINTST_BWR_POS (4U) +#define SDIOC_NORINTST_BWR (0x0010U) +#define SDIOC_NORINTST_BRR_POS (5U) +#define SDIOC_NORINTST_BRR (0x0020U) +#define SDIOC_NORINTST_CIST_POS (6U) +#define SDIOC_NORINTST_CIST (0x0040U) +#define SDIOC_NORINTST_CRM_POS (7U) +#define SDIOC_NORINTST_CRM (0x0080U) +#define SDIOC_NORINTST_CINT_POS (8U) +#define SDIOC_NORINTST_CINT (0x0100U) +#define SDIOC_NORINTST_EI_POS (15U) +#define SDIOC_NORINTST_EI (0x8000U) + +/* Bit definition for SDIOC_ERRINTST register */ +#define SDIOC_ERRINTST_CTOE_POS (0U) +#define SDIOC_ERRINTST_CTOE (0x0001U) +#define SDIOC_ERRINTST_CCE_POS (1U) +#define SDIOC_ERRINTST_CCE (0x0002U) +#define SDIOC_ERRINTST_CEBE_POS (2U) +#define SDIOC_ERRINTST_CEBE (0x0004U) +#define SDIOC_ERRINTST_CIE_POS (3U) +#define SDIOC_ERRINTST_CIE (0x0008U) +#define SDIOC_ERRINTST_DTOE_POS (4U) +#define SDIOC_ERRINTST_DTOE (0x0010U) +#define SDIOC_ERRINTST_DCE_POS (5U) +#define SDIOC_ERRINTST_DCE (0x0020U) +#define SDIOC_ERRINTST_DEBE_POS (6U) +#define SDIOC_ERRINTST_DEBE (0x0040U) +#define SDIOC_ERRINTST_ACE_POS (8U) +#define SDIOC_ERRINTST_ACE (0x0100U) + +/* Bit definition for SDIOC_NORINTSTEN register */ +#define SDIOC_NORINTSTEN_CCEN_POS (0U) +#define SDIOC_NORINTSTEN_CCEN (0x0001U) +#define SDIOC_NORINTSTEN_TCEN_POS (1U) +#define SDIOC_NORINTSTEN_TCEN (0x0002U) +#define SDIOC_NORINTSTEN_BGEEN_POS (2U) +#define SDIOC_NORINTSTEN_BGEEN (0x0004U) +#define SDIOC_NORINTSTEN_BWREN_POS (4U) +#define SDIOC_NORINTSTEN_BWREN (0x0010U) +#define SDIOC_NORINTSTEN_BRREN_POS (5U) +#define SDIOC_NORINTSTEN_BRREN (0x0020U) +#define SDIOC_NORINTSTEN_CISTEN_POS (6U) +#define SDIOC_NORINTSTEN_CISTEN (0x0040U) +#define SDIOC_NORINTSTEN_CRMEN_POS (7U) +#define SDIOC_NORINTSTEN_CRMEN (0x0080U) +#define SDIOC_NORINTSTEN_CINTEN_POS (8U) +#define SDIOC_NORINTSTEN_CINTEN (0x0100U) + +/* Bit definition for SDIOC_ERRINTSTEN register */ +#define SDIOC_ERRINTSTEN_CTOEEN_POS (0U) +#define SDIOC_ERRINTSTEN_CTOEEN (0x0001U) +#define SDIOC_ERRINTSTEN_CCEEN_POS (1U) +#define SDIOC_ERRINTSTEN_CCEEN (0x0002U) +#define SDIOC_ERRINTSTEN_CEBEEN_POS (2U) +#define SDIOC_ERRINTSTEN_CEBEEN (0x0004U) +#define SDIOC_ERRINTSTEN_CIEEN_POS (3U) +#define SDIOC_ERRINTSTEN_CIEEN (0x0008U) +#define SDIOC_ERRINTSTEN_DTOEEN_POS (4U) +#define SDIOC_ERRINTSTEN_DTOEEN (0x0010U) +#define SDIOC_ERRINTSTEN_DCEEN_POS (5U) +#define SDIOC_ERRINTSTEN_DCEEN (0x0020U) +#define SDIOC_ERRINTSTEN_DEBEEN_POS (6U) +#define SDIOC_ERRINTSTEN_DEBEEN (0x0040U) +#define SDIOC_ERRINTSTEN_ACEEN_POS (8U) +#define SDIOC_ERRINTSTEN_ACEEN (0x0100U) + +/* Bit definition for SDIOC_NORINTSGEN register */ +#define SDIOC_NORINTSGEN_CCSEN_POS (0U) +#define SDIOC_NORINTSGEN_CCSEN (0x0001U) +#define SDIOC_NORINTSGEN_TCSEN_POS (1U) +#define SDIOC_NORINTSGEN_TCSEN (0x0002U) +#define SDIOC_NORINTSGEN_BGESEN_POS (2U) +#define SDIOC_NORINTSGEN_BGESEN (0x0004U) +#define SDIOC_NORINTSGEN_BWRSEN_POS (4U) +#define SDIOC_NORINTSGEN_BWRSEN (0x0010U) +#define SDIOC_NORINTSGEN_BRRSEN_POS (5U) +#define SDIOC_NORINTSGEN_BRRSEN (0x0020U) +#define SDIOC_NORINTSGEN_CISTSEN_POS (6U) +#define SDIOC_NORINTSGEN_CISTSEN (0x0040U) +#define SDIOC_NORINTSGEN_CRMSEN_POS (7U) +#define SDIOC_NORINTSGEN_CRMSEN (0x0080U) +#define SDIOC_NORINTSGEN_CINTSEN_POS (8U) +#define SDIOC_NORINTSGEN_CINTSEN (0x0100U) + +/* Bit definition for SDIOC_ERRINTSGEN register */ +#define SDIOC_ERRINTSGEN_CTOESEN_POS (0U) +#define SDIOC_ERRINTSGEN_CTOESEN (0x0001U) +#define SDIOC_ERRINTSGEN_CCESEN_POS (1U) +#define SDIOC_ERRINTSGEN_CCESEN (0x0002U) +#define SDIOC_ERRINTSGEN_CEBESEN_POS (2U) +#define SDIOC_ERRINTSGEN_CEBESEN (0x0004U) +#define SDIOC_ERRINTSGEN_CIESEN_POS (3U) +#define SDIOC_ERRINTSGEN_CIESEN (0x0008U) +#define SDIOC_ERRINTSGEN_DTOESEN_POS (4U) +#define SDIOC_ERRINTSGEN_DTOESEN (0x0010U) +#define SDIOC_ERRINTSGEN_DCESEN_POS (5U) +#define SDIOC_ERRINTSGEN_DCESEN (0x0020U) +#define SDIOC_ERRINTSGEN_DEBESEN_POS (6U) +#define SDIOC_ERRINTSGEN_DEBESEN (0x0040U) +#define SDIOC_ERRINTSGEN_ACESEN_POS (8U) +#define SDIOC_ERRINTSGEN_ACESEN (0x0100U) + +/* Bit definition for SDIOC_ATCERRST register */ +#define SDIOC_ATCERRST_NE_POS (0U) +#define SDIOC_ATCERRST_NE (0x0001U) +#define SDIOC_ATCERRST_TOE_POS (1U) +#define SDIOC_ATCERRST_TOE (0x0002U) +#define SDIOC_ATCERRST_CE_POS (2U) +#define SDIOC_ATCERRST_CE (0x0004U) +#define SDIOC_ATCERRST_EBE_POS (3U) +#define SDIOC_ATCERRST_EBE (0x0008U) +#define SDIOC_ATCERRST_IE_POS (4U) +#define SDIOC_ATCERRST_IE (0x0010U) +#define SDIOC_ATCERRST_CMDE_POS (7U) +#define SDIOC_ATCERRST_CMDE (0x0080U) + +/* Bit definition for SDIOC_FEA register */ +#define SDIOC_FEA_FNE_POS (0U) +#define SDIOC_FEA_FNE (0x0001U) +#define SDIOC_FEA_FTOE_POS (1U) +#define SDIOC_FEA_FTOE (0x0002U) +#define SDIOC_FEA_FCE_POS (2U) +#define SDIOC_FEA_FCE (0x0004U) +#define SDIOC_FEA_FEBE_POS (3U) +#define SDIOC_FEA_FEBE (0x0008U) +#define SDIOC_FEA_FIE_POS (4U) +#define SDIOC_FEA_FIE (0x0010U) +#define SDIOC_FEA_FCMDE_POS (7U) +#define SDIOC_FEA_FCMDE (0x0080U) + +/* Bit definition for SDIOC_FEE register */ +#define SDIOC_FEE_FCTOE_POS (0U) +#define SDIOC_FEE_FCTOE (0x0001U) +#define SDIOC_FEE_FCCE_POS (1U) +#define SDIOC_FEE_FCCE (0x0002U) +#define SDIOC_FEE_FCEBE_POS (2U) +#define SDIOC_FEE_FCEBE (0x0004U) +#define SDIOC_FEE_FCIE_POS (3U) +#define SDIOC_FEE_FCIE (0x0008U) +#define SDIOC_FEE_FDTOE_POS (4U) +#define SDIOC_FEE_FDTOE (0x0010U) +#define SDIOC_FEE_FDCE_POS (5U) +#define SDIOC_FEE_FDCE (0x0020U) +#define SDIOC_FEE_FDEBE_POS (6U) +#define SDIOC_FEE_FDEBE (0x0040U) +#define SDIOC_FEE_FACE_POS (8U) +#define SDIOC_FEE_FACE (0x0100U) + +/******************************************************************************* + Bit definition for Peripheral SPI +*******************************************************************************/ +/* Bit definition for SPI_DR register */ +#define SPI_DR (0xFFFFFFFFUL) + +/* Bit definition for SPI_CR1 register */ +#define SPI_CR1_SPIMDS_POS (0U) +#define SPI_CR1_SPIMDS (0x00000001UL) +#define SPI_CR1_TXMDS_POS (1U) +#define SPI_CR1_TXMDS (0x00000002UL) +#define SPI_CR1_MSTR_POS (3U) +#define SPI_CR1_MSTR (0x00000008UL) +#define SPI_CR1_SPLPBK_POS (4U) +#define SPI_CR1_SPLPBK (0x00000010UL) +#define SPI_CR1_SPLPBK2_POS (5U) +#define SPI_CR1_SPLPBK2 (0x00000020UL) +#define SPI_CR1_SPE_POS (6U) +#define SPI_CR1_SPE (0x00000040UL) +#define SPI_CR1_CSUSPE_POS (7U) +#define SPI_CR1_CSUSPE (0x00000080UL) +#define SPI_CR1_EIE_POS (8U) +#define SPI_CR1_EIE (0x00000100UL) +#define SPI_CR1_TXIE_POS (9U) +#define SPI_CR1_TXIE (0x00000200UL) +#define SPI_CR1_RXIE_POS (10U) +#define SPI_CR1_RXIE (0x00000400UL) +#define SPI_CR1_IDIE_POS (11U) +#define SPI_CR1_IDIE (0x00000800UL) +#define SPI_CR1_MODFE_POS (12U) +#define SPI_CR1_MODFE (0x00001000UL) +#define SPI_CR1_PATE_POS (13U) +#define SPI_CR1_PATE (0x00002000UL) +#define SPI_CR1_PAOE_POS (14U) +#define SPI_CR1_PAOE (0x00004000UL) +#define SPI_CR1_PAE_POS (15U) +#define SPI_CR1_PAE (0x00008000UL) + +/* Bit definition for SPI_CFG1 register */ +#define SPI_CFG1_FTHLV_POS (0U) +#define SPI_CFG1_FTHLV (0x00000003UL) +#define SPI_CFG1_FTHLV_0 (0x00000001UL) +#define SPI_CFG1_FTHLV_1 (0x00000002UL) +#define SPI_CFG1_SPRDTD_POS (6U) +#define SPI_CFG1_SPRDTD (0x00000040UL) +#define SPI_CFG1_SS0PV_POS (8U) +#define SPI_CFG1_SS0PV (0x00000100UL) +#define SPI_CFG1_SS1PV_POS (9U) +#define SPI_CFG1_SS1PV (0x00000200UL) +#define SPI_CFG1_SS2PV_POS (10U) +#define SPI_CFG1_SS2PV (0x00000400UL) +#define SPI_CFG1_SS3PV_POS (11U) +#define SPI_CFG1_SS3PV (0x00000800UL) +#define SPI_CFG1_MSSI_POS (20U) +#define SPI_CFG1_MSSI (0x00700000UL) +#define SPI_CFG1_MSSDL_POS (24U) +#define SPI_CFG1_MSSDL (0x07000000UL) +#define SPI_CFG1_MIDI_POS (28U) +#define SPI_CFG1_MIDI (0x70000000UL) + +/* Bit definition for SPI_SR register */ +#define SPI_SR_OVRERF_POS (0U) +#define SPI_SR_OVRERF (0x00000001UL) +#define SPI_SR_IDLNF_POS (1U) +#define SPI_SR_IDLNF (0x00000002UL) +#define SPI_SR_MODFERF_POS (2U) +#define SPI_SR_MODFERF (0x00000004UL) +#define SPI_SR_PERF_POS (3U) +#define SPI_SR_PERF (0x00000008UL) +#define SPI_SR_UDRERF_POS (4U) +#define SPI_SR_UDRERF (0x00000010UL) +#define SPI_SR_TDEF_POS (5U) +#define SPI_SR_TDEF (0x00000020UL) +#define SPI_SR_RDFF_POS (7U) +#define SPI_SR_RDFF (0x00000080UL) + +/* Bit definition for SPI_CFG2 register */ +#define SPI_CFG2_CPHA_POS (0U) +#define SPI_CFG2_CPHA (0x00000001UL) +#define SPI_CFG2_CPOL_POS (1U) +#define SPI_CFG2_CPOL (0x00000002UL) +#define SPI_CFG2_MBR_POS (2U) +#define SPI_CFG2_MBR (0x0000001CUL) +#define SPI_CFG2_SSA_POS (5U) +#define SPI_CFG2_SSA (0x000000E0UL) +#define SPI_CFG2_SSA_0 (0x00000020UL) +#define SPI_CFG2_SSA_1 (0x00000040UL) +#define SPI_CFG2_SSA_2 (0x00000080UL) +#define SPI_CFG2_DSIZE_POS (8U) +#define SPI_CFG2_DSIZE (0x00000F00UL) +#define SPI_CFG2_LSBF_POS (12U) +#define SPI_CFG2_LSBF (0x00001000UL) +#define SPI_CFG2_MIDIE_POS (13U) +#define SPI_CFG2_MIDIE (0x00002000UL) +#define SPI_CFG2_MSSDLE_POS (14U) +#define SPI_CFG2_MSSDLE (0x00004000UL) +#define SPI_CFG2_MSSIE_POS (15U) +#define SPI_CFG2_MSSIE (0x00008000UL) + +/******************************************************************************* + Bit definition for Peripheral SRAMC +*******************************************************************************/ +/* Bit definition for SRAMC_WTCR register */ +#define SRAMC_WTCR_SRAM12_RWT_POS (0U) +#define SRAMC_WTCR_SRAM12_RWT (0x00000007UL) +#define SRAMC_WTCR_SRAM12_WWT_POS (4U) +#define SRAMC_WTCR_SRAM12_WWT (0x00000070UL) +#define SRAMC_WTCR_SRAM3_RWT_POS (8U) +#define SRAMC_WTCR_SRAM3_RWT (0x00000700UL) +#define SRAMC_WTCR_SRAM3_WWT_POS (12U) +#define SRAMC_WTCR_SRAM3_WWT (0x00007000UL) +#define SRAMC_WTCR_SRAMH_RWT_POS (16U) +#define SRAMC_WTCR_SRAMH_RWT (0x00070000UL) +#define SRAMC_WTCR_SRAMH_WWT_POS (20U) +#define SRAMC_WTCR_SRAMH_WWT (0x00700000UL) +#define SRAMC_WTCR_SRAMR_RWT_POS (24U) +#define SRAMC_WTCR_SRAMR_RWT (0x07000000UL) +#define SRAMC_WTCR_SRAMR_WWT_POS (28U) +#define SRAMC_WTCR_SRAMR_WWT (0x70000000UL) + +/* Bit definition for SRAMC_WTPR register */ +#define SRAMC_WTPR_WTPRC_POS (0U) +#define SRAMC_WTPR_WTPRC (0x00000001UL) +#define SRAMC_WTPR_WTPRKW_POS (1U) +#define SRAMC_WTPR_WTPRKW (0x000000FEUL) + +/* Bit definition for SRAMC_CKCR register */ +#define SRAMC_CKCR_PYOAD_POS (0U) +#define SRAMC_CKCR_PYOAD (0x00000001UL) +#define SRAMC_CKCR_ECCOAD_POS (16U) +#define SRAMC_CKCR_ECCOAD (0x00010000UL) +#define SRAMC_CKCR_ECCMOD_POS (24U) +#define SRAMC_CKCR_ECCMOD (0x03000000UL) +#define SRAMC_CKCR_ECCMOD_0 (0x01000000UL) +#define SRAMC_CKCR_ECCMOD_1 (0x02000000UL) + +/* Bit definition for SRAMC_CKPR register */ +#define SRAMC_CKPR_CKPRC_POS (0U) +#define SRAMC_CKPR_CKPRC (0x00000001UL) +#define SRAMC_CKPR_CKPRKW_POS (1U) +#define SRAMC_CKPR_CKPRKW (0x000000FEUL) + +/* Bit definition for SRAMC_CKSR register */ +#define SRAMC_CKSR_SRAM3_1ERR_POS (0U) +#define SRAMC_CKSR_SRAM3_1ERR (0x00000001UL) +#define SRAMC_CKSR_SRAM3_2ERR_POS (1U) +#define SRAMC_CKSR_SRAM3_2ERR (0x00000002UL) +#define SRAMC_CKSR_SRAM12_PYERR_POS (2U) +#define SRAMC_CKSR_SRAM12_PYERR (0x00000004UL) +#define SRAMC_CKSR_SRAMH_PYERR_POS (3U) +#define SRAMC_CKSR_SRAMH_PYERR (0x00000008UL) +#define SRAMC_CKSR_SRAMR_PYERR_POS (4U) +#define SRAMC_CKSR_SRAMR_PYERR (0x00000010UL) + +/******************************************************************************* + Bit definition for Peripheral SWDT +*******************************************************************************/ +/* Bit definition for SWDT_SR register */ +#define SWDT_SR_CNT_POS (0U) +#define SWDT_SR_CNT (0x0000FFFFUL) +#define SWDT_SR_UDF_POS (16U) +#define SWDT_SR_UDF (0x00010000UL) +#define SWDT_SR_REF_POS (17U) +#define SWDT_SR_REF (0x00020000UL) + +/* Bit definition for SWDT_RR register */ +#define SWDT_RR_RF (0x0000FFFFUL) + +/******************************************************************************* + Bit definition for Peripheral TMR0 +*******************************************************************************/ +/* Bit definition for TMR0_CNTAR register */ +#define TMR0_CNTAR_CNTA (0x0000FFFFUL) + +/* Bit definition for TMR0_CNTBR register */ +#define TMR0_CNTBR_CNTB (0x0000FFFFUL) + +/* Bit definition for TMR0_CMPAR register */ +#define TMR0_CMPAR_CMPA (0x0000FFFFUL) + +/* Bit definition for TMR0_CMPBR register */ +#define TMR0_CMPBR_CMPB (0x0000FFFFUL) + +/* Bit definition for TMR0_BCONR register */ +#define TMR0_BCONR_CSTA_POS (0U) +#define TMR0_BCONR_CSTA (0x00000001UL) +#define TMR0_BCONR_CAPMDA_POS (1U) +#define TMR0_BCONR_CAPMDA (0x00000002UL) +#define TMR0_BCONR_INTENA_POS (2U) +#define TMR0_BCONR_INTENA (0x00000004UL) +#define TMR0_BCONR_CKDIVA_POS (4U) +#define TMR0_BCONR_CKDIVA (0x000000F0UL) +#define TMR0_BCONR_SYNSA_POS (8U) +#define TMR0_BCONR_SYNSA (0x00000100UL) +#define TMR0_BCONR_SYNCLKA_POS (9U) +#define TMR0_BCONR_SYNCLKA (0x00000200UL) +#define TMR0_BCONR_ASYNCLKA_POS (10U) +#define TMR0_BCONR_ASYNCLKA (0x00000400UL) +#define TMR0_BCONR_HSTAA_POS (12U) +#define TMR0_BCONR_HSTAA (0x00001000UL) +#define TMR0_BCONR_HSTPA_POS (13U) +#define TMR0_BCONR_HSTPA (0x00002000UL) +#define TMR0_BCONR_HCLEA_POS (14U) +#define TMR0_BCONR_HCLEA (0x00004000UL) +#define TMR0_BCONR_HICPA_POS (15U) +#define TMR0_BCONR_HICPA (0x00008000UL) +#define TMR0_BCONR_CSTB_POS (16U) +#define TMR0_BCONR_CSTB (0x00010000UL) +#define TMR0_BCONR_CAPMDB_POS (17U) +#define TMR0_BCONR_CAPMDB (0x00020000UL) +#define TMR0_BCONR_INTENB_POS (18U) +#define TMR0_BCONR_INTENB (0x00040000UL) +#define TMR0_BCONR_CKDIVB_POS (20U) +#define TMR0_BCONR_CKDIVB (0x00F00000UL) +#define TMR0_BCONR_SYNSB_POS (24U) +#define TMR0_BCONR_SYNSB (0x01000000UL) +#define TMR0_BCONR_SYNCLKB_POS (25U) +#define TMR0_BCONR_SYNCLKB (0x02000000UL) +#define TMR0_BCONR_ASYNCLKB_POS (26U) +#define TMR0_BCONR_ASYNCLKB (0x04000000UL) +#define TMR0_BCONR_HSTAB_POS (28U) +#define TMR0_BCONR_HSTAB (0x10000000UL) +#define TMR0_BCONR_HSTPB_POS (29U) +#define TMR0_BCONR_HSTPB (0x20000000UL) +#define TMR0_BCONR_HCLEB_POS (30U) +#define TMR0_BCONR_HCLEB (0x40000000UL) +#define TMR0_BCONR_HICPB_POS (31U) +#define TMR0_BCONR_HICPB (0x80000000UL) + +/* Bit definition for TMR0_STFLR register */ +#define TMR0_STFLR_CMFA_POS (0U) +#define TMR0_STFLR_CMFA (0x00000001UL) +#define TMR0_STFLR_CMFB_POS (16U) +#define TMR0_STFLR_CMFB (0x00010000UL) + +/******************************************************************************* + Bit definition for Peripheral TMR4 +*******************************************************************************/ +/* Bit definition for TMR4_OCCRUH register */ +#define TMR4_OCCRUH (0xFFFFU) + +/* Bit definition for TMR4_OCCRUL register */ +#define TMR4_OCCRUL (0xFFFFU) + +/* Bit definition for TMR4_OCCRVH register */ +#define TMR4_OCCRVH (0xFFFFU) + +/* Bit definition for TMR4_OCCRVL register */ +#define TMR4_OCCRVL (0xFFFFU) + +/* Bit definition for TMR4_OCCRWH register */ +#define TMR4_OCCRWH (0xFFFFU) + +/* Bit definition for TMR4_OCCRWL register */ +#define TMR4_OCCRWL (0xFFFFU) + +/* Bit definition for TMR4_OCSR register */ +#define TMR4_OCSR_OCEH_POS (0U) +#define TMR4_OCSR_OCEH (0x0001U) +#define TMR4_OCSR_OCEL_POS (1U) +#define TMR4_OCSR_OCEL (0x0002U) +#define TMR4_OCSR_OCPH_POS (2U) +#define TMR4_OCSR_OCPH (0x0004U) +#define TMR4_OCSR_OCPL_POS (3U) +#define TMR4_OCSR_OCPL (0x0008U) +#define TMR4_OCSR_OCIEH_POS (4U) +#define TMR4_OCSR_OCIEH (0x0010U) +#define TMR4_OCSR_OCIEL_POS (5U) +#define TMR4_OCSR_OCIEL (0x0020U) +#define TMR4_OCSR_OCFH_POS (6U) +#define TMR4_OCSR_OCFH (0x0040U) +#define TMR4_OCSR_OCFL_POS (7U) +#define TMR4_OCSR_OCFL (0x0080U) + +/* Bit definition for TMR4_OCER register */ +#define TMR4_OCER_CHBUFEN_POS (0U) +#define TMR4_OCER_CHBUFEN (0x0003U) +#define TMR4_OCER_CHBUFEN_0 (0x0001U) +#define TMR4_OCER_CHBUFEN_1 (0x0002U) +#define TMR4_OCER_CLBUFEN_POS (2U) +#define TMR4_OCER_CLBUFEN (0x000CU) +#define TMR4_OCER_CLBUFEN_0 (0x0004U) +#define TMR4_OCER_CLBUFEN_1 (0x0008U) +#define TMR4_OCER_MHBUFEN_POS (4U) +#define TMR4_OCER_MHBUFEN (0x0030U) +#define TMR4_OCER_MHBUFEN_0 (0x0010U) +#define TMR4_OCER_MHBUFEN_1 (0x0020U) +#define TMR4_OCER_MLBUFEN_POS (6U) +#define TMR4_OCER_MLBUFEN (0x00C0U) +#define TMR4_OCER_MLBUFEN_0 (0x0040U) +#define TMR4_OCER_MLBUFEN_1 (0x0080U) +#define TMR4_OCER_LMCH_POS (8U) +#define TMR4_OCER_LMCH (0x0100U) +#define TMR4_OCER_LMCL_POS (9U) +#define TMR4_OCER_LMCL (0x0200U) +#define TMR4_OCER_LMMH_POS (10U) +#define TMR4_OCER_LMMH (0x0400U) +#define TMR4_OCER_LMML_POS (11U) +#define TMR4_OCER_LMML (0x0800U) +#define TMR4_OCER_MCECH_POS (12U) +#define TMR4_OCER_MCECH (0x1000U) +#define TMR4_OCER_MCECL_POS (13U) +#define TMR4_OCER_MCECL (0x2000U) + +/* Bit definition for TMR4_OCMRH register */ +#define TMR4_OCMRH_OCFDCH_POS (0U) +#define TMR4_OCMRH_OCFDCH (0x0001U) +#define TMR4_OCMRH_OCFPKH_POS (1U) +#define TMR4_OCMRH_OCFPKH (0x0002U) +#define TMR4_OCMRH_OCFUCH_POS (2U) +#define TMR4_OCMRH_OCFUCH (0x0004U) +#define TMR4_OCMRH_OCFZRH_POS (3U) +#define TMR4_OCMRH_OCFZRH (0x0008U) +#define TMR4_OCMRH_OPDCH_POS (4U) +#define TMR4_OCMRH_OPDCH (0x0030U) +#define TMR4_OCMRH_OPDCH_0 (0x0010U) +#define TMR4_OCMRH_OPDCH_1 (0x0020U) +#define TMR4_OCMRH_OPPKH_POS (6U) +#define TMR4_OCMRH_OPPKH (0x00C0U) +#define TMR4_OCMRH_OPPKH_0 (0x0040U) +#define TMR4_OCMRH_OPPKH_1 (0x0080U) +#define TMR4_OCMRH_OPUCH_POS (8U) +#define TMR4_OCMRH_OPUCH (0x0300U) +#define TMR4_OCMRH_OPUCH_0 (0x0100U) +#define TMR4_OCMRH_OPUCH_1 (0x0200U) +#define TMR4_OCMRH_OPZRH_POS (10U) +#define TMR4_OCMRH_OPZRH (0x0C00U) +#define TMR4_OCMRH_OPZRH_0 (0x0400U) +#define TMR4_OCMRH_OPZRH_1 (0x0800U) +#define TMR4_OCMRH_OPNPKH_POS (12U) +#define TMR4_OCMRH_OPNPKH (0x3000U) +#define TMR4_OCMRH_OPNPKH_0 (0x1000U) +#define TMR4_OCMRH_OPNPKH_1 (0x2000U) +#define TMR4_OCMRH_OPNZRH_POS (14U) +#define TMR4_OCMRH_OPNZRH (0xC000U) +#define TMR4_OCMRH_OPNZRH_0 (0x4000U) +#define TMR4_OCMRH_OPNZRH_1 (0x8000U) + +/* Bit definition for TMR4_OCMRL register */ +#define TMR4_OCMRL_OCFDCL_POS (0U) +#define TMR4_OCMRL_OCFDCL (0x00000001UL) +#define TMR4_OCMRL_OCFPKL_POS (1U) +#define TMR4_OCMRL_OCFPKL (0x00000002UL) +#define TMR4_OCMRL_OCFUCL_POS (2U) +#define TMR4_OCMRL_OCFUCL (0x00000004UL) +#define TMR4_OCMRL_OCFZRL_POS (3U) +#define TMR4_OCMRL_OCFZRL (0x00000008UL) +#define TMR4_OCMRL_OPDCL_POS (4U) +#define TMR4_OCMRL_OPDCL (0x00000030UL) +#define TMR4_OCMRL_OPDCL_0 (0x00000010UL) +#define TMR4_OCMRL_OPDCL_1 (0x00000020UL) +#define TMR4_OCMRL_OPPKL_POS (6U) +#define TMR4_OCMRL_OPPKL (0x000000C0UL) +#define TMR4_OCMRL_OPPKL_0 (0x00000040UL) +#define TMR4_OCMRL_OPPKL_1 (0x00000080UL) +#define TMR4_OCMRL_OPUCL_POS (8U) +#define TMR4_OCMRL_OPUCL (0x00000300UL) +#define TMR4_OCMRL_OPUCL_0 (0x00000100UL) +#define TMR4_OCMRL_OPUCL_1 (0x00000200UL) +#define TMR4_OCMRL_OPZRL_POS (10U) +#define TMR4_OCMRL_OPZRL (0x00000C00UL) +#define TMR4_OCMRL_OPZRL_0 (0x00000400UL) +#define TMR4_OCMRL_OPZRL_1 (0x00000800UL) +#define TMR4_OCMRL_OPNPKL_POS (12U) +#define TMR4_OCMRL_OPNPKL (0x00003000UL) +#define TMR4_OCMRL_OPNPKL_0 (0x00001000UL) +#define TMR4_OCMRL_OPNPKL_1 (0x00002000UL) +#define TMR4_OCMRL_OPNZRL_POS (14U) +#define TMR4_OCMRL_OPNZRL (0x0000C000UL) +#define TMR4_OCMRL_OPNZRL_0 (0x00004000UL) +#define TMR4_OCMRL_OPNZRL_1 (0x00008000UL) +#define TMR4_OCMRL_EOPNDCL_POS (16U) +#define TMR4_OCMRL_EOPNDCL (0x00030000UL) +#define TMR4_OCMRL_EOPNDCL_0 (0x00010000UL) +#define TMR4_OCMRL_EOPNDCL_1 (0x00020000UL) +#define TMR4_OCMRL_EOPNUCL_POS (18U) +#define TMR4_OCMRL_EOPNUCL (0x000C0000UL) +#define TMR4_OCMRL_EOPNUCL_0 (0x00040000UL) +#define TMR4_OCMRL_EOPNUCL_1 (0x00080000UL) +#define TMR4_OCMRL_EOPDCL_POS (20U) +#define TMR4_OCMRL_EOPDCL (0x00300000UL) +#define TMR4_OCMRL_EOPDCL_0 (0x00100000UL) +#define TMR4_OCMRL_EOPDCL_1 (0x00200000UL) +#define TMR4_OCMRL_EOPPKL_POS (22U) +#define TMR4_OCMRL_EOPPKL (0x00C00000UL) +#define TMR4_OCMRL_EOPPKL_0 (0x00400000UL) +#define TMR4_OCMRL_EOPPKL_1 (0x00800000UL) +#define TMR4_OCMRL_EOPUCL_POS (24U) +#define TMR4_OCMRL_EOPUCL (0x03000000UL) +#define TMR4_OCMRL_EOPUCL_0 (0x01000000UL) +#define TMR4_OCMRL_EOPUCL_1 (0x02000000UL) +#define TMR4_OCMRL_EOPZRL_POS (26U) +#define TMR4_OCMRL_EOPZRL (0x0C000000UL) +#define TMR4_OCMRL_EOPZRL_0 (0x04000000UL) +#define TMR4_OCMRL_EOPZRL_1 (0x08000000UL) +#define TMR4_OCMRL_EOPNPKL_POS (28U) +#define TMR4_OCMRL_EOPNPKL (0x30000000UL) +#define TMR4_OCMRL_EOPNPKL_0 (0x10000000UL) +#define TMR4_OCMRL_EOPNPKL_1 (0x20000000UL) +#define TMR4_OCMRL_EOPNZRL_POS (30U) +#define TMR4_OCMRL_EOPNZRL (0xC0000000UL) +#define TMR4_OCMRL_EOPNZRL_0 (0x40000000UL) +#define TMR4_OCMRL_EOPNZRL_1 (0x80000000UL) + +/* Bit definition for TMR4_CPSR register */ +#define TMR4_CPSR (0xFFFFU) + +/* Bit definition for TMR4_CNTR register */ +#define TMR4_CNTR (0xFFFFU) + +/* Bit definition for TMR4_CCSR register */ +#define TMR4_CCSR_CKDIV_POS (0U) +#define TMR4_CCSR_CKDIV (0x000FU) +#define TMR4_CCSR_CLEAR_POS (4U) +#define TMR4_CCSR_CLEAR (0x0010U) +#define TMR4_CCSR_MODE_POS (5U) +#define TMR4_CCSR_MODE (0x0020U) +#define TMR4_CCSR_STOP_POS (6U) +#define TMR4_CCSR_STOP (0x0040U) +#define TMR4_CCSR_BUFEN_POS (7U) +#define TMR4_CCSR_BUFEN (0x0080U) +#define TMR4_CCSR_IRQPEN_POS (8U) +#define TMR4_CCSR_IRQPEN (0x0100U) +#define TMR4_CCSR_IRQPF_POS (9U) +#define TMR4_CCSR_IRQPF (0x0200U) +#define TMR4_CCSR_IRQZEN_POS (13U) +#define TMR4_CCSR_IRQZEN (0x2000U) +#define TMR4_CCSR_IRQZF_POS (14U) +#define TMR4_CCSR_IRQZF (0x4000U) +#define TMR4_CCSR_ECKEN_POS (15U) +#define TMR4_CCSR_ECKEN (0x8000U) + +/* Bit definition for TMR4_CVPR register */ +#define TMR4_CVPR_ZIM_POS (0U) +#define TMR4_CVPR_ZIM (0x000FU) +#define TMR4_CVPR_PIM_POS (4U) +#define TMR4_CVPR_PIM (0x00F0U) +#define TMR4_CVPR_ZIC_POS (8U) +#define TMR4_CVPR_ZIC (0x0F00U) +#define TMR4_CVPR_PIC_POS (12U) +#define TMR4_CVPR_PIC (0xF000U) + +/* Bit definition for TMR4_PFSRU register */ +#define TMR4_PFSRU (0xFFFFU) + +/* Bit definition for TMR4_PDARU register */ +#define TMR4_PDARU (0xFFFFU) + +/* Bit definition for TMR4_PDBRU register */ +#define TMR4_PDBRU (0xFFFFU) + +/* Bit definition for TMR4_PFSRV register */ +#define TMR4_PFSRV (0xFFFFU) + +/* Bit definition for TMR4_PDARV register */ +#define TMR4_PDARV (0xFFFFU) + +/* Bit definition for TMR4_PDBRV register */ +#define TMR4_PDBRV (0xFFFFU) + +/* Bit definition for TMR4_PFSRW register */ +#define TMR4_PFSRW (0xFFFFU) + +/* Bit definition for TMR4_PDARW register */ +#define TMR4_PDARW (0xFFFFU) + +/* Bit definition for TMR4_PDBRW register */ +#define TMR4_PDBRW (0xFFFFU) + +/* Bit definition for TMR4_POCR register */ +#define TMR4_POCR_DIVCK_POS (0U) +#define TMR4_POCR_DIVCK (0x0007U) +#define TMR4_POCR_PWMMD_POS (4U) +#define TMR4_POCR_PWMMD (0x0030U) +#define TMR4_POCR_PWMMD_0 (0x0010U) +#define TMR4_POCR_PWMMD_1 (0x0020U) +#define TMR4_POCR_LVLS_POS (6U) +#define TMR4_POCR_LVLS (0x00C0U) +#define TMR4_POCR_LVLS_0 (0x0040U) +#define TMR4_POCR_LVLS_1 (0x0080U) + +/* Bit definition for TMR4_RCSR register */ +#define TMR4_RCSR_RTIDU_POS (0U) +#define TMR4_RCSR_RTIDU (0x0001U) +#define TMR4_RCSR_RTIDV_POS (1U) +#define TMR4_RCSR_RTIDV (0x0002U) +#define TMR4_RCSR_RTIDW_POS (2U) +#define TMR4_RCSR_RTIDW (0x0004U) +#define TMR4_RCSR_RTIFU_POS (4U) +#define TMR4_RCSR_RTIFU (0x0010U) +#define TMR4_RCSR_RTICU_POS (5U) +#define TMR4_RCSR_RTICU (0x0020U) +#define TMR4_RCSR_RTEU_POS (6U) +#define TMR4_RCSR_RTEU (0x0040U) +#define TMR4_RCSR_RTSU_POS (7U) +#define TMR4_RCSR_RTSU (0x0080U) +#define TMR4_RCSR_RTIFV_POS (8U) +#define TMR4_RCSR_RTIFV (0x0100U) +#define TMR4_RCSR_RTICV_POS (9U) +#define TMR4_RCSR_RTICV (0x0200U) +#define TMR4_RCSR_RTEV_POS (10U) +#define TMR4_RCSR_RTEV (0x0400U) +#define TMR4_RCSR_RTSV_POS (11U) +#define TMR4_RCSR_RTSV (0x0800U) +#define TMR4_RCSR_RTIFW_POS (12U) +#define TMR4_RCSR_RTIFW (0x1000U) +#define TMR4_RCSR_RTICW_POS (13U) +#define TMR4_RCSR_RTICW (0x2000U) +#define TMR4_RCSR_RTEW_POS (14U) +#define TMR4_RCSR_RTEW (0x4000U) +#define TMR4_RCSR_RTSW_POS (15U) +#define TMR4_RCSR_RTSW (0x8000U) + +/* Bit definition for TMR4_SCCRUH register */ +#define TMR4_SCCRUH (0xFFFFU) + +/* Bit definition for TMR4_SCCRUL register */ +#define TMR4_SCCRUL (0xFFFFU) + +/* Bit definition for TMR4_SCCRVH register */ +#define TMR4_SCCRVH (0xFFFFU) + +/* Bit definition for TMR4_SCCRVL register */ +#define TMR4_SCCRVL (0xFFFFU) + +/* Bit definition for TMR4_SCCRWH register */ +#define TMR4_SCCRWH (0xFFFFU) + +/* Bit definition for TMR4_SCCRWL register */ +#define TMR4_SCCRWL (0xFFFFU) + +/* Bit definition for TMR4_SCSR register */ +#define TMR4_SCSR_BUFEN_POS (0U) +#define TMR4_SCSR_BUFEN (0x0003U) +#define TMR4_SCSR_BUFEN_0 (0x0001U) +#define TMR4_SCSR_BUFEN_1 (0x0002U) +#define TMR4_SCSR_EVTOS_POS (2U) +#define TMR4_SCSR_EVTOS (0x001CU) +#define TMR4_SCSR_LMC_POS (5U) +#define TMR4_SCSR_LMC (0x0020U) +#define TMR4_SCSR_EVTMS_POS (8U) +#define TMR4_SCSR_EVTMS (0x0100U) +#define TMR4_SCSR_EVTDS_POS (9U) +#define TMR4_SCSR_EVTDS (0x0200U) +#define TMR4_SCSR_DEN_POS (12U) +#define TMR4_SCSR_DEN (0x1000U) +#define TMR4_SCSR_PEN_POS (13U) +#define TMR4_SCSR_PEN (0x2000U) +#define TMR4_SCSR_UEN_POS (14U) +#define TMR4_SCSR_UEN (0x4000U) +#define TMR4_SCSR_ZEN_POS (15U) +#define TMR4_SCSR_ZEN (0x8000U) + +/* Bit definition for TMR4_SCMR register */ +#define TMR4_SCMR_AMC_POS (0U) +#define TMR4_SCMR_AMC (0x000FU) +#define TMR4_SCMR_MZCE_POS (6U) +#define TMR4_SCMR_MZCE (0x0040U) +#define TMR4_SCMR_MPCE_POS (7U) +#define TMR4_SCMR_MPCE (0x0080U) + +/* Bit definition for TMR4_ECSR register */ +#define TMR4_ECSR_HOLD_POS (7U) +#define TMR4_ECSR_HOLD (0x0080U) + +/******************************************************************************* + Bit definition for Peripheral TMR4_ECER +*******************************************************************************/ +/* Bit definition for TMR4_ECER_ECER register */ +#define TMR4_ECER_ECER_EMBVAL (0x00000003UL) + +/******************************************************************************* + Bit definition for Peripheral TMR6 +*******************************************************************************/ +/* Bit definition for TMR6_CNTER register */ +#define TMR6_CNTER_CNT (0x0000FFFFUL) + +/* Bit definition for TMR6_PERAR register */ +#define TMR6_PERAR_PERA (0x0000FFFFUL) + +/* Bit definition for TMR6_PERBR register */ +#define TMR6_PERBR_PERB (0x0000FFFFUL) + +/* Bit definition for TMR6_PERCR register */ +#define TMR6_PERCR_PERC (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMAR register */ +#define TMR6_GCMAR_GCMA (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMBR register */ +#define TMR6_GCMBR_GCMB (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMCR register */ +#define TMR6_GCMCR_GCMC (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMDR register */ +#define TMR6_GCMDR_GCMD (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMER register */ +#define TMR6_GCMER_GCME (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMFR register */ +#define TMR6_GCMFR_GCMF (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMAR register */ +#define TMR6_SCMAR_SCMA (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMBR register */ +#define TMR6_SCMBR_SCMB (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMCR register */ +#define TMR6_SCMCR_SCMC (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMDR register */ +#define TMR6_SCMDR_SCMD (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMER register */ +#define TMR6_SCMER_SCME (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMFR register */ +#define TMR6_SCMFR_SCMF (0x0000FFFFUL) + +/* Bit definition for TMR6_DTUAR register */ +#define TMR6_DTUAR_DTUA (0x0000FFFFUL) + +/* Bit definition for TMR6_DTDAR register */ +#define TMR6_DTDAR_DTDA (0x0000FFFFUL) + +/* Bit definition for TMR6_DTUBR register */ +#define TMR6_DTUBR_DTUB (0x0000FFFFUL) + +/* Bit definition for TMR6_DTDBR register */ +#define TMR6_DTDBR_DTDB (0x0000FFFFUL) + +/* Bit definition for TMR6_GCONR register */ +#define TMR6_GCONR_START_POS (0U) +#define TMR6_GCONR_START (0x00000001UL) +#define TMR6_GCONR_MODE_POS (1U) +#define TMR6_GCONR_MODE (0x0000000EUL) +#define TMR6_GCONR_CKDIV_POS (4U) +#define TMR6_GCONR_CKDIV (0x00000070UL) +#define TMR6_GCONR_DIR_POS (8U) +#define TMR6_GCONR_DIR (0x00000100UL) +#define TMR6_GCONR_ZMSKREV_POS (16U) +#define TMR6_GCONR_ZMSKREV (0x00010000UL) +#define TMR6_GCONR_ZMSKPOS_POS (17U) +#define TMR6_GCONR_ZMSKPOS (0x00020000UL) +#define TMR6_GCONR_ZMSKVAL_POS (18U) +#define TMR6_GCONR_ZMSKVAL (0x000C0000UL) +#define TMR6_GCONR_ZMSKVAL_0 (0x00040000UL) +#define TMR6_GCONR_ZMSKVAL_1 (0x00080000UL) + +/* Bit definition for TMR6_ICONR register */ +#define TMR6_ICONR_INTENA_POS (0U) +#define TMR6_ICONR_INTENA (0x00000001UL) +#define TMR6_ICONR_INTENB_POS (1U) +#define TMR6_ICONR_INTENB (0x00000002UL) +#define TMR6_ICONR_INTENC_POS (2U) +#define TMR6_ICONR_INTENC (0x00000004UL) +#define TMR6_ICONR_INTEND_POS (3U) +#define TMR6_ICONR_INTEND (0x00000008UL) +#define TMR6_ICONR_INTENE_POS (4U) +#define TMR6_ICONR_INTENE (0x00000010UL) +#define TMR6_ICONR_INTENF_POS (5U) +#define TMR6_ICONR_INTENF (0x00000020UL) +#define TMR6_ICONR_INTENOVF_POS (6U) +#define TMR6_ICONR_INTENOVF (0x00000040UL) +#define TMR6_ICONR_INTENUDF_POS (7U) +#define TMR6_ICONR_INTENUDF (0x00000080UL) +#define TMR6_ICONR_INTENDTE_POS (8U) +#define TMR6_ICONR_INTENDTE (0x00000100UL) +#define TMR6_ICONR_INTENSAU_POS (16U) +#define TMR6_ICONR_INTENSAU (0x00010000UL) +#define TMR6_ICONR_INTENSAD_POS (17U) +#define TMR6_ICONR_INTENSAD (0x00020000UL) +#define TMR6_ICONR_INTENSBU_POS (18U) +#define TMR6_ICONR_INTENSBU (0x00040000UL) +#define TMR6_ICONR_INTENSBD_POS (19U) +#define TMR6_ICONR_INTENSBD (0x00080000UL) + +/* Bit definition for TMR6_PCONR register */ +#define TMR6_PCONR_CAPMDA_POS (0U) +#define TMR6_PCONR_CAPMDA (0x00000001UL) +#define TMR6_PCONR_STACA_POS (1U) +#define TMR6_PCONR_STACA (0x00000002UL) +#define TMR6_PCONR_STPCA_POS (2U) +#define TMR6_PCONR_STPCA (0x00000004UL) +#define TMR6_PCONR_STASTPSA_POS (3U) +#define TMR6_PCONR_STASTPSA (0x00000008UL) +#define TMR6_PCONR_CMPCA_POS (4U) +#define TMR6_PCONR_CMPCA (0x00000030UL) +#define TMR6_PCONR_CMPCA_0 (0x00000010UL) +#define TMR6_PCONR_CMPCA_1 (0x00000020UL) +#define TMR6_PCONR_PERCA_POS (6U) +#define TMR6_PCONR_PERCA (0x000000C0UL) +#define TMR6_PCONR_PERCA_0 (0x00000040UL) +#define TMR6_PCONR_PERCA_1 (0x00000080UL) +#define TMR6_PCONR_OUTENA_POS (8U) +#define TMR6_PCONR_OUTENA (0x00000100UL) +#define TMR6_PCONR_EMBVALA_POS (11U) +#define TMR6_PCONR_EMBVALA (0x00001800UL) +#define TMR6_PCONR_EMBVALA_0 (0x00000800UL) +#define TMR6_PCONR_EMBVALA_1 (0x00001000UL) +#define TMR6_PCONR_CAPMDB_POS (16U) +#define TMR6_PCONR_CAPMDB (0x00010000UL) +#define TMR6_PCONR_STACB_POS (17U) +#define TMR6_PCONR_STACB (0x00020000UL) +#define TMR6_PCONR_STPCB_POS (18U) +#define TMR6_PCONR_STPCB (0x00040000UL) +#define TMR6_PCONR_STASTPSB_POS (19U) +#define TMR6_PCONR_STASTPSB (0x00080000UL) +#define TMR6_PCONR_CMPCB_POS (20U) +#define TMR6_PCONR_CMPCB (0x00300000UL) +#define TMR6_PCONR_CMPCB_0 (0x00100000UL) +#define TMR6_PCONR_CMPCB_1 (0x00200000UL) +#define TMR6_PCONR_PERCB_POS (22U) +#define TMR6_PCONR_PERCB (0x00C00000UL) +#define TMR6_PCONR_PERCB_0 (0x00400000UL) +#define TMR6_PCONR_PERCB_1 (0x00800000UL) +#define TMR6_PCONR_OUTENB_POS (24U) +#define TMR6_PCONR_OUTENB (0x01000000UL) +#define TMR6_PCONR_EMBVALB_POS (27U) +#define TMR6_PCONR_EMBVALB (0x18000000UL) +#define TMR6_PCONR_EMBVALB_0 (0x08000000UL) +#define TMR6_PCONR_EMBVALB_1 (0x10000000UL) + +/* Bit definition for TMR6_BCONR register */ +#define TMR6_BCONR_BENA_POS (0U) +#define TMR6_BCONR_BENA (0x00000001UL) +#define TMR6_BCONR_BSEA_POS (1U) +#define TMR6_BCONR_BSEA (0x00000002UL) +#define TMR6_BCONR_BENB_POS (2U) +#define TMR6_BCONR_BENB (0x00000004UL) +#define TMR6_BCONR_BSEB_POS (3U) +#define TMR6_BCONR_BSEB (0x00000008UL) +#define TMR6_BCONR_BENP_POS (8U) +#define TMR6_BCONR_BENP (0x00000100UL) +#define TMR6_BCONR_BSEP_POS (9U) +#define TMR6_BCONR_BSEP (0x00000200UL) +#define TMR6_BCONR_BENSPA_POS (16U) +#define TMR6_BCONR_BENSPA (0x00010000UL) +#define TMR6_BCONR_BSESPA_POS (17U) +#define TMR6_BCONR_BSESPA (0x00020000UL) +#define TMR6_BCONR_BTRUSPA_POS (20U) +#define TMR6_BCONR_BTRUSPA (0x00100000UL) +#define TMR6_BCONR_BTRDSPA_POS (21U) +#define TMR6_BCONR_BTRDSPA (0x00200000UL) +#define TMR6_BCONR_BENSPB_POS (24U) +#define TMR6_BCONR_BENSPB (0x01000000UL) +#define TMR6_BCONR_BSESPB_POS (25U) +#define TMR6_BCONR_BSESPB (0x02000000UL) +#define TMR6_BCONR_BTRUSPB_POS (28U) +#define TMR6_BCONR_BTRUSPB (0x10000000UL) +#define TMR6_BCONR_BTRDSPB_POS (29U) +#define TMR6_BCONR_BTRDSPB (0x20000000UL) + +/* Bit definition for TMR6_DCONR register */ +#define TMR6_DCONR_DTCEN_POS (0U) +#define TMR6_DCONR_DTCEN (0x00000001UL) +#define TMR6_DCONR_DTBENU_POS (4U) +#define TMR6_DCONR_DTBENU (0x00000010UL) +#define TMR6_DCONR_DTBEND_POS (5U) +#define TMR6_DCONR_DTBEND (0x00000020UL) +#define TMR6_DCONR_SEPA_POS (8U) +#define TMR6_DCONR_SEPA (0x00000100UL) + +/* Bit definition for TMR6_FCONR register */ +#define TMR6_FCONR_NOFIENGA_POS (0U) +#define TMR6_FCONR_NOFIENGA (0x00000001UL) +#define TMR6_FCONR_NOFICKGA_POS (1U) +#define TMR6_FCONR_NOFICKGA (0x00000006UL) +#define TMR6_FCONR_NOFICKGA_0 (0x00000002UL) +#define TMR6_FCONR_NOFICKGA_1 (0x00000004UL) +#define TMR6_FCONR_NOFIENGB_POS (4U) +#define TMR6_FCONR_NOFIENGB (0x00000010UL) +#define TMR6_FCONR_NOFICKGB_POS (5U) +#define TMR6_FCONR_NOFICKGB (0x00000060UL) +#define TMR6_FCONR_NOFICKGB_0 (0x00000020UL) +#define TMR6_FCONR_NOFICKGB_1 (0x00000040UL) +#define TMR6_FCONR_NOFIENTA_POS (16U) +#define TMR6_FCONR_NOFIENTA (0x00010000UL) +#define TMR6_FCONR_NOFICKTA_POS (17U) +#define TMR6_FCONR_NOFICKTA (0x00060000UL) +#define TMR6_FCONR_NOFICKTA_0 (0x00020000UL) +#define TMR6_FCONR_NOFICKTA_1 (0x00040000UL) +#define TMR6_FCONR_NOFIENTB_POS (20U) +#define TMR6_FCONR_NOFIENTB (0x00100000UL) +#define TMR6_FCONR_NOFICKTB_POS (21U) +#define TMR6_FCONR_NOFICKTB (0x00600000UL) +#define TMR6_FCONR_NOFICKTB_0 (0x00200000UL) +#define TMR6_FCONR_NOFICKTB_1 (0x00400000UL) + +/* Bit definition for TMR6_VPERR register */ +#define TMR6_VPERR_SPPERIA_POS (8U) +#define TMR6_VPERR_SPPERIA (0x00000100UL) +#define TMR6_VPERR_SPPERIB_POS (9U) +#define TMR6_VPERR_SPPERIB (0x00000200UL) +#define TMR6_VPERR_PCNTE_POS (16U) +#define TMR6_VPERR_PCNTE (0x00030000UL) +#define TMR6_VPERR_PCNTE_0 (0x00010000UL) +#define TMR6_VPERR_PCNTE_1 (0x00020000UL) +#define TMR6_VPERR_PCNTS_POS (18U) +#define TMR6_VPERR_PCNTS (0x001C0000UL) + +/* Bit definition for TMR6_STFLR register */ +#define TMR6_STFLR_CMAF_POS (0U) +#define TMR6_STFLR_CMAF (0x00000001UL) +#define TMR6_STFLR_CMBF_POS (1U) +#define TMR6_STFLR_CMBF (0x00000002UL) +#define TMR6_STFLR_CMCF_POS (2U) +#define TMR6_STFLR_CMCF (0x00000004UL) +#define TMR6_STFLR_CMDF_POS (3U) +#define TMR6_STFLR_CMDF (0x00000008UL) +#define TMR6_STFLR_CMEF_POS (4U) +#define TMR6_STFLR_CMEF (0x00000010UL) +#define TMR6_STFLR_CMFF_POS (5U) +#define TMR6_STFLR_CMFF (0x00000020UL) +#define TMR6_STFLR_OVFF_POS (6U) +#define TMR6_STFLR_OVFF (0x00000040UL) +#define TMR6_STFLR_UDFF_POS (7U) +#define TMR6_STFLR_UDFF (0x00000080UL) +#define TMR6_STFLR_DTEF_POS (8U) +#define TMR6_STFLR_DTEF (0x00000100UL) +#define TMR6_STFLR_CMSAUF_POS (9U) +#define TMR6_STFLR_CMSAUF (0x00000200UL) +#define TMR6_STFLR_CMSADF_POS (10U) +#define TMR6_STFLR_CMSADF (0x00000400UL) +#define TMR6_STFLR_CMSBUF_POS (11U) +#define TMR6_STFLR_CMSBUF (0x00000800UL) +#define TMR6_STFLR_CMSBDF_POS (12U) +#define TMR6_STFLR_CMSBDF (0x00001000UL) +#define TMR6_STFLR_VPERNUM_POS (21U) +#define TMR6_STFLR_VPERNUM (0x00E00000UL) +#define TMR6_STFLR_DIRF_POS (31U) +#define TMR6_STFLR_DIRF (0x80000000UL) + +/* Bit definition for TMR6_HSTAR register */ +#define TMR6_HSTAR_HSTA0_POS (0U) +#define TMR6_HSTAR_HSTA0 (0x00000001UL) +#define TMR6_HSTAR_HSTA1_POS (1U) +#define TMR6_HSTAR_HSTA1 (0x00000002UL) +#define TMR6_HSTAR_HSTA4_POS (4U) +#define TMR6_HSTAR_HSTA4 (0x00000010UL) +#define TMR6_HSTAR_HSTA5_POS (5U) +#define TMR6_HSTAR_HSTA5 (0x00000020UL) +#define TMR6_HSTAR_HSTA6_POS (6U) +#define TMR6_HSTAR_HSTA6 (0x00000040UL) +#define TMR6_HSTAR_HSTA7_POS (7U) +#define TMR6_HSTAR_HSTA7 (0x00000080UL) +#define TMR6_HSTAR_HSTA8_POS (8U) +#define TMR6_HSTAR_HSTA8 (0x00000100UL) +#define TMR6_HSTAR_HSTA9_POS (9U) +#define TMR6_HSTAR_HSTA9 (0x00000200UL) +#define TMR6_HSTAR_HSTA10_POS (10U) +#define TMR6_HSTAR_HSTA10 (0x00000400UL) +#define TMR6_HSTAR_HSTA11_POS (11U) +#define TMR6_HSTAR_HSTA11 (0x00000800UL) +#define TMR6_HSTAR_STAS_POS (31U) +#define TMR6_HSTAR_STAS (0x80000000UL) + +/* Bit definition for TMR6_HSTPR register */ +#define TMR6_HSTPR_HSTP0_POS (0U) +#define TMR6_HSTPR_HSTP0 (0x00000001UL) +#define TMR6_HSTPR_HSTP1_POS (1U) +#define TMR6_HSTPR_HSTP1 (0x00000002UL) +#define TMR6_HSTPR_HSTP4_POS (4U) +#define TMR6_HSTPR_HSTP4 (0x00000010UL) +#define TMR6_HSTPR_HSTP5_POS (5U) +#define TMR6_HSTPR_HSTP5 (0x00000020UL) +#define TMR6_HSTPR_HSTP6_POS (6U) +#define TMR6_HSTPR_HSTP6 (0x00000040UL) +#define TMR6_HSTPR_HSTP7_POS (7U) +#define TMR6_HSTPR_HSTP7 (0x00000080UL) +#define TMR6_HSTPR_HSTP8_POS (8U) +#define TMR6_HSTPR_HSTP8 (0x00000100UL) +#define TMR6_HSTPR_HSTP9_POS (9U) +#define TMR6_HSTPR_HSTP9 (0x00000200UL) +#define TMR6_HSTPR_HSTP10_POS (10U) +#define TMR6_HSTPR_HSTP10 (0x00000400UL) +#define TMR6_HSTPR_HSTP11_POS (11U) +#define TMR6_HSTPR_HSTP11 (0x00000800UL) +#define TMR6_HSTPR_STPS_POS (31U) +#define TMR6_HSTPR_STPS (0x80000000UL) + +/* Bit definition for TMR6_HCLRR register */ +#define TMR6_HCLRR_HCLE0_POS (0U) +#define TMR6_HCLRR_HCLE0 (0x00000001UL) +#define TMR6_HCLRR_HCLE1_POS (1U) +#define TMR6_HCLRR_HCLE1 (0x00000002UL) +#define TMR6_HCLRR_HCLE4_POS (4U) +#define TMR6_HCLRR_HCLE4 (0x00000010UL) +#define TMR6_HCLRR_HCLE5_POS (5U) +#define TMR6_HCLRR_HCLE5 (0x00000020UL) +#define TMR6_HCLRR_HCLE6_POS (6U) +#define TMR6_HCLRR_HCLE6 (0x00000040UL) +#define TMR6_HCLRR_HCLE7_POS (7U) +#define TMR6_HCLRR_HCLE7 (0x00000080UL) +#define TMR6_HCLRR_HCLE8_POS (8U) +#define TMR6_HCLRR_HCLE8 (0x00000100UL) +#define TMR6_HCLRR_HCLE9_POS (9U) +#define TMR6_HCLRR_HCLE9 (0x00000200UL) +#define TMR6_HCLRR_HCLE10_POS (10U) +#define TMR6_HCLRR_HCLE10 (0x00000400UL) +#define TMR6_HCLRR_HCLE11_POS (11U) +#define TMR6_HCLRR_HCLE11 (0x00000800UL) +#define TMR6_HCLRR_CLES_POS (31U) +#define TMR6_HCLRR_CLES (0x80000000UL) + +/* Bit definition for TMR6_HCPAR register */ +#define TMR6_HCPAR_HCPA0_POS (0U) +#define TMR6_HCPAR_HCPA0 (0x00000001UL) +#define TMR6_HCPAR_HCPA1_POS (1U) +#define TMR6_HCPAR_HCPA1 (0x00000002UL) +#define TMR6_HCPAR_HCPA4_POS (4U) +#define TMR6_HCPAR_HCPA4 (0x00000010UL) +#define TMR6_HCPAR_HCPA5_POS (5U) +#define TMR6_HCPAR_HCPA5 (0x00000020UL) +#define TMR6_HCPAR_HCPA6_POS (6U) +#define TMR6_HCPAR_HCPA6 (0x00000040UL) +#define TMR6_HCPAR_HCPA7_POS (7U) +#define TMR6_HCPAR_HCPA7 (0x00000080UL) +#define TMR6_HCPAR_HCPA8_POS (8U) +#define TMR6_HCPAR_HCPA8 (0x00000100UL) +#define TMR6_HCPAR_HCPA9_POS (9U) +#define TMR6_HCPAR_HCPA9 (0x00000200UL) +#define TMR6_HCPAR_HCPA10_POS (10U) +#define TMR6_HCPAR_HCPA10 (0x00000400UL) +#define TMR6_HCPAR_HCPA11_POS (11U) +#define TMR6_HCPAR_HCPA11 (0x00000800UL) + +/* Bit definition for TMR6_HCPBR register */ +#define TMR6_HCPBR_HCPB0_POS (0U) +#define TMR6_HCPBR_HCPB0 (0x00000001UL) +#define TMR6_HCPBR_HCPB1_POS (1U) +#define TMR6_HCPBR_HCPB1 (0x00000002UL) +#define TMR6_HCPBR_HCPB4_POS (4U) +#define TMR6_HCPBR_HCPB4 (0x00000010UL) +#define TMR6_HCPBR_HCPB5_POS (5U) +#define TMR6_HCPBR_HCPB5 (0x00000020UL) +#define TMR6_HCPBR_HCPB6_POS (6U) +#define TMR6_HCPBR_HCPB6 (0x00000040UL) +#define TMR6_HCPBR_HCPB7_POS (7U) +#define TMR6_HCPBR_HCPB7 (0x00000080UL) +#define TMR6_HCPBR_HCPB8_POS (8U) +#define TMR6_HCPBR_HCPB8 (0x00000100UL) +#define TMR6_HCPBR_HCPB9_POS (9U) +#define TMR6_HCPBR_HCPB9 (0x00000200UL) +#define TMR6_HCPBR_HCPB10_POS (10U) +#define TMR6_HCPBR_HCPB10 (0x00000400UL) +#define TMR6_HCPBR_HCPB11_POS (11U) +#define TMR6_HCPBR_HCPB11 (0x00000800UL) + +/* Bit definition for TMR6_HCUPR register */ +#define TMR6_HCUPR_HCUP0_POS (0U) +#define TMR6_HCUPR_HCUP0 (0x00000001UL) +#define TMR6_HCUPR_HCUP1_POS (1U) +#define TMR6_HCUPR_HCUP1 (0x00000002UL) +#define TMR6_HCUPR_HCUP2_POS (2U) +#define TMR6_HCUPR_HCUP2 (0x00000004UL) +#define TMR6_HCUPR_HCUP3_POS (3U) +#define TMR6_HCUPR_HCUP3 (0x00000008UL) +#define TMR6_HCUPR_HCUP4_POS (4U) +#define TMR6_HCUPR_HCUP4 (0x00000010UL) +#define TMR6_HCUPR_HCUP5_POS (5U) +#define TMR6_HCUPR_HCUP5 (0x00000020UL) +#define TMR6_HCUPR_HCUP6_POS (6U) +#define TMR6_HCUPR_HCUP6 (0x00000040UL) +#define TMR6_HCUPR_HCUP7_POS (7U) +#define TMR6_HCUPR_HCUP7 (0x00000080UL) +#define TMR6_HCUPR_HCUP8_POS (8U) +#define TMR6_HCUPR_HCUP8 (0x00000100UL) +#define TMR6_HCUPR_HCUP9_POS (9U) +#define TMR6_HCUPR_HCUP9 (0x00000200UL) +#define TMR6_HCUPR_HCUP10_POS (10U) +#define TMR6_HCUPR_HCUP10 (0x00000400UL) +#define TMR6_HCUPR_HCUP11_POS (11U) +#define TMR6_HCUPR_HCUP11 (0x00000800UL) +#define TMR6_HCUPR_HCUP16_POS (16U) +#define TMR6_HCUPR_HCUP16 (0x00010000UL) +#define TMR6_HCUPR_HCUP17_POS (17U) +#define TMR6_HCUPR_HCUP17 (0x00020000UL) + +/* Bit definition for TMR6_HCDOR register */ +#define TMR6_HCDOR_HCDO0_POS (0U) +#define TMR6_HCDOR_HCDO0 (0x00000001UL) +#define TMR6_HCDOR_HCDO1_POS (1U) +#define TMR6_HCDOR_HCDO1 (0x00000002UL) +#define TMR6_HCDOR_HCDO2_POS (2U) +#define TMR6_HCDOR_HCDO2 (0x00000004UL) +#define TMR6_HCDOR_HCDO3_POS (3U) +#define TMR6_HCDOR_HCDO3 (0x00000008UL) +#define TMR6_HCDOR_HCDO4_POS (4U) +#define TMR6_HCDOR_HCDO4 (0x00000010UL) +#define TMR6_HCDOR_HCDO5_POS (5U) +#define TMR6_HCDOR_HCDO5 (0x00000020UL) +#define TMR6_HCDOR_HCDO6_POS (6U) +#define TMR6_HCDOR_HCDO6 (0x00000040UL) +#define TMR6_HCDOR_HCDO7_POS (7U) +#define TMR6_HCDOR_HCDO7 (0x00000080UL) +#define TMR6_HCDOR_HCDO8_POS (8U) +#define TMR6_HCDOR_HCDO8 (0x00000100UL) +#define TMR6_HCDOR_HCDO9_POS (9U) +#define TMR6_HCDOR_HCDO9 (0x00000200UL) +#define TMR6_HCDOR_HCDO10_POS (10U) +#define TMR6_HCDOR_HCDO10 (0x00000400UL) +#define TMR6_HCDOR_HCDO11_POS (11U) +#define TMR6_HCDOR_HCDO11 (0x00000800UL) +#define TMR6_HCDOR_HCDO16_POS (16U) +#define TMR6_HCDOR_HCDO16 (0x00010000UL) +#define TMR6_HCDOR_HCDO17_POS (17U) +#define TMR6_HCDOR_HCDO17 (0x00020000UL) + +/******************************************************************************* + Bit definition for Peripheral TMR6_COMMON +*******************************************************************************/ +/* Bit definition for TMR6_COMMON_SSTAR register */ +#define TMR6_COMMON_SSTAR_SSTA1_POS (0U) +#define TMR6_COMMON_SSTAR_SSTA1 (0x00000001UL) +#define TMR6_COMMON_SSTAR_SSTA2_POS (1U) +#define TMR6_COMMON_SSTAR_SSTA2 (0x00000002UL) +#define TMR6_COMMON_SSTAR_SSTA3_POS (2U) +#define TMR6_COMMON_SSTAR_SSTA3 (0x00000004UL) + +/* Bit definition for TMR6_COMMON_SSTPR register */ +#define TMR6_COMMON_SSTPR_SSTP1_POS (0U) +#define TMR6_COMMON_SSTPR_SSTP1 (0x00000001UL) +#define TMR6_COMMON_SSTPR_SSTP2_POS (1U) +#define TMR6_COMMON_SSTPR_SSTP2 (0x00000002UL) +#define TMR6_COMMON_SSTPR_SSTP3_POS (2U) +#define TMR6_COMMON_SSTPR_SSTP3 (0x00000004UL) + +/* Bit definition for TMR6_COMMON_SCLRR register */ +#define TMR6_COMMON_SCLRR_SCLE1_POS (0U) +#define TMR6_COMMON_SCLRR_SCLE1 (0x00000001UL) +#define TMR6_COMMON_SCLRR_SCLE2_POS (1U) +#define TMR6_COMMON_SCLRR_SCLE2 (0x00000002UL) +#define TMR6_COMMON_SCLRR_SCLE3_POS (2U) +#define TMR6_COMMON_SCLRR_SCLE3 (0x00000004UL) + +/******************************************************************************* + Bit definition for Peripheral TMRA +*******************************************************************************/ +/* Bit definition for TMRA_CNTER register */ +#define TMRA_CNTER_CNT (0xFFFFU) + +/* Bit definition for TMRA_PERAR register */ +#define TMRA_PERAR_PER (0xFFFFU) + +/* Bit definition for TMRA_CMPAR register */ +#define TMRA_CMPAR_CMP (0xFFFFU) + +/* Bit definition for TMRA_BCSTRL register */ +#define TMRA_BCSTRL_START_POS (0U) +#define TMRA_BCSTRL_START (0x01U) +#define TMRA_BCSTRL_DIR_POS (1U) +#define TMRA_BCSTRL_DIR (0x02U) +#define TMRA_BCSTRL_MODE_POS (2U) +#define TMRA_BCSTRL_MODE (0x04U) +#define TMRA_BCSTRL_SYNST_POS (3U) +#define TMRA_BCSTRL_SYNST (0x08U) +#define TMRA_BCSTRL_CKDIV_POS (4U) +#define TMRA_BCSTRL_CKDIV (0xF0U) + +/* Bit definition for TMRA_BCSTRH register */ +#define TMRA_BCSTRH_OVSTP_POS (0U) +#define TMRA_BCSTRH_OVSTP (0x01U) +#define TMRA_BCSTRH_ITENOVF_POS (4U) +#define TMRA_BCSTRH_ITENOVF (0x10U) +#define TMRA_BCSTRH_ITENUDF_POS (5U) +#define TMRA_BCSTRH_ITENUDF (0x20U) +#define TMRA_BCSTRH_OVFF_POS (6U) +#define TMRA_BCSTRH_OVFF (0x40U) +#define TMRA_BCSTRH_UDFF_POS (7U) +#define TMRA_BCSTRH_UDFF (0x80U) + +/* Bit definition for TMRA_HCONR register */ +#define TMRA_HCONR_HSTA0_POS (0U) +#define TMRA_HCONR_HSTA0 (0x0001U) +#define TMRA_HCONR_HSTA1_POS (1U) +#define TMRA_HCONR_HSTA1 (0x0002U) +#define TMRA_HCONR_HSTA2_POS (2U) +#define TMRA_HCONR_HSTA2 (0x0004U) +#define TMRA_HCONR_HSTP0_POS (4U) +#define TMRA_HCONR_HSTP0 (0x0010U) +#define TMRA_HCONR_HSTP1_POS (5U) +#define TMRA_HCONR_HSTP1 (0x0020U) +#define TMRA_HCONR_HSTP2_POS (6U) +#define TMRA_HCONR_HSTP2 (0x0040U) +#define TMRA_HCONR_HCLE0_POS (8U) +#define TMRA_HCONR_HCLE0 (0x0100U) +#define TMRA_HCONR_HCLE1_POS (9U) +#define TMRA_HCONR_HCLE1 (0x0200U) +#define TMRA_HCONR_HCLE2_POS (10U) +#define TMRA_HCONR_HCLE2 (0x0400U) +#define TMRA_HCONR_HCLE3_POS (12U) +#define TMRA_HCONR_HCLE3 (0x1000U) +#define TMRA_HCONR_HCLE4_POS (13U) +#define TMRA_HCONR_HCLE4 (0x2000U) +#define TMRA_HCONR_HCLE5_POS (14U) +#define TMRA_HCONR_HCLE5 (0x4000U) +#define TMRA_HCONR_HCLE6_POS (15U) +#define TMRA_HCONR_HCLE6 (0x8000U) + +/* Bit definition for TMRA_HCUPR register */ +#define TMRA_HCUPR_HCUP0_POS (0U) +#define TMRA_HCUPR_HCUP0 (0x0001U) +#define TMRA_HCUPR_HCUP1_POS (1U) +#define TMRA_HCUPR_HCUP1 (0x0002U) +#define TMRA_HCUPR_HCUP2_POS (2U) +#define TMRA_HCUPR_HCUP2 (0x0004U) +#define TMRA_HCUPR_HCUP3_POS (3U) +#define TMRA_HCUPR_HCUP3 (0x0008U) +#define TMRA_HCUPR_HCUP4_POS (4U) +#define TMRA_HCUPR_HCUP4 (0x0010U) +#define TMRA_HCUPR_HCUP5_POS (5U) +#define TMRA_HCUPR_HCUP5 (0x0020U) +#define TMRA_HCUPR_HCUP6_POS (6U) +#define TMRA_HCUPR_HCUP6 (0x0040U) +#define TMRA_HCUPR_HCUP7_POS (7U) +#define TMRA_HCUPR_HCUP7 (0x0080U) +#define TMRA_HCUPR_HCUP8_POS (8U) +#define TMRA_HCUPR_HCUP8 (0x0100U) +#define TMRA_HCUPR_HCUP9_POS (9U) +#define TMRA_HCUPR_HCUP9 (0x0200U) +#define TMRA_HCUPR_HCUP10_POS (10U) +#define TMRA_HCUPR_HCUP10 (0x0400U) +#define TMRA_HCUPR_HCUP11_POS (11U) +#define TMRA_HCUPR_HCUP11 (0x0800U) +#define TMRA_HCUPR_HCUP12_POS (12U) +#define TMRA_HCUPR_HCUP12 (0x1000U) + +/* Bit definition for TMRA_HCDOR register */ +#define TMRA_HCDOR_HCDO0_POS (0U) +#define TMRA_HCDOR_HCDO0 (0x0001U) +#define TMRA_HCDOR_HCDO1_POS (1U) +#define TMRA_HCDOR_HCDO1 (0x0002U) +#define TMRA_HCDOR_HCDO2_POS (2U) +#define TMRA_HCDOR_HCDO2 (0x0004U) +#define TMRA_HCDOR_HCDO3_POS (3U) +#define TMRA_HCDOR_HCDO3 (0x0008U) +#define TMRA_HCDOR_HCDO4_POS (4U) +#define TMRA_HCDOR_HCDO4 (0x0010U) +#define TMRA_HCDOR_HCDO5_POS (5U) +#define TMRA_HCDOR_HCDO5 (0x0020U) +#define TMRA_HCDOR_HCDO6_POS (6U) +#define TMRA_HCDOR_HCDO6 (0x0040U) +#define TMRA_HCDOR_HCDO7_POS (7U) +#define TMRA_HCDOR_HCDO7 (0x0080U) +#define TMRA_HCDOR_HCDO8_POS (8U) +#define TMRA_HCDOR_HCDO8 (0x0100U) +#define TMRA_HCDOR_HCDO9_POS (9U) +#define TMRA_HCDOR_HCDO9 (0x0200U) +#define TMRA_HCDOR_HCDO10_POS (10U) +#define TMRA_HCDOR_HCDO10 (0x0400U) +#define TMRA_HCDOR_HCDO11_POS (11U) +#define TMRA_HCDOR_HCDO11 (0x0800U) +#define TMRA_HCDOR_HCDO12_POS (12U) +#define TMRA_HCDOR_HCDO12 (0x1000U) + +/* Bit definition for TMRA_ICONR register */ +#define TMRA_ICONR_ITEN1_POS (0U) +#define TMRA_ICONR_ITEN1 (0x0001U) +#define TMRA_ICONR_ITEN2_POS (1U) +#define TMRA_ICONR_ITEN2 (0x0002U) +#define TMRA_ICONR_ITEN3_POS (2U) +#define TMRA_ICONR_ITEN3 (0x0004U) +#define TMRA_ICONR_ITEN4_POS (3U) +#define TMRA_ICONR_ITEN4 (0x0008U) +#define TMRA_ICONR_ITEN5_POS (4U) +#define TMRA_ICONR_ITEN5 (0x0010U) +#define TMRA_ICONR_ITEN6_POS (5U) +#define TMRA_ICONR_ITEN6 (0x0020U) +#define TMRA_ICONR_ITEN7_POS (6U) +#define TMRA_ICONR_ITEN7 (0x0040U) +#define TMRA_ICONR_ITEN8_POS (7U) +#define TMRA_ICONR_ITEN8 (0x0080U) + +/* Bit definition for TMRA_ECONR register */ +#define TMRA_ECONR_ETEN1_POS (0U) +#define TMRA_ECONR_ETEN1 (0x0001U) +#define TMRA_ECONR_ETEN2_POS (1U) +#define TMRA_ECONR_ETEN2 (0x0002U) +#define TMRA_ECONR_ETEN3_POS (2U) +#define TMRA_ECONR_ETEN3 (0x0004U) +#define TMRA_ECONR_ETEN4_POS (3U) +#define TMRA_ECONR_ETEN4 (0x0008U) +#define TMRA_ECONR_ETEN5_POS (4U) +#define TMRA_ECONR_ETEN5 (0x0010U) +#define TMRA_ECONR_ETEN6_POS (5U) +#define TMRA_ECONR_ETEN6 (0x0020U) +#define TMRA_ECONR_ETEN7_POS (6U) +#define TMRA_ECONR_ETEN7 (0x0040U) +#define TMRA_ECONR_ETEN8_POS (7U) +#define TMRA_ECONR_ETEN8 (0x0080U) + +/* Bit definition for TMRA_FCONR register */ +#define TMRA_FCONR_NOFIENTG_POS (0U) +#define TMRA_FCONR_NOFIENTG (0x0001U) +#define TMRA_FCONR_NOFICKTG_POS (1U) +#define TMRA_FCONR_NOFICKTG (0x0006U) +#define TMRA_FCONR_NOFIENCA_POS (8U) +#define TMRA_FCONR_NOFIENCA (0x0100U) +#define TMRA_FCONR_NOFICKCA_POS (9U) +#define TMRA_FCONR_NOFICKCA (0x0600U) +#define TMRA_FCONR_NOFIENCB_POS (12U) +#define TMRA_FCONR_NOFIENCB (0x1000U) +#define TMRA_FCONR_NOFICKCB_POS (13U) +#define TMRA_FCONR_NOFICKCB (0x6000U) + +/* Bit definition for TMRA_STFLR register */ +#define TMRA_STFLR_CMPF1_POS (0U) +#define TMRA_STFLR_CMPF1 (0x0001U) +#define TMRA_STFLR_CMPF2_POS (1U) +#define TMRA_STFLR_CMPF2 (0x0002U) +#define TMRA_STFLR_CMPF3_POS (2U) +#define TMRA_STFLR_CMPF3 (0x0004U) +#define TMRA_STFLR_CMPF4_POS (3U) +#define TMRA_STFLR_CMPF4 (0x0008U) +#define TMRA_STFLR_CMPF5_POS (4U) +#define TMRA_STFLR_CMPF5 (0x0010U) +#define TMRA_STFLR_CMPF6_POS (5U) +#define TMRA_STFLR_CMPF6 (0x0020U) +#define TMRA_STFLR_CMPF7_POS (6U) +#define TMRA_STFLR_CMPF7 (0x0040U) +#define TMRA_STFLR_CMPF8_POS (7U) +#define TMRA_STFLR_CMPF8 (0x0080U) + +/* Bit definition for TMRA_BCONR register */ +#define TMRA_BCONR_BEN_POS (0U) +#define TMRA_BCONR_BEN (0x0001U) +#define TMRA_BCONR_BSE0_POS (1U) +#define TMRA_BCONR_BSE0 (0x0002U) +#define TMRA_BCONR_BSE1_POS (2U) +#define TMRA_BCONR_BSE1 (0x0004U) + +/* Bit definition for TMRA_CCONR register */ +#define TMRA_CCONR_CAPMD_POS (0U) +#define TMRA_CCONR_CAPMD (0x0001U) +#define TMRA_CCONR_HICP0_POS (4U) +#define TMRA_CCONR_HICP0 (0x0010U) +#define TMRA_CCONR_HICP1_POS (5U) +#define TMRA_CCONR_HICP1 (0x0020U) +#define TMRA_CCONR_HICP2_POS (6U) +#define TMRA_CCONR_HICP2 (0x0040U) +#define TMRA_CCONR_HICP3_POS (8U) +#define TMRA_CCONR_HICP3 (0x0100U) +#define TMRA_CCONR_HICP4_POS (9U) +#define TMRA_CCONR_HICP4 (0x0200U) +#define TMRA_CCONR_NOFIENCP_POS (12U) +#define TMRA_CCONR_NOFIENCP (0x1000U) +#define TMRA_CCONR_NOFICKCP_POS (13U) +#define TMRA_CCONR_NOFICKCP (0x6000U) +#define TMRA_CCONR_NOFICKCP_0 (0x2000U) +#define TMRA_CCONR_NOFICKCP_1 (0x4000U) + +/* Bit definition for TMRA_PCONR register */ +#define TMRA_PCONR_STAC_POS (0U) +#define TMRA_PCONR_STAC (0x0003U) +#define TMRA_PCONR_STAC_0 (0x0001U) +#define TMRA_PCONR_STAC_1 (0x0002U) +#define TMRA_PCONR_STPC_POS (2U) +#define TMRA_PCONR_STPC (0x000CU) +#define TMRA_PCONR_STPC_0 (0x0004U) +#define TMRA_PCONR_STPC_1 (0x0008U) +#define TMRA_PCONR_CMPC_POS (4U) +#define TMRA_PCONR_CMPC (0x0030U) +#define TMRA_PCONR_CMPC_0 (0x0010U) +#define TMRA_PCONR_CMPC_1 (0x0020U) +#define TMRA_PCONR_PERC_POS (6U) +#define TMRA_PCONR_PERC (0x00C0U) +#define TMRA_PCONR_PERC_0 (0x0040U) +#define TMRA_PCONR_PERC_1 (0x0080U) +#define TMRA_PCONR_FORC_POS (8U) +#define TMRA_PCONR_FORC (0x0300U) +#define TMRA_PCONR_FORC_0 (0x0100U) +#define TMRA_PCONR_FORC_1 (0x0200U) +#define TMRA_PCONR_OUTEN_POS (12U) +#define TMRA_PCONR_OUTEN (0x1000U) + +/******************************************************************************* + Bit definition for Peripheral TRNG +*******************************************************************************/ +/* Bit definition for TRNG_CR register */ +#define TRNG_CR_EN_POS (0U) +#define TRNG_CR_EN (0x00000001UL) +#define TRNG_CR_RUN_POS (1U) +#define TRNG_CR_RUN (0x00000002UL) + +/* Bit definition for TRNG_MR register */ +#define TRNG_MR_LOAD_POS (0U) +#define TRNG_MR_LOAD (0x00000001UL) +#define TRNG_MR_CNT_POS (2U) +#define TRNG_MR_CNT (0x0000001CUL) + +/* Bit definition for TRNG_DR0 register */ +#define TRNG_DR0 (0xFFFFFFFFUL) + +/* Bit definition for TRNG_DR1 register */ +#define TRNG_DR1 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral USART +*******************************************************************************/ +/* Bit definition for USART_SR register */ +#define USART_SR_PE_POS (0U) +#define USART_SR_PE (0x00000001UL) +#define USART_SR_FE_POS (1U) +#define USART_SR_FE (0x00000002UL) +#define USART_SR_ORE_POS (3U) +#define USART_SR_ORE (0x00000008UL) +#define USART_SR_RXNE_POS (5U) +#define USART_SR_RXNE (0x00000020UL) +#define USART_SR_TC_POS (6U) +#define USART_SR_TC (0x00000040UL) +#define USART_SR_TXE_POS (7U) +#define USART_SR_TXE (0x00000080UL) +#define USART_SR_RTOF_POS (8U) +#define USART_SR_RTOF (0x00000100UL) +#define USART_SR_MPB_POS (16U) +#define USART_SR_MPB (0x00010000UL) + +/* Bit definition for USART_TDR register */ +#define USART_TDR_TDR_POS (0U) +#define USART_TDR_TDR (0x01FFU) +#define USART_TDR_MPID_POS (9U) +#define USART_TDR_MPID (0x0200U) + +/* Bit definition for USART_RDR register */ +#define USART_RDR_RDR (0x01FFU) + +/* Bit definition for USART_BRR register */ +#define USART_BRR_DIV_FRACTION_POS (0U) +#define USART_BRR_DIV_FRACTION (0x0000007FUL) +#define USART_BRR_DIV_INTEGER_POS (8U) +#define USART_BRR_DIV_INTEGER (0x0000FF00UL) + +/* Bit definition for USART_CR1 register */ +#define USART_CR1_RTOE_POS (0U) +#define USART_CR1_RTOE (0x00000001UL) +#define USART_CR1_RTOIE_POS (1U) +#define USART_CR1_RTOIE (0x00000002UL) +#define USART_CR1_RE_POS (2U) +#define USART_CR1_RE (0x00000004UL) +#define USART_CR1_TE_POS (3U) +#define USART_CR1_TE (0x00000008UL) +#define USART_CR1_SLME_POS (4U) +#define USART_CR1_SLME (0x00000010UL) +#define USART_CR1_RIE_POS (5U) +#define USART_CR1_RIE (0x00000020UL) +#define USART_CR1_TCIE_POS (6U) +#define USART_CR1_TCIE (0x00000040UL) +#define USART_CR1_TXEIE_POS (7U) +#define USART_CR1_TXEIE (0x00000080UL) +#define USART_CR1_PS_POS (9U) +#define USART_CR1_PS (0x00000200UL) +#define USART_CR1_PCE_POS (10U) +#define USART_CR1_PCE (0x00000400UL) +#define USART_CR1_M_POS (12U) +#define USART_CR1_M (0x00001000UL) +#define USART_CR1_OVER8_POS (15U) +#define USART_CR1_OVER8 (0x00008000UL) +#define USART_CR1_CPE_POS (16U) +#define USART_CR1_CPE (0x00010000UL) +#define USART_CR1_CFE_POS (17U) +#define USART_CR1_CFE (0x00020000UL) +#define USART_CR1_CORE_POS (19U) +#define USART_CR1_CORE (0x00080000UL) +#define USART_CR1_CRTOF_POS (20U) +#define USART_CR1_CRTOF (0x00100000UL) +#define USART_CR1_MS_POS (24U) +#define USART_CR1_MS (0x01000000UL) +#define USART_CR1_ML_POS (28U) +#define USART_CR1_ML (0x10000000UL) +#define USART_CR1_FBME_POS (29U) +#define USART_CR1_FBME (0x20000000UL) +#define USART_CR1_NFE_POS (30U) +#define USART_CR1_NFE (0x40000000UL) +#define USART_CR1_SBS_POS (31U) +#define USART_CR1_SBS (0x80000000UL) + +/* Bit definition for USART_CR2 register */ +#define USART_CR2_MPE_POS (0U) +#define USART_CR2_MPE (0x00000001UL) +#define USART_CR2_CLKC_POS (11U) +#define USART_CR2_CLKC (0x00001800UL) +#define USART_CR2_CLKC_0 (0x00000800UL) +#define USART_CR2_CLKC_1 (0x00001000UL) +#define USART_CR2_STOP_POS (13U) +#define USART_CR2_STOP (0x00002000UL) + +/* Bit definition for USART_CR3 register */ +#define USART_CR3_SCEN_POS (5U) +#define USART_CR3_SCEN (0x00000020UL) +#define USART_CR3_CTSE_POS (9U) +#define USART_CR3_CTSE (0x00000200UL) +#define USART_CR3_BCN_POS (21U) +#define USART_CR3_BCN (0x00E00000UL) + +/* Bit definition for USART_PR register */ +#define USART_PR_PSC (0x00000003UL) +#define USART_PR_PSC_0 (0x00000001UL) +#define USART_PR_PSC_1 (0x00000002UL) + +/******************************************************************************* + Bit definition for Peripheral USBFS +*******************************************************************************/ +/* Bit definition for USBFS_GVBUSCFG register */ +#define USBFS_GVBUSCFG_VBUSOVEN_POS (6U) +#define USBFS_GVBUSCFG_VBUSOVEN (0x00000040UL) +#define USBFS_GVBUSCFG_VBUSVAL_POS (7U) +#define USBFS_GVBUSCFG_VBUSVAL (0x00000080UL) + +/* Bit definition for USBFS_GAHBCFG register */ +#define USBFS_GAHBCFG_GINTMSK_POS (0U) +#define USBFS_GAHBCFG_GINTMSK (0x00000001UL) +#define USBFS_GAHBCFG_HBSTLEN_POS (1U) +#define USBFS_GAHBCFG_HBSTLEN (0x0000001EUL) +#define USBFS_GAHBCFG_DMAEN_POS (5U) +#define USBFS_GAHBCFG_DMAEN (0x00000020UL) +#define USBFS_GAHBCFG_TXFELVL_POS (7U) +#define USBFS_GAHBCFG_TXFELVL (0x00000080UL) +#define USBFS_GAHBCFG_PTXFELVL_POS (8U) +#define USBFS_GAHBCFG_PTXFELVL (0x00000100UL) + +/* Bit definition for USBFS_GUSBCFG register */ +#define USBFS_GUSBCFG_TOCAL_POS (0U) +#define USBFS_GUSBCFG_TOCAL (0x00000007UL) +#define USBFS_GUSBCFG_PHYSEL_POS (6U) +#define USBFS_GUSBCFG_PHYSEL (0x00000040UL) +#define USBFS_GUSBCFG_TRDT_POS (10U) +#define USBFS_GUSBCFG_TRDT (0x00003C00UL) +#define USBFS_GUSBCFG_FHMOD_POS (29U) +#define USBFS_GUSBCFG_FHMOD (0x20000000UL) +#define USBFS_GUSBCFG_FDMOD_POS (30U) +#define USBFS_GUSBCFG_FDMOD (0x40000000UL) + +/* Bit definition for USBFS_GRSTCTL register */ +#define USBFS_GRSTCTL_CSRST_POS (0U) +#define USBFS_GRSTCTL_CSRST (0x00000001UL) +#define USBFS_GRSTCTL_HSRST_POS (1U) +#define USBFS_GRSTCTL_HSRST (0x00000002UL) +#define USBFS_GRSTCTL_FCRST_POS (2U) +#define USBFS_GRSTCTL_FCRST (0x00000004UL) +#define USBFS_GRSTCTL_RXFFLSH_POS (4U) +#define USBFS_GRSTCTL_RXFFLSH (0x00000010UL) +#define USBFS_GRSTCTL_TXFFLSH_POS (5U) +#define USBFS_GRSTCTL_TXFFLSH (0x00000020UL) +#define USBFS_GRSTCTL_TXFNUM_POS (6U) +#define USBFS_GRSTCTL_TXFNUM (0x000007C0UL) +#define USBFS_GRSTCTL_DMAREQ_POS (30U) +#define USBFS_GRSTCTL_DMAREQ (0x40000000UL) +#define USBFS_GRSTCTL_AHBIDL_POS (31U) +#define USBFS_GRSTCTL_AHBIDL (0x80000000UL) + +/* Bit definition for USBFS_GINTSTS register */ +#define USBFS_GINTSTS_CMOD_POS (0U) +#define USBFS_GINTSTS_CMOD (0x00000001UL) +#define USBFS_GINTSTS_MMIS_POS (1U) +#define USBFS_GINTSTS_MMIS (0x00000002UL) +#define USBFS_GINTSTS_SOF_POS (3U) +#define USBFS_GINTSTS_SOF (0x00000008UL) +#define USBFS_GINTSTS_RXFNE_POS (4U) +#define USBFS_GINTSTS_RXFNE (0x00000010UL) +#define USBFS_GINTSTS_NPTXFE_POS (5U) +#define USBFS_GINTSTS_NPTXFE (0x00000020UL) +#define USBFS_GINTSTS_GINAKEFF_POS (6U) +#define USBFS_GINTSTS_GINAKEFF (0x00000040UL) +#define USBFS_GINTSTS_GONAKEFF_POS (7U) +#define USBFS_GINTSTS_GONAKEFF (0x00000080UL) +#define USBFS_GINTSTS_ESUSP_POS (10U) +#define USBFS_GINTSTS_ESUSP (0x00000400UL) +#define USBFS_GINTSTS_USBSUSP_POS (11U) +#define USBFS_GINTSTS_USBSUSP (0x00000800UL) +#define USBFS_GINTSTS_USBRST_POS (12U) +#define USBFS_GINTSTS_USBRST (0x00001000UL) +#define USBFS_GINTSTS_ENUMDNE_POS (13U) +#define USBFS_GINTSTS_ENUMDNE (0x00002000UL) +#define USBFS_GINTSTS_ISOODRP_POS (14U) +#define USBFS_GINTSTS_ISOODRP (0x00004000UL) +#define USBFS_GINTSTS_EOPF_POS (15U) +#define USBFS_GINTSTS_EOPF (0x00008000UL) +#define USBFS_GINTSTS_IEPINT_POS (18U) +#define USBFS_GINTSTS_IEPINT (0x00040000UL) +#define USBFS_GINTSTS_OEPINT_POS (19U) +#define USBFS_GINTSTS_OEPINT (0x00080000UL) +#define USBFS_GINTSTS_IISOIXFR_POS (20U) +#define USBFS_GINTSTS_IISOIXFR (0x00100000UL) +#define USBFS_GINTSTS_IPXFR_INCOMPISOOUT_POS (21U) +#define USBFS_GINTSTS_IPXFR_INCOMPISOOUT (0x00200000UL) +#define USBFS_GINTSTS_DATAFSUSP_POS (22U) +#define USBFS_GINTSTS_DATAFSUSP (0x00400000UL) +#define USBFS_GINTSTS_HPRTINT_POS (24U) +#define USBFS_GINTSTS_HPRTINT (0x01000000UL) +#define USBFS_GINTSTS_HCINT_POS (25U) +#define USBFS_GINTSTS_HCINT (0x02000000UL) +#define USBFS_GINTSTS_PTXFE_POS (26U) +#define USBFS_GINTSTS_PTXFE (0x04000000UL) +#define USBFS_GINTSTS_CIDSCHG_POS (28U) +#define USBFS_GINTSTS_CIDSCHG (0x10000000UL) +#define USBFS_GINTSTS_DISCINT_POS (29U) +#define USBFS_GINTSTS_DISCINT (0x20000000UL) +#define USBFS_GINTSTS_VBUSVINT_POS (30U) +#define USBFS_GINTSTS_VBUSVINT (0x40000000UL) +#define USBFS_GINTSTS_WKUINT_POS (31U) +#define USBFS_GINTSTS_WKUINT (0x80000000UL) + +/* Bit definition for USBFS_GINTMSK register */ +#define USBFS_GINTMSK_MMISM_POS (1U) +#define USBFS_GINTMSK_MMISM (0x00000002UL) +#define USBFS_GINTMSK_SOFM_POS (3U) +#define USBFS_GINTMSK_SOFM (0x00000008UL) +#define USBFS_GINTMSK_RXFNEM_POS (4U) +#define USBFS_GINTMSK_RXFNEM (0x00000010UL) +#define USBFS_GINTMSK_NPTXFEM_POS (5U) +#define USBFS_GINTMSK_NPTXFEM (0x00000020UL) +#define USBFS_GINTMSK_GINAKEFFM_POS (6U) +#define USBFS_GINTMSK_GINAKEFFM (0x00000040UL) +#define USBFS_GINTMSK_GONAKEFFM_POS (7U) +#define USBFS_GINTMSK_GONAKEFFM (0x00000080UL) +#define USBFS_GINTMSK_ESUSPM_POS (10U) +#define USBFS_GINTMSK_ESUSPM (0x00000400UL) +#define USBFS_GINTMSK_USBSUSPM_POS (11U) +#define USBFS_GINTMSK_USBSUSPM (0x00000800UL) +#define USBFS_GINTMSK_USBRSTM_POS (12U) +#define USBFS_GINTMSK_USBRSTM (0x00001000UL) +#define USBFS_GINTMSK_ENUMDNEM_POS (13U) +#define USBFS_GINTMSK_ENUMDNEM (0x00002000UL) +#define USBFS_GINTMSK_ISOODRPM_POS (14U) +#define USBFS_GINTMSK_ISOODRPM (0x00004000UL) +#define USBFS_GINTMSK_EOPFM_POS (15U) +#define USBFS_GINTMSK_EOPFM (0x00008000UL) +#define USBFS_GINTMSK_IEPIM_POS (18U) +#define USBFS_GINTMSK_IEPIM (0x00040000UL) +#define USBFS_GINTMSK_OEPIM_POS (19U) +#define USBFS_GINTMSK_OEPIM (0x00080000UL) +#define USBFS_GINTMSK_IISOIXFRM_POS (20U) +#define USBFS_GINTMSK_IISOIXFRM (0x00100000UL) +#define USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM_POS (21U) +#define USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM (0x00200000UL) +#define USBFS_GINTMSK_DATAFSUSPM_POS (22U) +#define USBFS_GINTMSK_DATAFSUSPM (0x00400000UL) +#define USBFS_GINTMSK_HPRTIM_POS (24U) +#define USBFS_GINTMSK_HPRTIM (0x01000000UL) +#define USBFS_GINTMSK_HCIM_POS (25U) +#define USBFS_GINTMSK_HCIM (0x02000000UL) +#define USBFS_GINTMSK_PTXFEM_POS (26U) +#define USBFS_GINTMSK_PTXFEM (0x04000000UL) +#define USBFS_GINTMSK_CIDSCHGM_POS (28U) +#define USBFS_GINTMSK_CIDSCHGM (0x10000000UL) +#define USBFS_GINTMSK_DISCIM_POS (29U) +#define USBFS_GINTMSK_DISCIM (0x20000000UL) +#define USBFS_GINTMSK_VBUSVIM_POS (30U) +#define USBFS_GINTMSK_VBUSVIM (0x40000000UL) +#define USBFS_GINTMSK_WKUIM_POS (31U) +#define USBFS_GINTMSK_WKUIM (0x80000000UL) + +/* Bit definition for USBFS_GRXSTSR register */ +#define USBFS_GRXSTSR_CHNUM_EPNUM_POS (0U) +#define USBFS_GRXSTSR_CHNUM_EPNUM (0x0000000FUL) +#define USBFS_GRXSTSR_BCNT_POS (4U) +#define USBFS_GRXSTSR_BCNT (0x00007FF0UL) +#define USBFS_GRXSTSR_DPID_POS (15U) +#define USBFS_GRXSTSR_DPID (0x00018000UL) +#define USBFS_GRXSTSR_PKTSTS_POS (17U) +#define USBFS_GRXSTSR_PKTSTS (0x001E0000UL) + +/* Bit definition for USBFS_GRXSTSP register */ +#define USBFS_GRXSTSP_CHNUM_EPNUM_POS (0U) +#define USBFS_GRXSTSP_CHNUM_EPNUM (0x0000000FUL) +#define USBFS_GRXSTSP_BCNT_POS (4U) +#define USBFS_GRXSTSP_BCNT (0x00007FF0UL) +#define USBFS_GRXSTSP_DPID_POS (15U) +#define USBFS_GRXSTSP_DPID (0x00018000UL) +#define USBFS_GRXSTSP_PKTSTS_POS (17U) +#define USBFS_GRXSTSP_PKTSTS (0x001E0000UL) + +/* Bit definition for USBFS_GRXFSIZ register */ +#define USBFS_GRXFSIZ_RXFD (0x000007FFUL) + +/* Bit definition for USBFS_HNPTXFSIZ register */ +#define USBFS_HNPTXFSIZ_NPTXFSA_POS (0U) +#define USBFS_HNPTXFSIZ_NPTXFSA (0x0000FFFFUL) +#define USBFS_HNPTXFSIZ_NPTXFD_POS (16U) +#define USBFS_HNPTXFSIZ_NPTXFD (0xFFFF0000UL) + +/* Bit definition for USBFS_HNPTXSTS register */ +#define USBFS_HNPTXSTS_NPTXFSAV_POS (0U) +#define USBFS_HNPTXSTS_NPTXFSAV (0x0000FFFFUL) +#define USBFS_HNPTXSTS_NPTQXSAV_POS (16U) +#define USBFS_HNPTXSTS_NPTQXSAV (0x00FF0000UL) +#define USBFS_HNPTXSTS_NPTXQTOP_POS (24U) +#define USBFS_HNPTXSTS_NPTXQTOP (0x7F000000UL) + +/* Bit definition for USBFS_CID register */ +#define USBFS_CID (0xFFFFFFFFUL) + +/* Bit definition for USBFS_HPTXFSIZ register */ +#define USBFS_HPTXFSIZ_PTXSA_POS (0U) +#define USBFS_HPTXFSIZ_PTXSA (0x00000FFFUL) +#define USBFS_HPTXFSIZ_PTXFD_POS (16U) +#define USBFS_HPTXFSIZ_PTXFD (0x07FF0000UL) + +/* Bit definition for USBFS_DIEPTXF register */ +#define USBFS_DIEPTXF_INEPTXSA_POS (0U) +#define USBFS_DIEPTXF_INEPTXSA (0x00000FFFUL) +#define USBFS_DIEPTXF_INEPTXFD_POS (16U) +#define USBFS_DIEPTXF_INEPTXFD (0x03FF0000UL) + +/* Bit definition for USBFS_HCFG register */ +#define USBFS_HCFG_FSLSPCS_POS (0U) +#define USBFS_HCFG_FSLSPCS (0x00000003UL) +#define USBFS_HCFG_FSLSS_POS (2U) +#define USBFS_HCFG_FSLSS (0x00000004UL) + +/* Bit definition for USBFS_HFIR register */ +#define USBFS_HFIR_FRIVL (0x0000FFFFUL) + +/* Bit definition for USBFS_HFNUM register */ +#define USBFS_HFNUM_FRNUM_POS (0U) +#define USBFS_HFNUM_FRNUM (0x0000FFFFUL) +#define USBFS_HFNUM_FTREM_POS (16U) +#define USBFS_HFNUM_FTREM (0xFFFF0000UL) + +/* Bit definition for USBFS_HPTXSTS register */ +#define USBFS_HPTXSTS_PTXFSAVL_POS (0U) +#define USBFS_HPTXSTS_PTXFSAVL (0x0000FFFFUL) +#define USBFS_HPTXSTS_PTXQSAV_POS (16U) +#define USBFS_HPTXSTS_PTXQSAV (0x00FF0000UL) +#define USBFS_HPTXSTS_PTXQTOP_POS (24U) +#define USBFS_HPTXSTS_PTXQTOP (0xFF000000UL) + +/* Bit definition for USBFS_HAINT register */ +#define USBFS_HAINT_HAINT (0x00000FFFUL) + +/* Bit definition for USBFS_HAINTMSK register */ +#define USBFS_HAINTMSK_HAINTM (0x00000FFFUL) + +/* Bit definition for USBFS_HPRT register */ +#define USBFS_HPRT_PCSTS_POS (0U) +#define USBFS_HPRT_PCSTS (0x00000001UL) +#define USBFS_HPRT_PCDET_POS (1U) +#define USBFS_HPRT_PCDET (0x00000002UL) +#define USBFS_HPRT_PENA_POS (2U) +#define USBFS_HPRT_PENA (0x00000004UL) +#define USBFS_HPRT_PENCHNG_POS (3U) +#define USBFS_HPRT_PENCHNG (0x00000008UL) +#define USBFS_HPRT_PRES_POS (6U) +#define USBFS_HPRT_PRES (0x00000040UL) +#define USBFS_HPRT_PSUSP_POS (7U) +#define USBFS_HPRT_PSUSP (0x00000080UL) +#define USBFS_HPRT_PRST_POS (8U) +#define USBFS_HPRT_PRST (0x00000100UL) +#define USBFS_HPRT_PLSTS_POS (10U) +#define USBFS_HPRT_PLSTS (0x00000C00UL) +#define USBFS_HPRT_PWPR_POS (12U) +#define USBFS_HPRT_PWPR (0x00001000UL) +#define USBFS_HPRT_PSPD_POS (17U) +#define USBFS_HPRT_PSPD (0x00060000UL) + +/* Bit definition for USBFS_HCCHAR register */ +#define USBFS_HCCHAR_MPSIZ_POS (0U) +#define USBFS_HCCHAR_MPSIZ (0x000007FFUL) +#define USBFS_HCCHAR_EPNUM_POS (11U) +#define USBFS_HCCHAR_EPNUM (0x00007800UL) +#define USBFS_HCCHAR_EPDIR_POS (15U) +#define USBFS_HCCHAR_EPDIR (0x00008000UL) +#define USBFS_HCCHAR_LSDEV_POS (17U) +#define USBFS_HCCHAR_LSDEV (0x00020000UL) +#define USBFS_HCCHAR_EPTYP_POS (18U) +#define USBFS_HCCHAR_EPTYP (0x000C0000UL) +#define USBFS_HCCHAR_DAD_POS (22U) +#define USBFS_HCCHAR_DAD (0x1FC00000UL) +#define USBFS_HCCHAR_ODDFRM_POS (29U) +#define USBFS_HCCHAR_ODDFRM (0x20000000UL) +#define USBFS_HCCHAR_CHDIS_POS (30U) +#define USBFS_HCCHAR_CHDIS (0x40000000UL) +#define USBFS_HCCHAR_CHENA_POS (31U) +#define USBFS_HCCHAR_CHENA (0x80000000UL) + +/* Bit definition for USBFS_HCINT register */ +#define USBFS_HCINT_XFRC_POS (0U) +#define USBFS_HCINT_XFRC (0x00000001UL) +#define USBFS_HCINT_CHH_POS (1U) +#define USBFS_HCINT_CHH (0x00000002UL) +#define USBFS_HCINT_STALL_POS (3U) +#define USBFS_HCINT_STALL (0x00000008UL) +#define USBFS_HCINT_NAK_POS (4U) +#define USBFS_HCINT_NAK (0x00000010UL) +#define USBFS_HCINT_ACK_POS (5U) +#define USBFS_HCINT_ACK (0x00000020UL) +#define USBFS_HCINT_TXERR_POS (7U) +#define USBFS_HCINT_TXERR (0x00000080UL) +#define USBFS_HCINT_BBERR_POS (8U) +#define USBFS_HCINT_BBERR (0x00000100UL) +#define USBFS_HCINT_FRMOR_POS (9U) +#define USBFS_HCINT_FRMOR (0x00000200UL) +#define USBFS_HCINT_DTERR_POS (10U) +#define USBFS_HCINT_DTERR (0x00000400UL) + +/* Bit definition for USBFS_HCINTMSK register */ +#define USBFS_HCINTMSK_XFRCM_POS (0U) +#define USBFS_HCINTMSK_XFRCM (0x00000001UL) +#define USBFS_HCINTMSK_CHHM_POS (1U) +#define USBFS_HCINTMSK_CHHM (0x00000002UL) +#define USBFS_HCINTMSK_STALLM_POS (3U) +#define USBFS_HCINTMSK_STALLM (0x00000008UL) +#define USBFS_HCINTMSK_NAKM_POS (4U) +#define USBFS_HCINTMSK_NAKM (0x00000010UL) +#define USBFS_HCINTMSK_ACKM_POS (5U) +#define USBFS_HCINTMSK_ACKM (0x00000020UL) +#define USBFS_HCINTMSK_TXERRM_POS (7U) +#define USBFS_HCINTMSK_TXERRM (0x00000080UL) +#define USBFS_HCINTMSK_BBERRM_POS (8U) +#define USBFS_HCINTMSK_BBERRM (0x00000100UL) +#define USBFS_HCINTMSK_FRMORM_POS (9U) +#define USBFS_HCINTMSK_FRMORM (0x00000200UL) +#define USBFS_HCINTMSK_DTERRM_POS (10U) +#define USBFS_HCINTMSK_DTERRM (0x00000400UL) + +/* Bit definition for USBFS_HCTSIZ register */ +#define USBFS_HCTSIZ_XFRSIZ_POS (0U) +#define USBFS_HCTSIZ_XFRSIZ (0x0007FFFFUL) +#define USBFS_HCTSIZ_PKTCNT_POS (19U) +#define USBFS_HCTSIZ_PKTCNT (0x1FF80000UL) +#define USBFS_HCTSIZ_DPID_POS (29U) +#define USBFS_HCTSIZ_DPID (0x60000000UL) + +/* Bit definition for USBFS_HCDMA register */ +#define USBFS_HCDMA (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DCFG register */ +#define USBFS_DCFG_DSPD_POS (0U) +#define USBFS_DCFG_DSPD (0x00000003UL) +#define USBFS_DCFG_NZLSOHSK_POS (2U) +#define USBFS_DCFG_NZLSOHSK (0x00000004UL) +#define USBFS_DCFG_DAD_POS (4U) +#define USBFS_DCFG_DAD (0x000007F0UL) +#define USBFS_DCFG_PFIVL_POS (11U) +#define USBFS_DCFG_PFIVL (0x00001800UL) + +/* Bit definition for USBFS_DCTL register */ +#define USBFS_DCTL_RWUSIG_POS (0U) +#define USBFS_DCTL_RWUSIG (0x00000001UL) +#define USBFS_DCTL_SDIS_POS (1U) +#define USBFS_DCTL_SDIS (0x00000002UL) +#define USBFS_DCTL_GINSTS_POS (2U) +#define USBFS_DCTL_GINSTS (0x00000004UL) +#define USBFS_DCTL_GONSTS_POS (3U) +#define USBFS_DCTL_GONSTS (0x00000008UL) +#define USBFS_DCTL_SGINAK_POS (7U) +#define USBFS_DCTL_SGINAK (0x00000080UL) +#define USBFS_DCTL_CGINAK_POS (8U) +#define USBFS_DCTL_CGINAK (0x00000100UL) +#define USBFS_DCTL_SGONAK_POS (9U) +#define USBFS_DCTL_SGONAK (0x00000200UL) +#define USBFS_DCTL_CGONAK_POS (10U) +#define USBFS_DCTL_CGONAK (0x00000400UL) +#define USBFS_DCTL_POPRGDNE_POS (11U) +#define USBFS_DCTL_POPRGDNE (0x00000800UL) + +/* Bit definition for USBFS_DSTS register */ +#define USBFS_DSTS_SUSPSTS_POS (0U) +#define USBFS_DSTS_SUSPSTS (0x00000001UL) +#define USBFS_DSTS_ENUMSPD_POS (1U) +#define USBFS_DSTS_ENUMSPD (0x00000006UL) +#define USBFS_DSTS_EERR_POS (3U) +#define USBFS_DSTS_EERR (0x00000008UL) +#define USBFS_DSTS_FNSOF_POS (8U) +#define USBFS_DSTS_FNSOF (0x003FFF00UL) + +/* Bit definition for USBFS_DIEPMSK register */ +#define USBFS_DIEPMSK_XFRCM_POS (0U) +#define USBFS_DIEPMSK_XFRCM (0x00000001UL) +#define USBFS_DIEPMSK_EPDM_POS (1U) +#define USBFS_DIEPMSK_EPDM (0x00000002UL) +#define USBFS_DIEPMSK_TOM_POS (3U) +#define USBFS_DIEPMSK_TOM (0x00000008UL) +#define USBFS_DIEPMSK_TTXFEMSK_POS (4U) +#define USBFS_DIEPMSK_TTXFEMSK (0x00000010UL) +#define USBFS_DIEPMSK_INEPNMM_POS (5U) +#define USBFS_DIEPMSK_INEPNMM (0x00000020UL) +#define USBFS_DIEPMSK_INEPNEM_POS (6U) +#define USBFS_DIEPMSK_INEPNEM (0x00000040UL) + +/* Bit definition for USBFS_DOEPMSK register */ +#define USBFS_DOEPMSK_XFRCM_POS (0U) +#define USBFS_DOEPMSK_XFRCM (0x00000001UL) +#define USBFS_DOEPMSK_EPDM_POS (1U) +#define USBFS_DOEPMSK_EPDM (0x00000002UL) +#define USBFS_DOEPMSK_STUPM_POS (3U) +#define USBFS_DOEPMSK_STUPM (0x00000008UL) +#define USBFS_DOEPMSK_OTEPDM_POS (4U) +#define USBFS_DOEPMSK_OTEPDM (0x00000010UL) + +/* Bit definition for USBFS_DAINT register */ +#define USBFS_DAINT_IEPINT_POS (0U) +#define USBFS_DAINT_IEPINT (0x0000003FUL) +#define USBFS_DAINT_OEPINT_POS (16U) +#define USBFS_DAINT_OEPINT (0x003F0000UL) + +/* Bit definition for USBFS_DAINTMSK register */ +#define USBFS_DAINTMSK_IEPINTM_POS (0U) +#define USBFS_DAINTMSK_IEPINTM (0x0000003FUL) +#define USBFS_DAINTMSK_OEPINTM_POS (16U) +#define USBFS_DAINTMSK_OEPINTM (0x003F0000UL) + +/* Bit definition for USBFS_DIEPEMPMSK register */ +#define USBFS_DIEPEMPMSK_INEPTXFEM (0x0000003FUL) + +/* Bit definition for USBFS_DIEPCTL0 register */ +#define USBFS_DIEPCTL0_MPSIZ_POS (0U) +#define USBFS_DIEPCTL0_MPSIZ (0x00000003UL) +#define USBFS_DIEPCTL0_USBAEP_POS (15U) +#define USBFS_DIEPCTL0_USBAEP (0x00008000UL) +#define USBFS_DIEPCTL0_NAKSTS_POS (17U) +#define USBFS_DIEPCTL0_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL0_EPTYP_POS (18U) +#define USBFS_DIEPCTL0_EPTYP (0x000C0000UL) +#define USBFS_DIEPCTL0_STALL_POS (21U) +#define USBFS_DIEPCTL0_STALL (0x00200000UL) +#define USBFS_DIEPCTL0_TXFNUM_POS (22U) +#define USBFS_DIEPCTL0_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL0_CNAK_POS (26U) +#define USBFS_DIEPCTL0_CNAK (0x04000000UL) +#define USBFS_DIEPCTL0_SNAK_POS (27U) +#define USBFS_DIEPCTL0_SNAK (0x08000000UL) +#define USBFS_DIEPCTL0_EPDIS_POS (30U) +#define USBFS_DIEPCTL0_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL0_EPENA_POS (31U) +#define USBFS_DIEPCTL0_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPINT register */ +#define USBFS_DIEPINT_XFRC_POS (0U) +#define USBFS_DIEPINT_XFRC (0x00000001UL) +#define USBFS_DIEPINT_EPDISD_POS (1U) +#define USBFS_DIEPINT_EPDISD (0x00000002UL) +#define USBFS_DIEPINT_TOC_POS (3U) +#define USBFS_DIEPINT_TOC (0x00000008UL) +#define USBFS_DIEPINT_TTXFE_POS (4U) +#define USBFS_DIEPINT_TTXFE (0x00000010UL) +#define USBFS_DIEPINT_INEPNE_POS (6U) +#define USBFS_DIEPINT_INEPNE (0x00000040UL) +#define USBFS_DIEPINT_TXFE_POS (7U) +#define USBFS_DIEPINT_TXFE (0x00000080UL) + +/* Bit definition for USBFS_DIEPTSIZ0 register */ +#define USBFS_DIEPTSIZ0_XFRSIZ_POS (0U) +#define USBFS_DIEPTSIZ0_XFRSIZ (0x0000007FUL) +#define USBFS_DIEPTSIZ0_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ0_PKTCNT (0x00180000UL) + +/* Bit definition for USBFS_DIEPDMA register */ +#define USBFS_DIEPDMA (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DTXFSTS register */ +#define USBFS_DTXFSTS_INEPTFSAV (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL register */ +#define USBFS_DIEPCTL_MPSIZ_POS (0U) +#define USBFS_DIEPCTL_MPSIZ (0x000007FFUL) +#define USBFS_DIEPCTL_USBAEP_POS (15U) +#define USBFS_DIEPCTL_USBAEP (0x00008000UL) +#define USBFS_DIEPCTL_EONUM_DPID_POS (16U) +#define USBFS_DIEPCTL_EONUM_DPID (0x00010000UL) +#define USBFS_DIEPCTL_NAKSTS_POS (17U) +#define USBFS_DIEPCTL_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL_EPTYP_POS (18U) +#define USBFS_DIEPCTL_EPTYP (0x000C0000UL) +#define USBFS_DIEPCTL_STALL_POS (21U) +#define USBFS_DIEPCTL_STALL (0x00200000UL) +#define USBFS_DIEPCTL_TXFNUM_POS (22U) +#define USBFS_DIEPCTL_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL_CNAK_POS (26U) +#define USBFS_DIEPCTL_CNAK (0x04000000UL) +#define USBFS_DIEPCTL_SNAK_POS (27U) +#define USBFS_DIEPCTL_SNAK (0x08000000UL) +#define USBFS_DIEPCTL_SD0PID_SEVNFRM_POS (28U) +#define USBFS_DIEPCTL_SD0PID_SEVNFRM (0x10000000UL) +#define USBFS_DIEPCTL_SODDFRM_POS (29U) +#define USBFS_DIEPCTL_SODDFRM (0x20000000UL) +#define USBFS_DIEPCTL_EPDIS_POS (30U) +#define USBFS_DIEPCTL_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL_EPENA_POS (31U) +#define USBFS_DIEPCTL_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPTSIZ register */ +#define USBFS_DIEPTSIZ_XFRSIZ_POS (0U) +#define USBFS_DIEPTSIZ_XFRSIZ (0x0007FFFFUL) +#define USBFS_DIEPTSIZ_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ_PKTCNT (0x1FF80000UL) + +/* Bit definition for USBFS_DOEPCTL0 register */ +#define USBFS_DOEPCTL0_MPSIZ_POS (0U) +#define USBFS_DOEPCTL0_MPSIZ (0x00000003UL) +#define USBFS_DOEPCTL0_USBAEP_POS (15U) +#define USBFS_DOEPCTL0_USBAEP (0x00008000UL) +#define USBFS_DOEPCTL0_NAKSTS_POS (17U) +#define USBFS_DOEPCTL0_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL0_EPTYP_POS (18U) +#define USBFS_DOEPCTL0_EPTYP (0x000C0000UL) +#define USBFS_DOEPCTL0_SNPM_POS (20U) +#define USBFS_DOEPCTL0_SNPM (0x00100000UL) +#define USBFS_DOEPCTL0_STALL_POS (21U) +#define USBFS_DOEPCTL0_STALL (0x00200000UL) +#define USBFS_DOEPCTL0_CNAK_POS (26U) +#define USBFS_DOEPCTL0_CNAK (0x04000000UL) +#define USBFS_DOEPCTL0_SNAK_POS (27U) +#define USBFS_DOEPCTL0_SNAK (0x08000000UL) +#define USBFS_DOEPCTL0_EPDIS_POS (30U) +#define USBFS_DOEPCTL0_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL0_EPENA_POS (31U) +#define USBFS_DOEPCTL0_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPINT register */ +#define USBFS_DOEPINT_XFRC_POS (0U) +#define USBFS_DOEPINT_XFRC (0x00000001UL) +#define USBFS_DOEPINT_EPDISD_POS (1U) +#define USBFS_DOEPINT_EPDISD (0x00000002UL) +#define USBFS_DOEPINT_STUP_POS (3U) +#define USBFS_DOEPINT_STUP (0x00000008UL) +#define USBFS_DOEPINT_OTEPDIS_POS (4U) +#define USBFS_DOEPINT_OTEPDIS (0x00000010UL) +#define USBFS_DOEPINT_B2BSTUP_POS (6U) +#define USBFS_DOEPINT_B2BSTUP (0x00000040UL) + +/* Bit definition for USBFS_DOEPTSIZ0 register */ +#define USBFS_DOEPTSIZ0_XFRSIZ_POS (0U) +#define USBFS_DOEPTSIZ0_XFRSIZ (0x0000007FUL) +#define USBFS_DOEPTSIZ0_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ0_PKTCNT (0x00080000UL) +#define USBFS_DOEPTSIZ0_STUPCNT_POS (29U) +#define USBFS_DOEPTSIZ0_STUPCNT (0x60000000UL) + +/* Bit definition for USBFS_DOEPDMA register */ +#define USBFS_DOEPDMA (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DOEPCTL register */ +#define USBFS_DOEPCTL_MPSIZ_POS (0U) +#define USBFS_DOEPCTL_MPSIZ (0x000007FFUL) +#define USBFS_DOEPCTL_USBAEP_POS (15U) +#define USBFS_DOEPCTL_USBAEP (0x00008000UL) +#define USBFS_DOEPCTL_DPID_POS (16U) +#define USBFS_DOEPCTL_DPID (0x00010000UL) +#define USBFS_DOEPCTL_NAKSTS_POS (17U) +#define USBFS_DOEPCTL_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL_EPTYP_POS (18U) +#define USBFS_DOEPCTL_EPTYP (0x000C0000UL) +#define USBFS_DOEPCTL_SNPM_POS (20U) +#define USBFS_DOEPCTL_SNPM (0x00100000UL) +#define USBFS_DOEPCTL_STALL_POS (21U) +#define USBFS_DOEPCTL_STALL (0x00200000UL) +#define USBFS_DOEPCTL_CNAK_POS (26U) +#define USBFS_DOEPCTL_CNAK (0x04000000UL) +#define USBFS_DOEPCTL_SNAK_POS (27U) +#define USBFS_DOEPCTL_SNAK (0x08000000UL) +#define USBFS_DOEPCTL_SD0PID_POS (28U) +#define USBFS_DOEPCTL_SD0PID (0x10000000UL) +#define USBFS_DOEPCTL_SD1PID_POS (29U) +#define USBFS_DOEPCTL_SD1PID (0x20000000UL) +#define USBFS_DOEPCTL_EPDIS_POS (30U) +#define USBFS_DOEPCTL_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL_EPENA_POS (31U) +#define USBFS_DOEPCTL_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPTSIZ register */ +#define USBFS_DOEPTSIZ_XFRSIZ_POS (0U) +#define USBFS_DOEPTSIZ_XFRSIZ (0x0007FFFFUL) +#define USBFS_DOEPTSIZ_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ_PKTCNT (0x1FF80000UL) + +/* Bit definition for USBFS_GCCTL register */ +#define USBFS_GCCTL_STPPCLK_POS (0U) +#define USBFS_GCCTL_STPPCLK (0x00000001UL) +#define USBFS_GCCTL_GATEHCLK_POS (1U) +#define USBFS_GCCTL_GATEHCLK (0x00000002UL) + +/******************************************************************************* + Bit definition for Peripheral WDT +*******************************************************************************/ +/* Bit definition for WDT_CR register */ +#define WDT_CR_PERI_POS (0U) +#define WDT_CR_PERI (0x00000003UL) +#define WDT_CR_PERI_0 (0x00000001UL) +#define WDT_CR_PERI_1 (0x00000002UL) +#define WDT_CR_CKS_POS (4U) +#define WDT_CR_CKS (0x000000F0UL) +#define WDT_CR_WDPT_POS (8U) +#define WDT_CR_WDPT (0x00000F00UL) +#define WDT_CR_SLPOFF_POS (16U) +#define WDT_CR_SLPOFF (0x00010000UL) +#define WDT_CR_ITS_POS (31U) +#define WDT_CR_ITS (0x80000000UL) + +/* Bit definition for WDT_SR register */ +#define WDT_SR_CNT_POS (0U) +#define WDT_SR_CNT (0x0000FFFFUL) +#define WDT_SR_UDF_POS (16U) +#define WDT_SR_UDF (0x00010000UL) +#define WDT_SR_REF_POS (17U) +#define WDT_SR_REF (0x00020000UL) + +/* Bit definition for WDT_RR register */ +#define WDT_RR_RF (0x0000FFFFUL) + +/******************************************************************************/ +/* Device Specific Registers bit_band structure */ +/******************************************************************************/ + +typedef struct { + __IO uint32_t STRT; + uint32_t RESERVED0[7]; +} stc_adc_str_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t CLREN; + __IO uint32_t DFMT; + uint32_t RESERVED1[8]; +} stc_adc_cr0_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t RSCHSEL; + uint32_t RESERVED1[13]; +} stc_adc_cr1_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t TRGENA; + uint32_t RESERVED1[7]; + __IO uint32_t TRGENB; +} stc_adc_trgsr_bit_t; + +typedef struct { + __IO uint32_t EOCAF; + __IO uint32_t EOCBF; + uint32_t RESERVED0[6]; +} stc_adc_isr_bit_t; + +typedef struct { + __IO uint32_t EOCAIEN; + __IO uint32_t EOCBIEN; + uint32_t RESERVED0[6]; +} stc_adc_icr_bit_t; + +typedef struct { + __IO uint32_t SYNCEN; + uint32_t RESERVED0[15]; +} stc_adc_synccr_bit_t; + +typedef struct { + __IO uint32_t AWDEN; + uint32_t RESERVED0[3]; + __IO uint32_t AWDMD; + uint32_t RESERVED1[3]; + __IO uint32_t AWDIEN; + uint32_t RESERVED2[7]; +} stc_adc_awdcr_bit_t; + +typedef struct { + __IO uint32_t PGAVSSEN; + uint32_t RESERVED0[15]; +} stc_adc_pgainsr1_bit_t; + +typedef struct { + __IO uint32_t START; + __IO uint32_t MODE; + uint32_t RESERVED0[30]; +} stc_aes_cr_bit_t; + +typedef struct { + __O uint32_t STRG; + uint32_t RESERVED0[31]; +} stc_aos_intsfttrg_bit_t; + +typedef struct { + __IO uint32_t NFEN1; + uint32_t RESERVED0[7]; + __IO uint32_t NFEN2; + uint32_t RESERVED1[7]; + __IO uint32_t NFEN3; + uint32_t RESERVED2[7]; + __IO uint32_t NFEN4; + uint32_t RESERVED3[7]; +} stc_aos_pevntnfcr_bit_t; + +typedef struct { + __IO uint32_t BUSOFF; + __I uint32_t TACTIVE; + __I uint32_t RACTIVE; + __IO uint32_t TSSS; + __IO uint32_t TPSS; + __IO uint32_t LBMI; + __IO uint32_t LBME; + __IO uint32_t RESET; +} stc_can_cfg_stat_bit_t; + +typedef struct { + __IO uint32_t TSA; + __IO uint32_t TSALL; + __IO uint32_t TSONE; + __IO uint32_t TPA; + __IO uint32_t TPE; + uint32_t RESERVED0[1]; + __IO uint32_t LOM; + __IO uint32_t TBSEL; +} stc_can_tcmd_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t TTTBM; + __IO uint32_t TSMODE; + __IO uint32_t TSNEXT; + uint32_t RESERVED1[1]; +} stc_can_tctrl_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t RBALL; + __IO uint32_t RREL; + __I uint32_t ROV; + __IO uint32_t ROM; + __IO uint32_t SACK; +} stc_can_rctrl_bit_t; + +typedef struct { + __I uint32_t TSFF; + __IO uint32_t EIE; + __IO uint32_t TSIE; + __IO uint32_t TPIE; + __IO uint32_t RAFIE; + __IO uint32_t RFIE; + __IO uint32_t ROIE; + __IO uint32_t RIE; +} stc_can_rtie_bit_t; + +typedef struct { + __IO uint32_t AIF; + __IO uint32_t EIF; + __IO uint32_t TSIF; + __IO uint32_t TPIF; + __IO uint32_t RAFIF; + __IO uint32_t RFIF; + __IO uint32_t ROIF; + __IO uint32_t RIF; +} stc_can_rtif_bit_t; + +typedef struct { + __IO uint32_t BEIF; + __IO uint32_t BEIE; + __IO uint32_t ALIF; + __IO uint32_t ALIE; + __IO uint32_t EPIF; + __IO uint32_t EPIE; + __I uint32_t EPASS; + __I uint32_t EWARN; +} stc_can_errint_bit_t; + +typedef struct { + uint32_t RESERVED0[5]; + __IO uint32_t SELMASK; + uint32_t RESERVED1[2]; +} stc_can_acfctrl_bit_t; + +typedef struct { + __IO uint32_t AE_1; + __IO uint32_t AE_2; + __IO uint32_t AE_3; + __IO uint32_t AE_4; + __IO uint32_t AE_5; + __IO uint32_t AE_6; + __IO uint32_t AE_7; + __IO uint32_t AE_8; +} stc_can_acfen_bit_t; + +typedef struct { + uint32_t RESERVED0[29]; + __IO uint32_t AIDE; + __IO uint32_t AIDEE; + uint32_t RESERVED1[1]; +} stc_can_acf_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t TBF; + __IO uint32_t TBE; +} stc_can_tbslot_bit_t; + +typedef struct { + __IO uint32_t TTEN; + uint32_t RESERVED0[2]; + __IO uint32_t TTIF; + __IO uint32_t TTIE; + __IO uint32_t TEIF; + __IO uint32_t WTIF; + __IO uint32_t WTIE; +} stc_can_ttcfg_bit_t; + +typedef struct { + uint32_t RESERVED0[31]; + __IO uint32_t REF_IDE; +} stc_can_ref_msg_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t IEN; + __IO uint32_t CVSEN; + uint32_t RESERVED1[3]; + __IO uint32_t OUTEN; + __IO uint32_t INV; + __IO uint32_t CMPOE; + __IO uint32_t CMPON; +} stc_cmp_ctrl_bit_t; + +typedef struct { + __IO uint32_t RVSL0; + __IO uint32_t RVSL1; + __IO uint32_t RVSL2; + __IO uint32_t RVSL3; + uint32_t RESERVED0[4]; + __IO uint32_t CVSL0; + __IO uint32_t CVSL1; + __IO uint32_t CVSL2; + __IO uint32_t CVSL3; + __IO uint32_t C4SL0; + __IO uint32_t C4SL1; + __IO uint32_t C4SL2; + uint32_t RESERVED1[1]; +} stc_cmp_vltsel_bit_t; + +typedef struct { + __I uint32_t OMON; + uint32_t RESERVED0[15]; +} stc_cmp_outmon_bit_t; + +typedef struct { + __IO uint32_t DA1EN; + __IO uint32_t DA2EN; + uint32_t RESERVED0[14]; +} stc_cmp_common_dacr_bit_t; + +typedef struct { + __IO uint32_t DA1SW; + __IO uint32_t DA2SW; + uint32_t RESERVED0[2]; + __IO uint32_t VREFSW; + uint32_t RESERVED1[11]; +} stc_cmp_common_rvadc_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t CR; + __IO uint32_t REFIN; + __IO uint32_t REFOUT; + __IO uint32_t XOROUT; + uint32_t RESERVED1[27]; +} stc_crc_cr_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __I uint32_t CRCFLAG_16; + uint32_t RESERVED1[15]; +} stc_crc_reslt_bit_t; + +typedef struct { + __I uint32_t CRCFLAG_32; + uint32_t RESERVED0[31]; +} stc_crc_flg_bit_t; + +typedef struct { + __IO uint32_t CDBGPWRUPREQ; + __IO uint32_t CDBGPWRUPACK; + uint32_t RESERVED0[30]; +} stc_dbgc_mcudbgstat_bit_t; + +typedef struct { + __IO uint32_t SWDTSTP; + __IO uint32_t WDTSTP; + __IO uint32_t RTCSTP; + uint32_t RESERVED0[11]; + __IO uint32_t TMR01STP; + __IO uint32_t TMR02STP; + uint32_t RESERVED1[4]; + __IO uint32_t TMR41STP; + __IO uint32_t TMR42STP; + __IO uint32_t TMR43STP; + __IO uint32_t TM61STP; + __IO uint32_t TM62STP; + __IO uint32_t TMR63STP; + __IO uint32_t TMRA1STP; + __IO uint32_t TMRA2STP; + __IO uint32_t TMRA3STP; + __IO uint32_t TMRA4STP; + __IO uint32_t TMRA5STP; + __IO uint32_t TMRA6STP; +} stc_dbgc_mcustpctl_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t TRACEIOEN; + uint32_t RESERVED1[29]; +} stc_dbgc_mcutracectl_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t COMPTRG; + uint32_t RESERVED1[22]; + __IO uint32_t INTEN; +} stc_dcu_ctl_bit_t; + +typedef struct { + __O uint32_t FLAG_OP; + __O uint32_t FLAG_LS2; + __O uint32_t FLAG_EQ2; + __O uint32_t FLAG_GT2; + __O uint32_t FLAG_LS1; + __O uint32_t FLAG_EQ1; + __O uint32_t FLAG_GT1; + uint32_t RESERVED0[25]; +} stc_dcu_flag_bit_t; + +typedef struct { + __O uint32_t CLR_OP; + __O uint32_t CLR_LS2; + __O uint32_t CLR_EQ2; + __O uint32_t CLR_GT2; + __O uint32_t CLR_LS1; + __O uint32_t CLR_EQ1; + __O uint32_t CLR_GT1; + uint32_t RESERVED0[25]; +} stc_dcu_flagclr_bit_t; + +typedef struct { + __IO uint32_t SEL_OP; + __IO uint32_t SEL_LS2; + __IO uint32_t SEL_EQ2; + __IO uint32_t SEL_GT2; + __IO uint32_t SEL_LS1; + __IO uint32_t SEL_EQ1; + __IO uint32_t SEL_GT1; + uint32_t RESERVED0[25]; +} stc_dcu_intevtsel_bit_t; + +typedef struct { + __IO uint32_t EN; + uint32_t RESERVED0[31]; +} stc_dma_en_bit_t; + +typedef struct { + __I uint32_t TRNERR0; + __I uint32_t TRNERR1; + __I uint32_t TRNERR2; + __I uint32_t TRNERR3; + uint32_t RESERVED0[12]; + __I uint32_t REQERR0; + __I uint32_t REQERR1; + __I uint32_t REQERR2; + __I uint32_t REQERR3; + uint32_t RESERVED1[12]; +} stc_dma_intstat0_bit_t; + +typedef struct { + __I uint32_t TC0; + __I uint32_t TC1; + __I uint32_t TC2; + __I uint32_t TC3; + uint32_t RESERVED0[12]; + __I uint32_t BTC0; + __I uint32_t BTC1; + __I uint32_t BTC2; + __I uint32_t BTC3; + uint32_t RESERVED1[12]; +} stc_dma_intstat1_bit_t; + +typedef struct { + __IO uint32_t MSKTRNERR0; + __IO uint32_t MSKTRNERR1; + __IO uint32_t MSKTRNERR2; + __IO uint32_t MSKTRNERR3; + uint32_t RESERVED0[12]; + __IO uint32_t MSKREQERR0; + __IO uint32_t MSKREQERR1; + __IO uint32_t MSKREQERR2; + __IO uint32_t MSKREQERR3; + uint32_t RESERVED1[12]; +} stc_dma_intmask0_bit_t; + +typedef struct { + __IO uint32_t MSKTC0; + __IO uint32_t MSKTC1; + __IO uint32_t MSKTC2; + __IO uint32_t MSKTC3; + uint32_t RESERVED0[12]; + __IO uint32_t MSKBTC0; + __IO uint32_t MSKBTC1; + __IO uint32_t MSKBTC2; + __IO uint32_t MSKBTC3; + uint32_t RESERVED1[12]; +} stc_dma_intmask1_bit_t; + +typedef struct { + __O uint32_t CLRTRNERR0; + __O uint32_t CLRTRNERR1; + __O uint32_t CLRTRNERR2; + __O uint32_t CLRTRNERR3; + uint32_t RESERVED0[12]; + __O uint32_t CLRREQERR0; + __O uint32_t CLRREQERR1; + __O uint32_t CLRREQERR2; + __O uint32_t CLRREQERR3; + uint32_t RESERVED1[12]; +} stc_dma_intclr0_bit_t; + +typedef struct { + __O uint32_t CLRTC0; + __O uint32_t CLRTC1; + __O uint32_t CLRTC2; + __O uint32_t CLRTC3; + uint32_t RESERVED0[12]; + __O uint32_t CLRBTC0; + __O uint32_t CLRBTC1; + __O uint32_t CLRBTC2; + __O uint32_t CLRBTC3; + uint32_t RESERVED1[12]; +} stc_dma_intclr1_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __I uint32_t RCFGREQ; + uint32_t RESERVED1[16]; +} stc_dma_reqstat_bit_t; + +typedef struct { + __I uint32_t DMAACT; + __I uint32_t RCFGACT; + uint32_t RESERVED0[30]; +} stc_dma_chstat_bit_t; + +typedef struct { + __IO uint32_t RCFGEN; + __IO uint32_t RCFGLLP; + uint32_t RESERVED0[30]; +} stc_dma_rcfgctl_bit_t; + +typedef struct { + __O uint32_t SWREQ0; + __O uint32_t SWREQ1; + __O uint32_t SWREQ2; + __O uint32_t SWREQ3; + __O uint32_t SWREQ4; + __O uint32_t SWREQ5; + __O uint32_t SWREQ6; + __O uint32_t SWREQ7; + uint32_t RESERVED0[7]; + __O uint32_t SWRCFGREQ; + uint32_t RESERVED1[16]; +} stc_dma_swreq_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t SRPTEN; + __IO uint32_t DRPTEN; + __IO uint32_t SNSEQEN; + __IO uint32_t DNSEQEN; + uint32_t RESERVED1[2]; + __IO uint32_t LLPEN; + __IO uint32_t LLPRUN; + __IO uint32_t IE; + uint32_t RESERVED2[19]; +} stc_dma_chctl_bit_t; + +typedef struct { + __IO uint32_t FSTP; + uint32_t RESERVED0[31]; +} stc_efm_fstp_bit_t; + +typedef struct { + __IO uint32_t SLPMD; + uint32_t RESERVED0[7]; + __IO uint32_t LVM; + uint32_t RESERVED1[7]; + __IO uint32_t CACHE; + uint32_t RESERVED2[7]; + __IO uint32_t CRST; + uint32_t RESERVED3[7]; +} stc_efm_frmc_bit_t; + +typedef struct { + __IO uint32_t PEMODE; + uint32_t RESERVED0[7]; + __IO uint32_t BUSHLDCTL; + uint32_t RESERVED1[23]; +} stc_efm_fwmc_bit_t; + +typedef struct { + __I uint32_t PEWERR; + __I uint32_t PEPRTERR; + __I uint32_t PGSZERR; + __I uint32_t PGMISMTCH; + __I uint32_t OPTEND; + __I uint32_t COLERR; + uint32_t RESERVED0[2]; + __I uint32_t RDY; + uint32_t RESERVED1[23]; +} stc_efm_fsr_bit_t; + +typedef struct { + __IO uint32_t PEWERRCLR; + __IO uint32_t PEPRTERRCLR; + __IO uint32_t PGSZERRCLR; + __IO uint32_t PGMISMTCHCLR; + __IO uint32_t OPTENDCLR; + __IO uint32_t COLERRCLR; + uint32_t RESERVED0[26]; +} stc_efm_fsclr_bit_t; + +typedef struct { + __IO uint32_t PEERRITE; + __IO uint32_t OPTENDITE; + __IO uint32_t COLERRITE; + uint32_t RESERVED0[29]; +} stc_efm_fite_bit_t; + +typedef struct { + __I uint32_t FSWP; + uint32_t RESERVED0[31]; +} stc_efm_fswp_bit_t; + +typedef struct { + uint32_t RESERVED0[31]; + __IO uint32_t EN; +} stc_efm_mmf_remcr_bit_t; + +typedef struct { + __IO uint32_t PORTINEN; + __IO uint32_t CMPEN1; + __IO uint32_t CMPEN2; + __IO uint32_t CMPEN3; + uint32_t RESERVED0[1]; + __IO uint32_t OSCSTPEN; + __IO uint32_t PWMSEN0; + __IO uint32_t PWMSEN1; + __IO uint32_t PWMSEN2; + uint32_t RESERVED1[21]; + __IO uint32_t NFEN; + __IO uint32_t INVSEL; +} stc_emb_ctl_bit_t; + +typedef struct { + __IO uint32_t PWMLV0; + __IO uint32_t PWMLV1; + __IO uint32_t PWMLV2; + uint32_t RESERVED0[29]; +} stc_emb_pwmlv_bit_t; + +typedef struct { + __IO uint32_t SOE; + uint32_t RESERVED0[31]; +} stc_emb_soe_bit_t; + +typedef struct { + __I uint32_t PORTINF; + __I uint32_t PWMSF; + __I uint32_t CMPF; + __I uint32_t OSF; + __I uint32_t PORTINST; + __I uint32_t PWMST; + uint32_t RESERVED0[26]; +} stc_emb_stat_bit_t; + +typedef struct { + __O uint32_t PORTINFCLR; + __O uint32_t PWMSFCLR; + __O uint32_t CMPFCLR; + __O uint32_t OSFCLR; + uint32_t RESERVED0[28]; +} stc_emb_statclr_bit_t; + +typedef struct { + __IO uint32_t PORTININTEN; + __IO uint32_t PWMSINTEN; + __IO uint32_t CMPINTEN; + __IO uint32_t OSINTEN; + uint32_t RESERVED0[28]; +} stc_emb_inten_bit_t; + +typedef struct { + __IO uint32_t START; + uint32_t RESERVED0[31]; +} stc_fcm_str_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t INEXS; + uint32_t RESERVED1[7]; + __IO uint32_t EXREFE; + uint32_t RESERVED2[16]; +} stc_fcm_rccr_bit_t; + +typedef struct { + __IO uint32_t ERRIE; + __IO uint32_t MENDIE; + __IO uint32_t OVFIE; + uint32_t RESERVED0[1]; + __IO uint32_t ERRINTRS; + uint32_t RESERVED1[2]; + __IO uint32_t ERRE; + uint32_t RESERVED2[24]; +} stc_fcm_rier_bit_t; + +typedef struct { + __I uint32_t ERRF; + __I uint32_t MENDF; + __I uint32_t OVF; + uint32_t RESERVED0[29]; +} stc_fcm_sr_bit_t; + +typedef struct { + __O uint32_t ERRFCLR; + __O uint32_t MENDFCLR; + __O uint32_t OVFCLR; + uint32_t RESERVED0[29]; +} stc_fcm_clr_bit_t; + +typedef struct { + __I uint32_t PIN00; + __I uint32_t PIN01; + __I uint32_t PIN02; + __I uint32_t PIN03; + __I uint32_t PIN04; + __I uint32_t PIN05; + __I uint32_t PIN06; + __I uint32_t PIN07; + __I uint32_t PIN08; + __I uint32_t PIN09; + __I uint32_t PIN10; + __I uint32_t PIN11; + __I uint32_t PIN12; + __I uint32_t PIN13; + __I uint32_t PIN14; + __I uint32_t PIN15; +} stc_gpio_pidr_bit_t; + +typedef struct { + __IO uint32_t POUT00; + __IO uint32_t POUT01; + __IO uint32_t POUT02; + __IO uint32_t POUT03; + __IO uint32_t POUT04; + __IO uint32_t POUT05; + __IO uint32_t POUT06; + __IO uint32_t POUT07; + __IO uint32_t POUT08; + __IO uint32_t POUT09; + __IO uint32_t POUT10; + __IO uint32_t POUT11; + __IO uint32_t POUT12; + __IO uint32_t POUT13; + __IO uint32_t POUT14; + __IO uint32_t POUT15; +} stc_gpio_podr_bit_t; + +typedef struct { + __IO uint32_t POUTE00; + __IO uint32_t POUTE01; + __IO uint32_t POUTE02; + __IO uint32_t POUTE03; + __IO uint32_t POUTE04; + __IO uint32_t POUTE05; + __IO uint32_t POUTE06; + __IO uint32_t POUTE07; + __IO uint32_t POUTE08; + __IO uint32_t POUTE09; + __IO uint32_t POUTE10; + __IO uint32_t POUTE11; + __IO uint32_t POUTE12; + __IO uint32_t POUTE13; + __IO uint32_t POUTE14; + __IO uint32_t POUTE15; +} stc_gpio_poer_bit_t; + +typedef struct { + __IO uint32_t POS00; + __IO uint32_t POS01; + __IO uint32_t POS02; + __IO uint32_t POS03; + __IO uint32_t POS04; + __IO uint32_t POS05; + __IO uint32_t POS06; + __IO uint32_t POS07; + __IO uint32_t POS08; + __IO uint32_t POS09; + __IO uint32_t POS10; + __IO uint32_t POS11; + __IO uint32_t POS12; + __IO uint32_t POS13; + __IO uint32_t POS14; + __IO uint32_t POS15; +} stc_gpio_posr_bit_t; + +typedef struct { + __IO uint32_t POR00; + __IO uint32_t POR01; + __IO uint32_t POR02; + __IO uint32_t POR03; + __IO uint32_t POR04; + __IO uint32_t POR05; + __IO uint32_t POR06; + __IO uint32_t POR07; + __IO uint32_t POR08; + __IO uint32_t POR09; + __IO uint32_t POR10; + __IO uint32_t POR11; + __IO uint32_t POR12; + __IO uint32_t POR13; + __IO uint32_t POR14; + __IO uint32_t POR15; +} stc_gpio_porr_bit_t; + +typedef struct { + __IO uint32_t POT00; + __IO uint32_t POT01; + __IO uint32_t POT02; + __IO uint32_t POT03; + __IO uint32_t POT04; + __IO uint32_t POT05; + __IO uint32_t POT06; + __IO uint32_t POT07; + __IO uint32_t POT08; + __IO uint32_t POT09; + __IO uint32_t POT10; + __IO uint32_t POT11; + __IO uint32_t POT12; + __IO uint32_t POT13; + __IO uint32_t POT14; + __IO uint32_t POT15; +} stc_gpio_potr_bit_t; + +typedef struct { + __I uint32_t PIN00; + __I uint32_t PIN01; + __I uint32_t PIN02; + uint32_t RESERVED0[13]; +} stc_gpio_pidrh_bit_t; + +typedef struct { + __IO uint32_t POUT00; + __IO uint32_t POUT01; + __IO uint32_t POUT02; + uint32_t RESERVED0[13]; +} stc_gpio_podrh_bit_t; + +typedef struct { + __IO uint32_t POUTE00; + __IO uint32_t POUTE01; + __IO uint32_t POUTE02; + uint32_t RESERVED0[13]; +} stc_gpio_poerh_bit_t; + +typedef struct { + __IO uint32_t POS00; + __IO uint32_t POS01; + __IO uint32_t POS02; + uint32_t RESERVED0[13]; +} stc_gpio_posrh_bit_t; + +typedef struct { + __IO uint32_t POR00; + __IO uint32_t POR01; + __IO uint32_t POR02; + uint32_t RESERVED0[13]; +} stc_gpio_porrh_bit_t; + +typedef struct { + __IO uint32_t POT00; + __IO uint32_t POT01; + __IO uint32_t POT02; + uint32_t RESERVED0[13]; +} stc_gpio_potrh_bit_t; + +typedef struct { + __IO uint32_t WE; + uint32_t RESERVED0[15]; +} stc_gpio_pwpr_bit_t; + +typedef struct { + __IO uint32_t POUT; + __IO uint32_t POUTE; + __IO uint32_t NOD; + uint32_t RESERVED0[3]; + __IO uint32_t PUU; + uint32_t RESERVED1[1]; + __I uint32_t PIN; + __IO uint32_t INVE; + uint32_t RESERVED2[2]; + __IO uint32_t INTE; + uint32_t RESERVED3[1]; + __IO uint32_t LTE; + __IO uint32_t DDIS; +} stc_gpio_pcr_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t BFE; + uint32_t RESERVED1[7]; +} stc_gpio_pfsr_bit_t; + +typedef struct { + __IO uint32_t START; + __IO uint32_t FST_GRP; + uint32_t RESERVED0[30]; +} stc_hash_cr_bit_t; + +typedef struct { + __IO uint32_t PE; + __IO uint32_t SMBUS; + __IO uint32_t SMBALRTEN; + __IO uint32_t SMBDEFAULTEN; + __IO uint32_t SMBHOSTEN; + uint32_t RESERVED0[1]; + __IO uint32_t GCEN; + __IO uint32_t RESTART; + __IO uint32_t START; + __IO uint32_t STOP; + __IO uint32_t ACK; + uint32_t RESERVED1[4]; + __IO uint32_t SWRST; + uint32_t RESERVED2[16]; +} stc_i2c_cr1_bit_t; + +typedef struct { + __IO uint32_t STARTIE; + __IO uint32_t SLADDR0IE; + __IO uint32_t SLADDR1IE; + __IO uint32_t TENDIE; + __IO uint32_t STOPIE; + uint32_t RESERVED0[1]; + __IO uint32_t RFULLIE; + __IO uint32_t TEMPTYIE; + uint32_t RESERVED1[1]; + __IO uint32_t ARLOIE; + uint32_t RESERVED2[2]; + __IO uint32_t NACKIE; + uint32_t RESERVED3[1]; + __IO uint32_t TMOUTIE; + uint32_t RESERVED4[5]; + __IO uint32_t GENCALLIE; + __IO uint32_t SMBDEFAULTIE; + __IO uint32_t SMBHOSTIE; + __IO uint32_t SMBALRTIE; + uint32_t RESERVED5[8]; +} stc_i2c_cr2_bit_t; + +typedef struct { + __IO uint32_t TMOUTEN; + __IO uint32_t LTMOUT; + __IO uint32_t HTMOUT; + uint32_t RESERVED0[4]; + __IO uint32_t FACKEN; + uint32_t RESERVED1[24]; +} stc_i2c_cr3_bit_t; + +typedef struct { + uint32_t RESERVED0[10]; + __IO uint32_t BUSWAIT; + uint32_t RESERVED1[21]; +} stc_i2c_cr4_bit_t; + +typedef struct { + uint32_t RESERVED0[12]; + __IO uint32_t SLADDR0EN; + uint32_t RESERVED1[2]; + __IO uint32_t ADDRMOD0; + uint32_t RESERVED2[16]; +} stc_i2c_slr0_bit_t; + +typedef struct { + uint32_t RESERVED0[12]; + __IO uint32_t SLADDR1EN; + uint32_t RESERVED1[2]; + __IO uint32_t ADDRMOD1; + uint32_t RESERVED2[16]; +} stc_i2c_slr1_bit_t; + +typedef struct { + __IO uint32_t STARTF; + __IO uint32_t SLADDR0F; + __IO uint32_t SLADDR1F; + __IO uint32_t TENDF; + __IO uint32_t STOPF; + uint32_t RESERVED0[1]; + __IO uint32_t RFULLF; + __IO uint32_t TEMPTYF; + uint32_t RESERVED1[1]; + __IO uint32_t ARLOF; + __IO uint32_t ACKRF; + uint32_t RESERVED2[1]; + __IO uint32_t NACKF; + uint32_t RESERVED3[1]; + __IO uint32_t TMOUTF; + uint32_t RESERVED4[1]; + __IO uint32_t MSL; + __IO uint32_t BUSY; + __IO uint32_t TRA; + uint32_t RESERVED5[1]; + __IO uint32_t GENCALLF; + __IO uint32_t SMBDEFAULTF; + __IO uint32_t SMBHOSTF; + __IO uint32_t SMBALRTF; + uint32_t RESERVED6[8]; +} stc_i2c_sr_bit_t; + +typedef struct { + __O uint32_t STARTFCLR; + __O uint32_t SLADDR0FCLR; + __O uint32_t SLADDR1FCLR; + __O uint32_t TENDFCLR; + __O uint32_t STOPFCLR; + uint32_t RESERVED0[1]; + __O uint32_t RFULLFCLR; + __O uint32_t TEMPTYFCLR; + uint32_t RESERVED1[1]; + __O uint32_t ARLOFCLR; + uint32_t RESERVED2[2]; + __O uint32_t NACKFCLR; + uint32_t RESERVED3[1]; + __O uint32_t TMOUTFCLR; + uint32_t RESERVED4[5]; + __O uint32_t GENCALLFCLR; + __O uint32_t SMBDEFAULTFCLR; + __O uint32_t SMBHOSTFCLR; + __O uint32_t SMBALRTFCLR; + uint32_t RESERVED5[8]; +} stc_i2c_clr_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t DNFEN; + __IO uint32_t ANFEN; + uint32_t RESERVED1[26]; +} stc_i2c_fltr_bit_t; + +typedef struct { + __IO uint32_t TXE; + __IO uint32_t TXIE; + __IO uint32_t RXE; + __IO uint32_t RXIE; + __IO uint32_t EIE; + __IO uint32_t WMS; + __IO uint32_t ODD; + __IO uint32_t MCKOE; + uint32_t RESERVED0[8]; + __IO uint32_t FIFOR; + uint32_t RESERVED1[1]; + __IO uint32_t I2SPLLSEL; + __IO uint32_t SDOE; + __IO uint32_t LRCKOE; + __IO uint32_t CKOE; + __IO uint32_t DUPLEX; + __IO uint32_t CLKSEL; + uint32_t RESERVED2[8]; +} stc_i2s_ctrl_bit_t; + +typedef struct { + __I uint32_t TXBA; + __I uint32_t RXBA; + __I uint32_t TXBE; + __I uint32_t TXBF; + __I uint32_t RXBE; + __I uint32_t RXBF; + uint32_t RESERVED0[26]; +} stc_i2s_sr_bit_t; + +typedef struct { + __IO uint32_t TXERR; + __IO uint32_t RXERR; + uint32_t RESERVED0[30]; +} stc_i2s_er_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t CHLEN; + __IO uint32_t PCMSYNC; + uint32_t RESERVED1[26]; +} stc_i2s_cfgr_bit_t; + +typedef struct { + __I uint32_t SWDTAUTS; + __I uint32_t SWDTITS; + uint32_t RESERVED0[10]; + __I uint32_t SWDTSLPOFF; + uint32_t RESERVED1[3]; + __I uint32_t WDTAUTS; + __I uint32_t WDTITS; + uint32_t RESERVED2[10]; + __I uint32_t WDTSLPOFF; + uint32_t RESERVED3[3]; +} stc_icg_icg0_bit_t; + +typedef struct { + __I uint32_t HRCFREQSEL; + uint32_t RESERVED0[7]; + __I uint32_t HRCSTOP; + uint32_t RESERVED1[9]; + __I uint32_t BORDIS; + uint32_t RESERVED2[9]; + __I uint32_t NMITRG; + __I uint32_t NMIEN; + __I uint32_t NFEN; + __I uint32_t NMIICGEN; +} stc_icg_icg1_bit_t; + +typedef struct { + __IO uint32_t NMITRG; + uint32_t RESERVED0[6]; + __IO uint32_t NFEN; + uint32_t RESERVED1[24]; +} stc_intc_nmicr_bit_t; + +typedef struct { + __IO uint32_t NMIENR; + __IO uint32_t SWDTENR; + __IO uint32_t PVD1ENR; + __IO uint32_t PVD2ENR; + uint32_t RESERVED0[1]; + __IO uint32_t XTALSTPENR; + uint32_t RESERVED1[2]; + __IO uint32_t REPENR; + __IO uint32_t RECCENR; + __IO uint32_t BUSMENR; + __IO uint32_t WDTENR; + uint32_t RESERVED2[20]; +} stc_intc_nmienr_bit_t; + +typedef struct { + __IO uint32_t NMIFR; + __IO uint32_t SWDTFR; + __IO uint32_t PVD1FR; + __IO uint32_t PVD2FR; + uint32_t RESERVED0[1]; + __IO uint32_t XTALSTPFR; + uint32_t RESERVED1[2]; + __IO uint32_t REPFR; + __IO uint32_t RECCFR; + __IO uint32_t BUSMFR; + __IO uint32_t WDTFR; + uint32_t RESERVED2[20]; +} stc_intc_nmifr_bit_t; + +typedef struct { + __IO uint32_t NMICFR; + __IO uint32_t SWDTCFR; + __IO uint32_t PVD1CFR; + __IO uint32_t PVD2CFR; + uint32_t RESERVED0[1]; + __IO uint32_t XTALSTPCFR; + uint32_t RESERVED1[2]; + __IO uint32_t REPCFR; + __IO uint32_t RECCCFR; + __IO uint32_t BUSMCFR; + __IO uint32_t WDTCFR; + uint32_t RESERVED2[20]; +} stc_intc_nmicfr_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t EFEN; + uint32_t RESERVED1[24]; +} stc_intc_eirqcr_bit_t; + +typedef struct { + __IO uint32_t EIRQWUEN0; + __IO uint32_t EIRQWUEN1; + __IO uint32_t EIRQWUEN2; + __IO uint32_t EIRQWUEN3; + __IO uint32_t EIRQWUEN4; + __IO uint32_t EIRQWUEN5; + __IO uint32_t EIRQWUEN6; + __IO uint32_t EIRQWUEN7; + __IO uint32_t EIRQWUEN8; + __IO uint32_t EIRQWUEN9; + __IO uint32_t EIRQWUEN10; + __IO uint32_t EIRQWUEN11; + __IO uint32_t EIRQWUEN12; + __IO uint32_t EIRQWUEN13; + __IO uint32_t EIRQWUEN14; + __IO uint32_t EIRQWUEN15; + __IO uint32_t SWDTWUEN; + __IO uint32_t PVD1WUEN; + __IO uint32_t PVD2WUEN; + __IO uint32_t CMPI0WUEN; + __IO uint32_t WKTMWUEN; + __IO uint32_t RTCALMWUEN; + __IO uint32_t RTCPRDWUEN; + __IO uint32_t TMR0WUEN; + uint32_t RESERVED0[1]; + __IO uint32_t RXWUEN; + uint32_t RESERVED1[6]; +} stc_intc_wupen_bit_t; + +typedef struct { + __IO uint32_t EIFR0; + __IO uint32_t EIFR1; + __IO uint32_t EIFR2; + __IO uint32_t EIFR3; + __IO uint32_t EIFR4; + __IO uint32_t EIFR5; + __IO uint32_t EIFR6; + __IO uint32_t EIFR7; + __IO uint32_t EIFR8; + __IO uint32_t EIFR9; + __IO uint32_t EIFR10; + __IO uint32_t EIFR11; + __IO uint32_t EIFR12; + __IO uint32_t EIFR13; + __IO uint32_t EIFR14; + __IO uint32_t EIFR15; + uint32_t RESERVED0[16]; +} stc_intc_eifr_bit_t; + +typedef struct { + __IO uint32_t EIFCR0; + __IO uint32_t EIFCR1; + __IO uint32_t EIFCR2; + __IO uint32_t EIFCR3; + __IO uint32_t EIFCR4; + __IO uint32_t EIFCR5; + __IO uint32_t EIFCR6; + __IO uint32_t EIFCR7; + __IO uint32_t EIFCR8; + __IO uint32_t EIFCR9; + __IO uint32_t EIFCR10; + __IO uint32_t EIFCR11; + __IO uint32_t EIFCR12; + __IO uint32_t EIFCR13; + __IO uint32_t EIFCR14; + __IO uint32_t EIFCR15; + uint32_t RESERVED0[16]; +} stc_intc_eifcr_bit_t; + +typedef struct { + __IO uint32_t VSEL0; + __IO uint32_t VSEL1; + __IO uint32_t VSEL2; + __IO uint32_t VSEL3; + __IO uint32_t VSEL4; + __IO uint32_t VSEL5; + __IO uint32_t VSEL6; + __IO uint32_t VSEL7; + __IO uint32_t VSEL8; + __IO uint32_t VSEL9; + __IO uint32_t VSEL10; + __IO uint32_t VSEL11; + __IO uint32_t VSEL12; + __IO uint32_t VSEL13; + __IO uint32_t VSEL14; + __IO uint32_t VSEL15; + __IO uint32_t VSEL16; + __IO uint32_t VSEL17; + __IO uint32_t VSEL18; + __IO uint32_t VSEL19; + __IO uint32_t VSEL20; + __IO uint32_t VSEL21; + __IO uint32_t VSEL22; + __IO uint32_t VSEL23; + __IO uint32_t VSEL24; + __IO uint32_t VSEL25; + __IO uint32_t VSEL26; + __IO uint32_t VSEL27; + __IO uint32_t VSEL28; + __IO uint32_t VSEL29; + __IO uint32_t VSEL30; + __IO uint32_t VSEL31; +} stc_intc_vssel_bit_t; + +typedef struct { + __IO uint32_t SWIE0; + __IO uint32_t SWIE1; + __IO uint32_t SWIE2; + __IO uint32_t SWIE3; + __IO uint32_t SWIE4; + __IO uint32_t SWIE5; + __IO uint32_t SWIE6; + __IO uint32_t SWIE7; + __IO uint32_t SWIE8; + __IO uint32_t SWIE9; + __IO uint32_t SWIE10; + __IO uint32_t SWIE11; + __IO uint32_t SWIE12; + __IO uint32_t SWIE13; + __IO uint32_t SWIE14; + __IO uint32_t SWIE15; + __IO uint32_t SWIE16; + __IO uint32_t SWIE17; + __IO uint32_t SWIE18; + __IO uint32_t SWIE19; + __IO uint32_t SWIE20; + __IO uint32_t SWIE21; + __IO uint32_t SWIE22; + __IO uint32_t SWIE23; + __IO uint32_t SWIE24; + __IO uint32_t SWIE25; + __IO uint32_t SWIE26; + __IO uint32_t SWIE27; + __IO uint32_t SWIE28; + __IO uint32_t SWIE29; + __IO uint32_t SWIE30; + __IO uint32_t SWIE31; +} stc_intc_swier_bit_t; + +typedef struct { + __IO uint32_t EVTE0; + __IO uint32_t EVTE1; + __IO uint32_t EVTE2; + __IO uint32_t EVTE3; + __IO uint32_t EVTE4; + __IO uint32_t EVTE5; + __IO uint32_t EVTE6; + __IO uint32_t EVTE7; + __IO uint32_t EVTE8; + __IO uint32_t EVTE9; + __IO uint32_t EVTE10; + __IO uint32_t EVTE11; + __IO uint32_t EVTE12; + __IO uint32_t EVTE13; + __IO uint32_t EVTE14; + __IO uint32_t EVTE15; + __IO uint32_t EVTE16; + __IO uint32_t EVTE17; + __IO uint32_t EVTE18; + __IO uint32_t EVTE19; + __IO uint32_t EVTE20; + __IO uint32_t EVTE21; + __IO uint32_t EVTE22; + __IO uint32_t EVTE23; + __IO uint32_t EVTE24; + __IO uint32_t EVTE25; + __IO uint32_t EVTE26; + __IO uint32_t EVTE27; + __IO uint32_t EVTE28; + __IO uint32_t EVTE29; + __IO uint32_t EVTE30; + __IO uint32_t EVTE31; +} stc_intc_evter_bit_t; + +typedef struct { + __IO uint32_t IER0; + __IO uint32_t IER1; + __IO uint32_t IER2; + __IO uint32_t IER3; + __IO uint32_t IER4; + __IO uint32_t IER5; + __IO uint32_t IER6; + __IO uint32_t IER7; + __IO uint32_t IER8; + __IO uint32_t IER9; + __IO uint32_t IER10; + __IO uint32_t IER11; + __IO uint32_t IER12; + __IO uint32_t IER13; + __IO uint32_t IER14; + __IO uint32_t IER15; + __IO uint32_t IER16; + __IO uint32_t IER17; + __IO uint32_t IER18; + __IO uint32_t IER19; + __IO uint32_t IER20; + __IO uint32_t IER21; + __IO uint32_t IER22; + __IO uint32_t IER23; + __IO uint32_t IER24; + __IO uint32_t IER25; + __IO uint32_t IER26; + __IO uint32_t IER27; + __IO uint32_t IER28; + __IO uint32_t IER29; + __IO uint32_t IER30; + __IO uint32_t IER31; +} stc_intc_ier_bit_t; + +typedef struct { + __IO uint32_t SEN; + uint32_t RESERVED0[31]; +} stc_keyscan_ser_bit_t; + +typedef struct { + __IO uint32_t S2RGRP; + __IO uint32_t S2RGWP; + uint32_t RESERVED0[5]; + __IO uint32_t S2RGE; + __IO uint32_t S1RGRP; + __IO uint32_t S1RGWP; + uint32_t RESERVED1[5]; + __IO uint32_t S1RGE; + __IO uint32_t FRGRP; + __IO uint32_t FRGWP; + uint32_t RESERVED2[5]; + __IO uint32_t FRGE; + uint32_t RESERVED3[8]; +} stc_mpu_rgcr_bit_t; + +typedef struct { + __IO uint32_t SMPU2BRP; + __IO uint32_t SMPU2BWP; + uint32_t RESERVED0[5]; + __IO uint32_t SMPU2E; + __IO uint32_t SMPU1BRP; + __IO uint32_t SMPU1BWP; + uint32_t RESERVED1[5]; + __IO uint32_t SMPU1E; + __IO uint32_t FMPUBRP; + __IO uint32_t FMPUBWP; + uint32_t RESERVED2[5]; + __IO uint32_t FMPUE; + uint32_t RESERVED3[8]; +} stc_mpu_cr_bit_t; + +typedef struct { + __I uint32_t SMPU2EAF; + uint32_t RESERVED0[7]; + __I uint32_t SMPU1EAF; + uint32_t RESERVED1[7]; + __I uint32_t FMPUEAF; + uint32_t RESERVED2[15]; +} stc_mpu_sr_bit_t; + +typedef struct { + __O uint32_t SMPU2ECLR; + uint32_t RESERVED0[7]; + __O uint32_t SMPU1ECLR; + uint32_t RESERVED1[7]; + __O uint32_t FMPUECLR; + uint32_t RESERVED2[15]; +} stc_mpu_eclr_bit_t; + +typedef struct { + __IO uint32_t MPUWE; + uint32_t RESERVED0[31]; +} stc_mpu_wp_bit_t; + +typedef struct { + __IO uint32_t AESRDP; + __IO uint32_t AESWRP; + __IO uint32_t HASHRDP; + __IO uint32_t HASHWRP; + __IO uint32_t TRNGRDP; + __IO uint32_t TRNGWRP; + __IO uint32_t CRCRDP; + __IO uint32_t CRCWRP; + __IO uint32_t EFMRDP; + __IO uint32_t EFMWRP; + uint32_t RESERVED0[2]; + __IO uint32_t WDTRDP; + __IO uint32_t WDTWRP; + __IO uint32_t SWDTRDP; + __IO uint32_t SWDTWRP; + __IO uint32_t BKSRAMRDP; + __IO uint32_t BKSRAMWRP; + __IO uint32_t RTCRDP; + __IO uint32_t RTCWRP; + __IO uint32_t DMPURDP; + __IO uint32_t DMPUWRP; + __IO uint32_t SRAMCRDP; + __IO uint32_t SRAMCWRP; + __IO uint32_t INTCRDP; + __IO uint32_t INTCWRP; + __IO uint32_t SYSCRDP; + __IO uint32_t SYSCWRP; + __IO uint32_t MSTPRDP; + __IO uint32_t MSTPWRP; + uint32_t RESERVED1[1]; + __IO uint32_t BUSERRE; +} stc_mpu_ippr_bit_t; + +typedef struct { + __IO uint32_t OTSST; + __IO uint32_t OTSCK; + __IO uint32_t OTSIE; + __IO uint32_t TSSTP; + uint32_t RESERVED0[12]; +} stc_ots_ctl_bit_t; + +typedef struct { + __IO uint32_t DFB; + __IO uint32_t SOFEN; + uint32_t RESERVED0[30]; +} stc_peric_usbfs_syctlreg_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t SELMMC1; + uint32_t RESERVED1[1]; + __IO uint32_t SELMMC2; + uint32_t RESERVED2[28]; +} stc_peric_sdioc_syctlreg_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t PFE; + __IO uint32_t PFSAE; + __IO uint32_t DCOME; + __IO uint32_t XIPE; + __IO uint32_t SPIMD3; + uint32_t RESERVED1[24]; +} stc_qspi_cr_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t FOUR_BIC; + uint32_t RESERVED1[1]; + __IO uint32_t SSNHD; + __IO uint32_t SSNLD; + __IO uint32_t WPOL; + uint32_t RESERVED2[8]; + __IO uint32_t DUTY; + uint32_t RESERVED3[16]; +} stc_qspi_fcr_bit_t; + +typedef struct { + __IO uint32_t BUSY; + uint32_t RESERVED0[5]; + __IO uint32_t XIPF; + __IO uint32_t RAER; + uint32_t RESERVED1[6]; + __IO uint32_t PFFUL; + __IO uint32_t PFAN; + uint32_t RESERVED2[16]; +} stc_qspi_sr_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __O uint32_t RAERCLR; + uint32_t RESERVED1[24]; +} stc_qspi_clr_bit_t; + +typedef struct { + __IO uint32_t PORF; + __IO uint32_t PINRF; + __IO uint32_t BORF; + __IO uint32_t PVD1RF; + __IO uint32_t PVD2RF; + __IO uint32_t WDRF; + __IO uint32_t SWDRF; + __IO uint32_t PDRF; + __IO uint32_t SWRF; + __IO uint32_t MPUERF; + __IO uint32_t RAPERF; + __IO uint32_t RAECRF; + __IO uint32_t CKFERF; + __IO uint32_t XTALERF; + __IO uint32_t MULTIRF; + __IO uint32_t CLRF; +} stc_rmu_rstf0_bit_t; + +typedef struct { + __IO uint32_t RESET; + uint32_t RESERVED0[7]; +} stc_rtc_cr0_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t AMPM; + __IO uint32_t ALMFCLR; + __IO uint32_t ONEHZOE; + __IO uint32_t ONEHZSEL; + __IO uint32_t START; +} stc_rtc_cr1_bit_t; + +typedef struct { + __IO uint32_t RWREQ; + __IO uint32_t RWEN; + uint32_t RESERVED0[1]; + __IO uint32_t ALMF; + uint32_t RESERVED1[1]; + __IO uint32_t PRDIE; + __IO uint32_t ALMIE; + __IO uint32_t ALME; +} stc_rtc_cr2_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t LRCEN; + uint32_t RESERVED1[2]; + __IO uint32_t RCKSEL; +} stc_rtc_cr3_bit_t; + +typedef struct { + __IO uint32_t COMP8; + uint32_t RESERVED0[6]; + __IO uint32_t COMPEN; +} stc_rtc_errcrh_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t BCE; + uint32_t RESERVED1[2]; + __IO uint32_t DDIR; + __IO uint32_t MULB; + uint32_t RESERVED2[10]; +} stc_sdioc_transmode_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t CCE; + __IO uint32_t ICE; + __IO uint32_t DAT; + uint32_t RESERVED1[10]; +} stc_sdioc_cmd_bit_t; + +typedef struct { + __I uint32_t CIC; + __I uint32_t CID; + __I uint32_t DA; + uint32_t RESERVED0[5]; + __I uint32_t WTA; + __I uint32_t RTA; + __I uint32_t BWE; + __I uint32_t BRE; + uint32_t RESERVED1[4]; + __I uint32_t CIN; + __I uint32_t CSS; + __I uint32_t CDL; + __I uint32_t WPL; + uint32_t RESERVED2[4]; + __I uint32_t CMDL; + uint32_t RESERVED3[7]; +} stc_sdioc_pstat_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t DW; + __IO uint32_t HSEN; + uint32_t RESERVED1[2]; + __IO uint32_t EXDW; + __IO uint32_t CDTL; + __IO uint32_t CDSS; +} stc_sdioc_hostcon_bit_t; + +typedef struct { + __IO uint32_t PWON; + uint32_t RESERVED0[7]; +} stc_sdioc_pwrcon_bit_t; + +typedef struct { + __IO uint32_t SABGR; + __IO uint32_t CR; + __IO uint32_t RWC; + __IO uint32_t IABG; + uint32_t RESERVED0[4]; +} stc_sdioc_blkgpcon_bit_t; + +typedef struct { + __IO uint32_t ICE; + uint32_t RESERVED0[1]; + __IO uint32_t CE; + uint32_t RESERVED1[13]; +} stc_sdioc_clkcon_bit_t; + +typedef struct { + __IO uint32_t RSTA; + __IO uint32_t RSTC; + __IO uint32_t RSTD; + uint32_t RESERVED0[5]; +} stc_sdioc_sftrst_bit_t; + +typedef struct { + __IO uint32_t CC; + __IO uint32_t TC; + __IO uint32_t BGE; + uint32_t RESERVED0[1]; + __IO uint32_t BWR; + __IO uint32_t BRR; + __IO uint32_t CIST; + __IO uint32_t CRM; + __I uint32_t CINT; + uint32_t RESERVED1[6]; + __I uint32_t EI; +} stc_sdioc_norintst_bit_t; + +typedef struct { + __IO uint32_t CTOE; + __IO uint32_t CCE; + __IO uint32_t CEBE; + __IO uint32_t CIE; + __IO uint32_t DTOE; + __IO uint32_t DCE; + __IO uint32_t DEBE; + uint32_t RESERVED0[1]; + __IO uint32_t ACE; + uint32_t RESERVED1[7]; +} stc_sdioc_errintst_bit_t; + +typedef struct { + __IO uint32_t CCEN; + __IO uint32_t TCEN; + __IO uint32_t BGEEN; + uint32_t RESERVED0[1]; + __IO uint32_t BWREN; + __IO uint32_t BRREN; + __IO uint32_t CISTEN; + __IO uint32_t CRMEN; + __IO uint32_t CINTEN; + uint32_t RESERVED1[7]; +} stc_sdioc_norintsten_bit_t; + +typedef struct { + __IO uint32_t CTOEEN; + __IO uint32_t CCEEN; + __IO uint32_t CEBEEN; + __IO uint32_t CIEEN; + __IO uint32_t DTOEEN; + __IO uint32_t DCEEN; + __IO uint32_t DEBEEN; + uint32_t RESERVED0[1]; + __IO uint32_t ACEEN; + uint32_t RESERVED1[7]; +} stc_sdioc_errintsten_bit_t; + +typedef struct { + __IO uint32_t CCSEN; + __IO uint32_t TCSEN; + __IO uint32_t BGESEN; + uint32_t RESERVED0[1]; + __IO uint32_t BWRSEN; + __IO uint32_t BRRSEN; + __IO uint32_t CISTSEN; + __IO uint32_t CRMSEN; + __IO uint32_t CINTSEN; + uint32_t RESERVED1[7]; +} stc_sdioc_norintsgen_bit_t; + +typedef struct { + __IO uint32_t CTOESEN; + __IO uint32_t CCESEN; + __IO uint32_t CEBESEN; + __IO uint32_t CIESEN; + __IO uint32_t DTOESEN; + __IO uint32_t DCESEN; + __IO uint32_t DEBESEN; + uint32_t RESERVED0[1]; + __IO uint32_t ACESEN; + uint32_t RESERVED1[7]; +} stc_sdioc_errintsgen_bit_t; + +typedef struct { + __I uint32_t NE; + __I uint32_t TOE; + __I uint32_t CE; + __I uint32_t EBE; + __I uint32_t IE; + uint32_t RESERVED0[2]; + __I uint32_t CMDE; + uint32_t RESERVED1[8]; +} stc_sdioc_atcerrst_bit_t; + +typedef struct { + __O uint32_t FNE; + __O uint32_t FTOE; + __O uint32_t FCE; + __O uint32_t FEBE; + __O uint32_t FIE; + uint32_t RESERVED0[2]; + __O uint32_t FCMDE; + uint32_t RESERVED1[8]; +} stc_sdioc_fea_bit_t; + +typedef struct { + __O uint32_t FCTOE; + __O uint32_t FCCE; + __O uint32_t FCEBE; + __O uint32_t FCIE; + __O uint32_t FDTOE; + __O uint32_t FDCE; + __O uint32_t FDEBE; + uint32_t RESERVED0[1]; + __O uint32_t FACE; + uint32_t RESERVED1[7]; +} stc_sdioc_fee_bit_t; + +typedef struct { + __IO uint32_t SPIMDS; + __IO uint32_t TXMDS; + uint32_t RESERVED0[1]; + __IO uint32_t MSTR; + __IO uint32_t SPLPBK; + __IO uint32_t SPLPBK2; + __IO uint32_t SPE; + __IO uint32_t CSUSPE; + __IO uint32_t EIE; + __IO uint32_t TXIE; + __IO uint32_t RXIE; + __IO uint32_t IDIE; + __IO uint32_t MODFE; + __IO uint32_t PATE; + __IO uint32_t PAOE; + __IO uint32_t PAE; + uint32_t RESERVED1[16]; +} stc_spi_cr1_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t SPRDTD; + uint32_t RESERVED1[1]; + __IO uint32_t SS0PV; + __IO uint32_t SS1PV; + __IO uint32_t SS2PV; + __IO uint32_t SS3PV; + uint32_t RESERVED2[20]; +} stc_spi_cfg1_bit_t; + +typedef struct { + __IO uint32_t OVRERF; + __I uint32_t IDLNF; + __IO uint32_t MODFERF; + __IO uint32_t PERF; + __IO uint32_t UDRERF; + __IO uint32_t TDEF; + uint32_t RESERVED0[1]; + __IO uint32_t RDFF; + uint32_t RESERVED1[24]; +} stc_spi_sr_bit_t; + +typedef struct { + __IO uint32_t CPHA; + __IO uint32_t CPOL; + uint32_t RESERVED0[10]; + __IO uint32_t LSBF; + __IO uint32_t MIDIE; + __IO uint32_t MSSDLE; + __IO uint32_t MSSIE; + uint32_t RESERVED1[16]; +} stc_spi_cfg2_bit_t; + +typedef struct { + __IO uint32_t WTPRC; + uint32_t RESERVED0[31]; +} stc_sramc_wtpr_bit_t; + +typedef struct { + __IO uint32_t PYOAD; + uint32_t RESERVED0[15]; + __IO uint32_t ECCOAD; + uint32_t RESERVED1[15]; +} stc_sramc_ckcr_bit_t; + +typedef struct { + __IO uint32_t CKPRC; + uint32_t RESERVED0[31]; +} stc_sramc_ckpr_bit_t; + +typedef struct { + __IO uint32_t SRAM3_1ERR; + __IO uint32_t SRAM3_2ERR; + __IO uint32_t SRAM12_PYERR; + __IO uint32_t SRAMH_PYERR; + __IO uint32_t SRAMR_PYERR; + uint32_t RESERVED0[27]; +} stc_sramc_cksr_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __IO uint32_t UDF; + __IO uint32_t REF; + uint32_t RESERVED1[14]; +} stc_swdt_sr_bit_t; + +typedef struct { + __IO uint32_t CSTA; + __IO uint32_t CAPMDA; + __IO uint32_t INTENA; + uint32_t RESERVED0[5]; + __IO uint32_t SYNSA; + __IO uint32_t SYNCLKA; + __IO uint32_t ASYNCLKA; + uint32_t RESERVED1[1]; + __IO uint32_t HSTAA; + __IO uint32_t HSTPA; + __IO uint32_t HCLEA; + __IO uint32_t HICPA; + __IO uint32_t CSTB; + __IO uint32_t CAPMDB; + __IO uint32_t INTENB; + uint32_t RESERVED2[5]; + __IO uint32_t SYNSB; + __IO uint32_t SYNCLKB; + __IO uint32_t ASYNCLKB; + uint32_t RESERVED3[1]; + __IO uint32_t HSTAB; + __IO uint32_t HSTPB; + __IO uint32_t HCLEB; + __IO uint32_t HICPB; +} stc_tmr0_bconr_bit_t; + +typedef struct { + __IO uint32_t CMFA; + uint32_t RESERVED0[15]; + __IO uint32_t CMFB; + uint32_t RESERVED1[15]; +} stc_tmr0_stflr_bit_t; + +typedef struct { + __IO uint32_t OCEH; + __IO uint32_t OCEL; + __IO uint32_t OCPH; + __IO uint32_t OCPL; + __IO uint32_t OCIEH; + __IO uint32_t OCIEL; + __IO uint32_t OCFH; + __IO uint32_t OCFL; + uint32_t RESERVED0[8]; +} stc_tmr4_ocsr_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t LMCH; + __IO uint32_t LMCL; + __IO uint32_t LMMH; + __IO uint32_t LMML; + __IO uint32_t MCECH; + __IO uint32_t MCECL; + uint32_t RESERVED1[2]; +} stc_tmr4_ocer_bit_t; + +typedef struct { + __IO uint32_t OCFDCH; + __IO uint32_t OCFPKH; + __IO uint32_t OCFUCH; + __IO uint32_t OCFZRH; + uint32_t RESERVED0[12]; +} stc_tmr4_ocmrh_bit_t; + +typedef struct { + __IO uint32_t OCFDCL; + __IO uint32_t OCFPKL; + __IO uint32_t OCFUCL; + __IO uint32_t OCFZRL; + uint32_t RESERVED0[28]; +} stc_tmr4_ocmrl_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t CLEAR; + __IO uint32_t MODE; + __IO uint32_t STOP; + __IO uint32_t BUFEN; + __IO uint32_t IRQPEN; + __IO uint32_t IRQPF; + uint32_t RESERVED1[3]; + __IO uint32_t IRQZEN; + __IO uint32_t IRQZF; + __IO uint32_t ECKEN; +} stc_tmr4_ccsr_bit_t; + +typedef struct { + __IO uint32_t RTIDU; + __IO uint32_t RTIDV; + __IO uint32_t RTIDW; + uint32_t RESERVED0[1]; + __I uint32_t RTIFU; + __IO uint32_t RTICU; + __IO uint32_t RTEU; + __IO uint32_t RTSU; + __I uint32_t RTIFV; + __IO uint32_t RTICV; + __IO uint32_t RTEV; + __IO uint32_t RTSV; + __I uint32_t RTIFW; + __IO uint32_t RTICW; + __IO uint32_t RTEW; + __IO uint32_t RTSW; +} stc_tmr4_rcsr_bit_t; + +typedef struct { + uint32_t RESERVED0[5]; + __IO uint32_t LMC; + uint32_t RESERVED1[2]; + __IO uint32_t EVTMS; + __IO uint32_t EVTDS; + uint32_t RESERVED2[2]; + __IO uint32_t DEN; + __IO uint32_t PEN; + __IO uint32_t UEN; + __IO uint32_t ZEN; +} stc_tmr4_scsr_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t MZCE; + __IO uint32_t MPCE; + uint32_t RESERVED1[8]; +} stc_tmr4_scmr_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t HOLD; + uint32_t RESERVED1[8]; +} stc_tmr4_ecsr_bit_t; + +typedef struct { + __IO uint32_t START; + uint32_t RESERVED0[7]; + __IO uint32_t DIR; + uint32_t RESERVED1[7]; + __IO uint32_t ZMSKREV; + __IO uint32_t ZMSKPOS; + uint32_t RESERVED2[14]; +} stc_tmr6_gconr_bit_t; + +typedef struct { + __IO uint32_t INTENA; + __IO uint32_t INTENB; + __IO uint32_t INTENC; + __IO uint32_t INTEND; + __IO uint32_t INTENE; + __IO uint32_t INTENF; + __IO uint32_t INTENOVF; + __IO uint32_t INTENUDF; + __IO uint32_t INTENDTE; + uint32_t RESERVED0[7]; + __IO uint32_t INTENSAU; + __IO uint32_t INTENSAD; + __IO uint32_t INTENSBU; + __IO uint32_t INTENSBD; + uint32_t RESERVED1[12]; +} stc_tmr6_iconr_bit_t; + +typedef struct { + __IO uint32_t CAPMDA; + __IO uint32_t STACA; + __IO uint32_t STPCA; + __IO uint32_t STASTPSA; + uint32_t RESERVED0[4]; + __IO uint32_t OUTENA; + uint32_t RESERVED1[7]; + __IO uint32_t CAPMDB; + __IO uint32_t STACB; + __IO uint32_t STPCB; + __IO uint32_t STASTPSB; + uint32_t RESERVED2[4]; + __IO uint32_t OUTENB; + uint32_t RESERVED3[7]; +} stc_tmr6_pconr_bit_t; + +typedef struct { + __IO uint32_t BENA; + __IO uint32_t BSEA; + __IO uint32_t BENB; + __IO uint32_t BSEB; + uint32_t RESERVED0[4]; + __IO uint32_t BENP; + __IO uint32_t BSEP; + uint32_t RESERVED1[6]; + __IO uint32_t BENSPA; + __IO uint32_t BSESPA; + uint32_t RESERVED2[2]; + __IO uint32_t BTRUSPA; + __IO uint32_t BTRDSPA; + uint32_t RESERVED3[2]; + __IO uint32_t BENSPB; + __IO uint32_t BSESPB; + uint32_t RESERVED4[2]; + __IO uint32_t BTRUSPB; + __IO uint32_t BTRDSPB; + uint32_t RESERVED5[2]; +} stc_tmr6_bconr_bit_t; + +typedef struct { + __IO uint32_t DTCEN; + uint32_t RESERVED0[3]; + __IO uint32_t DTBENU; + __IO uint32_t DTBEND; + uint32_t RESERVED1[2]; + __IO uint32_t SEPA; + uint32_t RESERVED2[23]; +} stc_tmr6_dconr_bit_t; + +typedef struct { + __IO uint32_t NOFIENGA; + uint32_t RESERVED0[3]; + __IO uint32_t NOFIENGB; + uint32_t RESERVED1[11]; + __IO uint32_t NOFIENTA; + uint32_t RESERVED2[3]; + __IO uint32_t NOFIENTB; + uint32_t RESERVED3[11]; +} stc_tmr6_fconr_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t SPPERIA; + __IO uint32_t SPPERIB; + uint32_t RESERVED1[22]; +} stc_tmr6_vperr_bit_t; + +typedef struct { + __IO uint32_t CMAF; + __IO uint32_t CMBF; + __IO uint32_t CMCF; + __IO uint32_t CMDF; + __IO uint32_t CMEF; + __IO uint32_t CMFF; + __IO uint32_t OVFF; + __IO uint32_t UDFF; + __I uint32_t DTEF; + __IO uint32_t CMSAUF; + __IO uint32_t CMSADF; + __IO uint32_t CMSBUF; + __IO uint32_t CMSBDF; + uint32_t RESERVED0[18]; + __I uint32_t DIRF; +} stc_tmr6_stflr_bit_t; + +typedef struct { + __IO uint32_t HSTA0; + __IO uint32_t HSTA1; + uint32_t RESERVED0[2]; + __IO uint32_t HSTA4; + __IO uint32_t HSTA5; + __IO uint32_t HSTA6; + __IO uint32_t HSTA7; + __IO uint32_t HSTA8; + __IO uint32_t HSTA9; + __IO uint32_t HSTA10; + __IO uint32_t HSTA11; + uint32_t RESERVED1[19]; + __IO uint32_t STAS; +} stc_tmr6_hstar_bit_t; + +typedef struct { + __IO uint32_t HSTP0; + __IO uint32_t HSTP1; + uint32_t RESERVED0[2]; + __IO uint32_t HSTP4; + __IO uint32_t HSTP5; + __IO uint32_t HSTP6; + __IO uint32_t HSTP7; + __IO uint32_t HSTP8; + __IO uint32_t HSTP9; + __IO uint32_t HSTP10; + __IO uint32_t HSTP11; + uint32_t RESERVED1[19]; + __IO uint32_t STPS; +} stc_tmr6_hstpr_bit_t; + +typedef struct { + __IO uint32_t HCLE0; + __IO uint32_t HCLE1; + uint32_t RESERVED0[2]; + __IO uint32_t HCLE4; + __IO uint32_t HCLE5; + __IO uint32_t HCLE6; + __IO uint32_t HCLE7; + __IO uint32_t HCLE8; + __IO uint32_t HCLE9; + __IO uint32_t HCLE10; + __IO uint32_t HCLE11; + uint32_t RESERVED1[19]; + __IO uint32_t CLES; +} stc_tmr6_hclrr_bit_t; + +typedef struct { + __IO uint32_t HCPA0; + __IO uint32_t HCPA1; + uint32_t RESERVED0[2]; + __IO uint32_t HCPA4; + __IO uint32_t HCPA5; + __IO uint32_t HCPA6; + __IO uint32_t HCPA7; + __IO uint32_t HCPA8; + __IO uint32_t HCPA9; + __IO uint32_t HCPA10; + __IO uint32_t HCPA11; + uint32_t RESERVED1[20]; +} stc_tmr6_hcpar_bit_t; + +typedef struct { + __IO uint32_t HCPB0; + __IO uint32_t HCPB1; + uint32_t RESERVED0[2]; + __IO uint32_t HCPB4; + __IO uint32_t HCPB5; + __IO uint32_t HCPB6; + __IO uint32_t HCPB7; + __IO uint32_t HCPB8; + __IO uint32_t HCPB9; + __IO uint32_t HCPB10; + __IO uint32_t HCPB11; + uint32_t RESERVED1[20]; +} stc_tmr6_hcpbr_bit_t; + +typedef struct { + __IO uint32_t HCUP0; + __IO uint32_t HCUP1; + __IO uint32_t HCUP2; + __IO uint32_t HCUP3; + __IO uint32_t HCUP4; + __IO uint32_t HCUP5; + __IO uint32_t HCUP6; + __IO uint32_t HCUP7; + __IO uint32_t HCUP8; + __IO uint32_t HCUP9; + __IO uint32_t HCUP10; + __IO uint32_t HCUP11; + uint32_t RESERVED0[4]; + __IO uint32_t HCUP16; + __IO uint32_t HCUP17; + uint32_t RESERVED1[14]; +} stc_tmr6_hcupr_bit_t; + +typedef struct { + __IO uint32_t HCDO0; + __IO uint32_t HCDO1; + __IO uint32_t HCDO2; + __IO uint32_t HCDO3; + __IO uint32_t HCDO4; + __IO uint32_t HCDO5; + __IO uint32_t HCDO6; + __IO uint32_t HCDO7; + __IO uint32_t HCDO8; + __IO uint32_t HCDO9; + __IO uint32_t HCDO10; + __IO uint32_t HCDO11; + uint32_t RESERVED0[4]; + __IO uint32_t HCDO16; + __IO uint32_t HCDO17; + uint32_t RESERVED1[14]; +} stc_tmr6_hcdor_bit_t; + +typedef struct { + __IO uint32_t SSTA1; + __IO uint32_t SSTA2; + __IO uint32_t SSTA3; + uint32_t RESERVED0[29]; +} stc_tmr6_common_sstar_bit_t; + +typedef struct { + __IO uint32_t SSTP1; + __IO uint32_t SSTP2; + __IO uint32_t SSTP3; + uint32_t RESERVED0[29]; +} stc_tmr6_common_sstpr_bit_t; + +typedef struct { + __IO uint32_t SCLE1; + __IO uint32_t SCLE2; + __IO uint32_t SCLE3; + uint32_t RESERVED0[29]; +} stc_tmr6_common_sclrr_bit_t; + +typedef struct { + __IO uint32_t START; + __IO uint32_t DIR; + __IO uint32_t MODE; + __IO uint32_t SYNST; + uint32_t RESERVED0[4]; +} stc_tmra_bcstrl_bit_t; + +typedef struct { + __IO uint32_t OVSTP; + uint32_t RESERVED0[3]; + __IO uint32_t ITENOVF; + __IO uint32_t ITENUDF; + __IO uint32_t OVFF; + __IO uint32_t UDFF; +} stc_tmra_bcstrh_bit_t; + +typedef struct { + __IO uint32_t HSTA0; + __IO uint32_t HSTA1; + __IO uint32_t HSTA2; + uint32_t RESERVED0[1]; + __IO uint32_t HSTP0; + __IO uint32_t HSTP1; + __IO uint32_t HSTP2; + uint32_t RESERVED1[1]; + __IO uint32_t HCLE0; + __IO uint32_t HCLE1; + __IO uint32_t HCLE2; + uint32_t RESERVED2[1]; + __IO uint32_t HCLE3; + __IO uint32_t HCLE4; + __IO uint32_t HCLE5; + __IO uint32_t HCLE6; +} stc_tmra_hconr_bit_t; + +typedef struct { + __IO uint32_t HCUP0; + __IO uint32_t HCUP1; + __IO uint32_t HCUP2; + __IO uint32_t HCUP3; + __IO uint32_t HCUP4; + __IO uint32_t HCUP5; + __IO uint32_t HCUP6; + __IO uint32_t HCUP7; + __IO uint32_t HCUP8; + __IO uint32_t HCUP9; + __IO uint32_t HCUP10; + __IO uint32_t HCUP11; + __IO uint32_t HCUP12; + uint32_t RESERVED0[3]; +} stc_tmra_hcupr_bit_t; + +typedef struct { + __IO uint32_t HCDO0; + __IO uint32_t HCDO1; + __IO uint32_t HCDO2; + __IO uint32_t HCDO3; + __IO uint32_t HCDO4; + __IO uint32_t HCDO5; + __IO uint32_t HCDO6; + __IO uint32_t HCDO7; + __IO uint32_t HCDO8; + __IO uint32_t HCDO9; + __IO uint32_t HCDO10; + __IO uint32_t HCDO11; + __IO uint32_t HCDO12; + uint32_t RESERVED0[3]; +} stc_tmra_hcdor_bit_t; + +typedef struct { + __IO uint32_t ITEN1; + __IO uint32_t ITEN2; + __IO uint32_t ITEN3; + __IO uint32_t ITEN4; + __IO uint32_t ITEN5; + __IO uint32_t ITEN6; + __IO uint32_t ITEN7; + __IO uint32_t ITEN8; + uint32_t RESERVED0[8]; +} stc_tmra_iconr_bit_t; + +typedef struct { + __IO uint32_t ETEN1; + __IO uint32_t ETEN2; + __IO uint32_t ETEN3; + __IO uint32_t ETEN4; + __IO uint32_t ETEN5; + __IO uint32_t ETEN6; + __IO uint32_t ETEN7; + __IO uint32_t ETEN8; + uint32_t RESERVED0[8]; +} stc_tmra_econr_bit_t; + +typedef struct { + __IO uint32_t NOFIENTG; + uint32_t RESERVED0[7]; + __IO uint32_t NOFIENCA; + uint32_t RESERVED1[3]; + __IO uint32_t NOFIENCB; + uint32_t RESERVED2[3]; +} stc_tmra_fconr_bit_t; + +typedef struct { + __IO uint32_t CMPF1; + __IO uint32_t CMPF2; + __IO uint32_t CMPF3; + __IO uint32_t CMPF4; + __IO uint32_t CMPF5; + __IO uint32_t CMPF6; + __IO uint32_t CMPF7; + __IO uint32_t CMPF8; + uint32_t RESERVED0[8]; +} stc_tmra_stflr_bit_t; + +typedef struct { + __IO uint32_t BEN; + __IO uint32_t BSE0; + __IO uint32_t BSE1; + uint32_t RESERVED0[13]; +} stc_tmra_bconr_bit_t; + +typedef struct { + __IO uint32_t CAPMD; + uint32_t RESERVED0[3]; + __IO uint32_t HICP0; + __IO uint32_t HICP1; + __IO uint32_t HICP2; + uint32_t RESERVED1[1]; + __IO uint32_t HICP3; + __IO uint32_t HICP4; + uint32_t RESERVED2[2]; + __IO uint32_t NOFIENCP; + uint32_t RESERVED3[3]; +} stc_tmra_cconr_bit_t; + +typedef struct { + uint32_t RESERVED0[12]; + __IO uint32_t OUTEN; + uint32_t RESERVED1[3]; +} stc_tmra_pconr_bit_t; + +typedef struct { + __IO uint32_t EN; + __IO uint32_t RUN; + uint32_t RESERVED0[30]; +} stc_trng_cr_bit_t; + +typedef struct { + __IO uint32_t LOAD; + uint32_t RESERVED0[31]; +} stc_trng_mr_bit_t; + +typedef struct { + __I uint32_t PE; + __I uint32_t FE; + uint32_t RESERVED0[1]; + __I uint32_t ORE; + uint32_t RESERVED1[1]; + __I uint32_t RXNE; + __I uint32_t TC; + __I uint32_t TXE; + __I uint32_t RTOF; + uint32_t RESERVED2[7]; + __I uint32_t MPB; + uint32_t RESERVED3[15]; +} stc_usart_sr_bit_t; + +typedef struct { + uint32_t RESERVED0[9]; + __IO uint32_t MPID; + uint32_t RESERVED1[6]; +} stc_usart_tdr_bit_t; + +typedef struct { + __IO uint32_t RTOE; + __IO uint32_t RTOIE; + __IO uint32_t RE; + __IO uint32_t TE; + __IO uint32_t SLME; + __IO uint32_t RIE; + __IO uint32_t TCIE; + __IO uint32_t TXEIE; + uint32_t RESERVED0[1]; + __IO uint32_t PS; + __IO uint32_t PCE; + uint32_t RESERVED1[1]; + __IO uint32_t M; + uint32_t RESERVED2[2]; + __IO uint32_t OVER8; + __O uint32_t CPE; + __O uint32_t CFE; + uint32_t RESERVED3[1]; + __O uint32_t CORE; + __O uint32_t CRTOF; + uint32_t RESERVED4[3]; + __IO uint32_t MS; + uint32_t RESERVED5[3]; + __IO uint32_t ML; + __IO uint32_t FBME; + __IO uint32_t NFE; + __IO uint32_t SBS; +} stc_usart_cr1_bit_t; + +typedef struct { + __IO uint32_t MPE; + uint32_t RESERVED0[12]; + __IO uint32_t STOP; + uint32_t RESERVED1[18]; +} stc_usart_cr2_bit_t; + +typedef struct { + uint32_t RESERVED0[5]; + __IO uint32_t SCEN; + uint32_t RESERVED1[3]; + __IO uint32_t CTSE; + uint32_t RESERVED2[22]; +} stc_usart_cr3_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t VBUSOVEN; + __IO uint32_t VBUSVAL; + uint32_t RESERVED1[24]; +} stc_usbfs_gvbuscfg_bit_t; + +typedef struct { + __IO uint32_t GINTMSK; + uint32_t RESERVED0[4]; + __IO uint32_t DMAEN; + uint32_t RESERVED1[1]; + __IO uint32_t TXFELVL; + __IO uint32_t PTXFELVL; + uint32_t RESERVED2[23]; +} stc_usbfs_gahbcfg_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t PHYSEL; + uint32_t RESERVED1[22]; + __IO uint32_t FHMOD; + __IO uint32_t FDMOD; + uint32_t RESERVED2[1]; +} stc_usbfs_gusbcfg_bit_t; + +typedef struct { + __IO uint32_t CSRST; + __IO uint32_t HSRST; + __IO uint32_t FCRST; + uint32_t RESERVED0[1]; + __IO uint32_t RXFFLSH; + __IO uint32_t TXFFLSH; + uint32_t RESERVED1[24]; + __I uint32_t DMAREQ; + __I uint32_t AHBIDL; +} stc_usbfs_grstctl_bit_t; + +typedef struct { + __I uint32_t CMOD; + __IO uint32_t MMIS; + uint32_t RESERVED0[1]; + __IO uint32_t SOF; + __I uint32_t RXFNE; + __I uint32_t NPTXFE; + __I uint32_t GINAKEFF; + __I uint32_t GONAKEFF; + uint32_t RESERVED1[2]; + __IO uint32_t ESUSP; + __IO uint32_t USBSUSP; + __IO uint32_t USBRST; + __IO uint32_t ENUMDNE; + __IO uint32_t ISOODRP; + __IO uint32_t EOPF; + uint32_t RESERVED2[2]; + __I uint32_t IEPINT; + __I uint32_t OEPINT; + __IO uint32_t IISOIXFR; + __IO uint32_t IPXFR_INCOMPISOOUT; + __IO uint32_t DATAFSUSP; + uint32_t RESERVED3[1]; + __I uint32_t HPRTINT; + __I uint32_t HCINT; + __I uint32_t PTXFE; + uint32_t RESERVED4[1]; + __IO uint32_t CIDSCHG; + __IO uint32_t DISCINT; + __IO uint32_t VBUSVINT; + __IO uint32_t WKUINT; +} stc_usbfs_gintsts_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t MMISM; + uint32_t RESERVED1[1]; + __IO uint32_t SOFM; + __IO uint32_t RXFNEM; + __IO uint32_t NPTXFEM; + __IO uint32_t GINAKEFFM; + __IO uint32_t GONAKEFFM; + uint32_t RESERVED2[2]; + __IO uint32_t ESUSPM; + __IO uint32_t USBSUSPM; + __IO uint32_t USBRSTM; + __IO uint32_t ENUMDNEM; + __IO uint32_t ISOODRPM; + __IO uint32_t EOPFM; + uint32_t RESERVED3[2]; + __IO uint32_t IEPIM; + __IO uint32_t OEPIM; + __IO uint32_t IISOIXFRM; + __IO uint32_t IPXFRM_INCOMPISOOUTM; + __IO uint32_t DATAFSUSPM; + uint32_t RESERVED4[1]; + __IO uint32_t HPRTIM; + __IO uint32_t HCIM; + __IO uint32_t PTXFEM; + uint32_t RESERVED5[1]; + __IO uint32_t CIDSCHGM; + __IO uint32_t DISCIM; + __IO uint32_t VBUSVIM; + __IO uint32_t WKUIM; +} stc_usbfs_gintmsk_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t FSLSS; + uint32_t RESERVED1[29]; +} stc_usbfs_hcfg_bit_t; + +typedef struct { + __I uint32_t PCSTS; + __IO uint32_t PCDET; + __IO uint32_t PENA; + __IO uint32_t PENCHNG; + uint32_t RESERVED0[2]; + __IO uint32_t PRES; + __IO uint32_t PSUSP; + __IO uint32_t PRST; + uint32_t RESERVED1[3]; + __IO uint32_t PWPR; + uint32_t RESERVED2[19]; +} stc_usbfs_hprt_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSDEV; + uint32_t RESERVED2[11]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbfs_hcchar_bit_t; + +typedef struct { + __IO uint32_t XFRC; + __IO uint32_t CHH; + uint32_t RESERVED0[1]; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + uint32_t RESERVED1[1]; + __IO uint32_t TXERR; + __IO uint32_t BBERR; + __IO uint32_t FRMOR; + __IO uint32_t DTERR; + uint32_t RESERVED2[21]; +} stc_usbfs_hcint_bit_t; + +typedef struct { + __IO uint32_t XFRCM; + __IO uint32_t CHHM; + uint32_t RESERVED0[1]; + __IO uint32_t STALLM; + __IO uint32_t NAKM; + __IO uint32_t ACKM; + uint32_t RESERVED1[1]; + __IO uint32_t TXERRM; + __IO uint32_t BBERRM; + __IO uint32_t FRMORM; + __IO uint32_t DTERRM; + uint32_t RESERVED2[21]; +} stc_usbfs_hcintmsk_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t NZLSOHSK; + uint32_t RESERVED1[29]; +} stc_usbfs_dcfg_bit_t; + +typedef struct { + __IO uint32_t RWUSIG; + __IO uint32_t SDIS; + __I uint32_t GINSTS; + __I uint32_t GONSTS; + uint32_t RESERVED0[3]; + __O uint32_t SGINAK; + __O uint32_t CGINAK; + __O uint32_t SGONAK; + __O uint32_t CGONAK; + __IO uint32_t POPRGDNE; + uint32_t RESERVED1[20]; +} stc_usbfs_dctl_bit_t; + +typedef struct { + __I uint32_t SUSPSTS; + uint32_t RESERVED0[2]; + __I uint32_t EERR; + uint32_t RESERVED1[28]; +} stc_usbfs_dsts_bit_t; + +typedef struct { + __IO uint32_t XFRCM; + __IO uint32_t EPDM; + uint32_t RESERVED0[1]; + __IO uint32_t TOM; + __IO uint32_t TTXFEMSK; + __IO uint32_t INEPNMM; + __IO uint32_t INEPNEM; + uint32_t RESERVED1[25]; +} stc_usbfs_diepmsk_bit_t; + +typedef struct { + __IO uint32_t XFRCM; + __IO uint32_t EPDM; + uint32_t RESERVED0[1]; + __IO uint32_t STUPM; + __IO uint32_t OTEPDM; + uint32_t RESERVED1[27]; +} stc_usbfs_doepmsk_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __I uint32_t USBAEP; + uint32_t RESERVED1[1]; + __I uint32_t NAKSTS; + uint32_t RESERVED2[3]; + __IO uint32_t STALL; + uint32_t RESERVED3[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + uint32_t RESERVED4[2]; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl0_bit_t; + +typedef struct { + __IO uint32_t XFRC; + __IO uint32_t EPDISD; + uint32_t RESERVED0[1]; + __IO uint32_t TOC; + __IO uint32_t TTXFE; + uint32_t RESERVED1[1]; + __IO uint32_t INEPNE; + __I uint32_t TXFE; + uint32_t RESERVED2[24]; +} stc_usbfs_diepint_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __IO uint32_t USBAEP; + __I uint32_t EONUM_DPID; + __I uint32_t NAKSTS; + uint32_t RESERVED1[3]; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SD0PID_SEVNFRM; + __IO uint32_t SODDFRM; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __I uint32_t USBAEP; + uint32_t RESERVED1[1]; + __I uint32_t NAKSTS; + uint32_t RESERVED2[2]; + __IO uint32_t SNPM; + __IO uint32_t STALL; + uint32_t RESERVED3[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + uint32_t RESERVED4[2]; + __I uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl0_bit_t; + +typedef struct { + __IO uint32_t XFRC; + __IO uint32_t EPDISD; + uint32_t RESERVED0[1]; + __IO uint32_t STUP; + __IO uint32_t OTEPDIS; + uint32_t RESERVED1[1]; + __IO uint32_t B2BSTUP; + uint32_t RESERVED2[25]; +} stc_usbfs_doepint_bit_t; + +typedef struct { + uint32_t RESERVED0[19]; + __IO uint32_t PKTCNT; + uint32_t RESERVED1[12]; +} stc_usbfs_doeptsiz0_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __IO uint32_t USBAEP; + __I uint32_t DPID; + __I uint32_t NAKSTS; + uint32_t RESERVED1[2]; + __IO uint32_t SNPM; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SD0PID; + __IO uint32_t SD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl_bit_t; + +typedef struct { + __IO uint32_t STPPCLK; + __IO uint32_t GATEHCLK; + uint32_t RESERVED0[30]; +} stc_usbfs_gcctl_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __IO uint32_t SLPOFF; + uint32_t RESERVED1[14]; + __IO uint32_t ITS; +} stc_wdt_cr_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __IO uint32_t UDF; + __IO uint32_t REF; + uint32_t RESERVED1[14]; +} stc_wdt_sr_bit_t; + + +typedef struct { + stc_adc_str_bit_t STR_b; + uint32_t RESERVED0[8]; + stc_adc_cr0_bit_t CR0_b; + stc_adc_cr1_bit_t CR1_b; + uint32_t RESERVED1[32]; + stc_adc_trgsr_bit_t TRGSR_b; + uint32_t RESERVED2[464]; + stc_adc_isr_bit_t ISR_b; + stc_adc_icr_bit_t ICR_b; + uint32_t RESERVED3[32]; + stc_adc_synccr_bit_t SYNCCR_b; + uint32_t RESERVED4[656]; + stc_adc_awdcr_bit_t AWDCR_b; + uint32_t RESERVED5[352]; + stc_adc_pgainsr1_bit_t PGAINSR1_b; +} bCM_ADC_TypeDef; + +typedef struct { + stc_aes_cr_bit_t CR_b; +} bCM_AES_TypeDef; + +typedef struct { + stc_aos_intsfttrg_bit_t INTSFTTRG_b; + uint32_t RESERVED0[2912]; + stc_aos_pevntnfcr_bit_t PEVNTNFCR_b; +} bCM_AOS_TypeDef; + +typedef struct { + uint32_t RESERVED0[1280]; + stc_can_cfg_stat_bit_t CFG_STAT_b; + stc_can_tcmd_bit_t TCMD_b; + stc_can_tctrl_bit_t TCTRL_b; + stc_can_rctrl_bit_t RCTRL_b; + stc_can_rtie_bit_t RTIE_b; + stc_can_rtif_bit_t RTIF_b; + stc_can_errint_bit_t ERRINT_b; + uint32_t RESERVED1[104]; + stc_can_acfctrl_bit_t ACFCTRL_b; + uint32_t RESERVED2[8]; + stc_can_acfen_bit_t ACFEN_b; + uint32_t RESERVED3[8]; + stc_can_acf_bit_t ACF_b; + uint32_t RESERVED4[16]; + stc_can_tbslot_bit_t TBSLOT_b; + stc_can_ttcfg_bit_t TTCFG_b; + stc_can_ref_msg_bit_t REF_MSG_b; +} bCM_CAN_TypeDef; + +typedef struct { + stc_cmp_ctrl_bit_t CTRL_b; + stc_cmp_vltsel_bit_t VLTSEL_b; + stc_cmp_outmon_bit_t OUTMON_b; +} bCM_CMP_TypeDef; + +typedef struct { + uint32_t RESERVED0[2112]; + stc_cmp_common_dacr_bit_t DACR_b; + uint32_t RESERVED1[16]; + stc_cmp_common_rvadc_bit_t RVADC_b; +} bCM_CMP_COMMON_TypeDef; + +typedef struct { + stc_crc_cr_bit_t CR_b; + stc_crc_reslt_bit_t RESLT_b; + uint32_t RESERVED0[32]; + stc_crc_flg_bit_t FLG_b; +} bCM_CRC_TypeDef; + +typedef struct { + uint32_t RESERVED0[224]; + stc_dbgc_mcudbgstat_bit_t MCUDBGSTAT_b; + stc_dbgc_mcustpctl_bit_t MCUSTPCTL_b; + stc_dbgc_mcutracectl_bit_t MCUTRACECTL_b; +} bCM_DBGC_TypeDef; + +typedef struct { + stc_dcu_ctl_bit_t CTL_b; + stc_dcu_flag_bit_t FLAG_b; + uint32_t RESERVED0[96]; + stc_dcu_flagclr_bit_t FLAGCLR_b; + stc_dcu_intevtsel_bit_t INTEVTSEL_b; +} bCM_DCU_TypeDef; + +typedef struct { + stc_dma_en_bit_t EN_b; + stc_dma_intstat0_bit_t INTSTAT0_b; + stc_dma_intstat1_bit_t INTSTAT1_b; + stc_dma_intmask0_bit_t INTMASK0_b; + stc_dma_intmask1_bit_t INTMASK1_b; + stc_dma_intclr0_bit_t INTCLR0_b; + stc_dma_intclr1_bit_t INTCLR1_b; + uint32_t RESERVED0[32]; + stc_dma_reqstat_bit_t REQSTAT_b; + stc_dma_chstat_bit_t CHSTAT_b; + uint32_t RESERVED1[32]; + stc_dma_rcfgctl_bit_t RCFGCTL_b; + stc_dma_swreq_bit_t SWREQ_b; + uint32_t RESERVED2[320]; + stc_dma_chctl_bit_t CHCTL0_b; + uint32_t RESERVED3[480]; + stc_dma_chctl_bit_t CHCTL1_b; + uint32_t RESERVED4[480]; + stc_dma_chctl_bit_t CHCTL2_b; + uint32_t RESERVED5[480]; + stc_dma_chctl_bit_t CHCTL3_b; +} bCM_DMA_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_efm_fstp_bit_t FSTP_b; + stc_efm_frmc_bit_t FRMC_b; + stc_efm_fwmc_bit_t FWMC_b; + stc_efm_fsr_bit_t FSR_b; + stc_efm_fsclr_bit_t FSCLR_b; + stc_efm_fite_bit_t FITE_b; + stc_efm_fswp_bit_t FSWP_b; + uint32_t RESERVED1[1824]; + stc_efm_mmf_remcr_bit_t MMF_REMCR0_b; + stc_efm_mmf_remcr_bit_t MMF_REMCR1_b; +} bCM_EFM_TypeDef; + +typedef struct { + stc_emb_ctl_bit_t CTL_b; + stc_emb_pwmlv_bit_t PWMLV_b; + stc_emb_soe_bit_t SOE_b; + stc_emb_stat_bit_t STAT_b; + stc_emb_statclr_bit_t STATCLR_b; + stc_emb_inten_bit_t INTEN_b; +} bCM_EMB_TypeDef; + +typedef struct { + uint32_t RESERVED0[96]; + stc_fcm_str_bit_t STR_b; + uint32_t RESERVED1[32]; + stc_fcm_rccr_bit_t RCCR_b; + stc_fcm_rier_bit_t RIER_b; + stc_fcm_sr_bit_t SR_b; + stc_fcm_clr_bit_t CLR_b; +} bCM_FCM_TypeDef; + +typedef struct { + stc_gpio_pidr_bit_t PIDRA_b; + uint32_t RESERVED0[16]; + stc_gpio_podr_bit_t PODRA_b; + stc_gpio_poer_bit_t POERA_b; + stc_gpio_posr_bit_t POSRA_b; + stc_gpio_porr_bit_t PORRA_b; + stc_gpio_potr_bit_t POTRA_b; + uint32_t RESERVED1[16]; + stc_gpio_pidr_bit_t PIDRB_b; + uint32_t RESERVED2[16]; + stc_gpio_podr_bit_t PODRB_b; + stc_gpio_poer_bit_t POERB_b; + stc_gpio_posr_bit_t POSRB_b; + stc_gpio_porr_bit_t PORRB_b; + stc_gpio_potr_bit_t POTRB_b; + uint32_t RESERVED3[16]; + stc_gpio_pidr_bit_t PIDRC_b; + uint32_t RESERVED4[16]; + stc_gpio_podr_bit_t PODRC_b; + stc_gpio_poer_bit_t POERC_b; + stc_gpio_posr_bit_t POSRC_b; + stc_gpio_porr_bit_t PORRC_b; + stc_gpio_potr_bit_t POTRC_b; + uint32_t RESERVED5[16]; + stc_gpio_pidr_bit_t PIDRD_b; + uint32_t RESERVED6[16]; + stc_gpio_podr_bit_t PODRD_b; + stc_gpio_poer_bit_t POERD_b; + stc_gpio_posr_bit_t POSRD_b; + stc_gpio_porr_bit_t PORRD_b; + stc_gpio_potr_bit_t POTRD_b; + uint32_t RESERVED7[16]; + stc_gpio_pidr_bit_t PIDRE_b; + uint32_t RESERVED8[16]; + stc_gpio_podr_bit_t PODRE_b; + stc_gpio_poer_bit_t POERE_b; + stc_gpio_posr_bit_t POSRE_b; + stc_gpio_porr_bit_t PORRE_b; + stc_gpio_potr_bit_t POTRE_b; + uint32_t RESERVED9[16]; + stc_gpio_pidrh_bit_t PIDRH_b; + uint32_t RESERVED10[16]; + stc_gpio_podrh_bit_t PODRH_b; + stc_gpio_poerh_bit_t POERH_b; + stc_gpio_posrh_bit_t POSRH_b; + stc_gpio_porrh_bit_t PORRH_b; + stc_gpio_potrh_bit_t POTRH_b; + uint32_t RESERVED11[7408]; + stc_gpio_pwpr_bit_t PWPR_b; + uint32_t RESERVED12[16]; + stc_gpio_pcr_bit_t PCRA0_b; + stc_gpio_pfsr_bit_t PFSRA0_b; + stc_gpio_pcr_bit_t PCRA1_b; + stc_gpio_pfsr_bit_t PFSRA1_b; + stc_gpio_pcr_bit_t PCRA2_b; + stc_gpio_pfsr_bit_t PFSRA2_b; + stc_gpio_pcr_bit_t PCRA3_b; + stc_gpio_pfsr_bit_t PFSRA3_b; + stc_gpio_pcr_bit_t PCRA4_b; + stc_gpio_pfsr_bit_t PFSRA4_b; + stc_gpio_pcr_bit_t PCRA5_b; + stc_gpio_pfsr_bit_t PFSRA5_b; + stc_gpio_pcr_bit_t PCRA6_b; + stc_gpio_pfsr_bit_t PFSRA6_b; + stc_gpio_pcr_bit_t PCRA7_b; + stc_gpio_pfsr_bit_t PFSRA7_b; + stc_gpio_pcr_bit_t PCRA8_b; + stc_gpio_pfsr_bit_t PFSRA8_b; + stc_gpio_pcr_bit_t PCRA9_b; + stc_gpio_pfsr_bit_t PFSRA9_b; + stc_gpio_pcr_bit_t PCRA10_b; + stc_gpio_pfsr_bit_t PFSRA10_b; + stc_gpio_pcr_bit_t PCRA11_b; + stc_gpio_pfsr_bit_t PFSRA11_b; + stc_gpio_pcr_bit_t PCRA12_b; + stc_gpio_pfsr_bit_t PFSRA12_b; + stc_gpio_pcr_bit_t PCRA13_b; + stc_gpio_pfsr_bit_t PFSRA13_b; + stc_gpio_pcr_bit_t PCRA14_b; + stc_gpio_pfsr_bit_t PFSRA14_b; + stc_gpio_pcr_bit_t PCRA15_b; + stc_gpio_pfsr_bit_t PFSRA15_b; + stc_gpio_pcr_bit_t PCRB0_b; + stc_gpio_pfsr_bit_t PFSRB0_b; + stc_gpio_pcr_bit_t PCRB1_b; + stc_gpio_pfsr_bit_t PFSRB1_b; + stc_gpio_pcr_bit_t PCRB2_b; + stc_gpio_pfsr_bit_t PFSRB2_b; + stc_gpio_pcr_bit_t PCRB3_b; + stc_gpio_pfsr_bit_t PFSRB3_b; + stc_gpio_pcr_bit_t PCRB4_b; + stc_gpio_pfsr_bit_t PFSRB4_b; + stc_gpio_pcr_bit_t PCRB5_b; + stc_gpio_pfsr_bit_t PFSRB5_b; + stc_gpio_pcr_bit_t PCRB6_b; + stc_gpio_pfsr_bit_t PFSRB6_b; + stc_gpio_pcr_bit_t PCRB7_b; + stc_gpio_pfsr_bit_t PFSRB7_b; + stc_gpio_pcr_bit_t PCRB8_b; + stc_gpio_pfsr_bit_t PFSRB8_b; + stc_gpio_pcr_bit_t PCRB9_b; + stc_gpio_pfsr_bit_t PFSRB9_b; + stc_gpio_pcr_bit_t PCRB10_b; + stc_gpio_pfsr_bit_t PFSRB10_b; + stc_gpio_pcr_bit_t PCRB11_b; + stc_gpio_pfsr_bit_t PFSRB11_b; + stc_gpio_pcr_bit_t PCRB12_b; + stc_gpio_pfsr_bit_t PFSRB12_b; + stc_gpio_pcr_bit_t PCRB13_b; + stc_gpio_pfsr_bit_t PFSRB13_b; + stc_gpio_pcr_bit_t PCRB14_b; + stc_gpio_pfsr_bit_t PFSRB14_b; + stc_gpio_pcr_bit_t PCRB15_b; + stc_gpio_pfsr_bit_t PFSRB15_b; + stc_gpio_pcr_bit_t PCRC0_b; + stc_gpio_pfsr_bit_t PFSRC0_b; + stc_gpio_pcr_bit_t PCRC1_b; + stc_gpio_pfsr_bit_t PFSRC1_b; + stc_gpio_pcr_bit_t PCRC2_b; + stc_gpio_pfsr_bit_t PFSRC2_b; + stc_gpio_pcr_bit_t PCRC3_b; + stc_gpio_pfsr_bit_t PFSRC3_b; + stc_gpio_pcr_bit_t PCRC4_b; + stc_gpio_pfsr_bit_t PFSRC4_b; + stc_gpio_pcr_bit_t PCRC5_b; + stc_gpio_pfsr_bit_t PFSRC5_b; + stc_gpio_pcr_bit_t PCRC6_b; + stc_gpio_pfsr_bit_t PFSRC6_b; + stc_gpio_pcr_bit_t PCRC7_b; + stc_gpio_pfsr_bit_t PFSRC7_b; + stc_gpio_pcr_bit_t PCRC8_b; + stc_gpio_pfsr_bit_t PFSRC8_b; + stc_gpio_pcr_bit_t PCRC9_b; + stc_gpio_pfsr_bit_t PFSRC9_b; + stc_gpio_pcr_bit_t PCRC10_b; + stc_gpio_pfsr_bit_t PFSRC10_b; + stc_gpio_pcr_bit_t PCRC11_b; + stc_gpio_pfsr_bit_t PFSRC11_b; + stc_gpio_pcr_bit_t PCRC12_b; + stc_gpio_pfsr_bit_t PFSRC12_b; + stc_gpio_pcr_bit_t PCRC13_b; + stc_gpio_pfsr_bit_t PFSRC13_b; + stc_gpio_pcr_bit_t PCRC14_b; + stc_gpio_pfsr_bit_t PFSRC14_b; + stc_gpio_pcr_bit_t PCRC15_b; + stc_gpio_pfsr_bit_t PFSRC15_b; + stc_gpio_pcr_bit_t PCRD0_b; + stc_gpio_pfsr_bit_t PFSRD0_b; + stc_gpio_pcr_bit_t PCRD1_b; + stc_gpio_pfsr_bit_t PFSRD1_b; + stc_gpio_pcr_bit_t PCRD2_b; + stc_gpio_pfsr_bit_t PFSRD2_b; + stc_gpio_pcr_bit_t PCRD3_b; + stc_gpio_pfsr_bit_t PFSRD3_b; + stc_gpio_pcr_bit_t PCRD4_b; + stc_gpio_pfsr_bit_t PFSRD4_b; + stc_gpio_pcr_bit_t PCRD5_b; + stc_gpio_pfsr_bit_t PFSRD5_b; + stc_gpio_pcr_bit_t PCRD6_b; + stc_gpio_pfsr_bit_t PFSRD6_b; + stc_gpio_pcr_bit_t PCRD7_b; + stc_gpio_pfsr_bit_t PFSRD7_b; + stc_gpio_pcr_bit_t PCRD8_b; + stc_gpio_pfsr_bit_t PFSRD8_b; + stc_gpio_pcr_bit_t PCRD9_b; + stc_gpio_pfsr_bit_t PFSRD9_b; + stc_gpio_pcr_bit_t PCRD10_b; + stc_gpio_pfsr_bit_t PFSRD10_b; + stc_gpio_pcr_bit_t PCRD11_b; + stc_gpio_pfsr_bit_t PFSRD11_b; + stc_gpio_pcr_bit_t PCRD12_b; + stc_gpio_pfsr_bit_t PFSRD12_b; + stc_gpio_pcr_bit_t PCRD13_b; + stc_gpio_pfsr_bit_t PFSRD13_b; + stc_gpio_pcr_bit_t PCRD14_b; + stc_gpio_pfsr_bit_t PFSRD14_b; + stc_gpio_pcr_bit_t PCRD15_b; + stc_gpio_pfsr_bit_t PFSRD15_b; + stc_gpio_pcr_bit_t PCRE0_b; + stc_gpio_pfsr_bit_t PFSRE0_b; + stc_gpio_pcr_bit_t PCRE1_b; + stc_gpio_pfsr_bit_t PFSRE1_b; + stc_gpio_pcr_bit_t PCRE2_b; + stc_gpio_pfsr_bit_t PFSRE2_b; + stc_gpio_pcr_bit_t PCRE3_b; + stc_gpio_pfsr_bit_t PFSRE3_b; + stc_gpio_pcr_bit_t PCRE4_b; + stc_gpio_pfsr_bit_t PFSRE4_b; + stc_gpio_pcr_bit_t PCRE5_b; + stc_gpio_pfsr_bit_t PFSRE5_b; + stc_gpio_pcr_bit_t PCRE6_b; + stc_gpio_pfsr_bit_t PFSRE6_b; + stc_gpio_pcr_bit_t PCRE7_b; + stc_gpio_pfsr_bit_t PFSRE7_b; + stc_gpio_pcr_bit_t PCRE8_b; + stc_gpio_pfsr_bit_t PFSRE8_b; + stc_gpio_pcr_bit_t PCRE9_b; + stc_gpio_pfsr_bit_t PFSRE9_b; + stc_gpio_pcr_bit_t PCRE10_b; + stc_gpio_pfsr_bit_t PFSRE10_b; + stc_gpio_pcr_bit_t PCRE11_b; + stc_gpio_pfsr_bit_t PFSRE11_b; + stc_gpio_pcr_bit_t PCRE12_b; + stc_gpio_pfsr_bit_t PFSRE12_b; + stc_gpio_pcr_bit_t PCRE13_b; + stc_gpio_pfsr_bit_t PFSRE13_b; + stc_gpio_pcr_bit_t PCRE14_b; + stc_gpio_pfsr_bit_t PFSRE14_b; + stc_gpio_pcr_bit_t PCRE15_b; + stc_gpio_pfsr_bit_t PFSRE15_b; + stc_gpio_pcr_bit_t PCRH0_b; + stc_gpio_pfsr_bit_t PFSRH0_b; + stc_gpio_pcr_bit_t PCRH1_b; + stc_gpio_pfsr_bit_t PFSRH1_b; + stc_gpio_pcr_bit_t PCRH2_b; + stc_gpio_pfsr_bit_t PFSRH2_b; +} bCM_GPIO_TypeDef; + +typedef struct { + stc_hash_cr_bit_t CR_b; +} bCM_HASH_TypeDef; + +typedef struct { + stc_i2c_cr1_bit_t CR1_b; + stc_i2c_cr2_bit_t CR2_b; + stc_i2c_cr3_bit_t CR3_b; + stc_i2c_cr4_bit_t CR4_b; + stc_i2c_slr0_bit_t SLR0_b; + stc_i2c_slr1_bit_t SLR1_b; + uint32_t RESERVED0[32]; + stc_i2c_sr_bit_t SR_b; + stc_i2c_clr_bit_t CLR_b; + uint32_t RESERVED1[96]; + stc_i2c_fltr_bit_t FLTR_b; +} bCM_I2C_TypeDef; + +typedef struct { + stc_i2s_ctrl_bit_t CTRL_b; + stc_i2s_sr_bit_t SR_b; + stc_i2s_er_bit_t ER_b; + stc_i2s_cfgr_bit_t CFGR_b; +} bCM_I2S_TypeDef; + +typedef struct { + stc_icg_icg0_bit_t ICG0_b; + stc_icg_icg1_bit_t ICG1_b; +} bCM_ICG_TypeDef; + +typedef struct { + stc_intc_nmicr_bit_t NMICR_b; + stc_intc_nmienr_bit_t NMIENR_b; + stc_intc_nmifr_bit_t NMIFR_b; + stc_intc_nmicfr_bit_t NMICFR_b; + stc_intc_eirqcr_bit_t EIRQCR0_b; + stc_intc_eirqcr_bit_t EIRQCR1_b; + stc_intc_eirqcr_bit_t EIRQCR2_b; + stc_intc_eirqcr_bit_t EIRQCR3_b; + stc_intc_eirqcr_bit_t EIRQCR4_b; + stc_intc_eirqcr_bit_t EIRQCR5_b; + stc_intc_eirqcr_bit_t EIRQCR6_b; + stc_intc_eirqcr_bit_t EIRQCR7_b; + stc_intc_eirqcr_bit_t EIRQCR8_b; + stc_intc_eirqcr_bit_t EIRQCR9_b; + stc_intc_eirqcr_bit_t EIRQCR10_b; + stc_intc_eirqcr_bit_t EIRQCR11_b; + stc_intc_eirqcr_bit_t EIRQCR12_b; + stc_intc_eirqcr_bit_t EIRQCR13_b; + stc_intc_eirqcr_bit_t EIRQCR14_b; + stc_intc_eirqcr_bit_t EIRQCR15_b; + stc_intc_wupen_bit_t WUPEN_b; + stc_intc_eifr_bit_t EIFR_b; + stc_intc_eifcr_bit_t EIFCR_b; + uint32_t RESERVED0[4096]; + stc_intc_vssel_bit_t VSSEL128_b; + stc_intc_vssel_bit_t VSSEL129_b; + stc_intc_vssel_bit_t VSSEL130_b; + stc_intc_vssel_bit_t VSSEL131_b; + stc_intc_vssel_bit_t VSSEL132_b; + stc_intc_vssel_bit_t VSSEL133_b; + stc_intc_vssel_bit_t VSSEL134_b; + stc_intc_vssel_bit_t VSSEL135_b; + stc_intc_vssel_bit_t VSSEL136_b; + stc_intc_vssel_bit_t VSSEL137_b; + stc_intc_vssel_bit_t VSSEL138_b; + stc_intc_vssel_bit_t VSSEL139_b; + stc_intc_vssel_bit_t VSSEL140_b; + stc_intc_vssel_bit_t VSSEL141_b; + stc_intc_vssel_bit_t VSSEL142_b; + stc_intc_vssel_bit_t VSSEL143_b; + stc_intc_swier_bit_t SWIER_b; + stc_intc_evter_bit_t EVTER_b; + stc_intc_ier_bit_t IER_b; +} bCM_INTC_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_keyscan_ser_bit_t SER_b; +} bCM_KEYSCAN_TypeDef; + +typedef struct { + uint32_t RESERVED0[512]; + stc_mpu_rgcr_bit_t RGCR0_b; + stc_mpu_rgcr_bit_t RGCR1_b; + stc_mpu_rgcr_bit_t RGCR2_b; + stc_mpu_rgcr_bit_t RGCR3_b; + stc_mpu_rgcr_bit_t RGCR4_b; + stc_mpu_rgcr_bit_t RGCR5_b; + stc_mpu_rgcr_bit_t RGCR6_b; + stc_mpu_rgcr_bit_t RGCR7_b; + stc_mpu_rgcr_bit_t RGCR8_b; + stc_mpu_rgcr_bit_t RGCR9_b; + stc_mpu_rgcr_bit_t RGCR10_b; + stc_mpu_rgcr_bit_t RGCR11_b; + stc_mpu_rgcr_bit_t RGCR12_b; + stc_mpu_rgcr_bit_t RGCR13_b; + stc_mpu_rgcr_bit_t RGCR14_b; + stc_mpu_rgcr_bit_t RGCR15_b; + stc_mpu_cr_bit_t CR_b; + stc_mpu_sr_bit_t SR_b; + stc_mpu_eclr_bit_t ECLR_b; + stc_mpu_wp_bit_t WP_b; + uint32_t RESERVED1[130144]; + stc_mpu_ippr_bit_t IPPR_b; +} bCM_MPU_TypeDef; + +typedef struct { + stc_ots_ctl_bit_t CTL_b; +} bCM_OTS_TypeDef; + +typedef struct { + stc_peric_usbfs_syctlreg_bit_t USBFS_SYCTLREG_b; + stc_peric_sdioc_syctlreg_bit_t SDIOC_SYCTLREG_b; +} bCM_PERIC_TypeDef; + +typedef struct { + stc_qspi_cr_bit_t CR_b; + uint32_t RESERVED0[32]; + stc_qspi_fcr_bit_t FCR_b; + stc_qspi_sr_bit_t SR_b; + uint32_t RESERVED1[160]; + stc_qspi_clr_bit_t CLR_b; +} bCM_QSPI_TypeDef; + +typedef struct { + stc_rmu_rstf0_bit_t RSTF0_b; +} bCM_RMU_TypeDef; + +typedef struct { + stc_rtc_cr0_bit_t CR0_b; + uint32_t RESERVED0[24]; + stc_rtc_cr1_bit_t CR1_b; + uint32_t RESERVED1[24]; + stc_rtc_cr2_bit_t CR2_b; + uint32_t RESERVED2[24]; + stc_rtc_cr3_bit_t CR3_b; + uint32_t RESERVED3[344]; + stc_rtc_errcrh_bit_t ERRCRH_b; +} bCM_RTC_TypeDef; + +typedef struct { + uint32_t RESERVED0[96]; + stc_sdioc_transmode_bit_t TRANSMODE_b; + stc_sdioc_cmd_bit_t CMD_b; + uint32_t RESERVED1[160]; + stc_sdioc_pstat_bit_t PSTAT_b; + stc_sdioc_hostcon_bit_t HOSTCON_b; + stc_sdioc_pwrcon_bit_t PWRCON_b; + stc_sdioc_blkgpcon_bit_t BLKGPCON_b; + uint32_t RESERVED2[8]; + stc_sdioc_clkcon_bit_t CLKCON_b; + uint32_t RESERVED3[8]; + stc_sdioc_sftrst_bit_t SFTRST_b; + stc_sdioc_norintst_bit_t NORINTST_b; + stc_sdioc_errintst_bit_t ERRINTST_b; + stc_sdioc_norintsten_bit_t NORINTSTEN_b; + stc_sdioc_errintsten_bit_t ERRINTSTEN_b; + stc_sdioc_norintsgen_bit_t NORINTSGEN_b; + stc_sdioc_errintsgen_bit_t ERRINTSGEN_b; + stc_sdioc_atcerrst_bit_t ATCERRST_b; + uint32_t RESERVED4[144]; + stc_sdioc_fea_bit_t FEA_b; + stc_sdioc_fee_bit_t FEE_b; +} bCM_SDIOC_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_spi_cr1_bit_t CR1_b; + uint32_t RESERVED1[32]; + stc_spi_cfg1_bit_t CFG1_b; + uint32_t RESERVED2[32]; + stc_spi_sr_bit_t SR_b; + stc_spi_cfg2_bit_t CFG2_b; +} bCM_SPI_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_sramc_wtpr_bit_t WTPR_b; + stc_sramc_ckcr_bit_t CKCR_b; + stc_sramc_ckpr_bit_t CKPR_b; + stc_sramc_cksr_bit_t CKSR_b; +} bCM_SRAMC_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_swdt_sr_bit_t SR_b; +} bCM_SWDT_TypeDef; + +typedef struct { + uint32_t RESERVED0[128]; + stc_tmr0_bconr_bit_t BCONR_b; + stc_tmr0_stflr_bit_t STFLR_b; +} bCM_TMR0_TypeDef; + +typedef struct { + uint32_t RESERVED0[192]; + stc_tmr4_ocsr_bit_t OCSRU_b; + stc_tmr4_ocer_bit_t OCERU_b; + stc_tmr4_ocsr_bit_t OCSRV_b; + stc_tmr4_ocer_bit_t OCERV_b; + stc_tmr4_ocsr_bit_t OCSRW_b; + stc_tmr4_ocer_bit_t OCERW_b; + stc_tmr4_ocmrh_bit_t OCMRUH_b; + uint32_t RESERVED1[16]; + stc_tmr4_ocmrl_bit_t OCMRUL_b; + stc_tmr4_ocmrh_bit_t OCMRVH_b; + uint32_t RESERVED2[16]; + stc_tmr4_ocmrl_bit_t OCMRVL_b; + stc_tmr4_ocmrh_bit_t OCMRWH_b; + uint32_t RESERVED3[16]; + stc_tmr4_ocmrl_bit_t OCMRWL_b; + uint32_t RESERVED4[96]; + stc_tmr4_ccsr_bit_t CCSR_b; + uint32_t RESERVED5[720]; + stc_tmr4_rcsr_bit_t RCSR_b; + uint32_t RESERVED6[272]; + stc_tmr4_scsr_bit_t SCSRUH_b; + stc_tmr4_scmr_bit_t SCMRUH_b; + stc_tmr4_scsr_bit_t SCSRUL_b; + stc_tmr4_scmr_bit_t SCMRUL_b; + stc_tmr4_scsr_bit_t SCSRVH_b; + stc_tmr4_scmr_bit_t SCMRVH_b; + stc_tmr4_scsr_bit_t SCSRVL_b; + stc_tmr4_scmr_bit_t SCMRVL_b; + stc_tmr4_scsr_bit_t SCSRWH_b; + stc_tmr4_scmr_bit_t SCMRWH_b; + stc_tmr4_scsr_bit_t SCSRWL_b; + stc_tmr4_scmr_bit_t SCMRWL_b; + uint32_t RESERVED7[128]; + stc_tmr4_ecsr_bit_t ECSR_b; +} bCM_TMR4_TypeDef; + +typedef struct { + uint32_t RESERVED0[640]; + stc_tmr6_gconr_bit_t GCONR_b; + stc_tmr6_iconr_bit_t ICONR_b; + stc_tmr6_pconr_bit_t PCONR_b; + stc_tmr6_bconr_bit_t BCONR_b; + stc_tmr6_dconr_bit_t DCONR_b; + uint32_t RESERVED1[32]; + stc_tmr6_fconr_bit_t FCONR_b; + stc_tmr6_vperr_bit_t VPERR_b; + stc_tmr6_stflr_bit_t STFLR_b; + stc_tmr6_hstar_bit_t HSTAR_b; + stc_tmr6_hstpr_bit_t HSTPR_b; + stc_tmr6_hclrr_bit_t HCLRR_b; + stc_tmr6_hcpar_bit_t HCPAR_b; + stc_tmr6_hcpbr_bit_t HCPBR_b; + stc_tmr6_hcupr_bit_t HCUPR_b; + stc_tmr6_hcdor_bit_t HCDOR_b; +} bCM_TMR6_TypeDef; + +typedef struct { + uint32_t RESERVED0[1952]; + stc_tmr6_common_sstar_bit_t SSTAR_b; + stc_tmr6_common_sstpr_bit_t SSTPR_b; + stc_tmr6_common_sclrr_bit_t SCLRR_b; +} bCM_TMR6_COMMON_TypeDef; + +typedef struct { + uint32_t RESERVED0[1024]; + stc_tmra_bcstrl_bit_t BCSTRL_b; + stc_tmra_bcstrh_bit_t BCSTRH_b; + uint32_t RESERVED1[16]; + stc_tmra_hconr_bit_t HCONR_b; + uint32_t RESERVED2[16]; + stc_tmra_hcupr_bit_t HCUPR_b; + uint32_t RESERVED3[16]; + stc_tmra_hcdor_bit_t HCDOR_b; + uint32_t RESERVED4[16]; + stc_tmra_iconr_bit_t ICONR_b; + uint32_t RESERVED5[16]; + stc_tmra_econr_bit_t ECONR_b; + uint32_t RESERVED6[16]; + stc_tmra_fconr_bit_t FCONR_b; + uint32_t RESERVED7[16]; + stc_tmra_stflr_bit_t STFLR_b; + uint32_t RESERVED8[272]; + stc_tmra_bconr_bit_t BCONR1_b; + uint32_t RESERVED9[48]; + stc_tmra_bconr_bit_t BCONR2_b; + uint32_t RESERVED10[48]; + stc_tmra_bconr_bit_t BCONR3_b; + uint32_t RESERVED11[48]; + stc_tmra_bconr_bit_t BCONR4_b; + uint32_t RESERVED12[304]; + stc_tmra_cconr_bit_t CCONR1_b; + uint32_t RESERVED13[16]; + stc_tmra_cconr_bit_t CCONR2_b; + uint32_t RESERVED14[16]; + stc_tmra_cconr_bit_t CCONR3_b; + uint32_t RESERVED15[16]; + stc_tmra_cconr_bit_t CCONR4_b; + uint32_t RESERVED16[16]; + stc_tmra_cconr_bit_t CCONR5_b; + uint32_t RESERVED17[16]; + stc_tmra_cconr_bit_t CCONR6_b; + uint32_t RESERVED18[16]; + stc_tmra_cconr_bit_t CCONR7_b; + uint32_t RESERVED19[16]; + stc_tmra_cconr_bit_t CCONR8_b; + uint32_t RESERVED20[272]; + stc_tmra_pconr_bit_t PCONR1_b; + uint32_t RESERVED21[16]; + stc_tmra_pconr_bit_t PCONR2_b; + uint32_t RESERVED22[16]; + stc_tmra_pconr_bit_t PCONR3_b; + uint32_t RESERVED23[16]; + stc_tmra_pconr_bit_t PCONR4_b; + uint32_t RESERVED24[16]; + stc_tmra_pconr_bit_t PCONR5_b; + uint32_t RESERVED25[16]; + stc_tmra_pconr_bit_t PCONR6_b; + uint32_t RESERVED26[16]; + stc_tmra_pconr_bit_t PCONR7_b; + uint32_t RESERVED27[16]; + stc_tmra_pconr_bit_t PCONR8_b; +} bCM_TMRA_TypeDef; + +typedef struct { + stc_trng_cr_bit_t CR_b; + stc_trng_mr_bit_t MR_b; +} bCM_TRNG_TypeDef; + +typedef struct { + stc_usart_sr_bit_t SR_b; + stc_usart_tdr_bit_t TDR_b; + uint32_t RESERVED0[48]; + stc_usart_cr1_bit_t CR1_b; + stc_usart_cr2_bit_t CR2_b; + stc_usart_cr3_bit_t CR3_b; +} bCM_USART_TypeDef; + +typedef struct { + stc_usbfs_gvbuscfg_bit_t GVBUSCFG_b; + uint32_t RESERVED0[32]; + stc_usbfs_gahbcfg_bit_t GAHBCFG_b; + stc_usbfs_gusbcfg_bit_t GUSBCFG_b; + stc_usbfs_grstctl_bit_t GRSTCTL_b; + stc_usbfs_gintsts_bit_t GINTSTS_b; + stc_usbfs_gintmsk_bit_t GINTMSK_b; + uint32_t RESERVED1[7968]; + stc_usbfs_hcfg_bit_t HCFG_b; + uint32_t RESERVED2[480]; + stc_usbfs_hprt_bit_t HPRT_b; + uint32_t RESERVED3[1504]; + stc_usbfs_hcchar_bit_t HCCHAR0_b; + uint32_t RESERVED4[32]; + stc_usbfs_hcint_bit_t HCINT0_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK0_b; + uint32_t RESERVED5[128]; + stc_usbfs_hcchar_bit_t HCCHAR1_b; + uint32_t RESERVED6[32]; + stc_usbfs_hcint_bit_t HCINT1_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK1_b; + uint32_t RESERVED7[128]; + stc_usbfs_hcchar_bit_t HCCHAR2_b; + uint32_t RESERVED8[32]; + stc_usbfs_hcint_bit_t HCINT2_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK2_b; + uint32_t RESERVED9[128]; + stc_usbfs_hcchar_bit_t HCCHAR3_b; + uint32_t RESERVED10[32]; + stc_usbfs_hcint_bit_t HCINT3_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK3_b; + uint32_t RESERVED11[128]; + stc_usbfs_hcchar_bit_t HCCHAR4_b; + uint32_t RESERVED12[32]; + stc_usbfs_hcint_bit_t HCINT4_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK4_b; + uint32_t RESERVED13[128]; + stc_usbfs_hcchar_bit_t HCCHAR5_b; + uint32_t RESERVED14[32]; + stc_usbfs_hcint_bit_t HCINT5_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK5_b; + uint32_t RESERVED15[128]; + stc_usbfs_hcchar_bit_t HCCHAR6_b; + uint32_t RESERVED16[32]; + stc_usbfs_hcint_bit_t HCINT6_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK6_b; + uint32_t RESERVED17[128]; + stc_usbfs_hcchar_bit_t HCCHAR7_b; + uint32_t RESERVED18[32]; + stc_usbfs_hcint_bit_t HCINT7_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK7_b; + uint32_t RESERVED19[128]; + stc_usbfs_hcchar_bit_t HCCHAR8_b; + uint32_t RESERVED20[32]; + stc_usbfs_hcint_bit_t HCINT8_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK8_b; + uint32_t RESERVED21[128]; + stc_usbfs_hcchar_bit_t HCCHAR9_b; + uint32_t RESERVED22[32]; + stc_usbfs_hcint_bit_t HCINT9_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK9_b; + uint32_t RESERVED23[128]; + stc_usbfs_hcchar_bit_t HCCHAR10_b; + uint32_t RESERVED24[32]; + stc_usbfs_hcint_bit_t HCINT10_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK10_b; + uint32_t RESERVED25[128]; + stc_usbfs_hcchar_bit_t HCCHAR11_b; + uint32_t RESERVED26[32]; + stc_usbfs_hcint_bit_t HCINT11_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK11_b; + uint32_t RESERVED27[3200]; + stc_usbfs_dcfg_bit_t DCFG_b; + stc_usbfs_dctl_bit_t DCTL_b; + stc_usbfs_dsts_bit_t DSTS_b; + uint32_t RESERVED28[32]; + stc_usbfs_diepmsk_bit_t DIEPMSK_b; + stc_usbfs_doepmsk_bit_t DOEPMSK_b; + uint32_t RESERVED29[1856]; + stc_usbfs_diepctl0_bit_t DIEPCTL0_b; + uint32_t RESERVED30[32]; + stc_usbfs_diepint_bit_t DIEPINT0_b; + uint32_t RESERVED31[160]; + stc_usbfs_diepctl_bit_t DIEPCTL1_b; + uint32_t RESERVED32[32]; + stc_usbfs_diepint_bit_t DIEPINT1_b; + uint32_t RESERVED33[160]; + stc_usbfs_diepctl_bit_t DIEPCTL2_b; + uint32_t RESERVED34[32]; + stc_usbfs_diepint_bit_t DIEPINT2_b; + uint32_t RESERVED35[160]; + stc_usbfs_diepctl_bit_t DIEPCTL3_b; + uint32_t RESERVED36[32]; + stc_usbfs_diepint_bit_t DIEPINT3_b; + uint32_t RESERVED37[160]; + stc_usbfs_diepctl_bit_t DIEPCTL4_b; + uint32_t RESERVED38[32]; + stc_usbfs_diepint_bit_t DIEPINT4_b; + uint32_t RESERVED39[160]; + stc_usbfs_diepctl_bit_t DIEPCTL5_b; + uint32_t RESERVED40[32]; + stc_usbfs_diepint_bit_t DIEPINT5_b; + uint32_t RESERVED41[2720]; + stc_usbfs_doepctl0_bit_t DOEPCTL0_b; + uint32_t RESERVED42[32]; + stc_usbfs_doepint_bit_t DOEPINT0_b; + uint32_t RESERVED43[32]; + stc_usbfs_doeptsiz0_bit_t DOEPTSIZ0_b; + uint32_t RESERVED44[96]; + stc_usbfs_doepctl_bit_t DOEPCTL1_b; + uint32_t RESERVED45[32]; + stc_usbfs_doepint_bit_t DOEPINT1_b; + uint32_t RESERVED46[160]; + stc_usbfs_doepctl_bit_t DOEPCTL2_b; + uint32_t RESERVED47[32]; + stc_usbfs_doepint_bit_t DOEPINT2_b; + uint32_t RESERVED48[160]; + stc_usbfs_doepctl_bit_t DOEPCTL3_b; + uint32_t RESERVED49[32]; + stc_usbfs_doepint_bit_t DOEPINT3_b; + uint32_t RESERVED50[160]; + stc_usbfs_doepctl_bit_t DOEPCTL4_b; + uint32_t RESERVED51[32]; + stc_usbfs_doepint_bit_t DOEPINT4_b; + uint32_t RESERVED52[160]; + stc_usbfs_doepctl_bit_t DOEPCTL5_b; + uint32_t RESERVED53[32]; + stc_usbfs_doepint_bit_t DOEPINT5_b; + uint32_t RESERVED54[4768]; + stc_usbfs_gcctl_bit_t GCCTL_b; +} bCM_USBFS_TypeDef; + +typedef struct { + stc_wdt_cr_bit_t CR_b; + stc_wdt_sr_bit_t SR_b; +} bCM_WDT_TypeDef; + + +/******************************************************************************/ +/* Device Specific Peripheral bit_band declaration & memory map */ +/******************************************************************************/ +#define bCM_ADC1 ((bCM_ADC_TypeDef *)0x42800000UL) +#define bCM_ADC2 ((bCM_ADC_TypeDef *)0x42808000UL) +#define bCM_AES ((bCM_AES_TypeDef *)0x42100000UL) +#define bCM_AOS ((bCM_AOS_TypeDef *)0x42210000UL) +#define bCM_CAN ((bCM_CAN_TypeDef *)0x42E08000UL) +#define bCM_CMP1 ((bCM_CMP_TypeDef *)0x42940000UL) +#define bCM_CMP2 ((bCM_CMP_TypeDef *)0x42940200UL) +#define bCM_CMP3 ((bCM_CMP_TypeDef *)0x42940400UL) +#define bCM_CMP_COMMON ((bCM_CMP_COMMON_TypeDef *)0x42940000UL) +#define bCM_CRC ((bCM_CRC_TypeDef *)0x42118000UL) +#define bCM_DCU1 ((bCM_DCU_TypeDef *)0x42A40000UL) +#define bCM_DCU2 ((bCM_DCU_TypeDef *)0x42A48000UL) +#define bCM_DCU3 ((bCM_DCU_TypeDef *)0x42A50000UL) +#define bCM_DCU4 ((bCM_DCU_TypeDef *)0x42A58000UL) +#define bCM_DMA1 ((bCM_DMA_TypeDef *)0x42A60000UL) +#define bCM_DMA2 ((bCM_DMA_TypeDef *)0x42A68000UL) +#define bCM_EFM ((bCM_EFM_TypeDef *)0x42208000UL) +#define bCM_EMB0 ((bCM_EMB_TypeDef *)0x422F8000UL) +#define bCM_EMB1 ((bCM_EMB_TypeDef *)0x422F8400UL) +#define bCM_EMB2 ((bCM_EMB_TypeDef *)0x422F8800UL) +#define bCM_EMB3 ((bCM_EMB_TypeDef *)0x422F8C00UL) +#define bCM_FCM ((bCM_FCM_TypeDef *)0x42908000UL) +#define bCM_GPIO ((bCM_GPIO_TypeDef *)0x42A70000UL) +#define bCM_HASH ((bCM_HASH_TypeDef *)0x42108000UL) +#define bCM_I2C1 ((bCM_I2C_TypeDef *)0x429C0000UL) +#define bCM_I2C2 ((bCM_I2C_TypeDef *)0x429C8000UL) +#define bCM_I2C3 ((bCM_I2C_TypeDef *)0x429D0000UL) +#define bCM_I2S1 ((bCM_I2S_TypeDef *)0x423C0000UL) +#define bCM_I2S2 ((bCM_I2S_TypeDef *)0x423C8000UL) +#define bCM_I2S3 ((bCM_I2S_TypeDef *)0x42440000UL) +#define bCM_I2S4 ((bCM_I2S_TypeDef *)0x42448000UL) +#define bCM_INTC ((bCM_INTC_TypeDef *)0x42A20000UL) +#define bCM_KEYSCAN ((bCM_KEYSCAN_TypeDef *)0x42A18000UL) +#define bCM_MPU ((bCM_MPU_TypeDef *)0x42A00000UL) +#define bCM_OTS ((bCM_OTS_TypeDef *)0x42948000UL) +#define bCM_PERIC ((bCM_PERIC_TypeDef *)0x42AA8000UL) +#define bCM_RMU ((bCM_RMU_TypeDef *)0x42A81800UL) +#define bCM_RTC ((bCM_RTC_TypeDef *)0x42980000UL) +#define bCM_SDIOC1 ((bCM_SDIOC_TypeDef *)0x42DF8000UL) +#define bCM_SDIOC2 ((bCM_SDIOC_TypeDef *)0x42E00000UL) +#define bCM_SPI1 ((bCM_SPI_TypeDef *)0x42380000UL) +#define bCM_SPI2 ((bCM_SPI_TypeDef *)0x42388000UL) +#define bCM_SPI3 ((bCM_SPI_TypeDef *)0x42400000UL) +#define bCM_SPI4 ((bCM_SPI_TypeDef *)0x42408000UL) +#define bCM_SRAMC ((bCM_SRAMC_TypeDef *)0x42A10000UL) +#define bCM_SWDT ((bCM_SWDT_TypeDef *)0x42928000UL) +#define bCM_TMR0_1 ((bCM_TMR0_TypeDef *)0x42480000UL) +#define bCM_TMR0_2 ((bCM_TMR0_TypeDef *)0x42488000UL) +#define bCM_TMR4_1 ((bCM_TMR4_TypeDef *)0x422E0000UL) +#define bCM_TMR4_2 ((bCM_TMR4_TypeDef *)0x42490000UL) +#define bCM_TMR4_3 ((bCM_TMR4_TypeDef *)0x42498000UL) +#define bCM_TMR6_1 ((bCM_TMR6_TypeDef *)0x42300000UL) +#define bCM_TMR6_2 ((bCM_TMR6_TypeDef *)0x42308000UL) +#define bCM_TMR6_3 ((bCM_TMR6_TypeDef *)0x42310000UL) +#define bCM_TMR6_COMMON ((bCM_TMR6_COMMON_TypeDef *)0x42306000UL) +#define bCM_TMRA_1 ((bCM_TMRA_TypeDef *)0x422A0000UL) +#define bCM_TMRA_2 ((bCM_TMRA_TypeDef *)0x422A8000UL) +#define bCM_TMRA_3 ((bCM_TMRA_TypeDef *)0x422B0000UL) +#define bCM_TMRA_4 ((bCM_TMRA_TypeDef *)0x422B8000UL) +#define bCM_TMRA_5 ((bCM_TMRA_TypeDef *)0x422C0000UL) +#define bCM_TMRA_6 ((bCM_TMRA_TypeDef *)0x422C8000UL) +#define bCM_TRNG ((bCM_TRNG_TypeDef *)0x42820000UL) +#define bCM_USART1 ((bCM_USART_TypeDef *)0x423A0000UL) +#define bCM_USART2 ((bCM_USART_TypeDef *)0x423A8000UL) +#define bCM_USART3 ((bCM_USART_TypeDef *)0x42420000UL) +#define bCM_USART4 ((bCM_USART_TypeDef *)0x42428000UL) +#define bCM_USBFS ((bCM_USBFS_TypeDef *)0x43800000UL) +#define bCM_WDT ((bCM_WDT_TypeDef *)0x42920000UL) + + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460PETB_H__ */ diff --git a/Project/RTE/Device/HC32F460PETB/HC32F460PETB.h.base@1.0.0 b/Project/RTE/Device/HC32F460PETB/HC32F460PETB.h.base@1.0.0 new file mode 100644 index 0000000..a898c7c --- /dev/null +++ b/Project/RTE/Device/HC32F460PETB/HC32F460PETB.h.base@1.0.0 @@ -0,0 +1,12351 @@ +/** + ******************************************************************************* + * @file HC32F460PETB.h + * @brief Headerfile for HC32F460PETB series MCU + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-01-15 CDT Modify headfile based on reference manual Rev1.5 + 2023-09-30 CDT Modify headfile based on reference manual Rev1.6 + Optimze for the unused bit definitions + 2024-11-08 CDT Modify CMP/DBGC/DCU/DMA/QSPI/TMR4/TMR6/I2C/I2S registers + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + **/ + +#ifndef __HC32F460PETB_H__ +#define __HC32F460PETB_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Configuration of the Cortex-M4 Processor and Core Peripherals + ******************************************************************************/ +#define __MPU_PRESENT 1 /*!< HC32F460PETB provides MPU */ +#define __VTOR_PRESENT 1 /*!< HC32F460PETB supported vector table registers */ +#define __NVIC_PRIO_BITS 4 /*!< HC32F460PETB uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/******************************************************************************* + * Interrupt Number Definition + ******************************************************************************/ +typedef enum { + NMI_IRQn = -14, /* Non Maskable */ + HardFault_IRQn = -13, /* Hard Fault */ + MemManageFault_IRQn = -12, /* MemManage Fault */ + BusFault_IRQn = -11, /* Bus Fault */ + UsageFault_IRQn = -10, /* Usage Fault */ + SVC_IRQn = -5, /* SVCall */ + DebugMonitor_IRQn = -4, /* DebugMonitor */ + PendSV_IRQn = -2, /* Pend SV */ + SysTick_IRQn = -1, /* System Tick */ + INT000_IRQn = 0, + INT001_IRQn = 1, + INT002_IRQn = 2, + INT003_IRQn = 3, + INT004_IRQn = 4, + INT005_IRQn = 5, + INT006_IRQn = 6, + INT007_IRQn = 7, + INT008_IRQn = 8, + INT009_IRQn = 9, + INT010_IRQn = 10, + INT011_IRQn = 11, + INT012_IRQn = 12, + INT013_IRQn = 13, + INT014_IRQn = 14, + INT015_IRQn = 15, + INT016_IRQn = 16, + INT017_IRQn = 17, + INT018_IRQn = 18, + INT019_IRQn = 19, + INT020_IRQn = 20, + INT021_IRQn = 21, + INT022_IRQn = 22, + INT023_IRQn = 23, + INT024_IRQn = 24, + INT025_IRQn = 25, + INT026_IRQn = 26, + INT027_IRQn = 27, + INT028_IRQn = 28, + INT029_IRQn = 29, + INT030_IRQn = 30, + INT031_IRQn = 31, + INT032_IRQn = 32, + INT033_IRQn = 33, + INT034_IRQn = 34, + INT035_IRQn = 35, + INT036_IRQn = 36, + INT037_IRQn = 37, + INT038_IRQn = 38, + INT039_IRQn = 39, + INT040_IRQn = 40, + INT041_IRQn = 41, + INT042_IRQn = 42, + INT043_IRQn = 43, + INT044_IRQn = 44, + INT045_IRQn = 45, + INT046_IRQn = 46, + INT047_IRQn = 47, + INT048_IRQn = 48, + INT049_IRQn = 49, + INT050_IRQn = 50, + INT051_IRQn = 51, + INT052_IRQn = 52, + INT053_IRQn = 53, + INT054_IRQn = 54, + INT055_IRQn = 55, + INT056_IRQn = 56, + INT057_IRQn = 57, + INT058_IRQn = 58, + INT059_IRQn = 59, + INT060_IRQn = 60, + INT061_IRQn = 61, + INT062_IRQn = 62, + INT063_IRQn = 63, + INT064_IRQn = 64, + INT065_IRQn = 65, + INT066_IRQn = 66, + INT067_IRQn = 67, + INT068_IRQn = 68, + INT069_IRQn = 69, + INT070_IRQn = 70, + INT071_IRQn = 71, + INT072_IRQn = 72, + INT073_IRQn = 73, + INT074_IRQn = 74, + INT075_IRQn = 75, + INT076_IRQn = 76, + INT077_IRQn = 77, + INT078_IRQn = 78, + INT079_IRQn = 79, + INT080_IRQn = 80, + INT081_IRQn = 81, + INT082_IRQn = 82, + INT083_IRQn = 83, + INT084_IRQn = 84, + INT085_IRQn = 85, + INT086_IRQn = 86, + INT087_IRQn = 87, + INT088_IRQn = 88, + INT089_IRQn = 89, + INT090_IRQn = 90, + INT091_IRQn = 91, + INT092_IRQn = 92, + INT093_IRQn = 93, + INT094_IRQn = 94, + INT095_IRQn = 95, + INT096_IRQn = 96, + INT097_IRQn = 97, + INT098_IRQn = 98, + INT099_IRQn = 99, + INT100_IRQn = 100, + INT101_IRQn = 101, + INT102_IRQn = 102, + INT103_IRQn = 103, + INT104_IRQn = 104, + INT105_IRQn = 105, + INT106_IRQn = 106, + INT107_IRQn = 107, + INT108_IRQn = 108, + INT109_IRQn = 109, + INT110_IRQn = 110, + INT111_IRQn = 111, + INT112_IRQn = 112, + INT113_IRQn = 113, + INT114_IRQn = 114, + INT115_IRQn = 115, + INT116_IRQn = 116, + INT117_IRQn = 117, + INT118_IRQn = 118, + INT119_IRQn = 119, + INT120_IRQn = 120, + INT121_IRQn = 121, + INT122_IRQn = 122, + INT123_IRQn = 123, + INT124_IRQn = 124, + INT125_IRQn = 125, + INT126_IRQn = 126, + INT127_IRQn = 127, + INT128_IRQn = 128, + INT129_IRQn = 129, + INT130_IRQn = 130, + INT131_IRQn = 131, + INT132_IRQn = 132, + INT133_IRQn = 133, + INT134_IRQn = 134, + INT135_IRQn = 135, + INT136_IRQn = 136, + INT137_IRQn = 137, + INT138_IRQn = 138, + INT139_IRQn = 139, + INT140_IRQn = 140, + INT141_IRQn = 141, + INT142_IRQn = 142, + INT143_IRQn = 143, + +} IRQn_Type; + +#include +#include + +/** + ******************************************************************************* + ** \brief Event number enumeration + ******************************************************************************/ +typedef enum { + EVT_SRC_SWI_IRQ0 = 0U, /* SWI_IRQ0 */ + EVT_SRC_SWI_IRQ1 = 1U, /* SWI_IRQ1 */ + EVT_SRC_SWI_IRQ2 = 2U, /* SWI_IRQ2 */ + EVT_SRC_SWI_IRQ3 = 3U, /* SWI_IRQ3 */ + EVT_SRC_SWI_IRQ4 = 4U, /* SWI_IRQ4 */ + EVT_SRC_SWI_IRQ5 = 5U, /* SWI_IRQ5 */ + EVT_SRC_SWI_IRQ6 = 6U, /* SWI_IRQ6 */ + EVT_SRC_SWI_IRQ7 = 7U, /* SWI_IRQ7 */ + EVT_SRC_SWI_IRQ8 = 8U, /* SWI_IRQ8 */ + EVT_SRC_SWI_IRQ9 = 9U, /* SWI_IRQ9 */ + EVT_SRC_SWI_IRQ10 = 10U, /* SWI_IRQ10 */ + EVT_SRC_SWI_IRQ11 = 11U, /* SWI_IRQ11 */ + EVT_SRC_SWI_IRQ12 = 12U, /* SWI_IRQ12 */ + EVT_SRC_SWI_IRQ13 = 13U, /* SWI_IRQ13 */ + EVT_SRC_SWI_IRQ14 = 14U, /* SWI_IRQ14 */ + EVT_SRC_SWI_IRQ15 = 15U, /* SWI_IRQ15 */ + EVT_SRC_SWI_IRQ16 = 16U, /* SWI_IRQ16 */ + EVT_SRC_SWI_IRQ17 = 17U, /* SWI_IRQ17 */ + EVT_SRC_SWI_IRQ18 = 18U, /* SWI_IRQ18 */ + EVT_SRC_SWI_IRQ19 = 19U, /* SWI_IRQ19 */ + EVT_SRC_SWI_IRQ20 = 20U, /* SWI_IRQ20 */ + EVT_SRC_SWI_IRQ21 = 21U, /* SWI_IRQ21 */ + EVT_SRC_SWI_IRQ22 = 22U, /* SWI_IRQ22 */ + EVT_SRC_SWI_IRQ23 = 23U, /* SWI_IRQ23 */ + EVT_SRC_SWI_IRQ24 = 24U, /* SWI_IRQ24 */ + EVT_SRC_SWI_IRQ25 = 25U, /* SWI_IRQ25 */ + EVT_SRC_SWI_IRQ26 = 26U, /* SWI_IRQ26 */ + EVT_SRC_SWI_IRQ27 = 27U, /* SWI_IRQ27 */ + EVT_SRC_SWI_IRQ28 = 28U, /* SWI_IRQ28 */ + EVT_SRC_SWI_IRQ29 = 29U, /* SWI_IRQ29 */ + EVT_SRC_SWI_IRQ30 = 30U, /* SWI_IRQ30 */ + EVT_SRC_SWI_IRQ31 = 31U, /* SWI_IRQ31 */ + + /* External Interrupt. */ + EVT_SRC_PORT_EIRQ0 = 0U, /* PORT_EIRQ0 */ + EVT_SRC_PORT_EIRQ1 = 1U, /* PORT_EIRQ1 */ + EVT_SRC_PORT_EIRQ2 = 2U, /* PORT_EIRQ2 */ + EVT_SRC_PORT_EIRQ3 = 3U, /* PORT_EIRQ3 */ + EVT_SRC_PORT_EIRQ4 = 4U, /* PORT_EIRQ4 */ + EVT_SRC_PORT_EIRQ5 = 5U, /* PORT_EIRQ5 */ + EVT_SRC_PORT_EIRQ6 = 6U, /* PORT_EIRQ6 */ + EVT_SRC_PORT_EIRQ7 = 7U, /* PORT_EIRQ7 */ + EVT_SRC_PORT_EIRQ8 = 8U, /* PORT_EIRQ8 */ + EVT_SRC_PORT_EIRQ9 = 9U, /* PORT_EIRQ9 */ + EVT_SRC_PORT_EIRQ10 = 10U, /* PORT_EIRQ10 */ + EVT_SRC_PORT_EIRQ11 = 11U, /* PORT_EIRQ11 */ + EVT_SRC_PORT_EIRQ12 = 12U, /* PORT_EIRQ12 */ + EVT_SRC_PORT_EIRQ13 = 13U, /* PORT_EIRQ13 */ + EVT_SRC_PORT_EIRQ14 = 14U, /* PORT_EIRQ14 */ + EVT_SRC_PORT_EIRQ15 = 15U, /* PORT_EIRQ15 */ + + /* DMAC */ + EVT_SRC_DMA1_TC0 = 32U, /* DMA1_TC0 */ + EVT_SRC_DMA1_TC1 = 33U, /* DMA1_TC1 */ + EVT_SRC_DMA1_TC2 = 34U, /* DMA1_TC2 */ + EVT_SRC_DMA1_TC3 = 35U, /* DMA1_TC3 */ + EVT_SRC_DMA2_TC0 = 36U, /* DMA2_TC0 */ + EVT_SRC_DMA2_TC1 = 37U, /* DMA2_TC1 */ + EVT_SRC_DMA2_TC2 = 38U, /* DMA2_TC2 */ + EVT_SRC_DMA2_TC3 = 39U, /* DMA2_TC3 */ + EVT_SRC_DMA1_BTC0 = 40U, /* DMA1_BTC0 */ + EVT_SRC_DMA1_BTC1 = 41U, /* DMA1_BTC1 */ + EVT_SRC_DMA1_BTC2 = 42U, /* DMA1_BTC2 */ + EVT_SRC_DMA1_BTC3 = 43U, /* DMA1_BTC3 */ + EVT_SRC_DMA2_BTC0 = 44U, /* DMA2_BTC0 */ + EVT_SRC_DMA2_BTC1 = 45U, /* DMA2_BTC1 */ + EVT_SRC_DMA2_BTC2 = 46U, /* DMA2_BTC2 */ + EVT_SRC_DMA2_BTC3 = 47U, /* DMA2_BTC3 */ + + /* EFM */ + EVT_SRC_EFM_OPTEND = 52U, /* EFM_OPTEND */ + + /* USB SOF */ + EVT_SRC_USBFS_SOF = 53U, /* USBFS_SOF */ + + /* DCU */ + EVT_SRC_DCU1 = 55U, /* DCU1 */ + EVT_SRC_DCU2 = 56U, /* DCU2 */ + EVT_SRC_DCU3 = 57U, /* DCU3 */ + EVT_SRC_DCU4 = 58U, /* DCU4 */ + + /* TIMER 0 */ + EVT_SRC_TMR0_1_CMP_A = 64U, /* TMR01_GCMA */ + EVT_SRC_TMR0_1_CMP_B = 65U, /* TMR01_GCMB */ + EVT_SRC_TMR0_2_CMP_A = 66U, /* TMR02_GCMA */ + EVT_SRC_TMR0_2_CMP_B = 67U, /* TMR02_GCMB */ + + /* RTC */ + EVT_SRC_RTC_ALM = 81U, /* RTC_ALM */ + EVT_SRC_RTC_PRD = 82U, /* RTC_PRD */ + + /* TIMER 6 */ + EVT_SRC_TMR6_1_GCMP_A = 96U, /* TMR61_GCMA */ + EVT_SRC_TMR6_1_GCMP_B = 97U, /* TMR61_GCMB */ + EVT_SRC_TMR6_1_GCMP_C = 98U, /* TMR61_GCMC */ + EVT_SRC_TMR6_1_GCMP_D = 99U, /* TMR61_GCMD */ + EVT_SRC_TMR6_1_GCMP_E = 100U, /* TMR61_GCME */ + EVT_SRC_TMR6_1_GCMP_F = 101U, /* TMR61_GCMF */ + EVT_SRC_TMR6_1_OVF = 102U, /* TMR61_GOVF */ + EVT_SRC_TMR6_1_UDF = 103U, /* TMR61_GUDF */ + EVT_SRC_TMR6_1_SCMP_A = 107U, /* TMR61_SCMA */ + EVT_SRC_TMR6_1_SCMP_B = 108U, /* TMR61_SCMB */ + EVT_SRC_TMR6_2_GCMP_A = 112U, /* TMR62_GCMA */ + EVT_SRC_TMR6_2_GCMP_B = 113U, /* TMR62_GCMB */ + EVT_SRC_TMR6_2_GCMP_C = 114U, /* TMR62_GCMC */ + EVT_SRC_TMR6_2_GCMP_D = 115U, /* TMR62_GCMD */ + EVT_SRC_TMR6_2_GCMP_E = 116U, /* TMR62_GCME */ + EVT_SRC_TMR6_2_GCMP_F = 117U, /* TMR62_GCMF */ + EVT_SRC_TMR6_2_OVF = 118U, /* TMR62_GOVF */ + EVT_SRC_TMR6_2_UDF = 119U, /* TMR62_GUDF */ + EVT_SRC_TMR6_2_SCMP_A = 123U, /* TMR62_SCMA */ + EVT_SRC_TMR6_2_SCMP_B = 124U, /* TMR62_SCMB */ + EVT_SRC_TMR6_3_GCMP_A = 128U, /* TMR63_GCMA */ + EVT_SRC_TMR6_3_GCMP_B = 129U, /* TMR63_GCMB */ + EVT_SRC_TMR6_3_GCMP_C = 130U, /* TMR63_GCMC */ + EVT_SRC_TMR6_3_GCMP_D = 131U, /* TMR63_GCMD */ + EVT_SRC_TMR6_3_GCMP_E = 132U, /* TMR63_GCME */ + EVT_SRC_TMR6_3_GCMP_F = 133U, /* TMR63_GCMF */ + EVT_SRC_TMR6_3_OVF = 134U, /* TMR63_GOVF */ + EVT_SRC_TMR6_3_UDF = 135U, /* TMR63_GUDF */ + EVT_SRC_TMR6_3_SCMP_A = 139U, /* TMR63_SCMA */ + EVT_SRC_TMR6_3_SCMP_B = 140U, /* TMR63_SCMB */ + + /* TIMER A */ + EVT_SRC_TMRA_1_OVF = 256U, /* TMRA1_OVF */ + EVT_SRC_TMRA_1_UDF = 257U, /* TMRA1_UDF */ + EVT_SRC_TMRA_1_CMP = 258U, /* TMRA1_CMP */ + EVT_SRC_TMRA_2_OVF = 259U, /* TMRA2_OVF */ + EVT_SRC_TMRA_2_UDF = 260U, /* TMRA2_UDF */ + EVT_SRC_TMRA_2_CMP = 261U, /* TMRA2_CMP */ + EVT_SRC_TMRA_3_OVF = 262U, /* TMRA3_OVF */ + EVT_SRC_TMRA_3_UDF = 263U, /* TMRA3_UDF */ + EVT_SRC_TMRA_3_CMP = 264U, /* TMRA3_CMP */ + EVT_SRC_TMRA_4_OVF = 265U, /* TMRA4_OVF */ + EVT_SRC_TMRA_4_UDF = 266U, /* TMRA4_UDF */ + EVT_SRC_TMRA_4_CMP = 267U, /* TMRA4_CMP */ + EVT_SRC_TMRA_5_OVF = 268U, /* TMRA5_OVF */ + EVT_SRC_TMRA_5_UDF = 269U, /* TMRA5_UDF */ + EVT_SRC_TMRA_5_CMP = 270U, /* TMRA5_CMP */ + EVT_SRC_TMRA_6_OVF = 272U, /* TMRA6_OVF */ + EVT_SRC_TMRA_6_UDF = 273U, /* TMRA6_UDF */ + EVT_SRC_TMRA_6_CMP = 274U, /* TMRA6_CMP */ + + /* USART */ + EVT_SRC_USART1_EI = 278U, /* USART1_EI */ + EVT_SRC_USART1_RI = 279U, /* USART1_RI */ + EVT_SRC_USART1_TI = 280U, /* USART1_TI */ + EVT_SRC_USART1_TCI = 281U, /* USART1_TCI */ + EVT_SRC_USART1_RTO = 282U, /* USART1_RTO */ + EVT_SRC_USART2_EI = 283U, /* USART2_EI */ + EVT_SRC_USART2_RI = 284U, /* USART2_RI */ + EVT_SRC_USART2_TI = 285U, /* USART2_TI */ + EVT_SRC_USART2_TCI = 286U, /* USART2_TCI */ + EVT_SRC_USART2_RTO = 287U, /* USART2_RTO */ + EVT_SRC_USART3_EI = 288U, /* USART3_EI */ + EVT_SRC_USART3_RI = 289U, /* USART3_RI */ + EVT_SRC_USART3_TI = 290U, /* USART3_TI */ + EVT_SRC_USART3_TCI = 291U, /* USART3_TCI */ + EVT_SRC_USART3_RTO = 292U, /* USART3_RTO */ + EVT_SRC_USART4_EI = 293U, /* USART4_EI */ + EVT_SRC_USART4_RI = 294U, /* USART4_RI */ + EVT_SRC_USART4_TI = 295U, /* USART4_TI */ + EVT_SRC_USART4_TCI = 296U, /* USART4_TCI */ + EVT_SRC_USART4_RTO = 297U, /* USART4_RTO */ + + /* SPI */ + EVT_SRC_SPI1_SPRI = 299U, /* SPI1_SPRI */ + EVT_SRC_SPI1_SPTI = 300U, /* SPI1_SPTI */ + EVT_SRC_SPI1_SPII = 301U, /* SPI1_SPII */ + EVT_SRC_SPI1_SPEI = 302U, /* SPI1_SPEI */ + EVT_SRC_SPI1_SPTEND = 303U, /* SPI1_SPTEND */ + EVT_SRC_SPI2_SPRI = 304U, /* SPI2_SPRI */ + EVT_SRC_SPI2_SPTI = 305U, /* SPI2_SPTI */ + EVT_SRC_SPI2_SPII = 306U, /* SPI2_SPII */ + EVT_SRC_SPI2_SPEI = 307U, /* SPI2_SPEI */ + EVT_SRC_SPI2_SPTEND = 308U, /* SPI2_SPTEND */ + EVT_SRC_SPI3_SPRI = 309U, /* SPI3_SPRI */ + EVT_SRC_SPI3_SPTI = 310U, /* SPI3_SPTI */ + EVT_SRC_SPI3_SPII = 311U, /* SPI3_SPII */ + EVT_SRC_SPI3_SPEI = 312U, /* SPI3_SPEI */ + EVT_SRC_SPI3_SPTEND = 313U, /* SPI3_SPTEND */ + EVT_SRC_SPI4_SPRI = 314U, /* SPI4_SPRI */ + EVT_SRC_SPI4_SPTI = 315U, /* SPI4_SPTI */ + EVT_SRC_SPI4_SPII = 316U, /* SPI4_SPII */ + EVT_SRC_SPI4_SPEI = 317U, /* SPI4_SPEI */ + EVT_SRC_SPI4_SPTEND = 318U, /* SPI4_SPTEND */ + + /* AOS */ + EVT_SRC_AOS_STRG = 319U, /* AOS_STRG */ + + /* TIMER 4 */ + EVT_SRC_TMR4_1_SCMP0 = 368U, /* TMR41_SCM0 */ + EVT_SRC_TMR4_1_SCMP1 = 369U, /* TMR41_SCM1 */ + EVT_SRC_TMR4_1_SCMP2 = 370U, /* TMR41_SCM2 */ + EVT_SRC_TMR4_1_SCMP3 = 371U, /* TMR41_SCM3 */ + EVT_SRC_TMR4_1_SCMP4 = 372U, /* TMR41_SCM4 */ + EVT_SRC_TMR4_1_SCMP5 = 373U, /* TMR41_SCM5 */ + EVT_SRC_TMR4_2_SCMP0 = 374U, /* TMR42_SCM0 */ + EVT_SRC_TMR4_2_SCMP1 = 375U, /* TMR42_SCM1 */ + EVT_SRC_TMR4_2_SCMP2 = 376U, /* TMR42_SCM2 */ + EVT_SRC_TMR4_2_SCMP3 = 377U, /* TMR42_SCM3 */ + EVT_SRC_TMR4_2_SCMP4 = 378U, /* TMR42_SCM4 */ + EVT_SRC_TMR4_2_SCMP5 = 379U, /* TMR42_SCM5 */ + EVT_SRC_TMR4_3_SCMP0 = 384U, /* TMR43_SCM0 */ + EVT_SRC_TMR4_3_SCMP1 = 385U, /* TMR43_SCM1 */ + EVT_SRC_TMR4_3_SCMP2 = 386U, /* TMR43_SCM2 */ + EVT_SRC_TMR4_3_SCMP3 = 387U, /* TMR43_SCM3 */ + EVT_SRC_TMR4_3_SCMP4 = 388U, /* TMR43_SCM4 */ + EVT_SRC_TMR4_3_SCMP5 = 389U, /* TMR43_SCM5 */ + + /* EVENT PORT */ + EVT_SRC_EVENT_PORT1 = 394U, /* EVENT_PORT1 */ + EVT_SRC_EVENT_PORT2 = 395U, /* EVENT_PORT2 */ + EVT_SRC_EVENT_PORT3 = 396U, /* EVENT_PORT3 */ + EVT_SRC_EVENT_PORT4 = 397U, /* EVENT_PORT4 */ + + /* I2S */ + EVT_SRC_I2S1_TXIRQOUT = 400U, /* I2S1_TXIRQOUT */ + EVT_SRC_I2S1_RXIRQOUT = 401U, /* I2S1_RXIRQOUT */ + EVT_SRC_I2S2_TXIRQOUT = 403U, /* I2S2_TXIRQOUT */ + EVT_SRC_I2S2_RXIRQOUT = 404U, /* I2S2_RXIRQOUT */ + EVT_SRC_I2S3_TXIRQOUT = 406U, /* I2S3_TXIRQOUT */ + EVT_SRC_I2S3_RXIRQOUT = 407U, /* I2S3_RXIRQOUT */ + EVT_SRC_I2S4_TXIRQOUT = 409U, /* I2S4_TXIRQOUT */ + EVT_SRC_I2S4_RXIRQOUT = 410U, /* I2S4_RXIRQOUT */ + + /* COMPARATOR */ + EVT_SRC_CMP1 = 416U, /* ACMP1 */ + EVT_SRC_CMP2 = 417U, /* ACMP1 */ + EVT_SRC_CMP3 = 418U, /* ACMP1 */ + + /* I2C */ + EVT_SRC_I2C1_RXI = 420U, /* I2C1_RXI */ + EVT_SRC_I2C1_TXI = 421U, /* I2C1_TXI */ + EVT_SRC_I2C1_TEI = 422U, /* I2C1_TEI */ + EVT_SRC_I2C1_EEI = 423U, /* I2C1_EEI */ + EVT_SRC_I2C2_RXI = 424U, /* I2C2_RXI */ + EVT_SRC_I2C2_TXI = 425U, /* I2C2_TXI */ + EVT_SRC_I2C2_TEI = 426U, /* I2C2_TEI */ + EVT_SRC_I2C2_EEI = 427U, /* I2C2_EEI */ + EVT_SRC_I2C3_RXI = 428U, /* I2C3_RXI */ + EVT_SRC_I2C3_TXI = 429U, /* I2C3_TXI */ + EVT_SRC_I2C3_TEI = 430U, /* I2C3_TEI */ + EVT_SRC_I2C3_EEI = 431U, /* I2C3_EEI */ + + /* LVD */ + EVT_SRC_LVD1 = 433U, /* LVD1 */ + EVT_SRC_LVD2 = 434U, /* LVD2 */ + + /* OTS */ + EVT_SRC_OTS = 435U, /* OTS */ + + /* WDT */ + EVT_SRC_WDT_REFUDF = 439U, /* WDT_REFUDF */ + + /* ADC */ + EVT_SRC_ADC1_EOCA = 448U, /* ADC1_EOCA */ + EVT_SRC_ADC1_EOCB = 449U, /* ADC1_EOCB */ + EVT_SRC_ADC1_CHCMP = 450U, /* ADC1_CHCMP */ + EVT_SRC_ADC1_SEQCMP = 451U, /* ADC1_SEQCMP */ + EVT_SRC_ADC2_EOCA = 452U, /* ADC2_EOCA */ + EVT_SRC_ADC2_EOCB = 453U, /* ADC2_EOCB */ + EVT_SRC_ADC2_CHCMP = 454U, /* ADC2_CHCMP */ + EVT_SRC_ADC2_SEQCMP = 455U, /* ADC2_SEQCMP */ + + /* TRNG */ + EVT_SRC_TRNG_END = 456U, /* TRNG_END */ + + /* SDIO */ + EVT_SRC_SDIOC1_DMAR = 480U, /* SDIOC1_DMAR */ + EVT_SRC_SDIOC1_DMAW = 481U, /* SDIOC1_DMAW */ + EVT_SRC_SDIOC2_DMAR = 483U, /* SDIOC2_DMAR */ + EVT_SRC_SDIOC2_DMAW = 484U, /* SDIOC2_DMAW */ + EVT_SRC_MAX = 511U, +} en_event_src_t; + +/** + ******************************************************************************* + ** \brief Interrupt number enumeration + ******************************************************************************/ +typedef enum { + INT_SRC_SWI_IRQ0 = 0U, /* SWI_IRQ0 */ + INT_SRC_SWI_IRQ1 = 1U, /* SWI_IRQ1 */ + INT_SRC_SWI_IRQ2 = 2U, /* SWI_IRQ2 */ + INT_SRC_SWI_IRQ3 = 3U, /* SWI_IRQ3 */ + INT_SRC_SWI_IRQ4 = 4U, /* SWI_IRQ4 */ + INT_SRC_SWI_IRQ5 = 5U, /* SWI_IRQ5 */ + INT_SRC_SWI_IRQ6 = 6U, /* SWI_IRQ6 */ + INT_SRC_SWI_IRQ7 = 7U, /* SWI_IRQ7 */ + INT_SRC_SWI_IRQ8 = 8U, /* SWI_IRQ8 */ + INT_SRC_SWI_IRQ9 = 9U, /* SWI_IRQ9 */ + INT_SRC_SWI_IRQ10 = 10U, /* SWI_IRQ10 */ + INT_SRC_SWI_IRQ11 = 11U, /* SWI_IRQ11 */ + INT_SRC_SWI_IRQ12 = 12U, /* SWI_IRQ12 */ + INT_SRC_SWI_IRQ13 = 13U, /* SWI_IRQ13 */ + INT_SRC_SWI_IRQ14 = 14U, /* SWI_IRQ14 */ + INT_SRC_SWI_IRQ15 = 15U, /* SWI_IRQ15 */ + INT_SRC_SWI_IRQ16 = 16U, /* SWI_IRQ16 */ + INT_SRC_SWI_IRQ17 = 17U, /* SWI_IRQ17 */ + INT_SRC_SWI_IRQ18 = 18U, /* SWI_IRQ18 */ + INT_SRC_SWI_IRQ19 = 19U, /* SWI_IRQ19 */ + INT_SRC_SWI_IRQ20 = 20U, /* SWI_IRQ20 */ + INT_SRC_SWI_IRQ21 = 21U, /* SWI_IRQ21 */ + INT_SRC_SWI_IRQ22 = 22U, /* SWI_IRQ22 */ + INT_SRC_SWI_IRQ23 = 23U, /* SWI_IRQ23 */ + INT_SRC_SWI_IRQ24 = 24U, /* SWI_IRQ24 */ + INT_SRC_SWI_IRQ25 = 25U, /* SWI_IRQ25 */ + INT_SRC_SWI_IRQ26 = 26U, /* SWI_IRQ26 */ + INT_SRC_SWI_IRQ27 = 27U, /* SWI_IRQ27 */ + INT_SRC_SWI_IRQ28 = 28U, /* SWI_IRQ28 */ + INT_SRC_SWI_IRQ29 = 29U, /* SWI_IRQ29 */ + INT_SRC_SWI_IRQ30 = 30U, /* SWI_IRQ30 */ + INT_SRC_SWI_IRQ31 = 31U, /* SWI_IRQ31 */ + + /* External Interrupt. */ + INT_SRC_PORT_EIRQ0 = 0U, /* PORT_EIRQ0 */ + INT_SRC_PORT_EIRQ1 = 1U, /* PORT_EIRQ1 */ + INT_SRC_PORT_EIRQ2 = 2U, /* PORT_EIRQ2 */ + INT_SRC_PORT_EIRQ3 = 3U, /* PORT_EIRQ3 */ + INT_SRC_PORT_EIRQ4 = 4U, /* PORT_EIRQ4 */ + INT_SRC_PORT_EIRQ5 = 5U, /* PORT_EIRQ5 */ + INT_SRC_PORT_EIRQ6 = 6U, /* PORT_EIRQ6 */ + INT_SRC_PORT_EIRQ7 = 7U, /* PORT_EIRQ7 */ + INT_SRC_PORT_EIRQ8 = 8U, /* PORT_EIRQ8 */ + INT_SRC_PORT_EIRQ9 = 9U, /* PORT_EIRQ9 */ + INT_SRC_PORT_EIRQ10 = 10U, /* PORT_EIRQ10 */ + INT_SRC_PORT_EIRQ11 = 11U, /* PORT_EIRQ11 */ + INT_SRC_PORT_EIRQ12 = 12U, /* PORT_EIRQ12 */ + INT_SRC_PORT_EIRQ13 = 13U, /* PORT_EIRQ13 */ + INT_SRC_PORT_EIRQ14 = 14U, /* PORT_EIRQ14 */ + INT_SRC_PORT_EIRQ15 = 15U, /* PORT_EIRQ15 */ + + /* DMAC */ + INT_SRC_DMA1_TC0 = 32U, /* DMA1_TC0 */ + INT_SRC_DMA1_TC1 = 33U, /* DMA1_TC1 */ + INT_SRC_DMA1_TC2 = 34U, /* DMA1_TC2 */ + INT_SRC_DMA1_TC3 = 35U, /* DMA1_TC3 */ + INT_SRC_DMA2_TC0 = 36U, /* DMA2_TC0 */ + INT_SRC_DMA2_TC1 = 37U, /* DMA2_TC1 */ + INT_SRC_DMA2_TC2 = 38U, /* DMA2_TC2 */ + INT_SRC_DMA2_TC3 = 39U, /* DMA2_TC3 */ + INT_SRC_DMA1_BTC0 = 40U, /* DMA1_BTC0 */ + INT_SRC_DMA1_BTC1 = 41U, /* DMA1_BTC1 */ + INT_SRC_DMA1_BTC2 = 42U, /* DMA1_BTC2 */ + INT_SRC_DMA1_BTC3 = 43U, /* DMA1_BTC3 */ + INT_SRC_DMA2_BTC0 = 44U, /* DMA2_BTC0 */ + INT_SRC_DMA2_BTC1 = 45U, /* DMA2_BTC1 */ + INT_SRC_DMA2_BTC2 = 46U, /* DMA2_BTC2 */ + INT_SRC_DMA2_BTC3 = 47U, /* DMA2_BTC3 */ + INT_SRC_DMA1_ERR = 48U, /* DMA1_ERR */ + INT_SRC_DMA2_ERR = 49U, /* DMA2_ERR */ + + /* EFM */ + INT_SRC_EFM_PEERR = 50U, /* EFM_PEERR */ + INT_SRC_EFM_COLERR = 51U, /* EFM_COLERR */ + INT_SRC_EFM_OPTEND = 52U, /* EFM_OPTEND */ + + /* QSPI */ + INT_SRC_QSPI_INTR = 54U, /* QSPI_INTR */ + + /* DCU */ + INT_SRC_DCU1 = 55U, /* DCU1 */ + INT_SRC_DCU2 = 56U, /* DCU2 */ + INT_SRC_DCU3 = 57U, /* DCU3 */ + INT_SRC_DCU4 = 58U, /* DCU4 */ + + /* TIMER 0 */ + INT_SRC_TMR0_1_CMP_A = 64U, /* TMR01_GCMA */ + INT_SRC_TMR0_1_CMP_B = 65U, /* TMR01_GCMB */ + INT_SRC_TMR0_2_CMP_A = 66U, /* TMR02_GCMA */ + INT_SRC_TMR0_2_CMP_B = 67U, /* TMR02_GCMB */ + + /* RTC */ + INT_SRC_RTC_ALM = 81U, /* RTC_ALM */ + INT_SRC_RTC_PRD = 82U, /* RTC_PRD */ + + /* XTAL32 stop */ + INT_SRC_XTAL32_STOP = 84U, /* XTAL32_STOP */ + + /* XTAL stop */ + INT_SRC_XTAL_STOP = 85U, /* XTAL_STOP */ + + /* wake-up timer */ + INT_SRC_WKTM_PRD = 86U, /* WKTM_PRD */ + + /* SWDT */ + INT_SRC_SWDT_REFUDF = 87U, /* SWDT_REFUDF */ + + /* TIMER 6 */ + INT_SRC_TMR6_1_GCMP_A = 96U, /* TMR61_GCMA */ + INT_SRC_TMR6_1_GCMP_B = 97U, /* TMR61_GCMB */ + INT_SRC_TMR6_1_GCMP_C = 98U, /* TMR61_GCMC */ + INT_SRC_TMR6_1_GCMP_D = 99U, /* TMR61_GCMD */ + INT_SRC_TMR6_1_GCMP_E = 100U, /* TMR61_GCME */ + INT_SRC_TMR6_1_GCMP_F = 101U, /* TMR61_GCMF */ + INT_SRC_TMR6_1_OVF = 102U, /* TMR61_GOVF */ + INT_SRC_TMR6_1_UDF = 103U, /* TMR61_GUDF */ + INT_SRC_TMR6_1_DTE = 104U, /* TMR61_GDTE */ + INT_SRC_TMR6_1_SCMP_A = 107U, /* TMR61_SCMA */ + INT_SRC_TMR6_1_SCMP_B = 108U, /* TMR61_SCMB */ + INT_SRC_TMR6_2_GCMP_A = 112U, /* TMR62_GCMA */ + INT_SRC_TMR6_2_GCMP_B = 113U, /* TMR62_GCMB */ + INT_SRC_TMR6_2_GCMP_C = 114U, /* TMR62_GCMC */ + INT_SRC_TMR6_2_GCMP_D = 115U, /* TMR62_GCMD */ + INT_SRC_TMR6_2_GCMP_E = 116U, /* TMR62_GCME */ + INT_SRC_TMR6_2_GCMP_F = 117U, /* TMR62_GCMF */ + INT_SRC_TMR6_2_OVF = 118U, /* TMR62_GOVF */ + INT_SRC_TMR6_2_UDF = 119U, /* TMR62_GUDF */ + INT_SRC_TMR6_2_DTE = 120U, /* TMR62_GDTE */ + INT_SRC_TMR6_2_SCMP_A = 123U, /* TMR62_SCMA */ + INT_SRC_TMR6_2_SCMP_B = 124U, /* TMR62_SCMB */ + INT_SRC_TMR6_3_GCMP_A = 128U, /* TMR63_GCMA */ + INT_SRC_TMR6_3_GCMP_B = 129U, /* TMR63_GCMB */ + INT_SRC_TMR6_3_GCMP_C = 130U, /* TMR63_GCMC */ + INT_SRC_TMR6_3_GCMP_D = 131U, /* TMR63_GCMD */ + INT_SRC_TMR6_3_GCMP_E = 132U, /* TMR63_GCME */ + INT_SRC_TMR6_3_GCMP_F = 133U, /* TMR63_GCMF */ + INT_SRC_TMR6_3_OVF = 134U, /* TMR63_GOVF */ + INT_SRC_TMR6_3_UDF = 135U, /* TMR63_GUDF */ + INT_SRC_TMR6_3_DTE = 136U, /* TMR63_GDTE */ + INT_SRC_TMR6_3_SCMP_A = 139U, /* TMR63_SCMA */ + INT_SRC_TMR6_3_SCMP_B = 140U, /* TMR63_SCMB */ + + /* TIMER A */ + INT_SRC_TMRA_1_OVF = 256U, /* TMRA1_OVF */ + INT_SRC_TMRA_1_UDF = 257U, /* TMRA1_UDF */ + INT_SRC_TMRA_1_CMP = 258U, /* TMRA1_CMP */ + INT_SRC_TMRA_2_OVF = 259U, /* TMRA2_OVF */ + INT_SRC_TMRA_2_UDF = 260U, /* TMRA2_UDF */ + INT_SRC_TMRA_2_CMP = 261U, /* TMRA2_CMP */ + INT_SRC_TMRA_3_OVF = 262U, /* TMRA3_OVF */ + INT_SRC_TMRA_3_UDF = 263U, /* TMRA3_UDF */ + INT_SRC_TMRA_3_CMP = 264U, /* TMRA3_CMP */ + INT_SRC_TMRA_4_OVF = 265U, /* TMRA4_OVF */ + INT_SRC_TMRA_4_UDF = 266U, /* TMRA4_UDF */ + INT_SRC_TMRA_4_CMP = 267U, /* TMRA4_CMP */ + INT_SRC_TMRA_5_OVF = 268U, /* TMRA5_OVF */ + INT_SRC_TMRA_5_UDF = 269U, /* TMRA5_UDF */ + INT_SRC_TMRA_5_CMP = 270U, /* TMRA5_CMP */ + INT_SRC_TMRA_6_OVF = 272U, /* TMRA6_OVF */ + INT_SRC_TMRA_6_UDF = 273U, /* TMRA6_UDF */ + INT_SRC_TMRA_6_CMP = 274U, /* TMRA6_CMP */ + + /* USB FS */ + INT_SRC_USBFS_GLB = 275U, /* USBFS_GLB */ + + /* USRAT */ + INT_SRC_USART1_EI = 278U, /* USART1_EI */ + INT_SRC_USART1_RI = 279U, /* USART1_RI */ + INT_SRC_USART1_TI = 280U, /* USART1_TI */ + INT_SRC_USART1_TCI = 281U, /* USART1_TCI */ + INT_SRC_USART1_RTO = 282U, /* USART1_RTO */ + INT_SRC_USART1_WUPI = 432U, /* USART1_WUPI */ + INT_SRC_USART2_EI = 283U, /* USART2_EI */ + INT_SRC_USART2_RI = 284U, /* USART2_RI */ + INT_SRC_USART2_TI = 285U, /* USART2_TI */ + INT_SRC_USART2_TCI = 286U, /* USART2_TCI */ + INT_SRC_USART2_RTO = 287U, /* USART2_RTO */ + INT_SRC_USART3_EI = 288U, /* USART3_EI */ + INT_SRC_USART3_RI = 289U, /* USART3_RI */ + INT_SRC_USART3_TI = 290U, /* USART3_TI */ + INT_SRC_USART3_TCI = 291U, /* USART3_TCI */ + INT_SRC_USART3_RTO = 292U, /* USART3_RTO */ + INT_SRC_USART4_EI = 293U, /* USART4_EI */ + INT_SRC_USART4_RI = 294U, /* USART4_RI */ + INT_SRC_USART4_TI = 295U, /* USART4_TI */ + INT_SRC_USART4_TCI = 296U, /* USART4_TCI */ + INT_SRC_USART4_RTO = 297U, /* USART4_RTO */ + + /* SPI */ + INT_SRC_SPI1_SPRI = 299U, /* SPI1_SPRI */ + INT_SRC_SPI1_SPTI = 300U, /* SPI1_SPTI */ + INT_SRC_SPI1_SPII = 301U, /* SPI1_SPII */ + INT_SRC_SPI1_SPEI = 302U, /* SPI1_SPEI */ + INT_SRC_SPI2_SPRI = 304U, /* SPI2_SPRI */ + INT_SRC_SPI2_SPTI = 305U, /* SPI2_SPTI */ + INT_SRC_SPI2_SPII = 306U, /* SPI2_SPII */ + INT_SRC_SPI2_SPEI = 307U, /* SPI2_SPEI */ + INT_SRC_SPI3_SPRI = 309U, /* SPI3_SPRI */ + INT_SRC_SPI3_SPTI = 310U, /* SPI3_SPTI */ + INT_SRC_SPI3_SPII = 311U, /* SPI3_SPII */ + INT_SRC_SPI3_SPEI = 312U, /* SPI3_SPEI */ + INT_SRC_SPI4_SPRI = 314U, /* SPI4_SPRI */ + INT_SRC_SPI4_SPTI = 315U, /* SPI4_SPTI */ + INT_SRC_SPI4_SPII = 316U, /* SPI4_SPII */ + INT_SRC_SPI4_SPEI = 317U, /* SPI4_SPEI */ + + /* TIMER 4 */ + INT_SRC_TMR4_1_GCMP_UH = 320U, /* TMR41_GCMUH */ + INT_SRC_TMR4_1_GCMP_UL = 321U, /* TMR41_GCMUL */ + INT_SRC_TMR4_1_GCMP_VH = 322U, /* TMR41_GCMVH */ + INT_SRC_TMR4_1_GCMP_VL = 323U, /* TMR41_GCMVL */ + INT_SRC_TMR4_1_GCMP_WH = 324U, /* TMR41_GCMWH */ + INT_SRC_TMR4_1_GCMP_WL = 325U, /* TMR41_GCMWL */ + INT_SRC_TMR4_1_OVF = 326U, /* TMR41_GOVF */ + INT_SRC_TMR4_1_UDF = 327U, /* TMR41_GUDF */ + INT_SRC_TMR4_1_RELOAD_U = 328U, /* TMR41_RLOU */ + INT_SRC_TMR4_1_RELOAD_V = 329U, /* TMR41_RLOV */ + INT_SRC_TMR4_1_RELOAD_W = 330U, /* TMR41_RLOW */ + INT_SRC_TMR4_2_GCMP_UH = 336U, /* TMR42_GCMUH */ + INT_SRC_TMR4_2_GCMP_UL = 337U, /* TMR42_GCMUL */ + INT_SRC_TMR4_2_GCMP_VH = 338U, /* TMR42_GCMVH */ + INT_SRC_TMR4_2_GCMP_VL = 339U, /* TMR42_GCMVL */ + INT_SRC_TMR4_2_GCMP_WH = 340U, /* TMR42_GCMWH */ + INT_SRC_TMR4_2_GCMP_WL = 341U, /* TMR42_GCMWL */ + INT_SRC_TMR4_2_OVF = 342U, /* TMR42_GOVF */ + INT_SRC_TMR4_2_UDF = 343U, /* TMR42_GUDF */ + INT_SRC_TMR4_2_RELOAD_U = 344U, /* TMR42_RLOU */ + INT_SRC_TMR4_2_RELOAD_V = 345U, /* TMR42_RLOV */ + INT_SRC_TMR4_2_RELOAD_W = 346U, /* TMR42_RLOW */ + INT_SRC_TMR4_3_GCMP_UH = 352U, /* TMR43_GCMUH */ + INT_SRC_TMR4_3_GCMP_UL = 353U, /* TMR43_GCMUL */ + INT_SRC_TMR4_3_GCMP_VH = 354U, /* TMR43_GCMVH */ + INT_SRC_TMR4_3_GCMP_VL = 355U, /* TMR43_GCMVL */ + INT_SRC_TMR4_3_GCMP_WH = 356U, /* TMR43_GCMWH */ + INT_SRC_TMR4_3_GCMP_WL = 357U, /* TMR43_GCMWL */ + INT_SRC_TMR4_3_OVF = 358U, /* TMR43_GOVF */ + INT_SRC_TMR4_3_UDF = 359U, /* TMR43_GUDF */ + INT_SRC_TMR4_3_RELOAD_U = 360U, /* TMR43_RLOU */ + INT_SRC_TMR4_3_RELOAD_V = 361U, /* TMR43_RLOV */ + INT_SRC_TMR4_3_RELOAD_W = 362U, /* TMR43_RLOW */ + + /* EMB */ + INT_SRC_EMB_GR0 = 390U, /* EMB_GR0 */ + INT_SRC_EMB_GR1 = 391U, /* EMB_GR1 */ + INT_SRC_EMB_GR2 = 392U, /* EMB_GR2 */ + INT_SRC_EMB_GR3 = 393U, /* EMB_GR3 */ + + /* EVENT PORT */ + INT_SRC_EVENT_PORT1 = 394U, /* EVENT_PORT1 */ + INT_SRC_EVENT_PORT2 = 395U, /* EVENT_PORT2 */ + INT_SRC_EVENT_PORT3 = 396U, /* EVENT_PORT3 */ + INT_SRC_EVENT_PORT4 = 397U, /* EVENT_PORT4 */ + + /* I2S */ + INT_SRC_I2S1_TXIRQOUT = 400U, /* I2S1_TXIRQOUT */ + INT_SRC_I2S1_RXIRQOUT = 401U, /* I2S1_RXIRQOUT */ + INT_SRC_I2S1_ERRIRQOUT = 402U, /* I2S1_ERRIRQOUT */ + INT_SRC_I2S2_TXIRQOUT = 403U, /* I2S2_TXIRQOUT */ + INT_SRC_I2S2_RXIRQOUT = 404U, /* I2S2_RXIRQOUT */ + INT_SRC_I2S2_ERRIRQOUT = 405U, /* I2S2_ERRIRQOUT */ + INT_SRC_I2S3_TXIRQOUT = 406U, /* I2S3_TXIRQOUT */ + INT_SRC_I2S3_RXIRQOUT = 407U, /* I2S3_RXIRQOUT */ + INT_SRC_I2S3_ERRIRQOUT = 408U, /* I2S3_ERRIRQOUT */ + INT_SRC_I2S4_TXIRQOUT = 409U, /* I2S4_TXIRQOUT */ + INT_SRC_I2S4_RXIRQOUT = 410U, /* I2S4_RXIRQOUT */ + INT_SRC_I2S4_ERRIRQOUT = 411U, /* I2S4_ERRIRQOUT */ + + /* COMPARATOR */ + INT_SRC_CMP1 = 416U, /* ACMP1 */ + INT_SRC_CMP2 = 417U, /* ACMP2 */ + INT_SRC_CMP3 = 418U, /* ACMP3 */ + + /* I2C */ + INT_SRC_I2C1_RXI = 420U, /* I2C1_RXI */ + INT_SRC_I2C1_TXI = 421U, /* I2C1_TXI */ + INT_SRC_I2C1_TEI = 422U, /* I2C1_TEI */ + INT_SRC_I2C1_EEI = 423U, /* I2C1_EEI */ + INT_SRC_I2C2_RXI = 424U, /* I2C2_RXI */ + INT_SRC_I2C2_TXI = 425U, /* I2C2_TXI */ + INT_SRC_I2C2_TEI = 426U, /* I2C2_TEI */ + INT_SRC_I2C2_EEI = 427U, /* I2C2_EEI */ + INT_SRC_I2C3_RXI = 428U, /* I2C3_RXI */ + INT_SRC_I2C3_TXI = 429U, /* I2C3_TXI */ + INT_SRC_I2C3_TEI = 430U, /* I2C3_TEI */ + INT_SRC_I2C3_EEI = 431U, /* I2C3_EEI */ + + /* LVD */ + INT_SRC_LVD1 = 433U, /* LVD1 */ + INT_SRC_LVD2 = 434U, /* LVD2 */ + + /* Temp. sensor */ + INT_SRC_OTS = 435U, /* OTS */ + + /* FCM */ + INT_SRC_FCMFERRI = 436U, /* FCMFERRI */ + INT_SRC_FCMMENDI = 437U, /* FCMMENDI */ + INT_SRC_FCMCOVFI = 438U, /* FCMCOVFI */ + + /* WDT */ + INT_SRC_WDT_REFUDF = 439U, /* WDT_REFUDF */ + + /* ADC */ + INT_SRC_ADC1_EOCA = 448U, /* ADC1_EOCA */ + INT_SRC_ADC1_EOCB = 449U, /* ADC1_EOCB */ + INT_SRC_ADC1_CHCMP = 450U, /* ADC1_CHCMP */ + INT_SRC_ADC1_SEQCMP = 451U, /* ADC1_SEQCMP */ + INT_SRC_ADC2_EOCA = 452U, /* ADC2_EOCA */ + INT_SRC_ADC2_EOCB = 453U, /* ADC2_EOCB */ + INT_SRC_ADC2_CHCMP = 454U, /* ADC2_CHCMP */ + INT_SRC_ADC2_SEQCMP = 455U, /* ADC2_SEQCMP */ + + /* TRNG */ + INT_SRC_TRNG_END = 456U, /* TRNG_END */ + + /* SDIOC */ + INT_SRC_SDIOC1_SD = 482U, /* SDIOC1_SD */ + INT_SRC_SDIOC2_SD = 485U, /* SDIOC2_SD */ + + /* CAN */ + INT_SRC_CAN_INT = 486U, /* CAN_INT */ + + INT_SRC_MAX = 511U, +} en_int_src_t; + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif +/** + * @brief ADC + */ +typedef struct { + __IO uint8_t STR; + uint8_t RESERVED0[1]; + __IO uint16_t CR0; + __IO uint16_t CR1; + uint8_t RESERVED1[4]; + __IO uint16_t TRGSR; + __IO uint32_t CHSELRA; + __IO uint32_t CHSELRB; + __IO uint32_t AVCHSELR; + uint8_t RESERVED2[8]; + __IO uint8_t SSTR0; + __IO uint8_t SSTR1; + __IO uint8_t SSTR2; + __IO uint8_t SSTR3; + __IO uint8_t SSTR4; + __IO uint8_t SSTR5; + __IO uint8_t SSTR6; + __IO uint8_t SSTR7; + __IO uint8_t SSTR8; + __IO uint8_t SSTR9; + __IO uint8_t SSTR10; + __IO uint8_t SSTR11; + __IO uint8_t SSTR12; + __IO uint8_t SSTR13; + __IO uint8_t SSTR14; + __IO uint8_t SSTR15; + __IO uint8_t SSTRL; + uint8_t RESERVED3[7]; + __IO uint16_t CHMUXR0; + __IO uint16_t CHMUXR1; + __IO uint16_t CHMUXR2; + __IO uint16_t CHMUXR3; + uint8_t RESERVED4[6]; + __IO uint8_t ISR; + __IO uint8_t ICR; + uint8_t RESERVED5[4]; + __IO uint16_t SYNCCR; + uint8_t RESERVED6[2]; + __I uint16_t DR0; + __I uint16_t DR1; + __I uint16_t DR2; + __I uint16_t DR3; + __I uint16_t DR4; + __I uint16_t DR5; + __I uint16_t DR6; + __I uint16_t DR7; + __I uint16_t DR8; + __I uint16_t DR9; + __I uint16_t DR10; + __I uint16_t DR11; + __I uint16_t DR12; + __I uint16_t DR13; + __I uint16_t DR14; + __I uint16_t DR15; + __I uint16_t DR16; + uint8_t RESERVED7[46]; + __IO uint16_t AWDCR; + uint8_t RESERVED8[2]; + __IO uint16_t AWDDR0; + __IO uint16_t AWDDR1; + uint8_t RESERVED9[4]; + __IO uint32_t AWDCHSR; + __IO uint32_t AWDSR; + uint8_t RESERVED10[12]; + __IO uint16_t PGACR; + __IO uint16_t PGAGSR; + uint8_t RESERVED11[8]; + __IO uint16_t PGAINSR0; + __IO uint16_t PGAINSR1; +} CM_ADC_TypeDef; + +/** + * @brief AES + */ +typedef struct { + __IO uint32_t CR; + uint8_t RESERVED0[12]; + __IO uint32_t DR0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t KR0; + __IO uint32_t KR1; + __IO uint32_t KR2; + __IO uint32_t KR3; +} CM_AES_TypeDef; + +/** + * @brief AOS + */ +typedef struct { + __O uint32_t INTSFTTRG; + __IO uint32_t DCU_TRGSEL1; + __IO uint32_t DCU_TRGSEL2; + __IO uint32_t DCU_TRGSEL3; + __IO uint32_t DCU_TRGSEL4; + __IO uint32_t DMA1_TRGSEL0; + __IO uint32_t DMA1_TRGSEL1; + __IO uint32_t DMA1_TRGSEL2; + __IO uint32_t DMA1_TRGSEL3; + __IO uint32_t DMA2_TRGSEL0; + __IO uint32_t DMA2_TRGSEL1; + __IO uint32_t DMA2_TRGSEL2; + __IO uint32_t DMA2_TRGSEL3; + __IO uint32_t DMA_RC_TRGSEL; + __IO uint32_t TMR6_TRGSEL0; + __IO uint32_t TMR6_TRGSEL1; + __IO uint32_t TMR0_TRGSEL; + __IO uint32_t PEVNT_TRGSEL12; + __IO uint32_t PEVNT_TRGSEL34; + __IO uint32_t TMRA_TRGSEL0; + __IO uint32_t TMRA_TRGSEL1; + __IO uint32_t OTS_TRGSEL; + __IO uint32_t ADC1_TRGSEL0; + __IO uint32_t ADC1_TRGSEL1; + __IO uint32_t ADC2_TRGSEL0; + __IO uint32_t ADC2_TRGSEL1; + __IO uint32_t COMTRG1; + __IO uint32_t COMTRG2; + uint8_t RESERVED0[144]; + __IO uint32_t PEVNTDIRR1; + __I uint32_t PEVNTIDR1; + __IO uint32_t PEVNTODR1; + __IO uint32_t PEVNTORR1; + __IO uint32_t PEVNTOSR1; + __IO uint32_t PEVNTRISR1; + __IO uint32_t PEVNTFALR1; + __IO uint32_t PEVNTDIRR2; + __I uint32_t PEVNTIDR2; + __IO uint32_t PEVNTODR2; + __IO uint32_t PEVNTORR2; + __IO uint32_t PEVNTOSR2; + __IO uint32_t PEVNTRISR2; + __IO uint32_t PEVNTFALR2; + __IO uint32_t PEVNTDIRR3; + __I uint32_t PEVNTIDR3; + __IO uint32_t PEVNTODR3; + __IO uint32_t PEVNTORR3; + __IO uint32_t PEVNTOSR3; + __IO uint32_t PEVNTRISR3; + __IO uint32_t PEVNTFALR3; + __IO uint32_t PEVNTDIRR4; + __I uint32_t PEVNTIDR4; + __IO uint32_t PEVNTODR4; + __IO uint32_t PEVNTORR4; + __IO uint32_t PEVNTOSR4; + __IO uint32_t PEVNTRISR4; + __IO uint32_t PEVNTFALR4; + __IO uint32_t PEVNTNFCR; +} CM_AOS_TypeDef; + +/** + * @brief CAN + */ +typedef struct { + __I uint32_t RBUF; + uint8_t RESERVED0[76]; + __IO uint32_t TBUF; + uint8_t RESERVED1[76]; + __IO uint8_t CFG_STAT; + __IO uint8_t TCMD; + __IO uint8_t TCTRL; + __IO uint8_t RCTRL; + __IO uint8_t RTIE; + __IO uint8_t RTIF; + __IO uint8_t ERRINT; + __IO uint8_t LIMIT; + __IO uint32_t SBT; + uint8_t RESERVED2[4]; + __I uint8_t EALCAP; + uint8_t RESERVED3[1]; + __IO uint8_t RECNT; + __IO uint8_t TECNT; + __IO uint8_t ACFCTRL; + uint8_t RESERVED4[1]; + __IO uint8_t ACFEN; + uint8_t RESERVED5[1]; + __IO uint32_t ACF; + uint8_t RESERVED6[2]; + __IO uint8_t TBSLOT; + __IO uint8_t TTCFG; + __IO uint32_t REF_MSG; + __IO uint16_t TRG_CFG; + __IO uint16_t TT_TRIG; + __IO uint16_t TT_WTRIG; +} CM_CAN_TypeDef; + +/** + * @brief CMP + */ +typedef struct { + __IO uint16_t CTRL; + __IO uint16_t VLTSEL; + __I uint16_t OUTMON; + __IO uint16_t CVSSTB; + __IO uint16_t CVSPRD; +} CM_CMP_TypeDef; + +/** + * @brief CMP_COMMON + */ +typedef struct { + uint8_t RESERVED0[256]; + __IO uint16_t DADR1; + __IO uint16_t DADR2; + uint8_t RESERVED1[4]; + __IO uint16_t DACR; + uint8_t RESERVED2[2]; + __IO uint16_t RVADC; +} CM_CMP_COMMON_TypeDef; + +/** + * @brief CMU + */ +typedef struct { + uint8_t RESERVED0[16]; + __IO uint16_t PERICKSEL; + __IO uint16_t I2SCKSEL; + uint8_t RESERVED1[12]; + __IO uint32_t SCFGR; + __IO uint8_t USBCKCFGR; + uint8_t RESERVED2[1]; + __IO uint8_t CKSWR; + uint8_t RESERVED3[3]; + __IO uint8_t PLLCR; + uint8_t RESERVED4[3]; + __IO uint8_t UPLLCR; + uint8_t RESERVED5[3]; + __IO uint8_t XTALCR; + uint8_t RESERVED6[3]; + __IO uint8_t HRCCR; + uint8_t RESERVED7[1]; + __IO uint8_t MRCCR; + uint8_t RESERVED8[3]; + __IO uint8_t OSCSTBSR; + __IO uint8_t MCO1CFGR; + __IO uint8_t MCO2CFGR; + __IO uint8_t TPIUCKCFGR; + __IO uint8_t XTALSTDCR; + __IO uint8_t XTALSTDSR; + uint8_t RESERVED9[31]; + __IO uint8_t MRCTRM; + __IO uint8_t HRCTRM; + uint8_t RESERVED10[63]; + __IO uint8_t XTALSTBCR; + uint8_t RESERVED11[93]; + __IO uint32_t PLLCFGR; + __IO uint32_t UPLLCFGR; + uint8_t RESERVED12[776]; + __IO uint8_t XTALCFGR; + uint8_t RESERVED13[15]; + __IO uint8_t XTAL32CR; + __IO uint8_t XTAL32CFGR; + uint8_t RESERVED14[3]; + __IO uint8_t XTAL32NFR; + uint8_t RESERVED15[1]; + __IO uint8_t LRCCR; + uint8_t RESERVED16[1]; + __IO uint8_t LRCTRM; +} CM_CMU_TypeDef; + +/** + * @brief CRC + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t RESLT; + uint8_t RESERVED0[4]; + __I uint32_t FLG; + uint8_t RESERVED1[112]; + __I uint32_t DAT0; + __I uint32_t DAT1; + __I uint32_t DAT2; + __I uint32_t DAT3; + __I uint32_t DAT4; + __I uint32_t DAT5; + __I uint32_t DAT6; + __I uint32_t DAT7; + __I uint32_t DAT8; + __I uint32_t DAT9; + __I uint32_t DAT10; + __I uint32_t DAT11; + __I uint32_t DAT12; + __I uint32_t DAT13; + __I uint32_t DAT14; + __I uint32_t DAT15; + __I uint32_t DAT16; + __I uint32_t DAT17; + __I uint32_t DAT18; + __I uint32_t DAT19; + __I uint32_t DAT20; + __I uint32_t DAT21; + __I uint32_t DAT22; + __I uint32_t DAT23; + __I uint32_t DAT24; + __I uint32_t DAT25; + __I uint32_t DAT26; + __I uint32_t DAT27; + __I uint32_t DAT28; + __I uint32_t DAT29; + __I uint32_t DAT30; + __I uint32_t DAT31; +} CM_CRC_TypeDef; + +/** + * @brief DBGC + */ +typedef struct { + uint8_t RESERVED0[28]; + __IO uint32_t MCUDBGSTAT; + __IO uint32_t MCUSTPCTL; + __IO uint32_t MCUTRACECTL; +} CM_DBGC_TypeDef; + +/** + * @brief DCU + */ +typedef struct { + __IO uint32_t CTL; + __O uint32_t FLAG; + __IO uint32_t DATA0; + __IO uint32_t DATA1; + __IO uint32_t DATA2; + __O uint32_t FLAGCLR; + __IO uint32_t INTEVTSEL; +} CM_DCU_TypeDef; + +/** + * @brief DMA + */ +typedef struct { + __IO uint32_t EN; + __I uint32_t INTSTAT0; + __I uint32_t INTSTAT1; + __IO uint32_t INTMASK0; + __IO uint32_t INTMASK1; + __O uint32_t INTCLR0; + __O uint32_t INTCLR1; + __IO uint32_t CHEN; + __I uint32_t REQSTAT; + __I uint32_t CHSTAT; + uint8_t RESERVED0[4]; + __IO uint32_t RCFGCTL; + __O uint32_t SWREQ; + uint8_t RESERVED1[12]; + __IO uint32_t SAR0; + __IO uint32_t DAR0; + __IO uint32_t DTCTL0; + union { + __IO uint32_t RPT0; + __IO uint32_t RPTB0; + }; + union { + __IO uint32_t SNSEQCTL0; + __IO uint32_t SNSEQCTLB0; + }; + union { + __IO uint32_t DNSEQCTL0; + __IO uint32_t DNSEQCTLB0; + }; + __IO uint32_t LLP0; + __IO uint32_t CHCTL0; + __I uint32_t MONSAR0; + __I uint32_t MONDAR0; + __I uint32_t MONDTCTL0; + __I uint32_t MONRPT0; + __I uint32_t MONSNSEQCTL0; + __I uint32_t MONDNSEQCTL0; + uint8_t RESERVED2[8]; + __IO uint32_t SAR1; + __IO uint32_t DAR1; + __IO uint32_t DTCTL1; + union { + __IO uint32_t RPT1; + __IO uint32_t RPTB1; + }; + union { + __IO uint32_t SNSEQCTL1; + __IO uint32_t SNSEQCTLB1; + }; + union { + __IO uint32_t DNSEQCTL1; + __IO uint32_t DNSEQCTLB1; + }; + __IO uint32_t LLP1; + __IO uint32_t CHCTL1; + __I uint32_t MONSAR1; + __I uint32_t MONDAR1; + __I uint32_t MONDTCTL1; + __I uint32_t MONRPT1; + __I uint32_t MONSNSEQCTL1; + __I uint32_t MONDNSEQCTL1; + uint8_t RESERVED3[8]; + __IO uint32_t SAR2; + __IO uint32_t DAR2; + __IO uint32_t DTCTL2; + union { + __IO uint32_t RPT2; + __IO uint32_t RPTB2; + }; + union { + __IO uint32_t SNSEQCTL2; + __IO uint32_t SNSEQCTLB2; + }; + union { + __IO uint32_t DNSEQCTL2; + __IO uint32_t DNSEQCTLB2; + }; + __IO uint32_t LLP2; + __IO uint32_t CHCTL2; + __I uint32_t MONSAR2; + __I uint32_t MONDAR2; + __I uint32_t MONDTCTL2; + __I uint32_t MONRPT2; + __I uint32_t MONSNSEQCTL2; + __I uint32_t MONDNSEQCTL2; + uint8_t RESERVED4[8]; + __IO uint32_t SAR3; + __IO uint32_t DAR3; + __IO uint32_t DTCTL3; + union { + __IO uint32_t RPT3; + __IO uint32_t RPTB3; + }; + union { + __IO uint32_t SNSEQCTL3; + __IO uint32_t SNSEQCTLB3; + }; + union { + __IO uint32_t DNSEQCTL3; + __IO uint32_t DNSEQCTLB3; + }; + __IO uint32_t LLP3; + __IO uint32_t CHCTL3; + __I uint32_t MONSAR3; + __I uint32_t MONDAR3; + __I uint32_t MONDTCTL3; + __I uint32_t MONRPT3; + __I uint32_t MONSNSEQCTL3; + __I uint32_t MONDNSEQCTL3; +} CM_DMA_TypeDef; + +/** + * @brief EFM + */ +typedef struct { + __IO uint32_t FAPRT; + __IO uint32_t FSTP; + __IO uint32_t FRMC; + __IO uint32_t FWMC; + __I uint32_t FSR; + __IO uint32_t FSCLR; + __IO uint32_t FITE; + __I uint32_t FSWP; + __IO uint32_t FPMTSW; + __IO uint32_t FPMTEW; + uint8_t RESERVED0[40]; + __I uint32_t UQID0; + __I uint32_t UQID1; + __I uint32_t UQID2; + uint8_t RESERVED1[164]; + __IO uint32_t MMF_REMPRT; + __IO uint32_t MMF_REMCR0; + __IO uint32_t MMF_REMCR1; +} CM_EFM_TypeDef; + +/** + * @brief EMB + */ +typedef struct { + __IO uint32_t CTL; + __IO uint32_t PWMLV; + __IO uint32_t SOE; + __I uint32_t STAT; + __O uint32_t STATCLR; + __IO uint32_t INTEN; +} CM_EMB_TypeDef; + +/** + * @brief FCM + */ +typedef struct { + __IO uint32_t LVR; + __IO uint32_t UVR; + __I uint32_t CNTR; + __IO uint32_t STR; + __IO uint32_t MCCR; + __IO uint32_t RCCR; + __IO uint32_t RIER; + __I uint32_t SR; + __O uint32_t CLR; +} CM_FCM_TypeDef; + +/** + * @brief GPIO + */ +typedef struct { + __I uint16_t PIDRA; + uint8_t RESERVED0[2]; + __IO uint16_t PODRA; + __IO uint16_t POERA; + __IO uint16_t POSRA; + __IO uint16_t PORRA; + __IO uint16_t POTRA; + uint8_t RESERVED1[2]; + __I uint16_t PIDRB; + uint8_t RESERVED2[2]; + __IO uint16_t PODRB; + __IO uint16_t POERB; + __IO uint16_t POSRB; + __IO uint16_t PORRB; + __IO uint16_t POTRB; + uint8_t RESERVED3[2]; + __I uint16_t PIDRC; + uint8_t RESERVED4[2]; + __IO uint16_t PODRC; + __IO uint16_t POERC; + __IO uint16_t POSRC; + __IO uint16_t PORRC; + __IO uint16_t POTRC; + uint8_t RESERVED5[2]; + __I uint16_t PIDRD; + uint8_t RESERVED6[2]; + __IO uint16_t PODRD; + __IO uint16_t POERD; + __IO uint16_t POSRD; + __IO uint16_t PORRD; + __IO uint16_t POTRD; + uint8_t RESERVED7[2]; + __I uint16_t PIDRE; + uint8_t RESERVED8[2]; + __IO uint16_t PODRE; + __IO uint16_t POERE; + __IO uint16_t POSRE; + __IO uint16_t PORRE; + __IO uint16_t POTRE; + uint8_t RESERVED9[2]; + __I uint16_t PIDRH; + uint8_t RESERVED10[2]; + __IO uint16_t PODRH; + __IO uint16_t POERH; + __IO uint16_t POSRH; + __IO uint16_t PORRH; + __IO uint16_t POTRH; + uint8_t RESERVED11[918]; + __IO uint16_t PSPCR; + uint8_t RESERVED12[2]; + __IO uint16_t PCCR; + __IO uint16_t PINAER; + __IO uint16_t PWPR; + uint8_t RESERVED13[2]; + __IO uint16_t PCRA0; + __IO uint16_t PFSRA0; + __IO uint16_t PCRA1; + __IO uint16_t PFSRA1; + __IO uint16_t PCRA2; + __IO uint16_t PFSRA2; + __IO uint16_t PCRA3; + __IO uint16_t PFSRA3; + __IO uint16_t PCRA4; + __IO uint16_t PFSRA4; + __IO uint16_t PCRA5; + __IO uint16_t PFSRA5; + __IO uint16_t PCRA6; + __IO uint16_t PFSRA6; + __IO uint16_t PCRA7; + __IO uint16_t PFSRA7; + __IO uint16_t PCRA8; + __IO uint16_t PFSRA8; + __IO uint16_t PCRA9; + __IO uint16_t PFSRA9; + __IO uint16_t PCRA10; + __IO uint16_t PFSRA10; + __IO uint16_t PCRA11; + __IO uint16_t PFSRA11; + __IO uint16_t PCRA12; + __IO uint16_t PFSRA12; + __IO uint16_t PCRA13; + __IO uint16_t PFSRA13; + __IO uint16_t PCRA14; + __IO uint16_t PFSRA14; + __IO uint16_t PCRA15; + __IO uint16_t PFSRA15; + __IO uint16_t PCRB0; + __IO uint16_t PFSRB0; + __IO uint16_t PCRB1; + __IO uint16_t PFSRB1; + __IO uint16_t PCRB2; + __IO uint16_t PFSRB2; + __IO uint16_t PCRB3; + __IO uint16_t PFSRB3; + __IO uint16_t PCRB4; + __IO uint16_t PFSRB4; + __IO uint16_t PCRB5; + __IO uint16_t PFSRB5; + __IO uint16_t PCRB6; + __IO uint16_t PFSRB6; + __IO uint16_t PCRB7; + __IO uint16_t PFSRB7; + __IO uint16_t PCRB8; + __IO uint16_t PFSRB8; + __IO uint16_t PCRB9; + __IO uint16_t PFSRB9; + __IO uint16_t PCRB10; + __IO uint16_t PFSRB10; + __IO uint16_t PCRB11; + __IO uint16_t PFSRB11; + __IO uint16_t PCRB12; + __IO uint16_t PFSRB12; + __IO uint16_t PCRB13; + __IO uint16_t PFSRB13; + __IO uint16_t PCRB14; + __IO uint16_t PFSRB14; + __IO uint16_t PCRB15; + __IO uint16_t PFSRB15; + __IO uint16_t PCRC0; + __IO uint16_t PFSRC0; + __IO uint16_t PCRC1; + __IO uint16_t PFSRC1; + __IO uint16_t PCRC2; + __IO uint16_t PFSRC2; + __IO uint16_t PCRC3; + __IO uint16_t PFSRC3; + __IO uint16_t PCRC4; + __IO uint16_t PFSRC4; + __IO uint16_t PCRC5; + __IO uint16_t PFSRC5; + __IO uint16_t PCRC6; + __IO uint16_t PFSRC6; + __IO uint16_t PCRC7; + __IO uint16_t PFSRC7; + __IO uint16_t PCRC8; + __IO uint16_t PFSRC8; + __IO uint16_t PCRC9; + __IO uint16_t PFSRC9; + __IO uint16_t PCRC10; + __IO uint16_t PFSRC10; + __IO uint16_t PCRC11; + __IO uint16_t PFSRC11; + __IO uint16_t PCRC12; + __IO uint16_t PFSRC12; + __IO uint16_t PCRC13; + __IO uint16_t PFSRC13; + __IO uint16_t PCRC14; + __IO uint16_t PFSRC14; + __IO uint16_t PCRC15; + __IO uint16_t PFSRC15; + __IO uint16_t PCRD0; + __IO uint16_t PFSRD0; + __IO uint16_t PCRD1; + __IO uint16_t PFSRD1; + __IO uint16_t PCRD2; + __IO uint16_t PFSRD2; + __IO uint16_t PCRD3; + __IO uint16_t PFSRD3; + __IO uint16_t PCRD4; + __IO uint16_t PFSRD4; + __IO uint16_t PCRD5; + __IO uint16_t PFSRD5; + __IO uint16_t PCRD6; + __IO uint16_t PFSRD6; + __IO uint16_t PCRD7; + __IO uint16_t PFSRD7; + __IO uint16_t PCRD8; + __IO uint16_t PFSRD8; + __IO uint16_t PCRD9; + __IO uint16_t PFSRD9; + __IO uint16_t PCRD10; + __IO uint16_t PFSRD10; + __IO uint16_t PCRD11; + __IO uint16_t PFSRD11; + __IO uint16_t PCRD12; + __IO uint16_t PFSRD12; + __IO uint16_t PCRD13; + __IO uint16_t PFSRD13; + __IO uint16_t PCRD14; + __IO uint16_t PFSRD14; + __IO uint16_t PCRD15; + __IO uint16_t PFSRD15; + __IO uint16_t PCRE0; + __IO uint16_t PFSRE0; + __IO uint16_t PCRE1; + __IO uint16_t PFSRE1; + __IO uint16_t PCRE2; + __IO uint16_t PFSRE2; + __IO uint16_t PCRE3; + __IO uint16_t PFSRE3; + __IO uint16_t PCRE4; + __IO uint16_t PFSRE4; + __IO uint16_t PCRE5; + __IO uint16_t PFSRE5; + __IO uint16_t PCRE6; + __IO uint16_t PFSRE6; + __IO uint16_t PCRE7; + __IO uint16_t PFSRE7; + __IO uint16_t PCRE8; + __IO uint16_t PFSRE8; + __IO uint16_t PCRE9; + __IO uint16_t PFSRE9; + __IO uint16_t PCRE10; + __IO uint16_t PFSRE10; + __IO uint16_t PCRE11; + __IO uint16_t PFSRE11; + __IO uint16_t PCRE12; + __IO uint16_t PFSRE12; + __IO uint16_t PCRE13; + __IO uint16_t PFSRE13; + __IO uint16_t PCRE14; + __IO uint16_t PFSRE14; + __IO uint16_t PCRE15; + __IO uint16_t PFSRE15; + __IO uint16_t PCRH0; + __IO uint16_t PFSRH0; + __IO uint16_t PCRH1; + __IO uint16_t PFSRH1; + __IO uint16_t PCRH2; + __IO uint16_t PFSRH2; +} CM_GPIO_TypeDef; + +/** + * @brief HASH + */ +typedef struct { + __IO uint32_t CR; + uint8_t RESERVED0[12]; + __IO uint32_t HR7; + __IO uint32_t HR6; + __IO uint32_t HR5; + __IO uint32_t HR4; + __IO uint32_t HR3; + __IO uint32_t HR2; + __IO uint32_t HR1; + __IO uint32_t HR0; + uint8_t RESERVED1[16]; + __IO uint32_t DR15; + __IO uint32_t DR14; + __IO uint32_t DR13; + __IO uint32_t DR12; + __IO uint32_t DR11; + __IO uint32_t DR10; + __IO uint32_t DR9; + __IO uint32_t DR8; + __IO uint32_t DR7; + __IO uint32_t DR6; + __IO uint32_t DR5; + __IO uint32_t DR4; + __IO uint32_t DR3; + __IO uint32_t DR2; + __IO uint32_t DR1; + __IO uint32_t DR0; +} CM_HASH_TypeDef; + +/** + * @brief I2C + */ +typedef struct { + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t CR3; + __IO uint32_t CR4; + __IO uint32_t SLR0; + __IO uint32_t SLR1; + __IO uint32_t SLTR; + __IO uint32_t SR; + __O uint32_t CLR; + __O uint8_t DTR; + uint8_t RESERVED0[3]; + __I uint8_t DRR; + uint8_t RESERVED1[3]; + __IO uint32_t CCR; + __IO uint32_t FLTR; +} CM_I2C_TypeDef; + +/** + * @brief I2S + */ +typedef struct { + __IO uint32_t CTRL; + __I uint32_t SR; + __IO uint32_t ER; + __IO uint32_t CFGR; + __O uint32_t TXBUF; + __I uint32_t RXBUF; + __IO uint32_t PR; +} CM_I2S_TypeDef; + +/** + * @brief ICG + */ +typedef struct { + __I uint32_t ICG0; + __I uint32_t ICG1; + __I uint32_t ICG2; + __I uint32_t ICG3; + __I uint32_t ICG4; + __I uint32_t ICG5; + __I uint32_t ICG6; + __I uint32_t ICG7; +} CM_ICG_TypeDef; + +/** + * @brief INTC + */ +typedef struct { + __IO uint32_t NMICR; + __IO uint32_t NMIENR; + __IO uint32_t NMIFR; + __IO uint32_t NMICFR; + __IO uint32_t EIRQCR0; + __IO uint32_t EIRQCR1; + __IO uint32_t EIRQCR2; + __IO uint32_t EIRQCR3; + __IO uint32_t EIRQCR4; + __IO uint32_t EIRQCR5; + __IO uint32_t EIRQCR6; + __IO uint32_t EIRQCR7; + __IO uint32_t EIRQCR8; + __IO uint32_t EIRQCR9; + __IO uint32_t EIRQCR10; + __IO uint32_t EIRQCR11; + __IO uint32_t EIRQCR12; + __IO uint32_t EIRQCR13; + __IO uint32_t EIRQCR14; + __IO uint32_t EIRQCR15; + __IO uint32_t WUPEN; + __IO uint32_t EIFR; + __IO uint32_t EIFCR; + __IO uint32_t SEL0; + __IO uint32_t SEL1; + __IO uint32_t SEL2; + __IO uint32_t SEL3; + __IO uint32_t SEL4; + __IO uint32_t SEL5; + __IO uint32_t SEL6; + __IO uint32_t SEL7; + __IO uint32_t SEL8; + __IO uint32_t SEL9; + __IO uint32_t SEL10; + __IO uint32_t SEL11; + __IO uint32_t SEL12; + __IO uint32_t SEL13; + __IO uint32_t SEL14; + __IO uint32_t SEL15; + __IO uint32_t SEL16; + __IO uint32_t SEL17; + __IO uint32_t SEL18; + __IO uint32_t SEL19; + __IO uint32_t SEL20; + __IO uint32_t SEL21; + __IO uint32_t SEL22; + __IO uint32_t SEL23; + __IO uint32_t SEL24; + __IO uint32_t SEL25; + __IO uint32_t SEL26; + __IO uint32_t SEL27; + __IO uint32_t SEL28; + __IO uint32_t SEL29; + __IO uint32_t SEL30; + __IO uint32_t SEL31; + __IO uint32_t SEL32; + __IO uint32_t SEL33; + __IO uint32_t SEL34; + __IO uint32_t SEL35; + __IO uint32_t SEL36; + __IO uint32_t SEL37; + __IO uint32_t SEL38; + __IO uint32_t SEL39; + __IO uint32_t SEL40; + __IO uint32_t SEL41; + __IO uint32_t SEL42; + __IO uint32_t SEL43; + __IO uint32_t SEL44; + __IO uint32_t SEL45; + __IO uint32_t SEL46; + __IO uint32_t SEL47; + __IO uint32_t SEL48; + __IO uint32_t SEL49; + __IO uint32_t SEL50; + __IO uint32_t SEL51; + __IO uint32_t SEL52; + __IO uint32_t SEL53; + __IO uint32_t SEL54; + __IO uint32_t SEL55; + __IO uint32_t SEL56; + __IO uint32_t SEL57; + __IO uint32_t SEL58; + __IO uint32_t SEL59; + __IO uint32_t SEL60; + __IO uint32_t SEL61; + __IO uint32_t SEL62; + __IO uint32_t SEL63; + __IO uint32_t SEL64; + __IO uint32_t SEL65; + __IO uint32_t SEL66; + __IO uint32_t SEL67; + __IO uint32_t SEL68; + __IO uint32_t SEL69; + __IO uint32_t SEL70; + __IO uint32_t SEL71; + __IO uint32_t SEL72; + __IO uint32_t SEL73; + __IO uint32_t SEL74; + __IO uint32_t SEL75; + __IO uint32_t SEL76; + __IO uint32_t SEL77; + __IO uint32_t SEL78; + __IO uint32_t SEL79; + __IO uint32_t SEL80; + __IO uint32_t SEL81; + __IO uint32_t SEL82; + __IO uint32_t SEL83; + __IO uint32_t SEL84; + __IO uint32_t SEL85; + __IO uint32_t SEL86; + __IO uint32_t SEL87; + __IO uint32_t SEL88; + __IO uint32_t SEL89; + __IO uint32_t SEL90; + __IO uint32_t SEL91; + __IO uint32_t SEL92; + __IO uint32_t SEL93; + __IO uint32_t SEL94; + __IO uint32_t SEL95; + __IO uint32_t SEL96; + __IO uint32_t SEL97; + __IO uint32_t SEL98; + __IO uint32_t SEL99; + __IO uint32_t SEL100; + __IO uint32_t SEL101; + __IO uint32_t SEL102; + __IO uint32_t SEL103; + __IO uint32_t SEL104; + __IO uint32_t SEL105; + __IO uint32_t SEL106; + __IO uint32_t SEL107; + __IO uint32_t SEL108; + __IO uint32_t SEL109; + __IO uint32_t SEL110; + __IO uint32_t SEL111; + __IO uint32_t SEL112; + __IO uint32_t SEL113; + __IO uint32_t SEL114; + __IO uint32_t SEL115; + __IO uint32_t SEL116; + __IO uint32_t SEL117; + __IO uint32_t SEL118; + __IO uint32_t SEL119; + __IO uint32_t SEL120; + __IO uint32_t SEL121; + __IO uint32_t SEL122; + __IO uint32_t SEL123; + __IO uint32_t SEL124; + __IO uint32_t SEL125; + __IO uint32_t SEL126; + __IO uint32_t SEL127; + __IO uint32_t VSSEL128; + __IO uint32_t VSSEL129; + __IO uint32_t VSSEL130; + __IO uint32_t VSSEL131; + __IO uint32_t VSSEL132; + __IO uint32_t VSSEL133; + __IO uint32_t VSSEL134; + __IO uint32_t VSSEL135; + __IO uint32_t VSSEL136; + __IO uint32_t VSSEL137; + __IO uint32_t VSSEL138; + __IO uint32_t VSSEL139; + __IO uint32_t VSSEL140; + __IO uint32_t VSSEL141; + __IO uint32_t VSSEL142; + __IO uint32_t VSSEL143; + __IO uint32_t SWIER; + __IO uint32_t EVTER; + __IO uint32_t IER; +} CM_INTC_TypeDef; + +/** + * @brief KEYSCAN + */ +typedef struct { + __IO uint32_t SCR; + __IO uint32_t SER; + __IO uint32_t SSR; +} CM_KEYSCAN_TypeDef; + +/** + * @brief MPU + */ +typedef struct { + __IO uint32_t RGD0; + __IO uint32_t RGD1; + __IO uint32_t RGD2; + __IO uint32_t RGD3; + __IO uint32_t RGD4; + __IO uint32_t RGD5; + __IO uint32_t RGD6; + __IO uint32_t RGD7; + __IO uint32_t RGD8; + __IO uint32_t RGD9; + __IO uint32_t RGD10; + __IO uint32_t RGD11; + __IO uint32_t RGD12; + __IO uint32_t RGD13; + __IO uint32_t RGD14; + __IO uint32_t RGD15; + __IO uint32_t RGCR0; + __IO uint32_t RGCR1; + __IO uint32_t RGCR2; + __IO uint32_t RGCR3; + __IO uint32_t RGCR4; + __IO uint32_t RGCR5; + __IO uint32_t RGCR6; + __IO uint32_t RGCR7; + __IO uint32_t RGCR8; + __IO uint32_t RGCR9; + __IO uint32_t RGCR10; + __IO uint32_t RGCR11; + __IO uint32_t RGCR12; + __IO uint32_t RGCR13; + __IO uint32_t RGCR14; + __IO uint32_t RGCR15; + __IO uint32_t CR; + __I uint32_t SR; + __O uint32_t ECLR; + __IO uint32_t WP; + uint8_t RESERVED0[16268]; + __IO uint32_t IPPR; +} CM_MPU_TypeDef; + +/** + * @brief OTS + */ +typedef struct { + __IO uint16_t CTL; + __IO uint16_t DR1; + __IO uint16_t DR2; + __IO uint16_t ECR; +} CM_OTS_TypeDef; + +/** + * @brief PERIC + */ +typedef struct { + __IO uint32_t USBFS_SYCTLREG; + __IO uint32_t SDIOC_SYCTLREG; +} CM_PERIC_TypeDef; + +/** + * @brief PWC + */ +typedef struct { + __IO uint32_t FCG0; + __IO uint32_t FCG1; + __IO uint32_t FCG2; + __IO uint32_t FCG3; + __IO uint32_t FCG0PC; + uint8_t RESERVED0[17388]; + __IO uint16_t WKTCR; + uint8_t RESERVED1[31754]; + __IO uint16_t STPMCR; + uint8_t RESERVED2[6]; + __IO uint32_t RAMPC0; + __IO uint16_t RAMOPM; + uint8_t RESERVED3[198]; + __IO uint8_t PVDICR; + __IO uint8_t PVDDSR; + uint8_t RESERVED4[796]; + __IO uint16_t FPRC; + __IO uint8_t PWRC0; + __IO uint8_t PWRC1; + __IO uint8_t PWRC2; + __IO uint8_t PWRC3; + __IO uint8_t PDWKE0; + __IO uint8_t PDWKE1; + __IO uint8_t PDWKE2; + __IO uint8_t PDWKES; + __IO uint8_t PDWKF0; + __IO uint8_t PDWKF1; + __IO uint8_t PWCMR; + uint8_t RESERVED5[4]; + __IO uint8_t MDSWCR; + uint8_t RESERVED6[2]; + __IO uint8_t PVDCR0; + __IO uint8_t PVDCR1; + __IO uint8_t PVDFCR; + __IO uint8_t PVDLCR; + uint8_t RESERVED7[21]; + __IO uint8_t XTAL32CS; +} CM_PWC_TypeDef; + +/** + * @brief QSPI + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t CSCR; + __IO uint32_t FCR; + __IO uint32_t SR; + __IO uint32_t DCOM; + __IO uint32_t CCMD; + __IO uint32_t XCMD; + uint8_t RESERVED0[8]; + __O uint32_t CLR; + uint8_t RESERVED1[2012]; + __IO uint32_t EXAR; +} CM_QSPI_TypeDef; + +/** + * @brief RMU + */ +typedef struct { + __IO uint16_t RSTF0; +} CM_RMU_TypeDef; + +/** + * @brief RTC + */ +typedef struct { + __IO uint8_t CR0; + uint8_t RESERVED0[3]; + __IO uint8_t CR1; + uint8_t RESERVED1[3]; + __IO uint8_t CR2; + uint8_t RESERVED2[3]; + __IO uint8_t CR3; + uint8_t RESERVED3[3]; + __IO uint8_t SEC; + uint8_t RESERVED4[3]; + __IO uint8_t MIN; + uint8_t RESERVED5[3]; + __IO uint8_t HOUR; + uint8_t RESERVED6[3]; + __IO uint8_t WEEK; + uint8_t RESERVED7[3]; + __IO uint8_t DAY; + uint8_t RESERVED8[3]; + __IO uint8_t MON; + uint8_t RESERVED9[3]; + __IO uint8_t YEAR; + uint8_t RESERVED10[3]; + __IO uint8_t ALMMIN; + uint8_t RESERVED11[3]; + __IO uint8_t ALMHOUR; + uint8_t RESERVED12[3]; + __IO uint8_t ALMWEEK; + uint8_t RESERVED13[3]; + __IO uint8_t ERRCRH; + uint8_t RESERVED14[3]; + __IO uint8_t ERRCRL; +} CM_RTC_TypeDef; + +/** + * @brief SDIOC + */ +typedef struct { + uint8_t RESERVED0[4]; + __IO uint16_t BLKSIZE; + __IO uint16_t BLKCNT; + __IO uint16_t ARG0; + __IO uint16_t ARG1; + __IO uint16_t TRANSMODE; + __IO uint16_t CMD; + __I uint16_t RESP0; + __I uint16_t RESP1; + __I uint16_t RESP2; + __I uint16_t RESP3; + __I uint16_t RESP4; + __I uint16_t RESP5; + __I uint16_t RESP6; + __I uint16_t RESP7; + __IO uint16_t BUF0; + __IO uint16_t BUF1; + __I uint32_t PSTAT; + __IO uint8_t HOSTCON; + __IO uint8_t PWRCON; + __IO uint8_t BLKGPCON; + uint8_t RESERVED1[1]; + __IO uint16_t CLKCON; + __IO uint8_t TOUTCON; + __IO uint8_t SFTRST; + __IO uint16_t NORINTST; + __IO uint16_t ERRINTST; + __IO uint16_t NORINTSTEN; + __IO uint16_t ERRINTSTEN; + __IO uint16_t NORINTSGEN; + __IO uint16_t ERRINTSGEN; + __I uint16_t ATCERRST; + uint8_t RESERVED2[18]; + __O uint16_t FEA; + __O uint16_t FEE; +} CM_SDIOC_TypeDef; + +/** + * @brief SPI + */ +typedef struct { + __IO uint32_t DR; + __IO uint32_t CR1; + uint8_t RESERVED0[4]; + __IO uint32_t CFG1; + uint8_t RESERVED1[4]; + __IO uint32_t SR; + __IO uint32_t CFG2; +} CM_SPI_TypeDef; + +/** + * @brief SRAMC + */ +typedef struct { + __IO uint32_t WTCR; + __IO uint32_t WTPR; + __IO uint32_t CKCR; + __IO uint32_t CKPR; + __IO uint32_t CKSR; +} CM_SRAMC_TypeDef; + +/** + * @brief SWDT + */ +typedef struct { + uint8_t RESERVED0[4]; + __IO uint32_t SR; + __IO uint32_t RR; +} CM_SWDT_TypeDef; + +/** + * @brief TMR0 + */ +typedef struct { + __IO uint32_t CNTAR; + __IO uint32_t CNTBR; + __IO uint32_t CMPAR; + __IO uint32_t CMPBR; + __IO uint32_t BCONR; + __IO uint32_t STFLR; +} CM_TMR0_TypeDef; + +/** + * @brief TMR4 + */ +typedef struct { + uint8_t RESERVED0[2]; + __IO uint16_t OCCRUH; + uint8_t RESERVED1[2]; + __IO uint16_t OCCRUL; + uint8_t RESERVED2[2]; + __IO uint16_t OCCRVH; + uint8_t RESERVED3[2]; + __IO uint16_t OCCRVL; + uint8_t RESERVED4[2]; + __IO uint16_t OCCRWH; + uint8_t RESERVED5[2]; + __IO uint16_t OCCRWL; + __IO uint16_t OCSRU; + __IO uint16_t OCERU; + __IO uint16_t OCSRV; + __IO uint16_t OCERV; + __IO uint16_t OCSRW; + __IO uint16_t OCERW; + __IO uint16_t OCMRUH; + uint8_t RESERVED6[2]; + __IO uint32_t OCMRUL; + __IO uint16_t OCMRVH; + uint8_t RESERVED7[2]; + __IO uint32_t OCMRVL; + __IO uint16_t OCMRWH; + uint8_t RESERVED8[2]; + __IO uint32_t OCMRWL; + uint8_t RESERVED9[6]; + __IO uint16_t CPSR; + uint8_t RESERVED10[2]; + __IO uint16_t CNTR; + __IO uint16_t CCSR; + __IO uint16_t CVPR; + uint8_t RESERVED11[54]; + __IO uint16_t PFSRU; + __IO uint16_t PDARU; + __IO uint16_t PDBRU; + uint8_t RESERVED12[2]; + __IO uint16_t PFSRV; + __IO uint16_t PDARV; + __IO uint16_t PDBRV; + uint8_t RESERVED13[2]; + __IO uint16_t PFSRW; + __IO uint16_t PDARW; + __IO uint16_t PDBRW; + __IO uint16_t POCRU; + uint8_t RESERVED14[2]; + __IO uint16_t POCRV; + uint8_t RESERVED15[2]; + __IO uint16_t POCRW; + uint8_t RESERVED16[2]; + __IO uint16_t RCSR; + uint8_t RESERVED17[12]; + __IO uint16_t SCCRUH; + uint8_t RESERVED18[2]; + __IO uint16_t SCCRUL; + uint8_t RESERVED19[2]; + __IO uint16_t SCCRVH; + uint8_t RESERVED20[2]; + __IO uint16_t SCCRVL; + uint8_t RESERVED21[2]; + __IO uint16_t SCCRWH; + uint8_t RESERVED22[2]; + __IO uint16_t SCCRWL; + __IO uint16_t SCSRUH; + __IO uint16_t SCMRUH; + __IO uint16_t SCSRUL; + __IO uint16_t SCMRUL; + __IO uint16_t SCSRVH; + __IO uint16_t SCMRVH; + __IO uint16_t SCSRVL; + __IO uint16_t SCMRVL; + __IO uint16_t SCSRWH; + __IO uint16_t SCMRWH; + __IO uint16_t SCSRWL; + __IO uint16_t SCMRWL; + uint8_t RESERVED23[16]; + __IO uint16_t ECSR; +} CM_TMR4_TypeDef; + +/** + * @brief TMR4_ECER + */ +typedef struct { + __IO uint32_t ECER1; + __IO uint32_t ECER2; + __IO uint32_t ECER3; +} CM_TMR4_ECER_TypeDef; + +/** + * @brief TMR6 + */ +typedef struct { + __IO uint32_t CNTER; + __IO uint32_t PERAR; + __IO uint32_t PERBR; + __IO uint32_t PERCR; + __IO uint32_t GCMAR; + __IO uint32_t GCMBR; + __IO uint32_t GCMCR; + __IO uint32_t GCMDR; + __IO uint32_t GCMER; + __IO uint32_t GCMFR; + __IO uint32_t SCMAR; + __IO uint32_t SCMBR; + __IO uint32_t SCMCR; + __IO uint32_t SCMDR; + __IO uint32_t SCMER; + __IO uint32_t SCMFR; + __IO uint32_t DTUAR; + __IO uint32_t DTDAR; + __IO uint32_t DTUBR; + __IO uint32_t DTDBR; + __IO uint32_t GCONR; + __IO uint32_t ICONR; + __IO uint32_t PCONR; + __IO uint32_t BCONR; + __IO uint32_t DCONR; + uint8_t RESERVED0[4]; + __IO uint32_t FCONR; + __IO uint32_t VPERR; + __IO uint32_t STFLR; + __IO uint32_t HSTAR; + __IO uint32_t HSTPR; + __IO uint32_t HCLRR; + __IO uint32_t HCPAR; + __IO uint32_t HCPBR; + __IO uint32_t HCUPR; + __IO uint32_t HCDOR; +} CM_TMR6_TypeDef; + +/** + * @brief TMR6_COMMON + */ +typedef struct { + uint8_t RESERVED0[244]; + __IO uint32_t SSTAR; + __IO uint32_t SSTPR; + __IO uint32_t SCLRR; +} CM_TMR6_COMMON_TypeDef; + +/** + * @brief TMRA + */ +typedef struct { + __IO uint16_t CNTER; + uint8_t RESERVED0[2]; + __IO uint16_t PERAR; + uint8_t RESERVED1[58]; + __IO uint16_t CMPAR1; + uint8_t RESERVED2[2]; + __IO uint16_t CMPAR2; + uint8_t RESERVED3[2]; + __IO uint16_t CMPAR3; + uint8_t RESERVED4[2]; + __IO uint16_t CMPAR4; + uint8_t RESERVED5[2]; + __IO uint16_t CMPAR5; + uint8_t RESERVED6[2]; + __IO uint16_t CMPAR6; + uint8_t RESERVED7[2]; + __IO uint16_t CMPAR7; + uint8_t RESERVED8[2]; + __IO uint16_t CMPAR8; + uint8_t RESERVED9[34]; + __IO uint8_t BCSTRL; + __IO uint8_t BCSTRH; + uint8_t RESERVED10[2]; + __IO uint16_t HCONR; + uint8_t RESERVED11[2]; + __IO uint16_t HCUPR; + uint8_t RESERVED12[2]; + __IO uint16_t HCDOR; + uint8_t RESERVED13[2]; + __IO uint16_t ICONR; + uint8_t RESERVED14[2]; + __IO uint16_t ECONR; + uint8_t RESERVED15[2]; + __IO uint16_t FCONR; + uint8_t RESERVED16[2]; + __IO uint16_t STFLR; + uint8_t RESERVED17[34]; + __IO uint16_t BCONR1; + uint8_t RESERVED18[6]; + __IO uint16_t BCONR2; + uint8_t RESERVED19[6]; + __IO uint16_t BCONR3; + uint8_t RESERVED20[6]; + __IO uint16_t BCONR4; + uint8_t RESERVED21[38]; + __IO uint16_t CCONR1; + uint8_t RESERVED22[2]; + __IO uint16_t CCONR2; + uint8_t RESERVED23[2]; + __IO uint16_t CCONR3; + uint8_t RESERVED24[2]; + __IO uint16_t CCONR4; + uint8_t RESERVED25[2]; + __IO uint16_t CCONR5; + uint8_t RESERVED26[2]; + __IO uint16_t CCONR6; + uint8_t RESERVED27[2]; + __IO uint16_t CCONR7; + uint8_t RESERVED28[2]; + __IO uint16_t CCONR8; + uint8_t RESERVED29[34]; + __IO uint16_t PCONR1; + uint8_t RESERVED30[2]; + __IO uint16_t PCONR2; + uint8_t RESERVED31[2]; + __IO uint16_t PCONR3; + uint8_t RESERVED32[2]; + __IO uint16_t PCONR4; + uint8_t RESERVED33[2]; + __IO uint16_t PCONR5; + uint8_t RESERVED34[2]; + __IO uint16_t PCONR6; + uint8_t RESERVED35[2]; + __IO uint16_t PCONR7; + uint8_t RESERVED36[2]; + __IO uint16_t PCONR8; +} CM_TMRA_TypeDef; + +/** + * @brief TRNG + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t MR; + uint8_t RESERVED0[4]; + __I uint32_t DR0; + __I uint32_t DR1; +} CM_TRNG_TypeDef; + +/** + * @brief USART + */ +typedef struct { + __I uint32_t SR; + __IO uint16_t TDR; + __I uint16_t RDR; + __IO uint32_t BRR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t CR3; + __IO uint32_t PR; +} CM_USART_TypeDef; + +/** + * @brief USBFS + */ +typedef struct { + __IO uint32_t GVBUSCFG; + uint8_t RESERVED0[4]; + __IO uint32_t GAHBCFG; + __IO uint32_t GUSBCFG; + __IO uint32_t GRSTCTL; + __IO uint32_t GINTSTS; + __IO uint32_t GINTMSK; + __I uint32_t GRXSTSR; + __I uint32_t GRXSTSP; + __IO uint32_t GRXFSIZ; + __IO uint32_t HNPTXFSIZ; + __I uint32_t HNPTXSTS; + uint8_t RESERVED1[12]; + __IO uint32_t CID; + uint8_t RESERVED2[192]; + __IO uint32_t HPTXFSIZ; + __IO uint32_t DIEPTXF1; + __IO uint32_t DIEPTXF2; + __IO uint32_t DIEPTXF3; + __IO uint32_t DIEPTXF4; + __IO uint32_t DIEPTXF5; + uint8_t RESERVED3[744]; + __IO uint32_t HCFG; + __IO uint32_t HFIR; + __I uint32_t HFNUM; + uint8_t RESERVED4[4]; + __I uint32_t HPTXSTS; + __I uint32_t HAINT; + __IO uint32_t HAINTMSK; + uint8_t RESERVED5[36]; + __IO uint32_t HPRT; + uint8_t RESERVED6[188]; + __IO uint32_t HCCHAR0; + uint8_t RESERVED7[4]; + __IO uint32_t HCINT0; + __IO uint32_t HCINTMSK0; + __IO uint32_t HCTSIZ0; + __IO uint32_t HCDMA0; + uint8_t RESERVED8[8]; + __IO uint32_t HCCHAR1; + uint8_t RESERVED9[4]; + __IO uint32_t HCINT1; + __IO uint32_t HCINTMSK1; + __IO uint32_t HCTSIZ1; + __IO uint32_t HCDMA1; + uint8_t RESERVED10[8]; + __IO uint32_t HCCHAR2; + uint8_t RESERVED11[4]; + __IO uint32_t HCINT2; + __IO uint32_t HCINTMSK2; + __IO uint32_t HCTSIZ2; + __IO uint32_t HCDMA2; + uint8_t RESERVED12[8]; + __IO uint32_t HCCHAR3; + uint8_t RESERVED13[4]; + __IO uint32_t HCINT3; + __IO uint32_t HCINTMSK3; + __IO uint32_t HCTSIZ3; + __IO uint32_t HCDMA3; + uint8_t RESERVED14[8]; + __IO uint32_t HCCHAR4; + uint8_t RESERVED15[4]; + __IO uint32_t HCINT4; + __IO uint32_t HCINTMSK4; + __IO uint32_t HCTSIZ4; + __IO uint32_t HCDMA4; + uint8_t RESERVED16[8]; + __IO uint32_t HCCHAR5; + uint8_t RESERVED17[4]; + __IO uint32_t HCINT5; + __IO uint32_t HCINTMSK5; + __IO uint32_t HCTSIZ5; + __IO uint32_t HCDMA5; + uint8_t RESERVED18[8]; + __IO uint32_t HCCHAR6; + uint8_t RESERVED19[4]; + __IO uint32_t HCINT6; + __IO uint32_t HCINTMSK6; + __IO uint32_t HCTSIZ6; + __IO uint32_t HCDMA6; + uint8_t RESERVED20[8]; + __IO uint32_t HCCHAR7; + uint8_t RESERVED21[4]; + __IO uint32_t HCINT7; + __IO uint32_t HCINTMSK7; + __IO uint32_t HCTSIZ7; + __IO uint32_t HCDMA7; + uint8_t RESERVED22[8]; + __IO uint32_t HCCHAR8; + uint8_t RESERVED23[4]; + __IO uint32_t HCINT8; + __IO uint32_t HCINTMSK8; + __IO uint32_t HCTSIZ8; + __IO uint32_t HCDMA8; + uint8_t RESERVED24[8]; + __IO uint32_t HCCHAR9; + uint8_t RESERVED25[4]; + __IO uint32_t HCINT9; + __IO uint32_t HCINTMSK9; + __IO uint32_t HCTSIZ9; + __IO uint32_t HCDMA9; + uint8_t RESERVED26[8]; + __IO uint32_t HCCHAR10; + uint8_t RESERVED27[4]; + __IO uint32_t HCINT10; + __IO uint32_t HCINTMSK10; + __IO uint32_t HCTSIZ10; + __IO uint32_t HCDMA10; + uint8_t RESERVED28[8]; + __IO uint32_t HCCHAR11; + uint8_t RESERVED29[4]; + __IO uint32_t HCINT11; + __IO uint32_t HCINTMSK11; + __IO uint32_t HCTSIZ11; + __IO uint32_t HCDMA11; + uint8_t RESERVED30[392]; + __IO uint32_t DCFG; + __IO uint32_t DCTL; + __I uint32_t DSTS; + uint8_t RESERVED31[4]; + __IO uint32_t DIEPMSK; + __IO uint32_t DOEPMSK; + __IO uint32_t DAINT; + __IO uint32_t DAINTMSK; + uint8_t RESERVED32[20]; + __IO uint32_t DIEPEMPMSK; + uint8_t RESERVED33[200]; + __IO uint32_t DIEPCTL0; + uint8_t RESERVED34[4]; + __IO uint32_t DIEPINT0; + uint8_t RESERVED35[4]; + __IO uint32_t DIEPTSIZ0; + __IO uint32_t DIEPDMA0; + __I uint32_t DTXFSTS0; + uint8_t RESERVED36[4]; + __IO uint32_t DIEPCTL1; + uint8_t RESERVED37[4]; + __IO uint32_t DIEPINT1; + uint8_t RESERVED38[4]; + __IO uint32_t DIEPTSIZ1; + __IO uint32_t DIEPDMA1; + __I uint32_t DTXFSTS1; + uint8_t RESERVED39[4]; + __IO uint32_t DIEPCTL2; + uint8_t RESERVED40[4]; + __IO uint32_t DIEPINT2; + uint8_t RESERVED41[4]; + __IO uint32_t DIEPTSIZ2; + __IO uint32_t DIEPDMA2; + __I uint32_t DTXFSTS2; + uint8_t RESERVED42[4]; + __IO uint32_t DIEPCTL3; + uint8_t RESERVED43[4]; + __IO uint32_t DIEPINT3; + uint8_t RESERVED44[4]; + __IO uint32_t DIEPTSIZ3; + __IO uint32_t DIEPDMA3; + __I uint32_t DTXFSTS3; + uint8_t RESERVED45[4]; + __IO uint32_t DIEPCTL4; + uint8_t RESERVED46[4]; + __IO uint32_t DIEPINT4; + uint8_t RESERVED47[4]; + __IO uint32_t DIEPTSIZ4; + __IO uint32_t DIEPDMA4; + __I uint32_t DTXFSTS4; + uint8_t RESERVED48[4]; + __IO uint32_t DIEPCTL5; + uint8_t RESERVED49[4]; + __IO uint32_t DIEPINT5; + uint8_t RESERVED50[4]; + __IO uint32_t DIEPTSIZ5; + __IO uint32_t DIEPDMA5; + __I uint32_t DTXFSTS5; + uint8_t RESERVED51[324]; + __IO uint32_t DOEPCTL0; + uint8_t RESERVED52[4]; + __IO uint32_t DOEPINT0; + uint8_t RESERVED53[4]; + __IO uint32_t DOEPTSIZ0; + __IO uint32_t DOEPDMA0; + uint8_t RESERVED54[8]; + __IO uint32_t DOEPCTL1; + uint8_t RESERVED55[4]; + __IO uint32_t DOEPINT1; + uint8_t RESERVED56[4]; + __IO uint32_t DOEPTSIZ1; + __IO uint32_t DOEPDMA1; + uint8_t RESERVED57[8]; + __IO uint32_t DOEPCTL2; + uint8_t RESERVED58[4]; + __IO uint32_t DOEPINT2; + uint8_t RESERVED59[4]; + __IO uint32_t DOEPTSIZ2; + __IO uint32_t DOEPDMA2; + uint8_t RESERVED60[8]; + __IO uint32_t DOEPCTL3; + uint8_t RESERVED61[4]; + __IO uint32_t DOEPINT3; + uint8_t RESERVED62[4]; + __IO uint32_t DOEPTSIZ3; + __IO uint32_t DOEPDMA3; + uint8_t RESERVED63[8]; + __IO uint32_t DOEPCTL4; + uint8_t RESERVED64[4]; + __IO uint32_t DOEPINT4; + uint8_t RESERVED65[4]; + __IO uint32_t DOEPTSIZ4; + __IO uint32_t DOEPDMA4; + uint8_t RESERVED66[8]; + __IO uint32_t DOEPCTL5; + uint8_t RESERVED67[4]; + __IO uint32_t DOEPINT5; + uint8_t RESERVED68[4]; + __IO uint32_t DOEPTSIZ5; + __IO uint32_t DOEPDMA5; + uint8_t RESERVED69[584]; + __IO uint32_t GCCTL; +} CM_USBFS_TypeDef; + +/** + * @brief WDT + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t SR; + __IO uint32_t RR; +} CM_WDT_TypeDef; + +/******************************************************************************/ +/* Memory Base Address */ +/******************************************************************************/ +#define EFM_BASE (0x00000000UL) /*!< EFM base address in the alias region */ +#define SRAM_BASE (0x1FFF8000UL) /*!< SRAM base address in the alias region */ +#define QSPI_BASE (0x98000000UL) /*!< QSPI base address in the alias region */ + +/******************************************************************************/ +/* Device Specific Peripheral Base Address */ +/******************************************************************************/ +#define CM_ADC1_BASE (0x40040000UL) +#define CM_ADC2_BASE (0x40040400UL) +#define CM_AES_BASE (0x40008000UL) +#define CM_AOS_BASE (0x40010800UL) +#define CM_CAN_BASE (0x40070400UL) +#define CM_CMP1_BASE (0x4004A000UL) +#define CM_CMP2_BASE (0x4004A010UL) +#define CM_CMP3_BASE (0x4004A020UL) +#define CM_CMP_COMMON_BASE (0x4004A000UL) +#define CM_CMU_BASE (0x40054000UL) +#define CM_CRC_BASE (0x40008C00UL) +#define CM_DBGC_BASE (0xE0042000UL) +#define CM_DCU1_BASE (0x40052000UL) +#define CM_DCU2_BASE (0x40052400UL) +#define CM_DCU3_BASE (0x40052800UL) +#define CM_DCU4_BASE (0x40052C00UL) +#define CM_DMA1_BASE (0x40053000UL) +#define CM_DMA2_BASE (0x40053400UL) +#define CM_EFM_BASE (0x40010400UL) +#define CM_EMB0_BASE (0x40017C00UL) +#define CM_EMB1_BASE (0x40017C20UL) +#define CM_EMB2_BASE (0x40017C40UL) +#define CM_EMB3_BASE (0x40017C60UL) +#define CM_FCM_BASE (0x40048400UL) +#define CM_GPIO_BASE (0x40053800UL) +#define CM_HASH_BASE (0x40008400UL) +#define CM_I2C1_BASE (0x4004E000UL) +#define CM_I2C2_BASE (0x4004E400UL) +#define CM_I2C3_BASE (0x4004E800UL) +#define CM_I2S1_BASE (0x4001E000UL) +#define CM_I2S2_BASE (0x4001E400UL) +#define CM_I2S3_BASE (0x40022000UL) +#define CM_I2S4_BASE (0x40022400UL) +#define CM_ICG_BASE (0x00000400UL) +#define CM_INTC_BASE (0x40051000UL) +#define CM_KEYSCAN_BASE (0x40050C00UL) +#define CM_MPU_BASE (0x40050000UL) +#define CM_OTS_BASE (0x4004A400UL) +#define CM_PERIC_BASE (0x40055400UL) +#define CM_PWC_BASE (0x40048000UL) +#define CM_QSPI_BASE (0x9C000000UL) +#define CM_RMU_BASE (0x400540C0UL) +#define CM_RTC_BASE (0x4004C000UL) +#define CM_SDIOC1_BASE (0x4006FC00UL) +#define CM_SDIOC2_BASE (0x40070000UL) +#define CM_SPI1_BASE (0x4001C000UL) +#define CM_SPI2_BASE (0x4001C400UL) +#define CM_SPI3_BASE (0x40020000UL) +#define CM_SPI4_BASE (0x40020400UL) +#define CM_SRAMC_BASE (0x40050800UL) +#define CM_SWDT_BASE (0x40049400UL) +#define CM_TMR0_1_BASE (0x40024000UL) +#define CM_TMR0_2_BASE (0x40024400UL) +#define CM_TMR4_1_BASE (0x40017000UL) +#define CM_TMR4_2_BASE (0x40024800UL) +#define CM_TMR4_3_BASE (0x40024C00UL) +#define CM_TMR4_ECER_BASE (0x40055408UL) +#define CM_TMR6_1_BASE (0x40018000UL) +#define CM_TMR6_2_BASE (0x40018400UL) +#define CM_TMR6_3_BASE (0x40018800UL) +#define CM_TMR6_COMMON_BASE (0x40018300UL) +#define CM_TMRA_1_BASE (0x40015000UL) +#define CM_TMRA_2_BASE (0x40015400UL) +#define CM_TMRA_3_BASE (0x40015800UL) +#define CM_TMRA_4_BASE (0x40015C00UL) +#define CM_TMRA_5_BASE (0x40016000UL) +#define CM_TMRA_6_BASE (0x40016400UL) +#define CM_TRNG_BASE (0x40041000UL) +#define CM_USART1_BASE (0x4001D000UL) +#define CM_USART2_BASE (0x4001D400UL) +#define CM_USART3_BASE (0x40021000UL) +#define CM_USART4_BASE (0x40021400UL) +#define CM_USBFS_BASE (0x400C0000UL) +#define CM_WDT_BASE (0x40049000UL) + +/******************************************************************************/ +/* Device Specific Peripheral declaration & memory map */ +/******************************************************************************/ +#define CM_ADC1 ((CM_ADC_TypeDef *)CM_ADC1_BASE) +#define CM_ADC2 ((CM_ADC_TypeDef *)CM_ADC2_BASE) +#define CM_AES ((CM_AES_TypeDef *)CM_AES_BASE) +#define CM_AOS ((CM_AOS_TypeDef *)CM_AOS_BASE) +#define CM_CAN ((CM_CAN_TypeDef *)CM_CAN_BASE) +#define CM_CMP1 ((CM_CMP_TypeDef *)CM_CMP1_BASE) +#define CM_CMP2 ((CM_CMP_TypeDef *)CM_CMP2_BASE) +#define CM_CMP3 ((CM_CMP_TypeDef *)CM_CMP3_BASE) +#define CM_CMP_COMMON ((CM_CMP_COMMON_TypeDef *)CM_CMP_COMMON_BASE) +#define CM_CMU ((CM_CMU_TypeDef *)CM_CMU_BASE) +#define CM_CRC ((CM_CRC_TypeDef *)CM_CRC_BASE) +#define CM_DBGC ((CM_DBGC_TypeDef *)CM_DBGC_BASE) +#define CM_DCU1 ((CM_DCU_TypeDef *)CM_DCU1_BASE) +#define CM_DCU2 ((CM_DCU_TypeDef *)CM_DCU2_BASE) +#define CM_DCU3 ((CM_DCU_TypeDef *)CM_DCU3_BASE) +#define CM_DCU4 ((CM_DCU_TypeDef *)CM_DCU4_BASE) +#define CM_DMA1 ((CM_DMA_TypeDef *)CM_DMA1_BASE) +#define CM_DMA2 ((CM_DMA_TypeDef *)CM_DMA2_BASE) +#define CM_EFM ((CM_EFM_TypeDef *)CM_EFM_BASE) +#define CM_EMB0 ((CM_EMB_TypeDef *)CM_EMB0_BASE) +#define CM_EMB1 ((CM_EMB_TypeDef *)CM_EMB1_BASE) +#define CM_EMB2 ((CM_EMB_TypeDef *)CM_EMB2_BASE) +#define CM_EMB3 ((CM_EMB_TypeDef *)CM_EMB3_BASE) +#define CM_FCM ((CM_FCM_TypeDef *)CM_FCM_BASE) +#define CM_GPIO ((CM_GPIO_TypeDef *)CM_GPIO_BASE) +#define CM_HASH ((CM_HASH_TypeDef *)CM_HASH_BASE) +#define CM_I2C1 ((CM_I2C_TypeDef *)CM_I2C1_BASE) +#define CM_I2C2 ((CM_I2C_TypeDef *)CM_I2C2_BASE) +#define CM_I2C3 ((CM_I2C_TypeDef *)CM_I2C3_BASE) +#define CM_I2S1 ((CM_I2S_TypeDef *)CM_I2S1_BASE) +#define CM_I2S2 ((CM_I2S_TypeDef *)CM_I2S2_BASE) +#define CM_I2S3 ((CM_I2S_TypeDef *)CM_I2S3_BASE) +#define CM_I2S4 ((CM_I2S_TypeDef *)CM_I2S4_BASE) +#define CM_ICG ((CM_ICG_TypeDef *)CM_ICG_BASE) +#define CM_INTC ((CM_INTC_TypeDef *)CM_INTC_BASE) +#define CM_KEYSCAN ((CM_KEYSCAN_TypeDef *)CM_KEYSCAN_BASE) +#define CM_MPU ((CM_MPU_TypeDef *)CM_MPU_BASE) +#define CM_OTS ((CM_OTS_TypeDef *)CM_OTS_BASE) +#define CM_PERIC ((CM_PERIC_TypeDef *)CM_PERIC_BASE) +#define CM_PWC ((CM_PWC_TypeDef *)CM_PWC_BASE) +#define CM_QSPI ((CM_QSPI_TypeDef *)CM_QSPI_BASE) +#define CM_RMU ((CM_RMU_TypeDef *)CM_RMU_BASE) +#define CM_RTC ((CM_RTC_TypeDef *)CM_RTC_BASE) +#define CM_SDIOC1 ((CM_SDIOC_TypeDef *)CM_SDIOC1_BASE) +#define CM_SDIOC2 ((CM_SDIOC_TypeDef *)CM_SDIOC2_BASE) +#define CM_SPI1 ((CM_SPI_TypeDef *)CM_SPI1_BASE) +#define CM_SPI2 ((CM_SPI_TypeDef *)CM_SPI2_BASE) +#define CM_SPI3 ((CM_SPI_TypeDef *)CM_SPI3_BASE) +#define CM_SPI4 ((CM_SPI_TypeDef *)CM_SPI4_BASE) +#define CM_SRAMC ((CM_SRAMC_TypeDef *)CM_SRAMC_BASE) +#define CM_SWDT ((CM_SWDT_TypeDef *)CM_SWDT_BASE) +#define CM_TMR0_1 ((CM_TMR0_TypeDef *)CM_TMR0_1_BASE) +#define CM_TMR0_2 ((CM_TMR0_TypeDef *)CM_TMR0_2_BASE) +#define CM_TMR4_1 ((CM_TMR4_TypeDef *)CM_TMR4_1_BASE) +#define CM_TMR4_2 ((CM_TMR4_TypeDef *)CM_TMR4_2_BASE) +#define CM_TMR4_3 ((CM_TMR4_TypeDef *)CM_TMR4_3_BASE) +#define CM_TMR4_ECER ((CM_TMR4_ECER_TypeDef *)CM_TMR4_ECER_BASE) +#define CM_TMR6_1 ((CM_TMR6_TypeDef *)CM_TMR6_1_BASE) +#define CM_TMR6_2 ((CM_TMR6_TypeDef *)CM_TMR6_2_BASE) +#define CM_TMR6_3 ((CM_TMR6_TypeDef *)CM_TMR6_3_BASE) +#define CM_TMR6_COMMON ((CM_TMR6_COMMON_TypeDef *)CM_TMR6_COMMON_BASE) +#define CM_TMRA_1 ((CM_TMRA_TypeDef *)CM_TMRA_1_BASE) +#define CM_TMRA_2 ((CM_TMRA_TypeDef *)CM_TMRA_2_BASE) +#define CM_TMRA_3 ((CM_TMRA_TypeDef *)CM_TMRA_3_BASE) +#define CM_TMRA_4 ((CM_TMRA_TypeDef *)CM_TMRA_4_BASE) +#define CM_TMRA_5 ((CM_TMRA_TypeDef *)CM_TMRA_5_BASE) +#define CM_TMRA_6 ((CM_TMRA_TypeDef *)CM_TMRA_6_BASE) +#define CM_TRNG ((CM_TRNG_TypeDef *)CM_TRNG_BASE) +#define CM_USART1 ((CM_USART_TypeDef *)CM_USART1_BASE) +#define CM_USART2 ((CM_USART_TypeDef *)CM_USART2_BASE) +#define CM_USART3 ((CM_USART_TypeDef *)CM_USART3_BASE) +#define CM_USART4 ((CM_USART_TypeDef *)CM_USART4_BASE) +#define CM_USBFS ((CM_USBFS_TypeDef *)CM_USBFS_BASE) +#define CM_WDT ((CM_WDT_TypeDef *)CM_WDT_BASE) + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************* + Bit definition for Peripheral ADC +*******************************************************************************/ +/* Bit definition for ADC_STR register */ +#define ADC_STR_STRT (0x01U) + +/* Bit definition for ADC_CR0 register */ +#define ADC_CR0_MS_POS (0U) +#define ADC_CR0_MS (0x0003U) +#define ADC_CR0_MS_0 (0x0001U) +#define ADC_CR0_MS_1 (0x0002U) +#define ADC_CR0_ACCSEL_POS (4U) +#define ADC_CR0_ACCSEL (0x0030U) +#define ADC_CR0_ACCSEL_0 (0x0010U) +#define ADC_CR0_ACCSEL_1 (0x0020U) +#define ADC_CR0_CLREN_POS (6U) +#define ADC_CR0_CLREN (0x0040U) +#define ADC_CR0_DFMT_POS (7U) +#define ADC_CR0_DFMT (0x0080U) +#define ADC_CR0_AVCNT_POS (8U) +#define ADC_CR0_AVCNT (0x0700U) + +/* Bit definition for ADC_CR1 register */ +#define ADC_CR1_RSCHSEL_POS (2U) +#define ADC_CR1_RSCHSEL (0x0004U) + +/* Bit definition for ADC_TRGSR register */ +#define ADC_TRGSR_TRGSELA_POS (0U) +#define ADC_TRGSR_TRGSELA (0x0003U) +#define ADC_TRGSR_TRGSELA_0 (0x0001U) +#define ADC_TRGSR_TRGSELA_1 (0x0002U) +#define ADC_TRGSR_TRGENA_POS (7U) +#define ADC_TRGSR_TRGENA (0x0080U) +#define ADC_TRGSR_TRGSELB_POS (8U) +#define ADC_TRGSR_TRGSELB (0x0300U) +#define ADC_TRGSR_TRGSELB_0 (0x0100U) +#define ADC_TRGSR_TRGSELB_1 (0x0200U) +#define ADC_TRGSR_TRGENB_POS (15U) +#define ADC_TRGSR_TRGENB (0x8000U) + +/* Bit definition for ADC_CHSELRA register */ +#define ADC_CHSELRA_CHSELA (0x0001FFFFUL) + +/* Bit definition for ADC_CHSELRB register */ +#define ADC_CHSELRB_CHSELB (0x0001FFFFUL) + +/* Bit definition for ADC_AVCHSELR register */ +#define ADC_AVCHSELR_AVCHSEL (0x0001FFFFUL) + +/* Bit definition for ADC_SSTR0 register */ +#define ADC_SSTR0 (0xFFU) + +/* Bit definition for ADC_SSTR1 register */ +#define ADC_SSTR1 (0xFFU) + +/* Bit definition for ADC_SSTR2 register */ +#define ADC_SSTR2 (0xFFU) + +/* Bit definition for ADC_SSTR3 register */ +#define ADC_SSTR3 (0xFFU) + +/* Bit definition for ADC_SSTR4 register */ +#define ADC_SSTR4 (0xFFU) + +/* Bit definition for ADC_SSTR5 register */ +#define ADC_SSTR5 (0xFFU) + +/* Bit definition for ADC_SSTR6 register */ +#define ADC_SSTR6 (0xFFU) + +/* Bit definition for ADC_SSTR7 register */ +#define ADC_SSTR7 (0xFFU) + +/* Bit definition for ADC_SSTR8 register */ +#define ADC_SSTR8 (0xFFU) + +/* Bit definition for ADC_SSTR9 register */ +#define ADC_SSTR9 (0xFFU) + +/* Bit definition for ADC_SSTR10 register */ +#define ADC_SSTR10 (0xFFU) + +/* Bit definition for ADC_SSTR11 register */ +#define ADC_SSTR11 (0xFFU) + +/* Bit definition for ADC_SSTR12 register */ +#define ADC_SSTR12 (0xFFU) + +/* Bit definition for ADC_SSTR13 register */ +#define ADC_SSTR13 (0xFFU) + +/* Bit definition for ADC_SSTR14 register */ +#define ADC_SSTR14 (0xFFU) + +/* Bit definition for ADC_SSTR15 register */ +#define ADC_SSTR15 (0xFFU) + +/* Bit definition for ADC_SSTRL register */ +#define ADC_SSTRL (0xFFU) + +/* Bit definition for ADC_CHMUXR0 register */ +#define ADC_CHMUXR0_CH00MUX_POS (0U) +#define ADC_CHMUXR0_CH00MUX (0x000FU) +#define ADC_CHMUXR0_CH01MUX_POS (4U) +#define ADC_CHMUXR0_CH01MUX (0x00F0U) +#define ADC_CHMUXR0_CH02MUX_POS (8U) +#define ADC_CHMUXR0_CH02MUX (0x0F00U) +#define ADC_CHMUXR0_CH03MUX_POS (12U) +#define ADC_CHMUXR0_CH03MUX (0xF000U) + +/* Bit definition for ADC_CHMUXR1 register */ +#define ADC_CHMUXR1_CH04MUX_POS (0U) +#define ADC_CHMUXR1_CH04MUX (0x000FU) +#define ADC_CHMUXR1_CH05MUX_POS (4U) +#define ADC_CHMUXR1_CH05MUX (0x00F0U) +#define ADC_CHMUXR1_CH06MUX_POS (8U) +#define ADC_CHMUXR1_CH06MUX (0x0F00U) +#define ADC_CHMUXR1_CH07MUX_POS (12U) +#define ADC_CHMUXR1_CH07MUX (0xF000U) + +/* Bit definition for ADC_CHMUXR2 register */ +#define ADC_CHMUXR2_CH08MUX_POS (0U) +#define ADC_CHMUXR2_CH08MUX (0x000FU) +#define ADC_CHMUXR2_CH09MUX_POS (4U) +#define ADC_CHMUXR2_CH09MUX (0x00F0U) +#define ADC_CHMUXR2_CH10MUX_POS (8U) +#define ADC_CHMUXR2_CH10MUX (0x0F00U) +#define ADC_CHMUXR2_CH11MUX_POS (12U) +#define ADC_CHMUXR2_CH11MUX (0xF000U) + +/* Bit definition for ADC_CHMUXR3 register */ +#define ADC_CHMUXR3_CH12MUX_POS (0U) +#define ADC_CHMUXR3_CH12MUX (0x000FU) +#define ADC_CHMUXR3_CH13MUX_POS (4U) +#define ADC_CHMUXR3_CH13MUX (0x00F0U) +#define ADC_CHMUXR3_CH14MUX_POS (8U) +#define ADC_CHMUXR3_CH14MUX (0x0F00U) +#define ADC_CHMUXR3_CH15MUX_POS (12U) +#define ADC_CHMUXR3_CH15MUX (0xF000U) + +/* Bit definition for ADC_ISR register */ +#define ADC_ISR_EOCAF_POS (0U) +#define ADC_ISR_EOCAF (0x01U) +#define ADC_ISR_EOCBF_POS (1U) +#define ADC_ISR_EOCBF (0x02U) + +/* Bit definition for ADC_ICR register */ +#define ADC_ICR_EOCAIEN_POS (0U) +#define ADC_ICR_EOCAIEN (0x01U) +#define ADC_ICR_EOCBIEN_POS (1U) +#define ADC_ICR_EOCBIEN (0x02U) + +/* Bit definition for ADC_SYNCCR register */ +#define ADC_SYNCCR_SYNCEN_POS (0U) +#define ADC_SYNCCR_SYNCEN (0x0001U) +#define ADC_SYNCCR_SYNCMD_POS (4U) +#define ADC_SYNCCR_SYNCMD (0x0070U) +#define ADC_SYNCCR_SYNCDLY_POS (8U) +#define ADC_SYNCCR_SYNCDLY (0xFF00U) + +/* Bit definition for ADC_DR0 register */ +#define ADC_DR0 (0xFFFFU) + +/* Bit definition for ADC_DR1 register */ +#define ADC_DR1 (0xFFFFU) + +/* Bit definition for ADC_DR2 register */ +#define ADC_DR2 (0xFFFFU) + +/* Bit definition for ADC_DR3 register */ +#define ADC_DR3 (0xFFFFU) + +/* Bit definition for ADC_DR4 register */ +#define ADC_DR4 (0xFFFFU) + +/* Bit definition for ADC_DR5 register */ +#define ADC_DR5 (0xFFFFU) + +/* Bit definition for ADC_DR6 register */ +#define ADC_DR6 (0xFFFFU) + +/* Bit definition for ADC_DR7 register */ +#define ADC_DR7 (0xFFFFU) + +/* Bit definition for ADC_DR8 register */ +#define ADC_DR8 (0xFFFFU) + +/* Bit definition for ADC_DR9 register */ +#define ADC_DR9 (0xFFFFU) + +/* Bit definition for ADC_DR10 register */ +#define ADC_DR10 (0xFFFFU) + +/* Bit definition for ADC_DR11 register */ +#define ADC_DR11 (0xFFFFU) + +/* Bit definition for ADC_DR12 register */ +#define ADC_DR12 (0xFFFFU) + +/* Bit definition for ADC_DR13 register */ +#define ADC_DR13 (0xFFFFU) + +/* Bit definition for ADC_DR14 register */ +#define ADC_DR14 (0xFFFFU) + +/* Bit definition for ADC_DR15 register */ +#define ADC_DR15 (0xFFFFU) + +/* Bit definition for ADC_DR16 register */ +#define ADC_DR16 (0xFFFFU) + +/* Bit definition for ADC_AWDCR register */ +#define ADC_AWDCR_AWDEN_POS (0U) +#define ADC_AWDCR_AWDEN (0x0001U) +#define ADC_AWDCR_AWDMD_POS (4U) +#define ADC_AWDCR_AWDMD (0x0010U) +#define ADC_AWDCR_AWDSS_POS (6U) +#define ADC_AWDCR_AWDSS (0x00C0U) +#define ADC_AWDCR_AWDSS_0 (0x0040U) +#define ADC_AWDCR_AWDSS_1 (0x0080U) +#define ADC_AWDCR_AWDIEN_POS (8U) +#define ADC_AWDCR_AWDIEN (0x0100U) + +/* Bit definition for ADC_AWDDR0 register */ +#define ADC_AWDDR0 (0xFFFFU) + +/* Bit definition for ADC_AWDDR1 register */ +#define ADC_AWDDR1 (0xFFFFU) + +/* Bit definition for ADC_AWDCHSR register */ +#define ADC_AWDCHSR_AWDCH (0x0001FFFFUL) + +/* Bit definition for ADC_AWDSR register */ +#define ADC_AWDSR_AWDF (0x0001FFFFUL) + +/* Bit definition for ADC_PGACR register */ +#define ADC_PGACR_PGACTL (0x000FU) + +/* Bit definition for ADC_PGAGSR register */ +#define ADC_PGAGSR_GAIN (0x000FU) + +/* Bit definition for ADC_PGAINSR0 register */ +#define ADC_PGAINSR0_PGAINSEL (0x01FFU) +#define ADC_PGAINSR0_PGAINSEL_0 (0x0001U) +#define ADC_PGAINSR0_PGAINSEL_1 (0x0002U) +#define ADC_PGAINSR0_PGAINSEL_2 (0x0004U) +#define ADC_PGAINSR0_PGAINSEL_3 (0x0008U) +#define ADC_PGAINSR0_PGAINSEL_4 (0x0010U) +#define ADC_PGAINSR0_PGAINSEL_5 (0x0020U) +#define ADC_PGAINSR0_PGAINSEL_6 (0x0040U) +#define ADC_PGAINSR0_PGAINSEL_7 (0x0080U) +#define ADC_PGAINSR0_PGAINSEL_8 (0x0100U) + +/* Bit definition for ADC_PGAINSR1 register */ +#define ADC_PGAINSR1_PGAVSSEN (0x0001U) + +/******************************************************************************* + Bit definition for Peripheral AES +*******************************************************************************/ +/* Bit definition for AES_CR register */ +#define AES_CR_START_POS (0U) +#define AES_CR_START (0x00000001UL) +#define AES_CR_MODE_POS (1U) +#define AES_CR_MODE (0x00000002UL) + +/* Bit definition for AES_DR0 register */ +#define AES_DR0 (0xFFFFFFFFUL) + +/* Bit definition for AES_DR1 register */ +#define AES_DR1 (0xFFFFFFFFUL) + +/* Bit definition for AES_DR2 register */ +#define AES_DR2 (0xFFFFFFFFUL) + +/* Bit definition for AES_DR3 register */ +#define AES_DR3 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR0 register */ +#define AES_KR0 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR1 register */ +#define AES_KR1 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR2 register */ +#define AES_KR2 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR3 register */ +#define AES_KR3 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral AOS +*******************************************************************************/ +/* Bit definition for AOS_INTSFTTRG register */ +#define AOS_INTSFTTRG_STRG (0x00000001UL) + +/* Bit definition for AOS_DCU_TRGSEL register */ +#define AOS_DCU_TRGSEL_TRGSEL_POS (0U) +#define AOS_DCU_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DCU_TRGSEL_COMEN_POS (30U) +#define AOS_DCU_TRGSEL_COMEN (0xC0000000UL) +#define AOS_DCU_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_DCU_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_DMA1_TRGSEL register */ +#define AOS_DMA1_TRGSEL_TRGSEL_POS (0U) +#define AOS_DMA1_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DMA1_TRGSEL_COMEN_POS (30U) +#define AOS_DMA1_TRGSEL_COMEN (0xC0000000UL) +#define AOS_DMA1_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_DMA1_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_DMA2_TRGSEL register */ +#define AOS_DMA2_TRGSEL_TRGSEL_POS (0U) +#define AOS_DMA2_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DMA2_TRGSEL_COMEN_POS (30U) +#define AOS_DMA2_TRGSEL_COMEN (0xC0000000UL) +#define AOS_DMA2_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_DMA2_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_DMA_RC_TRGSEL register */ +#define AOS_DMA_RC_TRGSEL_TRGSEL_POS (0U) +#define AOS_DMA_RC_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DMA_RC_TRGSEL_COMEN_POS (30U) +#define AOS_DMA_RC_TRGSEL_COMEN (0xC0000000UL) +#define AOS_DMA_RC_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_DMA_RC_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_TMR6_TRGSEL register */ +#define AOS_TMR6_TRGSEL_TRGSEL_POS (0U) +#define AOS_TMR6_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_TMR6_TRGSEL_COMEN_POS (30U) +#define AOS_TMR6_TRGSEL_COMEN (0xC0000000UL) +#define AOS_TMR6_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_TMR6_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_TMR0_TRGSEL register */ +#define AOS_TMR0_TRGSEL_TRGSEL_POS (0U) +#define AOS_TMR0_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_TMR0_TRGSEL_COMEN_POS (30U) +#define AOS_TMR0_TRGSEL_COMEN (0xC0000000UL) +#define AOS_TMR0_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_TMR0_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_PEVNT_TRGSEL register */ +#define AOS_PEVNT_TRGSEL_TRGSEL_POS (0U) +#define AOS_PEVNT_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_PEVNT_TRGSEL_COMEN_POS (30U) +#define AOS_PEVNT_TRGSEL_COMEN (0xC0000000UL) +#define AOS_PEVNT_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_PEVNT_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_TMRA_TRGSEL register */ +#define AOS_TMRA_TRGSEL_TRGSEL_POS (0U) +#define AOS_TMRA_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_TMRA_TRGSEL_COMEN_POS (30U) +#define AOS_TMRA_TRGSEL_COMEN (0xC0000000UL) +#define AOS_TMRA_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_TMRA_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_OTS_TRGSEL register */ +#define AOS_OTS_TRGSEL_TRGSEL_POS (0U) +#define AOS_OTS_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_OTS_TRGSEL_COMEN_POS (30U) +#define AOS_OTS_TRGSEL_COMEN (0xC0000000UL) +#define AOS_OTS_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_OTS_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_ADC1_TRGSEL register */ +#define AOS_ADC1_TRGSEL_TRGSEL_POS (0U) +#define AOS_ADC1_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_ADC1_TRGSEL_COMEN_POS (30U) +#define AOS_ADC1_TRGSEL_COMEN (0xC0000000UL) +#define AOS_ADC1_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_ADC1_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_ADC2_TRGSEL register */ +#define AOS_ADC2_TRGSEL_TRGSEL_POS (0U) +#define AOS_ADC2_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_ADC2_TRGSEL_COMEN_POS (30U) +#define AOS_ADC2_TRGSEL_COMEN (0xC0000000UL) +#define AOS_ADC2_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_ADC2_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_COMTRG1 register */ +#define AOS_COMTRG1_COMTRG (0x000001FFUL) + +/* Bit definition for AOS_COMTRG2 register */ +#define AOS_COMTRG2_COMTRG (0x000001FFUL) + +/* Bit definition for AOS_PEVNTDIRR register */ +#define AOS_PEVNTDIRR_PDIR (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTIDR register */ +#define AOS_PEVNTIDR_PIN (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTODR register */ +#define AOS_PEVNTODR_POUT (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTORR register */ +#define AOS_PEVNTORR_POR (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTOSR register */ +#define AOS_PEVNTOSR_POS (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTRISR register */ +#define AOS_PEVNTRISR_RIS (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTFALR register */ +#define AOS_PEVNTFALR_FAL (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTNFCR register */ +#define AOS_PEVNTNFCR_NFEN1_POS (0U) +#define AOS_PEVNTNFCR_NFEN1 (0x00000001UL) +#define AOS_PEVNTNFCR_DIVS1_POS (1U) +#define AOS_PEVNTNFCR_DIVS1 (0x00000006UL) +#define AOS_PEVNTNFCR_NFEN2_POS (8U) +#define AOS_PEVNTNFCR_NFEN2 (0x00000100UL) +#define AOS_PEVNTNFCR_DIVS2_POS (9U) +#define AOS_PEVNTNFCR_DIVS2 (0x00000600UL) +#define AOS_PEVNTNFCR_NFEN3_POS (16U) +#define AOS_PEVNTNFCR_NFEN3 (0x00010000UL) +#define AOS_PEVNTNFCR_DIVS3_POS (17U) +#define AOS_PEVNTNFCR_DIVS3 (0x00060000UL) +#define AOS_PEVNTNFCR_NFEN4_POS (24U) +#define AOS_PEVNTNFCR_NFEN4 (0x01000000UL) +#define AOS_PEVNTNFCR_DIVS4_POS (25U) +#define AOS_PEVNTNFCR_DIVS4 (0x06000000UL) + +/******************************************************************************* + Bit definition for Peripheral CAN +*******************************************************************************/ +/* Bit definition for CAN_RBUF register */ +#define CAN_RBUF (0xFFFFFFFFUL) + +/* Bit definition for CAN_TBUF register */ +#define CAN_TBUF (0xFFFFFFFFUL) + +/* Bit definition for CAN_CFG_STAT register */ +#define CAN_CFG_STAT_BUSOFF_POS (0U) +#define CAN_CFG_STAT_BUSOFF (0x01U) +#define CAN_CFG_STAT_TACTIVE_POS (1U) +#define CAN_CFG_STAT_TACTIVE (0x02U) +#define CAN_CFG_STAT_RACTIVE_POS (2U) +#define CAN_CFG_STAT_RACTIVE (0x04U) +#define CAN_CFG_STAT_TSSS_POS (3U) +#define CAN_CFG_STAT_TSSS (0x08U) +#define CAN_CFG_STAT_TPSS_POS (4U) +#define CAN_CFG_STAT_TPSS (0x10U) +#define CAN_CFG_STAT_LBMI_POS (5U) +#define CAN_CFG_STAT_LBMI (0x20U) +#define CAN_CFG_STAT_LBME_POS (6U) +#define CAN_CFG_STAT_LBME (0x40U) +#define CAN_CFG_STAT_RESET_POS (7U) +#define CAN_CFG_STAT_RESET (0x80U) + +/* Bit definition for CAN_TCMD register */ +#define CAN_TCMD_TSA_POS (0U) +#define CAN_TCMD_TSA (0x01U) +#define CAN_TCMD_TSALL_POS (1U) +#define CAN_TCMD_TSALL (0x02U) +#define CAN_TCMD_TSONE_POS (2U) +#define CAN_TCMD_TSONE (0x04U) +#define CAN_TCMD_TPA_POS (3U) +#define CAN_TCMD_TPA (0x08U) +#define CAN_TCMD_TPE_POS (4U) +#define CAN_TCMD_TPE (0x10U) +#define CAN_TCMD_LOM_POS (6U) +#define CAN_TCMD_LOM (0x40U) +#define CAN_TCMD_TBSEL_POS (7U) +#define CAN_TCMD_TBSEL (0x80U) + +/* Bit definition for CAN_TCTRL register */ +#define CAN_TCTRL_TSSTAT_POS (0U) +#define CAN_TCTRL_TSSTAT (0x03U) +#define CAN_TCTRL_TSSTAT_0 (0x01U) +#define CAN_TCTRL_TSSTAT_1 (0x02U) +#define CAN_TCTRL_TTTBM_POS (4U) +#define CAN_TCTRL_TTTBM (0x10U) +#define CAN_TCTRL_TSMODE_POS (5U) +#define CAN_TCTRL_TSMODE (0x20U) +#define CAN_TCTRL_TSNEXT_POS (6U) +#define CAN_TCTRL_TSNEXT (0x40U) + +/* Bit definition for CAN_RCTRL register */ +#define CAN_RCTRL_RSTAT_POS (0U) +#define CAN_RCTRL_RSTAT (0x03U) +#define CAN_RCTRL_RSTAT_0 (0x01U) +#define CAN_RCTRL_RSTAT_1 (0x02U) +#define CAN_RCTRL_RBALL_POS (3U) +#define CAN_RCTRL_RBALL (0x08U) +#define CAN_RCTRL_RREL_POS (4U) +#define CAN_RCTRL_RREL (0x10U) +#define CAN_RCTRL_ROV_POS (5U) +#define CAN_RCTRL_ROV (0x20U) +#define CAN_RCTRL_ROM_POS (6U) +#define CAN_RCTRL_ROM (0x40U) +#define CAN_RCTRL_SACK_POS (7U) +#define CAN_RCTRL_SACK (0x80U) + +/* Bit definition for CAN_RTIE register */ +#define CAN_RTIE_TSFF_POS (0U) +#define CAN_RTIE_TSFF (0x01U) +#define CAN_RTIE_EIE_POS (1U) +#define CAN_RTIE_EIE (0x02U) +#define CAN_RTIE_TSIE_POS (2U) +#define CAN_RTIE_TSIE (0x04U) +#define CAN_RTIE_TPIE_POS (3U) +#define CAN_RTIE_TPIE (0x08U) +#define CAN_RTIE_RAFIE_POS (4U) +#define CAN_RTIE_RAFIE (0x10U) +#define CAN_RTIE_RFIE_POS (5U) +#define CAN_RTIE_RFIE (0x20U) +#define CAN_RTIE_ROIE_POS (6U) +#define CAN_RTIE_ROIE (0x40U) +#define CAN_RTIE_RIE_POS (7U) +#define CAN_RTIE_RIE (0x80U) + +/* Bit definition for CAN_RTIF register */ +#define CAN_RTIF_AIF_POS (0U) +#define CAN_RTIF_AIF (0x01U) +#define CAN_RTIF_EIF_POS (1U) +#define CAN_RTIF_EIF (0x02U) +#define CAN_RTIF_TSIF_POS (2U) +#define CAN_RTIF_TSIF (0x04U) +#define CAN_RTIF_TPIF_POS (3U) +#define CAN_RTIF_TPIF (0x08U) +#define CAN_RTIF_RAFIF_POS (4U) +#define CAN_RTIF_RAFIF (0x10U) +#define CAN_RTIF_RFIF_POS (5U) +#define CAN_RTIF_RFIF (0x20U) +#define CAN_RTIF_ROIF_POS (6U) +#define CAN_RTIF_ROIF (0x40U) +#define CAN_RTIF_RIF_POS (7U) +#define CAN_RTIF_RIF (0x80U) + +/* Bit definition for CAN_ERRINT register */ +#define CAN_ERRINT_BEIF_POS (0U) +#define CAN_ERRINT_BEIF (0x01U) +#define CAN_ERRINT_BEIE_POS (1U) +#define CAN_ERRINT_BEIE (0x02U) +#define CAN_ERRINT_ALIF_POS (2U) +#define CAN_ERRINT_ALIF (0x04U) +#define CAN_ERRINT_ALIE_POS (3U) +#define CAN_ERRINT_ALIE (0x08U) +#define CAN_ERRINT_EPIF_POS (4U) +#define CAN_ERRINT_EPIF (0x10U) +#define CAN_ERRINT_EPIE_POS (5U) +#define CAN_ERRINT_EPIE (0x20U) +#define CAN_ERRINT_EPASS_POS (6U) +#define CAN_ERRINT_EPASS (0x40U) +#define CAN_ERRINT_EWARN_POS (7U) +#define CAN_ERRINT_EWARN (0x80U) + +/* Bit definition for CAN_LIMIT register */ +#define CAN_LIMIT_EWL_POS (0U) +#define CAN_LIMIT_EWL (0x0FU) +#define CAN_LIMIT_AFWL_POS (4U) +#define CAN_LIMIT_AFWL (0xF0U) + +/* Bit definition for CAN_SBT register */ +#define CAN_SBT_S_SEG_1_POS (0U) +#define CAN_SBT_S_SEG_1 (0x000000FFUL) +#define CAN_SBT_S_SEG_2_POS (8U) +#define CAN_SBT_S_SEG_2 (0x00007F00UL) +#define CAN_SBT_S_SJW_POS (16U) +#define CAN_SBT_S_SJW (0x007F0000UL) +#define CAN_SBT_S_PRESC_POS (24U) +#define CAN_SBT_S_PRESC (0xFF000000UL) + +/* Bit definition for CAN_EALCAP register */ +#define CAN_EALCAP_ALC_POS (0U) +#define CAN_EALCAP_ALC (0x1FU) +#define CAN_EALCAP_KOER_POS (5U) +#define CAN_EALCAP_KOER (0xE0U) + +/* Bit definition for CAN_RECNT register */ +#define CAN_RECNT (0xFFU) + +/* Bit definition for CAN_TECNT register */ +#define CAN_TECNT (0xFFU) + +/* Bit definition for CAN_ACFCTRL register */ +#define CAN_ACFCTRL_ACFADR_POS (0U) +#define CAN_ACFCTRL_ACFADR (0x0FU) +#define CAN_ACFCTRL_SELMASK_POS (5U) +#define CAN_ACFCTRL_SELMASK (0x20U) + +/* Bit definition for CAN_ACFEN register */ +#define CAN_ACFEN_AE_1_POS (0U) +#define CAN_ACFEN_AE_1 (0x01U) +#define CAN_ACFEN_AE_2_POS (1U) +#define CAN_ACFEN_AE_2 (0x02U) +#define CAN_ACFEN_AE_3_POS (2U) +#define CAN_ACFEN_AE_3 (0x04U) +#define CAN_ACFEN_AE_4_POS (3U) +#define CAN_ACFEN_AE_4 (0x08U) +#define CAN_ACFEN_AE_5_POS (4U) +#define CAN_ACFEN_AE_5 (0x10U) +#define CAN_ACFEN_AE_6_POS (5U) +#define CAN_ACFEN_AE_6 (0x20U) +#define CAN_ACFEN_AE_7_POS (6U) +#define CAN_ACFEN_AE_7 (0x40U) +#define CAN_ACFEN_AE_8_POS (7U) +#define CAN_ACFEN_AE_8 (0x80U) + +/* Bit definition for CAN_ACF register */ +#define CAN_ACF_ACODEORAMASK_POS (0U) +#define CAN_ACF_ACODEORAMASK (0x1FFFFFFFUL) +#define CAN_ACF_AIDE_POS (29U) +#define CAN_ACF_AIDE (0x20000000UL) +#define CAN_ACF_AIDEE_POS (30U) +#define CAN_ACF_AIDEE (0x40000000UL) + +/* Bit definition for CAN_TBSLOT register */ +#define CAN_TBSLOT_TBPTR_POS (0U) +#define CAN_TBSLOT_TBPTR (0x3FU) +#define CAN_TBSLOT_TBF_POS (6U) +#define CAN_TBSLOT_TBF (0x40U) +#define CAN_TBSLOT_TBE_POS (7U) +#define CAN_TBSLOT_TBE (0x80U) + +/* Bit definition for CAN_TTCFG register */ +#define CAN_TTCFG_TTEN_POS (0U) +#define CAN_TTCFG_TTEN (0x01U) +#define CAN_TTCFG_T_PRESC_POS (1U) +#define CAN_TTCFG_T_PRESC (0x06U) +#define CAN_TTCFG_T_PRESC_0 (0x02U) +#define CAN_TTCFG_T_PRESC_1 (0x04U) +#define CAN_TTCFG_TTIF_POS (3U) +#define CAN_TTCFG_TTIF (0x08U) +#define CAN_TTCFG_TTIE_POS (4U) +#define CAN_TTCFG_TTIE (0x10U) +#define CAN_TTCFG_TEIF_POS (5U) +#define CAN_TTCFG_TEIF (0x20U) +#define CAN_TTCFG_WTIF_POS (6U) +#define CAN_TTCFG_WTIF (0x40U) +#define CAN_TTCFG_WTIE_POS (7U) +#define CAN_TTCFG_WTIE (0x80U) + +/* Bit definition for CAN_REF_MSG register */ +#define CAN_REF_MSG_REF_ID_POS (0U) +#define CAN_REF_MSG_REF_ID (0x1FFFFFFFUL) +#define CAN_REF_MSG_REF_IDE_POS (31U) +#define CAN_REF_MSG_REF_IDE (0x80000000UL) + +/* Bit definition for CAN_TRG_CFG register */ +#define CAN_TRG_CFG_TTPTR_POS (0U) +#define CAN_TRG_CFG_TTPTR (0x003FU) +#define CAN_TRG_CFG_TTYPE_POS (8U) +#define CAN_TRG_CFG_TTYPE (0x0700U) +#define CAN_TRG_CFG_TTYPE_0 (0x0100U) +#define CAN_TRG_CFG_TTYPE_1 (0x0200U) +#define CAN_TRG_CFG_TTYPE_2 (0x0400U) +#define CAN_TRG_CFG_TEW_POS (12U) +#define CAN_TRG_CFG_TEW (0xF000U) + +/* Bit definition for CAN_TT_TRIG register */ +#define CAN_TT_TRIG (0xFFFFU) + +/* Bit definition for CAN_TT_WTRIG register */ +#define CAN_TT_WTRIG (0xFFFFU) + +/******************************************************************************* + Bit definition for Peripheral CMP +*******************************************************************************/ +/* Bit definition for CMP_CTRL register */ +#define CMP_CTRL_FLTSL_POS (0U) +#define CMP_CTRL_FLTSL (0x0007U) +#define CMP_CTRL_EDGSL_POS (5U) +#define CMP_CTRL_EDGSL (0x0060U) +#define CMP_CTRL_EDGSL_0 (0x0020U) +#define CMP_CTRL_EDGSL_1 (0x0040U) +#define CMP_CTRL_IEN_POS (7U) +#define CMP_CTRL_IEN (0x0080U) +#define CMP_CTRL_CVSEN_POS (8U) +#define CMP_CTRL_CVSEN (0x0100U) +#define CMP_CTRL_OUTEN_POS (12U) +#define CMP_CTRL_OUTEN (0x1000U) +#define CMP_CTRL_INV_POS (13U) +#define CMP_CTRL_INV (0x2000U) +#define CMP_CTRL_CMPOE_POS (14U) +#define CMP_CTRL_CMPOE (0x4000U) +#define CMP_CTRL_CMPON_POS (15U) +#define CMP_CTRL_CMPON (0x8000U) + +/* Bit definition for CMP_VLTSEL register */ +#define CMP_VLTSEL_RVSL_POS (0U) +#define CMP_VLTSEL_RVSL (0x000FU) +#define CMP_VLTSEL_RVSL_0 (0x0001U) +#define CMP_VLTSEL_RVSL_1 (0x0002U) +#define CMP_VLTSEL_RVSL_2 (0x0004U) +#define CMP_VLTSEL_RVSL_3 (0x0008U) +#define CMP_VLTSEL_CVSL_POS (8U) +#define CMP_VLTSEL_CVSL (0x0F00U) +#define CMP_VLTSEL_CVSL_0 (0x0100U) +#define CMP_VLTSEL_CVSL_1 (0x0200U) +#define CMP_VLTSEL_CVSL_2 (0x0400U) +#define CMP_VLTSEL_CVSL_3 (0x0800U) +#define CMP_VLTSEL_C4SL_POS (12U) +#define CMP_VLTSEL_C4SL (0x7000U) +#define CMP_VLTSEL_C4SL_0 (0x1000U) +#define CMP_VLTSEL_C4SL_1 (0x2000U) +#define CMP_VLTSEL_C4SL_2 (0x4000U) + +/* Bit definition for CMP_OUTMON register */ +#define CMP_OUTMON_OMON_POS (0U) +#define CMP_OUTMON_OMON (0x0001U) +#define CMP_OUTMON_CVST_POS (8U) +#define CMP_OUTMON_CVST (0x0F00U) + +/* Bit definition for CMP_CVSSTB register */ +#define CMP_CVSSTB_STB (0x000FU) + +/* Bit definition for CMP_CVSPRD register */ +#define CMP_CVSPRD_PRD (0x00FFU) + +/******************************************************************************* + Bit definition for Peripheral CMP_COMMON +*******************************************************************************/ +/* Bit definition for CMP_COMMON_DADR1 register */ +#define CMP_COMMON_DADR1_DATA (0x00FFU) + +/* Bit definition for CMP_COMMON_DADR2 register */ +#define CMP_COMMON_DADR2_DATA (0x00FFU) + +/* Bit definition for CMP_COMMON_DACR register */ +#define CMP_COMMON_DACR_DA1EN_POS (0U) +#define CMP_COMMON_DACR_DA1EN (0x0001U) +#define CMP_COMMON_DACR_DA2EN_POS (1U) +#define CMP_COMMON_DACR_DA2EN (0x0002U) + +/* Bit definition for CMP_COMMON_RVADC register */ +#define CMP_COMMON_RVADC_DA1SW_POS (0U) +#define CMP_COMMON_RVADC_DA1SW (0x0001U) +#define CMP_COMMON_RVADC_DA2SW_POS (1U) +#define CMP_COMMON_RVADC_DA2SW (0x0002U) +#define CMP_COMMON_RVADC_VREFSW_POS (4U) +#define CMP_COMMON_RVADC_VREFSW (0x0010U) +#define CMP_COMMON_RVADC_WPRT_POS (8U) +#define CMP_COMMON_RVADC_WPRT (0xFF00U) + +/******************************************************************************* + Bit definition for Peripheral CMU +*******************************************************************************/ +/* Bit definition for CMU_PERICKSEL register */ +#define CMU_PERICKSEL_PERICKSEL (0x000FU) + +/* Bit definition for CMU_I2SCKSEL register */ +#define CMU_I2SCKSEL_I2S1CKSEL_POS (0U) +#define CMU_I2SCKSEL_I2S1CKSEL (0x000FU) +#define CMU_I2SCKSEL_I2S2CKSEL_POS (4U) +#define CMU_I2SCKSEL_I2S2CKSEL (0x00F0U) +#define CMU_I2SCKSEL_I2S3CKSEL_POS (8U) +#define CMU_I2SCKSEL_I2S3CKSEL (0x0F00U) +#define CMU_I2SCKSEL_I2S4CKSEL_POS (12U) +#define CMU_I2SCKSEL_I2S4CKSEL (0xF000U) + +/* Bit definition for CMU_SCFGR register */ +#define CMU_SCFGR_PCLK0S_POS (0U) +#define CMU_SCFGR_PCLK0S (0x00000007UL) +#define CMU_SCFGR_PCLK1S_POS (4U) +#define CMU_SCFGR_PCLK1S (0x00000070UL) +#define CMU_SCFGR_PCLK2S_POS (8U) +#define CMU_SCFGR_PCLK2S (0x00000700UL) +#define CMU_SCFGR_PCLK3S_POS (12U) +#define CMU_SCFGR_PCLK3S (0x00007000UL) +#define CMU_SCFGR_PCLK4S_POS (16U) +#define CMU_SCFGR_PCLK4S (0x00070000UL) +#define CMU_SCFGR_EXCKS_POS (20U) +#define CMU_SCFGR_EXCKS (0x00700000UL) +#define CMU_SCFGR_HCLKS_POS (24U) +#define CMU_SCFGR_HCLKS (0x07000000UL) + +/* Bit definition for CMU_USBCKCFGR register */ +#define CMU_USBCKCFGR_USBCKS_POS (4U) +#define CMU_USBCKCFGR_USBCKS (0xF0U) + +/* Bit definition for CMU_CKSWR register */ +#define CMU_CKSWR_CKSW (0x07U) + +/* Bit definition for CMU_PLLCR register */ +#define CMU_PLLCR_MPLLOFF (0x01U) + +/* Bit definition for CMU_UPLLCR register */ +#define CMU_UPLLCR_UPLLOFF (0x01U) + +/* Bit definition for CMU_XTALCR register */ +#define CMU_XTALCR_XTALSTP (0x01U) + +/* Bit definition for CMU_HRCCR register */ +#define CMU_HRCCR_HRCSTP (0x01U) + +/* Bit definition for CMU_MRCCR register */ +#define CMU_MRCCR_MRCSTP (0x01U) + +/* Bit definition for CMU_OSCSTBSR register */ +#define CMU_OSCSTBSR_HRCSTBF_POS (0U) +#define CMU_OSCSTBSR_HRCSTBF (0x01U) +#define CMU_OSCSTBSR_XTALSTBF_POS (3U) +#define CMU_OSCSTBSR_XTALSTBF (0x08U) +#define CMU_OSCSTBSR_MPLLSTBF_POS (5U) +#define CMU_OSCSTBSR_MPLLSTBF (0x20U) +#define CMU_OSCSTBSR_UPLLSTBF_POS (6U) +#define CMU_OSCSTBSR_UPLLSTBF (0x40U) + +/* Bit definition for CMU_MCOCFGR register */ +#define CMU_MCOCFGR_MCOSEL_POS (0U) +#define CMU_MCOCFGR_MCOSEL (0x0FU) +#define CMU_MCOCFGR_MCODIV_POS (4U) +#define CMU_MCOCFGR_MCODIV (0x70U) +#define CMU_MCOCFGR_MCOEN_POS (7U) +#define CMU_MCOCFGR_MCOEN (0x80U) + +/* Bit definition for CMU_TPIUCKCFGR register */ +#define CMU_TPIUCKCFGR_TPIUCKS_POS (0U) +#define CMU_TPIUCKCFGR_TPIUCKS (0x03U) +#define CMU_TPIUCKCFGR_TPIUCKS_0 (0x01U) +#define CMU_TPIUCKCFGR_TPIUCKS_1 (0x02U) +#define CMU_TPIUCKCFGR_TPIUCKOE_POS (7U) +#define CMU_TPIUCKCFGR_TPIUCKOE (0x80U) + +/* Bit definition for CMU_XTALSTDCR register */ +#define CMU_XTALSTDCR_XTALSTDIE_POS (0U) +#define CMU_XTALSTDCR_XTALSTDIE (0x01U) +#define CMU_XTALSTDCR_XTALSTDRE_POS (1U) +#define CMU_XTALSTDCR_XTALSTDRE (0x02U) +#define CMU_XTALSTDCR_XTALSTDRIS_POS (2U) +#define CMU_XTALSTDCR_XTALSTDRIS (0x04U) +#define CMU_XTALSTDCR_XTALSTDE_POS (7U) +#define CMU_XTALSTDCR_XTALSTDE (0x80U) + +/* Bit definition for CMU_XTALSTDSR register */ +#define CMU_XTALSTDSR_XTALSTDF (0x01U) + +/* Bit definition for CMU_MRCTRM register */ +#define CMU_MRCTRM (0xFFU) + +/* Bit definition for CMU_HRCTRM register */ +#define CMU_HRCTRM (0xFFU) + +/* Bit definition for CMU_XTALSTBCR register */ +#define CMU_XTALSTBCR_XTALSTB (0x0FU) +#define CMU_XTALSTBCR_XTALSTB_0 (0x01U) +#define CMU_XTALSTBCR_XTALSTB_1 (0x02U) +#define CMU_XTALSTBCR_XTALSTB_2 (0x04U) +#define CMU_XTALSTBCR_XTALSTB_3 (0x08U) + +/* Bit definition for CMU_PLLCFGR register */ +#define CMU_PLLCFGR_MPLLM_POS (0U) +#define CMU_PLLCFGR_MPLLM (0x0000001FUL) +#define CMU_PLLCFGR_PLLSRC_POS (7U) +#define CMU_PLLCFGR_PLLSRC (0x00000080UL) +#define CMU_PLLCFGR_MPLLN_POS (8U) +#define CMU_PLLCFGR_MPLLN (0x0001FF00UL) +#define CMU_PLLCFGR_MPLLR_POS (20U) +#define CMU_PLLCFGR_MPLLR (0x00F00000UL) +#define CMU_PLLCFGR_MPLLQ_POS (24U) +#define CMU_PLLCFGR_MPLLQ (0x0F000000UL) +#define CMU_PLLCFGR_MPLLP_POS (28U) +#define CMU_PLLCFGR_MPLLP (0xF0000000UL) + +/* Bit definition for CMU_UPLLCFGR register */ +#define CMU_UPLLCFGR_UPLLM_POS (0U) +#define CMU_UPLLCFGR_UPLLM (0x0000001FUL) +#define CMU_UPLLCFGR_UPLLN_POS (8U) +#define CMU_UPLLCFGR_UPLLN (0x0001FF00UL) +#define CMU_UPLLCFGR_UPLLR_POS (20U) +#define CMU_UPLLCFGR_UPLLR (0x00F00000UL) +#define CMU_UPLLCFGR_UPLLQ_POS (24U) +#define CMU_UPLLCFGR_UPLLQ (0x0F000000UL) +#define CMU_UPLLCFGR_UPLLP_POS (28U) +#define CMU_UPLLCFGR_UPLLP (0xF0000000UL) + +/* Bit definition for CMU_XTALCFGR register */ +#define CMU_XTALCFGR_XTALDRV_POS (4U) +#define CMU_XTALCFGR_XTALDRV (0x30U) +#define CMU_XTALCFGR_XTALDRV_0 (0x10U) +#define CMU_XTALCFGR_XTALDRV_1 (0x20U) +#define CMU_XTALCFGR_XTALMS_POS (6U) +#define CMU_XTALCFGR_XTALMS (0x40U) +#define CMU_XTALCFGR_SUPDRV_POS (7U) +#define CMU_XTALCFGR_SUPDRV (0x80U) + +/* Bit definition for CMU_XTAL32CR register */ +#define CMU_XTAL32CR_XTAL32STP (0x01U) + +/* Bit definition for CMU_XTAL32CFGR register */ +#define CMU_XTAL32CFGR_XTAL32DRV (0x07U) +#define CMU_XTAL32CFGR_XTAL32DRV_0 (0x01U) +#define CMU_XTAL32CFGR_XTAL32DRV_1 (0x02U) +#define CMU_XTAL32CFGR_XTAL32DRV_2 (0x04U) + +/* Bit definition for CMU_XTAL32NFR register */ +#define CMU_XTAL32NFR_XTAL32NF (0x03U) +#define CMU_XTAL32NFR_XTAL32NF_0 (0x01U) +#define CMU_XTAL32NFR_XTAL32NF_1 (0x02U) + +/* Bit definition for CMU_LRCCR register */ +#define CMU_LRCCR_LRCSTP (0x01U) + +/* Bit definition for CMU_LRCTRM register */ +#define CMU_LRCTRM (0xFFU) + +/******************************************************************************* + Bit definition for Peripheral CRC +*******************************************************************************/ +/* Bit definition for CRC_CR register */ +#define CRC_CR_CR_POS (1U) +#define CRC_CR_CR (0x00000002UL) +#define CRC_CR_REFIN_POS (2U) +#define CRC_CR_REFIN (0x00000004UL) +#define CRC_CR_REFOUT_POS (3U) +#define CRC_CR_REFOUT (0x00000008UL) +#define CRC_CR_XOROUT_POS (4U) +#define CRC_CR_XOROUT (0x00000010UL) + +/* Bit definition for CRC_RESLT register */ +#define CRC_RESLT_CRC_REG_POS (0U) +#define CRC_RESLT_CRC_REG (0x0000FFFFUL) +#define CRC_RESLT_CRCFLAG_16_POS (16U) +#define CRC_RESLT_CRCFLAG_16 (0x00010000UL) + +/* Bit definition for CRC_FLG register */ +#define CRC_FLG_CRCFLAG_32 (0x00000001UL) + +/* Bit definition for CRC_DAT0 register */ +#define CRC_DAT0 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT1 register */ +#define CRC_DAT1 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT2 register */ +#define CRC_DAT2 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT3 register */ +#define CRC_DAT3 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT4 register */ +#define CRC_DAT4 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT5 register */ +#define CRC_DAT5 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT6 register */ +#define CRC_DAT6 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT7 register */ +#define CRC_DAT7 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT8 register */ +#define CRC_DAT8 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT9 register */ +#define CRC_DAT9 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT10 register */ +#define CRC_DAT10 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT11 register */ +#define CRC_DAT11 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT12 register */ +#define CRC_DAT12 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT13 register */ +#define CRC_DAT13 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT14 register */ +#define CRC_DAT14 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT15 register */ +#define CRC_DAT15 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT16 register */ +#define CRC_DAT16 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT17 register */ +#define CRC_DAT17 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT18 register */ +#define CRC_DAT18 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT19 register */ +#define CRC_DAT19 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT20 register */ +#define CRC_DAT20 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT21 register */ +#define CRC_DAT21 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT22 register */ +#define CRC_DAT22 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT23 register */ +#define CRC_DAT23 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT24 register */ +#define CRC_DAT24 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT25 register */ +#define CRC_DAT25 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT26 register */ +#define CRC_DAT26 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT27 register */ +#define CRC_DAT27 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT28 register */ +#define CRC_DAT28 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT29 register */ +#define CRC_DAT29 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT30 register */ +#define CRC_DAT30 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT31 register */ +#define CRC_DAT31 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral DBGC +*******************************************************************************/ +/* Bit definition for DBGC_MCUDBGSTAT register */ +#define DBGC_MCUDBGSTAT_CDBGPWRUPREQ_POS (0U) +#define DBGC_MCUDBGSTAT_CDBGPWRUPREQ (0x00000001UL) +#define DBGC_MCUDBGSTAT_CDBGPWRUPACK_POS (1U) +#define DBGC_MCUDBGSTAT_CDBGPWRUPACK (0x00000002UL) + +/* Bit definition for DBGC_MCUSTPCTL register */ +#define DBGC_MCUSTPCTL_SWDTSTP_POS (0U) +#define DBGC_MCUSTPCTL_SWDTSTP (0x00000001UL) +#define DBGC_MCUSTPCTL_WDTSTP_POS (1U) +#define DBGC_MCUSTPCTL_WDTSTP (0x00000002UL) +#define DBGC_MCUSTPCTL_RTCSTP_POS (2U) +#define DBGC_MCUSTPCTL_RTCSTP (0x00000004UL) +#define DBGC_MCUSTPCTL_TMR01STP_POS (14U) +#define DBGC_MCUSTPCTL_TMR01STP (0x00004000UL) +#define DBGC_MCUSTPCTL_TMR02STP_POS (15U) +#define DBGC_MCUSTPCTL_TMR02STP (0x00008000UL) +#define DBGC_MCUSTPCTL_TMR41STP_POS (20U) +#define DBGC_MCUSTPCTL_TMR41STP (0x00100000UL) +#define DBGC_MCUSTPCTL_TMR42STP_POS (21U) +#define DBGC_MCUSTPCTL_TMR42STP (0x00200000UL) +#define DBGC_MCUSTPCTL_TMR43STP_POS (22U) +#define DBGC_MCUSTPCTL_TMR43STP (0x00400000UL) +#define DBGC_MCUSTPCTL_TM61STP_POS (23U) +#define DBGC_MCUSTPCTL_TM61STP (0x00800000UL) +#define DBGC_MCUSTPCTL_TM62STP_POS (24U) +#define DBGC_MCUSTPCTL_TM62STP (0x01000000UL) +#define DBGC_MCUSTPCTL_TMR63STP_POS (25U) +#define DBGC_MCUSTPCTL_TMR63STP (0x02000000UL) +#define DBGC_MCUSTPCTL_TMRA1STP_POS (26U) +#define DBGC_MCUSTPCTL_TMRA1STP (0x04000000UL) +#define DBGC_MCUSTPCTL_TMRA2STP_POS (27U) +#define DBGC_MCUSTPCTL_TMRA2STP (0x08000000UL) +#define DBGC_MCUSTPCTL_TMRA3STP_POS (28U) +#define DBGC_MCUSTPCTL_TMRA3STP (0x10000000UL) +#define DBGC_MCUSTPCTL_TMRA4STP_POS (29U) +#define DBGC_MCUSTPCTL_TMRA4STP (0x20000000UL) +#define DBGC_MCUSTPCTL_TMRA5STP_POS (30U) +#define DBGC_MCUSTPCTL_TMRA5STP (0x40000000UL) +#define DBGC_MCUSTPCTL_TMRA6STP_POS (31U) +#define DBGC_MCUSTPCTL_TMRA6STP (0x80000000UL) + +/* Bit definition for DBGC_MCUTRACECTL register */ +#define DBGC_MCUTRACECTL_TRACEMODE_POS (0U) +#define DBGC_MCUTRACECTL_TRACEMODE (0x00000003UL) +#define DBGC_MCUTRACECTL_TRACEMODE_0 (0x00000001UL) +#define DBGC_MCUTRACECTL_TRACEMODE_1 (0x00000002UL) +#define DBGC_MCUTRACECTL_TRACEIOEN_POS (2U) +#define DBGC_MCUTRACECTL_TRACEIOEN (0x00000004UL) + +/******************************************************************************* + Bit definition for Peripheral DCU +*******************************************************************************/ +/* Bit definition for DCU_CTL register */ +#define DCU_CTL_MODE_POS (0U) +#define DCU_CTL_MODE (0x00000007UL) +#define DCU_CTL_DATASIZE_POS (3U) +#define DCU_CTL_DATASIZE (0x00000018UL) +#define DCU_CTL_DATASIZE_0 (0x00000008UL) +#define DCU_CTL_DATASIZE_1 (0x00000010UL) +#define DCU_CTL_COMPTRG_POS (8U) +#define DCU_CTL_COMPTRG (0x00000100UL) +#define DCU_CTL_INTEN_POS (31U) +#define DCU_CTL_INTEN (0x80000000UL) + +/* Bit definition for DCU_FLAG register */ +#define DCU_FLAG_FLAG_OP_POS (0U) +#define DCU_FLAG_FLAG_OP (0x00000001UL) +#define DCU_FLAG_FLAG_LS2_POS (1U) +#define DCU_FLAG_FLAG_LS2 (0x00000002UL) +#define DCU_FLAG_FLAG_EQ2_POS (2U) +#define DCU_FLAG_FLAG_EQ2 (0x00000004UL) +#define DCU_FLAG_FLAG_GT2_POS (3U) +#define DCU_FLAG_FLAG_GT2 (0x00000008UL) +#define DCU_FLAG_FLAG_LS1_POS (4U) +#define DCU_FLAG_FLAG_LS1 (0x00000010UL) +#define DCU_FLAG_FLAG_EQ1_POS (5U) +#define DCU_FLAG_FLAG_EQ1 (0x00000020UL) +#define DCU_FLAG_FLAG_GT1_POS (6U) +#define DCU_FLAG_FLAG_GT1 (0x00000040UL) + +/* Bit definition for DCU_DATA0 register */ +#define DCU_DATA0 (0xFFFFFFFFUL) + +/* Bit definition for DCU_DATA1 register */ +#define DCU_DATA1 (0xFFFFFFFFUL) + +/* Bit definition for DCU_DATA2 register */ +#define DCU_DATA2 (0xFFFFFFFFUL) + +/* Bit definition for DCU_FLAGCLR register */ +#define DCU_FLAGCLR_CLR_OP_POS (0U) +#define DCU_FLAGCLR_CLR_OP (0x00000001UL) +#define DCU_FLAGCLR_CLR_LS2_POS (1U) +#define DCU_FLAGCLR_CLR_LS2 (0x00000002UL) +#define DCU_FLAGCLR_CLR_EQ2_POS (2U) +#define DCU_FLAGCLR_CLR_EQ2 (0x00000004UL) +#define DCU_FLAGCLR_CLR_GT2_POS (3U) +#define DCU_FLAGCLR_CLR_GT2 (0x00000008UL) +#define DCU_FLAGCLR_CLR_LS1_POS (4U) +#define DCU_FLAGCLR_CLR_LS1 (0x00000010UL) +#define DCU_FLAGCLR_CLR_EQ1_POS (5U) +#define DCU_FLAGCLR_CLR_EQ1 (0x00000020UL) +#define DCU_FLAGCLR_CLR_GT1_POS (6U) +#define DCU_FLAGCLR_CLR_GT1 (0x00000040UL) + +/* Bit definition for DCU_INTEVTSEL register */ +#define DCU_INTEVTSEL_SEL_OP_POS (0U) +#define DCU_INTEVTSEL_SEL_OP (0x00000001UL) +#define DCU_INTEVTSEL_SEL_LS2_POS (1U) +#define DCU_INTEVTSEL_SEL_LS2 (0x00000002UL) +#define DCU_INTEVTSEL_SEL_EQ2_POS (2U) +#define DCU_INTEVTSEL_SEL_EQ2 (0x00000004UL) +#define DCU_INTEVTSEL_SEL_GT2_POS (3U) +#define DCU_INTEVTSEL_SEL_GT2 (0x00000008UL) +#define DCU_INTEVTSEL_SEL_LS1_POS (4U) +#define DCU_INTEVTSEL_SEL_LS1 (0x00000010UL) +#define DCU_INTEVTSEL_SEL_EQ1_POS (5U) +#define DCU_INTEVTSEL_SEL_EQ1 (0x00000020UL) +#define DCU_INTEVTSEL_SEL_GT1_POS (6U) +#define DCU_INTEVTSEL_SEL_GT1 (0x00000040UL) +#define DCU_INTEVTSEL_SEL_WIN_POS (7U) +#define DCU_INTEVTSEL_SEL_WIN (0x00000180UL) +#define DCU_INTEVTSEL_SEL_WIN_0 (0x00000080UL) +#define DCU_INTEVTSEL_SEL_WIN_1 (0x00000100UL) + +/******************************************************************************* + Bit definition for Peripheral DMA +*******************************************************************************/ +/* Bit definition for DMA_EN register */ +#define DMA_EN_EN (0x00000001UL) + +/* Bit definition for DMA_INTSTAT0 register */ +#define DMA_INTSTAT0_TRNERR_POS (0U) +#define DMA_INTSTAT0_TRNERR (0x0000000FUL) +#define DMA_INTSTAT0_TRNERR_0 (0x00000001UL) +#define DMA_INTSTAT0_TRNERR_1 (0x00000002UL) +#define DMA_INTSTAT0_TRNERR_2 (0x00000004UL) +#define DMA_INTSTAT0_TRNERR_3 (0x00000008UL) +#define DMA_INTSTAT0_REQERR_POS (16U) +#define DMA_INTSTAT0_REQERR (0x000F0000UL) +#define DMA_INTSTAT0_REQERR_0 (0x00010000UL) +#define DMA_INTSTAT0_REQERR_1 (0x00020000UL) +#define DMA_INTSTAT0_REQERR_2 (0x00040000UL) +#define DMA_INTSTAT0_REQERR_3 (0x00080000UL) + +/* Bit definition for DMA_INTSTAT1 register */ +#define DMA_INTSTAT1_TC_POS (0U) +#define DMA_INTSTAT1_TC (0x0000000FUL) +#define DMA_INTSTAT1_TC_0 (0x00000001UL) +#define DMA_INTSTAT1_TC_1 (0x00000002UL) +#define DMA_INTSTAT1_TC_2 (0x00000004UL) +#define DMA_INTSTAT1_TC_3 (0x00000008UL) +#define DMA_INTSTAT1_BTC_POS (16U) +#define DMA_INTSTAT1_BTC (0x000F0000UL) +#define DMA_INTSTAT1_BTC_0 (0x00010000UL) +#define DMA_INTSTAT1_BTC_1 (0x00020000UL) +#define DMA_INTSTAT1_BTC_2 (0x00040000UL) +#define DMA_INTSTAT1_BTC_3 (0x00080000UL) + +/* Bit definition for DMA_INTMASK0 register */ +#define DMA_INTMASK0_MSKTRNERR_POS (0U) +#define DMA_INTMASK0_MSKTRNERR (0x0000000FUL) +#define DMA_INTMASK0_MSKTRNERR_0 (0x00000001UL) +#define DMA_INTMASK0_MSKTRNERR_1 (0x00000002UL) +#define DMA_INTMASK0_MSKTRNERR_2 (0x00000004UL) +#define DMA_INTMASK0_MSKTRNERR_3 (0x00000008UL) +#define DMA_INTMASK0_MSKREQERR_POS (16U) +#define DMA_INTMASK0_MSKREQERR (0x000F0000UL) +#define DMA_INTMASK0_MSKREQERR_0 (0x00010000UL) +#define DMA_INTMASK0_MSKREQERR_1 (0x00020000UL) +#define DMA_INTMASK0_MSKREQERR_2 (0x00040000UL) +#define DMA_INTMASK0_MSKREQERR_3 (0x00080000UL) + +/* Bit definition for DMA_INTMASK1 register */ +#define DMA_INTMASK1_MSKTC_POS (0U) +#define DMA_INTMASK1_MSKTC (0x0000000FUL) +#define DMA_INTMASK1_MSKTC_0 (0x00000001UL) +#define DMA_INTMASK1_MSKTC_1 (0x00000002UL) +#define DMA_INTMASK1_MSKTC_2 (0x00000004UL) +#define DMA_INTMASK1_MSKTC_3 (0x00000008UL) +#define DMA_INTMASK1_MSKBTC_POS (16U) +#define DMA_INTMASK1_MSKBTC (0x000F0000UL) +#define DMA_INTMASK1_MSKBTC_0 (0x00010000UL) +#define DMA_INTMASK1_MSKBTC_1 (0x00020000UL) +#define DMA_INTMASK1_MSKBTC_2 (0x00040000UL) +#define DMA_INTMASK1_MSKBTC_3 (0x00080000UL) + +/* Bit definition for DMA_INTCLR0 register */ +#define DMA_INTCLR0_CLRTRNERR_POS (0U) +#define DMA_INTCLR0_CLRTRNERR (0x0000000FUL) +#define DMA_INTCLR0_CLRTRNERR_0 (0x00000001UL) +#define DMA_INTCLR0_CLRTRNERR_1 (0x00000002UL) +#define DMA_INTCLR0_CLRTRNERR_2 (0x00000004UL) +#define DMA_INTCLR0_CLRTRNERR_3 (0x00000008UL) +#define DMA_INTCLR0_CLRREQERR_POS (16U) +#define DMA_INTCLR0_CLRREQERR (0x000F0000UL) +#define DMA_INTCLR0_CLRREQERR_0 (0x00010000UL) +#define DMA_INTCLR0_CLRREQERR_1 (0x00020000UL) +#define DMA_INTCLR0_CLRREQERR_2 (0x00040000UL) +#define DMA_INTCLR0_CLRREQERR_3 (0x00080000UL) + +/* Bit definition for DMA_INTCLR1 register */ +#define DMA_INTCLR1_CLRTC_POS (0U) +#define DMA_INTCLR1_CLRTC (0x0000000FUL) +#define DMA_INTCLR1_CLRTC_0 (0x00000001UL) +#define DMA_INTCLR1_CLRTC_1 (0x00000002UL) +#define DMA_INTCLR1_CLRTC_2 (0x00000004UL) +#define DMA_INTCLR1_CLRTC_3 (0x00000008UL) +#define DMA_INTCLR1_CLRBTC_POS (16U) +#define DMA_INTCLR1_CLRBTC (0x000F0000UL) +#define DMA_INTCLR1_CLRBTC_0 (0x00010000UL) +#define DMA_INTCLR1_CLRBTC_1 (0x00020000UL) +#define DMA_INTCLR1_CLRBTC_2 (0x00040000UL) +#define DMA_INTCLR1_CLRBTC_3 (0x00080000UL) + +/* Bit definition for DMA_CHEN register */ +#define DMA_CHEN_CHEN (0x0000000FUL) +#define DMA_CHEN_CHEN_0 (0x00000001UL) +#define DMA_CHEN_CHEN_1 (0x00000002UL) +#define DMA_CHEN_CHEN_2 (0x00000004UL) +#define DMA_CHEN_CHEN_3 (0x00000008UL) + +/* Bit definition for DMA_REQSTAT register */ +#define DMA_REQSTAT_CHREQ_POS (0U) +#define DMA_REQSTAT_CHREQ (0x0000000FUL) +#define DMA_REQSTAT_CHREQ_0 (0x00000001UL) +#define DMA_REQSTAT_CHREQ_1 (0x00000002UL) +#define DMA_REQSTAT_CHREQ_2 (0x00000004UL) +#define DMA_REQSTAT_CHREQ_3 (0x00000008UL) +#define DMA_REQSTAT_RCFGREQ_POS (15U) +#define DMA_REQSTAT_RCFGREQ (0x00008000UL) + +/* Bit definition for DMA_CHSTAT register */ +#define DMA_CHSTAT_DMAACT_POS (0U) +#define DMA_CHSTAT_DMAACT (0x00000001UL) +#define DMA_CHSTAT_RCFGACT_POS (1U) +#define DMA_CHSTAT_RCFGACT (0x00000002UL) +#define DMA_CHSTAT_CHACT_POS (16U) +#define DMA_CHSTAT_CHACT (0x000F0000UL) +#define DMA_CHSTAT_CHACT_0 (0x00010000UL) +#define DMA_CHSTAT_CHACT_1 (0x00020000UL) +#define DMA_CHSTAT_CHACT_2 (0x00040000UL) +#define DMA_CHSTAT_CHACT_3 (0x00080000UL) + +/* Bit definition for DMA_RCFGCTL register */ +#define DMA_RCFGCTL_RCFGEN_POS (0U) +#define DMA_RCFGCTL_RCFGEN (0x00000001UL) +#define DMA_RCFGCTL_RCFGLLP_POS (1U) +#define DMA_RCFGCTL_RCFGLLP (0x00000002UL) +#define DMA_RCFGCTL_RCFGCHS_POS (8U) +#define DMA_RCFGCTL_RCFGCHS (0x00000F00UL) +#define DMA_RCFGCTL_RCFGCHS_0 (0x00000100UL) +#define DMA_RCFGCTL_RCFGCHS_1 (0x00000200UL) +#define DMA_RCFGCTL_RCFGCHS_2 (0x00000400UL) +#define DMA_RCFGCTL_RCFGCHS_3 (0x00000800UL) +#define DMA_RCFGCTL_SARMD_POS (16U) +#define DMA_RCFGCTL_SARMD (0x00030000UL) +#define DMA_RCFGCTL_SARMD_0 (0x00010000UL) +#define DMA_RCFGCTL_SARMD_1 (0x00020000UL) +#define DMA_RCFGCTL_DARMD_POS (18U) +#define DMA_RCFGCTL_DARMD (0x000C0000UL) +#define DMA_RCFGCTL_DARMD_0 (0x00040000UL) +#define DMA_RCFGCTL_DARMD_1 (0x00080000UL) +#define DMA_RCFGCTL_CNTMD_POS (20U) +#define DMA_RCFGCTL_CNTMD (0x00300000UL) +#define DMA_RCFGCTL_CNTMD_0 (0x00100000UL) +#define DMA_RCFGCTL_CNTMD_1 (0x00200000UL) + +/* Bit definition for DMA_SWREQ register */ +#define DMA_SWREQ_SWREQ_POS (0U) +#define DMA_SWREQ_SWREQ (0x000000FFUL) +#define DMA_SWREQ_SWREQ_0 (0x00000001UL) +#define DMA_SWREQ_SWREQ_1 (0x00000002UL) +#define DMA_SWREQ_SWREQ_2 (0x00000004UL) +#define DMA_SWREQ_SWREQ_3 (0x00000008UL) +#define DMA_SWREQ_SWREQ_4 (0x00000010UL) +#define DMA_SWREQ_SWREQ_5 (0x00000020UL) +#define DMA_SWREQ_SWREQ_6 (0x00000040UL) +#define DMA_SWREQ_SWREQ_7 (0x00000080UL) +#define DMA_SWREQ_SWRCFGREQ_POS (15U) +#define DMA_SWREQ_SWRCFGREQ (0x00008000UL) +#define DMA_SWREQ_SWREQWP_POS (16U) +#define DMA_SWREQ_SWREQWP (0x00FF0000UL) +#define DMA_SWREQ_SWRCFGWP_POS (24U) +#define DMA_SWREQ_SWRCFGWP (0xFF000000UL) + +/* Bit definition for DMA_SAR register */ +#define DMA_SAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_DAR register */ +#define DMA_DAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_DTCTL register */ +#define DMA_DTCTL_BLKSIZE_POS (0U) +#define DMA_DTCTL_BLKSIZE (0x000003FFUL) +#define DMA_DTCTL_CNT_POS (16U) +#define DMA_DTCTL_CNT (0xFFFF0000UL) + +/* Bit definition for DMA_RPT register */ +#define DMA_RPT_SRPT_POS (0U) +#define DMA_RPT_SRPT (0x000003FFUL) +#define DMA_RPT_DRPT_POS (16U) +#define DMA_RPT_DRPT (0x03FF0000UL) + +/* Bit definition for DMA_RPTB register */ +#define DMA_RPTB_SRPTB_POS (0U) +#define DMA_RPTB_SRPTB (0x000003FFUL) +#define DMA_RPTB_DRPTB_POS (16U) +#define DMA_RPTB_DRPTB (0x03FF0000UL) + +/* Bit definition for DMA_SNSEQCTL register */ +#define DMA_SNSEQCTL_SOFFSET_POS (0U) +#define DMA_SNSEQCTL_SOFFSET (0x000FFFFFUL) +#define DMA_SNSEQCTL_SNSCNT_POS (20U) +#define DMA_SNSEQCTL_SNSCNT (0xFFF00000UL) + +/* Bit definition for DMA_SNSEQCTLB register */ +#define DMA_SNSEQCTLB_SNSDIST_POS (0U) +#define DMA_SNSEQCTLB_SNSDIST (0x000FFFFFUL) +#define DMA_SNSEQCTLB_SNSCNTB_POS (20U) +#define DMA_SNSEQCTLB_SNSCNTB (0xFFF00000UL) + +/* Bit definition for DMA_DNSEQCTL register */ +#define DMA_DNSEQCTL_DOFFSET_POS (0U) +#define DMA_DNSEQCTL_DOFFSET (0x000FFFFFUL) +#define DMA_DNSEQCTL_DNSCNT_POS (20U) +#define DMA_DNSEQCTL_DNSCNT (0xFFF00000UL) + +/* Bit definition for DMA_DNSEQCTLB register */ +#define DMA_DNSEQCTLB_DNSDIST_POS (0U) +#define DMA_DNSEQCTLB_DNSDIST (0x000FFFFFUL) +#define DMA_DNSEQCTLB_DNSCNTB_POS (20U) +#define DMA_DNSEQCTLB_DNSCNTB (0xFFF00000UL) + +/* Bit definition for DMA_LLP register */ +#define DMA_LLP_LLP_POS (2U) +#define DMA_LLP_LLP (0xFFFFFFFCUL) + +/* Bit definition for DMA_CHCTL register */ +#define DMA_CHCTL_SINC_POS (0U) +#define DMA_CHCTL_SINC (0x00000003UL) +#define DMA_CHCTL_SINC_0 (0x00000001UL) +#define DMA_CHCTL_SINC_1 (0x00000002UL) +#define DMA_CHCTL_DINC_POS (2U) +#define DMA_CHCTL_DINC (0x0000000CUL) +#define DMA_CHCTL_DINC_0 (0x00000004UL) +#define DMA_CHCTL_DINC_1 (0x00000008UL) +#define DMA_CHCTL_SRPTEN_POS (4U) +#define DMA_CHCTL_SRPTEN (0x00000010UL) +#define DMA_CHCTL_DRPTEN_POS (5U) +#define DMA_CHCTL_DRPTEN (0x00000020UL) +#define DMA_CHCTL_SNSEQEN_POS (6U) +#define DMA_CHCTL_SNSEQEN (0x00000040UL) +#define DMA_CHCTL_DNSEQEN_POS (7U) +#define DMA_CHCTL_DNSEQEN (0x00000080UL) +#define DMA_CHCTL_HSIZE_POS (8U) +#define DMA_CHCTL_HSIZE (0x00000300UL) +#define DMA_CHCTL_HSIZE_0 (0x00000100UL) +#define DMA_CHCTL_HSIZE_1 (0x00000200UL) +#define DMA_CHCTL_LLPEN_POS (10U) +#define DMA_CHCTL_LLPEN (0x00000400UL) +#define DMA_CHCTL_LLPRUN_POS (11U) +#define DMA_CHCTL_LLPRUN (0x00000800UL) +#define DMA_CHCTL_IE_POS (12U) +#define DMA_CHCTL_IE (0x00001000UL) + +/* Bit definition for DMA_MONSAR register */ +#define DMA_MONSAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_MONDAR register */ +#define DMA_MONDAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_MONDTCTL register */ +#define DMA_MONDTCTL_BLKSIZE_POS (0U) +#define DMA_MONDTCTL_BLKSIZE (0x000003FFUL) +#define DMA_MONDTCTL_CNT_POS (16U) +#define DMA_MONDTCTL_CNT (0xFFFF0000UL) + +/* Bit definition for DMA_MONRPT register */ +#define DMA_MONRPT_SRPT_POS (0U) +#define DMA_MONRPT_SRPT (0x000003FFUL) +#define DMA_MONRPT_DRPT_POS (16U) +#define DMA_MONRPT_DRPT (0x03FF0000UL) + +/* Bit definition for DMA_MONSNSEQCTL register */ +#define DMA_MONSNSEQCTL_SOFFSET_POS (0U) +#define DMA_MONSNSEQCTL_SOFFSET (0x000FFFFFUL) +#define DMA_MONSNSEQCTL_SNSCNT_POS (20U) +#define DMA_MONSNSEQCTL_SNSCNT (0xFFF00000UL) + +/* Bit definition for DMA_MONDNSEQCTL register */ +#define DMA_MONDNSEQCTL_DOFFSET_POS (0U) +#define DMA_MONDNSEQCTL_DOFFSET (0x000FFFFFUL) +#define DMA_MONDNSEQCTL_DNSCNT_POS (20U) +#define DMA_MONDNSEQCTL_DNSCNT (0xFFF00000UL) + +/******************************************************************************* + Bit definition for Peripheral EFM +*******************************************************************************/ +/* Bit definition for EFM_FAPRT register */ +#define EFM_FAPRT_FAPRT (0x0000FFFFUL) + +/* Bit definition for EFM_FSTP register */ +#define EFM_FSTP_FSTP (0x00000001UL) + +/* Bit definition for EFM_FRMC register */ +#define EFM_FRMC_SLPMD_POS (0U) +#define EFM_FRMC_SLPMD (0x00000001UL) +#define EFM_FRMC_FLWT_POS (4U) +#define EFM_FRMC_FLWT (0x000000F0UL) +#define EFM_FRMC_LVM_POS (8U) +#define EFM_FRMC_LVM (0x00000100UL) +#define EFM_FRMC_CACHE_POS (16U) +#define EFM_FRMC_CACHE (0x00010000UL) +#define EFM_FRMC_CRST_POS (24U) +#define EFM_FRMC_CRST (0x01000000UL) + +/* Bit definition for EFM_FWMC register */ +#define EFM_FWMC_PEMODE_POS (0U) +#define EFM_FWMC_PEMODE (0x00000001UL) +#define EFM_FWMC_PEMOD_POS (4U) +#define EFM_FWMC_PEMOD (0x00000070UL) +#define EFM_FWMC_BUSHLDCTL_POS (8U) +#define EFM_FWMC_BUSHLDCTL (0x00000100UL) + +/* Bit definition for EFM_FSR register */ +#define EFM_FSR_PEWERR_POS (0U) +#define EFM_FSR_PEWERR (0x00000001UL) +#define EFM_FSR_PEPRTERR_POS (1U) +#define EFM_FSR_PEPRTERR (0x00000002UL) +#define EFM_FSR_PGSZERR_POS (2U) +#define EFM_FSR_PGSZERR (0x00000004UL) +#define EFM_FSR_PGMISMTCH_POS (3U) +#define EFM_FSR_PGMISMTCH (0x00000008UL) +#define EFM_FSR_OPTEND_POS (4U) +#define EFM_FSR_OPTEND (0x00000010UL) +#define EFM_FSR_COLERR_POS (5U) +#define EFM_FSR_COLERR (0x00000020UL) +#define EFM_FSR_RDY_POS (8U) +#define EFM_FSR_RDY (0x00000100UL) + +/* Bit definition for EFM_FSCLR register */ +#define EFM_FSCLR_PEWERRCLR_POS (0U) +#define EFM_FSCLR_PEWERRCLR (0x00000001UL) +#define EFM_FSCLR_PEPRTERRCLR_POS (1U) +#define EFM_FSCLR_PEPRTERRCLR (0x00000002UL) +#define EFM_FSCLR_PGSZERRCLR_POS (2U) +#define EFM_FSCLR_PGSZERRCLR (0x00000004UL) +#define EFM_FSCLR_PGMISMTCHCLR_POS (3U) +#define EFM_FSCLR_PGMISMTCHCLR (0x00000008UL) +#define EFM_FSCLR_OPTENDCLR_POS (4U) +#define EFM_FSCLR_OPTENDCLR (0x00000010UL) +#define EFM_FSCLR_COLERRCLR_POS (5U) +#define EFM_FSCLR_COLERRCLR (0x00000020UL) + +/* Bit definition for EFM_FITE register */ +#define EFM_FITE_PEERRITE_POS (0U) +#define EFM_FITE_PEERRITE (0x00000001UL) +#define EFM_FITE_OPTENDITE_POS (1U) +#define EFM_FITE_OPTENDITE (0x00000002UL) +#define EFM_FITE_COLERRITE_POS (2U) +#define EFM_FITE_COLERRITE (0x00000004UL) + +/* Bit definition for EFM_FSWP register */ +#define EFM_FSWP_FSWP (0x00000001UL) + +/* Bit definition for EFM_FPMTSW register */ +#define EFM_FPMTSW_FPMTSW (0x0007FFFFUL) + +/* Bit definition for EFM_FPMTEW register */ +#define EFM_FPMTEW_FPMTEW (0x0007FFFFUL) + +/* Bit definition for EFM_UQID0 register */ +#define EFM_UQID0 (0xFFFFFFFFUL) + +/* Bit definition for EFM_UQID1 register */ +#define EFM_UQID1 (0xFFFFFFFFUL) + +/* Bit definition for EFM_UQID2 register */ +#define EFM_UQID2 (0xFFFFFFFFUL) + +/* Bit definition for EFM_MMF_REMPRT register */ +#define EFM_MMF_REMPRT_REMPRT (0x0000FFFFUL) + +/* Bit definition for EFM_MMF_REMCR register */ +#define EFM_MMF_REMCR_RMSIZE_POS (0U) +#define EFM_MMF_REMCR_RMSIZE (0x0000001FUL) +#define EFM_MMF_REMCR_RMTADDR_POS (12U) +#define EFM_MMF_REMCR_RMTADDR (0x1FFFF000UL) +#define EFM_MMF_REMCR_EN_POS (31U) +#define EFM_MMF_REMCR_EN (0x80000000UL) + +/******************************************************************************* + Bit definition for Peripheral EMB +*******************************************************************************/ +/* Bit definition for EMB_CTL register */ +#define EMB_CTL_PORTINEN_POS (0U) +#define EMB_CTL_PORTINEN (0x00000001UL) +#define EMB_CTL_CMPEN1_POS (1U) +#define EMB_CTL_CMPEN1 (0x00000002UL) +#define EMB_CTL_CMPEN2_POS (2U) +#define EMB_CTL_CMPEN2 (0x00000004UL) +#define EMB_CTL_CMPEN3_POS (3U) +#define EMB_CTL_CMPEN3 (0x00000008UL) +#define EMB_CTL_OSCSTPEN_POS (5U) +#define EMB_CTL_OSCSTPEN (0x00000020UL) +#define EMB_CTL_PWMSEN0_POS (6U) +#define EMB_CTL_PWMSEN0 (0x00000040UL) +#define EMB_CTL_PWMSEN1_POS (7U) +#define EMB_CTL_PWMSEN1 (0x00000080UL) +#define EMB_CTL_PWMSEN2_POS (8U) +#define EMB_CTL_PWMSEN2 (0x00000100UL) +#define EMB_CTL_NFSEL_POS (28U) +#define EMB_CTL_NFSEL (0x30000000UL) +#define EMB_CTL_NFEN_POS (30U) +#define EMB_CTL_NFEN (0x40000000UL) +#define EMB_CTL_INVSEL_POS (31U) +#define EMB_CTL_INVSEL (0x80000000UL) + +/* Bit definition for EMB_PWMLV register */ +#define EMB_PWMLV_PWMLV0_POS (0U) +#define EMB_PWMLV_PWMLV0 (0x00000001UL) +#define EMB_PWMLV_PWMLV1_POS (1U) +#define EMB_PWMLV_PWMLV1 (0x00000002UL) +#define EMB_PWMLV_PWMLV2_POS (2U) +#define EMB_PWMLV_PWMLV2 (0x00000004UL) + +/* Bit definition for EMB_SOE register */ +#define EMB_SOE_SOE (0x00000001UL) + +/* Bit definition for EMB_STAT register */ +#define EMB_STAT_PORTINF_POS (0U) +#define EMB_STAT_PORTINF (0x00000001UL) +#define EMB_STAT_PWMSF_POS (1U) +#define EMB_STAT_PWMSF (0x00000002UL) +#define EMB_STAT_CMPF_POS (2U) +#define EMB_STAT_CMPF (0x00000004UL) +#define EMB_STAT_OSF_POS (3U) +#define EMB_STAT_OSF (0x00000008UL) +#define EMB_STAT_PORTINST_POS (4U) +#define EMB_STAT_PORTINST (0x00000010UL) +#define EMB_STAT_PWMST_POS (5U) +#define EMB_STAT_PWMST (0x00000020UL) + +/* Bit definition for EMB_STATCLR register */ +#define EMB_STATCLR_PORTINFCLR_POS (0U) +#define EMB_STATCLR_PORTINFCLR (0x00000001UL) +#define EMB_STATCLR_PWMSFCLR_POS (1U) +#define EMB_STATCLR_PWMSFCLR (0x00000002UL) +#define EMB_STATCLR_CMPFCLR_POS (2U) +#define EMB_STATCLR_CMPFCLR (0x00000004UL) +#define EMB_STATCLR_OSFCLR_POS (3U) +#define EMB_STATCLR_OSFCLR (0x00000008UL) + +/* Bit definition for EMB_INTEN register */ +#define EMB_INTEN_PORTININTEN_POS (0U) +#define EMB_INTEN_PORTININTEN (0x00000001UL) +#define EMB_INTEN_PWMSINTEN_POS (1U) +#define EMB_INTEN_PWMSINTEN (0x00000002UL) +#define EMB_INTEN_CMPINTEN_POS (2U) +#define EMB_INTEN_CMPINTEN (0x00000004UL) +#define EMB_INTEN_OSINTEN_POS (3U) +#define EMB_INTEN_OSINTEN (0x00000008UL) + +/******************************************************************************* + Bit definition for Peripheral FCM +*******************************************************************************/ +/* Bit definition for FCM_LVR register */ +#define FCM_LVR_LVR (0x0000FFFFUL) + +/* Bit definition for FCM_UVR register */ +#define FCM_UVR_UVR (0x0000FFFFUL) + +/* Bit definition for FCM_CNTR register */ +#define FCM_CNTR_CNTR (0x0000FFFFUL) + +/* Bit definition for FCM_STR register */ +#define FCM_STR_START (0x00000001UL) + +/* Bit definition for FCM_MCCR register */ +#define FCM_MCCR_MDIVS_POS (0U) +#define FCM_MCCR_MDIVS (0x00000003UL) +#define FCM_MCCR_MDIVS_0 (0x00000001UL) +#define FCM_MCCR_MDIVS_1 (0x00000002UL) +#define FCM_MCCR_MCKS_POS (4U) +#define FCM_MCCR_MCKS (0x000000F0UL) + +/* Bit definition for FCM_RCCR register */ +#define FCM_RCCR_RDIVS_POS (0U) +#define FCM_RCCR_RDIVS (0x00000003UL) +#define FCM_RCCR_RDIVS_0 (0x00000001UL) +#define FCM_RCCR_RDIVS_1 (0x00000002UL) +#define FCM_RCCR_RCKS_POS (3U) +#define FCM_RCCR_RCKS (0x00000078UL) +#define FCM_RCCR_INEXS_POS (7U) +#define FCM_RCCR_INEXS (0x00000080UL) +#define FCM_RCCR_DNFS_POS (8U) +#define FCM_RCCR_DNFS (0x00000300UL) +#define FCM_RCCR_DNFS_0 (0x00000100UL) +#define FCM_RCCR_DNFS_1 (0x00000200UL) +#define FCM_RCCR_EDGES_POS (12U) +#define FCM_RCCR_EDGES (0x00003000UL) +#define FCM_RCCR_EDGES_0 (0x00001000UL) +#define FCM_RCCR_EDGES_1 (0x00002000UL) +#define FCM_RCCR_EXREFE_POS (15U) +#define FCM_RCCR_EXREFE (0x00008000UL) + +/* Bit definition for FCM_RIER register */ +#define FCM_RIER_ERRIE_POS (0U) +#define FCM_RIER_ERRIE (0x00000001UL) +#define FCM_RIER_MENDIE_POS (1U) +#define FCM_RIER_MENDIE (0x00000002UL) +#define FCM_RIER_OVFIE_POS (2U) +#define FCM_RIER_OVFIE (0x00000004UL) +#define FCM_RIER_ERRINTRS_POS (4U) +#define FCM_RIER_ERRINTRS (0x00000010UL) +#define FCM_RIER_ERRE_POS (7U) +#define FCM_RIER_ERRE (0x00000080UL) + +/* Bit definition for FCM_SR register */ +#define FCM_SR_ERRF_POS (0U) +#define FCM_SR_ERRF (0x00000001UL) +#define FCM_SR_MENDF_POS (1U) +#define FCM_SR_MENDF (0x00000002UL) +#define FCM_SR_OVF_POS (2U) +#define FCM_SR_OVF (0x00000004UL) + +/* Bit definition for FCM_CLR register */ +#define FCM_CLR_ERRFCLR_POS (0U) +#define FCM_CLR_ERRFCLR (0x00000001UL) +#define FCM_CLR_MENDFCLR_POS (1U) +#define FCM_CLR_MENDFCLR (0x00000002UL) +#define FCM_CLR_OVFCLR_POS (2U) +#define FCM_CLR_OVFCLR (0x00000004UL) + +/******************************************************************************* + Bit definition for Peripheral GPIO +*******************************************************************************/ +/* Bit definition for GPIO_PIDR register */ +#define GPIO_PIDR_PIN00_POS (0U) +#define GPIO_PIDR_PIN00 (0x0001U) +#define GPIO_PIDR_PIN01_POS (1U) +#define GPIO_PIDR_PIN01 (0x0002U) +#define GPIO_PIDR_PIN02_POS (2U) +#define GPIO_PIDR_PIN02 (0x0004U) +#define GPIO_PIDR_PIN03_POS (3U) +#define GPIO_PIDR_PIN03 (0x0008U) +#define GPIO_PIDR_PIN04_POS (4U) +#define GPIO_PIDR_PIN04 (0x0010U) +#define GPIO_PIDR_PIN05_POS (5U) +#define GPIO_PIDR_PIN05 (0x0020U) +#define GPIO_PIDR_PIN06_POS (6U) +#define GPIO_PIDR_PIN06 (0x0040U) +#define GPIO_PIDR_PIN07_POS (7U) +#define GPIO_PIDR_PIN07 (0x0080U) +#define GPIO_PIDR_PIN08_POS (8U) +#define GPIO_PIDR_PIN08 (0x0100U) +#define GPIO_PIDR_PIN09_POS (9U) +#define GPIO_PIDR_PIN09 (0x0200U) +#define GPIO_PIDR_PIN10_POS (10U) +#define GPIO_PIDR_PIN10 (0x0400U) +#define GPIO_PIDR_PIN11_POS (11U) +#define GPIO_PIDR_PIN11 (0x0800U) +#define GPIO_PIDR_PIN12_POS (12U) +#define GPIO_PIDR_PIN12 (0x1000U) +#define GPIO_PIDR_PIN13_POS (13U) +#define GPIO_PIDR_PIN13 (0x2000U) +#define GPIO_PIDR_PIN14_POS (14U) +#define GPIO_PIDR_PIN14 (0x4000U) +#define GPIO_PIDR_PIN15_POS (15U) +#define GPIO_PIDR_PIN15 (0x8000U) + +/* Bit definition for GPIO_PODR register */ +#define GPIO_PODR_POUT00_POS (0U) +#define GPIO_PODR_POUT00 (0x0001U) +#define GPIO_PODR_POUT01_POS (1U) +#define GPIO_PODR_POUT01 (0x0002U) +#define GPIO_PODR_POUT02_POS (2U) +#define GPIO_PODR_POUT02 (0x0004U) +#define GPIO_PODR_POUT03_POS (3U) +#define GPIO_PODR_POUT03 (0x0008U) +#define GPIO_PODR_POUT04_POS (4U) +#define GPIO_PODR_POUT04 (0x0010U) +#define GPIO_PODR_POUT05_POS (5U) +#define GPIO_PODR_POUT05 (0x0020U) +#define GPIO_PODR_POUT06_POS (6U) +#define GPIO_PODR_POUT06 (0x0040U) +#define GPIO_PODR_POUT07_POS (7U) +#define GPIO_PODR_POUT07 (0x0080U) +#define GPIO_PODR_POUT08_POS (8U) +#define GPIO_PODR_POUT08 (0x0100U) +#define GPIO_PODR_POUT09_POS (9U) +#define GPIO_PODR_POUT09 (0x0200U) +#define GPIO_PODR_POUT10_POS (10U) +#define GPIO_PODR_POUT10 (0x0400U) +#define GPIO_PODR_POUT11_POS (11U) +#define GPIO_PODR_POUT11 (0x0800U) +#define GPIO_PODR_POUT12_POS (12U) +#define GPIO_PODR_POUT12 (0x1000U) +#define GPIO_PODR_POUT13_POS (13U) +#define GPIO_PODR_POUT13 (0x2000U) +#define GPIO_PODR_POUT14_POS (14U) +#define GPIO_PODR_POUT14 (0x4000U) +#define GPIO_PODR_POUT15_POS (15U) +#define GPIO_PODR_POUT15 (0x8000U) + +/* Bit definition for GPIO_POER register */ +#define GPIO_POER_POUTE00_POS (0U) +#define GPIO_POER_POUTE00 (0x0001U) +#define GPIO_POER_POUTE01_POS (1U) +#define GPIO_POER_POUTE01 (0x0002U) +#define GPIO_POER_POUTE02_POS (2U) +#define GPIO_POER_POUTE02 (0x0004U) +#define GPIO_POER_POUTE03_POS (3U) +#define GPIO_POER_POUTE03 (0x0008U) +#define GPIO_POER_POUTE04_POS (4U) +#define GPIO_POER_POUTE04 (0x0010U) +#define GPIO_POER_POUTE05_POS (5U) +#define GPIO_POER_POUTE05 (0x0020U) +#define GPIO_POER_POUTE06_POS (6U) +#define GPIO_POER_POUTE06 (0x0040U) +#define GPIO_POER_POUTE07_POS (7U) +#define GPIO_POER_POUTE07 (0x0080U) +#define GPIO_POER_POUTE08_POS (8U) +#define GPIO_POER_POUTE08 (0x0100U) +#define GPIO_POER_POUTE09_POS (9U) +#define GPIO_POER_POUTE09 (0x0200U) +#define GPIO_POER_POUTE10_POS (10U) +#define GPIO_POER_POUTE10 (0x0400U) +#define GPIO_POER_POUTE11_POS (11U) +#define GPIO_POER_POUTE11 (0x0800U) +#define GPIO_POER_POUTE12_POS (12U) +#define GPIO_POER_POUTE12 (0x1000U) +#define GPIO_POER_POUTE13_POS (13U) +#define GPIO_POER_POUTE13 (0x2000U) +#define GPIO_POER_POUTE14_POS (14U) +#define GPIO_POER_POUTE14 (0x4000U) +#define GPIO_POER_POUTE15_POS (15U) +#define GPIO_POER_POUTE15 (0x8000U) + +/* Bit definition for GPIO_POSR register */ +#define GPIO_POSR_POS00_POS (0U) +#define GPIO_POSR_POS00 (0x0001U) +#define GPIO_POSR_POS01_POS (1U) +#define GPIO_POSR_POS01 (0x0002U) +#define GPIO_POSR_POS02_POS (2U) +#define GPIO_POSR_POS02 (0x0004U) +#define GPIO_POSR_POS03_POS (3U) +#define GPIO_POSR_POS03 (0x0008U) +#define GPIO_POSR_POS04_POS (4U) +#define GPIO_POSR_POS04 (0x0010U) +#define GPIO_POSR_POS05_POS (5U) +#define GPIO_POSR_POS05 (0x0020U) +#define GPIO_POSR_POS06_POS (6U) +#define GPIO_POSR_POS06 (0x0040U) +#define GPIO_POSR_POS07_POS (7U) +#define GPIO_POSR_POS07 (0x0080U) +#define GPIO_POSR_POS08_POS (8U) +#define GPIO_POSR_POS08 (0x0100U) +#define GPIO_POSR_POS09_POS (9U) +#define GPIO_POSR_POS09 (0x0200U) +#define GPIO_POSR_POS10_POS (10U) +#define GPIO_POSR_POS10 (0x0400U) +#define GPIO_POSR_POS11_POS (11U) +#define GPIO_POSR_POS11 (0x0800U) +#define GPIO_POSR_POS12_POS (12U) +#define GPIO_POSR_POS12 (0x1000U) +#define GPIO_POSR_POS13_POS (13U) +#define GPIO_POSR_POS13 (0x2000U) +#define GPIO_POSR_POS14_POS (14U) +#define GPIO_POSR_POS14 (0x4000U) +#define GPIO_POSR_POS15_POS (15U) +#define GPIO_POSR_POS15 (0x8000U) + +/* Bit definition for GPIO_PORR register */ +#define GPIO_PORR_POR00_POS (0U) +#define GPIO_PORR_POR00 (0x0001U) +#define GPIO_PORR_POR01_POS (1U) +#define GPIO_PORR_POR01 (0x0002U) +#define GPIO_PORR_POR02_POS (2U) +#define GPIO_PORR_POR02 (0x0004U) +#define GPIO_PORR_POR03_POS (3U) +#define GPIO_PORR_POR03 (0x0008U) +#define GPIO_PORR_POR04_POS (4U) +#define GPIO_PORR_POR04 (0x0010U) +#define GPIO_PORR_POR05_POS (5U) +#define GPIO_PORR_POR05 (0x0020U) +#define GPIO_PORR_POR06_POS (6U) +#define GPIO_PORR_POR06 (0x0040U) +#define GPIO_PORR_POR07_POS (7U) +#define GPIO_PORR_POR07 (0x0080U) +#define GPIO_PORR_POR08_POS (8U) +#define GPIO_PORR_POR08 (0x0100U) +#define GPIO_PORR_POR09_POS (9U) +#define GPIO_PORR_POR09 (0x0200U) +#define GPIO_PORR_POR10_POS (10U) +#define GPIO_PORR_POR10 (0x0400U) +#define GPIO_PORR_POR11_POS (11U) +#define GPIO_PORR_POR11 (0x0800U) +#define GPIO_PORR_POR12_POS (12U) +#define GPIO_PORR_POR12 (0x1000U) +#define GPIO_PORR_POR13_POS (13U) +#define GPIO_PORR_POR13 (0x2000U) +#define GPIO_PORR_POR14_POS (14U) +#define GPIO_PORR_POR14 (0x4000U) +#define GPIO_PORR_POR15_POS (15U) +#define GPIO_PORR_POR15 (0x8000U) + +/* Bit definition for GPIO_POTR register */ +#define GPIO_POTR_POT00_POS (0U) +#define GPIO_POTR_POT00 (0x0001U) +#define GPIO_POTR_POT01_POS (1U) +#define GPIO_POTR_POT01 (0x0002U) +#define GPIO_POTR_POT02_POS (2U) +#define GPIO_POTR_POT02 (0x0004U) +#define GPIO_POTR_POT03_POS (3U) +#define GPIO_POTR_POT03 (0x0008U) +#define GPIO_POTR_POT04_POS (4U) +#define GPIO_POTR_POT04 (0x0010U) +#define GPIO_POTR_POT05_POS (5U) +#define GPIO_POTR_POT05 (0x0020U) +#define GPIO_POTR_POT06_POS (6U) +#define GPIO_POTR_POT06 (0x0040U) +#define GPIO_POTR_POT07_POS (7U) +#define GPIO_POTR_POT07 (0x0080U) +#define GPIO_POTR_POT08_POS (8U) +#define GPIO_POTR_POT08 (0x0100U) +#define GPIO_POTR_POT09_POS (9U) +#define GPIO_POTR_POT09 (0x0200U) +#define GPIO_POTR_POT10_POS (10U) +#define GPIO_POTR_POT10 (0x0400U) +#define GPIO_POTR_POT11_POS (11U) +#define GPIO_POTR_POT11 (0x0800U) +#define GPIO_POTR_POT12_POS (12U) +#define GPIO_POTR_POT12 (0x1000U) +#define GPIO_POTR_POT13_POS (13U) +#define GPIO_POTR_POT13 (0x2000U) +#define GPIO_POTR_POT14_POS (14U) +#define GPIO_POTR_POT14 (0x4000U) +#define GPIO_POTR_POT15_POS (15U) +#define GPIO_POTR_POT15 (0x8000U) + +/* Bit definition for GPIO_PIDRH register */ +#define GPIO_PIDRH_PIN00_POS (0U) +#define GPIO_PIDRH_PIN00 (0x0001U) +#define GPIO_PIDRH_PIN01_POS (1U) +#define GPIO_PIDRH_PIN01 (0x0002U) +#define GPIO_PIDRH_PIN02_POS (2U) +#define GPIO_PIDRH_PIN02 (0x0004U) + +/* Bit definition for GPIO_PODRH register */ +#define GPIO_PODRH_POUT00_POS (0U) +#define GPIO_PODRH_POUT00 (0x0001U) +#define GPIO_PODRH_POUT01_POS (1U) +#define GPIO_PODRH_POUT01 (0x0002U) +#define GPIO_PODRH_POUT02_POS (2U) +#define GPIO_PODRH_POUT02 (0x0004U) + +/* Bit definition for GPIO_POERH register */ +#define GPIO_POERH_POUTE00_POS (0U) +#define GPIO_POERH_POUTE00 (0x0001U) +#define GPIO_POERH_POUTE01_POS (1U) +#define GPIO_POERH_POUTE01 (0x0002U) +#define GPIO_POERH_POUTE02_POS (2U) +#define GPIO_POERH_POUTE02 (0x0004U) + +/* Bit definition for GPIO_POSRH register */ +#define GPIO_POSRH_POS00_POS (0U) +#define GPIO_POSRH_POS00 (0x0001U) +#define GPIO_POSRH_POS01_POS (1U) +#define GPIO_POSRH_POS01 (0x0002U) +#define GPIO_POSRH_POS02_POS (2U) +#define GPIO_POSRH_POS02 (0x0004U) + +/* Bit definition for GPIO_PORRH register */ +#define GPIO_PORRH_POR00_POS (0U) +#define GPIO_PORRH_POR00 (0x0001U) +#define GPIO_PORRH_POR01_POS (1U) +#define GPIO_PORRH_POR01 (0x0002U) +#define GPIO_PORRH_POR02_POS (2U) +#define GPIO_PORRH_POR02 (0x0004U) + +/* Bit definition for GPIO_POTRH register */ +#define GPIO_POTRH_POT00_POS (0U) +#define GPIO_POTRH_POT00 (0x0001U) +#define GPIO_POTRH_POT01_POS (1U) +#define GPIO_POTRH_POT01 (0x0002U) +#define GPIO_POTRH_POT02_POS (2U) +#define GPIO_POTRH_POT02 (0x0004U) + +/* Bit definition for GPIO_PSPCR register */ +#define GPIO_PSPCR_SPFE (0x001FU) +#define GPIO_PSPCR_SPFE_0 (0x0001U) +#define GPIO_PSPCR_SPFE_1 (0x0002U) +#define GPIO_PSPCR_SPFE_2 (0x0004U) +#define GPIO_PSPCR_SPFE_3 (0x0008U) +#define GPIO_PSPCR_SPFE_4 (0x0010U) + +/* Bit definition for GPIO_PCCR register */ +#define GPIO_PCCR_BFSEL_POS (0U) +#define GPIO_PCCR_BFSEL (0x000FU) +#define GPIO_PCCR_BFSEL_0 (0x0001U) +#define GPIO_PCCR_BFSEL_1 (0x0002U) +#define GPIO_PCCR_BFSEL_2 (0x0004U) +#define GPIO_PCCR_BFSEL_3 (0x0008U) +#define GPIO_PCCR_RDWT_POS (14U) +#define GPIO_PCCR_RDWT (0xC000U) +#define GPIO_PCCR_RDWT_0 (0x4000U) +#define GPIO_PCCR_RDWT_1 (0x8000U) + +/* Bit definition for GPIO_PINAER register */ +#define GPIO_PINAER_PINAE (0x003FU) +#define GPIO_PINAER_PINAE_0 (0x0001U) +#define GPIO_PINAER_PINAE_1 (0x0002U) +#define GPIO_PINAER_PINAE_2 (0x0004U) +#define GPIO_PINAER_PINAE_3 (0x0008U) +#define GPIO_PINAER_PINAE_4 (0x0010U) +#define GPIO_PINAER_PINAE_5 (0x0020U) + +/* Bit definition for GPIO_PWPR register */ +#define GPIO_PWPR_WE_POS (0U) +#define GPIO_PWPR_WE (0x0001U) +#define GPIO_PWPR_WP_POS (8U) +#define GPIO_PWPR_WP (0xFF00U) +#define GPIO_PWPR_WP_0 (0x0100U) +#define GPIO_PWPR_WP_1 (0x0200U) +#define GPIO_PWPR_WP_2 (0x0400U) +#define GPIO_PWPR_WP_3 (0x0800U) +#define GPIO_PWPR_WP_4 (0x1000U) +#define GPIO_PWPR_WP_5 (0x2000U) +#define GPIO_PWPR_WP_6 (0x4000U) +#define GPIO_PWPR_WP_7 (0x8000U) + +/* Bit definition for GPIO_PCR register */ +#define GPIO_PCR_POUT_POS (0U) +#define GPIO_PCR_POUT (0x0001U) +#define GPIO_PCR_POUTE_POS (1U) +#define GPIO_PCR_POUTE (0x0002U) +#define GPIO_PCR_NOD_POS (2U) +#define GPIO_PCR_NOD (0x0004U) +#define GPIO_PCR_DRV_POS (4U) +#define GPIO_PCR_DRV (0x0030U) +#define GPIO_PCR_DRV_0 (0x0010U) +#define GPIO_PCR_DRV_1 (0x0020U) +#define GPIO_PCR_PUU_POS (6U) +#define GPIO_PCR_PUU (0x0040U) +#define GPIO_PCR_PIN_POS (8U) +#define GPIO_PCR_PIN (0x0100U) +#define GPIO_PCR_INVE_POS (9U) +#define GPIO_PCR_INVE (0x0200U) +#define GPIO_PCR_INTE_POS (12U) +#define GPIO_PCR_INTE (0x1000U) +#define GPIO_PCR_LTE_POS (14U) +#define GPIO_PCR_LTE (0x4000U) +#define GPIO_PCR_DDIS_POS (15U) +#define GPIO_PCR_DDIS (0x8000U) + +/* Bit definition for GPIO_PFSR register */ +#define GPIO_PFSR_FSEL_POS (0U) +#define GPIO_PFSR_FSEL (0x003FU) +#define GPIO_PFSR_FSEL_0 (0x0001U) +#define GPIO_PFSR_FSEL_1 (0x0002U) +#define GPIO_PFSR_FSEL_2 (0x0004U) +#define GPIO_PFSR_FSEL_3 (0x0008U) +#define GPIO_PFSR_FSEL_4 (0x0010U) +#define GPIO_PFSR_FSEL_5 (0x0020U) +#define GPIO_PFSR_BFE_POS (8U) +#define GPIO_PFSR_BFE (0x0100U) + +/******************************************************************************* + Bit definition for Peripheral HASH +*******************************************************************************/ +/* Bit definition for HASH_CR register */ +#define HASH_CR_START_POS (0U) +#define HASH_CR_START (0x00000001UL) +#define HASH_CR_FST_GRP_POS (1U) +#define HASH_CR_FST_GRP (0x00000002UL) + +/* Bit definition for HASH_HR7 register */ +#define HASH_HR7 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR6 register */ +#define HASH_HR6 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR5 register */ +#define HASH_HR5 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR4 register */ +#define HASH_HR4 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR3 register */ +#define HASH_HR3 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR2 register */ +#define HASH_HR2 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR1 register */ +#define HASH_HR1 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR0 register */ +#define HASH_HR0 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR15 register */ +#define HASH_DR15 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR14 register */ +#define HASH_DR14 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR13 register */ +#define HASH_DR13 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR12 register */ +#define HASH_DR12 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR11 register */ +#define HASH_DR11 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR10 register */ +#define HASH_DR10 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR9 register */ +#define HASH_DR9 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR8 register */ +#define HASH_DR8 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR7 register */ +#define HASH_DR7 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR6 register */ +#define HASH_DR6 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR5 register */ +#define HASH_DR5 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR4 register */ +#define HASH_DR4 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR3 register */ +#define HASH_DR3 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR2 register */ +#define HASH_DR2 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR1 register */ +#define HASH_DR1 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR0 register */ +#define HASH_DR0 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral I2C +*******************************************************************************/ +/* Bit definition for I2C_CR1 register */ +#define I2C_CR1_PE_POS (0U) +#define I2C_CR1_PE (0x00000001UL) +#define I2C_CR1_SMBUS_POS (1U) +#define I2C_CR1_SMBUS (0x00000002UL) +#define I2C_CR1_SMBALRTEN_POS (2U) +#define I2C_CR1_SMBALRTEN (0x00000004UL) +#define I2C_CR1_SMBDEFAULTEN_POS (3U) +#define I2C_CR1_SMBDEFAULTEN (0x00000008UL) +#define I2C_CR1_SMBHOSTEN_POS (4U) +#define I2C_CR1_SMBHOSTEN (0x00000010UL) +#define I2C_CR1_GCEN_POS (6U) +#define I2C_CR1_GCEN (0x00000040UL) +#define I2C_CR1_RESTART_POS (7U) +#define I2C_CR1_RESTART (0x00000080UL) +#define I2C_CR1_START_POS (8U) +#define I2C_CR1_START (0x00000100UL) +#define I2C_CR1_STOP_POS (9U) +#define I2C_CR1_STOP (0x00000200UL) +#define I2C_CR1_ACK_POS (10U) +#define I2C_CR1_ACK (0x00000400UL) +#define I2C_CR1_SWRST_POS (15U) +#define I2C_CR1_SWRST (0x00008000UL) + +/* Bit definition for I2C_CR2 register */ +#define I2C_CR2_STARTIE_POS (0U) +#define I2C_CR2_STARTIE (0x00000001UL) +#define I2C_CR2_SLADDR0IE_POS (1U) +#define I2C_CR2_SLADDR0IE (0x00000002UL) +#define I2C_CR2_SLADDR1IE_POS (2U) +#define I2C_CR2_SLADDR1IE (0x00000004UL) +#define I2C_CR2_TENDIE_POS (3U) +#define I2C_CR2_TENDIE (0x00000008UL) +#define I2C_CR2_STOPIE_POS (4U) +#define I2C_CR2_STOPIE (0x00000010UL) +#define I2C_CR2_RFULLIE_POS (6U) +#define I2C_CR2_RFULLIE (0x00000040UL) +#define I2C_CR2_TEMPTYIE_POS (7U) +#define I2C_CR2_TEMPTYIE (0x00000080UL) +#define I2C_CR2_ARLOIE_POS (9U) +#define I2C_CR2_ARLOIE (0x00000200UL) +#define I2C_CR2_NACKIE_POS (12U) +#define I2C_CR2_NACKIE (0x00001000UL) +#define I2C_CR2_TMOUTIE_POS (14U) +#define I2C_CR2_TMOUTIE (0x00004000UL) +#define I2C_CR2_GENCALLIE_POS (20U) +#define I2C_CR2_GENCALLIE (0x00100000UL) +#define I2C_CR2_SMBDEFAULTIE_POS (21U) +#define I2C_CR2_SMBDEFAULTIE (0x00200000UL) +#define I2C_CR2_SMBHOSTIE_POS (22U) +#define I2C_CR2_SMBHOSTIE (0x00400000UL) +#define I2C_CR2_SMBALRTIE_POS (23U) +#define I2C_CR2_SMBALRTIE (0x00800000UL) + +/* Bit definition for I2C_CR3 register */ +#define I2C_CR3_TMOUTEN_POS (0U) +#define I2C_CR3_TMOUTEN (0x00000001UL) +#define I2C_CR3_LTMOUT_POS (1U) +#define I2C_CR3_LTMOUT (0x00000002UL) +#define I2C_CR3_HTMOUT_POS (2U) +#define I2C_CR3_HTMOUT (0x00000004UL) +#define I2C_CR3_FACKEN_POS (7U) +#define I2C_CR3_FACKEN (0x00000080UL) + +/* Bit definition for I2C_CR4 register */ +#define I2C_CR4_BUSWAIT_POS (10U) +#define I2C_CR4_BUSWAIT (0x00000400UL) + +/* Bit definition for I2C_SLR0 register */ +#define I2C_SLR0_SLADDR0_POS (0U) +#define I2C_SLR0_SLADDR0 (0x000003FFUL) +#define I2C_SLR0_SLADDR0EN_POS (12U) +#define I2C_SLR0_SLADDR0EN (0x00001000UL) +#define I2C_SLR0_ADDRMOD0_POS (15U) +#define I2C_SLR0_ADDRMOD0 (0x00008000UL) + +/* Bit definition for I2C_SLR1 register */ +#define I2C_SLR1_SLADDR1_POS (0U) +#define I2C_SLR1_SLADDR1 (0x000003FFUL) +#define I2C_SLR1_SLADDR1EN_POS (12U) +#define I2C_SLR1_SLADDR1EN (0x00001000UL) +#define I2C_SLR1_ADDRMOD1_POS (15U) +#define I2C_SLR1_ADDRMOD1 (0x00008000UL) + +/* Bit definition for I2C_SLTR register */ +#define I2C_SLTR_TOUTLOW_POS (0U) +#define I2C_SLTR_TOUTLOW (0x0000FFFFUL) +#define I2C_SLTR_TOUTHIGH_POS (16U) +#define I2C_SLTR_TOUTHIGH (0xFFFF0000UL) + +/* Bit definition for I2C_SR register */ +#define I2C_SR_STARTF_POS (0U) +#define I2C_SR_STARTF (0x00000001UL) +#define I2C_SR_SLADDR0F_POS (1U) +#define I2C_SR_SLADDR0F (0x00000002UL) +#define I2C_SR_SLADDR1F_POS (2U) +#define I2C_SR_SLADDR1F (0x00000004UL) +#define I2C_SR_TENDF_POS (3U) +#define I2C_SR_TENDF (0x00000008UL) +#define I2C_SR_STOPF_POS (4U) +#define I2C_SR_STOPF (0x00000010UL) +#define I2C_SR_RFULLF_POS (6U) +#define I2C_SR_RFULLF (0x00000040UL) +#define I2C_SR_TEMPTYF_POS (7U) +#define I2C_SR_TEMPTYF (0x00000080UL) +#define I2C_SR_ARLOF_POS (9U) +#define I2C_SR_ARLOF (0x00000200UL) +#define I2C_SR_ACKRF_POS (10U) +#define I2C_SR_ACKRF (0x00000400UL) +#define I2C_SR_NACKF_POS (12U) +#define I2C_SR_NACKF (0x00001000UL) +#define I2C_SR_TMOUTF_POS (14U) +#define I2C_SR_TMOUTF (0x00004000UL) +#define I2C_SR_MSL_POS (16U) +#define I2C_SR_MSL (0x00010000UL) +#define I2C_SR_BUSY_POS (17U) +#define I2C_SR_BUSY (0x00020000UL) +#define I2C_SR_TRA_POS (18U) +#define I2C_SR_TRA (0x00040000UL) +#define I2C_SR_GENCALLF_POS (20U) +#define I2C_SR_GENCALLF (0x00100000UL) +#define I2C_SR_SMBDEFAULTF_POS (21U) +#define I2C_SR_SMBDEFAULTF (0x00200000UL) +#define I2C_SR_SMBHOSTF_POS (22U) +#define I2C_SR_SMBHOSTF (0x00400000UL) +#define I2C_SR_SMBALRTF_POS (23U) +#define I2C_SR_SMBALRTF (0x00800000UL) + +/* Bit definition for I2C_CLR register */ +#define I2C_CLR_STARTFCLR_POS (0U) +#define I2C_CLR_STARTFCLR (0x00000001UL) +#define I2C_CLR_SLADDR0FCLR_POS (1U) +#define I2C_CLR_SLADDR0FCLR (0x00000002UL) +#define I2C_CLR_SLADDR1FCLR_POS (2U) +#define I2C_CLR_SLADDR1FCLR (0x00000004UL) +#define I2C_CLR_TENDFCLR_POS (3U) +#define I2C_CLR_TENDFCLR (0x00000008UL) +#define I2C_CLR_STOPFCLR_POS (4U) +#define I2C_CLR_STOPFCLR (0x00000010UL) +#define I2C_CLR_RFULLFCLR_POS (6U) +#define I2C_CLR_RFULLFCLR (0x00000040UL) +#define I2C_CLR_TEMPTYFCLR_POS (7U) +#define I2C_CLR_TEMPTYFCLR (0x00000080UL) +#define I2C_CLR_ARLOFCLR_POS (9U) +#define I2C_CLR_ARLOFCLR (0x00000200UL) +#define I2C_CLR_NACKFCLR_POS (12U) +#define I2C_CLR_NACKFCLR (0x00001000UL) +#define I2C_CLR_TMOUTFCLR_POS (14U) +#define I2C_CLR_TMOUTFCLR (0x00004000UL) +#define I2C_CLR_GENCALLFCLR_POS (20U) +#define I2C_CLR_GENCALLFCLR (0x00100000UL) +#define I2C_CLR_SMBDEFAULTFCLR_POS (21U) +#define I2C_CLR_SMBDEFAULTFCLR (0x00200000UL) +#define I2C_CLR_SMBHOSTFCLR_POS (22U) +#define I2C_CLR_SMBHOSTFCLR (0x00400000UL) +#define I2C_CLR_SMBALRTFCLR_POS (23U) +#define I2C_CLR_SMBALRTFCLR (0x00800000UL) + +/* Bit definition for I2C_DTR register */ +#define I2C_DTR_DT (0xFFU) + +/* Bit definition for I2C_DRR register */ +#define I2C_DRR_DR (0xFFU) + +/* Bit definition for I2C_CCR register */ +#define I2C_CCR_SLOWW_POS (0U) +#define I2C_CCR_SLOWW (0x0000001FUL) +#define I2C_CCR_SHIGHW_POS (8U) +#define I2C_CCR_SHIGHW (0x00001F00UL) +#define I2C_CCR_CKDIV_POS (16U) +#define I2C_CCR_CKDIV (0x00070000UL) + +/* Bit definition for I2C_FLTR register */ +#define I2C_FLTR_DNF_POS (0U) +#define I2C_FLTR_DNF (0x00000003UL) +#define I2C_FLTR_DNF_0 (0x00000001UL) +#define I2C_FLTR_DNF_1 (0x00000002UL) +#define I2C_FLTR_DNFEN_POS (4U) +#define I2C_FLTR_DNFEN (0x00000010UL) +#define I2C_FLTR_ANFEN_POS (5U) +#define I2C_FLTR_ANFEN (0x00000020UL) + +/******************************************************************************* + Bit definition for Peripheral I2S +*******************************************************************************/ +/* Bit definition for I2S_CTRL register */ +#define I2S_CTRL_TXE_POS (0U) +#define I2S_CTRL_TXE (0x00000001UL) +#define I2S_CTRL_TXIE_POS (1U) +#define I2S_CTRL_TXIE (0x00000002UL) +#define I2S_CTRL_RXE_POS (2U) +#define I2S_CTRL_RXE (0x00000004UL) +#define I2S_CTRL_RXIE_POS (3U) +#define I2S_CTRL_RXIE (0x00000008UL) +#define I2S_CTRL_EIE_POS (4U) +#define I2S_CTRL_EIE (0x00000010UL) +#define I2S_CTRL_WMS_POS (5U) +#define I2S_CTRL_WMS (0x00000020UL) +#define I2S_CTRL_ODD_POS (6U) +#define I2S_CTRL_ODD (0x00000040UL) +#define I2S_CTRL_MCKOE_POS (7U) +#define I2S_CTRL_MCKOE (0x00000080UL) +#define I2S_CTRL_TXBIRQWL_POS (8U) +#define I2S_CTRL_TXBIRQWL (0x00000700UL) +#define I2S_CTRL_RXBIRQWL_POS (12U) +#define I2S_CTRL_RXBIRQWL (0x00007000UL) +#define I2S_CTRL_FIFOR_POS (16U) +#define I2S_CTRL_FIFOR (0x00010000UL) +#define I2S_CTRL_I2SPLLSEL_POS (18U) +#define I2S_CTRL_I2SPLLSEL (0x00040000UL) +#define I2S_CTRL_SDOE_POS (19U) +#define I2S_CTRL_SDOE (0x00080000UL) +#define I2S_CTRL_LRCKOE_POS (20U) +#define I2S_CTRL_LRCKOE (0x00100000UL) +#define I2S_CTRL_CKOE_POS (21U) +#define I2S_CTRL_CKOE (0x00200000UL) +#define I2S_CTRL_DUPLEX_POS (22U) +#define I2S_CTRL_DUPLEX (0x00400000UL) +#define I2S_CTRL_CLKSEL_POS (23U) +#define I2S_CTRL_CLKSEL (0x00800000UL) + +/* Bit definition for I2S_SR register */ +#define I2S_SR_TXBA_POS (0U) +#define I2S_SR_TXBA (0x00000001UL) +#define I2S_SR_RXBA_POS (1U) +#define I2S_SR_RXBA (0x00000002UL) +#define I2S_SR_TXBE_POS (2U) +#define I2S_SR_TXBE (0x00000004UL) +#define I2S_SR_TXBF_POS (3U) +#define I2S_SR_TXBF (0x00000008UL) +#define I2S_SR_RXBE_POS (4U) +#define I2S_SR_RXBE (0x00000010UL) +#define I2S_SR_RXBF_POS (5U) +#define I2S_SR_RXBF (0x00000020UL) + +/* Bit definition for I2S_ER register */ +#define I2S_ER_TXERR_POS (0U) +#define I2S_ER_TXERR (0x00000001UL) +#define I2S_ER_RXERR_POS (1U) +#define I2S_ER_RXERR (0x00000002UL) + +/* Bit definition for I2S_CFGR register */ +#define I2S_CFGR_I2SSTD_POS (0U) +#define I2S_CFGR_I2SSTD (0x00000003UL) +#define I2S_CFGR_I2SSTD_0 (0x00000001UL) +#define I2S_CFGR_I2SSTD_1 (0x00000002UL) +#define I2S_CFGR_DATLEN_POS (2U) +#define I2S_CFGR_DATLEN (0x0000000CUL) +#define I2S_CFGR_DATLEN_0 (0x00000004UL) +#define I2S_CFGR_DATLEN_1 (0x00000008UL) +#define I2S_CFGR_CHLEN_POS (4U) +#define I2S_CFGR_CHLEN (0x00000010UL) +#define I2S_CFGR_PCMSYNC_POS (5U) +#define I2S_CFGR_PCMSYNC (0x00000020UL) + +/* Bit definition for I2S_TXBUF register */ +#define I2S_TXBUF (0xFFFFFFFFUL) + +/* Bit definition for I2S_RXBUF register */ +#define I2S_RXBUF (0xFFFFFFFFUL) + +/* Bit definition for I2S_PR register */ +#define I2S_PR_I2SDIV (0x000000FFUL) + +/******************************************************************************* + Bit definition for Peripheral ICG +*******************************************************************************/ +/* Bit definition for ICG_ICG0 register */ +#define ICG_ICG0_SWDTAUTS_POS (0U) +#define ICG_ICG0_SWDTAUTS (0x00000001UL) +#define ICG_ICG0_SWDTITS_POS (1U) +#define ICG_ICG0_SWDTITS (0x00000002UL) +#define ICG_ICG0_SWDTPERI_POS (2U) +#define ICG_ICG0_SWDTPERI (0x0000000CUL) +#define ICG_ICG0_SWDTPERI_0 (0x00000004UL) +#define ICG_ICG0_SWDTPERI_1 (0x00000008UL) +#define ICG_ICG0_SWDTCKS_POS (4U) +#define ICG_ICG0_SWDTCKS (0x000000F0UL) +#define ICG_ICG0_SWDTWDPT_POS (8U) +#define ICG_ICG0_SWDTWDPT (0x00000F00UL) +#define ICG_ICG0_SWDTSLPOFF_POS (12U) +#define ICG_ICG0_SWDTSLPOFF (0x00001000UL) +#define ICG_ICG0_WDTAUTS_POS (16U) +#define ICG_ICG0_WDTAUTS (0x00010000UL) +#define ICG_ICG0_WDTITS_POS (17U) +#define ICG_ICG0_WDTITS (0x00020000UL) +#define ICG_ICG0_WDTPERI_POS (18U) +#define ICG_ICG0_WDTPERI (0x000C0000UL) +#define ICG_ICG0_WDTPERI_0 (0x00040000UL) +#define ICG_ICG0_WDTPERI_1 (0x00080000UL) +#define ICG_ICG0_WDTCKS_POS (20U) +#define ICG_ICG0_WDTCKS (0x00F00000UL) +#define ICG_ICG0_WDTWDPT_POS (24U) +#define ICG_ICG0_WDTWDPT (0x0F000000UL) +#define ICG_ICG0_WDTSLPOFF_POS (28U) +#define ICG_ICG0_WDTSLPOFF (0x10000000UL) + +/* Bit definition for ICG_ICG1 register */ +#define ICG_ICG1_HRCFREQSEL_POS (0U) +#define ICG_ICG1_HRCFREQSEL (0x00000001UL) +#define ICG_ICG1_HRCSTOP_POS (8U) +#define ICG_ICG1_HRCSTOP (0x00000100UL) +#define ICG_ICG1_BOR_LEV_POS (16U) +#define ICG_ICG1_BOR_LEV (0x00030000UL) +#define ICG_ICG1_BOR_LEV_0 (0x00010000UL) +#define ICG_ICG1_BOR_LEV_1 (0x00020000UL) +#define ICG_ICG1_BORDIS_POS (18U) +#define ICG_ICG1_BORDIS (0x00040000UL) +#define ICG_ICG1_SMPCLK_POS (26U) +#define ICG_ICG1_SMPCLK (0x0C000000UL) +#define ICG_ICG1_SMPCLK_0 (0x04000000UL) +#define ICG_ICG1_SMPCLK_1 (0x08000000UL) +#define ICG_ICG1_NMITRG_POS (28U) +#define ICG_ICG1_NMITRG (0x10000000UL) +#define ICG_ICG1_NMIEN_POS (29U) +#define ICG_ICG1_NMIEN (0x20000000UL) +#define ICG_ICG1_NFEN_POS (30U) +#define ICG_ICG1_NFEN (0x40000000UL) +#define ICG_ICG1_NMIICGEN_POS (31U) +#define ICG_ICG1_NMIICGEN (0x80000000UL) + +/* Bit definition for ICG_ICG2 register */ +#define ICG_ICG2 (0xFFFFFFFFUL) + +/* Bit definition for ICG_ICG3 register */ +#define ICG_ICG3 (0xFFFFFFFFUL) + +/* Bit definition for ICG_ICG4 register */ +#define ICG_ICG4 (0xFFFFFFFFUL) + +/* Bit definition for ICG_ICG5 register */ +#define ICG_ICG5 (0xFFFFFFFFUL) + +/* Bit definition for ICG_ICG6 register */ +#define ICG_ICG6 (0xFFFFFFFFUL) + +/* Bit definition for ICG_ICG7 register */ +#define ICG_ICG7 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral INTC +*******************************************************************************/ +/* Bit definition for INTC_NMICR register */ +#define INTC_NMICR_NMITRG_POS (0U) +#define INTC_NMICR_NMITRG (0x00000001UL) +#define INTC_NMICR_NSMPCLK_POS (4U) +#define INTC_NMICR_NSMPCLK (0x00000030UL) +#define INTC_NMICR_NSMPCLK_0 (0x00000010UL) +#define INTC_NMICR_NSMPCLK_1 (0x00000020UL) +#define INTC_NMICR_NFEN_POS (7U) +#define INTC_NMICR_NFEN (0x00000080UL) + +/* Bit definition for INTC_NMIENR register */ +#define INTC_NMIENR_NMIENR_POS (0U) +#define INTC_NMIENR_NMIENR (0x00000001UL) +#define INTC_NMIENR_SWDTENR_POS (1U) +#define INTC_NMIENR_SWDTENR (0x00000002UL) +#define INTC_NMIENR_PVD1ENR_POS (2U) +#define INTC_NMIENR_PVD1ENR (0x00000004UL) +#define INTC_NMIENR_PVD2ENR_POS (3U) +#define INTC_NMIENR_PVD2ENR (0x00000008UL) +#define INTC_NMIENR_XTALSTPENR_POS (5U) +#define INTC_NMIENR_XTALSTPENR (0x00000020UL) +#define INTC_NMIENR_REPENR_POS (8U) +#define INTC_NMIENR_REPENR (0x00000100UL) +#define INTC_NMIENR_RECCENR_POS (9U) +#define INTC_NMIENR_RECCENR (0x00000200UL) +#define INTC_NMIENR_BUSMENR_POS (10U) +#define INTC_NMIENR_BUSMENR (0x00000400UL) +#define INTC_NMIENR_WDTENR_POS (11U) +#define INTC_NMIENR_WDTENR (0x00000800UL) + +/* Bit definition for INTC_NMIFR register */ +#define INTC_NMIFR_NMIFR_POS (0U) +#define INTC_NMIFR_NMIFR (0x00000001UL) +#define INTC_NMIFR_SWDTFR_POS (1U) +#define INTC_NMIFR_SWDTFR (0x00000002UL) +#define INTC_NMIFR_PVD1FR_POS (2U) +#define INTC_NMIFR_PVD1FR (0x00000004UL) +#define INTC_NMIFR_PVD2FR_POS (3U) +#define INTC_NMIFR_PVD2FR (0x00000008UL) +#define INTC_NMIFR_XTALSTPFR_POS (5U) +#define INTC_NMIFR_XTALSTPFR (0x00000020UL) +#define INTC_NMIFR_REPFR_POS (8U) +#define INTC_NMIFR_REPFR (0x00000100UL) +#define INTC_NMIFR_RECCFR_POS (9U) +#define INTC_NMIFR_RECCFR (0x00000200UL) +#define INTC_NMIFR_BUSMFR_POS (10U) +#define INTC_NMIFR_BUSMFR (0x00000400UL) +#define INTC_NMIFR_WDTFR_POS (11U) +#define INTC_NMIFR_WDTFR (0x00000800UL) + +/* Bit definition for INTC_NMICFR register */ +#define INTC_NMICFR_NMICFR_POS (0U) +#define INTC_NMICFR_NMICFR (0x00000001UL) +#define INTC_NMICFR_SWDTCFR_POS (1U) +#define INTC_NMICFR_SWDTCFR (0x00000002UL) +#define INTC_NMICFR_PVD1CFR_POS (2U) +#define INTC_NMICFR_PVD1CFR (0x00000004UL) +#define INTC_NMICFR_PVD2CFR_POS (3U) +#define INTC_NMICFR_PVD2CFR (0x00000008UL) +#define INTC_NMICFR_XTALSTPCFR_POS (5U) +#define INTC_NMICFR_XTALSTPCFR (0x00000020UL) +#define INTC_NMICFR_REPCFR_POS (8U) +#define INTC_NMICFR_REPCFR (0x00000100UL) +#define INTC_NMICFR_RECCCFR_POS (9U) +#define INTC_NMICFR_RECCCFR (0x00000200UL) +#define INTC_NMICFR_BUSMCFR_POS (10U) +#define INTC_NMICFR_BUSMCFR (0x00000400UL) +#define INTC_NMICFR_WDTCFR_POS (11U) +#define INTC_NMICFR_WDTCFR (0x00000800UL) + +/* Bit definition for INTC_EIRQCR register */ +#define INTC_EIRQCR_EIRQTRG_POS (0U) +#define INTC_EIRQCR_EIRQTRG (0x00000003UL) +#define INTC_EIRQCR_EIRQTRG_0 (0x00000001UL) +#define INTC_EIRQCR_EIRQTRG_1 (0x00000002UL) +#define INTC_EIRQCR_EISMPCLK_POS (4U) +#define INTC_EIRQCR_EISMPCLK (0x00000030UL) +#define INTC_EIRQCR_EISMPCLK_0 (0x00000010UL) +#define INTC_EIRQCR_EISMPCLK_1 (0x00000020UL) +#define INTC_EIRQCR_EFEN_POS (7U) +#define INTC_EIRQCR_EFEN (0x00000080UL) + +/* Bit definition for INTC_WUPEN register */ +#define INTC_WUPEN_EIRQWUEN_POS (0U) +#define INTC_WUPEN_EIRQWUEN (0x0000FFFFUL) +#define INTC_WUPEN_EIRQWUEN_0 (0x00000001UL) +#define INTC_WUPEN_EIRQWUEN_1 (0x00000002UL) +#define INTC_WUPEN_EIRQWUEN_2 (0x00000004UL) +#define INTC_WUPEN_EIRQWUEN_3 (0x00000008UL) +#define INTC_WUPEN_EIRQWUEN_4 (0x00000010UL) +#define INTC_WUPEN_EIRQWUEN_5 (0x00000020UL) +#define INTC_WUPEN_EIRQWUEN_6 (0x00000040UL) +#define INTC_WUPEN_EIRQWUEN_7 (0x00000080UL) +#define INTC_WUPEN_EIRQWUEN_8 (0x00000100UL) +#define INTC_WUPEN_EIRQWUEN_9 (0x00000200UL) +#define INTC_WUPEN_EIRQWUEN_10 (0x00000400UL) +#define INTC_WUPEN_EIRQWUEN_11 (0x00000800UL) +#define INTC_WUPEN_EIRQWUEN_12 (0x00001000UL) +#define INTC_WUPEN_EIRQWUEN_13 (0x00002000UL) +#define INTC_WUPEN_EIRQWUEN_14 (0x00004000UL) +#define INTC_WUPEN_EIRQWUEN_15 (0x00008000UL) +#define INTC_WUPEN_SWDTWUEN_POS (16U) +#define INTC_WUPEN_SWDTWUEN (0x00010000UL) +#define INTC_WUPEN_PVD1WUEN_POS (17U) +#define INTC_WUPEN_PVD1WUEN (0x00020000UL) +#define INTC_WUPEN_PVD2WUEN_POS (18U) +#define INTC_WUPEN_PVD2WUEN (0x00040000UL) +#define INTC_WUPEN_CMPI0WUEN_POS (19U) +#define INTC_WUPEN_CMPI0WUEN (0x00080000UL) +#define INTC_WUPEN_WKTMWUEN_POS (20U) +#define INTC_WUPEN_WKTMWUEN (0x00100000UL) +#define INTC_WUPEN_RTCALMWUEN_POS (21U) +#define INTC_WUPEN_RTCALMWUEN (0x00200000UL) +#define INTC_WUPEN_RTCPRDWUEN_POS (22U) +#define INTC_WUPEN_RTCPRDWUEN (0x00400000UL) +#define INTC_WUPEN_TMR0WUEN_POS (23U) +#define INTC_WUPEN_TMR0WUEN (0x00800000UL) +#define INTC_WUPEN_RXWUEN_POS (25U) +#define INTC_WUPEN_RXWUEN (0x02000000UL) + +/* Bit definition for INTC_EIFR register */ +#define INTC_EIFR_EIFR0_POS (0U) +#define INTC_EIFR_EIFR0 (0x00000001UL) +#define INTC_EIFR_EIFR1_POS (1U) +#define INTC_EIFR_EIFR1 (0x00000002UL) +#define INTC_EIFR_EIFR2_POS (2U) +#define INTC_EIFR_EIFR2 (0x00000004UL) +#define INTC_EIFR_EIFR3_POS (3U) +#define INTC_EIFR_EIFR3 (0x00000008UL) +#define INTC_EIFR_EIFR4_POS (4U) +#define INTC_EIFR_EIFR4 (0x00000010UL) +#define INTC_EIFR_EIFR5_POS (5U) +#define INTC_EIFR_EIFR5 (0x00000020UL) +#define INTC_EIFR_EIFR6_POS (6U) +#define INTC_EIFR_EIFR6 (0x00000040UL) +#define INTC_EIFR_EIFR7_POS (7U) +#define INTC_EIFR_EIFR7 (0x00000080UL) +#define INTC_EIFR_EIFR8_POS (8U) +#define INTC_EIFR_EIFR8 (0x00000100UL) +#define INTC_EIFR_EIFR9_POS (9U) +#define INTC_EIFR_EIFR9 (0x00000200UL) +#define INTC_EIFR_EIFR10_POS (10U) +#define INTC_EIFR_EIFR10 (0x00000400UL) +#define INTC_EIFR_EIFR11_POS (11U) +#define INTC_EIFR_EIFR11 (0x00000800UL) +#define INTC_EIFR_EIFR12_POS (12U) +#define INTC_EIFR_EIFR12 (0x00001000UL) +#define INTC_EIFR_EIFR13_POS (13U) +#define INTC_EIFR_EIFR13 (0x00002000UL) +#define INTC_EIFR_EIFR14_POS (14U) +#define INTC_EIFR_EIFR14 (0x00004000UL) +#define INTC_EIFR_EIFR15_POS (15U) +#define INTC_EIFR_EIFR15 (0x00008000UL) + +/* Bit definition for INTC_EIFCR register */ +#define INTC_EIFCR_EIFCR0_POS (0U) +#define INTC_EIFCR_EIFCR0 (0x00000001UL) +#define INTC_EIFCR_EIFCR1_POS (1U) +#define INTC_EIFCR_EIFCR1 (0x00000002UL) +#define INTC_EIFCR_EIFCR2_POS (2U) +#define INTC_EIFCR_EIFCR2 (0x00000004UL) +#define INTC_EIFCR_EIFCR3_POS (3U) +#define INTC_EIFCR_EIFCR3 (0x00000008UL) +#define INTC_EIFCR_EIFCR4_POS (4U) +#define INTC_EIFCR_EIFCR4 (0x00000010UL) +#define INTC_EIFCR_EIFCR5_POS (5U) +#define INTC_EIFCR_EIFCR5 (0x00000020UL) +#define INTC_EIFCR_EIFCR6_POS (6U) +#define INTC_EIFCR_EIFCR6 (0x00000040UL) +#define INTC_EIFCR_EIFCR7_POS (7U) +#define INTC_EIFCR_EIFCR7 (0x00000080UL) +#define INTC_EIFCR_EIFCR8_POS (8U) +#define INTC_EIFCR_EIFCR8 (0x00000100UL) +#define INTC_EIFCR_EIFCR9_POS (9U) +#define INTC_EIFCR_EIFCR9 (0x00000200UL) +#define INTC_EIFCR_EIFCR10_POS (10U) +#define INTC_EIFCR_EIFCR10 (0x00000400UL) +#define INTC_EIFCR_EIFCR11_POS (11U) +#define INTC_EIFCR_EIFCR11 (0x00000800UL) +#define INTC_EIFCR_EIFCR12_POS (12U) +#define INTC_EIFCR_EIFCR12 (0x00001000UL) +#define INTC_EIFCR_EIFCR13_POS (13U) +#define INTC_EIFCR_EIFCR13 (0x00002000UL) +#define INTC_EIFCR_EIFCR14_POS (14U) +#define INTC_EIFCR_EIFCR14 (0x00004000UL) +#define INTC_EIFCR_EIFCR15_POS (15U) +#define INTC_EIFCR_EIFCR15 (0x00008000UL) + +/* Bit definition for INTC_SEL register */ +#define INTC_SEL_INTSEL (0x000001FFUL) +#define INTC_SEL_INTSEL_0 (0x00000001UL) +#define INTC_SEL_INTSEL_1 (0x00000002UL) +#define INTC_SEL_INTSEL_2 (0x00000004UL) +#define INTC_SEL_INTSEL_3 (0x00000008UL) +#define INTC_SEL_INTSEL_4 (0x00000010UL) +#define INTC_SEL_INTSEL_5 (0x00000020UL) +#define INTC_SEL_INTSEL_6 (0x00000040UL) +#define INTC_SEL_INTSEL_7 (0x00000080UL) +#define INTC_SEL_INTSEL_8 (0x00000100UL) + +/* Bit definition for INTC_VSSEL register */ +#define INTC_VSSEL_VSEL0_POS (0U) +#define INTC_VSSEL_VSEL0 (0x00000001UL) +#define INTC_VSSEL_VSEL1_POS (1U) +#define INTC_VSSEL_VSEL1 (0x00000002UL) +#define INTC_VSSEL_VSEL2_POS (2U) +#define INTC_VSSEL_VSEL2 (0x00000004UL) +#define INTC_VSSEL_VSEL3_POS (3U) +#define INTC_VSSEL_VSEL3 (0x00000008UL) +#define INTC_VSSEL_VSEL4_POS (4U) +#define INTC_VSSEL_VSEL4 (0x00000010UL) +#define INTC_VSSEL_VSEL5_POS (5U) +#define INTC_VSSEL_VSEL5 (0x00000020UL) +#define INTC_VSSEL_VSEL6_POS (6U) +#define INTC_VSSEL_VSEL6 (0x00000040UL) +#define INTC_VSSEL_VSEL7_POS (7U) +#define INTC_VSSEL_VSEL7 (0x00000080UL) +#define INTC_VSSEL_VSEL8_POS (8U) +#define INTC_VSSEL_VSEL8 (0x00000100UL) +#define INTC_VSSEL_VSEL9_POS (9U) +#define INTC_VSSEL_VSEL9 (0x00000200UL) +#define INTC_VSSEL_VSEL10_POS (10U) +#define INTC_VSSEL_VSEL10 (0x00000400UL) +#define INTC_VSSEL_VSEL11_POS (11U) +#define INTC_VSSEL_VSEL11 (0x00000800UL) +#define INTC_VSSEL_VSEL12_POS (12U) +#define INTC_VSSEL_VSEL12 (0x00001000UL) +#define INTC_VSSEL_VSEL13_POS (13U) +#define INTC_VSSEL_VSEL13 (0x00002000UL) +#define INTC_VSSEL_VSEL14_POS (14U) +#define INTC_VSSEL_VSEL14 (0x00004000UL) +#define INTC_VSSEL_VSEL15_POS (15U) +#define INTC_VSSEL_VSEL15 (0x00008000UL) +#define INTC_VSSEL_VSEL16_POS (16U) +#define INTC_VSSEL_VSEL16 (0x00010000UL) +#define INTC_VSSEL_VSEL17_POS (17U) +#define INTC_VSSEL_VSEL17 (0x00020000UL) +#define INTC_VSSEL_VSEL18_POS (18U) +#define INTC_VSSEL_VSEL18 (0x00040000UL) +#define INTC_VSSEL_VSEL19_POS (19U) +#define INTC_VSSEL_VSEL19 (0x00080000UL) +#define INTC_VSSEL_VSEL20_POS (20U) +#define INTC_VSSEL_VSEL20 (0x00100000UL) +#define INTC_VSSEL_VSEL21_POS (21U) +#define INTC_VSSEL_VSEL21 (0x00200000UL) +#define INTC_VSSEL_VSEL22_POS (22U) +#define INTC_VSSEL_VSEL22 (0x00400000UL) +#define INTC_VSSEL_VSEL23_POS (23U) +#define INTC_VSSEL_VSEL23 (0x00800000UL) +#define INTC_VSSEL_VSEL24_POS (24U) +#define INTC_VSSEL_VSEL24 (0x01000000UL) +#define INTC_VSSEL_VSEL25_POS (25U) +#define INTC_VSSEL_VSEL25 (0x02000000UL) +#define INTC_VSSEL_VSEL26_POS (26U) +#define INTC_VSSEL_VSEL26 (0x04000000UL) +#define INTC_VSSEL_VSEL27_POS (27U) +#define INTC_VSSEL_VSEL27 (0x08000000UL) +#define INTC_VSSEL_VSEL28_POS (28U) +#define INTC_VSSEL_VSEL28 (0x10000000UL) +#define INTC_VSSEL_VSEL29_POS (29U) +#define INTC_VSSEL_VSEL29 (0x20000000UL) +#define INTC_VSSEL_VSEL30_POS (30U) +#define INTC_VSSEL_VSEL30 (0x40000000UL) +#define INTC_VSSEL_VSEL31_POS (31U) +#define INTC_VSSEL_VSEL31 (0x80000000UL) + +/* Bit definition for INTC_SWIER register */ +#define INTC_SWIER_SWIE0_POS (0U) +#define INTC_SWIER_SWIE0 (0x00000001UL) +#define INTC_SWIER_SWIE1_POS (1U) +#define INTC_SWIER_SWIE1 (0x00000002UL) +#define INTC_SWIER_SWIE2_POS (2U) +#define INTC_SWIER_SWIE2 (0x00000004UL) +#define INTC_SWIER_SWIE3_POS (3U) +#define INTC_SWIER_SWIE3 (0x00000008UL) +#define INTC_SWIER_SWIE4_POS (4U) +#define INTC_SWIER_SWIE4 (0x00000010UL) +#define INTC_SWIER_SWIE5_POS (5U) +#define INTC_SWIER_SWIE5 (0x00000020UL) +#define INTC_SWIER_SWIE6_POS (6U) +#define INTC_SWIER_SWIE6 (0x00000040UL) +#define INTC_SWIER_SWIE7_POS (7U) +#define INTC_SWIER_SWIE7 (0x00000080UL) +#define INTC_SWIER_SWIE8_POS (8U) +#define INTC_SWIER_SWIE8 (0x00000100UL) +#define INTC_SWIER_SWIE9_POS (9U) +#define INTC_SWIER_SWIE9 (0x00000200UL) +#define INTC_SWIER_SWIE10_POS (10U) +#define INTC_SWIER_SWIE10 (0x00000400UL) +#define INTC_SWIER_SWIE11_POS (11U) +#define INTC_SWIER_SWIE11 (0x00000800UL) +#define INTC_SWIER_SWIE12_POS (12U) +#define INTC_SWIER_SWIE12 (0x00001000UL) +#define INTC_SWIER_SWIE13_POS (13U) +#define INTC_SWIER_SWIE13 (0x00002000UL) +#define INTC_SWIER_SWIE14_POS (14U) +#define INTC_SWIER_SWIE14 (0x00004000UL) +#define INTC_SWIER_SWIE15_POS (15U) +#define INTC_SWIER_SWIE15 (0x00008000UL) +#define INTC_SWIER_SWIE16_POS (16U) +#define INTC_SWIER_SWIE16 (0x00010000UL) +#define INTC_SWIER_SWIE17_POS (17U) +#define INTC_SWIER_SWIE17 (0x00020000UL) +#define INTC_SWIER_SWIE18_POS (18U) +#define INTC_SWIER_SWIE18 (0x00040000UL) +#define INTC_SWIER_SWIE19_POS (19U) +#define INTC_SWIER_SWIE19 (0x00080000UL) +#define INTC_SWIER_SWIE20_POS (20U) +#define INTC_SWIER_SWIE20 (0x00100000UL) +#define INTC_SWIER_SWIE21_POS (21U) +#define INTC_SWIER_SWIE21 (0x00200000UL) +#define INTC_SWIER_SWIE22_POS (22U) +#define INTC_SWIER_SWIE22 (0x00400000UL) +#define INTC_SWIER_SWIE23_POS (23U) +#define INTC_SWIER_SWIE23 (0x00800000UL) +#define INTC_SWIER_SWIE24_POS (24U) +#define INTC_SWIER_SWIE24 (0x01000000UL) +#define INTC_SWIER_SWIE25_POS (25U) +#define INTC_SWIER_SWIE25 (0x02000000UL) +#define INTC_SWIER_SWIE26_POS (26U) +#define INTC_SWIER_SWIE26 (0x04000000UL) +#define INTC_SWIER_SWIE27_POS (27U) +#define INTC_SWIER_SWIE27 (0x08000000UL) +#define INTC_SWIER_SWIE28_POS (28U) +#define INTC_SWIER_SWIE28 (0x10000000UL) +#define INTC_SWIER_SWIE29_POS (29U) +#define INTC_SWIER_SWIE29 (0x20000000UL) +#define INTC_SWIER_SWIE30_POS (30U) +#define INTC_SWIER_SWIE30 (0x40000000UL) +#define INTC_SWIER_SWIE31_POS (31U) +#define INTC_SWIER_SWIE31 (0x80000000UL) + +/* Bit definition for INTC_EVTER register */ +#define INTC_EVTER_EVTE0_POS (0U) +#define INTC_EVTER_EVTE0 (0x00000001UL) +#define INTC_EVTER_EVTE1_POS (1U) +#define INTC_EVTER_EVTE1 (0x00000002UL) +#define INTC_EVTER_EVTE2_POS (2U) +#define INTC_EVTER_EVTE2 (0x00000004UL) +#define INTC_EVTER_EVTE3_POS (3U) +#define INTC_EVTER_EVTE3 (0x00000008UL) +#define INTC_EVTER_EVTE4_POS (4U) +#define INTC_EVTER_EVTE4 (0x00000010UL) +#define INTC_EVTER_EVTE5_POS (5U) +#define INTC_EVTER_EVTE5 (0x00000020UL) +#define INTC_EVTER_EVTE6_POS (6U) +#define INTC_EVTER_EVTE6 (0x00000040UL) +#define INTC_EVTER_EVTE7_POS (7U) +#define INTC_EVTER_EVTE7 (0x00000080UL) +#define INTC_EVTER_EVTE8_POS (8U) +#define INTC_EVTER_EVTE8 (0x00000100UL) +#define INTC_EVTER_EVTE9_POS (9U) +#define INTC_EVTER_EVTE9 (0x00000200UL) +#define INTC_EVTER_EVTE10_POS (10U) +#define INTC_EVTER_EVTE10 (0x00000400UL) +#define INTC_EVTER_EVTE11_POS (11U) +#define INTC_EVTER_EVTE11 (0x00000800UL) +#define INTC_EVTER_EVTE12_POS (12U) +#define INTC_EVTER_EVTE12 (0x00001000UL) +#define INTC_EVTER_EVTE13_POS (13U) +#define INTC_EVTER_EVTE13 (0x00002000UL) +#define INTC_EVTER_EVTE14_POS (14U) +#define INTC_EVTER_EVTE14 (0x00004000UL) +#define INTC_EVTER_EVTE15_POS (15U) +#define INTC_EVTER_EVTE15 (0x00008000UL) +#define INTC_EVTER_EVTE16_POS (16U) +#define INTC_EVTER_EVTE16 (0x00010000UL) +#define INTC_EVTER_EVTE17_POS (17U) +#define INTC_EVTER_EVTE17 (0x00020000UL) +#define INTC_EVTER_EVTE18_POS (18U) +#define INTC_EVTER_EVTE18 (0x00040000UL) +#define INTC_EVTER_EVTE19_POS (19U) +#define INTC_EVTER_EVTE19 (0x00080000UL) +#define INTC_EVTER_EVTE20_POS (20U) +#define INTC_EVTER_EVTE20 (0x00100000UL) +#define INTC_EVTER_EVTE21_POS (21U) +#define INTC_EVTER_EVTE21 (0x00200000UL) +#define INTC_EVTER_EVTE22_POS (22U) +#define INTC_EVTER_EVTE22 (0x00400000UL) +#define INTC_EVTER_EVTE23_POS (23U) +#define INTC_EVTER_EVTE23 (0x00800000UL) +#define INTC_EVTER_EVTE24_POS (24U) +#define INTC_EVTER_EVTE24 (0x01000000UL) +#define INTC_EVTER_EVTE25_POS (25U) +#define INTC_EVTER_EVTE25 (0x02000000UL) +#define INTC_EVTER_EVTE26_POS (26U) +#define INTC_EVTER_EVTE26 (0x04000000UL) +#define INTC_EVTER_EVTE27_POS (27U) +#define INTC_EVTER_EVTE27 (0x08000000UL) +#define INTC_EVTER_EVTE28_POS (28U) +#define INTC_EVTER_EVTE28 (0x10000000UL) +#define INTC_EVTER_EVTE29_POS (29U) +#define INTC_EVTER_EVTE29 (0x20000000UL) +#define INTC_EVTER_EVTE30_POS (30U) +#define INTC_EVTER_EVTE30 (0x40000000UL) +#define INTC_EVTER_EVTE31_POS (31U) +#define INTC_EVTER_EVTE31 (0x80000000UL) + +/* Bit definition for INTC_IER register */ +#define INTC_IER_IER0_POS (0U) +#define INTC_IER_IER0 (0x00000001UL) +#define INTC_IER_IER1_POS (1U) +#define INTC_IER_IER1 (0x00000002UL) +#define INTC_IER_IER2_POS (2U) +#define INTC_IER_IER2 (0x00000004UL) +#define INTC_IER_IER3_POS (3U) +#define INTC_IER_IER3 (0x00000008UL) +#define INTC_IER_IER4_POS (4U) +#define INTC_IER_IER4 (0x00000010UL) +#define INTC_IER_IER5_POS (5U) +#define INTC_IER_IER5 (0x00000020UL) +#define INTC_IER_IER6_POS (6U) +#define INTC_IER_IER6 (0x00000040UL) +#define INTC_IER_IER7_POS (7U) +#define INTC_IER_IER7 (0x00000080UL) +#define INTC_IER_IER8_POS (8U) +#define INTC_IER_IER8 (0x00000100UL) +#define INTC_IER_IER9_POS (9U) +#define INTC_IER_IER9 (0x00000200UL) +#define INTC_IER_IER10_POS (10U) +#define INTC_IER_IER10 (0x00000400UL) +#define INTC_IER_IER11_POS (11U) +#define INTC_IER_IER11 (0x00000800UL) +#define INTC_IER_IER12_POS (12U) +#define INTC_IER_IER12 (0x00001000UL) +#define INTC_IER_IER13_POS (13U) +#define INTC_IER_IER13 (0x00002000UL) +#define INTC_IER_IER14_POS (14U) +#define INTC_IER_IER14 (0x00004000UL) +#define INTC_IER_IER15_POS (15U) +#define INTC_IER_IER15 (0x00008000UL) +#define INTC_IER_IER16_POS (16U) +#define INTC_IER_IER16 (0x00010000UL) +#define INTC_IER_IER17_POS (17U) +#define INTC_IER_IER17 (0x00020000UL) +#define INTC_IER_IER18_POS (18U) +#define INTC_IER_IER18 (0x00040000UL) +#define INTC_IER_IER19_POS (19U) +#define INTC_IER_IER19 (0x00080000UL) +#define INTC_IER_IER20_POS (20U) +#define INTC_IER_IER20 (0x00100000UL) +#define INTC_IER_IER21_POS (21U) +#define INTC_IER_IER21 (0x00200000UL) +#define INTC_IER_IER22_POS (22U) +#define INTC_IER_IER22 (0x00400000UL) +#define INTC_IER_IER23_POS (23U) +#define INTC_IER_IER23 (0x00800000UL) +#define INTC_IER_IER24_POS (24U) +#define INTC_IER_IER24 (0x01000000UL) +#define INTC_IER_IER25_POS (25U) +#define INTC_IER_IER25 (0x02000000UL) +#define INTC_IER_IER26_POS (26U) +#define INTC_IER_IER26 (0x04000000UL) +#define INTC_IER_IER27_POS (27U) +#define INTC_IER_IER27 (0x08000000UL) +#define INTC_IER_IER28_POS (28U) +#define INTC_IER_IER28 (0x10000000UL) +#define INTC_IER_IER29_POS (29U) +#define INTC_IER_IER29 (0x20000000UL) +#define INTC_IER_IER30_POS (30U) +#define INTC_IER_IER30 (0x40000000UL) +#define INTC_IER_IER31_POS (31U) +#define INTC_IER_IER31 (0x80000000UL) + +/******************************************************************************* + Bit definition for Peripheral KEYSCAN +*******************************************************************************/ +/* Bit definition for KEYSCAN_SCR register */ +#define KEYSCAN_SCR_KEYINSEL_POS (0U) +#define KEYSCAN_SCR_KEYINSEL (0x0000FFFFUL) +#define KEYSCAN_SCR_KEYOUTSEL_POS (16U) +#define KEYSCAN_SCR_KEYOUTSEL (0x00070000UL) +#define KEYSCAN_SCR_CKSEL_POS (20U) +#define KEYSCAN_SCR_CKSEL (0x00300000UL) +#define KEYSCAN_SCR_CKSEL_0 (0x00100000UL) +#define KEYSCAN_SCR_CKSEL_1 (0x00200000UL) +#define KEYSCAN_SCR_T_LLEVEL_POS (24U) +#define KEYSCAN_SCR_T_LLEVEL (0x1F000000UL) +#define KEYSCAN_SCR_T_HIZ_POS (29U) +#define KEYSCAN_SCR_T_HIZ (0xE0000000UL) + +/* Bit definition for KEYSCAN_SER register */ +#define KEYSCAN_SER_SEN (0x00000001UL) + +/* Bit definition for KEYSCAN_SSR register */ +#define KEYSCAN_SSR_INDEX (0x00000007UL) + +/******************************************************************************* + Bit definition for Peripheral MPU +*******************************************************************************/ +/* Bit definition for MPU_RGD register */ +#define MPU_RGD_MPURGSIZE_POS (0U) +#define MPU_RGD_MPURGSIZE (0x0000001FUL) +#define MPU_RGD_MPURGADDR_POS (5U) +#define MPU_RGD_MPURGADDR (0xFFFFFFE0UL) + +/* Bit definition for MPU_RGCR register */ +#define MPU_RGCR_S2RGRP_POS (0U) +#define MPU_RGCR_S2RGRP (0x00000001UL) +#define MPU_RGCR_S2RGWP_POS (1U) +#define MPU_RGCR_S2RGWP (0x00000002UL) +#define MPU_RGCR_S2RGE_POS (7U) +#define MPU_RGCR_S2RGE (0x00000080UL) +#define MPU_RGCR_S1RGRP_POS (8U) +#define MPU_RGCR_S1RGRP (0x00000100UL) +#define MPU_RGCR_S1RGWP_POS (9U) +#define MPU_RGCR_S1RGWP (0x00000200UL) +#define MPU_RGCR_S1RGE_POS (15U) +#define MPU_RGCR_S1RGE (0x00008000UL) +#define MPU_RGCR_FRGRP_POS (16U) +#define MPU_RGCR_FRGRP (0x00010000UL) +#define MPU_RGCR_FRGWP_POS (17U) +#define MPU_RGCR_FRGWP (0x00020000UL) +#define MPU_RGCR_FRGE_POS (23U) +#define MPU_RGCR_FRGE (0x00800000UL) + +/* Bit definition for MPU_CR register */ +#define MPU_CR_SMPU2BRP_POS (0U) +#define MPU_CR_SMPU2BRP (0x00000001UL) +#define MPU_CR_SMPU2BWP_POS (1U) +#define MPU_CR_SMPU2BWP (0x00000002UL) +#define MPU_CR_SMPU2ACT_POS (2U) +#define MPU_CR_SMPU2ACT (0x0000000CUL) +#define MPU_CR_SMPU2ACT_0 (0x00000004UL) +#define MPU_CR_SMPU2ACT_1 (0x00000008UL) +#define MPU_CR_SMPU2E_POS (7U) +#define MPU_CR_SMPU2E (0x00000080UL) +#define MPU_CR_SMPU1BRP_POS (8U) +#define MPU_CR_SMPU1BRP (0x00000100UL) +#define MPU_CR_SMPU1BWP_POS (9U) +#define MPU_CR_SMPU1BWP (0x00000200UL) +#define MPU_CR_SMPU1ACT_POS (10U) +#define MPU_CR_SMPU1ACT (0x00000C00UL) +#define MPU_CR_SMPU1ACT_0 (0x00000400UL) +#define MPU_CR_SMPU1ACT_1 (0x00000800UL) +#define MPU_CR_SMPU1E_POS (15U) +#define MPU_CR_SMPU1E (0x00008000UL) +#define MPU_CR_FMPUBRP_POS (16U) +#define MPU_CR_FMPUBRP (0x00010000UL) +#define MPU_CR_FMPUBWP_POS (17U) +#define MPU_CR_FMPUBWP (0x00020000UL) +#define MPU_CR_FMPUACT_POS (18U) +#define MPU_CR_FMPUACT (0x000C0000UL) +#define MPU_CR_FMPUACT_0 (0x00040000UL) +#define MPU_CR_FMPUACT_1 (0x00080000UL) +#define MPU_CR_FMPUE_POS (23U) +#define MPU_CR_FMPUE (0x00800000UL) + +/* Bit definition for MPU_SR register */ +#define MPU_SR_SMPU2EAF_POS (0U) +#define MPU_SR_SMPU2EAF (0x00000001UL) +#define MPU_SR_SMPU1EAF_POS (8U) +#define MPU_SR_SMPU1EAF (0x00000100UL) +#define MPU_SR_FMPUEAF_POS (16U) +#define MPU_SR_FMPUEAF (0x00010000UL) + +/* Bit definition for MPU_ECLR register */ +#define MPU_ECLR_SMPU2ECLR_POS (0U) +#define MPU_ECLR_SMPU2ECLR (0x00000001UL) +#define MPU_ECLR_SMPU1ECLR_POS (8U) +#define MPU_ECLR_SMPU1ECLR (0x00000100UL) +#define MPU_ECLR_FMPUECLR_POS (16U) +#define MPU_ECLR_FMPUECLR (0x00010000UL) + +/* Bit definition for MPU_WP register */ +#define MPU_WP_MPUWE_POS (0U) +#define MPU_WP_MPUWE (0x00000001UL) +#define MPU_WP_WKEY_POS (1U) +#define MPU_WP_WKEY (0x0000FFFEUL) + +/* Bit definition for MPU_IPPR register */ +#define MPU_IPPR_AESRDP_POS (0U) +#define MPU_IPPR_AESRDP (0x00000001UL) +#define MPU_IPPR_AESWRP_POS (1U) +#define MPU_IPPR_AESWRP (0x00000002UL) +#define MPU_IPPR_HASHRDP_POS (2U) +#define MPU_IPPR_HASHRDP (0x00000004UL) +#define MPU_IPPR_HASHWRP_POS (3U) +#define MPU_IPPR_HASHWRP (0x00000008UL) +#define MPU_IPPR_TRNGRDP_POS (4U) +#define MPU_IPPR_TRNGRDP (0x00000010UL) +#define MPU_IPPR_TRNGWRP_POS (5U) +#define MPU_IPPR_TRNGWRP (0x00000020UL) +#define MPU_IPPR_CRCRDP_POS (6U) +#define MPU_IPPR_CRCRDP (0x00000040UL) +#define MPU_IPPR_CRCWRP_POS (7U) +#define MPU_IPPR_CRCWRP (0x00000080UL) +#define MPU_IPPR_EFMRDP_POS (8U) +#define MPU_IPPR_EFMRDP (0x00000100UL) +#define MPU_IPPR_EFMWRP_POS (9U) +#define MPU_IPPR_EFMWRP (0x00000200UL) +#define MPU_IPPR_WDTRDP_POS (12U) +#define MPU_IPPR_WDTRDP (0x00001000UL) +#define MPU_IPPR_WDTWRP_POS (13U) +#define MPU_IPPR_WDTWRP (0x00002000UL) +#define MPU_IPPR_SWDTRDP_POS (14U) +#define MPU_IPPR_SWDTRDP (0x00004000UL) +#define MPU_IPPR_SWDTWRP_POS (15U) +#define MPU_IPPR_SWDTWRP (0x00008000UL) +#define MPU_IPPR_BKSRAMRDP_POS (16U) +#define MPU_IPPR_BKSRAMRDP (0x00010000UL) +#define MPU_IPPR_BKSRAMWRP_POS (17U) +#define MPU_IPPR_BKSRAMWRP (0x00020000UL) +#define MPU_IPPR_RTCRDP_POS (18U) +#define MPU_IPPR_RTCRDP (0x00040000UL) +#define MPU_IPPR_RTCWRP_POS (19U) +#define MPU_IPPR_RTCWRP (0x00080000UL) +#define MPU_IPPR_DMPURDP_POS (20U) +#define MPU_IPPR_DMPURDP (0x00100000UL) +#define MPU_IPPR_DMPUWRP_POS (21U) +#define MPU_IPPR_DMPUWRP (0x00200000UL) +#define MPU_IPPR_SRAMCRDP_POS (22U) +#define MPU_IPPR_SRAMCRDP (0x00400000UL) +#define MPU_IPPR_SRAMCWRP_POS (23U) +#define MPU_IPPR_SRAMCWRP (0x00800000UL) +#define MPU_IPPR_INTCRDP_POS (24U) +#define MPU_IPPR_INTCRDP (0x01000000UL) +#define MPU_IPPR_INTCWRP_POS (25U) +#define MPU_IPPR_INTCWRP (0x02000000UL) +#define MPU_IPPR_SYSCRDP_POS (26U) +#define MPU_IPPR_SYSCRDP (0x04000000UL) +#define MPU_IPPR_SYSCWRP_POS (27U) +#define MPU_IPPR_SYSCWRP (0x08000000UL) +#define MPU_IPPR_MSTPRDP_POS (28U) +#define MPU_IPPR_MSTPRDP (0x10000000UL) +#define MPU_IPPR_MSTPWRP_POS (29U) +#define MPU_IPPR_MSTPWRP (0x20000000UL) +#define MPU_IPPR_BUSERRE_POS (31U) +#define MPU_IPPR_BUSERRE (0x80000000UL) + +/******************************************************************************* + Bit definition for Peripheral OTS +*******************************************************************************/ +/* Bit definition for OTS_CTL register */ +#define OTS_CTL_OTSST_POS (0U) +#define OTS_CTL_OTSST (0x0001U) +#define OTS_CTL_OTSCK_POS (1U) +#define OTS_CTL_OTSCK (0x0002U) +#define OTS_CTL_OTSIE_POS (2U) +#define OTS_CTL_OTSIE (0x0004U) +#define OTS_CTL_TSSTP_POS (3U) +#define OTS_CTL_TSSTP (0x0008U) + +/* Bit definition for OTS_DR1 register */ +#define OTS_DR1 (0xFFFFU) + +/* Bit definition for OTS_DR2 register */ +#define OTS_DR2 (0xFFFFU) + +/* Bit definition for OTS_ECR register */ +#define OTS_ECR (0xFFFFU) + +/******************************************************************************* + Bit definition for Peripheral PERIC +*******************************************************************************/ +/* Bit definition for PERIC_USBFS_SYCTLREG register */ +#define PERIC_USBFS_SYCTLREG_DFB_POS (0U) +#define PERIC_USBFS_SYCTLREG_DFB (0x00000001UL) +#define PERIC_USBFS_SYCTLREG_SOFEN_POS (1U) +#define PERIC_USBFS_SYCTLREG_SOFEN (0x00000002UL) + +/* Bit definition for PERIC_SDIOC_SYCTLREG register */ +#define PERIC_SDIOC_SYCTLREG_SELMMC1_POS (1U) +#define PERIC_SDIOC_SYCTLREG_SELMMC1 (0x00000002UL) +#define PERIC_SDIOC_SYCTLREG_SELMMC2_POS (3U) +#define PERIC_SDIOC_SYCTLREG_SELMMC2 (0x00000008UL) + +/******************************************************************************* + Bit definition for Peripheral PWC +*******************************************************************************/ +/* Bit definition for PWC_FCG0 register */ +#define PWC_FCG0_SRAMH_POS (0U) +#define PWC_FCG0_SRAMH (0x00000001UL) +#define PWC_FCG0_SRAM12_POS (4U) +#define PWC_FCG0_SRAM12 (0x00000010UL) +#define PWC_FCG0_SRAM3_POS (8U) +#define PWC_FCG0_SRAM3 (0x00000100UL) +#define PWC_FCG0_SRAMRET_POS (10U) +#define PWC_FCG0_SRAMRET (0x00000400UL) +#define PWC_FCG0_DMA1_POS (14U) +#define PWC_FCG0_DMA1 (0x00004000UL) +#define PWC_FCG0_DMA2_POS (15U) +#define PWC_FCG0_DMA2 (0x00008000UL) +#define PWC_FCG0_FCM_POS (16U) +#define PWC_FCG0_FCM (0x00010000UL) +#define PWC_FCG0_AOS_POS (17U) +#define PWC_FCG0_AOS (0x00020000UL) +#define PWC_FCG0_AES_POS (20U) +#define PWC_FCG0_AES (0x00100000UL) +#define PWC_FCG0_HASH_POS (21U) +#define PWC_FCG0_HASH (0x00200000UL) +#define PWC_FCG0_TRNG_POS (22U) +#define PWC_FCG0_TRNG (0x00400000UL) +#define PWC_FCG0_CRC_POS (23U) +#define PWC_FCG0_CRC (0x00800000UL) +#define PWC_FCG0_DCU1_POS (24U) +#define PWC_FCG0_DCU1 (0x01000000UL) +#define PWC_FCG0_DCU2_POS (25U) +#define PWC_FCG0_DCU2 (0x02000000UL) +#define PWC_FCG0_DCU3_POS (26U) +#define PWC_FCG0_DCU3 (0x04000000UL) +#define PWC_FCG0_DCU4_POS (27U) +#define PWC_FCG0_DCU4 (0x08000000UL) +#define PWC_FCG0_KEY_POS (31U) +#define PWC_FCG0_KEY (0x80000000UL) + +/* Bit definition for PWC_FCG1 register */ +#define PWC_FCG1_CAN_POS (0U) +#define PWC_FCG1_CAN (0x00000001UL) +#define PWC_FCG1_QSPI_POS (3U) +#define PWC_FCG1_QSPI (0x00000008UL) +#define PWC_FCG1_I2C1_POS (4U) +#define PWC_FCG1_I2C1 (0x00000010UL) +#define PWC_FCG1_I2C2_POS (5U) +#define PWC_FCG1_I2C2 (0x00000020UL) +#define PWC_FCG1_I2C3_POS (6U) +#define PWC_FCG1_I2C3 (0x00000040UL) +#define PWC_FCG1_USBFS_POS (8U) +#define PWC_FCG1_USBFS (0x00000100UL) +#define PWC_FCG1_SDIOC1_POS (10U) +#define PWC_FCG1_SDIOC1 (0x00000400UL) +#define PWC_FCG1_SDIOC2_POS (11U) +#define PWC_FCG1_SDIOC2 (0x00000800UL) +#define PWC_FCG1_I2S1_POS (12U) +#define PWC_FCG1_I2S1 (0x00001000UL) +#define PWC_FCG1_I2S2_POS (13U) +#define PWC_FCG1_I2S2 (0x00002000UL) +#define PWC_FCG1_I2S3_POS (14U) +#define PWC_FCG1_I2S3 (0x00004000UL) +#define PWC_FCG1_I2S4_POS (15U) +#define PWC_FCG1_I2S4 (0x00008000UL) +#define PWC_FCG1_SPI1_POS (16U) +#define PWC_FCG1_SPI1 (0x00010000UL) +#define PWC_FCG1_SPI2_POS (17U) +#define PWC_FCG1_SPI2 (0x00020000UL) +#define PWC_FCG1_SPI3_POS (18U) +#define PWC_FCG1_SPI3 (0x00040000UL) +#define PWC_FCG1_SPI4_POS (19U) +#define PWC_FCG1_SPI4 (0x00080000UL) +#define PWC_FCG1_USART1_POS (24U) +#define PWC_FCG1_USART1 (0x01000000UL) +#define PWC_FCG1_USART2_POS (25U) +#define PWC_FCG1_USART2 (0x02000000UL) +#define PWC_FCG1_USART3_POS (26U) +#define PWC_FCG1_USART3 (0x04000000UL) +#define PWC_FCG1_USART4_POS (27U) +#define PWC_FCG1_USART4 (0x08000000UL) + +/* Bit definition for PWC_FCG2 register */ +#define PWC_FCG2_TIMER0_1_POS (0U) +#define PWC_FCG2_TIMER0_1 (0x00000001UL) +#define PWC_FCG2_TIMER0_2_POS (1U) +#define PWC_FCG2_TIMER0_2 (0x00000002UL) +#define PWC_FCG2_TIMERA_1_POS (2U) +#define PWC_FCG2_TIMERA_1 (0x00000004UL) +#define PWC_FCG2_TIMERA_2_POS (3U) +#define PWC_FCG2_TIMERA_2 (0x00000008UL) +#define PWC_FCG2_TIMERA_3_POS (4U) +#define PWC_FCG2_TIMERA_3 (0x00000010UL) +#define PWC_FCG2_TIMERA_4_POS (5U) +#define PWC_FCG2_TIMERA_4 (0x00000020UL) +#define PWC_FCG2_TIMERA_5_POS (6U) +#define PWC_FCG2_TIMERA_5 (0x00000040UL) +#define PWC_FCG2_TIMERA_6_POS (7U) +#define PWC_FCG2_TIMERA_6 (0x00000080UL) +#define PWC_FCG2_TIMER4_1_POS (8U) +#define PWC_FCG2_TIMER4_1 (0x00000100UL) +#define PWC_FCG2_TIMER4_2_POS (9U) +#define PWC_FCG2_TIMER4_2 (0x00000200UL) +#define PWC_FCG2_TIMER4_3_POS (10U) +#define PWC_FCG2_TIMER4_3 (0x00000400UL) +#define PWC_FCG2_EMB_POS (15U) +#define PWC_FCG2_EMB (0x00008000UL) +#define PWC_FCG2_TIMER6_1_POS (16U) +#define PWC_FCG2_TIMER6_1 (0x00010000UL) +#define PWC_FCG2_TIMER6_2_POS (17U) +#define PWC_FCG2_TIMER6_2 (0x00020000UL) +#define PWC_FCG2_TIMER6_3_POS (18U) +#define PWC_FCG2_TIMER6_3 (0x00040000UL) + +/* Bit definition for PWC_FCG3 register */ +#define PWC_FCG3_ADC1_POS (0U) +#define PWC_FCG3_ADC1 (0x00000001UL) +#define PWC_FCG3_ADC2_POS (1U) +#define PWC_FCG3_ADC2 (0x00000002UL) +#define PWC_FCG3_CMP_POS (8U) +#define PWC_FCG3_CMP (0x00000100UL) +#define PWC_FCG3_OTS_POS (12U) +#define PWC_FCG3_OTS (0x00001000UL) + +/* Bit definition for PWC_FCG0PC register */ +#define PWC_FCG0PC_PRT0_POS (0U) +#define PWC_FCG0PC_PRT0 (0x00000001UL) +#define PWC_FCG0PC_FCG0PCWE_POS (16U) +#define PWC_FCG0PC_FCG0PCWE (0xFFFF0000UL) + +/* Bit definition for PWC_WKTCR register */ +#define PWC_WKTCR_WKTMCMP_POS (0U) +#define PWC_WKTCR_WKTMCMP (0x0FFFU) +#define PWC_WKTCR_WKOVF_POS (12U) +#define PWC_WKTCR_WKOVF (0x1000U) +#define PWC_WKTCR_WKCKS_POS (13U) +#define PWC_WKTCR_WKCKS (0x6000U) +#define PWC_WKTCR_WKCKS_0 (0x2000U) +#define PWC_WKTCR_WKCKS_1 (0x4000U) +#define PWC_WKTCR_WKTCE_POS (15U) +#define PWC_WKTCR_WKTCE (0x8000U) + +/* Bit definition for PWC_STPMCR register */ +#define PWC_STPMCR_FLNWT_POS (0U) +#define PWC_STPMCR_FLNWT (0x0001U) +#define PWC_STPMCR_CKSMRC_POS (1U) +#define PWC_STPMCR_CKSMRC (0x0002U) +#define PWC_STPMCR_STOP_POS (15U) +#define PWC_STPMCR_STOP (0x8000U) + +/* Bit definition for PWC_RAMPC0 register */ +#define PWC_RAMPC0_RAMPDC0_POS (0U) +#define PWC_RAMPC0_RAMPDC0 (0x00000001UL) +#define PWC_RAMPC0_RAMPDC1_POS (1U) +#define PWC_RAMPC0_RAMPDC1 (0x00000002UL) +#define PWC_RAMPC0_RAMPDC2_POS (2U) +#define PWC_RAMPC0_RAMPDC2 (0x00000004UL) +#define PWC_RAMPC0_RAMPDC3_POS (3U) +#define PWC_RAMPC0_RAMPDC3 (0x00000008UL) +#define PWC_RAMPC0_RAMPDC4_POS (4U) +#define PWC_RAMPC0_RAMPDC4 (0x00000010UL) +#define PWC_RAMPC0_RAMPDC5_POS (5U) +#define PWC_RAMPC0_RAMPDC5 (0x00000020UL) +#define PWC_RAMPC0_RAMPDC6_POS (6U) +#define PWC_RAMPC0_RAMPDC6 (0x00000040UL) +#define PWC_RAMPC0_RAMPDC7_POS (7U) +#define PWC_RAMPC0_RAMPDC7 (0x00000080UL) +#define PWC_RAMPC0_RAMPDC8_POS (8U) +#define PWC_RAMPC0_RAMPDC8 (0x00000100UL) + +/* Bit definition for PWC_RAMOPM register */ +#define PWC_RAMOPM (0xFFFFU) + +/* Bit definition for PWC_PVDICR register */ +#define PWC_PVDICR_PVD1NMIS_POS (0U) +#define PWC_PVDICR_PVD1NMIS (0x01U) +#define PWC_PVDICR_PVD2NMIS_POS (4U) +#define PWC_PVDICR_PVD2NMIS (0x10U) + +/* Bit definition for PWC_PVDDSR register */ +#define PWC_PVDDSR_PVD1MON_POS (0U) +#define PWC_PVDDSR_PVD1MON (0x01U) +#define PWC_PVDDSR_PVD1DETFLG_POS (1U) +#define PWC_PVDDSR_PVD1DETFLG (0x02U) +#define PWC_PVDDSR_PVD2MON_POS (4U) +#define PWC_PVDDSR_PVD2MON (0x10U) +#define PWC_PVDDSR_PVD2DETFLG_POS (5U) +#define PWC_PVDDSR_PVD2DETFLG (0x20U) + +/* Bit definition for PWC_FPRC register */ +#define PWC_FPRC_FPRCB0_POS (0U) +#define PWC_FPRC_FPRCB0 (0x0001U) +#define PWC_FPRC_FPRCB1_POS (1U) +#define PWC_FPRC_FPRCB1 (0x0002U) +#define PWC_FPRC_FPRCB2_POS (2U) +#define PWC_FPRC_FPRCB2 (0x0004U) +#define PWC_FPRC_FPRCB3_POS (3U) +#define PWC_FPRC_FPRCB3 (0x0008U) +#define PWC_FPRC_FPRCWE_POS (8U) +#define PWC_FPRC_FPRCWE (0xFF00U) + +/* Bit definition for PWC_PWRC0 register */ +#define PWC_PWRC0_PDMDS_POS (0U) +#define PWC_PWRC0_PDMDS (0x03U) +#define PWC_PWRC0_PDMDS_0 (0x01U) +#define PWC_PWRC0_PDMDS_1 (0x02U) +#define PWC_PWRC0_VVDRSD_POS (2U) +#define PWC_PWRC0_VVDRSD (0x04U) +#define PWC_PWRC0_RETRAMSD_POS (3U) +#define PWC_PWRC0_RETRAMSD (0x08U) +#define PWC_PWRC0_IORTN_POS (4U) +#define PWC_PWRC0_IORTN (0x30U) +#define PWC_PWRC0_IORTN_0 (0x10U) +#define PWC_PWRC0_IORTN_1 (0x20U) +#define PWC_PWRC0_PWDN_POS (7U) +#define PWC_PWRC0_PWDN (0x80U) + +/* Bit definition for PWC_PWRC1 register */ +#define PWC_PWRC1_VPLLSD_POS (0U) +#define PWC_PWRC1_VPLLSD (0x01U) +#define PWC_PWRC1_VHRCSD_POS (1U) +#define PWC_PWRC1_VHRCSD (0x02U) +#define PWC_PWRC1_STPDAS_POS (6U) +#define PWC_PWRC1_STPDAS (0xC0U) +#define PWC_PWRC1_STPDAS_0 (0x40U) +#define PWC_PWRC1_STPDAS_1 (0x80U) + +/* Bit definition for PWC_PWRC2 register */ +#define PWC_PWRC2_DDAS_POS (0U) +#define PWC_PWRC2_DDAS (0x0FU) +#define PWC_PWRC2_DDAS_0 (0x01U) +#define PWC_PWRC2_DDAS_1 (0x02U) +#define PWC_PWRC2_DDAS_2 (0x04U) +#define PWC_PWRC2_DDAS_3 (0x08U) +#define PWC_PWRC2_DVS_POS (4U) +#define PWC_PWRC2_DVS (0x30U) +#define PWC_PWRC2_DVS_0 (0x10U) +#define PWC_PWRC2_DVS_1 (0x20U) + +/* Bit definition for PWC_PWRC3 register */ +#define PWC_PWRC3_PDTS_POS (2U) +#define PWC_PWRC3_PDTS (0x04U) + +/* Bit definition for PWC_PDWKE0 register */ +#define PWC_PDWKE0_WKE00_POS (0U) +#define PWC_PDWKE0_WKE00 (0x01U) +#define PWC_PDWKE0_WKE01_POS (1U) +#define PWC_PDWKE0_WKE01 (0x02U) +#define PWC_PDWKE0_WKE02_POS (2U) +#define PWC_PDWKE0_WKE02 (0x04U) +#define PWC_PDWKE0_WKE03_POS (3U) +#define PWC_PDWKE0_WKE03 (0x08U) +#define PWC_PDWKE0_WKE10_POS (4U) +#define PWC_PDWKE0_WKE10 (0x10U) +#define PWC_PDWKE0_WKE11_POS (5U) +#define PWC_PDWKE0_WKE11 (0x20U) +#define PWC_PDWKE0_WKE12_POS (6U) +#define PWC_PDWKE0_WKE12 (0x40U) +#define PWC_PDWKE0_WKE13_POS (7U) +#define PWC_PDWKE0_WKE13 (0x80U) + +/* Bit definition for PWC_PDWKE1 register */ +#define PWC_PDWKE1_WKE20_POS (0U) +#define PWC_PDWKE1_WKE20 (0x01U) +#define PWC_PDWKE1_WKE21_POS (1U) +#define PWC_PDWKE1_WKE21 (0x02U) +#define PWC_PDWKE1_WKE22_POS (2U) +#define PWC_PDWKE1_WKE22 (0x04U) +#define PWC_PDWKE1_WKE23_POS (3U) +#define PWC_PDWKE1_WKE23 (0x08U) +#define PWC_PDWKE1_WKE30_POS (4U) +#define PWC_PDWKE1_WKE30 (0x10U) +#define PWC_PDWKE1_WKE31_POS (5U) +#define PWC_PDWKE1_WKE31 (0x20U) +#define PWC_PDWKE1_WKE32_POS (6U) +#define PWC_PDWKE1_WKE32 (0x40U) +#define PWC_PDWKE1_WKE33_POS (7U) +#define PWC_PDWKE1_WKE33 (0x80U) + +/* Bit definition for PWC_PDWKE2 register */ +#define PWC_PDWKE2_VD1WKE_POS (0U) +#define PWC_PDWKE2_VD1WKE (0x01U) +#define PWC_PDWKE2_VD2WKE_POS (1U) +#define PWC_PDWKE2_VD2WKE (0x02U) +#define PWC_PDWKE2_NMIWKE_POS (2U) +#define PWC_PDWKE2_NMIWKE (0x04U) +#define PWC_PDWKE2_RTCPRDWKE_POS (4U) +#define PWC_PDWKE2_RTCPRDWKE (0x10U) +#define PWC_PDWKE2_RTCALMWKE_POS (5U) +#define PWC_PDWKE2_RTCALMWKE (0x20U) +#define PWC_PDWKE2_WKTMWKE_POS (7U) +#define PWC_PDWKE2_WKTMWKE (0x80U) + +/* Bit definition for PWC_PDWKES register */ +#define PWC_PDWKES_WK0EGS_POS (0U) +#define PWC_PDWKES_WK0EGS (0x01U) +#define PWC_PDWKES_WK1EGS_POS (1U) +#define PWC_PDWKES_WK1EGS (0x02U) +#define PWC_PDWKES_WK2EGS_POS (2U) +#define PWC_PDWKES_WK2EGS (0x04U) +#define PWC_PDWKES_WK3EGS_POS (3U) +#define PWC_PDWKES_WK3EGS (0x08U) +#define PWC_PDWKES_VD1EGS_POS (4U) +#define PWC_PDWKES_VD1EGS (0x10U) +#define PWC_PDWKES_VD2EGS_POS (5U) +#define PWC_PDWKES_VD2EGS (0x20U) +#define PWC_PDWKES_NMIEGS_POS (6U) +#define PWC_PDWKES_NMIEGS (0x40U) + +/* Bit definition for PWC_PDWKF0 register */ +#define PWC_PDWKF0_PTWK0F_POS (0U) +#define PWC_PDWKF0_PTWK0F (0x01U) +#define PWC_PDWKF0_PTWK1F_POS (1U) +#define PWC_PDWKF0_PTWK1F (0x02U) +#define PWC_PDWKF0_PTWK2F_POS (2U) +#define PWC_PDWKF0_PTWK2F (0x04U) +#define PWC_PDWKF0_PTWK3F_POS (3U) +#define PWC_PDWKF0_PTWK3F (0x08U) +#define PWC_PDWKF0_VD1WKF_POS (4U) +#define PWC_PDWKF0_VD1WKF (0x10U) +#define PWC_PDWKF0_VD2WKF_POS (5U) +#define PWC_PDWKF0_VD2WKF (0x20U) +#define PWC_PDWKF0_NMIWKF_POS (6U) +#define PWC_PDWKF0_NMIWKF (0x40U) + +/* Bit definition for PWC_PDWKF1 register */ +#define PWC_PDWKF1_RTCPRDWKF_POS (4U) +#define PWC_PDWKF1_RTCPRDWKF (0x10U) +#define PWC_PDWKF1_RTCALMWKF_POS (5U) +#define PWC_PDWKF1_RTCALMWKF (0x20U) +#define PWC_PDWKF1_WKTMWKF_POS (7U) +#define PWC_PDWKF1_WKTMWKF (0x80U) + +/* Bit definition for PWC_PWCMR register */ +#define PWC_PWCMR_ADBUFE_POS (7U) +#define PWC_PWCMR_ADBUFE (0x80U) + +/* Bit definition for PWC_MDSWCR register */ +#define PWC_MDSWCR (0xFFU) + +/* Bit definition for PWC_PVDCR0 register */ +#define PWC_PVDCR0_EXVCCINEN_POS (0U) +#define PWC_PVDCR0_EXVCCINEN (0x01U) +#define PWC_PVDCR0_PVD1EN_POS (5U) +#define PWC_PVDCR0_PVD1EN (0x20U) +#define PWC_PVDCR0_PVD2EN_POS (6U) +#define PWC_PVDCR0_PVD2EN (0x40U) + +/* Bit definition for PWC_PVDCR1 register */ +#define PWC_PVDCR1_PVD1IRE_POS (0U) +#define PWC_PVDCR1_PVD1IRE (0x01U) +#define PWC_PVDCR1_PVD1IRS_POS (1U) +#define PWC_PVDCR1_PVD1IRS (0x02U) +#define PWC_PVDCR1_PVD1CMPOE_POS (2U) +#define PWC_PVDCR1_PVD1CMPOE (0x04U) +#define PWC_PVDCR1_PVD2IRE_POS (4U) +#define PWC_PVDCR1_PVD2IRE (0x10U) +#define PWC_PVDCR1_PVD2IRS_POS (5U) +#define PWC_PVDCR1_PVD2IRS (0x20U) +#define PWC_PVDCR1_PVD2CMPOE_POS (6U) +#define PWC_PVDCR1_PVD2CMPOE (0x40U) + +/* Bit definition for PWC_PVDFCR register */ +#define PWC_PVDFCR_PVD1NFDIS_POS (0U) +#define PWC_PVDFCR_PVD1NFDIS (0x01U) +#define PWC_PVDFCR_PVD1NFCKS_POS (1U) +#define PWC_PVDFCR_PVD1NFCKS (0x06U) +#define PWC_PVDFCR_PVD1NFCKS_0 (0x02U) +#define PWC_PVDFCR_PVD1NFCKS_1 (0x04U) +#define PWC_PVDFCR_PVD2NFDIS_POS (4U) +#define PWC_PVDFCR_PVD2NFDIS (0x10U) +#define PWC_PVDFCR_PVD2NFCKS_POS (5U) +#define PWC_PVDFCR_PVD2NFCKS (0x60U) +#define PWC_PVDFCR_PVD2NFCKS_0 (0x20U) +#define PWC_PVDFCR_PVD2NFCKS_1 (0x40U) + +/* Bit definition for PWC_PVDLCR register */ +#define PWC_PVDLCR_PVD1LVL_POS (0U) +#define PWC_PVDLCR_PVD1LVL (0x07U) +#define PWC_PVDLCR_PVD1LVL_0 (0x01U) +#define PWC_PVDLCR_PVD1LVL_1 (0x02U) +#define PWC_PVDLCR_PVD1LVL_2 (0x04U) +#define PWC_PVDLCR_PVD2LVL_POS (4U) +#define PWC_PVDLCR_PVD2LVL (0x70U) +#define PWC_PVDLCR_PVD2LVL_0 (0x10U) +#define PWC_PVDLCR_PVD2LVL_1 (0x20U) +#define PWC_PVDLCR_PVD2LVL_2 (0x40U) + +/* Bit definition for PWC_XTAL32CS register */ +#define PWC_XTAL32CS_CSDIS_POS (7U) +#define PWC_XTAL32CS_CSDIS (0x80U) + +/******************************************************************************* + Bit definition for Peripheral QSPI +*******************************************************************************/ +/* Bit definition for QSPI_CR register */ +#define QSPI_CR_MDSEL_POS (0U) +#define QSPI_CR_MDSEL (0x00000007UL) +#define QSPI_CR_PFE_POS (3U) +#define QSPI_CR_PFE (0x00000008UL) +#define QSPI_CR_PFSAE_POS (4U) +#define QSPI_CR_PFSAE (0x00000010UL) +#define QSPI_CR_DCOME_POS (5U) +#define QSPI_CR_DCOME (0x00000020UL) +#define QSPI_CR_XIPE_POS (6U) +#define QSPI_CR_XIPE (0x00000040UL) +#define QSPI_CR_SPIMD3_POS (7U) +#define QSPI_CR_SPIMD3 (0x00000080UL) +#define QSPI_CR_IPRSL_POS (8U) +#define QSPI_CR_IPRSL (0x00000300UL) +#define QSPI_CR_IPRSL_0 (0x00000100UL) +#define QSPI_CR_IPRSL_1 (0x00000200UL) +#define QSPI_CR_APRSL_POS (10U) +#define QSPI_CR_APRSL (0x00000C00UL) +#define QSPI_CR_APRSL_0 (0x00000400UL) +#define QSPI_CR_APRSL_1 (0x00000800UL) +#define QSPI_CR_DPRSL_POS (12U) +#define QSPI_CR_DPRSL (0x00003000UL) +#define QSPI_CR_DPRSL_0 (0x00001000UL) +#define QSPI_CR_DPRSL_1 (0x00002000UL) +#define QSPI_CR_DIV_POS (16U) +#define QSPI_CR_DIV (0x003F0000UL) + +/* Bit definition for QSPI_CSCR register */ +#define QSPI_CSCR_SSHW_POS (0U) +#define QSPI_CSCR_SSHW (0x0000000FUL) +#define QSPI_CSCR_SSNW_POS (4U) +#define QSPI_CSCR_SSNW (0x00000030UL) +#define QSPI_CSCR_SSNW_0 (0x00000010UL) +#define QSPI_CSCR_SSNW_1 (0x00000020UL) + +/* Bit definition for QSPI_FCR register */ +#define QSPI_FCR_AWSL_POS (0U) +#define QSPI_FCR_AWSL (0x00000003UL) +#define QSPI_FCR_AWSL_0 (0x00000001UL) +#define QSPI_FCR_AWSL_1 (0x00000002UL) +#define QSPI_FCR_FOUR_BIC_POS (2U) +#define QSPI_FCR_FOUR_BIC (0x00000004UL) +#define QSPI_FCR_SSNHD_POS (4U) +#define QSPI_FCR_SSNHD (0x00000010UL) +#define QSPI_FCR_SSNLD_POS (5U) +#define QSPI_FCR_SSNLD (0x00000020UL) +#define QSPI_FCR_WPOL_POS (6U) +#define QSPI_FCR_WPOL (0x00000040UL) +#define QSPI_FCR_DMCYCN_POS (8U) +#define QSPI_FCR_DMCYCN (0x00000F00UL) +#define QSPI_FCR_DUTY_POS (15U) +#define QSPI_FCR_DUTY (0x00008000UL) + +/* Bit definition for QSPI_SR register */ +#define QSPI_SR_BUSY_POS (0U) +#define QSPI_SR_BUSY (0x00000001UL) +#define QSPI_SR_XIPF_POS (6U) +#define QSPI_SR_XIPF (0x00000040UL) +#define QSPI_SR_RAER_POS (7U) +#define QSPI_SR_RAER (0x00000080UL) +#define QSPI_SR_PFNUM_POS (8U) +#define QSPI_SR_PFNUM (0x00001F00UL) +#define QSPI_SR_PFFUL_POS (14U) +#define QSPI_SR_PFFUL (0x00004000UL) +#define QSPI_SR_PFAN_POS (15U) +#define QSPI_SR_PFAN (0x00008000UL) + +/* Bit definition for QSPI_DCOM register */ +#define QSPI_DCOM_DCOM (0x000000FFUL) + +/* Bit definition for QSPI_CCMD register */ +#define QSPI_CCMD_RIC (0x000000FFUL) + +/* Bit definition for QSPI_XCMD register */ +#define QSPI_XCMD_XIPMC (0x000000FFUL) + +/* Bit definition for QSPI_CLR register */ +#define QSPI_CLR_RAERCLR_POS (7U) +#define QSPI_CLR_RAERCLR (0x00000080UL) + +/* Bit definition for QSPI_EXAR register */ +#define QSPI_EXAR_EXADR_POS (26U) +#define QSPI_EXAR_EXADR (0xFC000000UL) + +/******************************************************************************* + Bit definition for Peripheral RMU +*******************************************************************************/ +/* Bit definition for RMU_RSTF0 register */ +#define RMU_RSTF0_PORF_POS (0U) +#define RMU_RSTF0_PORF (0x0001U) +#define RMU_RSTF0_PINRF_POS (1U) +#define RMU_RSTF0_PINRF (0x0002U) +#define RMU_RSTF0_BORF_POS (2U) +#define RMU_RSTF0_BORF (0x0004U) +#define RMU_RSTF0_PVD1RF_POS (3U) +#define RMU_RSTF0_PVD1RF (0x0008U) +#define RMU_RSTF0_PVD2RF_POS (4U) +#define RMU_RSTF0_PVD2RF (0x0010U) +#define RMU_RSTF0_WDRF_POS (5U) +#define RMU_RSTF0_WDRF (0x0020U) +#define RMU_RSTF0_SWDRF_POS (6U) +#define RMU_RSTF0_SWDRF (0x0040U) +#define RMU_RSTF0_PDRF_POS (7U) +#define RMU_RSTF0_PDRF (0x0080U) +#define RMU_RSTF0_SWRF_POS (8U) +#define RMU_RSTF0_SWRF (0x0100U) +#define RMU_RSTF0_MPUERF_POS (9U) +#define RMU_RSTF0_MPUERF (0x0200U) +#define RMU_RSTF0_RAPERF_POS (10U) +#define RMU_RSTF0_RAPERF (0x0400U) +#define RMU_RSTF0_RAECRF_POS (11U) +#define RMU_RSTF0_RAECRF (0x0800U) +#define RMU_RSTF0_CKFERF_POS (12U) +#define RMU_RSTF0_CKFERF (0x1000U) +#define RMU_RSTF0_XTALERF_POS (13U) +#define RMU_RSTF0_XTALERF (0x2000U) +#define RMU_RSTF0_MULTIRF_POS (14U) +#define RMU_RSTF0_MULTIRF (0x4000U) +#define RMU_RSTF0_CLRF_POS (15U) +#define RMU_RSTF0_CLRF (0x8000U) + +/******************************************************************************* + Bit definition for Peripheral RTC +*******************************************************************************/ +/* Bit definition for RTC_CR0 register */ +#define RTC_CR0_RESET (0x01U) + +/* Bit definition for RTC_CR1 register */ +#define RTC_CR1_PRDS_POS (0U) +#define RTC_CR1_PRDS (0x07U) +#define RTC_CR1_AMPM_POS (3U) +#define RTC_CR1_AMPM (0x08U) +#define RTC_CR1_ALMFCLR_POS (4U) +#define RTC_CR1_ALMFCLR (0x10U) +#define RTC_CR1_ONEHZOE_POS (5U) +#define RTC_CR1_ONEHZOE (0x20U) +#define RTC_CR1_ONEHZSEL_POS (6U) +#define RTC_CR1_ONEHZSEL (0x40U) +#define RTC_CR1_START_POS (7U) +#define RTC_CR1_START (0x80U) + +/* Bit definition for RTC_CR2 register */ +#define RTC_CR2_RWREQ_POS (0U) +#define RTC_CR2_RWREQ (0x01U) +#define RTC_CR2_RWEN_POS (1U) +#define RTC_CR2_RWEN (0x02U) +#define RTC_CR2_ALMF_POS (3U) +#define RTC_CR2_ALMF (0x08U) +#define RTC_CR2_PRDIE_POS (5U) +#define RTC_CR2_PRDIE (0x20U) +#define RTC_CR2_ALMIE_POS (6U) +#define RTC_CR2_ALMIE (0x40U) +#define RTC_CR2_ALME_POS (7U) +#define RTC_CR2_ALME (0x80U) + +/* Bit definition for RTC_CR3 register */ +#define RTC_CR3_LRCEN_POS (4U) +#define RTC_CR3_LRCEN (0x10U) +#define RTC_CR3_RCKSEL_POS (7U) +#define RTC_CR3_RCKSEL (0x80U) + +/* Bit definition for RTC_SEC register */ +#define RTC_SEC_SECU_POS (0U) +#define RTC_SEC_SECU (0x0FU) +#define RTC_SEC_SECD_POS (4U) +#define RTC_SEC_SECD (0x70U) + +/* Bit definition for RTC_MIN register */ +#define RTC_MIN_MINU_POS (0U) +#define RTC_MIN_MINU (0x0FU) +#define RTC_MIN_MIND_POS (4U) +#define RTC_MIN_MIND (0x70U) + +/* Bit definition for RTC_HOUR register */ +#define RTC_HOUR_HOURU_POS (0U) +#define RTC_HOUR_HOURU (0x0FU) +#define RTC_HOUR_HOURU_0 (0x01U) +#define RTC_HOUR_HOURU_1 (0x02U) +#define RTC_HOUR_HOURU_2 (0x04U) +#define RTC_HOUR_HOURU_3 (0x08U) +#define RTC_HOUR_HOURD_POS (4U) +#define RTC_HOUR_HOURD (0x30U) +#define RTC_HOUR_HOURD_0 (0x10U) +#define RTC_HOUR_HOURD_1 (0x20U) + +/* Bit definition for RTC_WEEK register */ +#define RTC_WEEK_WEEK (0x07U) + +/* Bit definition for RTC_DAY register */ +#define RTC_DAY_DAYU_POS (0U) +#define RTC_DAY_DAYU (0x0FU) +#define RTC_DAY_DAYD_POS (4U) +#define RTC_DAY_DAYD (0x30U) + +/* Bit definition for RTC_MON register */ +#define RTC_MON_MON (0x1FU) + +/* Bit definition for RTC_YEAR register */ +#define RTC_YEAR_YEARU_POS (0U) +#define RTC_YEAR_YEARU (0x0FU) +#define RTC_YEAR_YEARD_POS (4U) +#define RTC_YEAR_YEARD (0xF0U) + +/* Bit definition for RTC_ALMMIN register */ +#define RTC_ALMMIN_ALMMINU_POS (0U) +#define RTC_ALMMIN_ALMMINU (0x0FU) +#define RTC_ALMMIN_ALMMIND_POS (4U) +#define RTC_ALMMIN_ALMMIND (0x70U) + +/* Bit definition for RTC_ALMHOUR register */ +#define RTC_ALMHOUR_ALMHOURU_POS (0U) +#define RTC_ALMHOUR_ALMHOURU (0x0FU) +#define RTC_ALMHOUR_ALMHOURD_POS (4U) +#define RTC_ALMHOUR_ALMHOURD (0x30U) +#define RTC_ALMHOUR_ALMHOURD_0 (0x10U) +#define RTC_ALMHOUR_ALMHOURD_1 (0x20U) + +/* Bit definition for RTC_ALMWEEK register */ +#define RTC_ALMWEEK_ALMWEEK (0x7FU) +#define RTC_ALMWEEK_ALMWEEK_0 (0x01U) +#define RTC_ALMWEEK_ALMWEEK_1 (0x02U) +#define RTC_ALMWEEK_ALMWEEK_2 (0x04U) +#define RTC_ALMWEEK_ALMWEEK_3 (0x08U) +#define RTC_ALMWEEK_ALMWEEK_4 (0x10U) +#define RTC_ALMWEEK_ALMWEEK_5 (0x20U) +#define RTC_ALMWEEK_ALMWEEK_6 (0x40U) + +/* Bit definition for RTC_ERRCRH register */ +#define RTC_ERRCRH_COMP8_POS (0U) +#define RTC_ERRCRH_COMP8 (0x01U) +#define RTC_ERRCRH_COMPEN_POS (7U) +#define RTC_ERRCRH_COMPEN (0x80U) + +/* Bit definition for RTC_ERRCRL register */ +#define RTC_ERRCRL_COMP (0xFFU) + +/******************************************************************************* + Bit definition for Peripheral SDIOC +*******************************************************************************/ +/* Bit definition for SDIOC_BLKSIZE register */ +#define SDIOC_BLKSIZE_TBS (0x0FFFU) + +/* Bit definition for SDIOC_BLKCNT register */ +#define SDIOC_BLKCNT (0xFFFFU) + +/* Bit definition for SDIOC_ARG0 register */ +#define SDIOC_ARG0 (0xFFFFU) + +/* Bit definition for SDIOC_ARG1 register */ +#define SDIOC_ARG1 (0xFFFFU) + +/* Bit definition for SDIOC_TRANSMODE register */ +#define SDIOC_TRANSMODE_BCE_POS (1U) +#define SDIOC_TRANSMODE_BCE (0x0002U) +#define SDIOC_TRANSMODE_ATCEN_POS (2U) +#define SDIOC_TRANSMODE_ATCEN (0x000CU) +#define SDIOC_TRANSMODE_ATCEN_0 (0x0004U) +#define SDIOC_TRANSMODE_ATCEN_1 (0x0008U) +#define SDIOC_TRANSMODE_DDIR_POS (4U) +#define SDIOC_TRANSMODE_DDIR (0x0010U) +#define SDIOC_TRANSMODE_MULB_POS (5U) +#define SDIOC_TRANSMODE_MULB (0x0020U) + +/* Bit definition for SDIOC_CMD register */ +#define SDIOC_CMD_RESTYP_POS (0U) +#define SDIOC_CMD_RESTYP (0x0003U) +#define SDIOC_CMD_RESTYP_0 (0x0001U) +#define SDIOC_CMD_RESTYP_1 (0x0002U) +#define SDIOC_CMD_CCE_POS (3U) +#define SDIOC_CMD_CCE (0x0008U) +#define SDIOC_CMD_ICE_POS (4U) +#define SDIOC_CMD_ICE (0x0010U) +#define SDIOC_CMD_DAT_POS (5U) +#define SDIOC_CMD_DAT (0x0020U) +#define SDIOC_CMD_TYP_POS (6U) +#define SDIOC_CMD_TYP (0x00C0U) +#define SDIOC_CMD_TYP_0 (0x0040U) +#define SDIOC_CMD_TYP_1 (0x0080U) +#define SDIOC_CMD_IDX_POS (8U) +#define SDIOC_CMD_IDX (0x3F00U) + +/* Bit definition for SDIOC_RESP0 register */ +#define SDIOC_RESP0 (0xFFFFU) + +/* Bit definition for SDIOC_RESP1 register */ +#define SDIOC_RESP1 (0xFFFFU) + +/* Bit definition for SDIOC_RESP2 register */ +#define SDIOC_RESP2 (0xFFFFU) + +/* Bit definition for SDIOC_RESP3 register */ +#define SDIOC_RESP3 (0xFFFFU) + +/* Bit definition for SDIOC_RESP4 register */ +#define SDIOC_RESP4 (0xFFFFU) + +/* Bit definition for SDIOC_RESP5 register */ +#define SDIOC_RESP5 (0xFFFFU) + +/* Bit definition for SDIOC_RESP6 register */ +#define SDIOC_RESP6 (0xFFFFU) + +/* Bit definition for SDIOC_RESP7 register */ +#define SDIOC_RESP7 (0xFFFFU) + +/* Bit definition for SDIOC_BUF0 register */ +#define SDIOC_BUF0 (0xFFFFU) + +/* Bit definition for SDIOC_BUF1 register */ +#define SDIOC_BUF1 (0xFFFFU) + +/* Bit definition for SDIOC_PSTAT register */ +#define SDIOC_PSTAT_CIC_POS (0U) +#define SDIOC_PSTAT_CIC (0x00000001UL) +#define SDIOC_PSTAT_CID_POS (1U) +#define SDIOC_PSTAT_CID (0x00000002UL) +#define SDIOC_PSTAT_DA_POS (2U) +#define SDIOC_PSTAT_DA (0x00000004UL) +#define SDIOC_PSTAT_WTA_POS (8U) +#define SDIOC_PSTAT_WTA (0x00000100UL) +#define SDIOC_PSTAT_RTA_POS (9U) +#define SDIOC_PSTAT_RTA (0x00000200UL) +#define SDIOC_PSTAT_BWE_POS (10U) +#define SDIOC_PSTAT_BWE (0x00000400UL) +#define SDIOC_PSTAT_BRE_POS (11U) +#define SDIOC_PSTAT_BRE (0x00000800UL) +#define SDIOC_PSTAT_CIN_POS (16U) +#define SDIOC_PSTAT_CIN (0x00010000UL) +#define SDIOC_PSTAT_CSS_POS (17U) +#define SDIOC_PSTAT_CSS (0x00020000UL) +#define SDIOC_PSTAT_CDL_POS (18U) +#define SDIOC_PSTAT_CDL (0x00040000UL) +#define SDIOC_PSTAT_WPL_POS (19U) +#define SDIOC_PSTAT_WPL (0x00080000UL) +#define SDIOC_PSTAT_DATL_POS (20U) +#define SDIOC_PSTAT_DATL (0x00F00000UL) +#define SDIOC_PSTAT_DATL_0 (0x00100000UL) +#define SDIOC_PSTAT_DATL_1 (0x00200000UL) +#define SDIOC_PSTAT_DATL_2 (0x00400000UL) +#define SDIOC_PSTAT_DATL_3 (0x00800000UL) +#define SDIOC_PSTAT_CMDL_POS (24U) +#define SDIOC_PSTAT_CMDL (0x01000000UL) + +/* Bit definition for SDIOC_HOSTCON register */ +#define SDIOC_HOSTCON_DW_POS (1U) +#define SDIOC_HOSTCON_DW (0x02U) +#define SDIOC_HOSTCON_HSEN_POS (2U) +#define SDIOC_HOSTCON_HSEN (0x04U) +#define SDIOC_HOSTCON_EXDW_POS (5U) +#define SDIOC_HOSTCON_EXDW (0x20U) +#define SDIOC_HOSTCON_CDTL_POS (6U) +#define SDIOC_HOSTCON_CDTL (0x40U) +#define SDIOC_HOSTCON_CDSS_POS (7U) +#define SDIOC_HOSTCON_CDSS (0x80U) + +/* Bit definition for SDIOC_PWRCON register */ +#define SDIOC_PWRCON_PWON (0x01U) + +/* Bit definition for SDIOC_BLKGPCON register */ +#define SDIOC_BLKGPCON_SABGR_POS (0U) +#define SDIOC_BLKGPCON_SABGR (0x01U) +#define SDIOC_BLKGPCON_CR_POS (1U) +#define SDIOC_BLKGPCON_CR (0x02U) +#define SDIOC_BLKGPCON_RWC_POS (2U) +#define SDIOC_BLKGPCON_RWC (0x04U) +#define SDIOC_BLKGPCON_IABG_POS (3U) +#define SDIOC_BLKGPCON_IABG (0x08U) + +/* Bit definition for SDIOC_CLKCON register */ +#define SDIOC_CLKCON_ICE_POS (0U) +#define SDIOC_CLKCON_ICE (0x0001U) +#define SDIOC_CLKCON_CE_POS (2U) +#define SDIOC_CLKCON_CE (0x0004U) +#define SDIOC_CLKCON_FS_POS (8U) +#define SDIOC_CLKCON_FS (0xFF00U) +#define SDIOC_CLKCON_FS_0 (0x0100U) +#define SDIOC_CLKCON_FS_1 (0x0200U) +#define SDIOC_CLKCON_FS_2 (0x0400U) +#define SDIOC_CLKCON_FS_3 (0x0800U) +#define SDIOC_CLKCON_FS_4 (0x1000U) +#define SDIOC_CLKCON_FS_5 (0x2000U) +#define SDIOC_CLKCON_FS_6 (0x4000U) +#define SDIOC_CLKCON_FS_7 (0x8000U) + +/* Bit definition for SDIOC_TOUTCON register */ +#define SDIOC_TOUTCON_DTO (0x0FU) + +/* Bit definition for SDIOC_SFTRST register */ +#define SDIOC_SFTRST_RSTA_POS (0U) +#define SDIOC_SFTRST_RSTA (0x01U) +#define SDIOC_SFTRST_RSTC_POS (1U) +#define SDIOC_SFTRST_RSTC (0x02U) +#define SDIOC_SFTRST_RSTD_POS (2U) +#define SDIOC_SFTRST_RSTD (0x04U) + +/* Bit definition for SDIOC_NORINTST register */ +#define SDIOC_NORINTST_CC_POS (0U) +#define SDIOC_NORINTST_CC (0x0001U) +#define SDIOC_NORINTST_TC_POS (1U) +#define SDIOC_NORINTST_TC (0x0002U) +#define SDIOC_NORINTST_BGE_POS (2U) +#define SDIOC_NORINTST_BGE (0x0004U) +#define SDIOC_NORINTST_BWR_POS (4U) +#define SDIOC_NORINTST_BWR (0x0010U) +#define SDIOC_NORINTST_BRR_POS (5U) +#define SDIOC_NORINTST_BRR (0x0020U) +#define SDIOC_NORINTST_CIST_POS (6U) +#define SDIOC_NORINTST_CIST (0x0040U) +#define SDIOC_NORINTST_CRM_POS (7U) +#define SDIOC_NORINTST_CRM (0x0080U) +#define SDIOC_NORINTST_CINT_POS (8U) +#define SDIOC_NORINTST_CINT (0x0100U) +#define SDIOC_NORINTST_EI_POS (15U) +#define SDIOC_NORINTST_EI (0x8000U) + +/* Bit definition for SDIOC_ERRINTST register */ +#define SDIOC_ERRINTST_CTOE_POS (0U) +#define SDIOC_ERRINTST_CTOE (0x0001U) +#define SDIOC_ERRINTST_CCE_POS (1U) +#define SDIOC_ERRINTST_CCE (0x0002U) +#define SDIOC_ERRINTST_CEBE_POS (2U) +#define SDIOC_ERRINTST_CEBE (0x0004U) +#define SDIOC_ERRINTST_CIE_POS (3U) +#define SDIOC_ERRINTST_CIE (0x0008U) +#define SDIOC_ERRINTST_DTOE_POS (4U) +#define SDIOC_ERRINTST_DTOE (0x0010U) +#define SDIOC_ERRINTST_DCE_POS (5U) +#define SDIOC_ERRINTST_DCE (0x0020U) +#define SDIOC_ERRINTST_DEBE_POS (6U) +#define SDIOC_ERRINTST_DEBE (0x0040U) +#define SDIOC_ERRINTST_ACE_POS (8U) +#define SDIOC_ERRINTST_ACE (0x0100U) + +/* Bit definition for SDIOC_NORINTSTEN register */ +#define SDIOC_NORINTSTEN_CCEN_POS (0U) +#define SDIOC_NORINTSTEN_CCEN (0x0001U) +#define SDIOC_NORINTSTEN_TCEN_POS (1U) +#define SDIOC_NORINTSTEN_TCEN (0x0002U) +#define SDIOC_NORINTSTEN_BGEEN_POS (2U) +#define SDIOC_NORINTSTEN_BGEEN (0x0004U) +#define SDIOC_NORINTSTEN_BWREN_POS (4U) +#define SDIOC_NORINTSTEN_BWREN (0x0010U) +#define SDIOC_NORINTSTEN_BRREN_POS (5U) +#define SDIOC_NORINTSTEN_BRREN (0x0020U) +#define SDIOC_NORINTSTEN_CISTEN_POS (6U) +#define SDIOC_NORINTSTEN_CISTEN (0x0040U) +#define SDIOC_NORINTSTEN_CRMEN_POS (7U) +#define SDIOC_NORINTSTEN_CRMEN (0x0080U) +#define SDIOC_NORINTSTEN_CINTEN_POS (8U) +#define SDIOC_NORINTSTEN_CINTEN (0x0100U) + +/* Bit definition for SDIOC_ERRINTSTEN register */ +#define SDIOC_ERRINTSTEN_CTOEEN_POS (0U) +#define SDIOC_ERRINTSTEN_CTOEEN (0x0001U) +#define SDIOC_ERRINTSTEN_CCEEN_POS (1U) +#define SDIOC_ERRINTSTEN_CCEEN (0x0002U) +#define SDIOC_ERRINTSTEN_CEBEEN_POS (2U) +#define SDIOC_ERRINTSTEN_CEBEEN (0x0004U) +#define SDIOC_ERRINTSTEN_CIEEN_POS (3U) +#define SDIOC_ERRINTSTEN_CIEEN (0x0008U) +#define SDIOC_ERRINTSTEN_DTOEEN_POS (4U) +#define SDIOC_ERRINTSTEN_DTOEEN (0x0010U) +#define SDIOC_ERRINTSTEN_DCEEN_POS (5U) +#define SDIOC_ERRINTSTEN_DCEEN (0x0020U) +#define SDIOC_ERRINTSTEN_DEBEEN_POS (6U) +#define SDIOC_ERRINTSTEN_DEBEEN (0x0040U) +#define SDIOC_ERRINTSTEN_ACEEN_POS (8U) +#define SDIOC_ERRINTSTEN_ACEEN (0x0100U) + +/* Bit definition for SDIOC_NORINTSGEN register */ +#define SDIOC_NORINTSGEN_CCSEN_POS (0U) +#define SDIOC_NORINTSGEN_CCSEN (0x0001U) +#define SDIOC_NORINTSGEN_TCSEN_POS (1U) +#define SDIOC_NORINTSGEN_TCSEN (0x0002U) +#define SDIOC_NORINTSGEN_BGESEN_POS (2U) +#define SDIOC_NORINTSGEN_BGESEN (0x0004U) +#define SDIOC_NORINTSGEN_BWRSEN_POS (4U) +#define SDIOC_NORINTSGEN_BWRSEN (0x0010U) +#define SDIOC_NORINTSGEN_BRRSEN_POS (5U) +#define SDIOC_NORINTSGEN_BRRSEN (0x0020U) +#define SDIOC_NORINTSGEN_CISTSEN_POS (6U) +#define SDIOC_NORINTSGEN_CISTSEN (0x0040U) +#define SDIOC_NORINTSGEN_CRMSEN_POS (7U) +#define SDIOC_NORINTSGEN_CRMSEN (0x0080U) +#define SDIOC_NORINTSGEN_CINTSEN_POS (8U) +#define SDIOC_NORINTSGEN_CINTSEN (0x0100U) + +/* Bit definition for SDIOC_ERRINTSGEN register */ +#define SDIOC_ERRINTSGEN_CTOESEN_POS (0U) +#define SDIOC_ERRINTSGEN_CTOESEN (0x0001U) +#define SDIOC_ERRINTSGEN_CCESEN_POS (1U) +#define SDIOC_ERRINTSGEN_CCESEN (0x0002U) +#define SDIOC_ERRINTSGEN_CEBESEN_POS (2U) +#define SDIOC_ERRINTSGEN_CEBESEN (0x0004U) +#define SDIOC_ERRINTSGEN_CIESEN_POS (3U) +#define SDIOC_ERRINTSGEN_CIESEN (0x0008U) +#define SDIOC_ERRINTSGEN_DTOESEN_POS (4U) +#define SDIOC_ERRINTSGEN_DTOESEN (0x0010U) +#define SDIOC_ERRINTSGEN_DCESEN_POS (5U) +#define SDIOC_ERRINTSGEN_DCESEN (0x0020U) +#define SDIOC_ERRINTSGEN_DEBESEN_POS (6U) +#define SDIOC_ERRINTSGEN_DEBESEN (0x0040U) +#define SDIOC_ERRINTSGEN_ACESEN_POS (8U) +#define SDIOC_ERRINTSGEN_ACESEN (0x0100U) + +/* Bit definition for SDIOC_ATCERRST register */ +#define SDIOC_ATCERRST_NE_POS (0U) +#define SDIOC_ATCERRST_NE (0x0001U) +#define SDIOC_ATCERRST_TOE_POS (1U) +#define SDIOC_ATCERRST_TOE (0x0002U) +#define SDIOC_ATCERRST_CE_POS (2U) +#define SDIOC_ATCERRST_CE (0x0004U) +#define SDIOC_ATCERRST_EBE_POS (3U) +#define SDIOC_ATCERRST_EBE (0x0008U) +#define SDIOC_ATCERRST_IE_POS (4U) +#define SDIOC_ATCERRST_IE (0x0010U) +#define SDIOC_ATCERRST_CMDE_POS (7U) +#define SDIOC_ATCERRST_CMDE (0x0080U) + +/* Bit definition for SDIOC_FEA register */ +#define SDIOC_FEA_FNE_POS (0U) +#define SDIOC_FEA_FNE (0x0001U) +#define SDIOC_FEA_FTOE_POS (1U) +#define SDIOC_FEA_FTOE (0x0002U) +#define SDIOC_FEA_FCE_POS (2U) +#define SDIOC_FEA_FCE (0x0004U) +#define SDIOC_FEA_FEBE_POS (3U) +#define SDIOC_FEA_FEBE (0x0008U) +#define SDIOC_FEA_FIE_POS (4U) +#define SDIOC_FEA_FIE (0x0010U) +#define SDIOC_FEA_FCMDE_POS (7U) +#define SDIOC_FEA_FCMDE (0x0080U) + +/* Bit definition for SDIOC_FEE register */ +#define SDIOC_FEE_FCTOE_POS (0U) +#define SDIOC_FEE_FCTOE (0x0001U) +#define SDIOC_FEE_FCCE_POS (1U) +#define SDIOC_FEE_FCCE (0x0002U) +#define SDIOC_FEE_FCEBE_POS (2U) +#define SDIOC_FEE_FCEBE (0x0004U) +#define SDIOC_FEE_FCIE_POS (3U) +#define SDIOC_FEE_FCIE (0x0008U) +#define SDIOC_FEE_FDTOE_POS (4U) +#define SDIOC_FEE_FDTOE (0x0010U) +#define SDIOC_FEE_FDCE_POS (5U) +#define SDIOC_FEE_FDCE (0x0020U) +#define SDIOC_FEE_FDEBE_POS (6U) +#define SDIOC_FEE_FDEBE (0x0040U) +#define SDIOC_FEE_FACE_POS (8U) +#define SDIOC_FEE_FACE (0x0100U) + +/******************************************************************************* + Bit definition for Peripheral SPI +*******************************************************************************/ +/* Bit definition for SPI_DR register */ +#define SPI_DR (0xFFFFFFFFUL) + +/* Bit definition for SPI_CR1 register */ +#define SPI_CR1_SPIMDS_POS (0U) +#define SPI_CR1_SPIMDS (0x00000001UL) +#define SPI_CR1_TXMDS_POS (1U) +#define SPI_CR1_TXMDS (0x00000002UL) +#define SPI_CR1_MSTR_POS (3U) +#define SPI_CR1_MSTR (0x00000008UL) +#define SPI_CR1_SPLPBK_POS (4U) +#define SPI_CR1_SPLPBK (0x00000010UL) +#define SPI_CR1_SPLPBK2_POS (5U) +#define SPI_CR1_SPLPBK2 (0x00000020UL) +#define SPI_CR1_SPE_POS (6U) +#define SPI_CR1_SPE (0x00000040UL) +#define SPI_CR1_CSUSPE_POS (7U) +#define SPI_CR1_CSUSPE (0x00000080UL) +#define SPI_CR1_EIE_POS (8U) +#define SPI_CR1_EIE (0x00000100UL) +#define SPI_CR1_TXIE_POS (9U) +#define SPI_CR1_TXIE (0x00000200UL) +#define SPI_CR1_RXIE_POS (10U) +#define SPI_CR1_RXIE (0x00000400UL) +#define SPI_CR1_IDIE_POS (11U) +#define SPI_CR1_IDIE (0x00000800UL) +#define SPI_CR1_MODFE_POS (12U) +#define SPI_CR1_MODFE (0x00001000UL) +#define SPI_CR1_PATE_POS (13U) +#define SPI_CR1_PATE (0x00002000UL) +#define SPI_CR1_PAOE_POS (14U) +#define SPI_CR1_PAOE (0x00004000UL) +#define SPI_CR1_PAE_POS (15U) +#define SPI_CR1_PAE (0x00008000UL) + +/* Bit definition for SPI_CFG1 register */ +#define SPI_CFG1_FTHLV_POS (0U) +#define SPI_CFG1_FTHLV (0x00000003UL) +#define SPI_CFG1_FTHLV_0 (0x00000001UL) +#define SPI_CFG1_FTHLV_1 (0x00000002UL) +#define SPI_CFG1_SPRDTD_POS (6U) +#define SPI_CFG1_SPRDTD (0x00000040UL) +#define SPI_CFG1_SS0PV_POS (8U) +#define SPI_CFG1_SS0PV (0x00000100UL) +#define SPI_CFG1_SS1PV_POS (9U) +#define SPI_CFG1_SS1PV (0x00000200UL) +#define SPI_CFG1_SS2PV_POS (10U) +#define SPI_CFG1_SS2PV (0x00000400UL) +#define SPI_CFG1_SS3PV_POS (11U) +#define SPI_CFG1_SS3PV (0x00000800UL) +#define SPI_CFG1_MSSI_POS (20U) +#define SPI_CFG1_MSSI (0x00700000UL) +#define SPI_CFG1_MSSDL_POS (24U) +#define SPI_CFG1_MSSDL (0x07000000UL) +#define SPI_CFG1_MIDI_POS (28U) +#define SPI_CFG1_MIDI (0x70000000UL) + +/* Bit definition for SPI_SR register */ +#define SPI_SR_OVRERF_POS (0U) +#define SPI_SR_OVRERF (0x00000001UL) +#define SPI_SR_IDLNF_POS (1U) +#define SPI_SR_IDLNF (0x00000002UL) +#define SPI_SR_MODFERF_POS (2U) +#define SPI_SR_MODFERF (0x00000004UL) +#define SPI_SR_PERF_POS (3U) +#define SPI_SR_PERF (0x00000008UL) +#define SPI_SR_UDRERF_POS (4U) +#define SPI_SR_UDRERF (0x00000010UL) +#define SPI_SR_TDEF_POS (5U) +#define SPI_SR_TDEF (0x00000020UL) +#define SPI_SR_RDFF_POS (7U) +#define SPI_SR_RDFF (0x00000080UL) + +/* Bit definition for SPI_CFG2 register */ +#define SPI_CFG2_CPHA_POS (0U) +#define SPI_CFG2_CPHA (0x00000001UL) +#define SPI_CFG2_CPOL_POS (1U) +#define SPI_CFG2_CPOL (0x00000002UL) +#define SPI_CFG2_MBR_POS (2U) +#define SPI_CFG2_MBR (0x0000001CUL) +#define SPI_CFG2_SSA_POS (5U) +#define SPI_CFG2_SSA (0x000000E0UL) +#define SPI_CFG2_SSA_0 (0x00000020UL) +#define SPI_CFG2_SSA_1 (0x00000040UL) +#define SPI_CFG2_SSA_2 (0x00000080UL) +#define SPI_CFG2_DSIZE_POS (8U) +#define SPI_CFG2_DSIZE (0x00000F00UL) +#define SPI_CFG2_LSBF_POS (12U) +#define SPI_CFG2_LSBF (0x00001000UL) +#define SPI_CFG2_MIDIE_POS (13U) +#define SPI_CFG2_MIDIE (0x00002000UL) +#define SPI_CFG2_MSSDLE_POS (14U) +#define SPI_CFG2_MSSDLE (0x00004000UL) +#define SPI_CFG2_MSSIE_POS (15U) +#define SPI_CFG2_MSSIE (0x00008000UL) + +/******************************************************************************* + Bit definition for Peripheral SRAMC +*******************************************************************************/ +/* Bit definition for SRAMC_WTCR register */ +#define SRAMC_WTCR_SRAM12_RWT_POS (0U) +#define SRAMC_WTCR_SRAM12_RWT (0x00000007UL) +#define SRAMC_WTCR_SRAM12_WWT_POS (4U) +#define SRAMC_WTCR_SRAM12_WWT (0x00000070UL) +#define SRAMC_WTCR_SRAM3_RWT_POS (8U) +#define SRAMC_WTCR_SRAM3_RWT (0x00000700UL) +#define SRAMC_WTCR_SRAM3_WWT_POS (12U) +#define SRAMC_WTCR_SRAM3_WWT (0x00007000UL) +#define SRAMC_WTCR_SRAMH_RWT_POS (16U) +#define SRAMC_WTCR_SRAMH_RWT (0x00070000UL) +#define SRAMC_WTCR_SRAMH_WWT_POS (20U) +#define SRAMC_WTCR_SRAMH_WWT (0x00700000UL) +#define SRAMC_WTCR_SRAMR_RWT_POS (24U) +#define SRAMC_WTCR_SRAMR_RWT (0x07000000UL) +#define SRAMC_WTCR_SRAMR_WWT_POS (28U) +#define SRAMC_WTCR_SRAMR_WWT (0x70000000UL) + +/* Bit definition for SRAMC_WTPR register */ +#define SRAMC_WTPR_WTPRC_POS (0U) +#define SRAMC_WTPR_WTPRC (0x00000001UL) +#define SRAMC_WTPR_WTPRKW_POS (1U) +#define SRAMC_WTPR_WTPRKW (0x000000FEUL) + +/* Bit definition for SRAMC_CKCR register */ +#define SRAMC_CKCR_PYOAD_POS (0U) +#define SRAMC_CKCR_PYOAD (0x00000001UL) +#define SRAMC_CKCR_ECCOAD_POS (16U) +#define SRAMC_CKCR_ECCOAD (0x00010000UL) +#define SRAMC_CKCR_ECCMOD_POS (24U) +#define SRAMC_CKCR_ECCMOD (0x03000000UL) +#define SRAMC_CKCR_ECCMOD_0 (0x01000000UL) +#define SRAMC_CKCR_ECCMOD_1 (0x02000000UL) + +/* Bit definition for SRAMC_CKPR register */ +#define SRAMC_CKPR_CKPRC_POS (0U) +#define SRAMC_CKPR_CKPRC (0x00000001UL) +#define SRAMC_CKPR_CKPRKW_POS (1U) +#define SRAMC_CKPR_CKPRKW (0x000000FEUL) + +/* Bit definition for SRAMC_CKSR register */ +#define SRAMC_CKSR_SRAM3_1ERR_POS (0U) +#define SRAMC_CKSR_SRAM3_1ERR (0x00000001UL) +#define SRAMC_CKSR_SRAM3_2ERR_POS (1U) +#define SRAMC_CKSR_SRAM3_2ERR (0x00000002UL) +#define SRAMC_CKSR_SRAM12_PYERR_POS (2U) +#define SRAMC_CKSR_SRAM12_PYERR (0x00000004UL) +#define SRAMC_CKSR_SRAMH_PYERR_POS (3U) +#define SRAMC_CKSR_SRAMH_PYERR (0x00000008UL) +#define SRAMC_CKSR_SRAMR_PYERR_POS (4U) +#define SRAMC_CKSR_SRAMR_PYERR (0x00000010UL) + +/******************************************************************************* + Bit definition for Peripheral SWDT +*******************************************************************************/ +/* Bit definition for SWDT_SR register */ +#define SWDT_SR_CNT_POS (0U) +#define SWDT_SR_CNT (0x0000FFFFUL) +#define SWDT_SR_UDF_POS (16U) +#define SWDT_SR_UDF (0x00010000UL) +#define SWDT_SR_REF_POS (17U) +#define SWDT_SR_REF (0x00020000UL) + +/* Bit definition for SWDT_RR register */ +#define SWDT_RR_RF (0x0000FFFFUL) + +/******************************************************************************* + Bit definition for Peripheral TMR0 +*******************************************************************************/ +/* Bit definition for TMR0_CNTAR register */ +#define TMR0_CNTAR_CNTA (0x0000FFFFUL) + +/* Bit definition for TMR0_CNTBR register */ +#define TMR0_CNTBR_CNTB (0x0000FFFFUL) + +/* Bit definition for TMR0_CMPAR register */ +#define TMR0_CMPAR_CMPA (0x0000FFFFUL) + +/* Bit definition for TMR0_CMPBR register */ +#define TMR0_CMPBR_CMPB (0x0000FFFFUL) + +/* Bit definition for TMR0_BCONR register */ +#define TMR0_BCONR_CSTA_POS (0U) +#define TMR0_BCONR_CSTA (0x00000001UL) +#define TMR0_BCONR_CAPMDA_POS (1U) +#define TMR0_BCONR_CAPMDA (0x00000002UL) +#define TMR0_BCONR_INTENA_POS (2U) +#define TMR0_BCONR_INTENA (0x00000004UL) +#define TMR0_BCONR_CKDIVA_POS (4U) +#define TMR0_BCONR_CKDIVA (0x000000F0UL) +#define TMR0_BCONR_SYNSA_POS (8U) +#define TMR0_BCONR_SYNSA (0x00000100UL) +#define TMR0_BCONR_SYNCLKA_POS (9U) +#define TMR0_BCONR_SYNCLKA (0x00000200UL) +#define TMR0_BCONR_ASYNCLKA_POS (10U) +#define TMR0_BCONR_ASYNCLKA (0x00000400UL) +#define TMR0_BCONR_HSTAA_POS (12U) +#define TMR0_BCONR_HSTAA (0x00001000UL) +#define TMR0_BCONR_HSTPA_POS (13U) +#define TMR0_BCONR_HSTPA (0x00002000UL) +#define TMR0_BCONR_HCLEA_POS (14U) +#define TMR0_BCONR_HCLEA (0x00004000UL) +#define TMR0_BCONR_HICPA_POS (15U) +#define TMR0_BCONR_HICPA (0x00008000UL) +#define TMR0_BCONR_CSTB_POS (16U) +#define TMR0_BCONR_CSTB (0x00010000UL) +#define TMR0_BCONR_CAPMDB_POS (17U) +#define TMR0_BCONR_CAPMDB (0x00020000UL) +#define TMR0_BCONR_INTENB_POS (18U) +#define TMR0_BCONR_INTENB (0x00040000UL) +#define TMR0_BCONR_CKDIVB_POS (20U) +#define TMR0_BCONR_CKDIVB (0x00F00000UL) +#define TMR0_BCONR_SYNSB_POS (24U) +#define TMR0_BCONR_SYNSB (0x01000000UL) +#define TMR0_BCONR_SYNCLKB_POS (25U) +#define TMR0_BCONR_SYNCLKB (0x02000000UL) +#define TMR0_BCONR_ASYNCLKB_POS (26U) +#define TMR0_BCONR_ASYNCLKB (0x04000000UL) +#define TMR0_BCONR_HSTAB_POS (28U) +#define TMR0_BCONR_HSTAB (0x10000000UL) +#define TMR0_BCONR_HSTPB_POS (29U) +#define TMR0_BCONR_HSTPB (0x20000000UL) +#define TMR0_BCONR_HCLEB_POS (30U) +#define TMR0_BCONR_HCLEB (0x40000000UL) +#define TMR0_BCONR_HICPB_POS (31U) +#define TMR0_BCONR_HICPB (0x80000000UL) + +/* Bit definition for TMR0_STFLR register */ +#define TMR0_STFLR_CMFA_POS (0U) +#define TMR0_STFLR_CMFA (0x00000001UL) +#define TMR0_STFLR_CMFB_POS (16U) +#define TMR0_STFLR_CMFB (0x00010000UL) + +/******************************************************************************* + Bit definition for Peripheral TMR4 +*******************************************************************************/ +/* Bit definition for TMR4_OCCRUH register */ +#define TMR4_OCCRUH (0xFFFFU) + +/* Bit definition for TMR4_OCCRUL register */ +#define TMR4_OCCRUL (0xFFFFU) + +/* Bit definition for TMR4_OCCRVH register */ +#define TMR4_OCCRVH (0xFFFFU) + +/* Bit definition for TMR4_OCCRVL register */ +#define TMR4_OCCRVL (0xFFFFU) + +/* Bit definition for TMR4_OCCRWH register */ +#define TMR4_OCCRWH (0xFFFFU) + +/* Bit definition for TMR4_OCCRWL register */ +#define TMR4_OCCRWL (0xFFFFU) + +/* Bit definition for TMR4_OCSR register */ +#define TMR4_OCSR_OCEH_POS (0U) +#define TMR4_OCSR_OCEH (0x0001U) +#define TMR4_OCSR_OCEL_POS (1U) +#define TMR4_OCSR_OCEL (0x0002U) +#define TMR4_OCSR_OCPH_POS (2U) +#define TMR4_OCSR_OCPH (0x0004U) +#define TMR4_OCSR_OCPL_POS (3U) +#define TMR4_OCSR_OCPL (0x0008U) +#define TMR4_OCSR_OCIEH_POS (4U) +#define TMR4_OCSR_OCIEH (0x0010U) +#define TMR4_OCSR_OCIEL_POS (5U) +#define TMR4_OCSR_OCIEL (0x0020U) +#define TMR4_OCSR_OCFH_POS (6U) +#define TMR4_OCSR_OCFH (0x0040U) +#define TMR4_OCSR_OCFL_POS (7U) +#define TMR4_OCSR_OCFL (0x0080U) + +/* Bit definition for TMR4_OCER register */ +#define TMR4_OCER_CHBUFEN_POS (0U) +#define TMR4_OCER_CHBUFEN (0x0003U) +#define TMR4_OCER_CHBUFEN_0 (0x0001U) +#define TMR4_OCER_CHBUFEN_1 (0x0002U) +#define TMR4_OCER_CLBUFEN_POS (2U) +#define TMR4_OCER_CLBUFEN (0x000CU) +#define TMR4_OCER_CLBUFEN_0 (0x0004U) +#define TMR4_OCER_CLBUFEN_1 (0x0008U) +#define TMR4_OCER_MHBUFEN_POS (4U) +#define TMR4_OCER_MHBUFEN (0x0030U) +#define TMR4_OCER_MHBUFEN_0 (0x0010U) +#define TMR4_OCER_MHBUFEN_1 (0x0020U) +#define TMR4_OCER_MLBUFEN_POS (6U) +#define TMR4_OCER_MLBUFEN (0x00C0U) +#define TMR4_OCER_MLBUFEN_0 (0x0040U) +#define TMR4_OCER_MLBUFEN_1 (0x0080U) +#define TMR4_OCER_LMCH_POS (8U) +#define TMR4_OCER_LMCH (0x0100U) +#define TMR4_OCER_LMCL_POS (9U) +#define TMR4_OCER_LMCL (0x0200U) +#define TMR4_OCER_LMMH_POS (10U) +#define TMR4_OCER_LMMH (0x0400U) +#define TMR4_OCER_LMML_POS (11U) +#define TMR4_OCER_LMML (0x0800U) +#define TMR4_OCER_MCECH_POS (12U) +#define TMR4_OCER_MCECH (0x1000U) +#define TMR4_OCER_MCECL_POS (13U) +#define TMR4_OCER_MCECL (0x2000U) + +/* Bit definition for TMR4_OCMRH register */ +#define TMR4_OCMRH_OCFDCH_POS (0U) +#define TMR4_OCMRH_OCFDCH (0x0001U) +#define TMR4_OCMRH_OCFPKH_POS (1U) +#define TMR4_OCMRH_OCFPKH (0x0002U) +#define TMR4_OCMRH_OCFUCH_POS (2U) +#define TMR4_OCMRH_OCFUCH (0x0004U) +#define TMR4_OCMRH_OCFZRH_POS (3U) +#define TMR4_OCMRH_OCFZRH (0x0008U) +#define TMR4_OCMRH_OPDCH_POS (4U) +#define TMR4_OCMRH_OPDCH (0x0030U) +#define TMR4_OCMRH_OPDCH_0 (0x0010U) +#define TMR4_OCMRH_OPDCH_1 (0x0020U) +#define TMR4_OCMRH_OPPKH_POS (6U) +#define TMR4_OCMRH_OPPKH (0x00C0U) +#define TMR4_OCMRH_OPPKH_0 (0x0040U) +#define TMR4_OCMRH_OPPKH_1 (0x0080U) +#define TMR4_OCMRH_OPUCH_POS (8U) +#define TMR4_OCMRH_OPUCH (0x0300U) +#define TMR4_OCMRH_OPUCH_0 (0x0100U) +#define TMR4_OCMRH_OPUCH_1 (0x0200U) +#define TMR4_OCMRH_OPZRH_POS (10U) +#define TMR4_OCMRH_OPZRH (0x0C00U) +#define TMR4_OCMRH_OPZRH_0 (0x0400U) +#define TMR4_OCMRH_OPZRH_1 (0x0800U) +#define TMR4_OCMRH_OPNPKH_POS (12U) +#define TMR4_OCMRH_OPNPKH (0x3000U) +#define TMR4_OCMRH_OPNPKH_0 (0x1000U) +#define TMR4_OCMRH_OPNPKH_1 (0x2000U) +#define TMR4_OCMRH_OPNZRH_POS (14U) +#define TMR4_OCMRH_OPNZRH (0xC000U) +#define TMR4_OCMRH_OPNZRH_0 (0x4000U) +#define TMR4_OCMRH_OPNZRH_1 (0x8000U) + +/* Bit definition for TMR4_OCMRL register */ +#define TMR4_OCMRL_OCFDCL_POS (0U) +#define TMR4_OCMRL_OCFDCL (0x00000001UL) +#define TMR4_OCMRL_OCFPKL_POS (1U) +#define TMR4_OCMRL_OCFPKL (0x00000002UL) +#define TMR4_OCMRL_OCFUCL_POS (2U) +#define TMR4_OCMRL_OCFUCL (0x00000004UL) +#define TMR4_OCMRL_OCFZRL_POS (3U) +#define TMR4_OCMRL_OCFZRL (0x00000008UL) +#define TMR4_OCMRL_OPDCL_POS (4U) +#define TMR4_OCMRL_OPDCL (0x00000030UL) +#define TMR4_OCMRL_OPDCL_0 (0x00000010UL) +#define TMR4_OCMRL_OPDCL_1 (0x00000020UL) +#define TMR4_OCMRL_OPPKL_POS (6U) +#define TMR4_OCMRL_OPPKL (0x000000C0UL) +#define TMR4_OCMRL_OPPKL_0 (0x00000040UL) +#define TMR4_OCMRL_OPPKL_1 (0x00000080UL) +#define TMR4_OCMRL_OPUCL_POS (8U) +#define TMR4_OCMRL_OPUCL (0x00000300UL) +#define TMR4_OCMRL_OPUCL_0 (0x00000100UL) +#define TMR4_OCMRL_OPUCL_1 (0x00000200UL) +#define TMR4_OCMRL_OPZRL_POS (10U) +#define TMR4_OCMRL_OPZRL (0x00000C00UL) +#define TMR4_OCMRL_OPZRL_0 (0x00000400UL) +#define TMR4_OCMRL_OPZRL_1 (0x00000800UL) +#define TMR4_OCMRL_OPNPKL_POS (12U) +#define TMR4_OCMRL_OPNPKL (0x00003000UL) +#define TMR4_OCMRL_OPNPKL_0 (0x00001000UL) +#define TMR4_OCMRL_OPNPKL_1 (0x00002000UL) +#define TMR4_OCMRL_OPNZRL_POS (14U) +#define TMR4_OCMRL_OPNZRL (0x0000C000UL) +#define TMR4_OCMRL_OPNZRL_0 (0x00004000UL) +#define TMR4_OCMRL_OPNZRL_1 (0x00008000UL) +#define TMR4_OCMRL_EOPNDCL_POS (16U) +#define TMR4_OCMRL_EOPNDCL (0x00030000UL) +#define TMR4_OCMRL_EOPNDCL_0 (0x00010000UL) +#define TMR4_OCMRL_EOPNDCL_1 (0x00020000UL) +#define TMR4_OCMRL_EOPNUCL_POS (18U) +#define TMR4_OCMRL_EOPNUCL (0x000C0000UL) +#define TMR4_OCMRL_EOPNUCL_0 (0x00040000UL) +#define TMR4_OCMRL_EOPNUCL_1 (0x00080000UL) +#define TMR4_OCMRL_EOPDCL_POS (20U) +#define TMR4_OCMRL_EOPDCL (0x00300000UL) +#define TMR4_OCMRL_EOPDCL_0 (0x00100000UL) +#define TMR4_OCMRL_EOPDCL_1 (0x00200000UL) +#define TMR4_OCMRL_EOPPKL_POS (22U) +#define TMR4_OCMRL_EOPPKL (0x00C00000UL) +#define TMR4_OCMRL_EOPPKL_0 (0x00400000UL) +#define TMR4_OCMRL_EOPPKL_1 (0x00800000UL) +#define TMR4_OCMRL_EOPUCL_POS (24U) +#define TMR4_OCMRL_EOPUCL (0x03000000UL) +#define TMR4_OCMRL_EOPUCL_0 (0x01000000UL) +#define TMR4_OCMRL_EOPUCL_1 (0x02000000UL) +#define TMR4_OCMRL_EOPZRL_POS (26U) +#define TMR4_OCMRL_EOPZRL (0x0C000000UL) +#define TMR4_OCMRL_EOPZRL_0 (0x04000000UL) +#define TMR4_OCMRL_EOPZRL_1 (0x08000000UL) +#define TMR4_OCMRL_EOPNPKL_POS (28U) +#define TMR4_OCMRL_EOPNPKL (0x30000000UL) +#define TMR4_OCMRL_EOPNPKL_0 (0x10000000UL) +#define TMR4_OCMRL_EOPNPKL_1 (0x20000000UL) +#define TMR4_OCMRL_EOPNZRL_POS (30U) +#define TMR4_OCMRL_EOPNZRL (0xC0000000UL) +#define TMR4_OCMRL_EOPNZRL_0 (0x40000000UL) +#define TMR4_OCMRL_EOPNZRL_1 (0x80000000UL) + +/* Bit definition for TMR4_CPSR register */ +#define TMR4_CPSR (0xFFFFU) + +/* Bit definition for TMR4_CNTR register */ +#define TMR4_CNTR (0xFFFFU) + +/* Bit definition for TMR4_CCSR register */ +#define TMR4_CCSR_CKDIV_POS (0U) +#define TMR4_CCSR_CKDIV (0x000FU) +#define TMR4_CCSR_CLEAR_POS (4U) +#define TMR4_CCSR_CLEAR (0x0010U) +#define TMR4_CCSR_MODE_POS (5U) +#define TMR4_CCSR_MODE (0x0020U) +#define TMR4_CCSR_STOP_POS (6U) +#define TMR4_CCSR_STOP (0x0040U) +#define TMR4_CCSR_BUFEN_POS (7U) +#define TMR4_CCSR_BUFEN (0x0080U) +#define TMR4_CCSR_IRQPEN_POS (8U) +#define TMR4_CCSR_IRQPEN (0x0100U) +#define TMR4_CCSR_IRQPF_POS (9U) +#define TMR4_CCSR_IRQPF (0x0200U) +#define TMR4_CCSR_IRQZEN_POS (13U) +#define TMR4_CCSR_IRQZEN (0x2000U) +#define TMR4_CCSR_IRQZF_POS (14U) +#define TMR4_CCSR_IRQZF (0x4000U) +#define TMR4_CCSR_ECKEN_POS (15U) +#define TMR4_CCSR_ECKEN (0x8000U) + +/* Bit definition for TMR4_CVPR register */ +#define TMR4_CVPR_ZIM_POS (0U) +#define TMR4_CVPR_ZIM (0x000FU) +#define TMR4_CVPR_PIM_POS (4U) +#define TMR4_CVPR_PIM (0x00F0U) +#define TMR4_CVPR_ZIC_POS (8U) +#define TMR4_CVPR_ZIC (0x0F00U) +#define TMR4_CVPR_PIC_POS (12U) +#define TMR4_CVPR_PIC (0xF000U) + +/* Bit definition for TMR4_PFSRU register */ +#define TMR4_PFSRU (0xFFFFU) + +/* Bit definition for TMR4_PDARU register */ +#define TMR4_PDARU (0xFFFFU) + +/* Bit definition for TMR4_PDBRU register */ +#define TMR4_PDBRU (0xFFFFU) + +/* Bit definition for TMR4_PFSRV register */ +#define TMR4_PFSRV (0xFFFFU) + +/* Bit definition for TMR4_PDARV register */ +#define TMR4_PDARV (0xFFFFU) + +/* Bit definition for TMR4_PDBRV register */ +#define TMR4_PDBRV (0xFFFFU) + +/* Bit definition for TMR4_PFSRW register */ +#define TMR4_PFSRW (0xFFFFU) + +/* Bit definition for TMR4_PDARW register */ +#define TMR4_PDARW (0xFFFFU) + +/* Bit definition for TMR4_PDBRW register */ +#define TMR4_PDBRW (0xFFFFU) + +/* Bit definition for TMR4_POCR register */ +#define TMR4_POCR_DIVCK_POS (0U) +#define TMR4_POCR_DIVCK (0x0007U) +#define TMR4_POCR_PWMMD_POS (4U) +#define TMR4_POCR_PWMMD (0x0030U) +#define TMR4_POCR_PWMMD_0 (0x0010U) +#define TMR4_POCR_PWMMD_1 (0x0020U) +#define TMR4_POCR_LVLS_POS (6U) +#define TMR4_POCR_LVLS (0x00C0U) +#define TMR4_POCR_LVLS_0 (0x0040U) +#define TMR4_POCR_LVLS_1 (0x0080U) + +/* Bit definition for TMR4_RCSR register */ +#define TMR4_RCSR_RTIDU_POS (0U) +#define TMR4_RCSR_RTIDU (0x0001U) +#define TMR4_RCSR_RTIDV_POS (1U) +#define TMR4_RCSR_RTIDV (0x0002U) +#define TMR4_RCSR_RTIDW_POS (2U) +#define TMR4_RCSR_RTIDW (0x0004U) +#define TMR4_RCSR_RTIFU_POS (4U) +#define TMR4_RCSR_RTIFU (0x0010U) +#define TMR4_RCSR_RTICU_POS (5U) +#define TMR4_RCSR_RTICU (0x0020U) +#define TMR4_RCSR_RTEU_POS (6U) +#define TMR4_RCSR_RTEU (0x0040U) +#define TMR4_RCSR_RTSU_POS (7U) +#define TMR4_RCSR_RTSU (0x0080U) +#define TMR4_RCSR_RTIFV_POS (8U) +#define TMR4_RCSR_RTIFV (0x0100U) +#define TMR4_RCSR_RTICV_POS (9U) +#define TMR4_RCSR_RTICV (0x0200U) +#define TMR4_RCSR_RTEV_POS (10U) +#define TMR4_RCSR_RTEV (0x0400U) +#define TMR4_RCSR_RTSV_POS (11U) +#define TMR4_RCSR_RTSV (0x0800U) +#define TMR4_RCSR_RTIFW_POS (12U) +#define TMR4_RCSR_RTIFW (0x1000U) +#define TMR4_RCSR_RTICW_POS (13U) +#define TMR4_RCSR_RTICW (0x2000U) +#define TMR4_RCSR_RTEW_POS (14U) +#define TMR4_RCSR_RTEW (0x4000U) +#define TMR4_RCSR_RTSW_POS (15U) +#define TMR4_RCSR_RTSW (0x8000U) + +/* Bit definition for TMR4_SCCRUH register */ +#define TMR4_SCCRUH (0xFFFFU) + +/* Bit definition for TMR4_SCCRUL register */ +#define TMR4_SCCRUL (0xFFFFU) + +/* Bit definition for TMR4_SCCRVH register */ +#define TMR4_SCCRVH (0xFFFFU) + +/* Bit definition for TMR4_SCCRVL register */ +#define TMR4_SCCRVL (0xFFFFU) + +/* Bit definition for TMR4_SCCRWH register */ +#define TMR4_SCCRWH (0xFFFFU) + +/* Bit definition for TMR4_SCCRWL register */ +#define TMR4_SCCRWL (0xFFFFU) + +/* Bit definition for TMR4_SCSR register */ +#define TMR4_SCSR_BUFEN_POS (0U) +#define TMR4_SCSR_BUFEN (0x0003U) +#define TMR4_SCSR_BUFEN_0 (0x0001U) +#define TMR4_SCSR_BUFEN_1 (0x0002U) +#define TMR4_SCSR_EVTOS_POS (2U) +#define TMR4_SCSR_EVTOS (0x001CU) +#define TMR4_SCSR_LMC_POS (5U) +#define TMR4_SCSR_LMC (0x0020U) +#define TMR4_SCSR_EVTMS_POS (8U) +#define TMR4_SCSR_EVTMS (0x0100U) +#define TMR4_SCSR_EVTDS_POS (9U) +#define TMR4_SCSR_EVTDS (0x0200U) +#define TMR4_SCSR_DEN_POS (12U) +#define TMR4_SCSR_DEN (0x1000U) +#define TMR4_SCSR_PEN_POS (13U) +#define TMR4_SCSR_PEN (0x2000U) +#define TMR4_SCSR_UEN_POS (14U) +#define TMR4_SCSR_UEN (0x4000U) +#define TMR4_SCSR_ZEN_POS (15U) +#define TMR4_SCSR_ZEN (0x8000U) + +/* Bit definition for TMR4_SCMR register */ +#define TMR4_SCMR_AMC_POS (0U) +#define TMR4_SCMR_AMC (0x000FU) +#define TMR4_SCMR_MZCE_POS (6U) +#define TMR4_SCMR_MZCE (0x0040U) +#define TMR4_SCMR_MPCE_POS (7U) +#define TMR4_SCMR_MPCE (0x0080U) + +/* Bit definition for TMR4_ECSR register */ +#define TMR4_ECSR_HOLD_POS (7U) +#define TMR4_ECSR_HOLD (0x0080U) + +/******************************************************************************* + Bit definition for Peripheral TMR4_ECER +*******************************************************************************/ +/* Bit definition for TMR4_ECER_ECER register */ +#define TMR4_ECER_ECER_EMBVAL (0x00000003UL) + +/******************************************************************************* + Bit definition for Peripheral TMR6 +*******************************************************************************/ +/* Bit definition for TMR6_CNTER register */ +#define TMR6_CNTER_CNT (0x0000FFFFUL) + +/* Bit definition for TMR6_PERAR register */ +#define TMR6_PERAR_PERA (0x0000FFFFUL) + +/* Bit definition for TMR6_PERBR register */ +#define TMR6_PERBR_PERB (0x0000FFFFUL) + +/* Bit definition for TMR6_PERCR register */ +#define TMR6_PERCR_PERC (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMAR register */ +#define TMR6_GCMAR_GCMA (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMBR register */ +#define TMR6_GCMBR_GCMB (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMCR register */ +#define TMR6_GCMCR_GCMC (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMDR register */ +#define TMR6_GCMDR_GCMD (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMER register */ +#define TMR6_GCMER_GCME (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMFR register */ +#define TMR6_GCMFR_GCMF (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMAR register */ +#define TMR6_SCMAR_SCMA (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMBR register */ +#define TMR6_SCMBR_SCMB (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMCR register */ +#define TMR6_SCMCR_SCMC (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMDR register */ +#define TMR6_SCMDR_SCMD (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMER register */ +#define TMR6_SCMER_SCME (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMFR register */ +#define TMR6_SCMFR_SCMF (0x0000FFFFUL) + +/* Bit definition for TMR6_DTUAR register */ +#define TMR6_DTUAR_DTUA (0x0000FFFFUL) + +/* Bit definition for TMR6_DTDAR register */ +#define TMR6_DTDAR_DTDA (0x0000FFFFUL) + +/* Bit definition for TMR6_DTUBR register */ +#define TMR6_DTUBR_DTUB (0x0000FFFFUL) + +/* Bit definition for TMR6_DTDBR register */ +#define TMR6_DTDBR_DTDB (0x0000FFFFUL) + +/* Bit definition for TMR6_GCONR register */ +#define TMR6_GCONR_START_POS (0U) +#define TMR6_GCONR_START (0x00000001UL) +#define TMR6_GCONR_MODE_POS (1U) +#define TMR6_GCONR_MODE (0x0000000EUL) +#define TMR6_GCONR_CKDIV_POS (4U) +#define TMR6_GCONR_CKDIV (0x00000070UL) +#define TMR6_GCONR_DIR_POS (8U) +#define TMR6_GCONR_DIR (0x00000100UL) +#define TMR6_GCONR_ZMSKREV_POS (16U) +#define TMR6_GCONR_ZMSKREV (0x00010000UL) +#define TMR6_GCONR_ZMSKPOS_POS (17U) +#define TMR6_GCONR_ZMSKPOS (0x00020000UL) +#define TMR6_GCONR_ZMSKVAL_POS (18U) +#define TMR6_GCONR_ZMSKVAL (0x000C0000UL) +#define TMR6_GCONR_ZMSKVAL_0 (0x00040000UL) +#define TMR6_GCONR_ZMSKVAL_1 (0x00080000UL) + +/* Bit definition for TMR6_ICONR register */ +#define TMR6_ICONR_INTENA_POS (0U) +#define TMR6_ICONR_INTENA (0x00000001UL) +#define TMR6_ICONR_INTENB_POS (1U) +#define TMR6_ICONR_INTENB (0x00000002UL) +#define TMR6_ICONR_INTENC_POS (2U) +#define TMR6_ICONR_INTENC (0x00000004UL) +#define TMR6_ICONR_INTEND_POS (3U) +#define TMR6_ICONR_INTEND (0x00000008UL) +#define TMR6_ICONR_INTENE_POS (4U) +#define TMR6_ICONR_INTENE (0x00000010UL) +#define TMR6_ICONR_INTENF_POS (5U) +#define TMR6_ICONR_INTENF (0x00000020UL) +#define TMR6_ICONR_INTENOVF_POS (6U) +#define TMR6_ICONR_INTENOVF (0x00000040UL) +#define TMR6_ICONR_INTENUDF_POS (7U) +#define TMR6_ICONR_INTENUDF (0x00000080UL) +#define TMR6_ICONR_INTENDTE_POS (8U) +#define TMR6_ICONR_INTENDTE (0x00000100UL) +#define TMR6_ICONR_INTENSAU_POS (16U) +#define TMR6_ICONR_INTENSAU (0x00010000UL) +#define TMR6_ICONR_INTENSAD_POS (17U) +#define TMR6_ICONR_INTENSAD (0x00020000UL) +#define TMR6_ICONR_INTENSBU_POS (18U) +#define TMR6_ICONR_INTENSBU (0x00040000UL) +#define TMR6_ICONR_INTENSBD_POS (19U) +#define TMR6_ICONR_INTENSBD (0x00080000UL) + +/* Bit definition for TMR6_PCONR register */ +#define TMR6_PCONR_CAPMDA_POS (0U) +#define TMR6_PCONR_CAPMDA (0x00000001UL) +#define TMR6_PCONR_STACA_POS (1U) +#define TMR6_PCONR_STACA (0x00000002UL) +#define TMR6_PCONR_STPCA_POS (2U) +#define TMR6_PCONR_STPCA (0x00000004UL) +#define TMR6_PCONR_STASTPSA_POS (3U) +#define TMR6_PCONR_STASTPSA (0x00000008UL) +#define TMR6_PCONR_CMPCA_POS (4U) +#define TMR6_PCONR_CMPCA (0x00000030UL) +#define TMR6_PCONR_CMPCA_0 (0x00000010UL) +#define TMR6_PCONR_CMPCA_1 (0x00000020UL) +#define TMR6_PCONR_PERCA_POS (6U) +#define TMR6_PCONR_PERCA (0x000000C0UL) +#define TMR6_PCONR_PERCA_0 (0x00000040UL) +#define TMR6_PCONR_PERCA_1 (0x00000080UL) +#define TMR6_PCONR_OUTENA_POS (8U) +#define TMR6_PCONR_OUTENA (0x00000100UL) +#define TMR6_PCONR_EMBVALA_POS (11U) +#define TMR6_PCONR_EMBVALA (0x00001800UL) +#define TMR6_PCONR_EMBVALA_0 (0x00000800UL) +#define TMR6_PCONR_EMBVALA_1 (0x00001000UL) +#define TMR6_PCONR_CAPMDB_POS (16U) +#define TMR6_PCONR_CAPMDB (0x00010000UL) +#define TMR6_PCONR_STACB_POS (17U) +#define TMR6_PCONR_STACB (0x00020000UL) +#define TMR6_PCONR_STPCB_POS (18U) +#define TMR6_PCONR_STPCB (0x00040000UL) +#define TMR6_PCONR_STASTPSB_POS (19U) +#define TMR6_PCONR_STASTPSB (0x00080000UL) +#define TMR6_PCONR_CMPCB_POS (20U) +#define TMR6_PCONR_CMPCB (0x00300000UL) +#define TMR6_PCONR_CMPCB_0 (0x00100000UL) +#define TMR6_PCONR_CMPCB_1 (0x00200000UL) +#define TMR6_PCONR_PERCB_POS (22U) +#define TMR6_PCONR_PERCB (0x00C00000UL) +#define TMR6_PCONR_PERCB_0 (0x00400000UL) +#define TMR6_PCONR_PERCB_1 (0x00800000UL) +#define TMR6_PCONR_OUTENB_POS (24U) +#define TMR6_PCONR_OUTENB (0x01000000UL) +#define TMR6_PCONR_EMBVALB_POS (27U) +#define TMR6_PCONR_EMBVALB (0x18000000UL) +#define TMR6_PCONR_EMBVALB_0 (0x08000000UL) +#define TMR6_PCONR_EMBVALB_1 (0x10000000UL) + +/* Bit definition for TMR6_BCONR register */ +#define TMR6_BCONR_BENA_POS (0U) +#define TMR6_BCONR_BENA (0x00000001UL) +#define TMR6_BCONR_BSEA_POS (1U) +#define TMR6_BCONR_BSEA (0x00000002UL) +#define TMR6_BCONR_BENB_POS (2U) +#define TMR6_BCONR_BENB (0x00000004UL) +#define TMR6_BCONR_BSEB_POS (3U) +#define TMR6_BCONR_BSEB (0x00000008UL) +#define TMR6_BCONR_BENP_POS (8U) +#define TMR6_BCONR_BENP (0x00000100UL) +#define TMR6_BCONR_BSEP_POS (9U) +#define TMR6_BCONR_BSEP (0x00000200UL) +#define TMR6_BCONR_BENSPA_POS (16U) +#define TMR6_BCONR_BENSPA (0x00010000UL) +#define TMR6_BCONR_BSESPA_POS (17U) +#define TMR6_BCONR_BSESPA (0x00020000UL) +#define TMR6_BCONR_BTRUSPA_POS (20U) +#define TMR6_BCONR_BTRUSPA (0x00100000UL) +#define TMR6_BCONR_BTRDSPA_POS (21U) +#define TMR6_BCONR_BTRDSPA (0x00200000UL) +#define TMR6_BCONR_BENSPB_POS (24U) +#define TMR6_BCONR_BENSPB (0x01000000UL) +#define TMR6_BCONR_BSESPB_POS (25U) +#define TMR6_BCONR_BSESPB (0x02000000UL) +#define TMR6_BCONR_BTRUSPB_POS (28U) +#define TMR6_BCONR_BTRUSPB (0x10000000UL) +#define TMR6_BCONR_BTRDSPB_POS (29U) +#define TMR6_BCONR_BTRDSPB (0x20000000UL) + +/* Bit definition for TMR6_DCONR register */ +#define TMR6_DCONR_DTCEN_POS (0U) +#define TMR6_DCONR_DTCEN (0x00000001UL) +#define TMR6_DCONR_DTBENU_POS (4U) +#define TMR6_DCONR_DTBENU (0x00000010UL) +#define TMR6_DCONR_DTBEND_POS (5U) +#define TMR6_DCONR_DTBEND (0x00000020UL) +#define TMR6_DCONR_SEPA_POS (8U) +#define TMR6_DCONR_SEPA (0x00000100UL) + +/* Bit definition for TMR6_FCONR register */ +#define TMR6_FCONR_NOFIENGA_POS (0U) +#define TMR6_FCONR_NOFIENGA (0x00000001UL) +#define TMR6_FCONR_NOFICKGA_POS (1U) +#define TMR6_FCONR_NOFICKGA (0x00000006UL) +#define TMR6_FCONR_NOFICKGA_0 (0x00000002UL) +#define TMR6_FCONR_NOFICKGA_1 (0x00000004UL) +#define TMR6_FCONR_NOFIENGB_POS (4U) +#define TMR6_FCONR_NOFIENGB (0x00000010UL) +#define TMR6_FCONR_NOFICKGB_POS (5U) +#define TMR6_FCONR_NOFICKGB (0x00000060UL) +#define TMR6_FCONR_NOFICKGB_0 (0x00000020UL) +#define TMR6_FCONR_NOFICKGB_1 (0x00000040UL) +#define TMR6_FCONR_NOFIENTA_POS (16U) +#define TMR6_FCONR_NOFIENTA (0x00010000UL) +#define TMR6_FCONR_NOFICKTA_POS (17U) +#define TMR6_FCONR_NOFICKTA (0x00060000UL) +#define TMR6_FCONR_NOFICKTA_0 (0x00020000UL) +#define TMR6_FCONR_NOFICKTA_1 (0x00040000UL) +#define TMR6_FCONR_NOFIENTB_POS (20U) +#define TMR6_FCONR_NOFIENTB (0x00100000UL) +#define TMR6_FCONR_NOFICKTB_POS (21U) +#define TMR6_FCONR_NOFICKTB (0x00600000UL) +#define TMR6_FCONR_NOFICKTB_0 (0x00200000UL) +#define TMR6_FCONR_NOFICKTB_1 (0x00400000UL) + +/* Bit definition for TMR6_VPERR register */ +#define TMR6_VPERR_SPPERIA_POS (8U) +#define TMR6_VPERR_SPPERIA (0x00000100UL) +#define TMR6_VPERR_SPPERIB_POS (9U) +#define TMR6_VPERR_SPPERIB (0x00000200UL) +#define TMR6_VPERR_PCNTE_POS (16U) +#define TMR6_VPERR_PCNTE (0x00030000UL) +#define TMR6_VPERR_PCNTE_0 (0x00010000UL) +#define TMR6_VPERR_PCNTE_1 (0x00020000UL) +#define TMR6_VPERR_PCNTS_POS (18U) +#define TMR6_VPERR_PCNTS (0x001C0000UL) + +/* Bit definition for TMR6_STFLR register */ +#define TMR6_STFLR_CMAF_POS (0U) +#define TMR6_STFLR_CMAF (0x00000001UL) +#define TMR6_STFLR_CMBF_POS (1U) +#define TMR6_STFLR_CMBF (0x00000002UL) +#define TMR6_STFLR_CMCF_POS (2U) +#define TMR6_STFLR_CMCF (0x00000004UL) +#define TMR6_STFLR_CMDF_POS (3U) +#define TMR6_STFLR_CMDF (0x00000008UL) +#define TMR6_STFLR_CMEF_POS (4U) +#define TMR6_STFLR_CMEF (0x00000010UL) +#define TMR6_STFLR_CMFF_POS (5U) +#define TMR6_STFLR_CMFF (0x00000020UL) +#define TMR6_STFLR_OVFF_POS (6U) +#define TMR6_STFLR_OVFF (0x00000040UL) +#define TMR6_STFLR_UDFF_POS (7U) +#define TMR6_STFLR_UDFF (0x00000080UL) +#define TMR6_STFLR_DTEF_POS (8U) +#define TMR6_STFLR_DTEF (0x00000100UL) +#define TMR6_STFLR_CMSAUF_POS (9U) +#define TMR6_STFLR_CMSAUF (0x00000200UL) +#define TMR6_STFLR_CMSADF_POS (10U) +#define TMR6_STFLR_CMSADF (0x00000400UL) +#define TMR6_STFLR_CMSBUF_POS (11U) +#define TMR6_STFLR_CMSBUF (0x00000800UL) +#define TMR6_STFLR_CMSBDF_POS (12U) +#define TMR6_STFLR_CMSBDF (0x00001000UL) +#define TMR6_STFLR_VPERNUM_POS (21U) +#define TMR6_STFLR_VPERNUM (0x00E00000UL) +#define TMR6_STFLR_DIRF_POS (31U) +#define TMR6_STFLR_DIRF (0x80000000UL) + +/* Bit definition for TMR6_HSTAR register */ +#define TMR6_HSTAR_HSTA0_POS (0U) +#define TMR6_HSTAR_HSTA0 (0x00000001UL) +#define TMR6_HSTAR_HSTA1_POS (1U) +#define TMR6_HSTAR_HSTA1 (0x00000002UL) +#define TMR6_HSTAR_HSTA4_POS (4U) +#define TMR6_HSTAR_HSTA4 (0x00000010UL) +#define TMR6_HSTAR_HSTA5_POS (5U) +#define TMR6_HSTAR_HSTA5 (0x00000020UL) +#define TMR6_HSTAR_HSTA6_POS (6U) +#define TMR6_HSTAR_HSTA6 (0x00000040UL) +#define TMR6_HSTAR_HSTA7_POS (7U) +#define TMR6_HSTAR_HSTA7 (0x00000080UL) +#define TMR6_HSTAR_HSTA8_POS (8U) +#define TMR6_HSTAR_HSTA8 (0x00000100UL) +#define TMR6_HSTAR_HSTA9_POS (9U) +#define TMR6_HSTAR_HSTA9 (0x00000200UL) +#define TMR6_HSTAR_HSTA10_POS (10U) +#define TMR6_HSTAR_HSTA10 (0x00000400UL) +#define TMR6_HSTAR_HSTA11_POS (11U) +#define TMR6_HSTAR_HSTA11 (0x00000800UL) +#define TMR6_HSTAR_STAS_POS (31U) +#define TMR6_HSTAR_STAS (0x80000000UL) + +/* Bit definition for TMR6_HSTPR register */ +#define TMR6_HSTPR_HSTP0_POS (0U) +#define TMR6_HSTPR_HSTP0 (0x00000001UL) +#define TMR6_HSTPR_HSTP1_POS (1U) +#define TMR6_HSTPR_HSTP1 (0x00000002UL) +#define TMR6_HSTPR_HSTP4_POS (4U) +#define TMR6_HSTPR_HSTP4 (0x00000010UL) +#define TMR6_HSTPR_HSTP5_POS (5U) +#define TMR6_HSTPR_HSTP5 (0x00000020UL) +#define TMR6_HSTPR_HSTP6_POS (6U) +#define TMR6_HSTPR_HSTP6 (0x00000040UL) +#define TMR6_HSTPR_HSTP7_POS (7U) +#define TMR6_HSTPR_HSTP7 (0x00000080UL) +#define TMR6_HSTPR_HSTP8_POS (8U) +#define TMR6_HSTPR_HSTP8 (0x00000100UL) +#define TMR6_HSTPR_HSTP9_POS (9U) +#define TMR6_HSTPR_HSTP9 (0x00000200UL) +#define TMR6_HSTPR_HSTP10_POS (10U) +#define TMR6_HSTPR_HSTP10 (0x00000400UL) +#define TMR6_HSTPR_HSTP11_POS (11U) +#define TMR6_HSTPR_HSTP11 (0x00000800UL) +#define TMR6_HSTPR_STPS_POS (31U) +#define TMR6_HSTPR_STPS (0x80000000UL) + +/* Bit definition for TMR6_HCLRR register */ +#define TMR6_HCLRR_HCLE0_POS (0U) +#define TMR6_HCLRR_HCLE0 (0x00000001UL) +#define TMR6_HCLRR_HCLE1_POS (1U) +#define TMR6_HCLRR_HCLE1 (0x00000002UL) +#define TMR6_HCLRR_HCLE4_POS (4U) +#define TMR6_HCLRR_HCLE4 (0x00000010UL) +#define TMR6_HCLRR_HCLE5_POS (5U) +#define TMR6_HCLRR_HCLE5 (0x00000020UL) +#define TMR6_HCLRR_HCLE6_POS (6U) +#define TMR6_HCLRR_HCLE6 (0x00000040UL) +#define TMR6_HCLRR_HCLE7_POS (7U) +#define TMR6_HCLRR_HCLE7 (0x00000080UL) +#define TMR6_HCLRR_HCLE8_POS (8U) +#define TMR6_HCLRR_HCLE8 (0x00000100UL) +#define TMR6_HCLRR_HCLE9_POS (9U) +#define TMR6_HCLRR_HCLE9 (0x00000200UL) +#define TMR6_HCLRR_HCLE10_POS (10U) +#define TMR6_HCLRR_HCLE10 (0x00000400UL) +#define TMR6_HCLRR_HCLE11_POS (11U) +#define TMR6_HCLRR_HCLE11 (0x00000800UL) +#define TMR6_HCLRR_CLES_POS (31U) +#define TMR6_HCLRR_CLES (0x80000000UL) + +/* Bit definition for TMR6_HCPAR register */ +#define TMR6_HCPAR_HCPA0_POS (0U) +#define TMR6_HCPAR_HCPA0 (0x00000001UL) +#define TMR6_HCPAR_HCPA1_POS (1U) +#define TMR6_HCPAR_HCPA1 (0x00000002UL) +#define TMR6_HCPAR_HCPA4_POS (4U) +#define TMR6_HCPAR_HCPA4 (0x00000010UL) +#define TMR6_HCPAR_HCPA5_POS (5U) +#define TMR6_HCPAR_HCPA5 (0x00000020UL) +#define TMR6_HCPAR_HCPA6_POS (6U) +#define TMR6_HCPAR_HCPA6 (0x00000040UL) +#define TMR6_HCPAR_HCPA7_POS (7U) +#define TMR6_HCPAR_HCPA7 (0x00000080UL) +#define TMR6_HCPAR_HCPA8_POS (8U) +#define TMR6_HCPAR_HCPA8 (0x00000100UL) +#define TMR6_HCPAR_HCPA9_POS (9U) +#define TMR6_HCPAR_HCPA9 (0x00000200UL) +#define TMR6_HCPAR_HCPA10_POS (10U) +#define TMR6_HCPAR_HCPA10 (0x00000400UL) +#define TMR6_HCPAR_HCPA11_POS (11U) +#define TMR6_HCPAR_HCPA11 (0x00000800UL) + +/* Bit definition for TMR6_HCPBR register */ +#define TMR6_HCPBR_HCPB0_POS (0U) +#define TMR6_HCPBR_HCPB0 (0x00000001UL) +#define TMR6_HCPBR_HCPB1_POS (1U) +#define TMR6_HCPBR_HCPB1 (0x00000002UL) +#define TMR6_HCPBR_HCPB4_POS (4U) +#define TMR6_HCPBR_HCPB4 (0x00000010UL) +#define TMR6_HCPBR_HCPB5_POS (5U) +#define TMR6_HCPBR_HCPB5 (0x00000020UL) +#define TMR6_HCPBR_HCPB6_POS (6U) +#define TMR6_HCPBR_HCPB6 (0x00000040UL) +#define TMR6_HCPBR_HCPB7_POS (7U) +#define TMR6_HCPBR_HCPB7 (0x00000080UL) +#define TMR6_HCPBR_HCPB8_POS (8U) +#define TMR6_HCPBR_HCPB8 (0x00000100UL) +#define TMR6_HCPBR_HCPB9_POS (9U) +#define TMR6_HCPBR_HCPB9 (0x00000200UL) +#define TMR6_HCPBR_HCPB10_POS (10U) +#define TMR6_HCPBR_HCPB10 (0x00000400UL) +#define TMR6_HCPBR_HCPB11_POS (11U) +#define TMR6_HCPBR_HCPB11 (0x00000800UL) + +/* Bit definition for TMR6_HCUPR register */ +#define TMR6_HCUPR_HCUP0_POS (0U) +#define TMR6_HCUPR_HCUP0 (0x00000001UL) +#define TMR6_HCUPR_HCUP1_POS (1U) +#define TMR6_HCUPR_HCUP1 (0x00000002UL) +#define TMR6_HCUPR_HCUP2_POS (2U) +#define TMR6_HCUPR_HCUP2 (0x00000004UL) +#define TMR6_HCUPR_HCUP3_POS (3U) +#define TMR6_HCUPR_HCUP3 (0x00000008UL) +#define TMR6_HCUPR_HCUP4_POS (4U) +#define TMR6_HCUPR_HCUP4 (0x00000010UL) +#define TMR6_HCUPR_HCUP5_POS (5U) +#define TMR6_HCUPR_HCUP5 (0x00000020UL) +#define TMR6_HCUPR_HCUP6_POS (6U) +#define TMR6_HCUPR_HCUP6 (0x00000040UL) +#define TMR6_HCUPR_HCUP7_POS (7U) +#define TMR6_HCUPR_HCUP7 (0x00000080UL) +#define TMR6_HCUPR_HCUP8_POS (8U) +#define TMR6_HCUPR_HCUP8 (0x00000100UL) +#define TMR6_HCUPR_HCUP9_POS (9U) +#define TMR6_HCUPR_HCUP9 (0x00000200UL) +#define TMR6_HCUPR_HCUP10_POS (10U) +#define TMR6_HCUPR_HCUP10 (0x00000400UL) +#define TMR6_HCUPR_HCUP11_POS (11U) +#define TMR6_HCUPR_HCUP11 (0x00000800UL) +#define TMR6_HCUPR_HCUP16_POS (16U) +#define TMR6_HCUPR_HCUP16 (0x00010000UL) +#define TMR6_HCUPR_HCUP17_POS (17U) +#define TMR6_HCUPR_HCUP17 (0x00020000UL) + +/* Bit definition for TMR6_HCDOR register */ +#define TMR6_HCDOR_HCDO0_POS (0U) +#define TMR6_HCDOR_HCDO0 (0x00000001UL) +#define TMR6_HCDOR_HCDO1_POS (1U) +#define TMR6_HCDOR_HCDO1 (0x00000002UL) +#define TMR6_HCDOR_HCDO2_POS (2U) +#define TMR6_HCDOR_HCDO2 (0x00000004UL) +#define TMR6_HCDOR_HCDO3_POS (3U) +#define TMR6_HCDOR_HCDO3 (0x00000008UL) +#define TMR6_HCDOR_HCDO4_POS (4U) +#define TMR6_HCDOR_HCDO4 (0x00000010UL) +#define TMR6_HCDOR_HCDO5_POS (5U) +#define TMR6_HCDOR_HCDO5 (0x00000020UL) +#define TMR6_HCDOR_HCDO6_POS (6U) +#define TMR6_HCDOR_HCDO6 (0x00000040UL) +#define TMR6_HCDOR_HCDO7_POS (7U) +#define TMR6_HCDOR_HCDO7 (0x00000080UL) +#define TMR6_HCDOR_HCDO8_POS (8U) +#define TMR6_HCDOR_HCDO8 (0x00000100UL) +#define TMR6_HCDOR_HCDO9_POS (9U) +#define TMR6_HCDOR_HCDO9 (0x00000200UL) +#define TMR6_HCDOR_HCDO10_POS (10U) +#define TMR6_HCDOR_HCDO10 (0x00000400UL) +#define TMR6_HCDOR_HCDO11_POS (11U) +#define TMR6_HCDOR_HCDO11 (0x00000800UL) +#define TMR6_HCDOR_HCDO16_POS (16U) +#define TMR6_HCDOR_HCDO16 (0x00010000UL) +#define TMR6_HCDOR_HCDO17_POS (17U) +#define TMR6_HCDOR_HCDO17 (0x00020000UL) + +/******************************************************************************* + Bit definition for Peripheral TMR6_COMMON +*******************************************************************************/ +/* Bit definition for TMR6_COMMON_SSTAR register */ +#define TMR6_COMMON_SSTAR_SSTA1_POS (0U) +#define TMR6_COMMON_SSTAR_SSTA1 (0x00000001UL) +#define TMR6_COMMON_SSTAR_SSTA2_POS (1U) +#define TMR6_COMMON_SSTAR_SSTA2 (0x00000002UL) +#define TMR6_COMMON_SSTAR_SSTA3_POS (2U) +#define TMR6_COMMON_SSTAR_SSTA3 (0x00000004UL) + +/* Bit definition for TMR6_COMMON_SSTPR register */ +#define TMR6_COMMON_SSTPR_SSTP1_POS (0U) +#define TMR6_COMMON_SSTPR_SSTP1 (0x00000001UL) +#define TMR6_COMMON_SSTPR_SSTP2_POS (1U) +#define TMR6_COMMON_SSTPR_SSTP2 (0x00000002UL) +#define TMR6_COMMON_SSTPR_SSTP3_POS (2U) +#define TMR6_COMMON_SSTPR_SSTP3 (0x00000004UL) + +/* Bit definition for TMR6_COMMON_SCLRR register */ +#define TMR6_COMMON_SCLRR_SCLE1_POS (0U) +#define TMR6_COMMON_SCLRR_SCLE1 (0x00000001UL) +#define TMR6_COMMON_SCLRR_SCLE2_POS (1U) +#define TMR6_COMMON_SCLRR_SCLE2 (0x00000002UL) +#define TMR6_COMMON_SCLRR_SCLE3_POS (2U) +#define TMR6_COMMON_SCLRR_SCLE3 (0x00000004UL) + +/******************************************************************************* + Bit definition for Peripheral TMRA +*******************************************************************************/ +/* Bit definition for TMRA_CNTER register */ +#define TMRA_CNTER_CNT (0xFFFFU) + +/* Bit definition for TMRA_PERAR register */ +#define TMRA_PERAR_PER (0xFFFFU) + +/* Bit definition for TMRA_CMPAR register */ +#define TMRA_CMPAR_CMP (0xFFFFU) + +/* Bit definition for TMRA_BCSTRL register */ +#define TMRA_BCSTRL_START_POS (0U) +#define TMRA_BCSTRL_START (0x01U) +#define TMRA_BCSTRL_DIR_POS (1U) +#define TMRA_BCSTRL_DIR (0x02U) +#define TMRA_BCSTRL_MODE_POS (2U) +#define TMRA_BCSTRL_MODE (0x04U) +#define TMRA_BCSTRL_SYNST_POS (3U) +#define TMRA_BCSTRL_SYNST (0x08U) +#define TMRA_BCSTRL_CKDIV_POS (4U) +#define TMRA_BCSTRL_CKDIV (0xF0U) + +/* Bit definition for TMRA_BCSTRH register */ +#define TMRA_BCSTRH_OVSTP_POS (0U) +#define TMRA_BCSTRH_OVSTP (0x01U) +#define TMRA_BCSTRH_ITENOVF_POS (4U) +#define TMRA_BCSTRH_ITENOVF (0x10U) +#define TMRA_BCSTRH_ITENUDF_POS (5U) +#define TMRA_BCSTRH_ITENUDF (0x20U) +#define TMRA_BCSTRH_OVFF_POS (6U) +#define TMRA_BCSTRH_OVFF (0x40U) +#define TMRA_BCSTRH_UDFF_POS (7U) +#define TMRA_BCSTRH_UDFF (0x80U) + +/* Bit definition for TMRA_HCONR register */ +#define TMRA_HCONR_HSTA0_POS (0U) +#define TMRA_HCONR_HSTA0 (0x0001U) +#define TMRA_HCONR_HSTA1_POS (1U) +#define TMRA_HCONR_HSTA1 (0x0002U) +#define TMRA_HCONR_HSTA2_POS (2U) +#define TMRA_HCONR_HSTA2 (0x0004U) +#define TMRA_HCONR_HSTP0_POS (4U) +#define TMRA_HCONR_HSTP0 (0x0010U) +#define TMRA_HCONR_HSTP1_POS (5U) +#define TMRA_HCONR_HSTP1 (0x0020U) +#define TMRA_HCONR_HSTP2_POS (6U) +#define TMRA_HCONR_HSTP2 (0x0040U) +#define TMRA_HCONR_HCLE0_POS (8U) +#define TMRA_HCONR_HCLE0 (0x0100U) +#define TMRA_HCONR_HCLE1_POS (9U) +#define TMRA_HCONR_HCLE1 (0x0200U) +#define TMRA_HCONR_HCLE2_POS (10U) +#define TMRA_HCONR_HCLE2 (0x0400U) +#define TMRA_HCONR_HCLE3_POS (12U) +#define TMRA_HCONR_HCLE3 (0x1000U) +#define TMRA_HCONR_HCLE4_POS (13U) +#define TMRA_HCONR_HCLE4 (0x2000U) +#define TMRA_HCONR_HCLE5_POS (14U) +#define TMRA_HCONR_HCLE5 (0x4000U) +#define TMRA_HCONR_HCLE6_POS (15U) +#define TMRA_HCONR_HCLE6 (0x8000U) + +/* Bit definition for TMRA_HCUPR register */ +#define TMRA_HCUPR_HCUP0_POS (0U) +#define TMRA_HCUPR_HCUP0 (0x0001U) +#define TMRA_HCUPR_HCUP1_POS (1U) +#define TMRA_HCUPR_HCUP1 (0x0002U) +#define TMRA_HCUPR_HCUP2_POS (2U) +#define TMRA_HCUPR_HCUP2 (0x0004U) +#define TMRA_HCUPR_HCUP3_POS (3U) +#define TMRA_HCUPR_HCUP3 (0x0008U) +#define TMRA_HCUPR_HCUP4_POS (4U) +#define TMRA_HCUPR_HCUP4 (0x0010U) +#define TMRA_HCUPR_HCUP5_POS (5U) +#define TMRA_HCUPR_HCUP5 (0x0020U) +#define TMRA_HCUPR_HCUP6_POS (6U) +#define TMRA_HCUPR_HCUP6 (0x0040U) +#define TMRA_HCUPR_HCUP7_POS (7U) +#define TMRA_HCUPR_HCUP7 (0x0080U) +#define TMRA_HCUPR_HCUP8_POS (8U) +#define TMRA_HCUPR_HCUP8 (0x0100U) +#define TMRA_HCUPR_HCUP9_POS (9U) +#define TMRA_HCUPR_HCUP9 (0x0200U) +#define TMRA_HCUPR_HCUP10_POS (10U) +#define TMRA_HCUPR_HCUP10 (0x0400U) +#define TMRA_HCUPR_HCUP11_POS (11U) +#define TMRA_HCUPR_HCUP11 (0x0800U) +#define TMRA_HCUPR_HCUP12_POS (12U) +#define TMRA_HCUPR_HCUP12 (0x1000U) + +/* Bit definition for TMRA_HCDOR register */ +#define TMRA_HCDOR_HCDO0_POS (0U) +#define TMRA_HCDOR_HCDO0 (0x0001U) +#define TMRA_HCDOR_HCDO1_POS (1U) +#define TMRA_HCDOR_HCDO1 (0x0002U) +#define TMRA_HCDOR_HCDO2_POS (2U) +#define TMRA_HCDOR_HCDO2 (0x0004U) +#define TMRA_HCDOR_HCDO3_POS (3U) +#define TMRA_HCDOR_HCDO3 (0x0008U) +#define TMRA_HCDOR_HCDO4_POS (4U) +#define TMRA_HCDOR_HCDO4 (0x0010U) +#define TMRA_HCDOR_HCDO5_POS (5U) +#define TMRA_HCDOR_HCDO5 (0x0020U) +#define TMRA_HCDOR_HCDO6_POS (6U) +#define TMRA_HCDOR_HCDO6 (0x0040U) +#define TMRA_HCDOR_HCDO7_POS (7U) +#define TMRA_HCDOR_HCDO7 (0x0080U) +#define TMRA_HCDOR_HCDO8_POS (8U) +#define TMRA_HCDOR_HCDO8 (0x0100U) +#define TMRA_HCDOR_HCDO9_POS (9U) +#define TMRA_HCDOR_HCDO9 (0x0200U) +#define TMRA_HCDOR_HCDO10_POS (10U) +#define TMRA_HCDOR_HCDO10 (0x0400U) +#define TMRA_HCDOR_HCDO11_POS (11U) +#define TMRA_HCDOR_HCDO11 (0x0800U) +#define TMRA_HCDOR_HCDO12_POS (12U) +#define TMRA_HCDOR_HCDO12 (0x1000U) + +/* Bit definition for TMRA_ICONR register */ +#define TMRA_ICONR_ITEN1_POS (0U) +#define TMRA_ICONR_ITEN1 (0x0001U) +#define TMRA_ICONR_ITEN2_POS (1U) +#define TMRA_ICONR_ITEN2 (0x0002U) +#define TMRA_ICONR_ITEN3_POS (2U) +#define TMRA_ICONR_ITEN3 (0x0004U) +#define TMRA_ICONR_ITEN4_POS (3U) +#define TMRA_ICONR_ITEN4 (0x0008U) +#define TMRA_ICONR_ITEN5_POS (4U) +#define TMRA_ICONR_ITEN5 (0x0010U) +#define TMRA_ICONR_ITEN6_POS (5U) +#define TMRA_ICONR_ITEN6 (0x0020U) +#define TMRA_ICONR_ITEN7_POS (6U) +#define TMRA_ICONR_ITEN7 (0x0040U) +#define TMRA_ICONR_ITEN8_POS (7U) +#define TMRA_ICONR_ITEN8 (0x0080U) + +/* Bit definition for TMRA_ECONR register */ +#define TMRA_ECONR_ETEN1_POS (0U) +#define TMRA_ECONR_ETEN1 (0x0001U) +#define TMRA_ECONR_ETEN2_POS (1U) +#define TMRA_ECONR_ETEN2 (0x0002U) +#define TMRA_ECONR_ETEN3_POS (2U) +#define TMRA_ECONR_ETEN3 (0x0004U) +#define TMRA_ECONR_ETEN4_POS (3U) +#define TMRA_ECONR_ETEN4 (0x0008U) +#define TMRA_ECONR_ETEN5_POS (4U) +#define TMRA_ECONR_ETEN5 (0x0010U) +#define TMRA_ECONR_ETEN6_POS (5U) +#define TMRA_ECONR_ETEN6 (0x0020U) +#define TMRA_ECONR_ETEN7_POS (6U) +#define TMRA_ECONR_ETEN7 (0x0040U) +#define TMRA_ECONR_ETEN8_POS (7U) +#define TMRA_ECONR_ETEN8 (0x0080U) + +/* Bit definition for TMRA_FCONR register */ +#define TMRA_FCONR_NOFIENTG_POS (0U) +#define TMRA_FCONR_NOFIENTG (0x0001U) +#define TMRA_FCONR_NOFICKTG_POS (1U) +#define TMRA_FCONR_NOFICKTG (0x0006U) +#define TMRA_FCONR_NOFIENCA_POS (8U) +#define TMRA_FCONR_NOFIENCA (0x0100U) +#define TMRA_FCONR_NOFICKCA_POS (9U) +#define TMRA_FCONR_NOFICKCA (0x0600U) +#define TMRA_FCONR_NOFIENCB_POS (12U) +#define TMRA_FCONR_NOFIENCB (0x1000U) +#define TMRA_FCONR_NOFICKCB_POS (13U) +#define TMRA_FCONR_NOFICKCB (0x6000U) + +/* Bit definition for TMRA_STFLR register */ +#define TMRA_STFLR_CMPF1_POS (0U) +#define TMRA_STFLR_CMPF1 (0x0001U) +#define TMRA_STFLR_CMPF2_POS (1U) +#define TMRA_STFLR_CMPF2 (0x0002U) +#define TMRA_STFLR_CMPF3_POS (2U) +#define TMRA_STFLR_CMPF3 (0x0004U) +#define TMRA_STFLR_CMPF4_POS (3U) +#define TMRA_STFLR_CMPF4 (0x0008U) +#define TMRA_STFLR_CMPF5_POS (4U) +#define TMRA_STFLR_CMPF5 (0x0010U) +#define TMRA_STFLR_CMPF6_POS (5U) +#define TMRA_STFLR_CMPF6 (0x0020U) +#define TMRA_STFLR_CMPF7_POS (6U) +#define TMRA_STFLR_CMPF7 (0x0040U) +#define TMRA_STFLR_CMPF8_POS (7U) +#define TMRA_STFLR_CMPF8 (0x0080U) + +/* Bit definition for TMRA_BCONR register */ +#define TMRA_BCONR_BEN_POS (0U) +#define TMRA_BCONR_BEN (0x0001U) +#define TMRA_BCONR_BSE0_POS (1U) +#define TMRA_BCONR_BSE0 (0x0002U) +#define TMRA_BCONR_BSE1_POS (2U) +#define TMRA_BCONR_BSE1 (0x0004U) + +/* Bit definition for TMRA_CCONR register */ +#define TMRA_CCONR_CAPMD_POS (0U) +#define TMRA_CCONR_CAPMD (0x0001U) +#define TMRA_CCONR_HICP0_POS (4U) +#define TMRA_CCONR_HICP0 (0x0010U) +#define TMRA_CCONR_HICP1_POS (5U) +#define TMRA_CCONR_HICP1 (0x0020U) +#define TMRA_CCONR_HICP2_POS (6U) +#define TMRA_CCONR_HICP2 (0x0040U) +#define TMRA_CCONR_HICP3_POS (8U) +#define TMRA_CCONR_HICP3 (0x0100U) +#define TMRA_CCONR_HICP4_POS (9U) +#define TMRA_CCONR_HICP4 (0x0200U) +#define TMRA_CCONR_NOFIENCP_POS (12U) +#define TMRA_CCONR_NOFIENCP (0x1000U) +#define TMRA_CCONR_NOFICKCP_POS (13U) +#define TMRA_CCONR_NOFICKCP (0x6000U) +#define TMRA_CCONR_NOFICKCP_0 (0x2000U) +#define TMRA_CCONR_NOFICKCP_1 (0x4000U) + +/* Bit definition for TMRA_PCONR register */ +#define TMRA_PCONR_STAC_POS (0U) +#define TMRA_PCONR_STAC (0x0003U) +#define TMRA_PCONR_STAC_0 (0x0001U) +#define TMRA_PCONR_STAC_1 (0x0002U) +#define TMRA_PCONR_STPC_POS (2U) +#define TMRA_PCONR_STPC (0x000CU) +#define TMRA_PCONR_STPC_0 (0x0004U) +#define TMRA_PCONR_STPC_1 (0x0008U) +#define TMRA_PCONR_CMPC_POS (4U) +#define TMRA_PCONR_CMPC (0x0030U) +#define TMRA_PCONR_CMPC_0 (0x0010U) +#define TMRA_PCONR_CMPC_1 (0x0020U) +#define TMRA_PCONR_PERC_POS (6U) +#define TMRA_PCONR_PERC (0x00C0U) +#define TMRA_PCONR_PERC_0 (0x0040U) +#define TMRA_PCONR_PERC_1 (0x0080U) +#define TMRA_PCONR_FORC_POS (8U) +#define TMRA_PCONR_FORC (0x0300U) +#define TMRA_PCONR_FORC_0 (0x0100U) +#define TMRA_PCONR_FORC_1 (0x0200U) +#define TMRA_PCONR_OUTEN_POS (12U) +#define TMRA_PCONR_OUTEN (0x1000U) + +/******************************************************************************* + Bit definition for Peripheral TRNG +*******************************************************************************/ +/* Bit definition for TRNG_CR register */ +#define TRNG_CR_EN_POS (0U) +#define TRNG_CR_EN (0x00000001UL) +#define TRNG_CR_RUN_POS (1U) +#define TRNG_CR_RUN (0x00000002UL) + +/* Bit definition for TRNG_MR register */ +#define TRNG_MR_LOAD_POS (0U) +#define TRNG_MR_LOAD (0x00000001UL) +#define TRNG_MR_CNT_POS (2U) +#define TRNG_MR_CNT (0x0000001CUL) + +/* Bit definition for TRNG_DR0 register */ +#define TRNG_DR0 (0xFFFFFFFFUL) + +/* Bit definition for TRNG_DR1 register */ +#define TRNG_DR1 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral USART +*******************************************************************************/ +/* Bit definition for USART_SR register */ +#define USART_SR_PE_POS (0U) +#define USART_SR_PE (0x00000001UL) +#define USART_SR_FE_POS (1U) +#define USART_SR_FE (0x00000002UL) +#define USART_SR_ORE_POS (3U) +#define USART_SR_ORE (0x00000008UL) +#define USART_SR_RXNE_POS (5U) +#define USART_SR_RXNE (0x00000020UL) +#define USART_SR_TC_POS (6U) +#define USART_SR_TC (0x00000040UL) +#define USART_SR_TXE_POS (7U) +#define USART_SR_TXE (0x00000080UL) +#define USART_SR_RTOF_POS (8U) +#define USART_SR_RTOF (0x00000100UL) +#define USART_SR_MPB_POS (16U) +#define USART_SR_MPB (0x00010000UL) + +/* Bit definition for USART_TDR register */ +#define USART_TDR_TDR_POS (0U) +#define USART_TDR_TDR (0x01FFU) +#define USART_TDR_MPID_POS (9U) +#define USART_TDR_MPID (0x0200U) + +/* Bit definition for USART_RDR register */ +#define USART_RDR_RDR (0x01FFU) + +/* Bit definition for USART_BRR register */ +#define USART_BRR_DIV_FRACTION_POS (0U) +#define USART_BRR_DIV_FRACTION (0x0000007FUL) +#define USART_BRR_DIV_INTEGER_POS (8U) +#define USART_BRR_DIV_INTEGER (0x0000FF00UL) + +/* Bit definition for USART_CR1 register */ +#define USART_CR1_RTOE_POS (0U) +#define USART_CR1_RTOE (0x00000001UL) +#define USART_CR1_RTOIE_POS (1U) +#define USART_CR1_RTOIE (0x00000002UL) +#define USART_CR1_RE_POS (2U) +#define USART_CR1_RE (0x00000004UL) +#define USART_CR1_TE_POS (3U) +#define USART_CR1_TE (0x00000008UL) +#define USART_CR1_SLME_POS (4U) +#define USART_CR1_SLME (0x00000010UL) +#define USART_CR1_RIE_POS (5U) +#define USART_CR1_RIE (0x00000020UL) +#define USART_CR1_TCIE_POS (6U) +#define USART_CR1_TCIE (0x00000040UL) +#define USART_CR1_TXEIE_POS (7U) +#define USART_CR1_TXEIE (0x00000080UL) +#define USART_CR1_PS_POS (9U) +#define USART_CR1_PS (0x00000200UL) +#define USART_CR1_PCE_POS (10U) +#define USART_CR1_PCE (0x00000400UL) +#define USART_CR1_M_POS (12U) +#define USART_CR1_M (0x00001000UL) +#define USART_CR1_OVER8_POS (15U) +#define USART_CR1_OVER8 (0x00008000UL) +#define USART_CR1_CPE_POS (16U) +#define USART_CR1_CPE (0x00010000UL) +#define USART_CR1_CFE_POS (17U) +#define USART_CR1_CFE (0x00020000UL) +#define USART_CR1_CORE_POS (19U) +#define USART_CR1_CORE (0x00080000UL) +#define USART_CR1_CRTOF_POS (20U) +#define USART_CR1_CRTOF (0x00100000UL) +#define USART_CR1_MS_POS (24U) +#define USART_CR1_MS (0x01000000UL) +#define USART_CR1_ML_POS (28U) +#define USART_CR1_ML (0x10000000UL) +#define USART_CR1_FBME_POS (29U) +#define USART_CR1_FBME (0x20000000UL) +#define USART_CR1_NFE_POS (30U) +#define USART_CR1_NFE (0x40000000UL) +#define USART_CR1_SBS_POS (31U) +#define USART_CR1_SBS (0x80000000UL) + +/* Bit definition for USART_CR2 register */ +#define USART_CR2_MPE_POS (0U) +#define USART_CR2_MPE (0x00000001UL) +#define USART_CR2_CLKC_POS (11U) +#define USART_CR2_CLKC (0x00001800UL) +#define USART_CR2_CLKC_0 (0x00000800UL) +#define USART_CR2_CLKC_1 (0x00001000UL) +#define USART_CR2_STOP_POS (13U) +#define USART_CR2_STOP (0x00002000UL) + +/* Bit definition for USART_CR3 register */ +#define USART_CR3_SCEN_POS (5U) +#define USART_CR3_SCEN (0x00000020UL) +#define USART_CR3_CTSE_POS (9U) +#define USART_CR3_CTSE (0x00000200UL) +#define USART_CR3_BCN_POS (21U) +#define USART_CR3_BCN (0x00E00000UL) + +/* Bit definition for USART_PR register */ +#define USART_PR_PSC (0x00000003UL) +#define USART_PR_PSC_0 (0x00000001UL) +#define USART_PR_PSC_1 (0x00000002UL) + +/******************************************************************************* + Bit definition for Peripheral USBFS +*******************************************************************************/ +/* Bit definition for USBFS_GVBUSCFG register */ +#define USBFS_GVBUSCFG_VBUSOVEN_POS (6U) +#define USBFS_GVBUSCFG_VBUSOVEN (0x00000040UL) +#define USBFS_GVBUSCFG_VBUSVAL_POS (7U) +#define USBFS_GVBUSCFG_VBUSVAL (0x00000080UL) + +/* Bit definition for USBFS_GAHBCFG register */ +#define USBFS_GAHBCFG_GINTMSK_POS (0U) +#define USBFS_GAHBCFG_GINTMSK (0x00000001UL) +#define USBFS_GAHBCFG_HBSTLEN_POS (1U) +#define USBFS_GAHBCFG_HBSTLEN (0x0000001EUL) +#define USBFS_GAHBCFG_DMAEN_POS (5U) +#define USBFS_GAHBCFG_DMAEN (0x00000020UL) +#define USBFS_GAHBCFG_TXFELVL_POS (7U) +#define USBFS_GAHBCFG_TXFELVL (0x00000080UL) +#define USBFS_GAHBCFG_PTXFELVL_POS (8U) +#define USBFS_GAHBCFG_PTXFELVL (0x00000100UL) + +/* Bit definition for USBFS_GUSBCFG register */ +#define USBFS_GUSBCFG_TOCAL_POS (0U) +#define USBFS_GUSBCFG_TOCAL (0x00000007UL) +#define USBFS_GUSBCFG_PHYSEL_POS (6U) +#define USBFS_GUSBCFG_PHYSEL (0x00000040UL) +#define USBFS_GUSBCFG_TRDT_POS (10U) +#define USBFS_GUSBCFG_TRDT (0x00003C00UL) +#define USBFS_GUSBCFG_FHMOD_POS (29U) +#define USBFS_GUSBCFG_FHMOD (0x20000000UL) +#define USBFS_GUSBCFG_FDMOD_POS (30U) +#define USBFS_GUSBCFG_FDMOD (0x40000000UL) + +/* Bit definition for USBFS_GRSTCTL register */ +#define USBFS_GRSTCTL_CSRST_POS (0U) +#define USBFS_GRSTCTL_CSRST (0x00000001UL) +#define USBFS_GRSTCTL_HSRST_POS (1U) +#define USBFS_GRSTCTL_HSRST (0x00000002UL) +#define USBFS_GRSTCTL_FCRST_POS (2U) +#define USBFS_GRSTCTL_FCRST (0x00000004UL) +#define USBFS_GRSTCTL_RXFFLSH_POS (4U) +#define USBFS_GRSTCTL_RXFFLSH (0x00000010UL) +#define USBFS_GRSTCTL_TXFFLSH_POS (5U) +#define USBFS_GRSTCTL_TXFFLSH (0x00000020UL) +#define USBFS_GRSTCTL_TXFNUM_POS (6U) +#define USBFS_GRSTCTL_TXFNUM (0x000007C0UL) +#define USBFS_GRSTCTL_DMAREQ_POS (30U) +#define USBFS_GRSTCTL_DMAREQ (0x40000000UL) +#define USBFS_GRSTCTL_AHBIDL_POS (31U) +#define USBFS_GRSTCTL_AHBIDL (0x80000000UL) + +/* Bit definition for USBFS_GINTSTS register */ +#define USBFS_GINTSTS_CMOD_POS (0U) +#define USBFS_GINTSTS_CMOD (0x00000001UL) +#define USBFS_GINTSTS_MMIS_POS (1U) +#define USBFS_GINTSTS_MMIS (0x00000002UL) +#define USBFS_GINTSTS_SOF_POS (3U) +#define USBFS_GINTSTS_SOF (0x00000008UL) +#define USBFS_GINTSTS_RXFNE_POS (4U) +#define USBFS_GINTSTS_RXFNE (0x00000010UL) +#define USBFS_GINTSTS_NPTXFE_POS (5U) +#define USBFS_GINTSTS_NPTXFE (0x00000020UL) +#define USBFS_GINTSTS_GINAKEFF_POS (6U) +#define USBFS_GINTSTS_GINAKEFF (0x00000040UL) +#define USBFS_GINTSTS_GONAKEFF_POS (7U) +#define USBFS_GINTSTS_GONAKEFF (0x00000080UL) +#define USBFS_GINTSTS_ESUSP_POS (10U) +#define USBFS_GINTSTS_ESUSP (0x00000400UL) +#define USBFS_GINTSTS_USBSUSP_POS (11U) +#define USBFS_GINTSTS_USBSUSP (0x00000800UL) +#define USBFS_GINTSTS_USBRST_POS (12U) +#define USBFS_GINTSTS_USBRST (0x00001000UL) +#define USBFS_GINTSTS_ENUMDNE_POS (13U) +#define USBFS_GINTSTS_ENUMDNE (0x00002000UL) +#define USBFS_GINTSTS_ISOODRP_POS (14U) +#define USBFS_GINTSTS_ISOODRP (0x00004000UL) +#define USBFS_GINTSTS_EOPF_POS (15U) +#define USBFS_GINTSTS_EOPF (0x00008000UL) +#define USBFS_GINTSTS_IEPINT_POS (18U) +#define USBFS_GINTSTS_IEPINT (0x00040000UL) +#define USBFS_GINTSTS_OEPINT_POS (19U) +#define USBFS_GINTSTS_OEPINT (0x00080000UL) +#define USBFS_GINTSTS_IISOIXFR_POS (20U) +#define USBFS_GINTSTS_IISOIXFR (0x00100000UL) +#define USBFS_GINTSTS_IPXFR_INCOMPISOOUT_POS (21U) +#define USBFS_GINTSTS_IPXFR_INCOMPISOOUT (0x00200000UL) +#define USBFS_GINTSTS_DATAFSUSP_POS (22U) +#define USBFS_GINTSTS_DATAFSUSP (0x00400000UL) +#define USBFS_GINTSTS_HPRTINT_POS (24U) +#define USBFS_GINTSTS_HPRTINT (0x01000000UL) +#define USBFS_GINTSTS_HCINT_POS (25U) +#define USBFS_GINTSTS_HCINT (0x02000000UL) +#define USBFS_GINTSTS_PTXFE_POS (26U) +#define USBFS_GINTSTS_PTXFE (0x04000000UL) +#define USBFS_GINTSTS_CIDSCHG_POS (28U) +#define USBFS_GINTSTS_CIDSCHG (0x10000000UL) +#define USBFS_GINTSTS_DISCINT_POS (29U) +#define USBFS_GINTSTS_DISCINT (0x20000000UL) +#define USBFS_GINTSTS_VBUSVINT_POS (30U) +#define USBFS_GINTSTS_VBUSVINT (0x40000000UL) +#define USBFS_GINTSTS_WKUINT_POS (31U) +#define USBFS_GINTSTS_WKUINT (0x80000000UL) + +/* Bit definition for USBFS_GINTMSK register */ +#define USBFS_GINTMSK_MMISM_POS (1U) +#define USBFS_GINTMSK_MMISM (0x00000002UL) +#define USBFS_GINTMSK_SOFM_POS (3U) +#define USBFS_GINTMSK_SOFM (0x00000008UL) +#define USBFS_GINTMSK_RXFNEM_POS (4U) +#define USBFS_GINTMSK_RXFNEM (0x00000010UL) +#define USBFS_GINTMSK_NPTXFEM_POS (5U) +#define USBFS_GINTMSK_NPTXFEM (0x00000020UL) +#define USBFS_GINTMSK_GINAKEFFM_POS (6U) +#define USBFS_GINTMSK_GINAKEFFM (0x00000040UL) +#define USBFS_GINTMSK_GONAKEFFM_POS (7U) +#define USBFS_GINTMSK_GONAKEFFM (0x00000080UL) +#define USBFS_GINTMSK_ESUSPM_POS (10U) +#define USBFS_GINTMSK_ESUSPM (0x00000400UL) +#define USBFS_GINTMSK_USBSUSPM_POS (11U) +#define USBFS_GINTMSK_USBSUSPM (0x00000800UL) +#define USBFS_GINTMSK_USBRSTM_POS (12U) +#define USBFS_GINTMSK_USBRSTM (0x00001000UL) +#define USBFS_GINTMSK_ENUMDNEM_POS (13U) +#define USBFS_GINTMSK_ENUMDNEM (0x00002000UL) +#define USBFS_GINTMSK_ISOODRPM_POS (14U) +#define USBFS_GINTMSK_ISOODRPM (0x00004000UL) +#define USBFS_GINTMSK_EOPFM_POS (15U) +#define USBFS_GINTMSK_EOPFM (0x00008000UL) +#define USBFS_GINTMSK_IEPIM_POS (18U) +#define USBFS_GINTMSK_IEPIM (0x00040000UL) +#define USBFS_GINTMSK_OEPIM_POS (19U) +#define USBFS_GINTMSK_OEPIM (0x00080000UL) +#define USBFS_GINTMSK_IISOIXFRM_POS (20U) +#define USBFS_GINTMSK_IISOIXFRM (0x00100000UL) +#define USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM_POS (21U) +#define USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM (0x00200000UL) +#define USBFS_GINTMSK_DATAFSUSPM_POS (22U) +#define USBFS_GINTMSK_DATAFSUSPM (0x00400000UL) +#define USBFS_GINTMSK_HPRTIM_POS (24U) +#define USBFS_GINTMSK_HPRTIM (0x01000000UL) +#define USBFS_GINTMSK_HCIM_POS (25U) +#define USBFS_GINTMSK_HCIM (0x02000000UL) +#define USBFS_GINTMSK_PTXFEM_POS (26U) +#define USBFS_GINTMSK_PTXFEM (0x04000000UL) +#define USBFS_GINTMSK_CIDSCHGM_POS (28U) +#define USBFS_GINTMSK_CIDSCHGM (0x10000000UL) +#define USBFS_GINTMSK_DISCIM_POS (29U) +#define USBFS_GINTMSK_DISCIM (0x20000000UL) +#define USBFS_GINTMSK_VBUSVIM_POS (30U) +#define USBFS_GINTMSK_VBUSVIM (0x40000000UL) +#define USBFS_GINTMSK_WKUIM_POS (31U) +#define USBFS_GINTMSK_WKUIM (0x80000000UL) + +/* Bit definition for USBFS_GRXSTSR register */ +#define USBFS_GRXSTSR_CHNUM_EPNUM_POS (0U) +#define USBFS_GRXSTSR_CHNUM_EPNUM (0x0000000FUL) +#define USBFS_GRXSTSR_BCNT_POS (4U) +#define USBFS_GRXSTSR_BCNT (0x00007FF0UL) +#define USBFS_GRXSTSR_DPID_POS (15U) +#define USBFS_GRXSTSR_DPID (0x00018000UL) +#define USBFS_GRXSTSR_PKTSTS_POS (17U) +#define USBFS_GRXSTSR_PKTSTS (0x001E0000UL) + +/* Bit definition for USBFS_GRXSTSP register */ +#define USBFS_GRXSTSP_CHNUM_EPNUM_POS (0U) +#define USBFS_GRXSTSP_CHNUM_EPNUM (0x0000000FUL) +#define USBFS_GRXSTSP_BCNT_POS (4U) +#define USBFS_GRXSTSP_BCNT (0x00007FF0UL) +#define USBFS_GRXSTSP_DPID_POS (15U) +#define USBFS_GRXSTSP_DPID (0x00018000UL) +#define USBFS_GRXSTSP_PKTSTS_POS (17U) +#define USBFS_GRXSTSP_PKTSTS (0x001E0000UL) + +/* Bit definition for USBFS_GRXFSIZ register */ +#define USBFS_GRXFSIZ_RXFD (0x000007FFUL) + +/* Bit definition for USBFS_HNPTXFSIZ register */ +#define USBFS_HNPTXFSIZ_NPTXFSA_POS (0U) +#define USBFS_HNPTXFSIZ_NPTXFSA (0x0000FFFFUL) +#define USBFS_HNPTXFSIZ_NPTXFD_POS (16U) +#define USBFS_HNPTXFSIZ_NPTXFD (0xFFFF0000UL) + +/* Bit definition for USBFS_HNPTXSTS register */ +#define USBFS_HNPTXSTS_NPTXFSAV_POS (0U) +#define USBFS_HNPTXSTS_NPTXFSAV (0x0000FFFFUL) +#define USBFS_HNPTXSTS_NPTQXSAV_POS (16U) +#define USBFS_HNPTXSTS_NPTQXSAV (0x00FF0000UL) +#define USBFS_HNPTXSTS_NPTXQTOP_POS (24U) +#define USBFS_HNPTXSTS_NPTXQTOP (0x7F000000UL) + +/* Bit definition for USBFS_CID register */ +#define USBFS_CID (0xFFFFFFFFUL) + +/* Bit definition for USBFS_HPTXFSIZ register */ +#define USBFS_HPTXFSIZ_PTXSA_POS (0U) +#define USBFS_HPTXFSIZ_PTXSA (0x00000FFFUL) +#define USBFS_HPTXFSIZ_PTXFD_POS (16U) +#define USBFS_HPTXFSIZ_PTXFD (0x07FF0000UL) + +/* Bit definition for USBFS_DIEPTXF register */ +#define USBFS_DIEPTXF_INEPTXSA_POS (0U) +#define USBFS_DIEPTXF_INEPTXSA (0x00000FFFUL) +#define USBFS_DIEPTXF_INEPTXFD_POS (16U) +#define USBFS_DIEPTXF_INEPTXFD (0x03FF0000UL) + +/* Bit definition for USBFS_HCFG register */ +#define USBFS_HCFG_FSLSPCS_POS (0U) +#define USBFS_HCFG_FSLSPCS (0x00000003UL) +#define USBFS_HCFG_FSLSS_POS (2U) +#define USBFS_HCFG_FSLSS (0x00000004UL) + +/* Bit definition for USBFS_HFIR register */ +#define USBFS_HFIR_FRIVL (0x0000FFFFUL) + +/* Bit definition for USBFS_HFNUM register */ +#define USBFS_HFNUM_FRNUM_POS (0U) +#define USBFS_HFNUM_FRNUM (0x0000FFFFUL) +#define USBFS_HFNUM_FTREM_POS (16U) +#define USBFS_HFNUM_FTREM (0xFFFF0000UL) + +/* Bit definition for USBFS_HPTXSTS register */ +#define USBFS_HPTXSTS_PTXFSAVL_POS (0U) +#define USBFS_HPTXSTS_PTXFSAVL (0x0000FFFFUL) +#define USBFS_HPTXSTS_PTXQSAV_POS (16U) +#define USBFS_HPTXSTS_PTXQSAV (0x00FF0000UL) +#define USBFS_HPTXSTS_PTXQTOP_POS (24U) +#define USBFS_HPTXSTS_PTXQTOP (0xFF000000UL) + +/* Bit definition for USBFS_HAINT register */ +#define USBFS_HAINT_HAINT (0x00000FFFUL) + +/* Bit definition for USBFS_HAINTMSK register */ +#define USBFS_HAINTMSK_HAINTM (0x00000FFFUL) + +/* Bit definition for USBFS_HPRT register */ +#define USBFS_HPRT_PCSTS_POS (0U) +#define USBFS_HPRT_PCSTS (0x00000001UL) +#define USBFS_HPRT_PCDET_POS (1U) +#define USBFS_HPRT_PCDET (0x00000002UL) +#define USBFS_HPRT_PENA_POS (2U) +#define USBFS_HPRT_PENA (0x00000004UL) +#define USBFS_HPRT_PENCHNG_POS (3U) +#define USBFS_HPRT_PENCHNG (0x00000008UL) +#define USBFS_HPRT_PRES_POS (6U) +#define USBFS_HPRT_PRES (0x00000040UL) +#define USBFS_HPRT_PSUSP_POS (7U) +#define USBFS_HPRT_PSUSP (0x00000080UL) +#define USBFS_HPRT_PRST_POS (8U) +#define USBFS_HPRT_PRST (0x00000100UL) +#define USBFS_HPRT_PLSTS_POS (10U) +#define USBFS_HPRT_PLSTS (0x00000C00UL) +#define USBFS_HPRT_PWPR_POS (12U) +#define USBFS_HPRT_PWPR (0x00001000UL) +#define USBFS_HPRT_PSPD_POS (17U) +#define USBFS_HPRT_PSPD (0x00060000UL) + +/* Bit definition for USBFS_HCCHAR register */ +#define USBFS_HCCHAR_MPSIZ_POS (0U) +#define USBFS_HCCHAR_MPSIZ (0x000007FFUL) +#define USBFS_HCCHAR_EPNUM_POS (11U) +#define USBFS_HCCHAR_EPNUM (0x00007800UL) +#define USBFS_HCCHAR_EPDIR_POS (15U) +#define USBFS_HCCHAR_EPDIR (0x00008000UL) +#define USBFS_HCCHAR_LSDEV_POS (17U) +#define USBFS_HCCHAR_LSDEV (0x00020000UL) +#define USBFS_HCCHAR_EPTYP_POS (18U) +#define USBFS_HCCHAR_EPTYP (0x000C0000UL) +#define USBFS_HCCHAR_DAD_POS (22U) +#define USBFS_HCCHAR_DAD (0x1FC00000UL) +#define USBFS_HCCHAR_ODDFRM_POS (29U) +#define USBFS_HCCHAR_ODDFRM (0x20000000UL) +#define USBFS_HCCHAR_CHDIS_POS (30U) +#define USBFS_HCCHAR_CHDIS (0x40000000UL) +#define USBFS_HCCHAR_CHENA_POS (31U) +#define USBFS_HCCHAR_CHENA (0x80000000UL) + +/* Bit definition for USBFS_HCINT register */ +#define USBFS_HCINT_XFRC_POS (0U) +#define USBFS_HCINT_XFRC (0x00000001UL) +#define USBFS_HCINT_CHH_POS (1U) +#define USBFS_HCINT_CHH (0x00000002UL) +#define USBFS_HCINT_STALL_POS (3U) +#define USBFS_HCINT_STALL (0x00000008UL) +#define USBFS_HCINT_NAK_POS (4U) +#define USBFS_HCINT_NAK (0x00000010UL) +#define USBFS_HCINT_ACK_POS (5U) +#define USBFS_HCINT_ACK (0x00000020UL) +#define USBFS_HCINT_TXERR_POS (7U) +#define USBFS_HCINT_TXERR (0x00000080UL) +#define USBFS_HCINT_BBERR_POS (8U) +#define USBFS_HCINT_BBERR (0x00000100UL) +#define USBFS_HCINT_FRMOR_POS (9U) +#define USBFS_HCINT_FRMOR (0x00000200UL) +#define USBFS_HCINT_DTERR_POS (10U) +#define USBFS_HCINT_DTERR (0x00000400UL) + +/* Bit definition for USBFS_HCINTMSK register */ +#define USBFS_HCINTMSK_XFRCM_POS (0U) +#define USBFS_HCINTMSK_XFRCM (0x00000001UL) +#define USBFS_HCINTMSK_CHHM_POS (1U) +#define USBFS_HCINTMSK_CHHM (0x00000002UL) +#define USBFS_HCINTMSK_STALLM_POS (3U) +#define USBFS_HCINTMSK_STALLM (0x00000008UL) +#define USBFS_HCINTMSK_NAKM_POS (4U) +#define USBFS_HCINTMSK_NAKM (0x00000010UL) +#define USBFS_HCINTMSK_ACKM_POS (5U) +#define USBFS_HCINTMSK_ACKM (0x00000020UL) +#define USBFS_HCINTMSK_TXERRM_POS (7U) +#define USBFS_HCINTMSK_TXERRM (0x00000080UL) +#define USBFS_HCINTMSK_BBERRM_POS (8U) +#define USBFS_HCINTMSK_BBERRM (0x00000100UL) +#define USBFS_HCINTMSK_FRMORM_POS (9U) +#define USBFS_HCINTMSK_FRMORM (0x00000200UL) +#define USBFS_HCINTMSK_DTERRM_POS (10U) +#define USBFS_HCINTMSK_DTERRM (0x00000400UL) + +/* Bit definition for USBFS_HCTSIZ register */ +#define USBFS_HCTSIZ_XFRSIZ_POS (0U) +#define USBFS_HCTSIZ_XFRSIZ (0x0007FFFFUL) +#define USBFS_HCTSIZ_PKTCNT_POS (19U) +#define USBFS_HCTSIZ_PKTCNT (0x1FF80000UL) +#define USBFS_HCTSIZ_DPID_POS (29U) +#define USBFS_HCTSIZ_DPID (0x60000000UL) + +/* Bit definition for USBFS_HCDMA register */ +#define USBFS_HCDMA (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DCFG register */ +#define USBFS_DCFG_DSPD_POS (0U) +#define USBFS_DCFG_DSPD (0x00000003UL) +#define USBFS_DCFG_NZLSOHSK_POS (2U) +#define USBFS_DCFG_NZLSOHSK (0x00000004UL) +#define USBFS_DCFG_DAD_POS (4U) +#define USBFS_DCFG_DAD (0x000007F0UL) +#define USBFS_DCFG_PFIVL_POS (11U) +#define USBFS_DCFG_PFIVL (0x00001800UL) + +/* Bit definition for USBFS_DCTL register */ +#define USBFS_DCTL_RWUSIG_POS (0U) +#define USBFS_DCTL_RWUSIG (0x00000001UL) +#define USBFS_DCTL_SDIS_POS (1U) +#define USBFS_DCTL_SDIS (0x00000002UL) +#define USBFS_DCTL_GINSTS_POS (2U) +#define USBFS_DCTL_GINSTS (0x00000004UL) +#define USBFS_DCTL_GONSTS_POS (3U) +#define USBFS_DCTL_GONSTS (0x00000008UL) +#define USBFS_DCTL_SGINAK_POS (7U) +#define USBFS_DCTL_SGINAK (0x00000080UL) +#define USBFS_DCTL_CGINAK_POS (8U) +#define USBFS_DCTL_CGINAK (0x00000100UL) +#define USBFS_DCTL_SGONAK_POS (9U) +#define USBFS_DCTL_SGONAK (0x00000200UL) +#define USBFS_DCTL_CGONAK_POS (10U) +#define USBFS_DCTL_CGONAK (0x00000400UL) +#define USBFS_DCTL_POPRGDNE_POS (11U) +#define USBFS_DCTL_POPRGDNE (0x00000800UL) + +/* Bit definition for USBFS_DSTS register */ +#define USBFS_DSTS_SUSPSTS_POS (0U) +#define USBFS_DSTS_SUSPSTS (0x00000001UL) +#define USBFS_DSTS_ENUMSPD_POS (1U) +#define USBFS_DSTS_ENUMSPD (0x00000006UL) +#define USBFS_DSTS_EERR_POS (3U) +#define USBFS_DSTS_EERR (0x00000008UL) +#define USBFS_DSTS_FNSOF_POS (8U) +#define USBFS_DSTS_FNSOF (0x003FFF00UL) + +/* Bit definition for USBFS_DIEPMSK register */ +#define USBFS_DIEPMSK_XFRCM_POS (0U) +#define USBFS_DIEPMSK_XFRCM (0x00000001UL) +#define USBFS_DIEPMSK_EPDM_POS (1U) +#define USBFS_DIEPMSK_EPDM (0x00000002UL) +#define USBFS_DIEPMSK_TOM_POS (3U) +#define USBFS_DIEPMSK_TOM (0x00000008UL) +#define USBFS_DIEPMSK_TTXFEMSK_POS (4U) +#define USBFS_DIEPMSK_TTXFEMSK (0x00000010UL) +#define USBFS_DIEPMSK_INEPNMM_POS (5U) +#define USBFS_DIEPMSK_INEPNMM (0x00000020UL) +#define USBFS_DIEPMSK_INEPNEM_POS (6U) +#define USBFS_DIEPMSK_INEPNEM (0x00000040UL) + +/* Bit definition for USBFS_DOEPMSK register */ +#define USBFS_DOEPMSK_XFRCM_POS (0U) +#define USBFS_DOEPMSK_XFRCM (0x00000001UL) +#define USBFS_DOEPMSK_EPDM_POS (1U) +#define USBFS_DOEPMSK_EPDM (0x00000002UL) +#define USBFS_DOEPMSK_STUPM_POS (3U) +#define USBFS_DOEPMSK_STUPM (0x00000008UL) +#define USBFS_DOEPMSK_OTEPDM_POS (4U) +#define USBFS_DOEPMSK_OTEPDM (0x00000010UL) + +/* Bit definition for USBFS_DAINT register */ +#define USBFS_DAINT_IEPINT_POS (0U) +#define USBFS_DAINT_IEPINT (0x0000003FUL) +#define USBFS_DAINT_OEPINT_POS (16U) +#define USBFS_DAINT_OEPINT (0x003F0000UL) + +/* Bit definition for USBFS_DAINTMSK register */ +#define USBFS_DAINTMSK_IEPINTM_POS (0U) +#define USBFS_DAINTMSK_IEPINTM (0x0000003FUL) +#define USBFS_DAINTMSK_OEPINTM_POS (16U) +#define USBFS_DAINTMSK_OEPINTM (0x003F0000UL) + +/* Bit definition for USBFS_DIEPEMPMSK register */ +#define USBFS_DIEPEMPMSK_INEPTXFEM (0x0000003FUL) + +/* Bit definition for USBFS_DIEPCTL0 register */ +#define USBFS_DIEPCTL0_MPSIZ_POS (0U) +#define USBFS_DIEPCTL0_MPSIZ (0x00000003UL) +#define USBFS_DIEPCTL0_USBAEP_POS (15U) +#define USBFS_DIEPCTL0_USBAEP (0x00008000UL) +#define USBFS_DIEPCTL0_NAKSTS_POS (17U) +#define USBFS_DIEPCTL0_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL0_EPTYP_POS (18U) +#define USBFS_DIEPCTL0_EPTYP (0x000C0000UL) +#define USBFS_DIEPCTL0_STALL_POS (21U) +#define USBFS_DIEPCTL0_STALL (0x00200000UL) +#define USBFS_DIEPCTL0_TXFNUM_POS (22U) +#define USBFS_DIEPCTL0_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL0_CNAK_POS (26U) +#define USBFS_DIEPCTL0_CNAK (0x04000000UL) +#define USBFS_DIEPCTL0_SNAK_POS (27U) +#define USBFS_DIEPCTL0_SNAK (0x08000000UL) +#define USBFS_DIEPCTL0_EPDIS_POS (30U) +#define USBFS_DIEPCTL0_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL0_EPENA_POS (31U) +#define USBFS_DIEPCTL0_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPINT register */ +#define USBFS_DIEPINT_XFRC_POS (0U) +#define USBFS_DIEPINT_XFRC (0x00000001UL) +#define USBFS_DIEPINT_EPDISD_POS (1U) +#define USBFS_DIEPINT_EPDISD (0x00000002UL) +#define USBFS_DIEPINT_TOC_POS (3U) +#define USBFS_DIEPINT_TOC (0x00000008UL) +#define USBFS_DIEPINT_TTXFE_POS (4U) +#define USBFS_DIEPINT_TTXFE (0x00000010UL) +#define USBFS_DIEPINT_INEPNE_POS (6U) +#define USBFS_DIEPINT_INEPNE (0x00000040UL) +#define USBFS_DIEPINT_TXFE_POS (7U) +#define USBFS_DIEPINT_TXFE (0x00000080UL) + +/* Bit definition for USBFS_DIEPTSIZ0 register */ +#define USBFS_DIEPTSIZ0_XFRSIZ_POS (0U) +#define USBFS_DIEPTSIZ0_XFRSIZ (0x0000007FUL) +#define USBFS_DIEPTSIZ0_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ0_PKTCNT (0x00180000UL) + +/* Bit definition for USBFS_DIEPDMA register */ +#define USBFS_DIEPDMA (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DTXFSTS register */ +#define USBFS_DTXFSTS_INEPTFSAV (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL register */ +#define USBFS_DIEPCTL_MPSIZ_POS (0U) +#define USBFS_DIEPCTL_MPSIZ (0x000007FFUL) +#define USBFS_DIEPCTL_USBAEP_POS (15U) +#define USBFS_DIEPCTL_USBAEP (0x00008000UL) +#define USBFS_DIEPCTL_EONUM_DPID_POS (16U) +#define USBFS_DIEPCTL_EONUM_DPID (0x00010000UL) +#define USBFS_DIEPCTL_NAKSTS_POS (17U) +#define USBFS_DIEPCTL_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL_EPTYP_POS (18U) +#define USBFS_DIEPCTL_EPTYP (0x000C0000UL) +#define USBFS_DIEPCTL_STALL_POS (21U) +#define USBFS_DIEPCTL_STALL (0x00200000UL) +#define USBFS_DIEPCTL_TXFNUM_POS (22U) +#define USBFS_DIEPCTL_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL_CNAK_POS (26U) +#define USBFS_DIEPCTL_CNAK (0x04000000UL) +#define USBFS_DIEPCTL_SNAK_POS (27U) +#define USBFS_DIEPCTL_SNAK (0x08000000UL) +#define USBFS_DIEPCTL_SD0PID_SEVNFRM_POS (28U) +#define USBFS_DIEPCTL_SD0PID_SEVNFRM (0x10000000UL) +#define USBFS_DIEPCTL_SODDFRM_POS (29U) +#define USBFS_DIEPCTL_SODDFRM (0x20000000UL) +#define USBFS_DIEPCTL_EPDIS_POS (30U) +#define USBFS_DIEPCTL_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL_EPENA_POS (31U) +#define USBFS_DIEPCTL_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPTSIZ register */ +#define USBFS_DIEPTSIZ_XFRSIZ_POS (0U) +#define USBFS_DIEPTSIZ_XFRSIZ (0x0007FFFFUL) +#define USBFS_DIEPTSIZ_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ_PKTCNT (0x1FF80000UL) + +/* Bit definition for USBFS_DOEPCTL0 register */ +#define USBFS_DOEPCTL0_MPSIZ_POS (0U) +#define USBFS_DOEPCTL0_MPSIZ (0x00000003UL) +#define USBFS_DOEPCTL0_USBAEP_POS (15U) +#define USBFS_DOEPCTL0_USBAEP (0x00008000UL) +#define USBFS_DOEPCTL0_NAKSTS_POS (17U) +#define USBFS_DOEPCTL0_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL0_EPTYP_POS (18U) +#define USBFS_DOEPCTL0_EPTYP (0x000C0000UL) +#define USBFS_DOEPCTL0_SNPM_POS (20U) +#define USBFS_DOEPCTL0_SNPM (0x00100000UL) +#define USBFS_DOEPCTL0_STALL_POS (21U) +#define USBFS_DOEPCTL0_STALL (0x00200000UL) +#define USBFS_DOEPCTL0_CNAK_POS (26U) +#define USBFS_DOEPCTL0_CNAK (0x04000000UL) +#define USBFS_DOEPCTL0_SNAK_POS (27U) +#define USBFS_DOEPCTL0_SNAK (0x08000000UL) +#define USBFS_DOEPCTL0_EPDIS_POS (30U) +#define USBFS_DOEPCTL0_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL0_EPENA_POS (31U) +#define USBFS_DOEPCTL0_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPINT register */ +#define USBFS_DOEPINT_XFRC_POS (0U) +#define USBFS_DOEPINT_XFRC (0x00000001UL) +#define USBFS_DOEPINT_EPDISD_POS (1U) +#define USBFS_DOEPINT_EPDISD (0x00000002UL) +#define USBFS_DOEPINT_STUP_POS (3U) +#define USBFS_DOEPINT_STUP (0x00000008UL) +#define USBFS_DOEPINT_OTEPDIS_POS (4U) +#define USBFS_DOEPINT_OTEPDIS (0x00000010UL) +#define USBFS_DOEPINT_B2BSTUP_POS (6U) +#define USBFS_DOEPINT_B2BSTUP (0x00000040UL) + +/* Bit definition for USBFS_DOEPTSIZ0 register */ +#define USBFS_DOEPTSIZ0_XFRSIZ_POS (0U) +#define USBFS_DOEPTSIZ0_XFRSIZ (0x0000007FUL) +#define USBFS_DOEPTSIZ0_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ0_PKTCNT (0x00080000UL) +#define USBFS_DOEPTSIZ0_STUPCNT_POS (29U) +#define USBFS_DOEPTSIZ0_STUPCNT (0x60000000UL) + +/* Bit definition for USBFS_DOEPDMA register */ +#define USBFS_DOEPDMA (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DOEPCTL register */ +#define USBFS_DOEPCTL_MPSIZ_POS (0U) +#define USBFS_DOEPCTL_MPSIZ (0x000007FFUL) +#define USBFS_DOEPCTL_USBAEP_POS (15U) +#define USBFS_DOEPCTL_USBAEP (0x00008000UL) +#define USBFS_DOEPCTL_DPID_POS (16U) +#define USBFS_DOEPCTL_DPID (0x00010000UL) +#define USBFS_DOEPCTL_NAKSTS_POS (17U) +#define USBFS_DOEPCTL_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL_EPTYP_POS (18U) +#define USBFS_DOEPCTL_EPTYP (0x000C0000UL) +#define USBFS_DOEPCTL_SNPM_POS (20U) +#define USBFS_DOEPCTL_SNPM (0x00100000UL) +#define USBFS_DOEPCTL_STALL_POS (21U) +#define USBFS_DOEPCTL_STALL (0x00200000UL) +#define USBFS_DOEPCTL_CNAK_POS (26U) +#define USBFS_DOEPCTL_CNAK (0x04000000UL) +#define USBFS_DOEPCTL_SNAK_POS (27U) +#define USBFS_DOEPCTL_SNAK (0x08000000UL) +#define USBFS_DOEPCTL_SD0PID_POS (28U) +#define USBFS_DOEPCTL_SD0PID (0x10000000UL) +#define USBFS_DOEPCTL_SD1PID_POS (29U) +#define USBFS_DOEPCTL_SD1PID (0x20000000UL) +#define USBFS_DOEPCTL_EPDIS_POS (30U) +#define USBFS_DOEPCTL_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL_EPENA_POS (31U) +#define USBFS_DOEPCTL_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPTSIZ register */ +#define USBFS_DOEPTSIZ_XFRSIZ_POS (0U) +#define USBFS_DOEPTSIZ_XFRSIZ (0x0007FFFFUL) +#define USBFS_DOEPTSIZ_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ_PKTCNT (0x1FF80000UL) + +/* Bit definition for USBFS_GCCTL register */ +#define USBFS_GCCTL_STPPCLK_POS (0U) +#define USBFS_GCCTL_STPPCLK (0x00000001UL) +#define USBFS_GCCTL_GATEHCLK_POS (1U) +#define USBFS_GCCTL_GATEHCLK (0x00000002UL) + +/******************************************************************************* + Bit definition for Peripheral WDT +*******************************************************************************/ +/* Bit definition for WDT_CR register */ +#define WDT_CR_PERI_POS (0U) +#define WDT_CR_PERI (0x00000003UL) +#define WDT_CR_PERI_0 (0x00000001UL) +#define WDT_CR_PERI_1 (0x00000002UL) +#define WDT_CR_CKS_POS (4U) +#define WDT_CR_CKS (0x000000F0UL) +#define WDT_CR_WDPT_POS (8U) +#define WDT_CR_WDPT (0x00000F00UL) +#define WDT_CR_SLPOFF_POS (16U) +#define WDT_CR_SLPOFF (0x00010000UL) +#define WDT_CR_ITS_POS (31U) +#define WDT_CR_ITS (0x80000000UL) + +/* Bit definition for WDT_SR register */ +#define WDT_SR_CNT_POS (0U) +#define WDT_SR_CNT (0x0000FFFFUL) +#define WDT_SR_UDF_POS (16U) +#define WDT_SR_UDF (0x00010000UL) +#define WDT_SR_REF_POS (17U) +#define WDT_SR_REF (0x00020000UL) + +/* Bit definition for WDT_RR register */ +#define WDT_RR_RF (0x0000FFFFUL) + +/******************************************************************************/ +/* Device Specific Registers bit_band structure */ +/******************************************************************************/ + +typedef struct { + __IO uint32_t STRT; + uint32_t RESERVED0[7]; +} stc_adc_str_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t CLREN; + __IO uint32_t DFMT; + uint32_t RESERVED1[8]; +} stc_adc_cr0_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t RSCHSEL; + uint32_t RESERVED1[13]; +} stc_adc_cr1_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t TRGENA; + uint32_t RESERVED1[7]; + __IO uint32_t TRGENB; +} stc_adc_trgsr_bit_t; + +typedef struct { + __IO uint32_t EOCAF; + __IO uint32_t EOCBF; + uint32_t RESERVED0[6]; +} stc_adc_isr_bit_t; + +typedef struct { + __IO uint32_t EOCAIEN; + __IO uint32_t EOCBIEN; + uint32_t RESERVED0[6]; +} stc_adc_icr_bit_t; + +typedef struct { + __IO uint32_t SYNCEN; + uint32_t RESERVED0[15]; +} stc_adc_synccr_bit_t; + +typedef struct { + __IO uint32_t AWDEN; + uint32_t RESERVED0[3]; + __IO uint32_t AWDMD; + uint32_t RESERVED1[3]; + __IO uint32_t AWDIEN; + uint32_t RESERVED2[7]; +} stc_adc_awdcr_bit_t; + +typedef struct { + __IO uint32_t PGAVSSEN; + uint32_t RESERVED0[15]; +} stc_adc_pgainsr1_bit_t; + +typedef struct { + __IO uint32_t START; + __IO uint32_t MODE; + uint32_t RESERVED0[30]; +} stc_aes_cr_bit_t; + +typedef struct { + __O uint32_t STRG; + uint32_t RESERVED0[31]; +} stc_aos_intsfttrg_bit_t; + +typedef struct { + __IO uint32_t NFEN1; + uint32_t RESERVED0[7]; + __IO uint32_t NFEN2; + uint32_t RESERVED1[7]; + __IO uint32_t NFEN3; + uint32_t RESERVED2[7]; + __IO uint32_t NFEN4; + uint32_t RESERVED3[7]; +} stc_aos_pevntnfcr_bit_t; + +typedef struct { + __IO uint32_t BUSOFF; + __I uint32_t TACTIVE; + __I uint32_t RACTIVE; + __IO uint32_t TSSS; + __IO uint32_t TPSS; + __IO uint32_t LBMI; + __IO uint32_t LBME; + __IO uint32_t RESET; +} stc_can_cfg_stat_bit_t; + +typedef struct { + __IO uint32_t TSA; + __IO uint32_t TSALL; + __IO uint32_t TSONE; + __IO uint32_t TPA; + __IO uint32_t TPE; + uint32_t RESERVED0[1]; + __IO uint32_t LOM; + __IO uint32_t TBSEL; +} stc_can_tcmd_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t TTTBM; + __IO uint32_t TSMODE; + __IO uint32_t TSNEXT; + uint32_t RESERVED1[1]; +} stc_can_tctrl_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t RBALL; + __IO uint32_t RREL; + __I uint32_t ROV; + __IO uint32_t ROM; + __IO uint32_t SACK; +} stc_can_rctrl_bit_t; + +typedef struct { + __I uint32_t TSFF; + __IO uint32_t EIE; + __IO uint32_t TSIE; + __IO uint32_t TPIE; + __IO uint32_t RAFIE; + __IO uint32_t RFIE; + __IO uint32_t ROIE; + __IO uint32_t RIE; +} stc_can_rtie_bit_t; + +typedef struct { + __IO uint32_t AIF; + __IO uint32_t EIF; + __IO uint32_t TSIF; + __IO uint32_t TPIF; + __IO uint32_t RAFIF; + __IO uint32_t RFIF; + __IO uint32_t ROIF; + __IO uint32_t RIF; +} stc_can_rtif_bit_t; + +typedef struct { + __IO uint32_t BEIF; + __IO uint32_t BEIE; + __IO uint32_t ALIF; + __IO uint32_t ALIE; + __IO uint32_t EPIF; + __IO uint32_t EPIE; + __I uint32_t EPASS; + __I uint32_t EWARN; +} stc_can_errint_bit_t; + +typedef struct { + uint32_t RESERVED0[5]; + __IO uint32_t SELMASK; + uint32_t RESERVED1[2]; +} stc_can_acfctrl_bit_t; + +typedef struct { + __IO uint32_t AE_1; + __IO uint32_t AE_2; + __IO uint32_t AE_3; + __IO uint32_t AE_4; + __IO uint32_t AE_5; + __IO uint32_t AE_6; + __IO uint32_t AE_7; + __IO uint32_t AE_8; +} stc_can_acfen_bit_t; + +typedef struct { + uint32_t RESERVED0[29]; + __IO uint32_t AIDE; + __IO uint32_t AIDEE; + uint32_t RESERVED1[1]; +} stc_can_acf_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t TBF; + __IO uint32_t TBE; +} stc_can_tbslot_bit_t; + +typedef struct { + __IO uint32_t TTEN; + uint32_t RESERVED0[2]; + __IO uint32_t TTIF; + __IO uint32_t TTIE; + __IO uint32_t TEIF; + __IO uint32_t WTIF; + __IO uint32_t WTIE; +} stc_can_ttcfg_bit_t; + +typedef struct { + uint32_t RESERVED0[31]; + __IO uint32_t REF_IDE; +} stc_can_ref_msg_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t IEN; + __IO uint32_t CVSEN; + uint32_t RESERVED1[3]; + __IO uint32_t OUTEN; + __IO uint32_t INV; + __IO uint32_t CMPOE; + __IO uint32_t CMPON; +} stc_cmp_ctrl_bit_t; + +typedef struct { + __IO uint32_t RVSL0; + __IO uint32_t RVSL1; + __IO uint32_t RVSL2; + __IO uint32_t RVSL3; + uint32_t RESERVED0[4]; + __IO uint32_t CVSL0; + __IO uint32_t CVSL1; + __IO uint32_t CVSL2; + __IO uint32_t CVSL3; + __IO uint32_t C4SL0; + __IO uint32_t C4SL1; + __IO uint32_t C4SL2; + uint32_t RESERVED1[1]; +} stc_cmp_vltsel_bit_t; + +typedef struct { + __I uint32_t OMON; + uint32_t RESERVED0[15]; +} stc_cmp_outmon_bit_t; + +typedef struct { + __IO uint32_t DA1EN; + __IO uint32_t DA2EN; + uint32_t RESERVED0[14]; +} stc_cmp_common_dacr_bit_t; + +typedef struct { + __IO uint32_t DA1SW; + __IO uint32_t DA2SW; + uint32_t RESERVED0[2]; + __IO uint32_t VREFSW; + uint32_t RESERVED1[11]; +} stc_cmp_common_rvadc_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t CR; + __IO uint32_t REFIN; + __IO uint32_t REFOUT; + __IO uint32_t XOROUT; + uint32_t RESERVED1[27]; +} stc_crc_cr_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __I uint32_t CRCFLAG_16; + uint32_t RESERVED1[15]; +} stc_crc_reslt_bit_t; + +typedef struct { + __I uint32_t CRCFLAG_32; + uint32_t RESERVED0[31]; +} stc_crc_flg_bit_t; + +typedef struct { + __IO uint32_t CDBGPWRUPREQ; + __IO uint32_t CDBGPWRUPACK; + uint32_t RESERVED0[30]; +} stc_dbgc_mcudbgstat_bit_t; + +typedef struct { + __IO uint32_t SWDTSTP; + __IO uint32_t WDTSTP; + __IO uint32_t RTCSTP; + uint32_t RESERVED0[11]; + __IO uint32_t TMR01STP; + __IO uint32_t TMR02STP; + uint32_t RESERVED1[4]; + __IO uint32_t TMR41STP; + __IO uint32_t TMR42STP; + __IO uint32_t TMR43STP; + __IO uint32_t TM61STP; + __IO uint32_t TM62STP; + __IO uint32_t TMR63STP; + __IO uint32_t TMRA1STP; + __IO uint32_t TMRA2STP; + __IO uint32_t TMRA3STP; + __IO uint32_t TMRA4STP; + __IO uint32_t TMRA5STP; + __IO uint32_t TMRA6STP; +} stc_dbgc_mcustpctl_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t TRACEIOEN; + uint32_t RESERVED1[29]; +} stc_dbgc_mcutracectl_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t COMPTRG; + uint32_t RESERVED1[22]; + __IO uint32_t INTEN; +} stc_dcu_ctl_bit_t; + +typedef struct { + __O uint32_t FLAG_OP; + __O uint32_t FLAG_LS2; + __O uint32_t FLAG_EQ2; + __O uint32_t FLAG_GT2; + __O uint32_t FLAG_LS1; + __O uint32_t FLAG_EQ1; + __O uint32_t FLAG_GT1; + uint32_t RESERVED0[25]; +} stc_dcu_flag_bit_t; + +typedef struct { + __O uint32_t CLR_OP; + __O uint32_t CLR_LS2; + __O uint32_t CLR_EQ2; + __O uint32_t CLR_GT2; + __O uint32_t CLR_LS1; + __O uint32_t CLR_EQ1; + __O uint32_t CLR_GT1; + uint32_t RESERVED0[25]; +} stc_dcu_flagclr_bit_t; + +typedef struct { + __IO uint32_t SEL_OP; + __IO uint32_t SEL_LS2; + __IO uint32_t SEL_EQ2; + __IO uint32_t SEL_GT2; + __IO uint32_t SEL_LS1; + __IO uint32_t SEL_EQ1; + __IO uint32_t SEL_GT1; + uint32_t RESERVED0[25]; +} stc_dcu_intevtsel_bit_t; + +typedef struct { + __IO uint32_t EN; + uint32_t RESERVED0[31]; +} stc_dma_en_bit_t; + +typedef struct { + __I uint32_t TRNERR0; + __I uint32_t TRNERR1; + __I uint32_t TRNERR2; + __I uint32_t TRNERR3; + uint32_t RESERVED0[12]; + __I uint32_t REQERR0; + __I uint32_t REQERR1; + __I uint32_t REQERR2; + __I uint32_t REQERR3; + uint32_t RESERVED1[12]; +} stc_dma_intstat0_bit_t; + +typedef struct { + __I uint32_t TC0; + __I uint32_t TC1; + __I uint32_t TC2; + __I uint32_t TC3; + uint32_t RESERVED0[12]; + __I uint32_t BTC0; + __I uint32_t BTC1; + __I uint32_t BTC2; + __I uint32_t BTC3; + uint32_t RESERVED1[12]; +} stc_dma_intstat1_bit_t; + +typedef struct { + __IO uint32_t MSKTRNERR0; + __IO uint32_t MSKTRNERR1; + __IO uint32_t MSKTRNERR2; + __IO uint32_t MSKTRNERR3; + uint32_t RESERVED0[12]; + __IO uint32_t MSKREQERR0; + __IO uint32_t MSKREQERR1; + __IO uint32_t MSKREQERR2; + __IO uint32_t MSKREQERR3; + uint32_t RESERVED1[12]; +} stc_dma_intmask0_bit_t; + +typedef struct { + __IO uint32_t MSKTC0; + __IO uint32_t MSKTC1; + __IO uint32_t MSKTC2; + __IO uint32_t MSKTC3; + uint32_t RESERVED0[12]; + __IO uint32_t MSKBTC0; + __IO uint32_t MSKBTC1; + __IO uint32_t MSKBTC2; + __IO uint32_t MSKBTC3; + uint32_t RESERVED1[12]; +} stc_dma_intmask1_bit_t; + +typedef struct { + __O uint32_t CLRTRNERR0; + __O uint32_t CLRTRNERR1; + __O uint32_t CLRTRNERR2; + __O uint32_t CLRTRNERR3; + uint32_t RESERVED0[12]; + __O uint32_t CLRREQERR0; + __O uint32_t CLRREQERR1; + __O uint32_t CLRREQERR2; + __O uint32_t CLRREQERR3; + uint32_t RESERVED1[12]; +} stc_dma_intclr0_bit_t; + +typedef struct { + __O uint32_t CLRTC0; + __O uint32_t CLRTC1; + __O uint32_t CLRTC2; + __O uint32_t CLRTC3; + uint32_t RESERVED0[12]; + __O uint32_t CLRBTC0; + __O uint32_t CLRBTC1; + __O uint32_t CLRBTC2; + __O uint32_t CLRBTC3; + uint32_t RESERVED1[12]; +} stc_dma_intclr1_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __I uint32_t RCFGREQ; + uint32_t RESERVED1[16]; +} stc_dma_reqstat_bit_t; + +typedef struct { + __I uint32_t DMAACT; + __I uint32_t RCFGACT; + uint32_t RESERVED0[30]; +} stc_dma_chstat_bit_t; + +typedef struct { + __IO uint32_t RCFGEN; + __IO uint32_t RCFGLLP; + uint32_t RESERVED0[30]; +} stc_dma_rcfgctl_bit_t; + +typedef struct { + __O uint32_t SWREQ0; + __O uint32_t SWREQ1; + __O uint32_t SWREQ2; + __O uint32_t SWREQ3; + __O uint32_t SWREQ4; + __O uint32_t SWREQ5; + __O uint32_t SWREQ6; + __O uint32_t SWREQ7; + uint32_t RESERVED0[7]; + __O uint32_t SWRCFGREQ; + uint32_t RESERVED1[16]; +} stc_dma_swreq_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t SRPTEN; + __IO uint32_t DRPTEN; + __IO uint32_t SNSEQEN; + __IO uint32_t DNSEQEN; + uint32_t RESERVED1[2]; + __IO uint32_t LLPEN; + __IO uint32_t LLPRUN; + __IO uint32_t IE; + uint32_t RESERVED2[19]; +} stc_dma_chctl_bit_t; + +typedef struct { + __IO uint32_t FSTP; + uint32_t RESERVED0[31]; +} stc_efm_fstp_bit_t; + +typedef struct { + __IO uint32_t SLPMD; + uint32_t RESERVED0[7]; + __IO uint32_t LVM; + uint32_t RESERVED1[7]; + __IO uint32_t CACHE; + uint32_t RESERVED2[7]; + __IO uint32_t CRST; + uint32_t RESERVED3[7]; +} stc_efm_frmc_bit_t; + +typedef struct { + __IO uint32_t PEMODE; + uint32_t RESERVED0[7]; + __IO uint32_t BUSHLDCTL; + uint32_t RESERVED1[23]; +} stc_efm_fwmc_bit_t; + +typedef struct { + __I uint32_t PEWERR; + __I uint32_t PEPRTERR; + __I uint32_t PGSZERR; + __I uint32_t PGMISMTCH; + __I uint32_t OPTEND; + __I uint32_t COLERR; + uint32_t RESERVED0[2]; + __I uint32_t RDY; + uint32_t RESERVED1[23]; +} stc_efm_fsr_bit_t; + +typedef struct { + __IO uint32_t PEWERRCLR; + __IO uint32_t PEPRTERRCLR; + __IO uint32_t PGSZERRCLR; + __IO uint32_t PGMISMTCHCLR; + __IO uint32_t OPTENDCLR; + __IO uint32_t COLERRCLR; + uint32_t RESERVED0[26]; +} stc_efm_fsclr_bit_t; + +typedef struct { + __IO uint32_t PEERRITE; + __IO uint32_t OPTENDITE; + __IO uint32_t COLERRITE; + uint32_t RESERVED0[29]; +} stc_efm_fite_bit_t; + +typedef struct { + __I uint32_t FSWP; + uint32_t RESERVED0[31]; +} stc_efm_fswp_bit_t; + +typedef struct { + uint32_t RESERVED0[31]; + __IO uint32_t EN; +} stc_efm_mmf_remcr_bit_t; + +typedef struct { + __IO uint32_t PORTINEN; + __IO uint32_t CMPEN1; + __IO uint32_t CMPEN2; + __IO uint32_t CMPEN3; + uint32_t RESERVED0[1]; + __IO uint32_t OSCSTPEN; + __IO uint32_t PWMSEN0; + __IO uint32_t PWMSEN1; + __IO uint32_t PWMSEN2; + uint32_t RESERVED1[21]; + __IO uint32_t NFEN; + __IO uint32_t INVSEL; +} stc_emb_ctl_bit_t; + +typedef struct { + __IO uint32_t PWMLV0; + __IO uint32_t PWMLV1; + __IO uint32_t PWMLV2; + uint32_t RESERVED0[29]; +} stc_emb_pwmlv_bit_t; + +typedef struct { + __IO uint32_t SOE; + uint32_t RESERVED0[31]; +} stc_emb_soe_bit_t; + +typedef struct { + __I uint32_t PORTINF; + __I uint32_t PWMSF; + __I uint32_t CMPF; + __I uint32_t OSF; + __I uint32_t PORTINST; + __I uint32_t PWMST; + uint32_t RESERVED0[26]; +} stc_emb_stat_bit_t; + +typedef struct { + __O uint32_t PORTINFCLR; + __O uint32_t PWMSFCLR; + __O uint32_t CMPFCLR; + __O uint32_t OSFCLR; + uint32_t RESERVED0[28]; +} stc_emb_statclr_bit_t; + +typedef struct { + __IO uint32_t PORTININTEN; + __IO uint32_t PWMSINTEN; + __IO uint32_t CMPINTEN; + __IO uint32_t OSINTEN; + uint32_t RESERVED0[28]; +} stc_emb_inten_bit_t; + +typedef struct { + __IO uint32_t START; + uint32_t RESERVED0[31]; +} stc_fcm_str_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t INEXS; + uint32_t RESERVED1[7]; + __IO uint32_t EXREFE; + uint32_t RESERVED2[16]; +} stc_fcm_rccr_bit_t; + +typedef struct { + __IO uint32_t ERRIE; + __IO uint32_t MENDIE; + __IO uint32_t OVFIE; + uint32_t RESERVED0[1]; + __IO uint32_t ERRINTRS; + uint32_t RESERVED1[2]; + __IO uint32_t ERRE; + uint32_t RESERVED2[24]; +} stc_fcm_rier_bit_t; + +typedef struct { + __I uint32_t ERRF; + __I uint32_t MENDF; + __I uint32_t OVF; + uint32_t RESERVED0[29]; +} stc_fcm_sr_bit_t; + +typedef struct { + __O uint32_t ERRFCLR; + __O uint32_t MENDFCLR; + __O uint32_t OVFCLR; + uint32_t RESERVED0[29]; +} stc_fcm_clr_bit_t; + +typedef struct { + __I uint32_t PIN00; + __I uint32_t PIN01; + __I uint32_t PIN02; + __I uint32_t PIN03; + __I uint32_t PIN04; + __I uint32_t PIN05; + __I uint32_t PIN06; + __I uint32_t PIN07; + __I uint32_t PIN08; + __I uint32_t PIN09; + __I uint32_t PIN10; + __I uint32_t PIN11; + __I uint32_t PIN12; + __I uint32_t PIN13; + __I uint32_t PIN14; + __I uint32_t PIN15; +} stc_gpio_pidr_bit_t; + +typedef struct { + __IO uint32_t POUT00; + __IO uint32_t POUT01; + __IO uint32_t POUT02; + __IO uint32_t POUT03; + __IO uint32_t POUT04; + __IO uint32_t POUT05; + __IO uint32_t POUT06; + __IO uint32_t POUT07; + __IO uint32_t POUT08; + __IO uint32_t POUT09; + __IO uint32_t POUT10; + __IO uint32_t POUT11; + __IO uint32_t POUT12; + __IO uint32_t POUT13; + __IO uint32_t POUT14; + __IO uint32_t POUT15; +} stc_gpio_podr_bit_t; + +typedef struct { + __IO uint32_t POUTE00; + __IO uint32_t POUTE01; + __IO uint32_t POUTE02; + __IO uint32_t POUTE03; + __IO uint32_t POUTE04; + __IO uint32_t POUTE05; + __IO uint32_t POUTE06; + __IO uint32_t POUTE07; + __IO uint32_t POUTE08; + __IO uint32_t POUTE09; + __IO uint32_t POUTE10; + __IO uint32_t POUTE11; + __IO uint32_t POUTE12; + __IO uint32_t POUTE13; + __IO uint32_t POUTE14; + __IO uint32_t POUTE15; +} stc_gpio_poer_bit_t; + +typedef struct { + __IO uint32_t POS00; + __IO uint32_t POS01; + __IO uint32_t POS02; + __IO uint32_t POS03; + __IO uint32_t POS04; + __IO uint32_t POS05; + __IO uint32_t POS06; + __IO uint32_t POS07; + __IO uint32_t POS08; + __IO uint32_t POS09; + __IO uint32_t POS10; + __IO uint32_t POS11; + __IO uint32_t POS12; + __IO uint32_t POS13; + __IO uint32_t POS14; + __IO uint32_t POS15; +} stc_gpio_posr_bit_t; + +typedef struct { + __IO uint32_t POR00; + __IO uint32_t POR01; + __IO uint32_t POR02; + __IO uint32_t POR03; + __IO uint32_t POR04; + __IO uint32_t POR05; + __IO uint32_t POR06; + __IO uint32_t POR07; + __IO uint32_t POR08; + __IO uint32_t POR09; + __IO uint32_t POR10; + __IO uint32_t POR11; + __IO uint32_t POR12; + __IO uint32_t POR13; + __IO uint32_t POR14; + __IO uint32_t POR15; +} stc_gpio_porr_bit_t; + +typedef struct { + __IO uint32_t POT00; + __IO uint32_t POT01; + __IO uint32_t POT02; + __IO uint32_t POT03; + __IO uint32_t POT04; + __IO uint32_t POT05; + __IO uint32_t POT06; + __IO uint32_t POT07; + __IO uint32_t POT08; + __IO uint32_t POT09; + __IO uint32_t POT10; + __IO uint32_t POT11; + __IO uint32_t POT12; + __IO uint32_t POT13; + __IO uint32_t POT14; + __IO uint32_t POT15; +} stc_gpio_potr_bit_t; + +typedef struct { + __I uint32_t PIN00; + __I uint32_t PIN01; + __I uint32_t PIN02; + uint32_t RESERVED0[13]; +} stc_gpio_pidrh_bit_t; + +typedef struct { + __IO uint32_t POUT00; + __IO uint32_t POUT01; + __IO uint32_t POUT02; + uint32_t RESERVED0[13]; +} stc_gpio_podrh_bit_t; + +typedef struct { + __IO uint32_t POUTE00; + __IO uint32_t POUTE01; + __IO uint32_t POUTE02; + uint32_t RESERVED0[13]; +} stc_gpio_poerh_bit_t; + +typedef struct { + __IO uint32_t POS00; + __IO uint32_t POS01; + __IO uint32_t POS02; + uint32_t RESERVED0[13]; +} stc_gpio_posrh_bit_t; + +typedef struct { + __IO uint32_t POR00; + __IO uint32_t POR01; + __IO uint32_t POR02; + uint32_t RESERVED0[13]; +} stc_gpio_porrh_bit_t; + +typedef struct { + __IO uint32_t POT00; + __IO uint32_t POT01; + __IO uint32_t POT02; + uint32_t RESERVED0[13]; +} stc_gpio_potrh_bit_t; + +typedef struct { + __IO uint32_t WE; + uint32_t RESERVED0[15]; +} stc_gpio_pwpr_bit_t; + +typedef struct { + __IO uint32_t POUT; + __IO uint32_t POUTE; + __IO uint32_t NOD; + uint32_t RESERVED0[3]; + __IO uint32_t PUU; + uint32_t RESERVED1[1]; + __I uint32_t PIN; + __IO uint32_t INVE; + uint32_t RESERVED2[2]; + __IO uint32_t INTE; + uint32_t RESERVED3[1]; + __IO uint32_t LTE; + __IO uint32_t DDIS; +} stc_gpio_pcr_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t BFE; + uint32_t RESERVED1[7]; +} stc_gpio_pfsr_bit_t; + +typedef struct { + __IO uint32_t START; + __IO uint32_t FST_GRP; + uint32_t RESERVED0[30]; +} stc_hash_cr_bit_t; + +typedef struct { + __IO uint32_t PE; + __IO uint32_t SMBUS; + __IO uint32_t SMBALRTEN; + __IO uint32_t SMBDEFAULTEN; + __IO uint32_t SMBHOSTEN; + uint32_t RESERVED0[1]; + __IO uint32_t GCEN; + __IO uint32_t RESTART; + __IO uint32_t START; + __IO uint32_t STOP; + __IO uint32_t ACK; + uint32_t RESERVED1[4]; + __IO uint32_t SWRST; + uint32_t RESERVED2[16]; +} stc_i2c_cr1_bit_t; + +typedef struct { + __IO uint32_t STARTIE; + __IO uint32_t SLADDR0IE; + __IO uint32_t SLADDR1IE; + __IO uint32_t TENDIE; + __IO uint32_t STOPIE; + uint32_t RESERVED0[1]; + __IO uint32_t RFULLIE; + __IO uint32_t TEMPTYIE; + uint32_t RESERVED1[1]; + __IO uint32_t ARLOIE; + uint32_t RESERVED2[2]; + __IO uint32_t NACKIE; + uint32_t RESERVED3[1]; + __IO uint32_t TMOUTIE; + uint32_t RESERVED4[5]; + __IO uint32_t GENCALLIE; + __IO uint32_t SMBDEFAULTIE; + __IO uint32_t SMBHOSTIE; + __IO uint32_t SMBALRTIE; + uint32_t RESERVED5[8]; +} stc_i2c_cr2_bit_t; + +typedef struct { + __IO uint32_t TMOUTEN; + __IO uint32_t LTMOUT; + __IO uint32_t HTMOUT; + uint32_t RESERVED0[4]; + __IO uint32_t FACKEN; + uint32_t RESERVED1[24]; +} stc_i2c_cr3_bit_t; + +typedef struct { + uint32_t RESERVED0[10]; + __IO uint32_t BUSWAIT; + uint32_t RESERVED1[21]; +} stc_i2c_cr4_bit_t; + +typedef struct { + uint32_t RESERVED0[12]; + __IO uint32_t SLADDR0EN; + uint32_t RESERVED1[2]; + __IO uint32_t ADDRMOD0; + uint32_t RESERVED2[16]; +} stc_i2c_slr0_bit_t; + +typedef struct { + uint32_t RESERVED0[12]; + __IO uint32_t SLADDR1EN; + uint32_t RESERVED1[2]; + __IO uint32_t ADDRMOD1; + uint32_t RESERVED2[16]; +} stc_i2c_slr1_bit_t; + +typedef struct { + __IO uint32_t STARTF; + __IO uint32_t SLADDR0F; + __IO uint32_t SLADDR1F; + __IO uint32_t TENDF; + __IO uint32_t STOPF; + uint32_t RESERVED0[1]; + __IO uint32_t RFULLF; + __IO uint32_t TEMPTYF; + uint32_t RESERVED1[1]; + __IO uint32_t ARLOF; + __IO uint32_t ACKRF; + uint32_t RESERVED2[1]; + __IO uint32_t NACKF; + uint32_t RESERVED3[1]; + __IO uint32_t TMOUTF; + uint32_t RESERVED4[1]; + __IO uint32_t MSL; + __IO uint32_t BUSY; + __IO uint32_t TRA; + uint32_t RESERVED5[1]; + __IO uint32_t GENCALLF; + __IO uint32_t SMBDEFAULTF; + __IO uint32_t SMBHOSTF; + __IO uint32_t SMBALRTF; + uint32_t RESERVED6[8]; +} stc_i2c_sr_bit_t; + +typedef struct { + __O uint32_t STARTFCLR; + __O uint32_t SLADDR0FCLR; + __O uint32_t SLADDR1FCLR; + __O uint32_t TENDFCLR; + __O uint32_t STOPFCLR; + uint32_t RESERVED0[1]; + __O uint32_t RFULLFCLR; + __O uint32_t TEMPTYFCLR; + uint32_t RESERVED1[1]; + __O uint32_t ARLOFCLR; + uint32_t RESERVED2[2]; + __O uint32_t NACKFCLR; + uint32_t RESERVED3[1]; + __O uint32_t TMOUTFCLR; + uint32_t RESERVED4[5]; + __O uint32_t GENCALLFCLR; + __O uint32_t SMBDEFAULTFCLR; + __O uint32_t SMBHOSTFCLR; + __O uint32_t SMBALRTFCLR; + uint32_t RESERVED5[8]; +} stc_i2c_clr_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t DNFEN; + __IO uint32_t ANFEN; + uint32_t RESERVED1[26]; +} stc_i2c_fltr_bit_t; + +typedef struct { + __IO uint32_t TXE; + __IO uint32_t TXIE; + __IO uint32_t RXE; + __IO uint32_t RXIE; + __IO uint32_t EIE; + __IO uint32_t WMS; + __IO uint32_t ODD; + __IO uint32_t MCKOE; + uint32_t RESERVED0[8]; + __IO uint32_t FIFOR; + uint32_t RESERVED1[1]; + __IO uint32_t I2SPLLSEL; + __IO uint32_t SDOE; + __IO uint32_t LRCKOE; + __IO uint32_t CKOE; + __IO uint32_t DUPLEX; + __IO uint32_t CLKSEL; + uint32_t RESERVED2[8]; +} stc_i2s_ctrl_bit_t; + +typedef struct { + __I uint32_t TXBA; + __I uint32_t RXBA; + __I uint32_t TXBE; + __I uint32_t TXBF; + __I uint32_t RXBE; + __I uint32_t RXBF; + uint32_t RESERVED0[26]; +} stc_i2s_sr_bit_t; + +typedef struct { + __IO uint32_t TXERR; + __IO uint32_t RXERR; + uint32_t RESERVED0[30]; +} stc_i2s_er_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t CHLEN; + __IO uint32_t PCMSYNC; + uint32_t RESERVED1[26]; +} stc_i2s_cfgr_bit_t; + +typedef struct { + __I uint32_t SWDTAUTS; + __I uint32_t SWDTITS; + uint32_t RESERVED0[10]; + __I uint32_t SWDTSLPOFF; + uint32_t RESERVED1[3]; + __I uint32_t WDTAUTS; + __I uint32_t WDTITS; + uint32_t RESERVED2[10]; + __I uint32_t WDTSLPOFF; + uint32_t RESERVED3[3]; +} stc_icg_icg0_bit_t; + +typedef struct { + __I uint32_t HRCFREQSEL; + uint32_t RESERVED0[7]; + __I uint32_t HRCSTOP; + uint32_t RESERVED1[9]; + __I uint32_t BORDIS; + uint32_t RESERVED2[9]; + __I uint32_t NMITRG; + __I uint32_t NMIEN; + __I uint32_t NFEN; + __I uint32_t NMIICGEN; +} stc_icg_icg1_bit_t; + +typedef struct { + __IO uint32_t NMITRG; + uint32_t RESERVED0[6]; + __IO uint32_t NFEN; + uint32_t RESERVED1[24]; +} stc_intc_nmicr_bit_t; + +typedef struct { + __IO uint32_t NMIENR; + __IO uint32_t SWDTENR; + __IO uint32_t PVD1ENR; + __IO uint32_t PVD2ENR; + uint32_t RESERVED0[1]; + __IO uint32_t XTALSTPENR; + uint32_t RESERVED1[2]; + __IO uint32_t REPENR; + __IO uint32_t RECCENR; + __IO uint32_t BUSMENR; + __IO uint32_t WDTENR; + uint32_t RESERVED2[20]; +} stc_intc_nmienr_bit_t; + +typedef struct { + __IO uint32_t NMIFR; + __IO uint32_t SWDTFR; + __IO uint32_t PVD1FR; + __IO uint32_t PVD2FR; + uint32_t RESERVED0[1]; + __IO uint32_t XTALSTPFR; + uint32_t RESERVED1[2]; + __IO uint32_t REPFR; + __IO uint32_t RECCFR; + __IO uint32_t BUSMFR; + __IO uint32_t WDTFR; + uint32_t RESERVED2[20]; +} stc_intc_nmifr_bit_t; + +typedef struct { + __IO uint32_t NMICFR; + __IO uint32_t SWDTCFR; + __IO uint32_t PVD1CFR; + __IO uint32_t PVD2CFR; + uint32_t RESERVED0[1]; + __IO uint32_t XTALSTPCFR; + uint32_t RESERVED1[2]; + __IO uint32_t REPCFR; + __IO uint32_t RECCCFR; + __IO uint32_t BUSMCFR; + __IO uint32_t WDTCFR; + uint32_t RESERVED2[20]; +} stc_intc_nmicfr_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t EFEN; + uint32_t RESERVED1[24]; +} stc_intc_eirqcr_bit_t; + +typedef struct { + __IO uint32_t EIRQWUEN0; + __IO uint32_t EIRQWUEN1; + __IO uint32_t EIRQWUEN2; + __IO uint32_t EIRQWUEN3; + __IO uint32_t EIRQWUEN4; + __IO uint32_t EIRQWUEN5; + __IO uint32_t EIRQWUEN6; + __IO uint32_t EIRQWUEN7; + __IO uint32_t EIRQWUEN8; + __IO uint32_t EIRQWUEN9; + __IO uint32_t EIRQWUEN10; + __IO uint32_t EIRQWUEN11; + __IO uint32_t EIRQWUEN12; + __IO uint32_t EIRQWUEN13; + __IO uint32_t EIRQWUEN14; + __IO uint32_t EIRQWUEN15; + __IO uint32_t SWDTWUEN; + __IO uint32_t PVD1WUEN; + __IO uint32_t PVD2WUEN; + __IO uint32_t CMPI0WUEN; + __IO uint32_t WKTMWUEN; + __IO uint32_t RTCALMWUEN; + __IO uint32_t RTCPRDWUEN; + __IO uint32_t TMR0WUEN; + uint32_t RESERVED0[1]; + __IO uint32_t RXWUEN; + uint32_t RESERVED1[6]; +} stc_intc_wupen_bit_t; + +typedef struct { + __IO uint32_t EIFR0; + __IO uint32_t EIFR1; + __IO uint32_t EIFR2; + __IO uint32_t EIFR3; + __IO uint32_t EIFR4; + __IO uint32_t EIFR5; + __IO uint32_t EIFR6; + __IO uint32_t EIFR7; + __IO uint32_t EIFR8; + __IO uint32_t EIFR9; + __IO uint32_t EIFR10; + __IO uint32_t EIFR11; + __IO uint32_t EIFR12; + __IO uint32_t EIFR13; + __IO uint32_t EIFR14; + __IO uint32_t EIFR15; + uint32_t RESERVED0[16]; +} stc_intc_eifr_bit_t; + +typedef struct { + __IO uint32_t EIFCR0; + __IO uint32_t EIFCR1; + __IO uint32_t EIFCR2; + __IO uint32_t EIFCR3; + __IO uint32_t EIFCR4; + __IO uint32_t EIFCR5; + __IO uint32_t EIFCR6; + __IO uint32_t EIFCR7; + __IO uint32_t EIFCR8; + __IO uint32_t EIFCR9; + __IO uint32_t EIFCR10; + __IO uint32_t EIFCR11; + __IO uint32_t EIFCR12; + __IO uint32_t EIFCR13; + __IO uint32_t EIFCR14; + __IO uint32_t EIFCR15; + uint32_t RESERVED0[16]; +} stc_intc_eifcr_bit_t; + +typedef struct { + __IO uint32_t VSEL0; + __IO uint32_t VSEL1; + __IO uint32_t VSEL2; + __IO uint32_t VSEL3; + __IO uint32_t VSEL4; + __IO uint32_t VSEL5; + __IO uint32_t VSEL6; + __IO uint32_t VSEL7; + __IO uint32_t VSEL8; + __IO uint32_t VSEL9; + __IO uint32_t VSEL10; + __IO uint32_t VSEL11; + __IO uint32_t VSEL12; + __IO uint32_t VSEL13; + __IO uint32_t VSEL14; + __IO uint32_t VSEL15; + __IO uint32_t VSEL16; + __IO uint32_t VSEL17; + __IO uint32_t VSEL18; + __IO uint32_t VSEL19; + __IO uint32_t VSEL20; + __IO uint32_t VSEL21; + __IO uint32_t VSEL22; + __IO uint32_t VSEL23; + __IO uint32_t VSEL24; + __IO uint32_t VSEL25; + __IO uint32_t VSEL26; + __IO uint32_t VSEL27; + __IO uint32_t VSEL28; + __IO uint32_t VSEL29; + __IO uint32_t VSEL30; + __IO uint32_t VSEL31; +} stc_intc_vssel_bit_t; + +typedef struct { + __IO uint32_t SWIE0; + __IO uint32_t SWIE1; + __IO uint32_t SWIE2; + __IO uint32_t SWIE3; + __IO uint32_t SWIE4; + __IO uint32_t SWIE5; + __IO uint32_t SWIE6; + __IO uint32_t SWIE7; + __IO uint32_t SWIE8; + __IO uint32_t SWIE9; + __IO uint32_t SWIE10; + __IO uint32_t SWIE11; + __IO uint32_t SWIE12; + __IO uint32_t SWIE13; + __IO uint32_t SWIE14; + __IO uint32_t SWIE15; + __IO uint32_t SWIE16; + __IO uint32_t SWIE17; + __IO uint32_t SWIE18; + __IO uint32_t SWIE19; + __IO uint32_t SWIE20; + __IO uint32_t SWIE21; + __IO uint32_t SWIE22; + __IO uint32_t SWIE23; + __IO uint32_t SWIE24; + __IO uint32_t SWIE25; + __IO uint32_t SWIE26; + __IO uint32_t SWIE27; + __IO uint32_t SWIE28; + __IO uint32_t SWIE29; + __IO uint32_t SWIE30; + __IO uint32_t SWIE31; +} stc_intc_swier_bit_t; + +typedef struct { + __IO uint32_t EVTE0; + __IO uint32_t EVTE1; + __IO uint32_t EVTE2; + __IO uint32_t EVTE3; + __IO uint32_t EVTE4; + __IO uint32_t EVTE5; + __IO uint32_t EVTE6; + __IO uint32_t EVTE7; + __IO uint32_t EVTE8; + __IO uint32_t EVTE9; + __IO uint32_t EVTE10; + __IO uint32_t EVTE11; + __IO uint32_t EVTE12; + __IO uint32_t EVTE13; + __IO uint32_t EVTE14; + __IO uint32_t EVTE15; + __IO uint32_t EVTE16; + __IO uint32_t EVTE17; + __IO uint32_t EVTE18; + __IO uint32_t EVTE19; + __IO uint32_t EVTE20; + __IO uint32_t EVTE21; + __IO uint32_t EVTE22; + __IO uint32_t EVTE23; + __IO uint32_t EVTE24; + __IO uint32_t EVTE25; + __IO uint32_t EVTE26; + __IO uint32_t EVTE27; + __IO uint32_t EVTE28; + __IO uint32_t EVTE29; + __IO uint32_t EVTE30; + __IO uint32_t EVTE31; +} stc_intc_evter_bit_t; + +typedef struct { + __IO uint32_t IER0; + __IO uint32_t IER1; + __IO uint32_t IER2; + __IO uint32_t IER3; + __IO uint32_t IER4; + __IO uint32_t IER5; + __IO uint32_t IER6; + __IO uint32_t IER7; + __IO uint32_t IER8; + __IO uint32_t IER9; + __IO uint32_t IER10; + __IO uint32_t IER11; + __IO uint32_t IER12; + __IO uint32_t IER13; + __IO uint32_t IER14; + __IO uint32_t IER15; + __IO uint32_t IER16; + __IO uint32_t IER17; + __IO uint32_t IER18; + __IO uint32_t IER19; + __IO uint32_t IER20; + __IO uint32_t IER21; + __IO uint32_t IER22; + __IO uint32_t IER23; + __IO uint32_t IER24; + __IO uint32_t IER25; + __IO uint32_t IER26; + __IO uint32_t IER27; + __IO uint32_t IER28; + __IO uint32_t IER29; + __IO uint32_t IER30; + __IO uint32_t IER31; +} stc_intc_ier_bit_t; + +typedef struct { + __IO uint32_t SEN; + uint32_t RESERVED0[31]; +} stc_keyscan_ser_bit_t; + +typedef struct { + __IO uint32_t S2RGRP; + __IO uint32_t S2RGWP; + uint32_t RESERVED0[5]; + __IO uint32_t S2RGE; + __IO uint32_t S1RGRP; + __IO uint32_t S1RGWP; + uint32_t RESERVED1[5]; + __IO uint32_t S1RGE; + __IO uint32_t FRGRP; + __IO uint32_t FRGWP; + uint32_t RESERVED2[5]; + __IO uint32_t FRGE; + uint32_t RESERVED3[8]; +} stc_mpu_rgcr_bit_t; + +typedef struct { + __IO uint32_t SMPU2BRP; + __IO uint32_t SMPU2BWP; + uint32_t RESERVED0[5]; + __IO uint32_t SMPU2E; + __IO uint32_t SMPU1BRP; + __IO uint32_t SMPU1BWP; + uint32_t RESERVED1[5]; + __IO uint32_t SMPU1E; + __IO uint32_t FMPUBRP; + __IO uint32_t FMPUBWP; + uint32_t RESERVED2[5]; + __IO uint32_t FMPUE; + uint32_t RESERVED3[8]; +} stc_mpu_cr_bit_t; + +typedef struct { + __I uint32_t SMPU2EAF; + uint32_t RESERVED0[7]; + __I uint32_t SMPU1EAF; + uint32_t RESERVED1[7]; + __I uint32_t FMPUEAF; + uint32_t RESERVED2[15]; +} stc_mpu_sr_bit_t; + +typedef struct { + __O uint32_t SMPU2ECLR; + uint32_t RESERVED0[7]; + __O uint32_t SMPU1ECLR; + uint32_t RESERVED1[7]; + __O uint32_t FMPUECLR; + uint32_t RESERVED2[15]; +} stc_mpu_eclr_bit_t; + +typedef struct { + __IO uint32_t MPUWE; + uint32_t RESERVED0[31]; +} stc_mpu_wp_bit_t; + +typedef struct { + __IO uint32_t AESRDP; + __IO uint32_t AESWRP; + __IO uint32_t HASHRDP; + __IO uint32_t HASHWRP; + __IO uint32_t TRNGRDP; + __IO uint32_t TRNGWRP; + __IO uint32_t CRCRDP; + __IO uint32_t CRCWRP; + __IO uint32_t EFMRDP; + __IO uint32_t EFMWRP; + uint32_t RESERVED0[2]; + __IO uint32_t WDTRDP; + __IO uint32_t WDTWRP; + __IO uint32_t SWDTRDP; + __IO uint32_t SWDTWRP; + __IO uint32_t BKSRAMRDP; + __IO uint32_t BKSRAMWRP; + __IO uint32_t RTCRDP; + __IO uint32_t RTCWRP; + __IO uint32_t DMPURDP; + __IO uint32_t DMPUWRP; + __IO uint32_t SRAMCRDP; + __IO uint32_t SRAMCWRP; + __IO uint32_t INTCRDP; + __IO uint32_t INTCWRP; + __IO uint32_t SYSCRDP; + __IO uint32_t SYSCWRP; + __IO uint32_t MSTPRDP; + __IO uint32_t MSTPWRP; + uint32_t RESERVED1[1]; + __IO uint32_t BUSERRE; +} stc_mpu_ippr_bit_t; + +typedef struct { + __IO uint32_t OTSST; + __IO uint32_t OTSCK; + __IO uint32_t OTSIE; + __IO uint32_t TSSTP; + uint32_t RESERVED0[12]; +} stc_ots_ctl_bit_t; + +typedef struct { + __IO uint32_t DFB; + __IO uint32_t SOFEN; + uint32_t RESERVED0[30]; +} stc_peric_usbfs_syctlreg_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t SELMMC1; + uint32_t RESERVED1[1]; + __IO uint32_t SELMMC2; + uint32_t RESERVED2[28]; +} stc_peric_sdioc_syctlreg_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t PFE; + __IO uint32_t PFSAE; + __IO uint32_t DCOME; + __IO uint32_t XIPE; + __IO uint32_t SPIMD3; + uint32_t RESERVED1[24]; +} stc_qspi_cr_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t FOUR_BIC; + uint32_t RESERVED1[1]; + __IO uint32_t SSNHD; + __IO uint32_t SSNLD; + __IO uint32_t WPOL; + uint32_t RESERVED2[8]; + __IO uint32_t DUTY; + uint32_t RESERVED3[16]; +} stc_qspi_fcr_bit_t; + +typedef struct { + __IO uint32_t BUSY; + uint32_t RESERVED0[5]; + __IO uint32_t XIPF; + __IO uint32_t RAER; + uint32_t RESERVED1[6]; + __IO uint32_t PFFUL; + __IO uint32_t PFAN; + uint32_t RESERVED2[16]; +} stc_qspi_sr_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __O uint32_t RAERCLR; + uint32_t RESERVED1[24]; +} stc_qspi_clr_bit_t; + +typedef struct { + __IO uint32_t PORF; + __IO uint32_t PINRF; + __IO uint32_t BORF; + __IO uint32_t PVD1RF; + __IO uint32_t PVD2RF; + __IO uint32_t WDRF; + __IO uint32_t SWDRF; + __IO uint32_t PDRF; + __IO uint32_t SWRF; + __IO uint32_t MPUERF; + __IO uint32_t RAPERF; + __IO uint32_t RAECRF; + __IO uint32_t CKFERF; + __IO uint32_t XTALERF; + __IO uint32_t MULTIRF; + __IO uint32_t CLRF; +} stc_rmu_rstf0_bit_t; + +typedef struct { + __IO uint32_t RESET; + uint32_t RESERVED0[7]; +} stc_rtc_cr0_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t AMPM; + __IO uint32_t ALMFCLR; + __IO uint32_t ONEHZOE; + __IO uint32_t ONEHZSEL; + __IO uint32_t START; +} stc_rtc_cr1_bit_t; + +typedef struct { + __IO uint32_t RWREQ; + __IO uint32_t RWEN; + uint32_t RESERVED0[1]; + __IO uint32_t ALMF; + uint32_t RESERVED1[1]; + __IO uint32_t PRDIE; + __IO uint32_t ALMIE; + __IO uint32_t ALME; +} stc_rtc_cr2_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t LRCEN; + uint32_t RESERVED1[2]; + __IO uint32_t RCKSEL; +} stc_rtc_cr3_bit_t; + +typedef struct { + __IO uint32_t COMP8; + uint32_t RESERVED0[6]; + __IO uint32_t COMPEN; +} stc_rtc_errcrh_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t BCE; + uint32_t RESERVED1[2]; + __IO uint32_t DDIR; + __IO uint32_t MULB; + uint32_t RESERVED2[10]; +} stc_sdioc_transmode_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t CCE; + __IO uint32_t ICE; + __IO uint32_t DAT; + uint32_t RESERVED1[10]; +} stc_sdioc_cmd_bit_t; + +typedef struct { + __I uint32_t CIC; + __I uint32_t CID; + __I uint32_t DA; + uint32_t RESERVED0[5]; + __I uint32_t WTA; + __I uint32_t RTA; + __I uint32_t BWE; + __I uint32_t BRE; + uint32_t RESERVED1[4]; + __I uint32_t CIN; + __I uint32_t CSS; + __I uint32_t CDL; + __I uint32_t WPL; + uint32_t RESERVED2[4]; + __I uint32_t CMDL; + uint32_t RESERVED3[7]; +} stc_sdioc_pstat_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t DW; + __IO uint32_t HSEN; + uint32_t RESERVED1[2]; + __IO uint32_t EXDW; + __IO uint32_t CDTL; + __IO uint32_t CDSS; +} stc_sdioc_hostcon_bit_t; + +typedef struct { + __IO uint32_t PWON; + uint32_t RESERVED0[7]; +} stc_sdioc_pwrcon_bit_t; + +typedef struct { + __IO uint32_t SABGR; + __IO uint32_t CR; + __IO uint32_t RWC; + __IO uint32_t IABG; + uint32_t RESERVED0[4]; +} stc_sdioc_blkgpcon_bit_t; + +typedef struct { + __IO uint32_t ICE; + uint32_t RESERVED0[1]; + __IO uint32_t CE; + uint32_t RESERVED1[13]; +} stc_sdioc_clkcon_bit_t; + +typedef struct { + __IO uint32_t RSTA; + __IO uint32_t RSTC; + __IO uint32_t RSTD; + uint32_t RESERVED0[5]; +} stc_sdioc_sftrst_bit_t; + +typedef struct { + __IO uint32_t CC; + __IO uint32_t TC; + __IO uint32_t BGE; + uint32_t RESERVED0[1]; + __IO uint32_t BWR; + __IO uint32_t BRR; + __IO uint32_t CIST; + __IO uint32_t CRM; + __I uint32_t CINT; + uint32_t RESERVED1[6]; + __I uint32_t EI; +} stc_sdioc_norintst_bit_t; + +typedef struct { + __IO uint32_t CTOE; + __IO uint32_t CCE; + __IO uint32_t CEBE; + __IO uint32_t CIE; + __IO uint32_t DTOE; + __IO uint32_t DCE; + __IO uint32_t DEBE; + uint32_t RESERVED0[1]; + __IO uint32_t ACE; + uint32_t RESERVED1[7]; +} stc_sdioc_errintst_bit_t; + +typedef struct { + __IO uint32_t CCEN; + __IO uint32_t TCEN; + __IO uint32_t BGEEN; + uint32_t RESERVED0[1]; + __IO uint32_t BWREN; + __IO uint32_t BRREN; + __IO uint32_t CISTEN; + __IO uint32_t CRMEN; + __IO uint32_t CINTEN; + uint32_t RESERVED1[7]; +} stc_sdioc_norintsten_bit_t; + +typedef struct { + __IO uint32_t CTOEEN; + __IO uint32_t CCEEN; + __IO uint32_t CEBEEN; + __IO uint32_t CIEEN; + __IO uint32_t DTOEEN; + __IO uint32_t DCEEN; + __IO uint32_t DEBEEN; + uint32_t RESERVED0[1]; + __IO uint32_t ACEEN; + uint32_t RESERVED1[7]; +} stc_sdioc_errintsten_bit_t; + +typedef struct { + __IO uint32_t CCSEN; + __IO uint32_t TCSEN; + __IO uint32_t BGESEN; + uint32_t RESERVED0[1]; + __IO uint32_t BWRSEN; + __IO uint32_t BRRSEN; + __IO uint32_t CISTSEN; + __IO uint32_t CRMSEN; + __IO uint32_t CINTSEN; + uint32_t RESERVED1[7]; +} stc_sdioc_norintsgen_bit_t; + +typedef struct { + __IO uint32_t CTOESEN; + __IO uint32_t CCESEN; + __IO uint32_t CEBESEN; + __IO uint32_t CIESEN; + __IO uint32_t DTOESEN; + __IO uint32_t DCESEN; + __IO uint32_t DEBESEN; + uint32_t RESERVED0[1]; + __IO uint32_t ACESEN; + uint32_t RESERVED1[7]; +} stc_sdioc_errintsgen_bit_t; + +typedef struct { + __I uint32_t NE; + __I uint32_t TOE; + __I uint32_t CE; + __I uint32_t EBE; + __I uint32_t IE; + uint32_t RESERVED0[2]; + __I uint32_t CMDE; + uint32_t RESERVED1[8]; +} stc_sdioc_atcerrst_bit_t; + +typedef struct { + __O uint32_t FNE; + __O uint32_t FTOE; + __O uint32_t FCE; + __O uint32_t FEBE; + __O uint32_t FIE; + uint32_t RESERVED0[2]; + __O uint32_t FCMDE; + uint32_t RESERVED1[8]; +} stc_sdioc_fea_bit_t; + +typedef struct { + __O uint32_t FCTOE; + __O uint32_t FCCE; + __O uint32_t FCEBE; + __O uint32_t FCIE; + __O uint32_t FDTOE; + __O uint32_t FDCE; + __O uint32_t FDEBE; + uint32_t RESERVED0[1]; + __O uint32_t FACE; + uint32_t RESERVED1[7]; +} stc_sdioc_fee_bit_t; + +typedef struct { + __IO uint32_t SPIMDS; + __IO uint32_t TXMDS; + uint32_t RESERVED0[1]; + __IO uint32_t MSTR; + __IO uint32_t SPLPBK; + __IO uint32_t SPLPBK2; + __IO uint32_t SPE; + __IO uint32_t CSUSPE; + __IO uint32_t EIE; + __IO uint32_t TXIE; + __IO uint32_t RXIE; + __IO uint32_t IDIE; + __IO uint32_t MODFE; + __IO uint32_t PATE; + __IO uint32_t PAOE; + __IO uint32_t PAE; + uint32_t RESERVED1[16]; +} stc_spi_cr1_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t SPRDTD; + uint32_t RESERVED1[1]; + __IO uint32_t SS0PV; + __IO uint32_t SS1PV; + __IO uint32_t SS2PV; + __IO uint32_t SS3PV; + uint32_t RESERVED2[20]; +} stc_spi_cfg1_bit_t; + +typedef struct { + __IO uint32_t OVRERF; + __I uint32_t IDLNF; + __IO uint32_t MODFERF; + __IO uint32_t PERF; + __IO uint32_t UDRERF; + __IO uint32_t TDEF; + uint32_t RESERVED0[1]; + __IO uint32_t RDFF; + uint32_t RESERVED1[24]; +} stc_spi_sr_bit_t; + +typedef struct { + __IO uint32_t CPHA; + __IO uint32_t CPOL; + uint32_t RESERVED0[10]; + __IO uint32_t LSBF; + __IO uint32_t MIDIE; + __IO uint32_t MSSDLE; + __IO uint32_t MSSIE; + uint32_t RESERVED1[16]; +} stc_spi_cfg2_bit_t; + +typedef struct { + __IO uint32_t WTPRC; + uint32_t RESERVED0[31]; +} stc_sramc_wtpr_bit_t; + +typedef struct { + __IO uint32_t PYOAD; + uint32_t RESERVED0[15]; + __IO uint32_t ECCOAD; + uint32_t RESERVED1[15]; +} stc_sramc_ckcr_bit_t; + +typedef struct { + __IO uint32_t CKPRC; + uint32_t RESERVED0[31]; +} stc_sramc_ckpr_bit_t; + +typedef struct { + __IO uint32_t SRAM3_1ERR; + __IO uint32_t SRAM3_2ERR; + __IO uint32_t SRAM12_PYERR; + __IO uint32_t SRAMH_PYERR; + __IO uint32_t SRAMR_PYERR; + uint32_t RESERVED0[27]; +} stc_sramc_cksr_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __IO uint32_t UDF; + __IO uint32_t REF; + uint32_t RESERVED1[14]; +} stc_swdt_sr_bit_t; + +typedef struct { + __IO uint32_t CSTA; + __IO uint32_t CAPMDA; + __IO uint32_t INTENA; + uint32_t RESERVED0[5]; + __IO uint32_t SYNSA; + __IO uint32_t SYNCLKA; + __IO uint32_t ASYNCLKA; + uint32_t RESERVED1[1]; + __IO uint32_t HSTAA; + __IO uint32_t HSTPA; + __IO uint32_t HCLEA; + __IO uint32_t HICPA; + __IO uint32_t CSTB; + __IO uint32_t CAPMDB; + __IO uint32_t INTENB; + uint32_t RESERVED2[5]; + __IO uint32_t SYNSB; + __IO uint32_t SYNCLKB; + __IO uint32_t ASYNCLKB; + uint32_t RESERVED3[1]; + __IO uint32_t HSTAB; + __IO uint32_t HSTPB; + __IO uint32_t HCLEB; + __IO uint32_t HICPB; +} stc_tmr0_bconr_bit_t; + +typedef struct { + __IO uint32_t CMFA; + uint32_t RESERVED0[15]; + __IO uint32_t CMFB; + uint32_t RESERVED1[15]; +} stc_tmr0_stflr_bit_t; + +typedef struct { + __IO uint32_t OCEH; + __IO uint32_t OCEL; + __IO uint32_t OCPH; + __IO uint32_t OCPL; + __IO uint32_t OCIEH; + __IO uint32_t OCIEL; + __IO uint32_t OCFH; + __IO uint32_t OCFL; + uint32_t RESERVED0[8]; +} stc_tmr4_ocsr_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t LMCH; + __IO uint32_t LMCL; + __IO uint32_t LMMH; + __IO uint32_t LMML; + __IO uint32_t MCECH; + __IO uint32_t MCECL; + uint32_t RESERVED1[2]; +} stc_tmr4_ocer_bit_t; + +typedef struct { + __IO uint32_t OCFDCH; + __IO uint32_t OCFPKH; + __IO uint32_t OCFUCH; + __IO uint32_t OCFZRH; + uint32_t RESERVED0[12]; +} stc_tmr4_ocmrh_bit_t; + +typedef struct { + __IO uint32_t OCFDCL; + __IO uint32_t OCFPKL; + __IO uint32_t OCFUCL; + __IO uint32_t OCFZRL; + uint32_t RESERVED0[28]; +} stc_tmr4_ocmrl_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t CLEAR; + __IO uint32_t MODE; + __IO uint32_t STOP; + __IO uint32_t BUFEN; + __IO uint32_t IRQPEN; + __IO uint32_t IRQPF; + uint32_t RESERVED1[3]; + __IO uint32_t IRQZEN; + __IO uint32_t IRQZF; + __IO uint32_t ECKEN; +} stc_tmr4_ccsr_bit_t; + +typedef struct { + __IO uint32_t RTIDU; + __IO uint32_t RTIDV; + __IO uint32_t RTIDW; + uint32_t RESERVED0[1]; + __I uint32_t RTIFU; + __IO uint32_t RTICU; + __IO uint32_t RTEU; + __IO uint32_t RTSU; + __I uint32_t RTIFV; + __IO uint32_t RTICV; + __IO uint32_t RTEV; + __IO uint32_t RTSV; + __I uint32_t RTIFW; + __IO uint32_t RTICW; + __IO uint32_t RTEW; + __IO uint32_t RTSW; +} stc_tmr4_rcsr_bit_t; + +typedef struct { + uint32_t RESERVED0[5]; + __IO uint32_t LMC; + uint32_t RESERVED1[2]; + __IO uint32_t EVTMS; + __IO uint32_t EVTDS; + uint32_t RESERVED2[2]; + __IO uint32_t DEN; + __IO uint32_t PEN; + __IO uint32_t UEN; + __IO uint32_t ZEN; +} stc_tmr4_scsr_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t MZCE; + __IO uint32_t MPCE; + uint32_t RESERVED1[8]; +} stc_tmr4_scmr_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t HOLD; + uint32_t RESERVED1[8]; +} stc_tmr4_ecsr_bit_t; + +typedef struct { + __IO uint32_t START; + uint32_t RESERVED0[7]; + __IO uint32_t DIR; + uint32_t RESERVED1[7]; + __IO uint32_t ZMSKREV; + __IO uint32_t ZMSKPOS; + uint32_t RESERVED2[14]; +} stc_tmr6_gconr_bit_t; + +typedef struct { + __IO uint32_t INTENA; + __IO uint32_t INTENB; + __IO uint32_t INTENC; + __IO uint32_t INTEND; + __IO uint32_t INTENE; + __IO uint32_t INTENF; + __IO uint32_t INTENOVF; + __IO uint32_t INTENUDF; + __IO uint32_t INTENDTE; + uint32_t RESERVED0[7]; + __IO uint32_t INTENSAU; + __IO uint32_t INTENSAD; + __IO uint32_t INTENSBU; + __IO uint32_t INTENSBD; + uint32_t RESERVED1[12]; +} stc_tmr6_iconr_bit_t; + +typedef struct { + __IO uint32_t CAPMDA; + __IO uint32_t STACA; + __IO uint32_t STPCA; + __IO uint32_t STASTPSA; + uint32_t RESERVED0[4]; + __IO uint32_t OUTENA; + uint32_t RESERVED1[7]; + __IO uint32_t CAPMDB; + __IO uint32_t STACB; + __IO uint32_t STPCB; + __IO uint32_t STASTPSB; + uint32_t RESERVED2[4]; + __IO uint32_t OUTENB; + uint32_t RESERVED3[7]; +} stc_tmr6_pconr_bit_t; + +typedef struct { + __IO uint32_t BENA; + __IO uint32_t BSEA; + __IO uint32_t BENB; + __IO uint32_t BSEB; + uint32_t RESERVED0[4]; + __IO uint32_t BENP; + __IO uint32_t BSEP; + uint32_t RESERVED1[6]; + __IO uint32_t BENSPA; + __IO uint32_t BSESPA; + uint32_t RESERVED2[2]; + __IO uint32_t BTRUSPA; + __IO uint32_t BTRDSPA; + uint32_t RESERVED3[2]; + __IO uint32_t BENSPB; + __IO uint32_t BSESPB; + uint32_t RESERVED4[2]; + __IO uint32_t BTRUSPB; + __IO uint32_t BTRDSPB; + uint32_t RESERVED5[2]; +} stc_tmr6_bconr_bit_t; + +typedef struct { + __IO uint32_t DTCEN; + uint32_t RESERVED0[3]; + __IO uint32_t DTBENU; + __IO uint32_t DTBEND; + uint32_t RESERVED1[2]; + __IO uint32_t SEPA; + uint32_t RESERVED2[23]; +} stc_tmr6_dconr_bit_t; + +typedef struct { + __IO uint32_t NOFIENGA; + uint32_t RESERVED0[3]; + __IO uint32_t NOFIENGB; + uint32_t RESERVED1[11]; + __IO uint32_t NOFIENTA; + uint32_t RESERVED2[3]; + __IO uint32_t NOFIENTB; + uint32_t RESERVED3[11]; +} stc_tmr6_fconr_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t SPPERIA; + __IO uint32_t SPPERIB; + uint32_t RESERVED1[22]; +} stc_tmr6_vperr_bit_t; + +typedef struct { + __IO uint32_t CMAF; + __IO uint32_t CMBF; + __IO uint32_t CMCF; + __IO uint32_t CMDF; + __IO uint32_t CMEF; + __IO uint32_t CMFF; + __IO uint32_t OVFF; + __IO uint32_t UDFF; + __I uint32_t DTEF; + __IO uint32_t CMSAUF; + __IO uint32_t CMSADF; + __IO uint32_t CMSBUF; + __IO uint32_t CMSBDF; + uint32_t RESERVED0[18]; + __I uint32_t DIRF; +} stc_tmr6_stflr_bit_t; + +typedef struct { + __IO uint32_t HSTA0; + __IO uint32_t HSTA1; + uint32_t RESERVED0[2]; + __IO uint32_t HSTA4; + __IO uint32_t HSTA5; + __IO uint32_t HSTA6; + __IO uint32_t HSTA7; + __IO uint32_t HSTA8; + __IO uint32_t HSTA9; + __IO uint32_t HSTA10; + __IO uint32_t HSTA11; + uint32_t RESERVED1[19]; + __IO uint32_t STAS; +} stc_tmr6_hstar_bit_t; + +typedef struct { + __IO uint32_t HSTP0; + __IO uint32_t HSTP1; + uint32_t RESERVED0[2]; + __IO uint32_t HSTP4; + __IO uint32_t HSTP5; + __IO uint32_t HSTP6; + __IO uint32_t HSTP7; + __IO uint32_t HSTP8; + __IO uint32_t HSTP9; + __IO uint32_t HSTP10; + __IO uint32_t HSTP11; + uint32_t RESERVED1[19]; + __IO uint32_t STPS; +} stc_tmr6_hstpr_bit_t; + +typedef struct { + __IO uint32_t HCLE0; + __IO uint32_t HCLE1; + uint32_t RESERVED0[2]; + __IO uint32_t HCLE4; + __IO uint32_t HCLE5; + __IO uint32_t HCLE6; + __IO uint32_t HCLE7; + __IO uint32_t HCLE8; + __IO uint32_t HCLE9; + __IO uint32_t HCLE10; + __IO uint32_t HCLE11; + uint32_t RESERVED1[19]; + __IO uint32_t CLES; +} stc_tmr6_hclrr_bit_t; + +typedef struct { + __IO uint32_t HCPA0; + __IO uint32_t HCPA1; + uint32_t RESERVED0[2]; + __IO uint32_t HCPA4; + __IO uint32_t HCPA5; + __IO uint32_t HCPA6; + __IO uint32_t HCPA7; + __IO uint32_t HCPA8; + __IO uint32_t HCPA9; + __IO uint32_t HCPA10; + __IO uint32_t HCPA11; + uint32_t RESERVED1[20]; +} stc_tmr6_hcpar_bit_t; + +typedef struct { + __IO uint32_t HCPB0; + __IO uint32_t HCPB1; + uint32_t RESERVED0[2]; + __IO uint32_t HCPB4; + __IO uint32_t HCPB5; + __IO uint32_t HCPB6; + __IO uint32_t HCPB7; + __IO uint32_t HCPB8; + __IO uint32_t HCPB9; + __IO uint32_t HCPB10; + __IO uint32_t HCPB11; + uint32_t RESERVED1[20]; +} stc_tmr6_hcpbr_bit_t; + +typedef struct { + __IO uint32_t HCUP0; + __IO uint32_t HCUP1; + __IO uint32_t HCUP2; + __IO uint32_t HCUP3; + __IO uint32_t HCUP4; + __IO uint32_t HCUP5; + __IO uint32_t HCUP6; + __IO uint32_t HCUP7; + __IO uint32_t HCUP8; + __IO uint32_t HCUP9; + __IO uint32_t HCUP10; + __IO uint32_t HCUP11; + uint32_t RESERVED0[4]; + __IO uint32_t HCUP16; + __IO uint32_t HCUP17; + uint32_t RESERVED1[14]; +} stc_tmr6_hcupr_bit_t; + +typedef struct { + __IO uint32_t HCDO0; + __IO uint32_t HCDO1; + __IO uint32_t HCDO2; + __IO uint32_t HCDO3; + __IO uint32_t HCDO4; + __IO uint32_t HCDO5; + __IO uint32_t HCDO6; + __IO uint32_t HCDO7; + __IO uint32_t HCDO8; + __IO uint32_t HCDO9; + __IO uint32_t HCDO10; + __IO uint32_t HCDO11; + uint32_t RESERVED0[4]; + __IO uint32_t HCDO16; + __IO uint32_t HCDO17; + uint32_t RESERVED1[14]; +} stc_tmr6_hcdor_bit_t; + +typedef struct { + __IO uint32_t SSTA1; + __IO uint32_t SSTA2; + __IO uint32_t SSTA3; + uint32_t RESERVED0[29]; +} stc_tmr6_common_sstar_bit_t; + +typedef struct { + __IO uint32_t SSTP1; + __IO uint32_t SSTP2; + __IO uint32_t SSTP3; + uint32_t RESERVED0[29]; +} stc_tmr6_common_sstpr_bit_t; + +typedef struct { + __IO uint32_t SCLE1; + __IO uint32_t SCLE2; + __IO uint32_t SCLE3; + uint32_t RESERVED0[29]; +} stc_tmr6_common_sclrr_bit_t; + +typedef struct { + __IO uint32_t START; + __IO uint32_t DIR; + __IO uint32_t MODE; + __IO uint32_t SYNST; + uint32_t RESERVED0[4]; +} stc_tmra_bcstrl_bit_t; + +typedef struct { + __IO uint32_t OVSTP; + uint32_t RESERVED0[3]; + __IO uint32_t ITENOVF; + __IO uint32_t ITENUDF; + __IO uint32_t OVFF; + __IO uint32_t UDFF; +} stc_tmra_bcstrh_bit_t; + +typedef struct { + __IO uint32_t HSTA0; + __IO uint32_t HSTA1; + __IO uint32_t HSTA2; + uint32_t RESERVED0[1]; + __IO uint32_t HSTP0; + __IO uint32_t HSTP1; + __IO uint32_t HSTP2; + uint32_t RESERVED1[1]; + __IO uint32_t HCLE0; + __IO uint32_t HCLE1; + __IO uint32_t HCLE2; + uint32_t RESERVED2[1]; + __IO uint32_t HCLE3; + __IO uint32_t HCLE4; + __IO uint32_t HCLE5; + __IO uint32_t HCLE6; +} stc_tmra_hconr_bit_t; + +typedef struct { + __IO uint32_t HCUP0; + __IO uint32_t HCUP1; + __IO uint32_t HCUP2; + __IO uint32_t HCUP3; + __IO uint32_t HCUP4; + __IO uint32_t HCUP5; + __IO uint32_t HCUP6; + __IO uint32_t HCUP7; + __IO uint32_t HCUP8; + __IO uint32_t HCUP9; + __IO uint32_t HCUP10; + __IO uint32_t HCUP11; + __IO uint32_t HCUP12; + uint32_t RESERVED0[3]; +} stc_tmra_hcupr_bit_t; + +typedef struct { + __IO uint32_t HCDO0; + __IO uint32_t HCDO1; + __IO uint32_t HCDO2; + __IO uint32_t HCDO3; + __IO uint32_t HCDO4; + __IO uint32_t HCDO5; + __IO uint32_t HCDO6; + __IO uint32_t HCDO7; + __IO uint32_t HCDO8; + __IO uint32_t HCDO9; + __IO uint32_t HCDO10; + __IO uint32_t HCDO11; + __IO uint32_t HCDO12; + uint32_t RESERVED0[3]; +} stc_tmra_hcdor_bit_t; + +typedef struct { + __IO uint32_t ITEN1; + __IO uint32_t ITEN2; + __IO uint32_t ITEN3; + __IO uint32_t ITEN4; + __IO uint32_t ITEN5; + __IO uint32_t ITEN6; + __IO uint32_t ITEN7; + __IO uint32_t ITEN8; + uint32_t RESERVED0[8]; +} stc_tmra_iconr_bit_t; + +typedef struct { + __IO uint32_t ETEN1; + __IO uint32_t ETEN2; + __IO uint32_t ETEN3; + __IO uint32_t ETEN4; + __IO uint32_t ETEN5; + __IO uint32_t ETEN6; + __IO uint32_t ETEN7; + __IO uint32_t ETEN8; + uint32_t RESERVED0[8]; +} stc_tmra_econr_bit_t; + +typedef struct { + __IO uint32_t NOFIENTG; + uint32_t RESERVED0[7]; + __IO uint32_t NOFIENCA; + uint32_t RESERVED1[3]; + __IO uint32_t NOFIENCB; + uint32_t RESERVED2[3]; +} stc_tmra_fconr_bit_t; + +typedef struct { + __IO uint32_t CMPF1; + __IO uint32_t CMPF2; + __IO uint32_t CMPF3; + __IO uint32_t CMPF4; + __IO uint32_t CMPF5; + __IO uint32_t CMPF6; + __IO uint32_t CMPF7; + __IO uint32_t CMPF8; + uint32_t RESERVED0[8]; +} stc_tmra_stflr_bit_t; + +typedef struct { + __IO uint32_t BEN; + __IO uint32_t BSE0; + __IO uint32_t BSE1; + uint32_t RESERVED0[13]; +} stc_tmra_bconr_bit_t; + +typedef struct { + __IO uint32_t CAPMD; + uint32_t RESERVED0[3]; + __IO uint32_t HICP0; + __IO uint32_t HICP1; + __IO uint32_t HICP2; + uint32_t RESERVED1[1]; + __IO uint32_t HICP3; + __IO uint32_t HICP4; + uint32_t RESERVED2[2]; + __IO uint32_t NOFIENCP; + uint32_t RESERVED3[3]; +} stc_tmra_cconr_bit_t; + +typedef struct { + uint32_t RESERVED0[12]; + __IO uint32_t OUTEN; + uint32_t RESERVED1[3]; +} stc_tmra_pconr_bit_t; + +typedef struct { + __IO uint32_t EN; + __IO uint32_t RUN; + uint32_t RESERVED0[30]; +} stc_trng_cr_bit_t; + +typedef struct { + __IO uint32_t LOAD; + uint32_t RESERVED0[31]; +} stc_trng_mr_bit_t; + +typedef struct { + __I uint32_t PE; + __I uint32_t FE; + uint32_t RESERVED0[1]; + __I uint32_t ORE; + uint32_t RESERVED1[1]; + __I uint32_t RXNE; + __I uint32_t TC; + __I uint32_t TXE; + __I uint32_t RTOF; + uint32_t RESERVED2[7]; + __I uint32_t MPB; + uint32_t RESERVED3[15]; +} stc_usart_sr_bit_t; + +typedef struct { + uint32_t RESERVED0[9]; + __IO uint32_t MPID; + uint32_t RESERVED1[6]; +} stc_usart_tdr_bit_t; + +typedef struct { + __IO uint32_t RTOE; + __IO uint32_t RTOIE; + __IO uint32_t RE; + __IO uint32_t TE; + __IO uint32_t SLME; + __IO uint32_t RIE; + __IO uint32_t TCIE; + __IO uint32_t TXEIE; + uint32_t RESERVED0[1]; + __IO uint32_t PS; + __IO uint32_t PCE; + uint32_t RESERVED1[1]; + __IO uint32_t M; + uint32_t RESERVED2[2]; + __IO uint32_t OVER8; + __O uint32_t CPE; + __O uint32_t CFE; + uint32_t RESERVED3[1]; + __O uint32_t CORE; + __O uint32_t CRTOF; + uint32_t RESERVED4[3]; + __IO uint32_t MS; + uint32_t RESERVED5[3]; + __IO uint32_t ML; + __IO uint32_t FBME; + __IO uint32_t NFE; + __IO uint32_t SBS; +} stc_usart_cr1_bit_t; + +typedef struct { + __IO uint32_t MPE; + uint32_t RESERVED0[12]; + __IO uint32_t STOP; + uint32_t RESERVED1[18]; +} stc_usart_cr2_bit_t; + +typedef struct { + uint32_t RESERVED0[5]; + __IO uint32_t SCEN; + uint32_t RESERVED1[3]; + __IO uint32_t CTSE; + uint32_t RESERVED2[22]; +} stc_usart_cr3_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t VBUSOVEN; + __IO uint32_t VBUSVAL; + uint32_t RESERVED1[24]; +} stc_usbfs_gvbuscfg_bit_t; + +typedef struct { + __IO uint32_t GINTMSK; + uint32_t RESERVED0[4]; + __IO uint32_t DMAEN; + uint32_t RESERVED1[1]; + __IO uint32_t TXFELVL; + __IO uint32_t PTXFELVL; + uint32_t RESERVED2[23]; +} stc_usbfs_gahbcfg_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t PHYSEL; + uint32_t RESERVED1[22]; + __IO uint32_t FHMOD; + __IO uint32_t FDMOD; + uint32_t RESERVED2[1]; +} stc_usbfs_gusbcfg_bit_t; + +typedef struct { + __IO uint32_t CSRST; + __IO uint32_t HSRST; + __IO uint32_t FCRST; + uint32_t RESERVED0[1]; + __IO uint32_t RXFFLSH; + __IO uint32_t TXFFLSH; + uint32_t RESERVED1[24]; + __I uint32_t DMAREQ; + __I uint32_t AHBIDL; +} stc_usbfs_grstctl_bit_t; + +typedef struct { + __I uint32_t CMOD; + __IO uint32_t MMIS; + uint32_t RESERVED0[1]; + __IO uint32_t SOF; + __I uint32_t RXFNE; + __I uint32_t NPTXFE; + __I uint32_t GINAKEFF; + __I uint32_t GONAKEFF; + uint32_t RESERVED1[2]; + __IO uint32_t ESUSP; + __IO uint32_t USBSUSP; + __IO uint32_t USBRST; + __IO uint32_t ENUMDNE; + __IO uint32_t ISOODRP; + __IO uint32_t EOPF; + uint32_t RESERVED2[2]; + __I uint32_t IEPINT; + __I uint32_t OEPINT; + __IO uint32_t IISOIXFR; + __IO uint32_t IPXFR_INCOMPISOOUT; + __IO uint32_t DATAFSUSP; + uint32_t RESERVED3[1]; + __I uint32_t HPRTINT; + __I uint32_t HCINT; + __I uint32_t PTXFE; + uint32_t RESERVED4[1]; + __IO uint32_t CIDSCHG; + __IO uint32_t DISCINT; + __IO uint32_t VBUSVINT; + __IO uint32_t WKUINT; +} stc_usbfs_gintsts_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t MMISM; + uint32_t RESERVED1[1]; + __IO uint32_t SOFM; + __IO uint32_t RXFNEM; + __IO uint32_t NPTXFEM; + __IO uint32_t GINAKEFFM; + __IO uint32_t GONAKEFFM; + uint32_t RESERVED2[2]; + __IO uint32_t ESUSPM; + __IO uint32_t USBSUSPM; + __IO uint32_t USBRSTM; + __IO uint32_t ENUMDNEM; + __IO uint32_t ISOODRPM; + __IO uint32_t EOPFM; + uint32_t RESERVED3[2]; + __IO uint32_t IEPIM; + __IO uint32_t OEPIM; + __IO uint32_t IISOIXFRM; + __IO uint32_t IPXFRM_INCOMPISOOUTM; + __IO uint32_t DATAFSUSPM; + uint32_t RESERVED4[1]; + __IO uint32_t HPRTIM; + __IO uint32_t HCIM; + __IO uint32_t PTXFEM; + uint32_t RESERVED5[1]; + __IO uint32_t CIDSCHGM; + __IO uint32_t DISCIM; + __IO uint32_t VBUSVIM; + __IO uint32_t WKUIM; +} stc_usbfs_gintmsk_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t FSLSS; + uint32_t RESERVED1[29]; +} stc_usbfs_hcfg_bit_t; + +typedef struct { + __I uint32_t PCSTS; + __IO uint32_t PCDET; + __IO uint32_t PENA; + __IO uint32_t PENCHNG; + uint32_t RESERVED0[2]; + __IO uint32_t PRES; + __IO uint32_t PSUSP; + __IO uint32_t PRST; + uint32_t RESERVED1[3]; + __IO uint32_t PWPR; + uint32_t RESERVED2[19]; +} stc_usbfs_hprt_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSDEV; + uint32_t RESERVED2[11]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbfs_hcchar_bit_t; + +typedef struct { + __IO uint32_t XFRC; + __IO uint32_t CHH; + uint32_t RESERVED0[1]; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + uint32_t RESERVED1[1]; + __IO uint32_t TXERR; + __IO uint32_t BBERR; + __IO uint32_t FRMOR; + __IO uint32_t DTERR; + uint32_t RESERVED2[21]; +} stc_usbfs_hcint_bit_t; + +typedef struct { + __IO uint32_t XFRCM; + __IO uint32_t CHHM; + uint32_t RESERVED0[1]; + __IO uint32_t STALLM; + __IO uint32_t NAKM; + __IO uint32_t ACKM; + uint32_t RESERVED1[1]; + __IO uint32_t TXERRM; + __IO uint32_t BBERRM; + __IO uint32_t FRMORM; + __IO uint32_t DTERRM; + uint32_t RESERVED2[21]; +} stc_usbfs_hcintmsk_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t NZLSOHSK; + uint32_t RESERVED1[29]; +} stc_usbfs_dcfg_bit_t; + +typedef struct { + __IO uint32_t RWUSIG; + __IO uint32_t SDIS; + __I uint32_t GINSTS; + __I uint32_t GONSTS; + uint32_t RESERVED0[3]; + __O uint32_t SGINAK; + __O uint32_t CGINAK; + __O uint32_t SGONAK; + __O uint32_t CGONAK; + __IO uint32_t POPRGDNE; + uint32_t RESERVED1[20]; +} stc_usbfs_dctl_bit_t; + +typedef struct { + __I uint32_t SUSPSTS; + uint32_t RESERVED0[2]; + __I uint32_t EERR; + uint32_t RESERVED1[28]; +} stc_usbfs_dsts_bit_t; + +typedef struct { + __IO uint32_t XFRCM; + __IO uint32_t EPDM; + uint32_t RESERVED0[1]; + __IO uint32_t TOM; + __IO uint32_t TTXFEMSK; + __IO uint32_t INEPNMM; + __IO uint32_t INEPNEM; + uint32_t RESERVED1[25]; +} stc_usbfs_diepmsk_bit_t; + +typedef struct { + __IO uint32_t XFRCM; + __IO uint32_t EPDM; + uint32_t RESERVED0[1]; + __IO uint32_t STUPM; + __IO uint32_t OTEPDM; + uint32_t RESERVED1[27]; +} stc_usbfs_doepmsk_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __I uint32_t USBAEP; + uint32_t RESERVED1[1]; + __I uint32_t NAKSTS; + uint32_t RESERVED2[3]; + __IO uint32_t STALL; + uint32_t RESERVED3[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + uint32_t RESERVED4[2]; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl0_bit_t; + +typedef struct { + __IO uint32_t XFRC; + __IO uint32_t EPDISD; + uint32_t RESERVED0[1]; + __IO uint32_t TOC; + __IO uint32_t TTXFE; + uint32_t RESERVED1[1]; + __IO uint32_t INEPNE; + __I uint32_t TXFE; + uint32_t RESERVED2[24]; +} stc_usbfs_diepint_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __IO uint32_t USBAEP; + __I uint32_t EONUM_DPID; + __I uint32_t NAKSTS; + uint32_t RESERVED1[3]; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SD0PID_SEVNFRM; + __IO uint32_t SODDFRM; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __I uint32_t USBAEP; + uint32_t RESERVED1[1]; + __I uint32_t NAKSTS; + uint32_t RESERVED2[2]; + __IO uint32_t SNPM; + __IO uint32_t STALL; + uint32_t RESERVED3[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + uint32_t RESERVED4[2]; + __I uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl0_bit_t; + +typedef struct { + __IO uint32_t XFRC; + __IO uint32_t EPDISD; + uint32_t RESERVED0[1]; + __IO uint32_t STUP; + __IO uint32_t OTEPDIS; + uint32_t RESERVED1[1]; + __IO uint32_t B2BSTUP; + uint32_t RESERVED2[25]; +} stc_usbfs_doepint_bit_t; + +typedef struct { + uint32_t RESERVED0[19]; + __IO uint32_t PKTCNT; + uint32_t RESERVED1[12]; +} stc_usbfs_doeptsiz0_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __IO uint32_t USBAEP; + __I uint32_t DPID; + __I uint32_t NAKSTS; + uint32_t RESERVED1[2]; + __IO uint32_t SNPM; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SD0PID; + __IO uint32_t SD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl_bit_t; + +typedef struct { + __IO uint32_t STPPCLK; + __IO uint32_t GATEHCLK; + uint32_t RESERVED0[30]; +} stc_usbfs_gcctl_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __IO uint32_t SLPOFF; + uint32_t RESERVED1[14]; + __IO uint32_t ITS; +} stc_wdt_cr_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __IO uint32_t UDF; + __IO uint32_t REF; + uint32_t RESERVED1[14]; +} stc_wdt_sr_bit_t; + + +typedef struct { + stc_adc_str_bit_t STR_b; + uint32_t RESERVED0[8]; + stc_adc_cr0_bit_t CR0_b; + stc_adc_cr1_bit_t CR1_b; + uint32_t RESERVED1[32]; + stc_adc_trgsr_bit_t TRGSR_b; + uint32_t RESERVED2[464]; + stc_adc_isr_bit_t ISR_b; + stc_adc_icr_bit_t ICR_b; + uint32_t RESERVED3[32]; + stc_adc_synccr_bit_t SYNCCR_b; + uint32_t RESERVED4[656]; + stc_adc_awdcr_bit_t AWDCR_b; + uint32_t RESERVED5[352]; + stc_adc_pgainsr1_bit_t PGAINSR1_b; +} bCM_ADC_TypeDef; + +typedef struct { + stc_aes_cr_bit_t CR_b; +} bCM_AES_TypeDef; + +typedef struct { + stc_aos_intsfttrg_bit_t INTSFTTRG_b; + uint32_t RESERVED0[2912]; + stc_aos_pevntnfcr_bit_t PEVNTNFCR_b; +} bCM_AOS_TypeDef; + +typedef struct { + uint32_t RESERVED0[1280]; + stc_can_cfg_stat_bit_t CFG_STAT_b; + stc_can_tcmd_bit_t TCMD_b; + stc_can_tctrl_bit_t TCTRL_b; + stc_can_rctrl_bit_t RCTRL_b; + stc_can_rtie_bit_t RTIE_b; + stc_can_rtif_bit_t RTIF_b; + stc_can_errint_bit_t ERRINT_b; + uint32_t RESERVED1[104]; + stc_can_acfctrl_bit_t ACFCTRL_b; + uint32_t RESERVED2[8]; + stc_can_acfen_bit_t ACFEN_b; + uint32_t RESERVED3[8]; + stc_can_acf_bit_t ACF_b; + uint32_t RESERVED4[16]; + stc_can_tbslot_bit_t TBSLOT_b; + stc_can_ttcfg_bit_t TTCFG_b; + stc_can_ref_msg_bit_t REF_MSG_b; +} bCM_CAN_TypeDef; + +typedef struct { + stc_cmp_ctrl_bit_t CTRL_b; + stc_cmp_vltsel_bit_t VLTSEL_b; + stc_cmp_outmon_bit_t OUTMON_b; +} bCM_CMP_TypeDef; + +typedef struct { + uint32_t RESERVED0[2112]; + stc_cmp_common_dacr_bit_t DACR_b; + uint32_t RESERVED1[16]; + stc_cmp_common_rvadc_bit_t RVADC_b; +} bCM_CMP_COMMON_TypeDef; + +typedef struct { + stc_crc_cr_bit_t CR_b; + stc_crc_reslt_bit_t RESLT_b; + uint32_t RESERVED0[32]; + stc_crc_flg_bit_t FLG_b; +} bCM_CRC_TypeDef; + +typedef struct { + uint32_t RESERVED0[224]; + stc_dbgc_mcudbgstat_bit_t MCUDBGSTAT_b; + stc_dbgc_mcustpctl_bit_t MCUSTPCTL_b; + stc_dbgc_mcutracectl_bit_t MCUTRACECTL_b; +} bCM_DBGC_TypeDef; + +typedef struct { + stc_dcu_ctl_bit_t CTL_b; + stc_dcu_flag_bit_t FLAG_b; + uint32_t RESERVED0[96]; + stc_dcu_flagclr_bit_t FLAGCLR_b; + stc_dcu_intevtsel_bit_t INTEVTSEL_b; +} bCM_DCU_TypeDef; + +typedef struct { + stc_dma_en_bit_t EN_b; + stc_dma_intstat0_bit_t INTSTAT0_b; + stc_dma_intstat1_bit_t INTSTAT1_b; + stc_dma_intmask0_bit_t INTMASK0_b; + stc_dma_intmask1_bit_t INTMASK1_b; + stc_dma_intclr0_bit_t INTCLR0_b; + stc_dma_intclr1_bit_t INTCLR1_b; + uint32_t RESERVED0[32]; + stc_dma_reqstat_bit_t REQSTAT_b; + stc_dma_chstat_bit_t CHSTAT_b; + uint32_t RESERVED1[32]; + stc_dma_rcfgctl_bit_t RCFGCTL_b; + stc_dma_swreq_bit_t SWREQ_b; + uint32_t RESERVED2[320]; + stc_dma_chctl_bit_t CHCTL0_b; + uint32_t RESERVED3[480]; + stc_dma_chctl_bit_t CHCTL1_b; + uint32_t RESERVED4[480]; + stc_dma_chctl_bit_t CHCTL2_b; + uint32_t RESERVED5[480]; + stc_dma_chctl_bit_t CHCTL3_b; +} bCM_DMA_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_efm_fstp_bit_t FSTP_b; + stc_efm_frmc_bit_t FRMC_b; + stc_efm_fwmc_bit_t FWMC_b; + stc_efm_fsr_bit_t FSR_b; + stc_efm_fsclr_bit_t FSCLR_b; + stc_efm_fite_bit_t FITE_b; + stc_efm_fswp_bit_t FSWP_b; + uint32_t RESERVED1[1824]; + stc_efm_mmf_remcr_bit_t MMF_REMCR0_b; + stc_efm_mmf_remcr_bit_t MMF_REMCR1_b; +} bCM_EFM_TypeDef; + +typedef struct { + stc_emb_ctl_bit_t CTL_b; + stc_emb_pwmlv_bit_t PWMLV_b; + stc_emb_soe_bit_t SOE_b; + stc_emb_stat_bit_t STAT_b; + stc_emb_statclr_bit_t STATCLR_b; + stc_emb_inten_bit_t INTEN_b; +} bCM_EMB_TypeDef; + +typedef struct { + uint32_t RESERVED0[96]; + stc_fcm_str_bit_t STR_b; + uint32_t RESERVED1[32]; + stc_fcm_rccr_bit_t RCCR_b; + stc_fcm_rier_bit_t RIER_b; + stc_fcm_sr_bit_t SR_b; + stc_fcm_clr_bit_t CLR_b; +} bCM_FCM_TypeDef; + +typedef struct { + stc_gpio_pidr_bit_t PIDRA_b; + uint32_t RESERVED0[16]; + stc_gpio_podr_bit_t PODRA_b; + stc_gpio_poer_bit_t POERA_b; + stc_gpio_posr_bit_t POSRA_b; + stc_gpio_porr_bit_t PORRA_b; + stc_gpio_potr_bit_t POTRA_b; + uint32_t RESERVED1[16]; + stc_gpio_pidr_bit_t PIDRB_b; + uint32_t RESERVED2[16]; + stc_gpio_podr_bit_t PODRB_b; + stc_gpio_poer_bit_t POERB_b; + stc_gpio_posr_bit_t POSRB_b; + stc_gpio_porr_bit_t PORRB_b; + stc_gpio_potr_bit_t POTRB_b; + uint32_t RESERVED3[16]; + stc_gpio_pidr_bit_t PIDRC_b; + uint32_t RESERVED4[16]; + stc_gpio_podr_bit_t PODRC_b; + stc_gpio_poer_bit_t POERC_b; + stc_gpio_posr_bit_t POSRC_b; + stc_gpio_porr_bit_t PORRC_b; + stc_gpio_potr_bit_t POTRC_b; + uint32_t RESERVED5[16]; + stc_gpio_pidr_bit_t PIDRD_b; + uint32_t RESERVED6[16]; + stc_gpio_podr_bit_t PODRD_b; + stc_gpio_poer_bit_t POERD_b; + stc_gpio_posr_bit_t POSRD_b; + stc_gpio_porr_bit_t PORRD_b; + stc_gpio_potr_bit_t POTRD_b; + uint32_t RESERVED7[16]; + stc_gpio_pidr_bit_t PIDRE_b; + uint32_t RESERVED8[16]; + stc_gpio_podr_bit_t PODRE_b; + stc_gpio_poer_bit_t POERE_b; + stc_gpio_posr_bit_t POSRE_b; + stc_gpio_porr_bit_t PORRE_b; + stc_gpio_potr_bit_t POTRE_b; + uint32_t RESERVED9[16]; + stc_gpio_pidrh_bit_t PIDRH_b; + uint32_t RESERVED10[16]; + stc_gpio_podrh_bit_t PODRH_b; + stc_gpio_poerh_bit_t POERH_b; + stc_gpio_posrh_bit_t POSRH_b; + stc_gpio_porrh_bit_t PORRH_b; + stc_gpio_potrh_bit_t POTRH_b; + uint32_t RESERVED11[7408]; + stc_gpio_pwpr_bit_t PWPR_b; + uint32_t RESERVED12[16]; + stc_gpio_pcr_bit_t PCRA0_b; + stc_gpio_pfsr_bit_t PFSRA0_b; + stc_gpio_pcr_bit_t PCRA1_b; + stc_gpio_pfsr_bit_t PFSRA1_b; + stc_gpio_pcr_bit_t PCRA2_b; + stc_gpio_pfsr_bit_t PFSRA2_b; + stc_gpio_pcr_bit_t PCRA3_b; + stc_gpio_pfsr_bit_t PFSRA3_b; + stc_gpio_pcr_bit_t PCRA4_b; + stc_gpio_pfsr_bit_t PFSRA4_b; + stc_gpio_pcr_bit_t PCRA5_b; + stc_gpio_pfsr_bit_t PFSRA5_b; + stc_gpio_pcr_bit_t PCRA6_b; + stc_gpio_pfsr_bit_t PFSRA6_b; + stc_gpio_pcr_bit_t PCRA7_b; + stc_gpio_pfsr_bit_t PFSRA7_b; + stc_gpio_pcr_bit_t PCRA8_b; + stc_gpio_pfsr_bit_t PFSRA8_b; + stc_gpio_pcr_bit_t PCRA9_b; + stc_gpio_pfsr_bit_t PFSRA9_b; + stc_gpio_pcr_bit_t PCRA10_b; + stc_gpio_pfsr_bit_t PFSRA10_b; + stc_gpio_pcr_bit_t PCRA11_b; + stc_gpio_pfsr_bit_t PFSRA11_b; + stc_gpio_pcr_bit_t PCRA12_b; + stc_gpio_pfsr_bit_t PFSRA12_b; + stc_gpio_pcr_bit_t PCRA13_b; + stc_gpio_pfsr_bit_t PFSRA13_b; + stc_gpio_pcr_bit_t PCRA14_b; + stc_gpio_pfsr_bit_t PFSRA14_b; + stc_gpio_pcr_bit_t PCRA15_b; + stc_gpio_pfsr_bit_t PFSRA15_b; + stc_gpio_pcr_bit_t PCRB0_b; + stc_gpio_pfsr_bit_t PFSRB0_b; + stc_gpio_pcr_bit_t PCRB1_b; + stc_gpio_pfsr_bit_t PFSRB1_b; + stc_gpio_pcr_bit_t PCRB2_b; + stc_gpio_pfsr_bit_t PFSRB2_b; + stc_gpio_pcr_bit_t PCRB3_b; + stc_gpio_pfsr_bit_t PFSRB3_b; + stc_gpio_pcr_bit_t PCRB4_b; + stc_gpio_pfsr_bit_t PFSRB4_b; + stc_gpio_pcr_bit_t PCRB5_b; + stc_gpio_pfsr_bit_t PFSRB5_b; + stc_gpio_pcr_bit_t PCRB6_b; + stc_gpio_pfsr_bit_t PFSRB6_b; + stc_gpio_pcr_bit_t PCRB7_b; + stc_gpio_pfsr_bit_t PFSRB7_b; + stc_gpio_pcr_bit_t PCRB8_b; + stc_gpio_pfsr_bit_t PFSRB8_b; + stc_gpio_pcr_bit_t PCRB9_b; + stc_gpio_pfsr_bit_t PFSRB9_b; + stc_gpio_pcr_bit_t PCRB10_b; + stc_gpio_pfsr_bit_t PFSRB10_b; + stc_gpio_pcr_bit_t PCRB11_b; + stc_gpio_pfsr_bit_t PFSRB11_b; + stc_gpio_pcr_bit_t PCRB12_b; + stc_gpio_pfsr_bit_t PFSRB12_b; + stc_gpio_pcr_bit_t PCRB13_b; + stc_gpio_pfsr_bit_t PFSRB13_b; + stc_gpio_pcr_bit_t PCRB14_b; + stc_gpio_pfsr_bit_t PFSRB14_b; + stc_gpio_pcr_bit_t PCRB15_b; + stc_gpio_pfsr_bit_t PFSRB15_b; + stc_gpio_pcr_bit_t PCRC0_b; + stc_gpio_pfsr_bit_t PFSRC0_b; + stc_gpio_pcr_bit_t PCRC1_b; + stc_gpio_pfsr_bit_t PFSRC1_b; + stc_gpio_pcr_bit_t PCRC2_b; + stc_gpio_pfsr_bit_t PFSRC2_b; + stc_gpio_pcr_bit_t PCRC3_b; + stc_gpio_pfsr_bit_t PFSRC3_b; + stc_gpio_pcr_bit_t PCRC4_b; + stc_gpio_pfsr_bit_t PFSRC4_b; + stc_gpio_pcr_bit_t PCRC5_b; + stc_gpio_pfsr_bit_t PFSRC5_b; + stc_gpio_pcr_bit_t PCRC6_b; + stc_gpio_pfsr_bit_t PFSRC6_b; + stc_gpio_pcr_bit_t PCRC7_b; + stc_gpio_pfsr_bit_t PFSRC7_b; + stc_gpio_pcr_bit_t PCRC8_b; + stc_gpio_pfsr_bit_t PFSRC8_b; + stc_gpio_pcr_bit_t PCRC9_b; + stc_gpio_pfsr_bit_t PFSRC9_b; + stc_gpio_pcr_bit_t PCRC10_b; + stc_gpio_pfsr_bit_t PFSRC10_b; + stc_gpio_pcr_bit_t PCRC11_b; + stc_gpio_pfsr_bit_t PFSRC11_b; + stc_gpio_pcr_bit_t PCRC12_b; + stc_gpio_pfsr_bit_t PFSRC12_b; + stc_gpio_pcr_bit_t PCRC13_b; + stc_gpio_pfsr_bit_t PFSRC13_b; + stc_gpio_pcr_bit_t PCRC14_b; + stc_gpio_pfsr_bit_t PFSRC14_b; + stc_gpio_pcr_bit_t PCRC15_b; + stc_gpio_pfsr_bit_t PFSRC15_b; + stc_gpio_pcr_bit_t PCRD0_b; + stc_gpio_pfsr_bit_t PFSRD0_b; + stc_gpio_pcr_bit_t PCRD1_b; + stc_gpio_pfsr_bit_t PFSRD1_b; + stc_gpio_pcr_bit_t PCRD2_b; + stc_gpio_pfsr_bit_t PFSRD2_b; + stc_gpio_pcr_bit_t PCRD3_b; + stc_gpio_pfsr_bit_t PFSRD3_b; + stc_gpio_pcr_bit_t PCRD4_b; + stc_gpio_pfsr_bit_t PFSRD4_b; + stc_gpio_pcr_bit_t PCRD5_b; + stc_gpio_pfsr_bit_t PFSRD5_b; + stc_gpio_pcr_bit_t PCRD6_b; + stc_gpio_pfsr_bit_t PFSRD6_b; + stc_gpio_pcr_bit_t PCRD7_b; + stc_gpio_pfsr_bit_t PFSRD7_b; + stc_gpio_pcr_bit_t PCRD8_b; + stc_gpio_pfsr_bit_t PFSRD8_b; + stc_gpio_pcr_bit_t PCRD9_b; + stc_gpio_pfsr_bit_t PFSRD9_b; + stc_gpio_pcr_bit_t PCRD10_b; + stc_gpio_pfsr_bit_t PFSRD10_b; + stc_gpio_pcr_bit_t PCRD11_b; + stc_gpio_pfsr_bit_t PFSRD11_b; + stc_gpio_pcr_bit_t PCRD12_b; + stc_gpio_pfsr_bit_t PFSRD12_b; + stc_gpio_pcr_bit_t PCRD13_b; + stc_gpio_pfsr_bit_t PFSRD13_b; + stc_gpio_pcr_bit_t PCRD14_b; + stc_gpio_pfsr_bit_t PFSRD14_b; + stc_gpio_pcr_bit_t PCRD15_b; + stc_gpio_pfsr_bit_t PFSRD15_b; + stc_gpio_pcr_bit_t PCRE0_b; + stc_gpio_pfsr_bit_t PFSRE0_b; + stc_gpio_pcr_bit_t PCRE1_b; + stc_gpio_pfsr_bit_t PFSRE1_b; + stc_gpio_pcr_bit_t PCRE2_b; + stc_gpio_pfsr_bit_t PFSRE2_b; + stc_gpio_pcr_bit_t PCRE3_b; + stc_gpio_pfsr_bit_t PFSRE3_b; + stc_gpio_pcr_bit_t PCRE4_b; + stc_gpio_pfsr_bit_t PFSRE4_b; + stc_gpio_pcr_bit_t PCRE5_b; + stc_gpio_pfsr_bit_t PFSRE5_b; + stc_gpio_pcr_bit_t PCRE6_b; + stc_gpio_pfsr_bit_t PFSRE6_b; + stc_gpio_pcr_bit_t PCRE7_b; + stc_gpio_pfsr_bit_t PFSRE7_b; + stc_gpio_pcr_bit_t PCRE8_b; + stc_gpio_pfsr_bit_t PFSRE8_b; + stc_gpio_pcr_bit_t PCRE9_b; + stc_gpio_pfsr_bit_t PFSRE9_b; + stc_gpio_pcr_bit_t PCRE10_b; + stc_gpio_pfsr_bit_t PFSRE10_b; + stc_gpio_pcr_bit_t PCRE11_b; + stc_gpio_pfsr_bit_t PFSRE11_b; + stc_gpio_pcr_bit_t PCRE12_b; + stc_gpio_pfsr_bit_t PFSRE12_b; + stc_gpio_pcr_bit_t PCRE13_b; + stc_gpio_pfsr_bit_t PFSRE13_b; + stc_gpio_pcr_bit_t PCRE14_b; + stc_gpio_pfsr_bit_t PFSRE14_b; + stc_gpio_pcr_bit_t PCRE15_b; + stc_gpio_pfsr_bit_t PFSRE15_b; + stc_gpio_pcr_bit_t PCRH0_b; + stc_gpio_pfsr_bit_t PFSRH0_b; + stc_gpio_pcr_bit_t PCRH1_b; + stc_gpio_pfsr_bit_t PFSRH1_b; + stc_gpio_pcr_bit_t PCRH2_b; + stc_gpio_pfsr_bit_t PFSRH2_b; +} bCM_GPIO_TypeDef; + +typedef struct { + stc_hash_cr_bit_t CR_b; +} bCM_HASH_TypeDef; + +typedef struct { + stc_i2c_cr1_bit_t CR1_b; + stc_i2c_cr2_bit_t CR2_b; + stc_i2c_cr3_bit_t CR3_b; + stc_i2c_cr4_bit_t CR4_b; + stc_i2c_slr0_bit_t SLR0_b; + stc_i2c_slr1_bit_t SLR1_b; + uint32_t RESERVED0[32]; + stc_i2c_sr_bit_t SR_b; + stc_i2c_clr_bit_t CLR_b; + uint32_t RESERVED1[96]; + stc_i2c_fltr_bit_t FLTR_b; +} bCM_I2C_TypeDef; + +typedef struct { + stc_i2s_ctrl_bit_t CTRL_b; + stc_i2s_sr_bit_t SR_b; + stc_i2s_er_bit_t ER_b; + stc_i2s_cfgr_bit_t CFGR_b; +} bCM_I2S_TypeDef; + +typedef struct { + stc_icg_icg0_bit_t ICG0_b; + stc_icg_icg1_bit_t ICG1_b; +} bCM_ICG_TypeDef; + +typedef struct { + stc_intc_nmicr_bit_t NMICR_b; + stc_intc_nmienr_bit_t NMIENR_b; + stc_intc_nmifr_bit_t NMIFR_b; + stc_intc_nmicfr_bit_t NMICFR_b; + stc_intc_eirqcr_bit_t EIRQCR0_b; + stc_intc_eirqcr_bit_t EIRQCR1_b; + stc_intc_eirqcr_bit_t EIRQCR2_b; + stc_intc_eirqcr_bit_t EIRQCR3_b; + stc_intc_eirqcr_bit_t EIRQCR4_b; + stc_intc_eirqcr_bit_t EIRQCR5_b; + stc_intc_eirqcr_bit_t EIRQCR6_b; + stc_intc_eirqcr_bit_t EIRQCR7_b; + stc_intc_eirqcr_bit_t EIRQCR8_b; + stc_intc_eirqcr_bit_t EIRQCR9_b; + stc_intc_eirqcr_bit_t EIRQCR10_b; + stc_intc_eirqcr_bit_t EIRQCR11_b; + stc_intc_eirqcr_bit_t EIRQCR12_b; + stc_intc_eirqcr_bit_t EIRQCR13_b; + stc_intc_eirqcr_bit_t EIRQCR14_b; + stc_intc_eirqcr_bit_t EIRQCR15_b; + stc_intc_wupen_bit_t WUPEN_b; + stc_intc_eifr_bit_t EIFR_b; + stc_intc_eifcr_bit_t EIFCR_b; + uint32_t RESERVED0[4096]; + stc_intc_vssel_bit_t VSSEL128_b; + stc_intc_vssel_bit_t VSSEL129_b; + stc_intc_vssel_bit_t VSSEL130_b; + stc_intc_vssel_bit_t VSSEL131_b; + stc_intc_vssel_bit_t VSSEL132_b; + stc_intc_vssel_bit_t VSSEL133_b; + stc_intc_vssel_bit_t VSSEL134_b; + stc_intc_vssel_bit_t VSSEL135_b; + stc_intc_vssel_bit_t VSSEL136_b; + stc_intc_vssel_bit_t VSSEL137_b; + stc_intc_vssel_bit_t VSSEL138_b; + stc_intc_vssel_bit_t VSSEL139_b; + stc_intc_vssel_bit_t VSSEL140_b; + stc_intc_vssel_bit_t VSSEL141_b; + stc_intc_vssel_bit_t VSSEL142_b; + stc_intc_vssel_bit_t VSSEL143_b; + stc_intc_swier_bit_t SWIER_b; + stc_intc_evter_bit_t EVTER_b; + stc_intc_ier_bit_t IER_b; +} bCM_INTC_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_keyscan_ser_bit_t SER_b; +} bCM_KEYSCAN_TypeDef; + +typedef struct { + uint32_t RESERVED0[512]; + stc_mpu_rgcr_bit_t RGCR0_b; + stc_mpu_rgcr_bit_t RGCR1_b; + stc_mpu_rgcr_bit_t RGCR2_b; + stc_mpu_rgcr_bit_t RGCR3_b; + stc_mpu_rgcr_bit_t RGCR4_b; + stc_mpu_rgcr_bit_t RGCR5_b; + stc_mpu_rgcr_bit_t RGCR6_b; + stc_mpu_rgcr_bit_t RGCR7_b; + stc_mpu_rgcr_bit_t RGCR8_b; + stc_mpu_rgcr_bit_t RGCR9_b; + stc_mpu_rgcr_bit_t RGCR10_b; + stc_mpu_rgcr_bit_t RGCR11_b; + stc_mpu_rgcr_bit_t RGCR12_b; + stc_mpu_rgcr_bit_t RGCR13_b; + stc_mpu_rgcr_bit_t RGCR14_b; + stc_mpu_rgcr_bit_t RGCR15_b; + stc_mpu_cr_bit_t CR_b; + stc_mpu_sr_bit_t SR_b; + stc_mpu_eclr_bit_t ECLR_b; + stc_mpu_wp_bit_t WP_b; + uint32_t RESERVED1[130144]; + stc_mpu_ippr_bit_t IPPR_b; +} bCM_MPU_TypeDef; + +typedef struct { + stc_ots_ctl_bit_t CTL_b; +} bCM_OTS_TypeDef; + +typedef struct { + stc_peric_usbfs_syctlreg_bit_t USBFS_SYCTLREG_b; + stc_peric_sdioc_syctlreg_bit_t SDIOC_SYCTLREG_b; +} bCM_PERIC_TypeDef; + +typedef struct { + stc_qspi_cr_bit_t CR_b; + uint32_t RESERVED0[32]; + stc_qspi_fcr_bit_t FCR_b; + stc_qspi_sr_bit_t SR_b; + uint32_t RESERVED1[160]; + stc_qspi_clr_bit_t CLR_b; +} bCM_QSPI_TypeDef; + +typedef struct { + stc_rmu_rstf0_bit_t RSTF0_b; +} bCM_RMU_TypeDef; + +typedef struct { + stc_rtc_cr0_bit_t CR0_b; + uint32_t RESERVED0[24]; + stc_rtc_cr1_bit_t CR1_b; + uint32_t RESERVED1[24]; + stc_rtc_cr2_bit_t CR2_b; + uint32_t RESERVED2[24]; + stc_rtc_cr3_bit_t CR3_b; + uint32_t RESERVED3[344]; + stc_rtc_errcrh_bit_t ERRCRH_b; +} bCM_RTC_TypeDef; + +typedef struct { + uint32_t RESERVED0[96]; + stc_sdioc_transmode_bit_t TRANSMODE_b; + stc_sdioc_cmd_bit_t CMD_b; + uint32_t RESERVED1[160]; + stc_sdioc_pstat_bit_t PSTAT_b; + stc_sdioc_hostcon_bit_t HOSTCON_b; + stc_sdioc_pwrcon_bit_t PWRCON_b; + stc_sdioc_blkgpcon_bit_t BLKGPCON_b; + uint32_t RESERVED2[8]; + stc_sdioc_clkcon_bit_t CLKCON_b; + uint32_t RESERVED3[8]; + stc_sdioc_sftrst_bit_t SFTRST_b; + stc_sdioc_norintst_bit_t NORINTST_b; + stc_sdioc_errintst_bit_t ERRINTST_b; + stc_sdioc_norintsten_bit_t NORINTSTEN_b; + stc_sdioc_errintsten_bit_t ERRINTSTEN_b; + stc_sdioc_norintsgen_bit_t NORINTSGEN_b; + stc_sdioc_errintsgen_bit_t ERRINTSGEN_b; + stc_sdioc_atcerrst_bit_t ATCERRST_b; + uint32_t RESERVED4[144]; + stc_sdioc_fea_bit_t FEA_b; + stc_sdioc_fee_bit_t FEE_b; +} bCM_SDIOC_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_spi_cr1_bit_t CR1_b; + uint32_t RESERVED1[32]; + stc_spi_cfg1_bit_t CFG1_b; + uint32_t RESERVED2[32]; + stc_spi_sr_bit_t SR_b; + stc_spi_cfg2_bit_t CFG2_b; +} bCM_SPI_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_sramc_wtpr_bit_t WTPR_b; + stc_sramc_ckcr_bit_t CKCR_b; + stc_sramc_ckpr_bit_t CKPR_b; + stc_sramc_cksr_bit_t CKSR_b; +} bCM_SRAMC_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_swdt_sr_bit_t SR_b; +} bCM_SWDT_TypeDef; + +typedef struct { + uint32_t RESERVED0[128]; + stc_tmr0_bconr_bit_t BCONR_b; + stc_tmr0_stflr_bit_t STFLR_b; +} bCM_TMR0_TypeDef; + +typedef struct { + uint32_t RESERVED0[192]; + stc_tmr4_ocsr_bit_t OCSRU_b; + stc_tmr4_ocer_bit_t OCERU_b; + stc_tmr4_ocsr_bit_t OCSRV_b; + stc_tmr4_ocer_bit_t OCERV_b; + stc_tmr4_ocsr_bit_t OCSRW_b; + stc_tmr4_ocer_bit_t OCERW_b; + stc_tmr4_ocmrh_bit_t OCMRUH_b; + uint32_t RESERVED1[16]; + stc_tmr4_ocmrl_bit_t OCMRUL_b; + stc_tmr4_ocmrh_bit_t OCMRVH_b; + uint32_t RESERVED2[16]; + stc_tmr4_ocmrl_bit_t OCMRVL_b; + stc_tmr4_ocmrh_bit_t OCMRWH_b; + uint32_t RESERVED3[16]; + stc_tmr4_ocmrl_bit_t OCMRWL_b; + uint32_t RESERVED4[96]; + stc_tmr4_ccsr_bit_t CCSR_b; + uint32_t RESERVED5[720]; + stc_tmr4_rcsr_bit_t RCSR_b; + uint32_t RESERVED6[272]; + stc_tmr4_scsr_bit_t SCSRUH_b; + stc_tmr4_scmr_bit_t SCMRUH_b; + stc_tmr4_scsr_bit_t SCSRUL_b; + stc_tmr4_scmr_bit_t SCMRUL_b; + stc_tmr4_scsr_bit_t SCSRVH_b; + stc_tmr4_scmr_bit_t SCMRVH_b; + stc_tmr4_scsr_bit_t SCSRVL_b; + stc_tmr4_scmr_bit_t SCMRVL_b; + stc_tmr4_scsr_bit_t SCSRWH_b; + stc_tmr4_scmr_bit_t SCMRWH_b; + stc_tmr4_scsr_bit_t SCSRWL_b; + stc_tmr4_scmr_bit_t SCMRWL_b; + uint32_t RESERVED7[128]; + stc_tmr4_ecsr_bit_t ECSR_b; +} bCM_TMR4_TypeDef; + +typedef struct { + uint32_t RESERVED0[640]; + stc_tmr6_gconr_bit_t GCONR_b; + stc_tmr6_iconr_bit_t ICONR_b; + stc_tmr6_pconr_bit_t PCONR_b; + stc_tmr6_bconr_bit_t BCONR_b; + stc_tmr6_dconr_bit_t DCONR_b; + uint32_t RESERVED1[32]; + stc_tmr6_fconr_bit_t FCONR_b; + stc_tmr6_vperr_bit_t VPERR_b; + stc_tmr6_stflr_bit_t STFLR_b; + stc_tmr6_hstar_bit_t HSTAR_b; + stc_tmr6_hstpr_bit_t HSTPR_b; + stc_tmr6_hclrr_bit_t HCLRR_b; + stc_tmr6_hcpar_bit_t HCPAR_b; + stc_tmr6_hcpbr_bit_t HCPBR_b; + stc_tmr6_hcupr_bit_t HCUPR_b; + stc_tmr6_hcdor_bit_t HCDOR_b; +} bCM_TMR6_TypeDef; + +typedef struct { + uint32_t RESERVED0[1952]; + stc_tmr6_common_sstar_bit_t SSTAR_b; + stc_tmr6_common_sstpr_bit_t SSTPR_b; + stc_tmr6_common_sclrr_bit_t SCLRR_b; +} bCM_TMR6_COMMON_TypeDef; + +typedef struct { + uint32_t RESERVED0[1024]; + stc_tmra_bcstrl_bit_t BCSTRL_b; + stc_tmra_bcstrh_bit_t BCSTRH_b; + uint32_t RESERVED1[16]; + stc_tmra_hconr_bit_t HCONR_b; + uint32_t RESERVED2[16]; + stc_tmra_hcupr_bit_t HCUPR_b; + uint32_t RESERVED3[16]; + stc_tmra_hcdor_bit_t HCDOR_b; + uint32_t RESERVED4[16]; + stc_tmra_iconr_bit_t ICONR_b; + uint32_t RESERVED5[16]; + stc_tmra_econr_bit_t ECONR_b; + uint32_t RESERVED6[16]; + stc_tmra_fconr_bit_t FCONR_b; + uint32_t RESERVED7[16]; + stc_tmra_stflr_bit_t STFLR_b; + uint32_t RESERVED8[272]; + stc_tmra_bconr_bit_t BCONR1_b; + uint32_t RESERVED9[48]; + stc_tmra_bconr_bit_t BCONR2_b; + uint32_t RESERVED10[48]; + stc_tmra_bconr_bit_t BCONR3_b; + uint32_t RESERVED11[48]; + stc_tmra_bconr_bit_t BCONR4_b; + uint32_t RESERVED12[304]; + stc_tmra_cconr_bit_t CCONR1_b; + uint32_t RESERVED13[16]; + stc_tmra_cconr_bit_t CCONR2_b; + uint32_t RESERVED14[16]; + stc_tmra_cconr_bit_t CCONR3_b; + uint32_t RESERVED15[16]; + stc_tmra_cconr_bit_t CCONR4_b; + uint32_t RESERVED16[16]; + stc_tmra_cconr_bit_t CCONR5_b; + uint32_t RESERVED17[16]; + stc_tmra_cconr_bit_t CCONR6_b; + uint32_t RESERVED18[16]; + stc_tmra_cconr_bit_t CCONR7_b; + uint32_t RESERVED19[16]; + stc_tmra_cconr_bit_t CCONR8_b; + uint32_t RESERVED20[272]; + stc_tmra_pconr_bit_t PCONR1_b; + uint32_t RESERVED21[16]; + stc_tmra_pconr_bit_t PCONR2_b; + uint32_t RESERVED22[16]; + stc_tmra_pconr_bit_t PCONR3_b; + uint32_t RESERVED23[16]; + stc_tmra_pconr_bit_t PCONR4_b; + uint32_t RESERVED24[16]; + stc_tmra_pconr_bit_t PCONR5_b; + uint32_t RESERVED25[16]; + stc_tmra_pconr_bit_t PCONR6_b; + uint32_t RESERVED26[16]; + stc_tmra_pconr_bit_t PCONR7_b; + uint32_t RESERVED27[16]; + stc_tmra_pconr_bit_t PCONR8_b; +} bCM_TMRA_TypeDef; + +typedef struct { + stc_trng_cr_bit_t CR_b; + stc_trng_mr_bit_t MR_b; +} bCM_TRNG_TypeDef; + +typedef struct { + stc_usart_sr_bit_t SR_b; + stc_usart_tdr_bit_t TDR_b; + uint32_t RESERVED0[48]; + stc_usart_cr1_bit_t CR1_b; + stc_usart_cr2_bit_t CR2_b; + stc_usart_cr3_bit_t CR3_b; +} bCM_USART_TypeDef; + +typedef struct { + stc_usbfs_gvbuscfg_bit_t GVBUSCFG_b; + uint32_t RESERVED0[32]; + stc_usbfs_gahbcfg_bit_t GAHBCFG_b; + stc_usbfs_gusbcfg_bit_t GUSBCFG_b; + stc_usbfs_grstctl_bit_t GRSTCTL_b; + stc_usbfs_gintsts_bit_t GINTSTS_b; + stc_usbfs_gintmsk_bit_t GINTMSK_b; + uint32_t RESERVED1[7968]; + stc_usbfs_hcfg_bit_t HCFG_b; + uint32_t RESERVED2[480]; + stc_usbfs_hprt_bit_t HPRT_b; + uint32_t RESERVED3[1504]; + stc_usbfs_hcchar_bit_t HCCHAR0_b; + uint32_t RESERVED4[32]; + stc_usbfs_hcint_bit_t HCINT0_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK0_b; + uint32_t RESERVED5[128]; + stc_usbfs_hcchar_bit_t HCCHAR1_b; + uint32_t RESERVED6[32]; + stc_usbfs_hcint_bit_t HCINT1_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK1_b; + uint32_t RESERVED7[128]; + stc_usbfs_hcchar_bit_t HCCHAR2_b; + uint32_t RESERVED8[32]; + stc_usbfs_hcint_bit_t HCINT2_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK2_b; + uint32_t RESERVED9[128]; + stc_usbfs_hcchar_bit_t HCCHAR3_b; + uint32_t RESERVED10[32]; + stc_usbfs_hcint_bit_t HCINT3_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK3_b; + uint32_t RESERVED11[128]; + stc_usbfs_hcchar_bit_t HCCHAR4_b; + uint32_t RESERVED12[32]; + stc_usbfs_hcint_bit_t HCINT4_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK4_b; + uint32_t RESERVED13[128]; + stc_usbfs_hcchar_bit_t HCCHAR5_b; + uint32_t RESERVED14[32]; + stc_usbfs_hcint_bit_t HCINT5_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK5_b; + uint32_t RESERVED15[128]; + stc_usbfs_hcchar_bit_t HCCHAR6_b; + uint32_t RESERVED16[32]; + stc_usbfs_hcint_bit_t HCINT6_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK6_b; + uint32_t RESERVED17[128]; + stc_usbfs_hcchar_bit_t HCCHAR7_b; + uint32_t RESERVED18[32]; + stc_usbfs_hcint_bit_t HCINT7_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK7_b; + uint32_t RESERVED19[128]; + stc_usbfs_hcchar_bit_t HCCHAR8_b; + uint32_t RESERVED20[32]; + stc_usbfs_hcint_bit_t HCINT8_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK8_b; + uint32_t RESERVED21[128]; + stc_usbfs_hcchar_bit_t HCCHAR9_b; + uint32_t RESERVED22[32]; + stc_usbfs_hcint_bit_t HCINT9_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK9_b; + uint32_t RESERVED23[128]; + stc_usbfs_hcchar_bit_t HCCHAR10_b; + uint32_t RESERVED24[32]; + stc_usbfs_hcint_bit_t HCINT10_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK10_b; + uint32_t RESERVED25[128]; + stc_usbfs_hcchar_bit_t HCCHAR11_b; + uint32_t RESERVED26[32]; + stc_usbfs_hcint_bit_t HCINT11_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK11_b; + uint32_t RESERVED27[3200]; + stc_usbfs_dcfg_bit_t DCFG_b; + stc_usbfs_dctl_bit_t DCTL_b; + stc_usbfs_dsts_bit_t DSTS_b; + uint32_t RESERVED28[32]; + stc_usbfs_diepmsk_bit_t DIEPMSK_b; + stc_usbfs_doepmsk_bit_t DOEPMSK_b; + uint32_t RESERVED29[1856]; + stc_usbfs_diepctl0_bit_t DIEPCTL0_b; + uint32_t RESERVED30[32]; + stc_usbfs_diepint_bit_t DIEPINT0_b; + uint32_t RESERVED31[160]; + stc_usbfs_diepctl_bit_t DIEPCTL1_b; + uint32_t RESERVED32[32]; + stc_usbfs_diepint_bit_t DIEPINT1_b; + uint32_t RESERVED33[160]; + stc_usbfs_diepctl_bit_t DIEPCTL2_b; + uint32_t RESERVED34[32]; + stc_usbfs_diepint_bit_t DIEPINT2_b; + uint32_t RESERVED35[160]; + stc_usbfs_diepctl_bit_t DIEPCTL3_b; + uint32_t RESERVED36[32]; + stc_usbfs_diepint_bit_t DIEPINT3_b; + uint32_t RESERVED37[160]; + stc_usbfs_diepctl_bit_t DIEPCTL4_b; + uint32_t RESERVED38[32]; + stc_usbfs_diepint_bit_t DIEPINT4_b; + uint32_t RESERVED39[160]; + stc_usbfs_diepctl_bit_t DIEPCTL5_b; + uint32_t RESERVED40[32]; + stc_usbfs_diepint_bit_t DIEPINT5_b; + uint32_t RESERVED41[2720]; + stc_usbfs_doepctl0_bit_t DOEPCTL0_b; + uint32_t RESERVED42[32]; + stc_usbfs_doepint_bit_t DOEPINT0_b; + uint32_t RESERVED43[32]; + stc_usbfs_doeptsiz0_bit_t DOEPTSIZ0_b; + uint32_t RESERVED44[96]; + stc_usbfs_doepctl_bit_t DOEPCTL1_b; + uint32_t RESERVED45[32]; + stc_usbfs_doepint_bit_t DOEPINT1_b; + uint32_t RESERVED46[160]; + stc_usbfs_doepctl_bit_t DOEPCTL2_b; + uint32_t RESERVED47[32]; + stc_usbfs_doepint_bit_t DOEPINT2_b; + uint32_t RESERVED48[160]; + stc_usbfs_doepctl_bit_t DOEPCTL3_b; + uint32_t RESERVED49[32]; + stc_usbfs_doepint_bit_t DOEPINT3_b; + uint32_t RESERVED50[160]; + stc_usbfs_doepctl_bit_t DOEPCTL4_b; + uint32_t RESERVED51[32]; + stc_usbfs_doepint_bit_t DOEPINT4_b; + uint32_t RESERVED52[160]; + stc_usbfs_doepctl_bit_t DOEPCTL5_b; + uint32_t RESERVED53[32]; + stc_usbfs_doepint_bit_t DOEPINT5_b; + uint32_t RESERVED54[4768]; + stc_usbfs_gcctl_bit_t GCCTL_b; +} bCM_USBFS_TypeDef; + +typedef struct { + stc_wdt_cr_bit_t CR_b; + stc_wdt_sr_bit_t SR_b; +} bCM_WDT_TypeDef; + + +/******************************************************************************/ +/* Device Specific Peripheral bit_band declaration & memory map */ +/******************************************************************************/ +#define bCM_ADC1 ((bCM_ADC_TypeDef *)0x42800000UL) +#define bCM_ADC2 ((bCM_ADC_TypeDef *)0x42808000UL) +#define bCM_AES ((bCM_AES_TypeDef *)0x42100000UL) +#define bCM_AOS ((bCM_AOS_TypeDef *)0x42210000UL) +#define bCM_CAN ((bCM_CAN_TypeDef *)0x42E08000UL) +#define bCM_CMP1 ((bCM_CMP_TypeDef *)0x42940000UL) +#define bCM_CMP2 ((bCM_CMP_TypeDef *)0x42940200UL) +#define bCM_CMP3 ((bCM_CMP_TypeDef *)0x42940400UL) +#define bCM_CMP_COMMON ((bCM_CMP_COMMON_TypeDef *)0x42940000UL) +#define bCM_CRC ((bCM_CRC_TypeDef *)0x42118000UL) +#define bCM_DCU1 ((bCM_DCU_TypeDef *)0x42A40000UL) +#define bCM_DCU2 ((bCM_DCU_TypeDef *)0x42A48000UL) +#define bCM_DCU3 ((bCM_DCU_TypeDef *)0x42A50000UL) +#define bCM_DCU4 ((bCM_DCU_TypeDef *)0x42A58000UL) +#define bCM_DMA1 ((bCM_DMA_TypeDef *)0x42A60000UL) +#define bCM_DMA2 ((bCM_DMA_TypeDef *)0x42A68000UL) +#define bCM_EFM ((bCM_EFM_TypeDef *)0x42208000UL) +#define bCM_EMB0 ((bCM_EMB_TypeDef *)0x422F8000UL) +#define bCM_EMB1 ((bCM_EMB_TypeDef *)0x422F8400UL) +#define bCM_EMB2 ((bCM_EMB_TypeDef *)0x422F8800UL) +#define bCM_EMB3 ((bCM_EMB_TypeDef *)0x422F8C00UL) +#define bCM_FCM ((bCM_FCM_TypeDef *)0x42908000UL) +#define bCM_GPIO ((bCM_GPIO_TypeDef *)0x42A70000UL) +#define bCM_HASH ((bCM_HASH_TypeDef *)0x42108000UL) +#define bCM_I2C1 ((bCM_I2C_TypeDef *)0x429C0000UL) +#define bCM_I2C2 ((bCM_I2C_TypeDef *)0x429C8000UL) +#define bCM_I2C3 ((bCM_I2C_TypeDef *)0x429D0000UL) +#define bCM_I2S1 ((bCM_I2S_TypeDef *)0x423C0000UL) +#define bCM_I2S2 ((bCM_I2S_TypeDef *)0x423C8000UL) +#define bCM_I2S3 ((bCM_I2S_TypeDef *)0x42440000UL) +#define bCM_I2S4 ((bCM_I2S_TypeDef *)0x42448000UL) +#define bCM_INTC ((bCM_INTC_TypeDef *)0x42A20000UL) +#define bCM_KEYSCAN ((bCM_KEYSCAN_TypeDef *)0x42A18000UL) +#define bCM_MPU ((bCM_MPU_TypeDef *)0x42A00000UL) +#define bCM_OTS ((bCM_OTS_TypeDef *)0x42948000UL) +#define bCM_PERIC ((bCM_PERIC_TypeDef *)0x42AA8000UL) +#define bCM_RMU ((bCM_RMU_TypeDef *)0x42A81800UL) +#define bCM_RTC ((bCM_RTC_TypeDef *)0x42980000UL) +#define bCM_SDIOC1 ((bCM_SDIOC_TypeDef *)0x42DF8000UL) +#define bCM_SDIOC2 ((bCM_SDIOC_TypeDef *)0x42E00000UL) +#define bCM_SPI1 ((bCM_SPI_TypeDef *)0x42380000UL) +#define bCM_SPI2 ((bCM_SPI_TypeDef *)0x42388000UL) +#define bCM_SPI3 ((bCM_SPI_TypeDef *)0x42400000UL) +#define bCM_SPI4 ((bCM_SPI_TypeDef *)0x42408000UL) +#define bCM_SRAMC ((bCM_SRAMC_TypeDef *)0x42A10000UL) +#define bCM_SWDT ((bCM_SWDT_TypeDef *)0x42928000UL) +#define bCM_TMR0_1 ((bCM_TMR0_TypeDef *)0x42480000UL) +#define bCM_TMR0_2 ((bCM_TMR0_TypeDef *)0x42488000UL) +#define bCM_TMR4_1 ((bCM_TMR4_TypeDef *)0x422E0000UL) +#define bCM_TMR4_2 ((bCM_TMR4_TypeDef *)0x42490000UL) +#define bCM_TMR4_3 ((bCM_TMR4_TypeDef *)0x42498000UL) +#define bCM_TMR6_1 ((bCM_TMR6_TypeDef *)0x42300000UL) +#define bCM_TMR6_2 ((bCM_TMR6_TypeDef *)0x42308000UL) +#define bCM_TMR6_3 ((bCM_TMR6_TypeDef *)0x42310000UL) +#define bCM_TMR6_COMMON ((bCM_TMR6_COMMON_TypeDef *)0x42306000UL) +#define bCM_TMRA_1 ((bCM_TMRA_TypeDef *)0x422A0000UL) +#define bCM_TMRA_2 ((bCM_TMRA_TypeDef *)0x422A8000UL) +#define bCM_TMRA_3 ((bCM_TMRA_TypeDef *)0x422B0000UL) +#define bCM_TMRA_4 ((bCM_TMRA_TypeDef *)0x422B8000UL) +#define bCM_TMRA_5 ((bCM_TMRA_TypeDef *)0x422C0000UL) +#define bCM_TMRA_6 ((bCM_TMRA_TypeDef *)0x422C8000UL) +#define bCM_TRNG ((bCM_TRNG_TypeDef *)0x42820000UL) +#define bCM_USART1 ((bCM_USART_TypeDef *)0x423A0000UL) +#define bCM_USART2 ((bCM_USART_TypeDef *)0x423A8000UL) +#define bCM_USART3 ((bCM_USART_TypeDef *)0x42420000UL) +#define bCM_USART4 ((bCM_USART_TypeDef *)0x42428000UL) +#define bCM_USBFS ((bCM_USBFS_TypeDef *)0x43800000UL) +#define bCM_WDT ((bCM_WDT_TypeDef *)0x42920000UL) + + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460PETB_H__ */ diff --git a/Project/RTE/Device/HC32F460PETB/startup_hc32f460.s b/Project/RTE/Device/HC32F460PETB/startup_hc32f460.s new file mode 100644 index 0000000..4968a94 --- /dev/null +++ b/Project/RTE/Device/HC32F460PETB/startup_hc32f460.s @@ -0,0 +1,623 @@ +;/** +; ****************************************************************************** +; @file startup_hc32f460.s +; @brief Startup for MDK. +; verbatim +; Change Logs: +; Date Author Notes +; 2022-03-31 CDT First version +; 2024-11-08 CDT Added code of clear SRAMC status flags +; endverbatim +; ***************************************************************************** +; * Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; ****************************************************************************** +; */ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Heap_Size EQU 0x00002000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Peripheral Interrupts + DCD IRQ000_Handler + DCD IRQ001_Handler + DCD IRQ002_Handler + DCD IRQ003_Handler + DCD IRQ004_Handler + DCD IRQ005_Handler + DCD IRQ006_Handler + DCD IRQ007_Handler + DCD IRQ008_Handler + DCD IRQ009_Handler + DCD IRQ010_Handler + DCD IRQ011_Handler + DCD IRQ012_Handler + DCD IRQ013_Handler + DCD IRQ014_Handler + DCD IRQ015_Handler + DCD IRQ016_Handler + DCD IRQ017_Handler + DCD IRQ018_Handler + DCD IRQ019_Handler + DCD IRQ020_Handler + DCD IRQ021_Handler + DCD IRQ022_Handler + DCD IRQ023_Handler + DCD IRQ024_Handler + DCD IRQ025_Handler + DCD IRQ026_Handler + DCD IRQ027_Handler + DCD IRQ028_Handler + DCD IRQ029_Handler + DCD IRQ030_Handler + DCD IRQ031_Handler + DCD IRQ032_Handler + DCD IRQ033_Handler + DCD IRQ034_Handler + DCD IRQ035_Handler + DCD IRQ036_Handler + DCD IRQ037_Handler + DCD IRQ038_Handler + DCD IRQ039_Handler + DCD IRQ040_Handler + DCD IRQ041_Handler + DCD IRQ042_Handler + DCD IRQ043_Handler + DCD IRQ044_Handler + DCD IRQ045_Handler + DCD IRQ046_Handler + DCD IRQ047_Handler + DCD IRQ048_Handler + DCD IRQ049_Handler + DCD IRQ050_Handler + DCD IRQ051_Handler + DCD IRQ052_Handler + DCD IRQ053_Handler + DCD IRQ054_Handler + DCD IRQ055_Handler + DCD IRQ056_Handler + DCD IRQ057_Handler + DCD IRQ058_Handler + DCD IRQ059_Handler + DCD IRQ060_Handler + DCD IRQ061_Handler + DCD IRQ062_Handler + DCD IRQ063_Handler + DCD IRQ064_Handler + DCD IRQ065_Handler + DCD IRQ066_Handler + DCD IRQ067_Handler + DCD IRQ068_Handler + DCD IRQ069_Handler + DCD IRQ070_Handler + DCD IRQ071_Handler + DCD IRQ072_Handler + DCD IRQ073_Handler + DCD IRQ074_Handler + DCD IRQ075_Handler + DCD IRQ076_Handler + DCD IRQ077_Handler + DCD IRQ078_Handler + DCD IRQ079_Handler + DCD IRQ080_Handler + DCD IRQ081_Handler + DCD IRQ082_Handler + DCD IRQ083_Handler + DCD IRQ084_Handler + DCD IRQ085_Handler + DCD IRQ086_Handler + DCD IRQ087_Handler + DCD IRQ088_Handler + DCD IRQ089_Handler + DCD IRQ090_Handler + DCD IRQ091_Handler + DCD IRQ092_Handler + DCD IRQ093_Handler + DCD IRQ094_Handler + DCD IRQ095_Handler + DCD IRQ096_Handler + DCD IRQ097_Handler + DCD IRQ098_Handler + DCD IRQ099_Handler + DCD IRQ100_Handler + DCD IRQ101_Handler + DCD IRQ102_Handler + DCD IRQ103_Handler + DCD IRQ104_Handler + DCD IRQ105_Handler + DCD IRQ106_Handler + DCD IRQ107_Handler + DCD IRQ108_Handler + DCD IRQ109_Handler + DCD IRQ110_Handler + DCD IRQ111_Handler + DCD IRQ112_Handler + DCD IRQ113_Handler + DCD IRQ114_Handler + DCD IRQ115_Handler + DCD IRQ116_Handler + DCD IRQ117_Handler + DCD IRQ118_Handler + DCD IRQ119_Handler + DCD IRQ120_Handler + DCD IRQ121_Handler + DCD IRQ122_Handler + DCD IRQ123_Handler + DCD IRQ124_Handler + DCD IRQ125_Handler + DCD IRQ126_Handler + DCD IRQ127_Handler + DCD IRQ128_Handler + DCD IRQ129_Handler + DCD IRQ130_Handler + DCD IRQ131_Handler + DCD IRQ132_Handler + DCD IRQ133_Handler + DCD IRQ134_Handler + DCD IRQ135_Handler + DCD IRQ136_Handler + DCD IRQ137_Handler + DCD IRQ138_Handler + DCD IRQ139_Handler + DCD IRQ140_Handler + DCD IRQ141_Handler + DCD IRQ142_Handler + DCD IRQ143_Handler + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main +;ClrSramSR + LDR R0, =0x40050810 + LDR R1, =0x1F + STR R1, [R0] +;SetSRAM3Wait + LDR R0, =0x40050804 + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x40050800 + MOV R1, #0x1100 + STR R1, [R0] + + LDR R0, =0x40050804 + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT IRQ000_Handler [WEAK] + EXPORT IRQ001_Handler [WEAK] + EXPORT IRQ002_Handler [WEAK] + EXPORT IRQ003_Handler [WEAK] + EXPORT IRQ004_Handler [WEAK] + EXPORT IRQ005_Handler [WEAK] + EXPORT IRQ006_Handler [WEAK] + EXPORT IRQ007_Handler [WEAK] + EXPORT IRQ008_Handler [WEAK] + EXPORT IRQ009_Handler [WEAK] + EXPORT IRQ010_Handler [WEAK] + EXPORT IRQ011_Handler [WEAK] + EXPORT IRQ012_Handler [WEAK] + EXPORT IRQ013_Handler [WEAK] + EXPORT IRQ014_Handler [WEAK] + EXPORT IRQ015_Handler [WEAK] + EXPORT IRQ016_Handler [WEAK] + EXPORT IRQ017_Handler [WEAK] + EXPORT IRQ018_Handler [WEAK] + EXPORT IRQ019_Handler [WEAK] + EXPORT IRQ020_Handler [WEAK] + EXPORT IRQ021_Handler [WEAK] + EXPORT IRQ022_Handler [WEAK] + EXPORT IRQ023_Handler [WEAK] + EXPORT IRQ024_Handler [WEAK] + EXPORT IRQ025_Handler [WEAK] + EXPORT IRQ026_Handler [WEAK] + EXPORT IRQ027_Handler [WEAK] + EXPORT IRQ028_Handler [WEAK] + EXPORT IRQ029_Handler [WEAK] + EXPORT IRQ030_Handler [WEAK] + EXPORT IRQ031_Handler [WEAK] + EXPORT IRQ032_Handler [WEAK] + EXPORT IRQ033_Handler [WEAK] + EXPORT IRQ034_Handler [WEAK] + EXPORT IRQ035_Handler [WEAK] + EXPORT IRQ036_Handler [WEAK] + EXPORT IRQ037_Handler [WEAK] + EXPORT IRQ038_Handler [WEAK] + EXPORT IRQ039_Handler [WEAK] + EXPORT IRQ040_Handler [WEAK] + EXPORT IRQ041_Handler [WEAK] + EXPORT IRQ042_Handler [WEAK] + EXPORT IRQ043_Handler [WEAK] + EXPORT IRQ044_Handler [WEAK] + EXPORT IRQ045_Handler [WEAK] + EXPORT IRQ046_Handler [WEAK] + EXPORT IRQ047_Handler [WEAK] + EXPORT IRQ048_Handler [WEAK] + EXPORT IRQ049_Handler [WEAK] + EXPORT IRQ050_Handler [WEAK] + EXPORT IRQ051_Handler [WEAK] + EXPORT IRQ052_Handler [WEAK] + EXPORT IRQ053_Handler [WEAK] + EXPORT IRQ054_Handler [WEAK] + EXPORT IRQ055_Handler [WEAK] + EXPORT IRQ056_Handler [WEAK] + EXPORT IRQ057_Handler [WEAK] + EXPORT IRQ058_Handler [WEAK] + EXPORT IRQ059_Handler [WEAK] + EXPORT IRQ060_Handler [WEAK] + EXPORT IRQ061_Handler [WEAK] + EXPORT IRQ062_Handler [WEAK] + EXPORT IRQ063_Handler [WEAK] + EXPORT IRQ064_Handler [WEAK] + EXPORT IRQ065_Handler [WEAK] + EXPORT IRQ066_Handler [WEAK] + EXPORT IRQ067_Handler [WEAK] + EXPORT IRQ068_Handler [WEAK] + EXPORT IRQ069_Handler [WEAK] + EXPORT IRQ070_Handler [WEAK] + EXPORT IRQ071_Handler [WEAK] + EXPORT IRQ072_Handler [WEAK] + EXPORT IRQ073_Handler [WEAK] + EXPORT IRQ074_Handler [WEAK] + EXPORT IRQ075_Handler [WEAK] + EXPORT IRQ076_Handler [WEAK] + EXPORT IRQ077_Handler [WEAK] + EXPORT IRQ078_Handler [WEAK] + EXPORT IRQ079_Handler [WEAK] + EXPORT IRQ080_Handler [WEAK] + EXPORT IRQ081_Handler [WEAK] + EXPORT IRQ082_Handler [WEAK] + EXPORT IRQ083_Handler [WEAK] + EXPORT IRQ084_Handler [WEAK] + EXPORT IRQ085_Handler [WEAK] + EXPORT IRQ086_Handler [WEAK] + EXPORT IRQ087_Handler [WEAK] + EXPORT IRQ088_Handler [WEAK] + EXPORT IRQ089_Handler [WEAK] + EXPORT IRQ090_Handler [WEAK] + EXPORT IRQ091_Handler [WEAK] + EXPORT IRQ092_Handler [WEAK] + EXPORT IRQ093_Handler [WEAK] + EXPORT IRQ094_Handler [WEAK] + EXPORT IRQ095_Handler [WEAK] + EXPORT IRQ096_Handler [WEAK] + EXPORT IRQ097_Handler [WEAK] + EXPORT IRQ098_Handler [WEAK] + EXPORT IRQ099_Handler [WEAK] + EXPORT IRQ100_Handler [WEAK] + EXPORT IRQ101_Handler [WEAK] + EXPORT IRQ102_Handler [WEAK] + EXPORT IRQ103_Handler [WEAK] + EXPORT IRQ104_Handler [WEAK] + EXPORT IRQ105_Handler [WEAK] + EXPORT IRQ106_Handler [WEAK] + EXPORT IRQ107_Handler [WEAK] + EXPORT IRQ108_Handler [WEAK] + EXPORT IRQ109_Handler [WEAK] + EXPORT IRQ110_Handler [WEAK] + EXPORT IRQ111_Handler [WEAK] + EXPORT IRQ112_Handler [WEAK] + EXPORT IRQ113_Handler [WEAK] + EXPORT IRQ114_Handler [WEAK] + EXPORT IRQ115_Handler [WEAK] + EXPORT IRQ116_Handler [WEAK] + EXPORT IRQ117_Handler [WEAK] + EXPORT IRQ118_Handler [WEAK] + EXPORT IRQ119_Handler [WEAK] + EXPORT IRQ120_Handler [WEAK] + EXPORT IRQ121_Handler [WEAK] + EXPORT IRQ122_Handler [WEAK] + EXPORT IRQ123_Handler [WEAK] + EXPORT IRQ124_Handler [WEAK] + EXPORT IRQ125_Handler [WEAK] + EXPORT IRQ126_Handler [WEAK] + EXPORT IRQ127_Handler [WEAK] + EXPORT IRQ128_Handler [WEAK] + EXPORT IRQ129_Handler [WEAK] + EXPORT IRQ130_Handler [WEAK] + EXPORT IRQ131_Handler [WEAK] + EXPORT IRQ132_Handler [WEAK] + EXPORT IRQ133_Handler [WEAK] + EXPORT IRQ134_Handler [WEAK] + EXPORT IRQ135_Handler [WEAK] + EXPORT IRQ136_Handler [WEAK] + EXPORT IRQ137_Handler [WEAK] + EXPORT IRQ138_Handler [WEAK] + EXPORT IRQ139_Handler [WEAK] + EXPORT IRQ140_Handler [WEAK] + EXPORT IRQ141_Handler [WEAK] + EXPORT IRQ142_Handler [WEAK] + EXPORT IRQ143_Handler [WEAK] + +IRQ000_Handler +IRQ001_Handler +IRQ002_Handler +IRQ003_Handler +IRQ004_Handler +IRQ005_Handler +IRQ006_Handler +IRQ007_Handler +IRQ008_Handler +IRQ009_Handler +IRQ010_Handler +IRQ011_Handler +IRQ012_Handler +IRQ013_Handler +IRQ014_Handler +IRQ015_Handler +IRQ016_Handler +IRQ017_Handler +IRQ018_Handler +IRQ019_Handler +IRQ020_Handler +IRQ021_Handler +IRQ022_Handler +IRQ023_Handler +IRQ024_Handler +IRQ025_Handler +IRQ026_Handler +IRQ027_Handler +IRQ028_Handler +IRQ029_Handler +IRQ030_Handler +IRQ031_Handler +IRQ032_Handler +IRQ033_Handler +IRQ034_Handler +IRQ035_Handler +IRQ036_Handler +IRQ037_Handler +IRQ038_Handler +IRQ039_Handler +IRQ040_Handler +IRQ041_Handler +IRQ042_Handler +IRQ043_Handler +IRQ044_Handler +IRQ045_Handler +IRQ046_Handler +IRQ047_Handler +IRQ048_Handler +IRQ049_Handler +IRQ050_Handler +IRQ051_Handler +IRQ052_Handler +IRQ053_Handler +IRQ054_Handler +IRQ055_Handler +IRQ056_Handler +IRQ057_Handler +IRQ058_Handler +IRQ059_Handler +IRQ060_Handler +IRQ061_Handler +IRQ062_Handler +IRQ063_Handler +IRQ064_Handler +IRQ065_Handler +IRQ066_Handler +IRQ067_Handler +IRQ068_Handler +IRQ069_Handler +IRQ070_Handler +IRQ071_Handler +IRQ072_Handler +IRQ073_Handler +IRQ074_Handler +IRQ075_Handler +IRQ076_Handler +IRQ077_Handler +IRQ078_Handler +IRQ079_Handler +IRQ080_Handler +IRQ081_Handler +IRQ082_Handler +IRQ083_Handler +IRQ084_Handler +IRQ085_Handler +IRQ086_Handler +IRQ087_Handler +IRQ088_Handler +IRQ089_Handler +IRQ090_Handler +IRQ091_Handler +IRQ092_Handler +IRQ093_Handler +IRQ094_Handler +IRQ095_Handler +IRQ096_Handler +IRQ097_Handler +IRQ098_Handler +IRQ099_Handler +IRQ100_Handler +IRQ101_Handler +IRQ102_Handler +IRQ103_Handler +IRQ104_Handler +IRQ105_Handler +IRQ106_Handler +IRQ107_Handler +IRQ108_Handler +IRQ109_Handler +IRQ110_Handler +IRQ111_Handler +IRQ112_Handler +IRQ113_Handler +IRQ114_Handler +IRQ115_Handler +IRQ116_Handler +IRQ117_Handler +IRQ118_Handler +IRQ119_Handler +IRQ120_Handler +IRQ121_Handler +IRQ122_Handler +IRQ123_Handler +IRQ124_Handler +IRQ125_Handler +IRQ126_Handler +IRQ127_Handler +IRQ128_Handler +IRQ129_Handler +IRQ130_Handler +IRQ131_Handler +IRQ132_Handler +IRQ133_Handler +IRQ134_Handler +IRQ135_Handler +IRQ136_Handler +IRQ137_Handler +IRQ138_Handler +IRQ139_Handler +IRQ140_Handler +IRQ141_Handler +IRQ142_Handler +IRQ143_Handler + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/Project/RTE/Device/HC32F460PETB/startup_hc32f460.s.base@1.0.0 b/Project/RTE/Device/HC32F460PETB/startup_hc32f460.s.base@1.0.0 new file mode 100644 index 0000000..4968a94 --- /dev/null +++ b/Project/RTE/Device/HC32F460PETB/startup_hc32f460.s.base@1.0.0 @@ -0,0 +1,623 @@ +;/** +; ****************************************************************************** +; @file startup_hc32f460.s +; @brief Startup for MDK. +; verbatim +; Change Logs: +; Date Author Notes +; 2022-03-31 CDT First version +; 2024-11-08 CDT Added code of clear SRAMC status flags +; endverbatim +; ***************************************************************************** +; * Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; ****************************************************************************** +; */ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Heap_Size EQU 0x00002000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Peripheral Interrupts + DCD IRQ000_Handler + DCD IRQ001_Handler + DCD IRQ002_Handler + DCD IRQ003_Handler + DCD IRQ004_Handler + DCD IRQ005_Handler + DCD IRQ006_Handler + DCD IRQ007_Handler + DCD IRQ008_Handler + DCD IRQ009_Handler + DCD IRQ010_Handler + DCD IRQ011_Handler + DCD IRQ012_Handler + DCD IRQ013_Handler + DCD IRQ014_Handler + DCD IRQ015_Handler + DCD IRQ016_Handler + DCD IRQ017_Handler + DCD IRQ018_Handler + DCD IRQ019_Handler + DCD IRQ020_Handler + DCD IRQ021_Handler + DCD IRQ022_Handler + DCD IRQ023_Handler + DCD IRQ024_Handler + DCD IRQ025_Handler + DCD IRQ026_Handler + DCD IRQ027_Handler + DCD IRQ028_Handler + DCD IRQ029_Handler + DCD IRQ030_Handler + DCD IRQ031_Handler + DCD IRQ032_Handler + DCD IRQ033_Handler + DCD IRQ034_Handler + DCD IRQ035_Handler + DCD IRQ036_Handler + DCD IRQ037_Handler + DCD IRQ038_Handler + DCD IRQ039_Handler + DCD IRQ040_Handler + DCD IRQ041_Handler + DCD IRQ042_Handler + DCD IRQ043_Handler + DCD IRQ044_Handler + DCD IRQ045_Handler + DCD IRQ046_Handler + DCD IRQ047_Handler + DCD IRQ048_Handler + DCD IRQ049_Handler + DCD IRQ050_Handler + DCD IRQ051_Handler + DCD IRQ052_Handler + DCD IRQ053_Handler + DCD IRQ054_Handler + DCD IRQ055_Handler + DCD IRQ056_Handler + DCD IRQ057_Handler + DCD IRQ058_Handler + DCD IRQ059_Handler + DCD IRQ060_Handler + DCD IRQ061_Handler + DCD IRQ062_Handler + DCD IRQ063_Handler + DCD IRQ064_Handler + DCD IRQ065_Handler + DCD IRQ066_Handler + DCD IRQ067_Handler + DCD IRQ068_Handler + DCD IRQ069_Handler + DCD IRQ070_Handler + DCD IRQ071_Handler + DCD IRQ072_Handler + DCD IRQ073_Handler + DCD IRQ074_Handler + DCD IRQ075_Handler + DCD IRQ076_Handler + DCD IRQ077_Handler + DCD IRQ078_Handler + DCD IRQ079_Handler + DCD IRQ080_Handler + DCD IRQ081_Handler + DCD IRQ082_Handler + DCD IRQ083_Handler + DCD IRQ084_Handler + DCD IRQ085_Handler + DCD IRQ086_Handler + DCD IRQ087_Handler + DCD IRQ088_Handler + DCD IRQ089_Handler + DCD IRQ090_Handler + DCD IRQ091_Handler + DCD IRQ092_Handler + DCD IRQ093_Handler + DCD IRQ094_Handler + DCD IRQ095_Handler + DCD IRQ096_Handler + DCD IRQ097_Handler + DCD IRQ098_Handler + DCD IRQ099_Handler + DCD IRQ100_Handler + DCD IRQ101_Handler + DCD IRQ102_Handler + DCD IRQ103_Handler + DCD IRQ104_Handler + DCD IRQ105_Handler + DCD IRQ106_Handler + DCD IRQ107_Handler + DCD IRQ108_Handler + DCD IRQ109_Handler + DCD IRQ110_Handler + DCD IRQ111_Handler + DCD IRQ112_Handler + DCD IRQ113_Handler + DCD IRQ114_Handler + DCD IRQ115_Handler + DCD IRQ116_Handler + DCD IRQ117_Handler + DCD IRQ118_Handler + DCD IRQ119_Handler + DCD IRQ120_Handler + DCD IRQ121_Handler + DCD IRQ122_Handler + DCD IRQ123_Handler + DCD IRQ124_Handler + DCD IRQ125_Handler + DCD IRQ126_Handler + DCD IRQ127_Handler + DCD IRQ128_Handler + DCD IRQ129_Handler + DCD IRQ130_Handler + DCD IRQ131_Handler + DCD IRQ132_Handler + DCD IRQ133_Handler + DCD IRQ134_Handler + DCD IRQ135_Handler + DCD IRQ136_Handler + DCD IRQ137_Handler + DCD IRQ138_Handler + DCD IRQ139_Handler + DCD IRQ140_Handler + DCD IRQ141_Handler + DCD IRQ142_Handler + DCD IRQ143_Handler + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main +;ClrSramSR + LDR R0, =0x40050810 + LDR R1, =0x1F + STR R1, [R0] +;SetSRAM3Wait + LDR R0, =0x40050804 + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x40050800 + MOV R1, #0x1100 + STR R1, [R0] + + LDR R0, =0x40050804 + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT IRQ000_Handler [WEAK] + EXPORT IRQ001_Handler [WEAK] + EXPORT IRQ002_Handler [WEAK] + EXPORT IRQ003_Handler [WEAK] + EXPORT IRQ004_Handler [WEAK] + EXPORT IRQ005_Handler [WEAK] + EXPORT IRQ006_Handler [WEAK] + EXPORT IRQ007_Handler [WEAK] + EXPORT IRQ008_Handler [WEAK] + EXPORT IRQ009_Handler [WEAK] + EXPORT IRQ010_Handler [WEAK] + EXPORT IRQ011_Handler [WEAK] + EXPORT IRQ012_Handler [WEAK] + EXPORT IRQ013_Handler [WEAK] + EXPORT IRQ014_Handler [WEAK] + EXPORT IRQ015_Handler [WEAK] + EXPORT IRQ016_Handler [WEAK] + EXPORT IRQ017_Handler [WEAK] + EXPORT IRQ018_Handler [WEAK] + EXPORT IRQ019_Handler [WEAK] + EXPORT IRQ020_Handler [WEAK] + EXPORT IRQ021_Handler [WEAK] + EXPORT IRQ022_Handler [WEAK] + EXPORT IRQ023_Handler [WEAK] + EXPORT IRQ024_Handler [WEAK] + EXPORT IRQ025_Handler [WEAK] + EXPORT IRQ026_Handler [WEAK] + EXPORT IRQ027_Handler [WEAK] + EXPORT IRQ028_Handler [WEAK] + EXPORT IRQ029_Handler [WEAK] + EXPORT IRQ030_Handler [WEAK] + EXPORT IRQ031_Handler [WEAK] + EXPORT IRQ032_Handler [WEAK] + EXPORT IRQ033_Handler [WEAK] + EXPORT IRQ034_Handler [WEAK] + EXPORT IRQ035_Handler [WEAK] + EXPORT IRQ036_Handler [WEAK] + EXPORT IRQ037_Handler [WEAK] + EXPORT IRQ038_Handler [WEAK] + EXPORT IRQ039_Handler [WEAK] + EXPORT IRQ040_Handler [WEAK] + EXPORT IRQ041_Handler [WEAK] + EXPORT IRQ042_Handler [WEAK] + EXPORT IRQ043_Handler [WEAK] + EXPORT IRQ044_Handler [WEAK] + EXPORT IRQ045_Handler [WEAK] + EXPORT IRQ046_Handler [WEAK] + EXPORT IRQ047_Handler [WEAK] + EXPORT IRQ048_Handler [WEAK] + EXPORT IRQ049_Handler [WEAK] + EXPORT IRQ050_Handler [WEAK] + EXPORT IRQ051_Handler [WEAK] + EXPORT IRQ052_Handler [WEAK] + EXPORT IRQ053_Handler [WEAK] + EXPORT IRQ054_Handler [WEAK] + EXPORT IRQ055_Handler [WEAK] + EXPORT IRQ056_Handler [WEAK] + EXPORT IRQ057_Handler [WEAK] + EXPORT IRQ058_Handler [WEAK] + EXPORT IRQ059_Handler [WEAK] + EXPORT IRQ060_Handler [WEAK] + EXPORT IRQ061_Handler [WEAK] + EXPORT IRQ062_Handler [WEAK] + EXPORT IRQ063_Handler [WEAK] + EXPORT IRQ064_Handler [WEAK] + EXPORT IRQ065_Handler [WEAK] + EXPORT IRQ066_Handler [WEAK] + EXPORT IRQ067_Handler [WEAK] + EXPORT IRQ068_Handler [WEAK] + EXPORT IRQ069_Handler [WEAK] + EXPORT IRQ070_Handler [WEAK] + EXPORT IRQ071_Handler [WEAK] + EXPORT IRQ072_Handler [WEAK] + EXPORT IRQ073_Handler [WEAK] + EXPORT IRQ074_Handler [WEAK] + EXPORT IRQ075_Handler [WEAK] + EXPORT IRQ076_Handler [WEAK] + EXPORT IRQ077_Handler [WEAK] + EXPORT IRQ078_Handler [WEAK] + EXPORT IRQ079_Handler [WEAK] + EXPORT IRQ080_Handler [WEAK] + EXPORT IRQ081_Handler [WEAK] + EXPORT IRQ082_Handler [WEAK] + EXPORT IRQ083_Handler [WEAK] + EXPORT IRQ084_Handler [WEAK] + EXPORT IRQ085_Handler [WEAK] + EXPORT IRQ086_Handler [WEAK] + EXPORT IRQ087_Handler [WEAK] + EXPORT IRQ088_Handler [WEAK] + EXPORT IRQ089_Handler [WEAK] + EXPORT IRQ090_Handler [WEAK] + EXPORT IRQ091_Handler [WEAK] + EXPORT IRQ092_Handler [WEAK] + EXPORT IRQ093_Handler [WEAK] + EXPORT IRQ094_Handler [WEAK] + EXPORT IRQ095_Handler [WEAK] + EXPORT IRQ096_Handler [WEAK] + EXPORT IRQ097_Handler [WEAK] + EXPORT IRQ098_Handler [WEAK] + EXPORT IRQ099_Handler [WEAK] + EXPORT IRQ100_Handler [WEAK] + EXPORT IRQ101_Handler [WEAK] + EXPORT IRQ102_Handler [WEAK] + EXPORT IRQ103_Handler [WEAK] + EXPORT IRQ104_Handler [WEAK] + EXPORT IRQ105_Handler [WEAK] + EXPORT IRQ106_Handler [WEAK] + EXPORT IRQ107_Handler [WEAK] + EXPORT IRQ108_Handler [WEAK] + EXPORT IRQ109_Handler [WEAK] + EXPORT IRQ110_Handler [WEAK] + EXPORT IRQ111_Handler [WEAK] + EXPORT IRQ112_Handler [WEAK] + EXPORT IRQ113_Handler [WEAK] + EXPORT IRQ114_Handler [WEAK] + EXPORT IRQ115_Handler [WEAK] + EXPORT IRQ116_Handler [WEAK] + EXPORT IRQ117_Handler [WEAK] + EXPORT IRQ118_Handler [WEAK] + EXPORT IRQ119_Handler [WEAK] + EXPORT IRQ120_Handler [WEAK] + EXPORT IRQ121_Handler [WEAK] + EXPORT IRQ122_Handler [WEAK] + EXPORT IRQ123_Handler [WEAK] + EXPORT IRQ124_Handler [WEAK] + EXPORT IRQ125_Handler [WEAK] + EXPORT IRQ126_Handler [WEAK] + EXPORT IRQ127_Handler [WEAK] + EXPORT IRQ128_Handler [WEAK] + EXPORT IRQ129_Handler [WEAK] + EXPORT IRQ130_Handler [WEAK] + EXPORT IRQ131_Handler [WEAK] + EXPORT IRQ132_Handler [WEAK] + EXPORT IRQ133_Handler [WEAK] + EXPORT IRQ134_Handler [WEAK] + EXPORT IRQ135_Handler [WEAK] + EXPORT IRQ136_Handler [WEAK] + EXPORT IRQ137_Handler [WEAK] + EXPORT IRQ138_Handler [WEAK] + EXPORT IRQ139_Handler [WEAK] + EXPORT IRQ140_Handler [WEAK] + EXPORT IRQ141_Handler [WEAK] + EXPORT IRQ142_Handler [WEAK] + EXPORT IRQ143_Handler [WEAK] + +IRQ000_Handler +IRQ001_Handler +IRQ002_Handler +IRQ003_Handler +IRQ004_Handler +IRQ005_Handler +IRQ006_Handler +IRQ007_Handler +IRQ008_Handler +IRQ009_Handler +IRQ010_Handler +IRQ011_Handler +IRQ012_Handler +IRQ013_Handler +IRQ014_Handler +IRQ015_Handler +IRQ016_Handler +IRQ017_Handler +IRQ018_Handler +IRQ019_Handler +IRQ020_Handler +IRQ021_Handler +IRQ022_Handler +IRQ023_Handler +IRQ024_Handler +IRQ025_Handler +IRQ026_Handler +IRQ027_Handler +IRQ028_Handler +IRQ029_Handler +IRQ030_Handler +IRQ031_Handler +IRQ032_Handler +IRQ033_Handler +IRQ034_Handler +IRQ035_Handler +IRQ036_Handler +IRQ037_Handler +IRQ038_Handler +IRQ039_Handler +IRQ040_Handler +IRQ041_Handler +IRQ042_Handler +IRQ043_Handler +IRQ044_Handler +IRQ045_Handler +IRQ046_Handler +IRQ047_Handler +IRQ048_Handler +IRQ049_Handler +IRQ050_Handler +IRQ051_Handler +IRQ052_Handler +IRQ053_Handler +IRQ054_Handler +IRQ055_Handler +IRQ056_Handler +IRQ057_Handler +IRQ058_Handler +IRQ059_Handler +IRQ060_Handler +IRQ061_Handler +IRQ062_Handler +IRQ063_Handler +IRQ064_Handler +IRQ065_Handler +IRQ066_Handler +IRQ067_Handler +IRQ068_Handler +IRQ069_Handler +IRQ070_Handler +IRQ071_Handler +IRQ072_Handler +IRQ073_Handler +IRQ074_Handler +IRQ075_Handler +IRQ076_Handler +IRQ077_Handler +IRQ078_Handler +IRQ079_Handler +IRQ080_Handler +IRQ081_Handler +IRQ082_Handler +IRQ083_Handler +IRQ084_Handler +IRQ085_Handler +IRQ086_Handler +IRQ087_Handler +IRQ088_Handler +IRQ089_Handler +IRQ090_Handler +IRQ091_Handler +IRQ092_Handler +IRQ093_Handler +IRQ094_Handler +IRQ095_Handler +IRQ096_Handler +IRQ097_Handler +IRQ098_Handler +IRQ099_Handler +IRQ100_Handler +IRQ101_Handler +IRQ102_Handler +IRQ103_Handler +IRQ104_Handler +IRQ105_Handler +IRQ106_Handler +IRQ107_Handler +IRQ108_Handler +IRQ109_Handler +IRQ110_Handler +IRQ111_Handler +IRQ112_Handler +IRQ113_Handler +IRQ114_Handler +IRQ115_Handler +IRQ116_Handler +IRQ117_Handler +IRQ118_Handler +IRQ119_Handler +IRQ120_Handler +IRQ121_Handler +IRQ122_Handler +IRQ123_Handler +IRQ124_Handler +IRQ125_Handler +IRQ126_Handler +IRQ127_Handler +IRQ128_Handler +IRQ129_Handler +IRQ130_Handler +IRQ131_Handler +IRQ132_Handler +IRQ133_Handler +IRQ134_Handler +IRQ135_Handler +IRQ136_Handler +IRQ137_Handler +IRQ138_Handler +IRQ139_Handler +IRQ140_Handler +IRQ141_Handler +IRQ142_Handler +IRQ143_Handler + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/Project/RTE/Device/HC32F460PETB/system_hc32f460.c b/Project/RTE/Device/HC32F460PETB/system_hc32f460.c new file mode 100644 index 0000000..9747054 --- /dev/null +++ b/Project/RTE/Device/HC32F460PETB/system_hc32f460.c @@ -0,0 +1,189 @@ +/** + ******************************************************************************* + * @file system_hc32f460.c + * @brief This file provides two functions and two global variables to be called + * from user application. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "system_hc32f460.h" +#include "hc32f460.h" + +/** + * @addtogroup CMSIS + * @{ + */ + +/** + * @addtogroup HC32F460_System + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ +/** + * @defgroup HC32F460_System_Local_Macros HC32F460 System Local Macros + * @{ + */ +#define HRC_16MHz_VALUE (16000000UL) /*!< Internal high speed RC freq. */ +#define HRC_20MHz_VALUE (20000000UL) /*!< Internal high speed RC freq. */ +/* HRC select */ +#define HRC_FREQ_MON() (*((volatile uint32_t *)(0x40010684UL))) + +/* Vector Table base offset field */ +#ifndef VECT_TAB_OFFSET +#define VECT_TAB_OFFSET (0x0UL) /*!< This value must be a multiple of 0x400. */ +#endif +/* Compiler Macros */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#ifndef __NO_INIT +#define __NO_INIT __attribute__((section(".bss.noinit"))) +#endif /* __NO_INIT */ +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /*!< GNU Compiler */ +#ifndef __NO_INIT +#define __NO_INIT __attribute__((section(".noinit"))) +#endif /* __NO_INIT */ +#elif defined (__ICCARM__) /*!< IAR Compiler */ +#ifndef __NO_INIT +#define __NO_INIT __no_init +#endif /* __NO_INIT */ +#elif defined (__CC_ARM) /*!< ARM Compiler */ +#ifndef __NO_INIT +#define __NO_INIT __attribute__((section(".bss.noinit"), zero_init)) +#endif /* __NO_INIT */ +#endif +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +/** + * @addtogroup HC32F460_System_Global_Variable + * @{ + */ + +/*!< System clock frequency (Core clock) */ +__NO_INIT uint32_t SystemCoreClock; +/*!< High speed RC frequency (HCR clock) */ +__NO_INIT uint32_t HRC_VALUE; + +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @addtogroup HC32F460_System_Global_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. Initialize the System and update + * the SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings */ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20) | (3UL << 22)); /* set CP10 and CP11 Full Access */ +#endif + SystemCoreClockUpdate(); + /* Configure the Vector Table relocation */ + SCB->VTOR = VECT_TAB_OFFSET; /* Vector Table Relocation */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint8_t u8SysClkSrc; + uint32_t plln; + uint32_t pllp; + uint32_t pllm; + uint32_t u32PllSrcFreq; + + /* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */ + if (1UL == (HRC_FREQ_MON() & 1UL)) { + HRC_VALUE = HRC_16MHz_VALUE; + } else { + HRC_VALUE = HRC_20MHz_VALUE; + } + u8SysClkSrc = CM_CMU->CKSWR & CMU_CKSWR_CKSW; + switch (u8SysClkSrc) { + case 0x00U: /* use internal high speed RC */ + SystemCoreClock = HRC_VALUE; + break; + case 0x01U: /* use internal middle speed RC */ + SystemCoreClock = MRC_VALUE; + break; + case 0x02U: /* use internal low speed RC */ + SystemCoreClock = LRC_VALUE; + break; + case 0x03U: /* use external high speed OSC */ + SystemCoreClock = XTAL_VALUE; + break; + case 0x04U: /* use external low speed OSC */ + SystemCoreClock = XTAL32_VALUE; + break; + case 0x05U: /* use MPLL */ + /* PLLCLK = ((pllsrc / pllm) * plln) / pllp */ + plln = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLN) >> CMU_PLLCFGR_MPLLN_POS; + pllp = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLP) >> CMU_PLLCFGR_MPLLP_POS; + pllm = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLM) >> CMU_PLLCFGR_MPLLM_POS; + if (0UL == (CM_CMU->PLLCFGR & CMU_PLLCFGR_PLLSRC)) { /* use external highspeed OSC as PLL source */ + u32PllSrcFreq = XTAL_VALUE; + } else { /* use internal high RC as PLL source */ + u32PllSrcFreq = HRC_VALUE; + } + SystemCoreClock = u32PllSrcFreq / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL); + break; + default: + break; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/Project/RTE/Device/HC32F460PETB/system_hc32f460.c.base@1.0.0 b/Project/RTE/Device/HC32F460PETB/system_hc32f460.c.base@1.0.0 new file mode 100644 index 0000000..9747054 --- /dev/null +++ b/Project/RTE/Device/HC32F460PETB/system_hc32f460.c.base@1.0.0 @@ -0,0 +1,189 @@ +/** + ******************************************************************************* + * @file system_hc32f460.c + * @brief This file provides two functions and two global variables to be called + * from user application. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "system_hc32f460.h" +#include "hc32f460.h" + +/** + * @addtogroup CMSIS + * @{ + */ + +/** + * @addtogroup HC32F460_System + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ +/** + * @defgroup HC32F460_System_Local_Macros HC32F460 System Local Macros + * @{ + */ +#define HRC_16MHz_VALUE (16000000UL) /*!< Internal high speed RC freq. */ +#define HRC_20MHz_VALUE (20000000UL) /*!< Internal high speed RC freq. */ +/* HRC select */ +#define HRC_FREQ_MON() (*((volatile uint32_t *)(0x40010684UL))) + +/* Vector Table base offset field */ +#ifndef VECT_TAB_OFFSET +#define VECT_TAB_OFFSET (0x0UL) /*!< This value must be a multiple of 0x400. */ +#endif +/* Compiler Macros */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#ifndef __NO_INIT +#define __NO_INIT __attribute__((section(".bss.noinit"))) +#endif /* __NO_INIT */ +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /*!< GNU Compiler */ +#ifndef __NO_INIT +#define __NO_INIT __attribute__((section(".noinit"))) +#endif /* __NO_INIT */ +#elif defined (__ICCARM__) /*!< IAR Compiler */ +#ifndef __NO_INIT +#define __NO_INIT __no_init +#endif /* __NO_INIT */ +#elif defined (__CC_ARM) /*!< ARM Compiler */ +#ifndef __NO_INIT +#define __NO_INIT __attribute__((section(".bss.noinit"), zero_init)) +#endif /* __NO_INIT */ +#endif +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +/** + * @addtogroup HC32F460_System_Global_Variable + * @{ + */ + +/*!< System clock frequency (Core clock) */ +__NO_INIT uint32_t SystemCoreClock; +/*!< High speed RC frequency (HCR clock) */ +__NO_INIT uint32_t HRC_VALUE; + +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @addtogroup HC32F460_System_Global_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. Initialize the System and update + * the SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings */ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20) | (3UL << 22)); /* set CP10 and CP11 Full Access */ +#endif + SystemCoreClockUpdate(); + /* Configure the Vector Table relocation */ + SCB->VTOR = VECT_TAB_OFFSET; /* Vector Table Relocation */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint8_t u8SysClkSrc; + uint32_t plln; + uint32_t pllp; + uint32_t pllm; + uint32_t u32PllSrcFreq; + + /* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */ + if (1UL == (HRC_FREQ_MON() & 1UL)) { + HRC_VALUE = HRC_16MHz_VALUE; + } else { + HRC_VALUE = HRC_20MHz_VALUE; + } + u8SysClkSrc = CM_CMU->CKSWR & CMU_CKSWR_CKSW; + switch (u8SysClkSrc) { + case 0x00U: /* use internal high speed RC */ + SystemCoreClock = HRC_VALUE; + break; + case 0x01U: /* use internal middle speed RC */ + SystemCoreClock = MRC_VALUE; + break; + case 0x02U: /* use internal low speed RC */ + SystemCoreClock = LRC_VALUE; + break; + case 0x03U: /* use external high speed OSC */ + SystemCoreClock = XTAL_VALUE; + break; + case 0x04U: /* use external low speed OSC */ + SystemCoreClock = XTAL32_VALUE; + break; + case 0x05U: /* use MPLL */ + /* PLLCLK = ((pllsrc / pllm) * plln) / pllp */ + plln = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLN) >> CMU_PLLCFGR_MPLLN_POS; + pllp = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLP) >> CMU_PLLCFGR_MPLLP_POS; + pllm = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLM) >> CMU_PLLCFGR_MPLLM_POS; + if (0UL == (CM_CMU->PLLCFGR & CMU_PLLCFGR_PLLSRC)) { /* use external highspeed OSC as PLL source */ + u32PllSrcFreq = XTAL_VALUE; + } else { /* use internal high RC as PLL source */ + u32PllSrcFreq = HRC_VALUE; + } + SystemCoreClock = u32PllSrcFreq / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL); + break; + default: + break; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/Project/RTE/Device/HC32F460PETB/system_hc32f460.h b/Project/RTE/Device/HC32F460PETB/system_hc32f460.h new file mode 100644 index 0000000..d911e9f --- /dev/null +++ b/Project/RTE/Device/HC32F460PETB/system_hc32f460.h @@ -0,0 +1,134 @@ +/** + ******************************************************************************* + * @file system_hc32f460.h + * @brief This file contains all the functions prototypes of the HC32 System. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __SYSTEM_HC32F460_H__ +#define __SYSTEM_HC32F460_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include + +/** + * @addtogroup CMSIS + * @{ + */ + +/** + * @addtogroup HC32F460_System + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ +/** + * @addtogroup HC32F460_System_Global_Macros + * @{ + */ + +/** + * @addtogroup HC32F460_System_Clock_Source + * @{ + */ +#if !defined (MRC_VALUE) +#define MRC_VALUE (8000000UL) /*!< Internal middle speed RC freq. */ +#endif + +#if !defined (LRC_VALUE) +#define LRC_VALUE (32768UL) /*!< Internal low speed RC freq. */ +#endif + +#if !defined (SWDTLRC_VALUE) +#define SWDTLRC_VALUE (10000UL) /*!< Internal SWDT low speed RC freq. */ +#endif + +#if !defined (XTAL_VALUE) +#define XTAL_VALUE (8000000UL) /*!< External high speed OSC freq. */ +#endif + +#if !defined (XTAL32_VALUE) +#define XTAL32_VALUE (32768UL) /*!< External low speed OSC freq. */ +#endif + +#if !defined (HCLK_VALUE) +#define HCLK_VALUE (SystemCoreClock >> ((CM_CMU->SCFGR & CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS)) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +/** + * @addtogroup HC32F460_System_Exported_Variable + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System clock frequency (Core clock) */ +extern uint32_t HRC_VALUE; /*!< HRC frequency */ + +/** + * @} + */ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup HC32F460_System_Global_Functions + * @{ + */ + +extern void SystemInit(void); /*!< Initialize the system */ +extern void SystemCoreClockUpdate(void); /*!< Update SystemCoreClock variable */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_HC32F460_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/Project/RTE/Device/HC32F460PETB/system_hc32f460.h.base@1.0.0 b/Project/RTE/Device/HC32F460PETB/system_hc32f460.h.base@1.0.0 new file mode 100644 index 0000000..d911e9f --- /dev/null +++ b/Project/RTE/Device/HC32F460PETB/system_hc32f460.h.base@1.0.0 @@ -0,0 +1,134 @@ +/** + ******************************************************************************* + * @file system_hc32f460.h + * @brief This file contains all the functions prototypes of the HC32 System. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __SYSTEM_HC32F460_H__ +#define __SYSTEM_HC32F460_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include + +/** + * @addtogroup CMSIS + * @{ + */ + +/** + * @addtogroup HC32F460_System + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ +/** + * @addtogroup HC32F460_System_Global_Macros + * @{ + */ + +/** + * @addtogroup HC32F460_System_Clock_Source + * @{ + */ +#if !defined (MRC_VALUE) +#define MRC_VALUE (8000000UL) /*!< Internal middle speed RC freq. */ +#endif + +#if !defined (LRC_VALUE) +#define LRC_VALUE (32768UL) /*!< Internal low speed RC freq. */ +#endif + +#if !defined (SWDTLRC_VALUE) +#define SWDTLRC_VALUE (10000UL) /*!< Internal SWDT low speed RC freq. */ +#endif + +#if !defined (XTAL_VALUE) +#define XTAL_VALUE (8000000UL) /*!< External high speed OSC freq. */ +#endif + +#if !defined (XTAL32_VALUE) +#define XTAL32_VALUE (32768UL) /*!< External low speed OSC freq. */ +#endif + +#if !defined (HCLK_VALUE) +#define HCLK_VALUE (SystemCoreClock >> ((CM_CMU->SCFGR & CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS)) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +/** + * @addtogroup HC32F460_System_Exported_Variable + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System clock frequency (Core clock) */ +extern uint32_t HRC_VALUE; /*!< HRC frequency */ + +/** + * @} + */ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup HC32F460_System_Global_Functions + * @{ + */ + +extern void SystemInit(void); /*!< Initialize the system */ +extern void SystemCoreClockUpdate(void); /*!< Update SystemCoreClock variable */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_HC32F460_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/Project/RTE/File_System/FS_Config.c b/Project/RTE/File_System/FS_Config.c new file mode 100644 index 0000000..21f42a7 --- /dev/null +++ b/Project/RTE/File_System/FS_Config.c @@ -0,0 +1,78 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::File System + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: FS_Config.c + * Purpose: File System Configuration + * Rev.: V6.3.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// FAT File System +// Define FAT File System parameters + +// Number of open files <1-16> +// Define number of files that can be opened at the same time. +// Default: 4 +#define FAT_MAX_OPEN_FILES 4 + +// + +// Embedded File System +// Define Embedded File System parameters + +// Number of open files <1-16> +// Define number of files that can be opened at the same time. +// Default: 4 +#define EFS_MAX_OPEN_FILES 4 + +// + +// Initial Current Drive <0=>F0: <1=>F1: +// <2=>M0: <3=>M1: +// <4=>N0: <5=>N1: +// <6=>R0: <9=>R1: +// <7=>U0: <8=>U1: +// Set initial setting for current drive. Current drive is used for File System functions +// that are invoked with the "" string and can be altered anytime during run-time. +#define FS_INITIAL_CDRIVE 2 + +#include "RTE_Components.h" + +#ifdef RTE_FileSystem_Drive_RAM_0 +#include "FS_Config_RAM_0.h" +#endif +#ifdef RTE_FileSystem_Drive_RAM_1 +#include "FS_Config_RAM_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_NOR_0 +#include "FS_Config_NOR_0.h" +#endif +#ifdef RTE_FileSystem_Drive_NOR_1 +#include "FS_Config_NOR_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_NAND_0 +#include "FS_Config_NAND_0.h" +#endif +#ifdef RTE_FileSystem_Drive_NAND_1 +#include "FS_Config_NAND_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_MC_0 +#include "FS_Config_MC_0.h" +#endif +#ifdef RTE_FileSystem_Drive_MC_1 +#include "FS_Config_MC_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_USB_0 +#include "FS_Config_USB_0.h" +#endif +#ifdef RTE_FileSystem_Drive_USB_1 +#include "FS_Config_USB_1.h" +#endif + +#include "fs_config.h" diff --git a/Project/RTE/File_System/FS_Config_MC_0.h b/Project/RTE/File_System/FS_Config_MC_0.h new file mode 100644 index 0000000..b04116e --- /dev/null +++ b/Project/RTE/File_System/FS_Config_MC_0.h @@ -0,0 +1,55 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::File System:Drive + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: FS_Config_MC_0.h + * Purpose: File System Configuration for Memory Card Drive + * Rev.: V6.2.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Memory Card Drive 0 +// Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:" +#define MC0_ENABLE 1 + +// Connect to hardware via Driver_MCI# <0-255> +// Select driver control block for hardware interface +#define MC0_MCI_DRIVER 0 + +// Connect to hardware via Driver_SPI# <0-255> +// Select driver control block for hardware interface when in SPI mode +#define MC0_SPI_DRIVER 0 + +// Memory Card Interface Mode <0=>Native <1=>SPI +// Native uses a SD Bus with up to 8 data lines, CLK, and CMD +// SPI uses 2 data lines (MOSI and MISO), SCLK and CS +#define MC0_SPI 0 + +// Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB +// <8=>8 KB <16=>16 KB <32=>32 KB +// Drive Cache stores data sectors and may be increased to speed-up +// file read/write operations on this drive (default: 4 KB) +#define MC0_CACHE_SIZE 4 + +// Locate Drive Cache and Drive Buffer +// Some microcontrollers support DMA only in specific memory areas and +// require to locate the drive buffers at a fixed address. +#define MC0_CACHE_RELOC 0 + +// Base address <0x0000-0xFFFFFE00:0x200> +// Set buffer base address to RAM areas that support DMA with the drive. +#define MC0_CACHE_ADDR 0x7FD00000 + +// +// Filename Cache Size <0-1000000> +// Define number of cached file or directory names. +// 48 bytes of RAM is required for each cached name. +#define MC0_NAME_CACHE_SIZE 0 + +// Use FAT Journal +// Protect File Allocation Table and Directory Entries for +// fail-safe operation. +#define MC0_FAT_JOURNAL 0 + +// diff --git a/Project/RTE/File_System/FS_Debug.c b/Project/RTE/File_System/FS_Debug.c new file mode 100644 index 0000000..38e37f5 --- /dev/null +++ b/Project/RTE/File_System/FS_Debug.c @@ -0,0 +1,50 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::File System + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: FS_Debug.c + * Purpose: File System Debug Configuration + * Rev.: V1.0.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// File System Debug +// Enable File System event recording +#define FS_DEBUG_EVR_ENABLE 0 + +// Core Management <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsCore: Core Management event recording +#define FS_DEBUG_EVR_CORE 1 + +// FAT File System <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsFAT: FAT File System event recording +#define FS_DEBUG_EVR_FAT 1 + +// EFS File System <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsEFS: EFS File System event recording +#define FS_DEBUG_EVR_EFS 1 + +// I/O Control Interface <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsIOC: I/O Control Interface event recording +#define FS_DEBUG_EVR_IOC 1 + +// NAND Flash Translation Layer <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsNFTL: NAND Flash Translation Layer event recording +#define FS_DEBUG_EVR_NFTL 1 + +// NAND Device Interface <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsNAND: NAND Device Interface event recording +#define FS_DEBUG_EVR_NAND 1 + +// Memory Card MCI <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsMcMCI: Memory Card MCI event recording +#define FS_DEBUG_EVR_MC_MCI 1 + +// Memory Card SPI <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsMcSPI: Memory Card SPI event recording +#define FS_DEBUG_EVR_MC_SPI 1 + +// + +#include "fs_debug.h" diff --git a/Project/RTE/Network/Net_Config.c b/Project/RTE/Network/Net_Config.c new file mode 100644 index 0000000..f72bbaf --- /dev/null +++ b/Project/RTE/Network/Net_Config.c @@ -0,0 +1,173 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::Network + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: Net_Config.c + * Purpose: Network Configuration + * Rev.: V7.1.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Network System Settings +// Global Network System definitions +// Local Host Name +// This is the name under which embedded host can be +// accessed on a local area network. +// Default: "my_host" +#define NET_HOST_NAME "my_host" + +// Memory Pool Size <1536-262144:4> +// This is the size of a memory pool in bytes. Buffers for +// network packets are allocated from this memory pool. +// Default: 12000 bytes +#define NET_MEM_POOL_SIZE 12000 + +// Start System Services +// If enabled, the system will automatically start server services +// (HTTP, FTP, TFTP server, ...) when initializing the network system. +// Default: Enabled +#define NET_START_SERVICE 1 + +// OS Resource Settings +// These settings are used to optimize usage of OS resources. +// Core Thread Stack Size <512-65535:4> +// Default: 1024 bytes +#define NET_THREAD_STACK_SIZE 1024 + +// Core Thread Priority +#define NET_THREAD_PRIORITY osPriorityNormal + +// +// + +//------------- <<< end of configuration section >>> --------------------------- + +#include "RTE_Components.h" + +#ifdef RTE_Network_Interface_ETH_0 +#include "Net_Config_ETH_0.h" +#endif +#ifdef RTE_Network_Interface_ETH_1 +#include "Net_Config_ETH_1.h" +#endif + +#ifdef RTE_Network_Interface_WiFi_0 +#include "Net_Config_WiFi_0.h" +#endif + +#ifdef RTE_Network_Interface_WiFi_1 +#include "Net_Config_WiFi_1.h" +#endif + +#ifdef RTE_Network_Interface_PPP +#include "Net_Config_PPP.h" +#endif + +#ifdef RTE_Network_Interface_SLIP +#include "Net_Config_SLIP.h" +#endif + +#ifdef RTE_Network_Socket_UDP +#include "Net_Config_UDP.h" +#endif +#ifdef RTE_Network_Socket_TCP +#include "Net_Config_TCP.h" +#endif +#ifdef RTE_Network_Socket_BSD +#include "Net_Config_BSD.h" +#endif + +#ifdef RTE_Network_Web_Server_RO +#include "Net_Config_HTTP_Server.h" +#endif +#ifdef RTE_Network_Web_Server_FS +#include "Net_Config_HTTP_Server.h" +#endif + +#ifdef RTE_Network_Telnet_Server +#include "Net_Config_Telnet_Server.h" +#endif + +#ifdef RTE_Network_TFTP_Server +#include "Net_Config_TFTP_Server.h" +#endif +#ifdef RTE_Network_TFTP_Client +#include "Net_Config_TFTP_Client.h" +#endif + +#ifdef RTE_Network_FTP_Server +#include "Net_Config_FTP_Server.h" +#endif +#ifdef RTE_Network_FTP_Client +#include "Net_Config_FTP_Client.h" +#endif + +#ifdef RTE_Network_DNS_Client +#include "Net_Config_DNS_Client.h" +#endif + +#ifdef RTE_Network_SMTP_Client +#include "Net_Config_SMTP_Client.h" +#endif + +#ifdef RTE_Network_SNMP_Agent +#include "Net_Config_SNMP_Agent.h" +#endif + +#ifdef RTE_Network_SNTP_Client +#include "Net_Config_SNTP_Client.h" +#endif + +#include "net_config.h" + +/** +\addtogroup net_genFunc +@{ +*/ +/** + \fn void net_sys_error (NET_ERROR error) + \ingroup net_cores + \brief Network system error handler. +*/ +void net_sys_error (NET_ERROR error) { + /* This function is called when a fatal error is encountered. */ + /* The normal program execution is not possible anymore. */ + + switch (error) { + case NET_ERROR_MEM_ALLOC: + /* Out of memory */ + break; + + case NET_ERROR_MEM_FREE: + /* Trying to release non existing memory block */ + break; + + case NET_ERROR_MEM_CORRUPT: + /* Memory Link pointer corrupted */ + /* More data written than the size of allocated memory block */ + break; + + case NET_ERROR_CONFIG: + /* Network configuration error detected */ + break; + + case NET_ERROR_UDP_ALLOC: + /* Out of UDP Sockets */ + break; + + case NET_ERROR_TCP_ALLOC: + /* Out of TCP Sockets */ + break; + + case NET_ERROR_TCP_STATE: + /* TCP State machine in undefined state */ + break; + } + + /* End-less loop */ + while (1); +} +/** +@} +*/ diff --git a/Project/RTE/Network/Net_Config_ETH_0.h b/Project/RTE/Network/Net_Config_ETH_0.h new file mode 100644 index 0000000..2fac34c --- /dev/null +++ b/Project/RTE/Network/Net_Config_ETH_0.h @@ -0,0 +1,253 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::Network:Interface + * Copyright (c) 2004-2020 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: Net_Config_ETH_0.h + * Purpose: Network Configuration for ETH Interface + * Rev.: V7.3.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Ethernet Network Interface 0 +#define ETH0_ENABLE 1 + +// Connect to hardware via Driver_ETH# <0-255> +// Select driver control block for MAC and PHY interface +#define ETH0_DRIVER 0 + +// MAC Address +// Ethernet MAC Address in text representation +// Value FF-FF-FF-FF-FF-FF is not allowed, +// LSB of first byte must be 0 (an ethernet Multicast bit). +// Default: "1E-30-6C-A2-45-5E" +#define ETH0_MAC_ADDR "1E-30-6C-A2-45-5E" + +// VLAN +// Enable or disable Virtual LAN +#define ETH0_VLAN_ENABLE 0 + +// VLAN Identifier <1-4093> +// A unique 12-bit numeric value +// Default: 1 +#define ETH0_VLAN_ID 1 +// + +// IPv4 +// Enable IPv4 Protocol for Network Interface +#define ETH0_IP4_ENABLE 1 + +// IP Address +// Static IPv4 Address in text representation +// Default: "192.168.0.100" +#define ETH0_IP4_ADDR "192.168.0.100" + +// Subnet mask +// Local Subnet mask in text representation +// Default: "255.255.255.0" +#define ETH0_IP4_MASK "255.255.255.0" + +// Default Gateway +// IP Address of Default Gateway in text representation +// Default: "192.168.0.254" +#define ETH0_IP4_GATEWAY "192.168.0.254" + +// Primary DNS Server +// IP Address of Primary DNS Server in text representation +// Default: "8.8.8.8" +#define ETH0_IP4_PRIMARY_DNS "8.8.8.8" + +// Secondary DNS Server +// IP Address of Secondary DNS Server in text representation +// Default: "8.8.4.4" +#define ETH0_IP4_SECONDARY_DNS "8.8.4.4" + +// IP Fragmentation +// This option enables fragmentation of outgoing IP datagrams, +// and reassembling the fragments of incoming IP datagrams. +// Default: enabled +#define ETH0_IP4_FRAG_ENABLE 1 + +// MTU size <576-1500> +// Maximum Transmission Unit in bytes +// Default: 1500 +#define ETH0_IP4_MTU 1500 +// + +// ARP Address Resolution +// ARP cache and node address resolver settings +// Cache Table size <5-100> +// Number of cached MAC/IP addresses +// Default: 10 +#define ETH0_ARP_TAB_SIZE 10 + +// Cache Timeout in seconds <5-255> +// A timeout for cached hardware/IP addresses +// Default: 150 +#define ETH0_ARP_CACHE_TOUT 150 + +// Number of Retries <0-20> +// Number of Retries to resolve an IP address +// before ARP module gives up +// Default: 4 +#define ETH0_ARP_MAX_RETRY 4 + +// Resend Timeout in seconds <1-10> +// A timeout to resend the ARP Request +// Default: 2 +#define ETH0_ARP_RESEND_TOUT 2 + +// Send Notification on Address changes +// When this option is enabled, the embedded host +// will send a Gratuitous ARP notification at startup, +// or when the device IP address has changed. +// Default: Disabled +#define ETH0_ARP_NOTIFY 0 +// + +// IGMP Group Management +// Enable or disable Internet Group Management Protocol +#define ETH0_IGMP_ENABLE 0 + +// Membership Table size <2-50> +// Number of Groups this host can join +// Default: 5 +#define ETH0_IGMP_TAB_SIZE 5 +// + +// NetBIOS Name Service +// When this option is enabled, the embedded host can be +// accessed by its name on local LAN using NBNS protocol. +#define ETH0_NBNS_ENABLE 1 + +// Dynamic Host Configuration +// When this option is enabled, local IP address, Net Mask +// and Default Gateway are obtained automatically from +// the DHCP Server on local LAN. +#define ETH0_DHCP_ENABLE 1 + +// Vendor Class Identifier +// This value is optional. If specified, it is added +// to DHCP request message, identifying vendor type. +// Default: "" +#define ETH0_DHCP_VCID "" + +// Bootfile Name +// This value is optional. If enabled, the Bootfile Name +// (option 67) is also requested from DHCP server. +// Default: disabled +#define ETH0_DHCP_BOOTFILE 0 + +// NTP Servers +// This value is optional. If enabled, a list of NTP Servers +// (option 42) is also requested from DHCP server. +// Default: disabled +#define ETH0_DHCP_NTP_SERVERS 0 +// + +// Disable ICMP Echo response +#define ETH0_ICMP_NO_ECHO 0 +// + +// IPv6 +// Enable IPv6 Protocol for Network Interface +#define ETH0_IP6_ENABLE 1 + +// IPv6 Address +// Static IPv6 Address in text representation +// Use unspecified address "::" when static +// IPv6 address is not used. +// Default: "fec0::2" +#define ETH0_IP6_ADDR "fec0::2" + +// Subnet prefix-length <1-128> +// Number of bits that define network address +// Default: 64 +#define ETH0_IP6_PREFIX_LEN 64 + +// Default Gateway +// Default Gateway IPv6 Address in text representation +// Default: "fec0::1" +#define ETH0_IP6_GATEWAY "fec0::1" + +// Primary DNS Server +// Primary DNS Server IPv6 Address in text representation +// Default: "2001:4860:4860::8888" +#define ETH0_IP6_PRIMARY_DNS "2001:4860:4860::8888" + +// Secondary DNS Server +// Secondary DNS Server IPv6 Address in text representation +// Default: "2001:4860:4860::8844" +#define ETH0_IP6_SECONDARY_DNS "2001:4860:4860::8844" + +// Neighbor Discovery +// Neighbor cache and node address resolver settings +// Cache Table size <5-100> +// Number of cached node addresses +// Default: 5 +#define ETH0_NDP_TAB_SIZE 5 + +// Cache Timeout in seconds <5-255> +// Timeout for cached node addresses +// Default: 150 +#define ETH0_NDP_CACHE_TOUT 150 + +// Number of Retries <0-20> +// Number of retries to resolve an IP address +// before NDP module gives up +// Default: 4 +#define ETH0_NDP_MAX_RETRY 4 + +// Resend Timeout in seconds <1-10> +// A timeout to resend Neighbor Solicitation +// Default: 2 +#define ETH0_NDP_RESEND_TOUT 2 +// + +// Dynamic Host Configuration +// When this option is enabled, local IPv6 address is +// automatically configured. +#define ETH0_DHCP6_ENABLE 1 + +// DHCPv6 Client Mode <0=>Stateless Mode <1=>Statefull Mode +// Stateless DHCPv6 Client uses router advertisements +// for IPv6 address autoconfiguration (SLAAC). +// Statefull DHCPv6 Client connects to DHCPv6 server for a +// leased IPv6 address and DNS server IPv6 addresses. +#define ETH0_DHCP6_MODE 1 + +// Vendor Class Option +// If enabled, Vendor Class option is added to DHCPv6 +// request message, identifying vendor type. +// Default: disabled +#define ETH0_DHCP6_VCLASS_ENABLE 0 + +// Enterprise ID +// Enterprise-number as registered with IANA. +// Default: 0 (Reserved) +#define ETH0_DHCP6_VCLASS_EID 0 + +// Vendor Class Data +// This string identifies vendor type. +// Default: "" +#define ETH0_DHCP6_VCLASS_DATA "" +// +// + +// Disable ICMP6 Echo response +#define ETH0_ICMP6_NO_ECHO 0 +// + +// OS Resource Settings +// These settings are used to optimize usage of OS resources. +// Interface Thread Stack Size <512-65535:4> +// Default: 512 bytes +#define ETH0_THREAD_STACK_SIZE 512 + +// Interface Thread Priority +#define ETH0_THREAD_PRIORITY osPriorityAboveNormal + +// +// + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/Project/RTE/Network/Net_Config_TCP.h b/Project/RTE/Network/Net_Config_TCP.h new file mode 100644 index 0000000..79ba88c --- /dev/null +++ b/Project/RTE/Network/Net_Config_TCP.h @@ -0,0 +1,69 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::Network:Socket + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: Net_Config_TCP.h + * Purpose: Network Configuration for TCP Sockets + * Rev.: V7.1.1 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// TCP Sockets +#define TCP_ENABLE 1 + +// Number of TCP Sockets <1-20> +// Number of available TCP sockets +// Default: 6 +#define TCP_NUM_SOCKS 6 + +// Number of Retries <0-20> +// How many times TCP module will try to retransmit data +// before giving up. Increase this value for high-latency +// and low throughput networks. +// Default: 5 +#define TCP_MAX_RETRY 5 + +// Retry Timeout in seconds <1-10> +// If data frame not acknowledged within this time frame, +// TCP module will try to resend the data again. +// Default: 4 +#define TCP_RETRY_TOUT 4 + +// Default Connect Timeout in seconds <1-65535> +// If no TCP data frame has been exchanged during this time, +// the TCP connection is either closed or a keep-alive frame +// is sent to verify that the connection still exists. +// Default: 120 +#define TCP_DEFAULT_TOUT 120 + +// Maximum Segment Size <536-1440> +// The Maximum Segment Size specifies the maximum +// number of bytes in the TCP segment's Data field. +// Default: 1440 +#define TCP_MAX_SEG_SIZE 1440 + +// Receive Window Size <536-65535> +// Receive Window Size specifies the size of data, +// that the socket is able to buffer in flow-control mode. +// Default: 4320 +#define TCP_RECEIVE_WIN_SIZE 4320 + +// + +// TCP Initial Retransmit period in seconds +#define TCP_INITIAL_RETRY_TOUT 1 + +// TCP SYN frame retransmit period in seconds +#define TCP_SYN_RETRY_TOUT 2 + +// Number of retries to establish a connection +#define TCP_CONNECT_RETRY 7 + +// Dynamic port start (default 49152) +#define TCP_DYN_PORT_START 49152 + +// Dynamic port end (default 65535) +#define TCP_DYN_PORT_END 65535 + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/Project/RTE/RTOS/board.c b/Project/RTE/RTOS/board.c new file mode 100644 index 0000000..7b3b1e8 --- /dev/null +++ b/Project/RTE/RTOS/board.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-24 the first version + */ + +#include +#include +#include "bsp.h" + +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) +/* + * Please modify RT_HEAP_SIZE if you enable RT_USING_HEAP + * the RT_HEAP_SIZE max value = (sram size - ZI size), 1024 means 1024 bytes + */ +#define RT_HEAP_SIZE (32*1024) +static rt_uint8_t rt_heap[RT_HEAP_SIZE]; + +RT_WEAK void *rt_heap_begin_get(void) +{ + return rt_heap; +} + +RT_WEAK void *rt_heap_end_get(void) +{ + return rt_heap + RT_HEAP_SIZE; +} +#endif + +void rt_os_tick_callback(void) +{ + rt_interrupt_enter(); + + rt_tick_increase(); + + rt_interrupt_leave(); +} + +void SysTick_IrqHandler(void) +{ + rt_os_tick_callback(); +} + +/** + * This function will initial your board. + */ +void rt_hw_board_init(void) +{ +//#error "TODO 1: OS Tick Configuration." + BSP_Init(); + /* + * TODO 1: OS Tick Configuration + * Enable the hardware timer and call the rt_os_tick_callback function + * periodically with the frequency RT_TICK_PER_SECOND. + */ + + /* Call components board initial (use INIT_BOARD_EXPORT()) */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) + rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get()); +#endif +} + +#ifdef RT_USING_CONSOLE + +static int uart_init(void) +{ +//#error "TODO 2: Enable the hardware uart and config baudrate." + DbgUart_Config(500000); + return 0; +} +INIT_BOARD_EXPORT(uart_init); + +void rt_hw_console_output(const char *str) +{ +//#error "TODO 3: Output the string 'str' through the uart." + rt_enter_critical(); + DebugUartSend((uint8_t *)str, strlen(str)); + rt_exit_critical(); +} + +#endif + diff --git a/Project/RTE/RTOS/board.c.base@3.1.5 b/Project/RTE/RTOS/board.c.base@3.1.5 new file mode 100644 index 0000000..e45e75f --- /dev/null +++ b/Project/RTE/RTOS/board.c.base@3.1.5 @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-24 the first version + */ + +#include +#include + +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) +/* + * Please modify RT_HEAP_SIZE if you enable RT_USING_HEAP + * the RT_HEAP_SIZE max value = (sram size - ZI size), 1024 means 1024 bytes + */ +#define RT_HEAP_SIZE (15*1024) +static rt_uint8_t rt_heap[RT_HEAP_SIZE]; + +RT_WEAK void *rt_heap_begin_get(void) +{ + return rt_heap; +} + +RT_WEAK void *rt_heap_end_get(void) +{ + return rt_heap + RT_HEAP_SIZE; +} +#endif + +void rt_os_tick_callback(void) +{ + rt_interrupt_enter(); + + rt_tick_increase(); + + rt_interrupt_leave(); +} + +/** + * This function will initial your board. + */ +void rt_hw_board_init(void) +{ +#error "TODO 1: OS Tick Configuration." + /* + * TODO 1: OS Tick Configuration + * Enable the hardware timer and call the rt_os_tick_callback function + * periodically with the frequency RT_TICK_PER_SECOND. + */ + + /* Call components board initial (use INIT_BOARD_EXPORT()) */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) + rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get()); +#endif +} + +#ifdef RT_USING_CONSOLE + +static int uart_init(void) +{ +#error "TODO 2: Enable the hardware uart and config baudrate." + return 0; +} +INIT_BOARD_EXPORT(uart_init); + +void rt_hw_console_output(const char *str) +{ +#error "TODO 3: Output the string 'str' through the uart." +} + +#endif + diff --git a/Project/RTE/RTOS/rtconfig.h b/Project/RTE/RTOS/rtconfig.h new file mode 100644 index 0000000..0aa25fe --- /dev/null +++ b/Project/RTE/RTOS/rtconfig.h @@ -0,0 +1,139 @@ +/* RT-Thread config file */ + +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic Configuration +// Maximal level of thread priority <8-256> +// Default: 32 +#define RT_THREAD_PRIORITY_MAX 16 +// OS tick per second +// Default: 1000 (1ms) +#define RT_TICK_PER_SECOND 1000 +// Alignment size for CPU architecture data access +// Default: 4 +#define RT_ALIGN_SIZE 4 +// the max length of object name<2-16> +// Default: 8 +#define RT_NAME_MAX 10 +// Using RT-Thread components initialization +// Using RT-Thread components initialization +#define RT_USING_COMPONENTS_INIT +// + +#define RT_USING_USER_MAIN + +// the stack size of main thread<1-4086> +// Default: 512 +#define RT_MAIN_THREAD_STACK_SIZE 512 + +// + +// Debug Configuration +// enable kernel debug configuration +// Default: enable kernel debug configuration +//#define RT_DEBUG +// +// enable components initialization debug configuration<0-1> +// Default: 0 +#define RT_DEBUG_INIT 0 +// thread stack over flow detect +// Diable Thread stack over flow detect +//#define RT_USING_OVERFLOW_CHECK +// +// + +// Hook Configuration +// using hook +// using hook +//#define RT_USING_HOOK +// +// using idle hook +// using idle hook +//#define RT_USING_IDLE_HOOK +// +// + +// Software timers Configuration +// Enables user timers +#define RT_USING_TIMER_SOFT 0 +#if RT_USING_TIMER_SOFT == 0 + #undef RT_USING_TIMER_SOFT +#endif +// The priority level of timer thread <0-31> +// Default: 4 +#define RT_TIMER_THREAD_PRIO 4 +// The stack size of timer thread <0-8192> +// Default: 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 +// + +// IPC(Inter-process communication) Configuration +// Using Semaphore +// Using Semaphore +#define RT_USING_SEMAPHORE +// +// Using Mutex +// Using Mutex +#define RT_USING_MUTEX +// +// Using Event +// Using Event +//#define RT_USING_EVENT +// +// Using MailBox +// Using MailBox +#define RT_USING_MAILBOX +// +// Using Message Queue +// Using Message Queue +#define RT_USING_MESSAGEQUEUE +// +// + +// Memory Management Configuration +// Memory Pool Management +// Memory Pool Management +//#define RT_USING_MEMPOOL +// +// Dynamic Heap Management(Algorithm: small memory ) +// Dynamic Heap Management +#define RT_USING_HEAP +#define RT_USING_SMALL_MEM +// +// using tiny size of memory +// using tiny size of memory +//#define RT_USING_TINY_SIZE +// +// + +// Console Configuration +// Using console +// Using console +#define RT_USING_CONSOLE +// +// the buffer size of console <1-1024> +// the buffer size of console +// Default: 128 (128Byte) +#define RT_CONSOLEBUF_SIZE 512 +// + +// FinSH Configuration +// include finsh config +// Select this choice if you using FinSH +//#include "finsh_config.h" +// +// + +// Device Configuration +// using device framework +// using device framework +//#define RT_USING_DEVICE +// +// + +// <<< end of configuration section >>> + +#endif diff --git a/Project/RTE/RTOS/rtconfig.h.base@3.1.5 b/Project/RTE/RTOS/rtconfig.h.base@3.1.5 new file mode 100644 index 0000000..5b54665 --- /dev/null +++ b/Project/RTE/RTOS/rtconfig.h.base@3.1.5 @@ -0,0 +1,139 @@ +/* RT-Thread config file */ + +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic Configuration +// Maximal level of thread priority <8-256> +// Default: 32 +#define RT_THREAD_PRIORITY_MAX 32 +// OS tick per second +// Default: 1000 (1ms) +#define RT_TICK_PER_SECOND 1000 +// Alignment size for CPU architecture data access +// Default: 4 +#define RT_ALIGN_SIZE 4 +// the max length of object name<2-16> +// Default: 8 +#define RT_NAME_MAX 8 +// Using RT-Thread components initialization +// Using RT-Thread components initialization +#define RT_USING_COMPONENTS_INIT +// + +#define RT_USING_USER_MAIN + +// the stack size of main thread<1-4086> +// Default: 512 +#define RT_MAIN_THREAD_STACK_SIZE 256 + +// + +// Debug Configuration +// enable kernel debug configuration +// Default: enable kernel debug configuration +//#define RT_DEBUG +// +// enable components initialization debug configuration<0-1> +// Default: 0 +#define RT_DEBUG_INIT 0 +// thread stack over flow detect +// Diable Thread stack over flow detect +//#define RT_USING_OVERFLOW_CHECK +// +// + +// Hook Configuration +// using hook +// using hook +//#define RT_USING_HOOK +// +// using idle hook +// using idle hook +//#define RT_USING_IDLE_HOOK +// +// + +// Software timers Configuration +// Enables user timers +#define RT_USING_TIMER_SOFT 0 +#if RT_USING_TIMER_SOFT == 0 + #undef RT_USING_TIMER_SOFT +#endif +// The priority level of timer thread <0-31> +// Default: 4 +#define RT_TIMER_THREAD_PRIO 4 +// The stack size of timer thread <0-8192> +// Default: 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 +// + +// IPC(Inter-process communication) Configuration +// Using Semaphore +// Using Semaphore +#define RT_USING_SEMAPHORE +// +// Using Mutex +// Using Mutex +//#define RT_USING_MUTEX +// +// Using Event +// Using Event +//#define RT_USING_EVENT +// +// Using MailBox +// Using MailBox +#define RT_USING_MAILBOX +// +// Using Message Queue +// Using Message Queue +//#define RT_USING_MESSAGEQUEUE +// +// + +// Memory Management Configuration +// Memory Pool Management +// Memory Pool Management +//#define RT_USING_MEMPOOL +// +// Dynamic Heap Management(Algorithm: small memory ) +// Dynamic Heap Management +#define RT_USING_HEAP +#define RT_USING_SMALL_MEM +// +// using tiny size of memory +// using tiny size of memory +//#define RT_USING_TINY_SIZE +// +// + +// Console Configuration +// Using console +// Using console +//#define RT_USING_CONSOLE +// +// the buffer size of console <1-1024> +// the buffer size of console +// Default: 128 (128Byte) +#define RT_CONSOLEBUF_SIZE 256 +// + +// FinSH Configuration +// include finsh config +// Select this choice if you using FinSH +//#include "finsh_config.h" +// +// + +// Device Configuration +// using device framework +// using device framework +//#define RT_USING_DEVICE +// +// + +// <<< end of configuration section >>> + +#endif diff --git a/Project/RTE/_Debug/RTE_Components.h b/Project/RTE/_Debug/RTE_Components.h new file mode 100644 index 0000000..e54c9c5 --- /dev/null +++ b/Project/RTE/_Debug/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'BootLoader' + * Target: 'Debug' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "HC32F460PETB.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Project/RTE/_Release/RTE_Components.h b/Project/RTE/_Release/RTE_Components.h new file mode 100644 index 0000000..99cee87 --- /dev/null +++ b/Project/RTE/_Release/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'BootLoader' + * Target: 'Release' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "HC32F460KETA.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Project/RTE/_i2c_24c256_Debug/RTE_Components.h b/Project/RTE/_i2c_24c256_Debug/RTE_Components.h new file mode 100644 index 0000000..bf25b8a --- /dev/null +++ b/Project/RTE/_i2c_24c256_Debug/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'DigitalModule_4Ch' + * Target: 'i2c_24c256_Debug' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "HC32F460PETB.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Project/RTE/_i2c_24c256_Release/RTE_Components.h b/Project/RTE/_i2c_24c256_Release/RTE_Components.h new file mode 100644 index 0000000..b3756ae --- /dev/null +++ b/Project/RTE/_i2c_24c256_Release/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'DigitalModule_4Ch' + * Target: 'i2c_24c256_Release' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "HC32F460PETB.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Project/RTE/_template_Debug/RTE_Components.h b/Project/RTE/_template_Debug/RTE_Components.h new file mode 100644 index 0000000..114830a --- /dev/null +++ b/Project/RTE/_template_Debug/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'DigitalModule_4Ch' + * Target: 'template_Debug' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "HC32F460PETB.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Project/startup_hc32f460.s b/Project/startup_hc32f460.s new file mode 100644 index 0000000..52a327d --- /dev/null +++ b/Project/startup_hc32f460.s @@ -0,0 +1,621 @@ +;/****************************************************************************** +; * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by HDSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +;/*****************************************************************************/ +;/* Startup for ARM */ +;/* Version V1.0 */ +;/* Date 2018-10-13 */ +;/* Target-mcu HC32F460 */ +;/*****************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00008000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Peripheral Interrupts + DCD IRQ000_Handler ; IRQ000_Handler + DCD IRQ001_Handler ; IRQ001_Handler + DCD IRQ002_Handler ; IRQ002_Handler + DCD IRQ003_Handler ; IRQ003_Handler + DCD IRQ004_Handler ; IRQ004_Handler + DCD IRQ005_Handler ; IRQ005_Handler + DCD IRQ006_Handler ; IRQ006_Handler + DCD IRQ007_Handler ; IRQ007_Handler + DCD IRQ008_Handler ; IRQ008_Handler + DCD IRQ009_Handler ; IRQ009_Handler + DCD IRQ010_Handler ; IRQ010_Handler + DCD IRQ011_Handler ; IRQ011_Handler + DCD IRQ012_Handler ; IRQ012_Handler + DCD IRQ013_Handler ; IRQ013_Handler + DCD IRQ014_Handler ; IRQ014_Handler + DCD IRQ015_Handler ; IRQ015_Handler + DCD IRQ016_Handler ; IRQ016_Handler + DCD IRQ017_Handler ; IRQ017_Handler + DCD IRQ018_Handler ; IRQ018_Handler + DCD IRQ019_Handler ; IRQ019_Handler + DCD IRQ020_Handler ; IRQ020_Handler + DCD IRQ021_Handler ; IRQ021_Handler + DCD IRQ022_Handler ; IRQ022_Handler + DCD IRQ023_Handler ; IRQ023_Handler + DCD IRQ024_Handler ; IRQ024_Handler + DCD IRQ025_Handler ; IRQ025_Handler + DCD IRQ026_Handler ; IRQ026_Handler + DCD IRQ027_Handler ; IRQ027_Handler + DCD IRQ028_Handler ; IRQ028_Handler + DCD IRQ029_Handler ; IRQ029_Handler + DCD IRQ030_Handler ; IRQ030_Handler + DCD IRQ031_Handler ; IRQ031_Handler + DCD IRQ032_Handler ; IRQ032_Handler + DCD IRQ033_Handler ; IRQ033_Handler + DCD IRQ034_Handler ; IRQ034_Handler + DCD IRQ035_Handler ; IRQ035_Handler + DCD IRQ036_Handler ; IRQ036_Handler + DCD IRQ037_Handler ; IRQ037_Handler + DCD IRQ038_Handler ; IRQ038_Handler + DCD IRQ039_Handler ; IRQ039_Handler + DCD IRQ040_Handler ; IRQ040_Handler + DCD IRQ041_Handler ; IRQ041_Handler + DCD IRQ042_Handler ; IRQ042_Handler + DCD IRQ043_Handler ; IRQ043_Handler + DCD IRQ044_Handler ; IRQ044_Handler + DCD IRQ045_Handler ; IRQ045_Handler + DCD IRQ046_Handler ; IRQ046_Handler + DCD IRQ047_Handler ; IRQ047_Handler + DCD IRQ048_Handler ; IRQ048_Handler + DCD IRQ049_Handler ; IRQ049_Handler + DCD IRQ050_Handler ; IRQ050_Handler + DCD IRQ051_Handler ; IRQ051_Handler + DCD IRQ052_Handler ; IRQ052_Handler + DCD IRQ053_Handler ; IRQ053_Handler + DCD IRQ054_Handler ; IRQ054_Handler + DCD IRQ055_Handler ; IRQ055_Handler + DCD IRQ056_Handler ; IRQ056_Handler + DCD IRQ057_Handler ; IRQ057_Handler + DCD IRQ058_Handler ; IRQ058_Handler + DCD IRQ059_Handler ; IRQ059_Handler + DCD IRQ060_Handler ; IRQ060_Handler + DCD IRQ061_Handler ; IRQ061_Handler + DCD IRQ062_Handler ; IRQ062_Handler + DCD IRQ063_Handler ; IRQ063_Handler + DCD IRQ064_Handler ; IRQ064_Handler + DCD IRQ065_Handler ; IRQ065_Handler + DCD IRQ066_Handler ; IRQ066_Handler + DCD IRQ067_Handler ; IRQ067_Handler + DCD IRQ068_Handler ; IRQ068_Handler + DCD IRQ069_Handler ; IRQ069_Handler + DCD IRQ070_Handler ; IRQ070_Handler + DCD IRQ071_Handler ; IRQ071_Handler + DCD IRQ072_Handler ; IRQ072_Handler + DCD IRQ073_Handler ; IRQ073_Handler + DCD IRQ074_Handler ; IRQ074_Handler + DCD IRQ075_Handler ; IRQ075_Handler + DCD IRQ076_Handler ; IRQ076_Handler + DCD IRQ077_Handler ; IRQ077_Handler + DCD IRQ078_Handler ; IRQ078_Handler + DCD IRQ079_Handler ; IRQ079_Handler + DCD IRQ080_Handler ; IRQ080_Handler + DCD IRQ081_Handler ; IRQ081_Handler + DCD IRQ082_Handler ; IRQ082_Handler + DCD IRQ083_Handler ; IRQ083_Handler + DCD IRQ084_Handler ; IRQ084_Handler + DCD IRQ085_Handler ; IRQ085_Handler + DCD IRQ086_Handler ; IRQ086_Handler + DCD IRQ087_Handler ; IRQ087_Handler + DCD IRQ088_Handler ; IRQ088_Handler + DCD IRQ089_Handler ; IRQ089_Handler + DCD IRQ090_Handler ; IRQ090_Handler + DCD IRQ091_Handler ; IRQ091_Handler + DCD IRQ092_Handler ; IRQ092_Handler + DCD IRQ093_Handler ; IRQ093_Handler + DCD IRQ094_Handler ; IRQ094_Handler + DCD IRQ095_Handler ; IRQ095_Handler + DCD IRQ096_Handler ; IRQ096_Handler + DCD IRQ097_Handler ; IRQ097_Handler + DCD IRQ098_Handler ; IRQ098_Handler + DCD IRQ099_Handler ; IRQ099_Handler + DCD IRQ100_Handler ; IRQ100_Handler + DCD IRQ101_Handler ; IRQ101_Handler + DCD IRQ102_Handler ; IRQ102_Handler + DCD IRQ103_Handler ; IRQ103_Handler + DCD IRQ104_Handler ; IRQ104_Handler + DCD IRQ105_Handler ; IRQ105_Handler + DCD IRQ106_Handler ; IRQ106_Handler + DCD IRQ107_Handler ; IRQ107_Handler + DCD IRQ108_Handler ; IRQ108_Handler + DCD IRQ109_Handler ; IRQ109_Handler + DCD IRQ110_Handler ; IRQ110_Handler + DCD IRQ111_Handler ; IRQ111_Handler + DCD IRQ112_Handler ; IRQ112_Handler + DCD IRQ113_Handler ; IRQ113_Handler + DCD IRQ114_Handler ; IRQ114_Handler + DCD IRQ115_Handler ; IRQ115_Handler + DCD IRQ116_Handler ; IRQ116_Handler + DCD IRQ117_Handler ; IRQ117_Handler + DCD IRQ118_Handler ; IRQ118_Handler + DCD IRQ119_Handler ; IRQ119_Handler + DCD IRQ120_Handler ; IRQ120_Handler + DCD IRQ121_Handler ; IRQ121_Handler + DCD IRQ122_Handler ; IRQ122_Handler + DCD IRQ123_Handler ; IRQ123_Handler + DCD IRQ124_Handler ; IRQ124_Handler + DCD IRQ125_Handler ; IRQ125_Handler + DCD IRQ126_Handler ; IRQ126_Handler + DCD IRQ127_Handler ; IRQ127_Handler + DCD IRQ128_Handler ; IRQ128_Handler + DCD IRQ129_Handler ; IRQ129_Handler + DCD IRQ130_Handler ; IRQ130_Handler + DCD IRQ131_Handler ; IRQ131_Handler + DCD IRQ132_Handler ; IRQ132_Handler + DCD IRQ133_Handler ; IRQ133_Handler + DCD IRQ134_Handler ; IRQ134_Handler + DCD IRQ135_Handler ; IRQ135_Handler + DCD IRQ136_Handler ; IRQ136_Handler + DCD IRQ137_Handler ; IRQ137_Handler + DCD IRQ138_Handler ; IRQ138_Handler + DCD IRQ139_Handler ; IRQ139_Handler + DCD IRQ140_Handler ; IRQ140_Handler + DCD IRQ141_Handler ; IRQ141_Handler + DCD IRQ142_Handler ; IRQ142_Handler + DCD IRQ143_Handler ; IRQ143_Handler + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main +SET_SRAM3_WAIT + LDR R0, =0x40050804 + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x40050800 + MOV R1, #0x1100 + STR R1, [R0] + + LDR R0, =0x40050804 + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT IRQ000_Handler [WEAK] + EXPORT IRQ001_Handler [WEAK] + EXPORT IRQ002_Handler [WEAK] + EXPORT IRQ003_Handler [WEAK] + EXPORT IRQ004_Handler [WEAK] + EXPORT IRQ005_Handler [WEAK] + EXPORT IRQ006_Handler [WEAK] + EXPORT IRQ007_Handler [WEAK] + EXPORT IRQ008_Handler [WEAK] + EXPORT IRQ009_Handler [WEAK] + EXPORT IRQ010_Handler [WEAK] + EXPORT IRQ011_Handler [WEAK] + EXPORT IRQ012_Handler [WEAK] + EXPORT IRQ013_Handler [WEAK] + EXPORT IRQ014_Handler [WEAK] + EXPORT IRQ015_Handler [WEAK] + EXPORT IRQ016_Handler [WEAK] + EXPORT IRQ017_Handler [WEAK] + EXPORT IRQ018_Handler [WEAK] + EXPORT IRQ019_Handler [WEAK] + EXPORT IRQ020_Handler [WEAK] + EXPORT IRQ021_Handler [WEAK] + EXPORT IRQ022_Handler [WEAK] + EXPORT IRQ023_Handler [WEAK] + EXPORT IRQ024_Handler [WEAK] + EXPORT IRQ025_Handler [WEAK] + EXPORT IRQ026_Handler [WEAK] + EXPORT IRQ027_Handler [WEAK] + EXPORT IRQ028_Handler [WEAK] + EXPORT IRQ029_Handler [WEAK] + EXPORT IRQ030_Handler [WEAK] + EXPORT IRQ031_Handler [WEAK] + EXPORT IRQ032_Handler [WEAK] + EXPORT IRQ033_Handler [WEAK] + EXPORT IRQ034_Handler [WEAK] + EXPORT IRQ035_Handler [WEAK] + EXPORT IRQ036_Handler [WEAK] + EXPORT IRQ037_Handler [WEAK] + EXPORT IRQ038_Handler [WEAK] + EXPORT IRQ039_Handler [WEAK] + EXPORT IRQ040_Handler [WEAK] + EXPORT IRQ041_Handler [WEAK] + EXPORT IRQ042_Handler [WEAK] + EXPORT IRQ043_Handler [WEAK] + EXPORT IRQ044_Handler [WEAK] + EXPORT IRQ045_Handler [WEAK] + EXPORT IRQ046_Handler [WEAK] + EXPORT IRQ047_Handler [WEAK] + EXPORT IRQ048_Handler [WEAK] + EXPORT IRQ049_Handler [WEAK] + EXPORT IRQ050_Handler [WEAK] + EXPORT IRQ051_Handler [WEAK] + EXPORT IRQ052_Handler [WEAK] + EXPORT IRQ053_Handler [WEAK] + EXPORT IRQ054_Handler [WEAK] + EXPORT IRQ055_Handler [WEAK] + EXPORT IRQ056_Handler [WEAK] + EXPORT IRQ057_Handler [WEAK] + EXPORT IRQ058_Handler [WEAK] + EXPORT IRQ059_Handler [WEAK] + EXPORT IRQ060_Handler [WEAK] + EXPORT IRQ061_Handler [WEAK] + EXPORT IRQ062_Handler [WEAK] + EXPORT IRQ063_Handler [WEAK] + EXPORT IRQ064_Handler [WEAK] + EXPORT IRQ065_Handler [WEAK] + EXPORT IRQ066_Handler [WEAK] + EXPORT IRQ067_Handler [WEAK] + EXPORT IRQ068_Handler [WEAK] + EXPORT IRQ069_Handler [WEAK] + EXPORT IRQ070_Handler [WEAK] + EXPORT IRQ071_Handler [WEAK] + EXPORT IRQ072_Handler [WEAK] + EXPORT IRQ073_Handler [WEAK] + EXPORT IRQ074_Handler [WEAK] + EXPORT IRQ075_Handler [WEAK] + EXPORT IRQ076_Handler [WEAK] + EXPORT IRQ077_Handler [WEAK] + EXPORT IRQ078_Handler [WEAK] + EXPORT IRQ079_Handler [WEAK] + EXPORT IRQ080_Handler [WEAK] + EXPORT IRQ081_Handler [WEAK] + EXPORT IRQ082_Handler [WEAK] + EXPORT IRQ083_Handler [WEAK] + EXPORT IRQ084_Handler [WEAK] + EXPORT IRQ085_Handler [WEAK] + EXPORT IRQ086_Handler [WEAK] + EXPORT IRQ087_Handler [WEAK] + EXPORT IRQ088_Handler [WEAK] + EXPORT IRQ089_Handler [WEAK] + EXPORT IRQ090_Handler [WEAK] + EXPORT IRQ091_Handler [WEAK] + EXPORT IRQ092_Handler [WEAK] + EXPORT IRQ093_Handler [WEAK] + EXPORT IRQ094_Handler [WEAK] + EXPORT IRQ095_Handler [WEAK] + EXPORT IRQ096_Handler [WEAK] + EXPORT IRQ097_Handler [WEAK] + EXPORT IRQ098_Handler [WEAK] + EXPORT IRQ099_Handler [WEAK] + EXPORT IRQ100_Handler [WEAK] + EXPORT IRQ101_Handler [WEAK] + EXPORT IRQ102_Handler [WEAK] + EXPORT IRQ103_Handler [WEAK] + EXPORT IRQ104_Handler [WEAK] + EXPORT IRQ105_Handler [WEAK] + EXPORT IRQ106_Handler [WEAK] + EXPORT IRQ107_Handler [WEAK] + EXPORT IRQ108_Handler [WEAK] + EXPORT IRQ109_Handler [WEAK] + EXPORT IRQ110_Handler [WEAK] + EXPORT IRQ111_Handler [WEAK] + EXPORT IRQ112_Handler [WEAK] + EXPORT IRQ113_Handler [WEAK] + EXPORT IRQ114_Handler [WEAK] + EXPORT IRQ115_Handler [WEAK] + EXPORT IRQ116_Handler [WEAK] + EXPORT IRQ117_Handler [WEAK] + EXPORT IRQ118_Handler [WEAK] + EXPORT IRQ119_Handler [WEAK] + EXPORT IRQ120_Handler [WEAK] + EXPORT IRQ121_Handler [WEAK] + EXPORT IRQ122_Handler [WEAK] + EXPORT IRQ123_Handler [WEAK] + EXPORT IRQ124_Handler [WEAK] + EXPORT IRQ125_Handler [WEAK] + EXPORT IRQ126_Handler [WEAK] + EXPORT IRQ127_Handler [WEAK] + EXPORT IRQ128_Handler [WEAK] + EXPORT IRQ129_Handler [WEAK] + EXPORT IRQ130_Handler [WEAK] + EXPORT IRQ131_Handler [WEAK] + EXPORT IRQ132_Handler [WEAK] + EXPORT IRQ133_Handler [WEAK] + EXPORT IRQ134_Handler [WEAK] + EXPORT IRQ135_Handler [WEAK] + EXPORT IRQ136_Handler [WEAK] + EXPORT IRQ137_Handler [WEAK] + EXPORT IRQ138_Handler [WEAK] + EXPORT IRQ139_Handler [WEAK] + EXPORT IRQ140_Handler [WEAK] + EXPORT IRQ141_Handler [WEAK] + EXPORT IRQ142_Handler [WEAK] + EXPORT IRQ143_Handler [WEAK] +IRQ000_Handler +IRQ001_Handler +IRQ002_Handler +IRQ003_Handler +IRQ004_Handler +IRQ005_Handler +IRQ006_Handler +IRQ007_Handler +IRQ008_Handler +IRQ009_Handler +IRQ010_Handler +IRQ011_Handler +IRQ012_Handler +IRQ013_Handler +IRQ014_Handler +IRQ015_Handler +IRQ016_Handler +IRQ017_Handler +IRQ018_Handler +IRQ019_Handler +IRQ020_Handler +IRQ021_Handler +IRQ022_Handler +IRQ023_Handler +IRQ024_Handler +IRQ025_Handler +IRQ026_Handler +IRQ027_Handler +IRQ028_Handler +IRQ029_Handler +IRQ030_Handler +IRQ031_Handler +IRQ032_Handler +IRQ033_Handler +IRQ034_Handler +IRQ035_Handler +IRQ036_Handler +IRQ037_Handler +IRQ038_Handler +IRQ039_Handler +IRQ040_Handler +IRQ041_Handler +IRQ042_Handler +IRQ043_Handler +IRQ044_Handler +IRQ045_Handler +IRQ046_Handler +IRQ047_Handler +IRQ048_Handler +IRQ049_Handler +IRQ050_Handler +IRQ051_Handler +IRQ052_Handler +IRQ053_Handler +IRQ054_Handler +IRQ055_Handler +IRQ056_Handler +IRQ057_Handler +IRQ058_Handler +IRQ059_Handler +IRQ060_Handler +IRQ061_Handler +IRQ062_Handler +IRQ063_Handler +IRQ064_Handler +IRQ065_Handler +IRQ066_Handler +IRQ067_Handler +IRQ068_Handler +IRQ069_Handler +IRQ070_Handler +IRQ071_Handler +IRQ072_Handler +IRQ073_Handler +IRQ074_Handler +IRQ075_Handler +IRQ076_Handler +IRQ077_Handler +IRQ078_Handler +IRQ079_Handler +IRQ080_Handler +IRQ081_Handler +IRQ082_Handler +IRQ083_Handler +IRQ084_Handler +IRQ085_Handler +IRQ086_Handler +IRQ087_Handler +IRQ088_Handler +IRQ089_Handler +IRQ090_Handler +IRQ091_Handler +IRQ092_Handler +IRQ093_Handler +IRQ094_Handler +IRQ095_Handler +IRQ096_Handler +IRQ097_Handler +IRQ098_Handler +IRQ099_Handler +IRQ100_Handler +IRQ101_Handler +IRQ102_Handler +IRQ103_Handler +IRQ104_Handler +IRQ105_Handler +IRQ106_Handler +IRQ107_Handler +IRQ108_Handler +IRQ109_Handler +IRQ110_Handler +IRQ111_Handler +IRQ112_Handler +IRQ113_Handler +IRQ114_Handler +IRQ115_Handler +IRQ116_Handler +IRQ117_Handler +IRQ118_Handler +IRQ119_Handler +IRQ120_Handler +IRQ121_Handler +IRQ122_Handler +IRQ123_Handler +IRQ124_Handler +IRQ125_Handler +IRQ126_Handler +IRQ127_Handler +IRQ128_Handler +IRQ129_Handler +IRQ130_Handler +IRQ131_Handler +IRQ132_Handler +IRQ133_Handler +IRQ134_Handler +IRQ135_Handler +IRQ136_Handler +IRQ137_Handler +IRQ138_Handler +IRQ139_Handler +IRQ140_Handler +IRQ141_Handler +IRQ142_Handler +IRQ143_Handler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/components/ringbuffer.c b/components/ringbuffer.c new file mode 100644 index 0000000..225076b --- /dev/null +++ b/components/ringbuffer.c @@ -0,0 +1,89 @@ +/****************************************************************************** + * @brief »·Ðλº³åÇø¹ÜÀí(²Î¿¼linux/kfifo) + * + * Copyright (c) 2016~2020, + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2016-05-30 Morro ³õ°æÍê³É + ******************************************************************************/ +#include "ringbuffer.h" +#include +#include + +#define min(a,b) ( (a) < (b) )? (a):(b) + +/* + *@brief ¹¹ÔìÒ»¸ö¿Õ»·Ðλº³åÇø + *@param[in] r - »·Ðλº³åÇø¹ÜÀíÆ÷ + *@param[in] buf - Êý¾Ý»º³åÇø + *@param[in] len - buf³¤¶È(±ØÐëÊÇ2µÄN´ÎÃÝ) + *@retval bool + */ +bool ring_buf_init(ring_buf_t *r,unsigned char *buf, unsigned int len) +{ + r->buf = buf; + r->size = len; + r->front = r->rear = 0; + return (buf != NULL) && ((len & len -1) == 0); +} + +/* + *@brief Çå¿Õ»·Ðλº³åÇø + *@param[in] r - ´ýÇå¿ÕµÄ»·Ðλº³åÇø + *@retval none + */ +void ring_buf_clr(ring_buf_t *r) +{ + r->front = r->rear = 0; +} + +/* + *@brief »ñÈ¡»·Ðλº³åÇøÊý¾Ý³¤¶È + *@retval »·Ðλº³åÇøÖÐÓÐЧ×Ö½ÚÊý + */ +int ring_buf_len(ring_buf_t *r) +{ + return r->rear - r->front; +} + +/* + *@brief ½«Ö¸¶¨³¤¶ÈµÄÊý¾Ý·Åµ½»·Ðλº³åÇøÖÐ + *@param[in] buf - Êý¾Ý»º³åÇø + * len - »º³åÇø³¤¶È + *@retval ʵ¼Ê·Åµ½ÖеÄÊý¾Ý + */ +int ring_buf_put(ring_buf_t *r,unsigned char *buf,unsigned int len) +{ + unsigned int i; + unsigned int left; + left = r->size + r->front - r->rear; + len = min(len , left); + i = min(len, r->size - (r->rear & r->size - 1)); + memcpy(r->buf + (r->rear & r->size - 1), buf, i); + memcpy(r->buf, buf + i, len - i); + r->rear += len; + return len; + +} + +/* + *@brief ´Ó»·Ðλº³åÇøÖжÁÈ¡Ö¸¶¨³¤¶ÈµÄÊý¾Ý + *@param[in] len - ¶ÁÈ¡³¤¶È + *@param[out] buf - Êä³öÊý¾Ý»º³åÇø + *@retval ʵ¼Ê¶ÁÈ¡³¤¶È + */ +int ring_buf_get(ring_buf_t *r,unsigned char *buf,unsigned int len) +{ + unsigned int i; + unsigned int left; + left = r->rear - r->front; + len = min(len , left); + i = min(len, r->size - (r->front & r->size - 1)); + memcpy(buf, r->buf + (r->front & r->size - 1), i); + memcpy(buf + i, r->buf, len - i); + r->front += len; + return len; +} diff --git a/components/ringbuffer.h b/components/ringbuffer.h new file mode 100644 index 0000000..b517e6c --- /dev/null +++ b/components/ringbuffer.h @@ -0,0 +1,45 @@ +/****************************************************************************** + * @brief »·Ðλº³åÇø¹ÜÀí(²Î¿¼linux/kfifo) + * + * Copyright (c) 2016~2020, + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2016-05-30 Morro ³õ°æÍê³É + ******************************************************************************/ + +#ifndef _RING_BUF_H_ +#define _RING_BUF_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*»·Ðλº³åÇø¹ÜÀíÆ÷*/ +typedef struct { + unsigned char *buf; /*»·Ðλº³åÇø */ + unsigned int size; /*»·Ðλº³åÇø */ + unsigned int front; /*Í·Ö¸Õë */ + unsigned int rear; /*βָÕë */ +}ring_buf_t; + +bool ring_buf_init(ring_buf_t *r,unsigned char *buf,unsigned int size); + +void ring_buf_clr(ring_buf_t *r); + +int ring_buf_len(ring_buf_t *r); + +int ring_buf_put(ring_buf_t *r,unsigned char *buf,unsigned int len); + +int ring_buf_get(ring_buf_t *r,unsigned char *buf,unsigned int len); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/components/update_protocol.c b/components/update_protocol.c new file mode 100644 index 0000000..88726c5 --- /dev/null +++ b/components/update_protocol.c @@ -0,0 +1,122 @@ +#include "update_protocol.h" +#include "string.h" + +static struct +{ + update_send_t pfnSend; + update_callback_t EventCb; +}g_update_protoc; + +uint16_t CRC_Modbus(uint16_t wBase, uint8_t* para, uint16_t length) +{ + uint16_t crc = 0xffff; + + uint16_t index, i; + + for (index = 0 ; index < length; index++) + { + crc ^= para[index]; + + for (i = 0; i < 8; i++) + { + if (crc & 1) + { + crc >>= 1; + crc ^= wBase; + } + else + crc >>= 1; + } + } + + return crc; +} + +void update_send_cmd(uint8_t Cmd, uint16_t Indx, int PageNum) +{ + uint8_t sData[24]={0}; + uint8_t sLen =0; + uint16_t crc16; + + update_protocol_hd_t *Frame = (update_protocol_hd_t*)sData; + + Frame->Header = 0x7a; + Frame->SlvAddr = 0x01; + Frame->Cmd = Cmd; + + if (Cmd == 0x01) + { + Frame->PayloadLen = 1; + sData[sizeof(update_protocol_hd_t)] = Indx; + } + else if (Cmd == 0x02) + { + Frame->PayloadLen = 4; + update_protocol_get_t *GDData = (update_protocol_get_t*)&sData[sizeof(update_protocol_hd_t)]; + GDData->PackageIndex = Indx; + GDData->PackageNum = PageNum; + } + + sLen = sizeof(update_protocol_hd_t) + Frame->PayloadLen; + crc16 = CRC_Modbus(CRC16_BASE, sData, sLen); + sData[sLen++] = crc16; + sData[sLen++] = (crc16 >> 8) & 0x00ff; + + g_update_protoc.pfnSend(sData, sLen); +} + +void update_init(update_send_t pCbs) +{ + g_update_protoc.pfnSend =pCbs; +} + +void update_event_cbs_reg(update_callback_t pCbs) +{ + + g_update_protoc.EventCb = pCbs; + +} + +uint8_t update_unpack(uint8_t* rxData, int rLen,uint8_t *cmd, void *pload, int *pLen){ + + uint16_t crc16; + + uint16_t check; + + check = CRC_Modbus(CRC16_BASE, rxData, rLen - 2); + + crc16 = (rxData[rLen - 1] << 8) | rxData[rLen - 2]; + + if (check != crc16 || rxData[0] !=0x7a || pload ==0) + { + return 0; + } + + update_protocol_hd_t *Frame = (update_protocol_hd_t*)rxData; + + *cmd = Frame->Cmd; + + if (Frame->Cmd == 0x81){ + + //update_protocol_req_t *UpData = (update_protocol_req_t*)&rxData[sizeof(update_protocol_hd_t)]; + + pload = 0; + + *pLen = 0; + + + }else if (Frame->Cmd == 0x82){ + + update_protocol_rsp_t *DownData = (update_protocol_rsp_t *)&rxData[sizeof(update_protocol_hd_t)]; + + memcpy(pload , &rxData[sizeof(update_protocol_hd_t) + sizeof(update_protocol_rsp_t)],DownData->DataLen); + + *pLen = DownData->DataLen; + + }else{ + + return 0; + } + + return 1; +} diff --git a/components/update_protocol.h b/components/update_protocol.h new file mode 100644 index 0000000..e7d0ca5 --- /dev/null +++ b/components/update_protocol.h @@ -0,0 +1,53 @@ +#ifndef _UPDATE_PROTOCOL_H_ +#define _UPDATE_PROTOCOL_H_ + +#include "stdint.h" + +#define CRC16_BASE 0xA001 + +//Ö¡Í·½á¹¹Ìå +typedef struct { + uint8_t Header; + uint8_t SlvAddr; + uint8_t Cmd; + uint8_t PayloadLen; +}update_protocol_hd_t; + +//Ö÷»úÏ·¢Éý¼¶ÇëÇóÔغɽṹÌå +typedef struct { + uint16_t PackageNum; + uint32_t AppSize; + uint32_t AppCrc32; +}__attribute__ ((packed))update_protocol_req_t; + +//´Ó»úÇëÇóÏ·¢½á¹¹Ìå +typedef struct { + uint16_t PackageIndex; + uint32_t PackageNum; +}__attribute__ ((packed))update_protocol_get_t; + +//Ö÷»úÓ¦´ðÏ·¢Êý¾Ý½á¹¹Ìå +typedef struct { + uint16_t PackageIndex; + uint16_t PackageNum; + uint8_t DataLen; +}__attribute__ ((packed))update_protocol_rsp_t; + + +typedef int (*update_callback_t)(uint8_t cmd, void *pdata, int len,void *pload,int size); + +typedef void (*update_send_t)(uint8_t *pBuf,int len); + +void update_init(update_send_t pCbs); + +void update_event_cbs_reg(update_callback_t pCbs); + +uint8_t update_unpack(uint8_t* rxData, int rLen,uint8_t *cmd, void *pUser, int *pLen); + +void update_send_cmd(uint8_t Cmd, uint16_t Indx, int PageNum); + +#endif + + + + diff --git a/device/dev_boot.c b/device/dev_boot.c new file mode 100644 index 0000000..37aa8bc --- /dev/null +++ b/device/dev_boot.c @@ -0,0 +1,144 @@ +#include "dev_boot.h" + +static uint32_t pdwCrc32Tbl[256]={0}; + +static void InitCrc32Table(void) +{ + for (int wCnt = 0; wCnt != 256; wCnt++) + { + uint32_t dwCrc = wCnt; + + for (int ucCnt = 0; ucCnt != 8; ucCnt++) + { + if (dwCrc & 1) + { + dwCrc = (dwCrc >> 1) ^ 0xEDB88320; + } + else + { + dwCrc >>= 1; + } + } + + pdwCrc32Tbl[wCnt] = dwCrc; + } +} + +void dev_boot_read_param(boot_para_t *pParam) +{ + hdl_flash_read_data(FLASH_BINFO_BASE,(uint8_t *)pParam,sizeof(boot_para_t)); +} + +int dev_boot_write_param(boot_para_t Param) +{ + int res = LL_OK; + + int wLen; + uint32_t *pData; + + pData= (uint32_t *)&Param; + + wLen = sizeof(boot_para_t); + + hdl_flash_unlock(); + /* Erase sector. */ + res = hdl_flash_erase_sector(FLASH_BINFO_BASE,FLASH_BINFO_SIZE); + + if(res == LL_OK){ + + res = hdl_flash_write_data (FLASH_BINFO_BASE, (uint8_t *)pData, wLen); + } + + hdl_flash_lock(); + + return res; +} + + +void dev_boot_erase_app(void) +{ + hdl_flash_unlock(); + + for(int Addr = FLASH_APP_BASE; Addr < FLASH_APP_SIZE; Addr += FLASH_SECTOR_SIZE) { + + EFM_SectorErase(Addr); + + SWDT_FeedDog(); + + } + /* Lock EFM. */ + hdl_flash_lock(); +} + +void dev_boot_write_app(uint32_t AddrOffset, uint8_t* wData, int wLen) +{ + hdl_flash_unlock(); + + hdl_flash_write_data (FLASH_APP_BASE + AddrOffset, (uint8_t *)wData, wLen); + + hdl_flash_lock(); +} + + +uint8_t dev_boot_check_app(void) +{ + uint32_t AppAddr =FLASH_APP_BASE; + + uint32_t u32StackTop = *((__IO uint32_t*)AppAddr); + + if ((u32StackTop > SRAM_BASE) && (u32StackTop <= (SRAM_BASE + SRAM_SIZE))) + { + + return 1; + } + + return 0; +} + + +void dev_boot_run_app(void) +{ + volatile uint32_t JumpAddress; + + func_ptr_t JumpToApplication; + + uint32_t AppAddr =FLASH_APP_BASE; + + uint32_t u32StackTop = *((__IO uint32_t*)AppAddr); + + if ((u32StackTop > SRAM_BASE) && (u32StackTop <= (SRAM_BASE + SRAM_SIZE))) + { + JumpAddress = *(__IO uint32_t*)(AppAddr + 4); + + JumpToApplication = (func_ptr_t)JumpAddress; + + __disable_fiq(); + + __set_MSP(*(__IO uint32_t*)AppAddr); + + JumpToApplication(); + } +} + + +uint32_t dev_boot_get_app_crc32(int dwLen) +{ + if(dwLen >= 0xFFFFFFFF) + return 0; + + InitCrc32Table(); + + uint32_t Data; + uint32_t dwCrc32Data = 0xFFFFFFFF; + + for (int dwCnt = 0; dwCnt != dwLen; ++dwCnt) + { + Data = *((volatile uint8_t*)(FLASH_APP_BASE + dwCnt)); + + uint32_t dwTbl = (dwCrc32Data ^ Data) & 0xFF; + + dwCrc32Data = ((dwCrc32Data >> 8) & 0xFFFFFF) ^ pdwCrc32Tbl[dwTbl]; + } + + return ~dwCrc32Data; +} diff --git a/device/dev_boot.h b/device/dev_boot.h new file mode 100644 index 0000000..4545252 --- /dev/null +++ b/device/dev_boot.h @@ -0,0 +1,54 @@ +#ifndef _DEV_BOOT_ +#define _DEV_BOOT_ + +#include "hdl_flash.h" + +#define APP_START_FLAG 0x55AA5A5A +#define APP_UPDATE_FLAG 0xA5A5AA55 + +#define BOOT_BASE (FLASH_BASE) +#define BOOT_SIZE (4*FLASH_SECTOR_SIZE) + +#define APP_ADDRESS (BOOT_BASE + BOOT_SIZE) +#define APP_SIZE (58*FLASH_SECTOR_SIZE) + +#define BOOT_PARA_ADDRESS (APP_ADDRESS + APP_SIZE) +#define BOOT_PARA_SIZE (FLASH_SECTOR_SIZE) + +#define APP_START_FLAG 0x55AA5A5A +#define APP_UPDATE_FLAG 0xA5A5AA55 + +typedef struct { + uint32_t AppFlag; + uint32_t DevType; + uint32_t DevAddr; + uint32_t UpdateFlag; + uint32_t PackageNum; + uint32_t AppSize; + uint32_t Crc32Check; +}boot_para_t; + + +void dev_boot_read_param(boot_para_t *pParam); + +int dev_boot_write_param(boot_para_t Param); + +void dev_boot_erase_app(void); + +void dev_boot_write_app(uint32_t AddrOffset, uint8_t* wData, int wLen); + +uint8_t dev_boot_check_app(void); + +uint32_t dev_boot_get_app_crc32(int dwLen); + +void dev_boot_run_app(void); + +#endif + + + + + + + + diff --git a/device/dev_rs485.c b/device/dev_rs485.c new file mode 100644 index 0000000..6f180d4 --- /dev/null +++ b/device/dev_rs485.c @@ -0,0 +1,67 @@ +#include "dev_rs485.h" +#include "hdl_led.h" + +static void rs485_rxpin_init(void) +{ + LL_PERIPH_WE(LL_PERIPH_GPIO); + + stc_gpio_init_t stcGpioInit={0}; + + GPIO_StructInit(&stcGpioInit); + + stcGpioInit.u16PinDir = PIN_DIR_OUT; + + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + + stcGpioInit.u16PullUp = PIN_PU_ON; + + stcGpioInit.u16PinAttr = PIN_ATTR_DIGITAL; + + (void)GPIO_Init(RS485_CTRL_PORT, RS485_CTRL_PIN, &stcGpioInit); + + LL_PERIPH_WP(LL_PERIPH_GPIO); +} + +static void rs485_rxpin_enable(void) +{ + GPIO_ResetPins(RS485_CTRL_PORT,RS485_CTRL_PIN); +} + +static void rs485_rxpin_disable(void) +{ + GPIO_SetPins(RS485_CTRL_PORT,RS485_CTRL_PIN); +} + + +int dev_rs485_init(void) +{ + hdl_com_uart_init(); + + rs485_rxpin_init(); + + rs485_rxpin_enable(); + + return 0; +} + +int dev_rs485_rx_register(dev_rs485_cb_t fnCallback) +{ + hdl_com_uart_rx_register((com_rx_callback)fnCallback); + + return 0; +} + +void dev_rs485_send(uint8_t* buf, int len) +{ + rs485_rxpin_disable(); + + hdl_com_uart_send(buf, len); + + rs485_rxpin_enable(); + +} + +int dev_rs485_deinit(void) +{ + return 0; +} diff --git a/device/dev_rs485.h b/device/dev_rs485.h new file mode 100644 index 0000000..30137d0 --- /dev/null +++ b/device/dev_rs485.h @@ -0,0 +1,22 @@ +#ifndef _DEV_RS485_H_ +#define _DEV_RS485_H_ + +#include "hdl_usart.h" + +#define RS485_CTRL_PORT (GPIO_PORT_C) +#define RS485_CTRL_PIN (GPIO_PIN_07) + +typedef void (*dev_rs485_cb_t)(uint8_t dat); + +extern int dev_rs485_init(void); + +extern void dev_rs485_send(uint8_t *buf, int len); + +extern int dev_rs485_read(uint8_t *buf, int len); + +extern int dev_rs485_rx_register(dev_rs485_cb_t fnCallback); + +extern int dev_rs485_deinit(void); + +#endif + diff --git a/hdl/hdl_clk.c b/hdl/hdl_clk.c new file mode 100644 index 0000000..84c57fd --- /dev/null +++ b/hdl/hdl_clk.c @@ -0,0 +1,132 @@ +#include "hdl_clk.h" + +/******************************************************************************************************** +* @函数å hdl_xtal_init +* @æè¿° 外部晶振åˆå§‹åŒ– +* @å‚æ•° æ—  +* @返回值 æ—  +* @æ³¨æ„ æ—  +********************************************************************************************************/ + +#if USING_XTAL +static void hdl_xtal_init(void) +{ + stc_clock_xtal_init_t stcXtalInit; + + /* XTAL 引脚é…ç½® */ + GPIO_AnalogCmd(GPIO_PORT_H, GPIO_PIN_00 | GPIO_PIN_01, ENABLE); + + (void)CLK_XtalStructInit(&stcXtalInit); + /* é…ç½®XTALå’Œå¯ç”¨XTAL */ + stcXtalInit.u8State = CLK_XTAL_ON; + stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; + stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; + stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS; + (void)CLK_XtalInit(&stcXtalInit); +} +#endif + + +/******************************************************************************************************** +* @函数å hdl_pll_init +* @æè¿° é”相环å€é¢‘åˆå§‹åŒ– +* @å‚æ•° æ—  +* @返回值 æ—  +* @æ³¨æ„ æ—  +********************************************************************************************************/ +static void hdl_pll_init(void) +{ + stc_clock_pll_init_t stcMPLLInit; + + (void)CLK_PLLStructInit(&stcMPLLInit); + + /* MPLL é…ç½® */ + /* 16MHz/M*N = 16/2*50/2 = 200MHz */ + stcMPLLInit.PLLCFGR = 0UL; + stcMPLLInit.PLLCFGR_f.PLLM = (2UL - 1UL); + stcMPLLInit.PLLCFGR_f.PLLN = (50UL - 1UL); + stcMPLLInit.PLLCFGR_f.PLLP = (2UL - 1UL); + stcMPLLInit.PLLCFGR_f.PLLQ = (2UL - 1UL); + stcMPLLInit.PLLCFGR_f.PLLR = (2UL - 1UL); + stcMPLLInit.u8PLLState = CLK_PLL_ON; + stcMPLLInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_HRC; /* HRC = 16MHz */ + (void)CLK_PLLInit(&stcMPLLInit); +} + + +/******************************************************************************************************** +* @函数å hdl_clk_init +* @æè¿° 时钟åˆå§‹åŒ– +* @å‚æ•° æ—  +* @返回值 æ—  +* @æ³¨æ„ æ—  +********************************************************************************************************/ +void hdl_clk_init(void) +{ + /* 解除写ä¿æŠ¤ */ + LL_PERIPH_WE(LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_GPIO | LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM); + + /* 设置时钟分频 */ + CLK_SetClockDiv(CLK_BUS_CLK_ALL, (CLK_HCLK_DIV1 | CLK_EXCLK_DIV2 | CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | \ + CLK_PCLK2_DIV4 | CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2)); + + /* SRAMåˆå§‹åŒ–包括读/写等待周期设置 */ + SRAM_SetWaitCycle(SRAM_SRAM_ALL, SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1); + SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0); + + /* 闪存读å–等待周期设置 */ + EFM_SetWaitCycle(EFM_WAIT_CYCLE5); + + /* XTAL åˆå§‹åŒ– */ +// hdl_xtal_init(); + /* XTAL32 åˆå§‹åŒ– */ + + /* MPLL åˆå§‹åŒ– */ + hdl_pll_init(); + + /* enable LRC */ + + /* enable HRC */ + /* 3 cycles for 126MHz ~ 200MHz */ + GPIO_SetReadWaitCycle(GPIO_RD_WAIT3); + + /* 切æ¢é©±åŠ¨èƒ½åŠ› */ + PWC_HighSpeedToHighPerformance(); + + EFM_DataCacheResetCmd(ENABLE); + + EFM_DataCacheResetCmd(DISABLE); + /* Enable cache */ + EFM_CacheCmd(ENABLE); + + /* 使能写ä¿æŠ¤ */ + LL_PERIPH_WP(LL_PERIPH_EFM | LL_PERIPH_GPIO | LL_PERIPH_SRAM); + + /* è®¾ç½®ç³»ç»Ÿæ—¶é’Ÿæº */ + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); + + /* 使能systick */ + (void)SysTick_Init(1000U); +} + +void hdl_delay_us(uint16_t us) +{ + for(int i=0;i OFFSET_CNT) + { + offset_cnt = 0; + cs5552.step = CS5552_START; + } + break; + case CS5552_OFFSET_READ: + if(RESET == GET_CS5552_DOUT()) + { + ad_value = hdl_cs5552_reg_read(0xFF); //»ñÈ¡Êý¾Ý + + if((ad_value & 0x1) == 0) + { + cs5552.offset_ch0[offset_cnt] = (ad_value & 0xFFFFFFFE) | 0x0; + } + + if((ad_value & 0x1) == 1) + { + cs5552.offset_ch1[offset_cnt] = (ad_value & 0xFFFFFFFE) | 0x0; + } + offset_cnt++; + cs5552.channel_sta = 1-cs5552.channel_sta; //Çл»Í¨µÀ + + cs5552.step = CS5552_OFFSET; + } + break; + case CS5552_START: + CLR_CS5552_CS(); + + if(cs5552.channel_sta == CS5552_CH0) + hdl_cs5552_write_read_byte(CONV_CH0); + if(cs5552.channel_sta == CS5552_CH1) + hdl_cs5552_write_read_byte(0x90); + cs5552.step = CS5552_READ; + break; + case CS5552_READ: + + if(RESET == GET_CS5552_DOUT()) + { + ad_value = hdl_cs5552_reg_read(0xFF); //»ñÈ¡Êý¾Ý + + if((ad_value & 0x1) == 0) + { + if((ad_value>>22) < 0x3F) //+ + cs5552.buf[0] = (ad_value & 0x3FFFFFFE) >> 13; + if((ad_value>>22) > 0xC0) //- + cs5552.buf[0] = ~(0x7FFFF - ((ad_value & 0xFFFFFFFE) >> 13)); + } + + if((ad_value & 0x1) == 1) + { + if((ad_value>>22) < 0x3F) //+ + cs5552.buf[1] = (ad_value & 0x3FFFFFFE) >> 13; + if((ad_value>>22) > 0xC0) //- + cs5552.buf[1] = ~(0x7FFFF - ((ad_value & 0xFFFFFFFE) >> 13)); + } + + cs5552.channel_sta = 1-cs5552.channel_sta; //Çл»Í¨µÀ + + cs5552.step = CS5552_START; + } + break; + } +} + + diff --git a/hdl/hdl_cs5552.h b/hdl/hdl_cs5552.h new file mode 100644 index 0000000..392d9b1 --- /dev/null +++ b/hdl/hdl_cs5552.h @@ -0,0 +1,110 @@ +#ifndef ____HDL_CS5552_H_ +#define ____HDL_CS5552_H_ + +#include "hc32_ll.h" +#include "hdl_clk.h" + +#define CS5552_SPI CM_SPI1 +#define CS5552_SPI_CLK FCG1_PERIPH_SPI1 + +#define CS5552_CS_PORT GPIO_PORT_A +#define CS5552_CS_PIN GPIO_PIN_04 +#define CS5552_CS_FUNC GPIO_FUNC_42 + +#define CS5552_SCLK_PORT GPIO_PORT_A +#define CS5552_SCLK_PIN GPIO_PIN_07 +#define CS5552_SCLK_FUNC GPIO_FUNC_43 + +#define CS5552_MISO_PORT GPIO_PORT_A +#define CS5552_MISO_PIN GPIO_PIN_06 +#define CS5552_MISO_FUNC GPIO_FUNC_41 + +#define CS5552_MOSI_PORT GPIO_PORT_A +#define CS5552_MOSI_PIN GPIO_PIN_05 +#define CS5552_MOSI_FUNC GPIO_FUNC_40 + +#define SET_CS5552_CS() GPIO_SetPins(CS5552_CS_PORT, CS5552_CS_PIN) +#define CLR_CS5552_CS() GPIO_ResetPins(CS5552_CS_PORT, CS5552_CS_PIN) + +#define SET_CS5552_DOUT() GPIO_SetPins(CS5552_MISO_PORT, CS5552_MISO_PIN) +#define CLR_CS5552_DOUT() GPIO_ResetPins(CS5552_MISO_PORT, CS5552_MISO_PIN) +#define GET_CS5552_DOUT() GPIO_ReadInputPins(CS5552_MISO_PORT, CS5552_MISO_PIN) + +#define SET_CS5552_DIN() GPIO_SetPins(CS5552_MOSI_PORT, CS5552_MOSI_PIN) +#define CLR_CS5552_DIN() GPIO_ResetPins(CS5552_MOSI_PORT, CS5552_MOSI_PIN) + +#define SET_CS5552_SCLK() GPIO_SetPins(CS5552_SCLK_PORT, CS5552_SCLK_PIN) +#define CLR_CS5552_SCLK() GPIO_ResetPins(CS5552_SCLK_PORT, CS5552_SCLK_PIN) + +#define OS_CH0_R 0x05 +#define OS_CH0_W 0x00 + +#define GAIN_CH0_R 0x0C +#define GAIN_CH0_W 0x09 + +#define OS_CH1_R 0x14 +#define OS_CH1_W 0x11 + +#define GAIN_CH1_R 0x1D +#define GAIN_CH1_W 0x18 + +#define CONV_CONF0_R 0x24 +#define CONV_CONF0_W 0x21 + +#define CONV_CONF1_R 0x2D +#define CONV_CONF1_W 0x28 + +#define SYS_CONF0_R 0x35 +#define SYS_CONF0_W 0x30 + +#define SYS_CONF1_R 0x3C +#define SYS_CONF1_W 0x39 + +#define SYS_CONF2_R 0x44 +#define SYS_CONF2_W 0x41 + +#define CONV_DATA_R 0x55 + +#define CONV_CH0 0x81 +#define CONV_CH1 0x90 + +#define SELF_OFFSET_CH0 0x84 +#define SELF_OFFSET_CH1 0x95 + +#define SYS_OFFSET_CH0 0x8B +#define SYS_OFFSET_CH1 0x9A + +#define OFFSET_CNT 9 + +typedef enum +{ + CS5552_IDLE, + CS5552_OFFSET, + CS5552_OFFSET_READ, + CS5552_START, + CS5552_READ +}en_cs5552_step; + +typedef enum +{ + CS5552_CH0, + CS5552_CH1, +}en_cs5552_ch; + +typedef struct +{ + en_cs5552_step step; //Á÷³Ì + en_cs5552_ch channel_sta; //µ±Ç°×ª»»Í¨µÀ + int32_t buf[2]; //ͨµÀÊý¾Ý + uint32_t offset_ch0[OFFSET_CNT]; //ͨµÀ0У׼ֵ + uint32_t offset_ch1[OFFSET_CNT]; //ͨµÀ1У׼ֵ +}stc_cs5552_t; + +void hdl_cs5552_init(void); +uint32_t hdl_cs5552_reg_read(uint8_t cmd); + +void hdl_cs5552_value_get(int32_t *buf); +void hdl_cs5552_conv_start(void); +void hdl_cs5552_proc(void); + +#endif diff --git a/hdl/hdl_encoder.c b/hdl/hdl_encoder.c new file mode 100644 index 0000000..3b0bc18 --- /dev/null +++ b/hdl/hdl_encoder.c @@ -0,0 +1,88 @@ +#include "hdl_encoder.h" + +static volatile uint8_t a_level = 0; +static volatile int16_t encoder_cnt = 0; + +static void hdl_encoder_a_callback(void) +{ + if (SET == EXTINT_GetExtIntStatus(ENCODER_A_EX_CH)) { + if(RESET == ENCODER_A_GET) + { + a_level = 0; + if(SET == ENCODER_B_GET) + a_level = 1; + } + if(SET == ENCODER_A_GET) + { + if((a_level == 1) && (RESET == ENCODER_B_GET)) + { + encoder_cnt++; + } + if((a_level == 0) && (SET == ENCODER_B_GET)) + { + encoder_cnt--; + } + } + + EXTINT_ClearExtIntStatus(ENCODER_A_EX_CH); + } +} + +static void hdl_encoder_b_callback(void) +{ + if (SET == EXTINT_GetExtIntStatus(ENCODER_B_EX_CH)) { + +// while (PIN_RESET == GPIO_ReadInputPins(KEY10_PORT, KEY10_PIN)) { +// ; +// } + EXTINT_ClearExtIntStatus(ENCODER_B_EX_CH); + } +} + +void hdl_encoder_init(void) +{ + stc_gpio_init_t stcGpioInit; + stc_extint_init_t stcExtIntInit; + stc_irq_signin_config_t stcIrqSignConfig; + + LL_PERIPH_WE(LL_PERIPH_GPIO); + + /* ÅäÖÃÒý½Å */ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PullUp = PIN_PU_ON; //ÉÏÀ­ÊäÈë + stcGpioInit.u16ExtInt = PIN_EXTINT_ON; //ÍⲿÖÐ¶Ï + (void)GPIO_Init(ENCODER_SW_PORT, ENCODER_SW_PIN, &stcGpioInit); + (void)GPIO_Init(ENCODER_A_PORT, ENCODER_A_PIN, &stcGpioInit); + (void)GPIO_Init(ENCODER_B_PORT, ENCODER_B_PIN, &stcGpioInit); + + /* ÅäÖÃÖÐ¶Ï */ + (void)EXTINT_StructInit(&stcExtIntInit); + stcExtIntInit.u32Filter = EXTINT_FILTER_ON; + stcExtIntInit.u32FilterClock = EXTINT_FCLK_DIV8; + stcExtIntInit.u32Edge = EXTINT_TRIG_BOTH; //Ë«±ßÑØÖÐ¶Ï + (void)EXTINT_Init(ENCODER_A_EX_CH, &stcExtIntInit); + (void)EXTINT_Init(ENCODER_B_EX_CH, &stcExtIntInit); + + /* ÅäÖÃÖжÏÔ´ */ + stcIrqSignConfig.enIntSrc = ENCODER_A_INT_SRC; + stcIrqSignConfig.enIRQn = ENCODER_A_INT_IRQn; + stcIrqSignConfig.pfnCallback = &hdl_encoder_a_callback; + (void)INTC_IrqSignIn(&stcIrqSignConfig); + NVIC_ClearPendingIRQ(stcIrqSignConfig.enIRQn); + NVIC_SetPriority(stcIrqSignConfig.enIRQn, DDL_IRQ_PRIO_DEFAULT); + NVIC_EnableIRQ(stcIrqSignConfig.enIRQn); + + stcIrqSignConfig.enIntSrc = ENCODER_B_INT_SRC; + stcIrqSignConfig.enIRQn = ENCODER_B_INT_IRQn; + stcIrqSignConfig.pfnCallback = &hdl_encoder_b_callback; + (void)INTC_IrqSignIn(&stcIrqSignConfig); + NVIC_ClearPendingIRQ(stcIrqSignConfig.enIRQn); + NVIC_SetPriority(stcIrqSignConfig.enIRQn, DDL_IRQ_PRIO_DEFAULT); + NVIC_EnableIRQ(stcIrqSignConfig.enIRQn); +} + +int16_t hdl_encoder_cnt_get(void) +{ + return encoder_cnt; +} + diff --git a/hdl/hdl_encoder.h b/hdl/hdl_encoder.h new file mode 100644 index 0000000..d6ab140 --- /dev/null +++ b/hdl/hdl_encoder.h @@ -0,0 +1,30 @@ +#ifndef ____HDL_ENCODER_H_ +#define ____HDL_ENCODER_H_ + +#include "hc32_ll.h" + +#define ENCODER_A_PORT GPIO_PORT_H +#define ENCODER_A_PIN GPIO_PIN_02 +#define ENCODER_A_EX_CH EXTINT_CH02 +#define ENCODER_A_INT_SRC INT_SRC_PORT_EIRQ2 +#define ENCODER_A_INT_IRQn INT033_IRQn +#define ENCODER_A_GET GPIO_ReadInputPins(ENCODER_A_PORT, ENCODER_A_PIN) + +#define ENCODER_B_PORT GPIO_PORT_C +#define ENCODER_B_PIN GPIO_PIN_13 +#define ENCODER_B_EX_CH EXTINT_CH13 +#define ENCODER_B_INT_SRC INT_SRC_PORT_EIRQ13 +#define ENCODER_B_INT_IRQn INT034_IRQn +#define ENCODER_B_GET GPIO_ReadInputPins(ENCODER_B_PORT, ENCODER_B_PIN) + +#define ENCODER_SW_PORT GPIO_PORT_C +#define ENCODER_SW_PIN GPIO_PIN_14 + + + + +void hdl_encoder_init(void); +int16_t hdl_encoder_cnt_get(void); + + +#endif diff --git a/hdl/hdl_flash.c b/hdl/hdl_flash.c new file mode 100644 index 0000000..7941087 --- /dev/null +++ b/hdl/hdl_flash.c @@ -0,0 +1,203 @@ +/** + ******************************************************************************* + * @file iap/iap_ymodem_boot/source/flash.c + * @brief This file provides firmware functions to manage the Flash driver. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hdl_flash.h" +#include "hdl_clk.h" + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + + +int32_t hdl_flash_unlock(void) +{ + LL_PERIPH_WE(LL_PERIPH_EFM ); + + /* Wait flash ready. */ + while (SET != EFM_GetStatus(EFM_FLAG_RDY)) { + ; + } + + //½âËøEFM + EFM_FWMC_Cmd(ENABLE); + EFM_CacheCmd(ENABLE); + + + return LL_OK; +} + +int32_t hdl_flash_lock(void){ + + /* Peripheral registers write protected */ + EFM_CacheCmd(DISABLE); + EFM_FWMC_Cmd(DISABLE); + LL_PERIPH_WP(LL_PERIPH_EFM ); + return LL_OK; +} + +/** + * @brief Check address alignment. + * @param u32Addr Flash address + * @retval An en_result_t enumeration value: + * - LL_OK: Address aligned + * - LL_ERR: Address unaligned + */ +int32_t hdl_flash_check_addralign(uint32_t u32Addr) +{ + uint32_t u32Step = FLASH_SECTOR_SIZE; + + if (VECT_TAB_STEP > FLASH_SECTOR_SIZE) { + u32Step = VECT_TAB_STEP; + } + if ((u32Addr % u32Step) != 0UL) { + return LL_ERR; + } + + return LL_OK; +} + +/** + * @brief Erase flash sector. + * @param u32Addr Flash address + * @param u32Size Firmware size (0: current address sector) + * @retval An en_result_t enumeration value: + * - LL_OK: Erase succeeded + * - LL_ERR: Erase timeout + * - LL_ERR_INVD_PARAM: The parameters is invalid. + */ +int32_t hdl_flash_erase_sector(uint32_t u32Addr, uint32_t u32Size) +{ + uint32_t i; + uint32_t u32PageNum; + + if (u32Addr >= (FLASH_BASE + FLASH_SIZE)) { + return LL_ERR_INVD_PARAM; + } + + if (u32Size == 0U) { + return EFM_SectorErase(u32Addr); + } else { + u32PageNum = u32Size / FLASH_SECTOR_SIZE; + if ((u32Size % FLASH_SECTOR_SIZE) != 0UL) { + u32PageNum += 1U; + } + for (i = 0; i < u32PageNum; i++) { + if (LL_OK != EFM_SectorErase(u32Addr + (i * FLASH_SECTOR_SIZE))) { + return LL_ERR; + } + } + } + + return LL_OK; +} + +/** + * @brief Write data to flash. + * @param u32Addr Flash address + * @param pu8Buff Pointer to the buffer to be written + * @param u32Len Buffer length + * @retval int32_t: + * - LL_OK: Program successful. + * - LL_ERR_INVD_PARAM: The parameters is invalid. + * - LL_ERR_NOT_RDY: EFM if not ready. + * - LL_ERR_ADDR_ALIGN: Address alignment error + */ +int32_t hdl_flash_write_data(uint32_t u32Addr, uint8_t *pu8Buff, uint32_t u32Len) +{ + if ((pu8Buff == NULL) || (u32Len == 0U) || ((u32Addr + u32Len) > (FLASH_BASE + FLASH_SIZE))) { + return LL_ERR_INVD_PARAM; + } + if (0UL != (u32Addr % 4U)) { + return LL_ERR_ADDR_ALIGN; + } + return EFM_Program(u32Addr, pu8Buff, u32Len); +} + +/** + * @brief Read data from flash. + * @param u32Addr Flash address + * @param pu8Buff Pointer to the buffer to be reading + * @param u32Len Buffer length + * @retval int32_t: + * - LL_OK: Read data succeeded + * - LL_ERR_INVD_PARAM: The parameters is invalid + * - LL_ERR_ADDR_ALIGN: Address alignment error + */ +int32_t hdl_flash_read_data(uint32_t u32Addr, uint8_t *pu8Buff, uint32_t u32Len) +{ + uint32_t i; + uint32_t u32WordLength, u8ByteRemain; + uint32_t *pu32ReadBuff; + __IO uint32_t *pu32FlashAddr; + uint8_t *pu8Byte; + __IO uint8_t *pu8FlashAddr; + + if ((pu8Buff == NULL) || (u32Len == 0U) || ((u32Addr + u32Len) > (FLASH_BASE + FLASH_SIZE))) { + return LL_ERR_INVD_PARAM; + } + if (0UL != (u32Addr % 4U)) { + return LL_ERR_ADDR_ALIGN; + } + + pu32ReadBuff = (uint32_t *)(uint32_t)pu8Buff; + pu32FlashAddr = (uint32_t *)u32Addr; + u32WordLength = u32Len / 4U; + u8ByteRemain = u32Len % 4U; + /* Read data */ + for (i = 0UL; i < u32WordLength; i++) { + *(pu32ReadBuff++) = *(pu32FlashAddr++); + } + if (0UL != u8ByteRemain) { + pu8Byte = (uint8_t *)pu32ReadBuff; + pu8FlashAddr = (uint8_t *)pu32FlashAddr; + for (i = 0UL; i < u8ByteRemain; i++) { + *(pu8Byte++) = *(pu8FlashAddr++); + } + } + + return LL_OK; +} + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/hdl/hdl_flash.h b/hdl/hdl_flash.h new file mode 100644 index 0000000..7872b57 --- /dev/null +++ b/hdl/hdl_flash.h @@ -0,0 +1,97 @@ +/** + ******************************************************************************* + * @file iap/iap_ymodem_boot/source/flash.h + * @brief This file contains all the functions prototypes of the Flash driver. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HDL_FLASH_H__ +#define __HDL_FLASH_H__ + +#include "stdint.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_efm.h" + +#include "hc32_ll_SWDT.h" + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Flash definitions */ +#define FLASH_BASE (EFM_START_ADDR) +#define FLASH_SIZE (EFM_END_ADDR + 1U) +#define FLASH_SECTOR_SIZE (EFM_SECTOR_SIZE) +#define FLASH_SECTOR_NUM (64U) + +/* SRAM definitions */ +#define SRAM_SIZE (0x02F000UL) +/* Vector table */ +#define VECT_TAB_STEP (0x000UL) + +/* flash rom map ´æ´¢·ÖÇø*/ +//boot 16k +#define FLASH_BOOT_BASE (FLASH_BASE) +#define FLASH_BOOT_SIZE (4*FLASH_SECTOR_SIZE) +//app +#define FLASH_APP_BASE (FLASH_BOOT_BASE+ FLASH_BOOT_SIZE) +#define FLASH_APP_SIZE (58*FLASH_SECTOR_SIZE) + +//boot info +#define FLASH_BINFO_BASE (FLASH_APP_BASE + FLASH_APP_SIZE) +#define FLASH_BINFO_SIZE (1*FLASH_SECTOR_SIZE) + +//user config +#define FLASH_CFG_BASE (FLASH_BINFO_BASE + FLASH_BINFO_SIZE) +#define FLASH_CFG_SIZE (1*FLASH_SECTOR_SIZE) + +#define FLASH_CFG_MAGIC (0xa5) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +int32_t hdl_flash_unlock(void); +int32_t hdl_flash_lock(void); + +int32_t hdl_flash_check_addralign(uint32_t u32Addr); +int32_t hdl_flash_erase_sector(uint32_t u32Addr, uint32_t u32Size); +int32_t hdl_flash_write_data(uint32_t u32Addr, uint8_t *pu8Buff, uint32_t u32Len); +int32_t hdl_flash_read_data(uint32_t u32Addr, uint8_t *pu8Buff, uint32_t u32Len); + +#ifdef __cplusplus +} +#endif + +#endif /* __FLASH_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/hdl/hdl_lcd.c b/hdl/hdl_lcd.c new file mode 100644 index 0000000..fbbe51e --- /dev/null +++ b/hdl/hdl_lcd.c @@ -0,0 +1,494 @@ +#include "hdl_lcd.h" + +static volatile uint8_t enTxCompleteFlag = 0; +lcd_dma_callback_t lcd_dma_cbs = NULL; +lcd_timer_callback_t lcd_timer_cbs = NULL; + +static void hdl_lcd_dma_tcpl_callback(void) +{ + enTxCompleteFlag = SET; + + if(lcd_dma_cbs) + { + lcd_dma_cbs(); + } + + DMA_ClearTransCompleteStatus(LCD_DMA_UNIT, LCD_DMA_TX_INT_CH); +} + +static void hdl_lcd_timer_callback(void) +{ + if(lcd_timer_cbs) + { + lcd_timer_cbs(); + } + + TMR0_ClearStatus(LCD_TIM_UINT, LCD_TIM_CH_FLAG); +} + +void hdl_lcd_timer_config(void) +{ + stc_tmr0_init_t stcTmr0Init; + stc_irq_signin_config_t stcIrqSignConfig; + + LL_PERIPH_WE(LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM); + + /* Enable timer0 and AOS clock */ + FCG_Fcg2PeriphClockCmd(LCD_TIM_CLK, ENABLE); + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_AOS, ENABLE); + + /* TIMER0 configuration */ + (void)TMR0_StructInit(&stcTmr0Init); + stcTmr0Init.u32ClockSrc = TMR0_CLK_SRC_INTERN_CLK; //ÄÚ²¿Ê±ÖÓ + stcTmr0Init.u32ClockDiv = TMR0_CLK_DIV64; //2·ÖƵ + stcTmr0Init.u32Func = TMR0_FUNC_CMP; //Êä³ö±È½Ï + stcTmr0Init.u16CompareValue = (uint16_t)LCD_TIME_CMP_VALUE; + (void)TMR0_Init(LCD_TIM_UINT, LCD_TIM_CH, &stcTmr0Init); + hdl_delay_ms(1U); + TMR0_HWStopCondCmd(LCD_TIM_UINT, LCD_TIM_CH, ENABLE); + hdl_delay_ms(1U); + TMR0_IntCmd(LCD_TIM_UINT, LCD_TIM_CH_INT, ENABLE); + + /* Interrupt configuration */ + stcIrqSignConfig.enIntSrc = LCD_TIM_INT_SRC; + stcIrqSignConfig.enIRQn = LCD_TIM_IRQn; + stcIrqSignConfig.pfnCallback = &hdl_lcd_timer_callback; + (void)INTC_IrqSignIn(&stcIrqSignConfig); + NVIC_ClearPendingIRQ(stcIrqSignConfig.enIRQn); + NVIC_SetPriority(stcIrqSignConfig.enIRQn, DDL_IRQ_PRIO_DEFAULT); + NVIC_EnableIRQ(stcIrqSignConfig.enIRQn); + + TMR0_Start(LCD_TIM_UINT, LCD_TIM_CH); + + LL_PERIPH_WP(LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM); +} + +void hdl_lcd_config(void) +{ + stc_spi_init_t stcSpiInit; + stc_dma_init_t stcDmaInit; + stc_irq_signin_config_t stcIrqSignConfig; + stc_gpio_init_t stcGpioInit; + + LL_PERIPH_WE(LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM); + + /* Òý½ÅÉèÖà */ + GPIO_SetDebugPort(GPIO_PIN_TRST,DISABLE); + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + (void)GPIO_Init(LCD_SCL_PORT, LCD_SCL_PIN, &stcGpioInit); + (void)GPIO_Init(LCD_SDA_PORT, LCD_SDA_PIN, &stcGpioInit); + + GPIO_SetFunc(LCD_SCL_PORT, LCD_SCL_PIN, LCD_SCL_FUNC); + GPIO_SetFunc(LCD_SDA_PORT, LCD_SDA_PIN, LCD_SDA_FUNC); + + stcGpioInit.u16PinDir = PIN_DIR_OUT; + (void)GPIO_Init(LCD_RES_PORT, LCD_RES_PIN, &stcGpioInit); + (void)GPIO_Init(LCD_DC_PORT, LCD_DC_PIN, &stcGpioInit); + + /* SPIÅäÖà */ + FCG_Fcg1PeriphClockCmd(LCD_SPI_CLK, ENABLE); + SPI_StructInit(&stcSpiInit); + stcSpiInit.u32WireMode = SPI_3_WIRE; + stcSpiInit.u32TransMode = SPI_SEND_ONLY; + stcSpiInit.u32MasterSlave = SPI_MASTER; + stcSpiInit.u32Parity = SPI_PARITY_INVD; + stcSpiInit.u32SpiMode = SPI_MD_3; + stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV2; + stcSpiInit.u32DataBits = SPI_DATA_SIZE_8BIT; + stcSpiInit.u32FirstBit = SPI_FIRST_MSB; + stcSpiInit.u32FrameLevel = SPI_1_FRAME; + (void)SPI_Init(LCD_SPI_UINT, &stcSpiInit); + + /* DMAÅäÖà */ + FCG_Fcg0PeriphClockCmd(LCD_DMA_CLK, ENABLE); + (void)DMA_StructInit(&stcDmaInit); + stcDmaInit.u32BlockSize = 1UL; + stcDmaInit.u32TransCount = 1; + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT; //Êý¾Ýλ¿í + stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_INC; //Ô´µØÖ·×ÔÔö + stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_FIX; //Ä¿±êµØÖ·¹Ì¶¨ + stcDmaInit.u32SrcAddr = (uint32_t)(0); + stcDmaInit.u32DestAddr = (uint32_t)(&LCD_SPI_UINT->DR); + stcDmaInit.u32IntEn = DMA_INT_ENABLE; + if (LL_OK != DMA_Init(LCD_DMA_UNIT, LCD_DMA_TX_CH, &stcDmaInit)) { + for (;;) { + } + } + AOS_SetTriggerEventSrc(LCD_DMA_TX_TRIG_CH, LCD_SPI_TX_EVT_SRC); //DMA·¢ËÍ´¥·¢Ô´ + + /* DMA ÖжÏÅäÖà */ + DMA_TransCompleteIntCmd(LCD_DMA_UNIT, DMA_INT_BTC_CH0, DISABLE); + + stcIrqSignConfig.enIntSrc = LCD_DMA_TX_INT_SRC; + stcIrqSignConfig.enIRQn = LCD_DMA_TX_IRQ_NUM; + stcIrqSignConfig.pfnCallback = &hdl_lcd_dma_tcpl_callback; + (void)INTC_IrqSignIn(&stcIrqSignConfig); + NVIC_ClearPendingIRQ(stcIrqSignConfig.enIRQn); + NVIC_SetPriority(stcIrqSignConfig.enIRQn, DDL_IRQ_PRIO_14); + NVIC_EnableIRQ(stcIrqSignConfig.enIRQn); + + LL_PERIPH_WP(LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM); + + DMA_Cmd(LCD_DMA_UNIT, ENABLE); + DMA_ChCmd(LCD_DMA_UNIT, LCD_DMA_TX_CH, ENABLE); +} + +static void hdl_lcd_write_byte(uint8_t dat) +{ + SPI_Cmd(LCD_SPI_UINT, ENABLE); + while (RESET == SPI_GetStatus(LCD_SPI_UINT, SPI_FLAG_TX_BUF_EMPTY)){} + SPI_WriteData(LCD_SPI_UINT, (uint32_t)dat); + while (RESET == SPI_GetStatus(LCD_SPI_UINT, SPI_FLAG_IDLE)){} + SPI_Cmd(LCD_SPI_UINT, DISABLE); +} + +void hdl_lcd_send(uint8_t *data, uint16_t len) +{ + LCD_DC_SET();//дÊý¾Ý + enTxCompleteFlag = RESET; + + DMA_SetSrcAddr(LCD_DMA_UNIT, LCD_DMA_TX_CH, (uint32_t)(data)); // ÖØÐÂÉèÖÃÔ´µØÖ·ºÍ·¢Ë͵ÄÊý¾Ý + DMA_SetTransCount(LCD_DMA_UNIT, LCD_DMA_TX_CH, len); //ÉèÖô«Êä´ÎÊý,´«ÊäÒ»´Î£¬¼ÆÊýÆ÷¼õµ½0Í£Ö¹ + + DMA_ChCmd(LCD_DMA_UNIT, LCD_DMA_TX_CH, ENABLE); //ʹÄÜDMA1ͨµÀ + SPI_Cmd(LCD_SPI_UINT, ENABLE); //ʹÄÜSPI + + while (RESET == enTxCompleteFlag) { + } + + SPI_Cmd(LCD_SPI_UINT, DISABLE); //ʧÄÜSPI +} + +void hdl_lcd_dma_callback_register(lcd_dma_callback_t pCBS) +{ + if(lcd_dma_cbs == 0) + { + lcd_dma_cbs = pCBS; + } +} + +void hdl_lcd_timer_callback_register(lcd_timer_callback_t pCBS) +{ + if(lcd_timer_cbs == 0) + { + lcd_timer_cbs = pCBS; + } +} + +/****************************************************************************** + º¯Êý˵Ã÷£ºLCDдÈëÊý¾Ý + Èë¿ÚÊý¾Ý£ºdat дÈëµÄÊý¾Ý + ·µ»ØÖµ£º ÎÞ +******************************************************************************/ +void LCD_WR_DATA8(uint8_t dat) +{ + LCD_DC_SET();//дÊý¾Ý + + hdl_lcd_write_byte(dat); +} + + +/****************************************************************************** + º¯Êý˵Ã÷£ºLCDдÈëÊý¾Ý + Èë¿ÚÊý¾Ý£ºdat дÈëµÄÊý¾Ý + ·µ»ØÖµ£º ÎÞ +******************************************************************************/ +void LCD_WR_DATA(uint16_t dat) +{ + LCD_DC_SET();//дÊý¾Ý + + hdl_lcd_write_byte(dat>>8); + hdl_lcd_write_byte(dat); +} + +/****************************************************************************** + º¯Êý˵Ã÷£ºLCDдÈëÃüÁî + Èë¿ÚÊý¾Ý£ºdat дÈëµÄÃüÁî + ·µ»ØÖµ£º ÎÞ +******************************************************************************/ +void LCD_WR_REG(uint8_t dat) +{ + LCD_DC_CLR();//дÃüÁî + + hdl_lcd_write_byte(dat); +} + +/****************************************************************************** + º¯Êý˵Ã÷£ºÉèÖÃÆðʼºÍ½áÊøµØÖ· + Èë¿ÚÊý¾Ý£ºx1,x2 ÉèÖÃÁеÄÆðʼºÍ½áÊøµØÖ· + y1,y2 ÉèÖÃÐеÄÆðʼºÍ½áÊøµØÖ· + ·µ»ØÖµ£º ÎÞ +******************************************************************************/ +void LCD_Address_Set(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2) +{ + LCD_WR_REG(0x2a);//ÁеØÖ·ÉèÖà + LCD_WR_DATA(x1); + LCD_WR_DATA(x2); + LCD_WR_REG(0x2b);//ÐеØÖ·ÉèÖà + LCD_WR_DATA(y1); + LCD_WR_DATA(y2); + LCD_WR_REG(0x2c);//´¢´æÆ÷д +} + +void hdl_lcd_fill(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2, uint8_t *color) +{ + LCD_Address_Set(x1,y1,x2,y2);//ÉèÖÃÏÔʾ·¶Î§ + + hdl_lcd_send(color, (x2-x1+1)*(y2-y1+1)*2); +} + +void LCD_DrawPoint(uint16_t x,uint16_t y,uint16_t color) +{ + LCD_Address_Set(x,y,x,y);//ÉèÖùâ±êλÖà + LCD_WR_DATA(color); +} + +void hdl_lcd_init(void) +{ + hdl_lcd_config(); + hdl_lcd_timer_config(); + + LCD_RES_CLR();//¸´Î» + hdl_delay_ms(100); + LCD_RES_SET(); + hdl_delay_ms(100); + + LCD_WR_REG(0xEF); + LCD_WR_REG(0xEB); + LCD_WR_DATA8(0x14); + + LCD_WR_REG(0xFE); + LCD_WR_REG(0xEF); + + LCD_WR_REG(0xEB); + LCD_WR_DATA8(0x14); + + LCD_WR_REG(0x84); + LCD_WR_DATA8(0x40); + + LCD_WR_REG(0x85); + LCD_WR_DATA8(0xFF); + + LCD_WR_REG(0x86); + LCD_WR_DATA8(0xFF); + + LCD_WR_REG(0x87); + LCD_WR_DATA8(0xFF); + + LCD_WR_REG(0x88); + LCD_WR_DATA8(0x0A); + + LCD_WR_REG(0x89); + LCD_WR_DATA8(0x21); + + LCD_WR_REG(0x8A); + LCD_WR_DATA8(0x00); + + LCD_WR_REG(0x8B); + LCD_WR_DATA8(0x80); + + LCD_WR_REG(0x8C); + LCD_WR_DATA8(0x01); + + LCD_WR_REG(0x8D); + LCD_WR_DATA8(0x01); + + LCD_WR_REG(0x8E); + LCD_WR_DATA8(0xFF); + + LCD_WR_REG(0x8F); + LCD_WR_DATA8(0xFF); + + + LCD_WR_REG(0xB6); + LCD_WR_DATA8(0x00); + LCD_WR_DATA8(0x20); + + LCD_WR_REG(0x36); + if(USE_HORIZONTAL==0)LCD_WR_DATA8(0x08); + else if(USE_HORIZONTAL==1)LCD_WR_DATA8(0xC8); + else if(USE_HORIZONTAL==2)LCD_WR_DATA8(0x68); + else LCD_WR_DATA8(0xA8); + + LCD_WR_REG(0x3A); + LCD_WR_DATA8(0x05); + + + LCD_WR_REG(0x90); + LCD_WR_DATA8(0x08); + LCD_WR_DATA8(0x08); + LCD_WR_DATA8(0x08); + LCD_WR_DATA8(0x08); + + LCD_WR_REG(0xBD); + LCD_WR_DATA8(0x06); + + LCD_WR_REG(0xBC); + LCD_WR_DATA8(0x00); + + LCD_WR_REG(0xFF); + LCD_WR_DATA8(0x60); + LCD_WR_DATA8(0x01); + LCD_WR_DATA8(0x04); + + LCD_WR_REG(0xC3); + LCD_WR_DATA8(0x13); + LCD_WR_REG(0xC4); + LCD_WR_DATA8(0x13); + LCD_WR_REG(0xC9); + LCD_WR_DATA8(0x22); + + LCD_WR_REG(0xBE); + LCD_WR_DATA8(0x11); + + LCD_WR_REG(0xE1); + LCD_WR_DATA8(0x10); + LCD_WR_DATA8(0x0E); + + LCD_WR_REG(0xDF); + LCD_WR_DATA8(0x21); + LCD_WR_DATA8(0x0c); + LCD_WR_DATA8(0x02); + + LCD_WR_REG(0xF0); + LCD_WR_DATA8(0x45); + LCD_WR_DATA8(0x09); + LCD_WR_DATA8(0x08); + LCD_WR_DATA8(0x08); + LCD_WR_DATA8(0x26); + LCD_WR_DATA8(0x2A); + + LCD_WR_REG(0xF1); + LCD_WR_DATA8(0x43); + LCD_WR_DATA8(0x70); + LCD_WR_DATA8(0x72); + LCD_WR_DATA8(0x36); + LCD_WR_DATA8(0x37); + LCD_WR_DATA8(0x6F); + + + LCD_WR_REG(0xF2); + LCD_WR_DATA8(0x45); + LCD_WR_DATA8(0x09); + LCD_WR_DATA8(0x08); + LCD_WR_DATA8(0x08); + LCD_WR_DATA8(0x26); + LCD_WR_DATA8(0x2A); + + LCD_WR_REG(0xF3); + LCD_WR_DATA8(0x43); + LCD_WR_DATA8(0x70); + LCD_WR_DATA8(0x72); + LCD_WR_DATA8(0x36); + LCD_WR_DATA8(0x37); + LCD_WR_DATA8(0x6F); + + LCD_WR_REG(0xED); + LCD_WR_DATA8(0x1B); + LCD_WR_DATA8(0x0B); + + LCD_WR_REG(0xAE); + LCD_WR_DATA8(0x77); + + LCD_WR_REG(0xCD); + LCD_WR_DATA8(0x63); + + + LCD_WR_REG(0x70); + LCD_WR_DATA8(0x07); + LCD_WR_DATA8(0x07); + LCD_WR_DATA8(0x04); + LCD_WR_DATA8(0x0E); + LCD_WR_DATA8(0x0F); + LCD_WR_DATA8(0x09); + LCD_WR_DATA8(0x07); + LCD_WR_DATA8(0x08); + LCD_WR_DATA8(0x03); + + LCD_WR_REG(0xE8); + LCD_WR_DATA8(0x34); + + LCD_WR_REG(0x62); + LCD_WR_DATA8(0x18); + LCD_WR_DATA8(0x0D); + LCD_WR_DATA8(0x71); + LCD_WR_DATA8(0xED); + LCD_WR_DATA8(0x70); + LCD_WR_DATA8(0x70); + LCD_WR_DATA8(0x18); + LCD_WR_DATA8(0x0F); + LCD_WR_DATA8(0x71); + LCD_WR_DATA8(0xEF); + LCD_WR_DATA8(0x70); + LCD_WR_DATA8(0x70); + + LCD_WR_REG(0x63); + LCD_WR_DATA8(0x18); + LCD_WR_DATA8(0x11); + LCD_WR_DATA8(0x71); + LCD_WR_DATA8(0xF1); + LCD_WR_DATA8(0x70); + LCD_WR_DATA8(0x70); + LCD_WR_DATA8(0x18); + LCD_WR_DATA8(0x13); + LCD_WR_DATA8(0x71); + LCD_WR_DATA8(0xF3); + LCD_WR_DATA8(0x70); + LCD_WR_DATA8(0x70); + + LCD_WR_REG(0x64); + LCD_WR_DATA8(0x28); + LCD_WR_DATA8(0x29); + LCD_WR_DATA8(0xF1); + LCD_WR_DATA8(0x01); + LCD_WR_DATA8(0xF1); + LCD_WR_DATA8(0x00); + LCD_WR_DATA8(0x07); + + LCD_WR_REG(0x66); + LCD_WR_DATA8(0x3C); + LCD_WR_DATA8(0x00); + LCD_WR_DATA8(0xCD); + LCD_WR_DATA8(0x67); + LCD_WR_DATA8(0x45); + LCD_WR_DATA8(0x45); + LCD_WR_DATA8(0x10); + LCD_WR_DATA8(0x00); + LCD_WR_DATA8(0x00); + LCD_WR_DATA8(0x00); + + LCD_WR_REG(0x67); + LCD_WR_DATA8(0x00); + LCD_WR_DATA8(0x3C); + LCD_WR_DATA8(0x00); + LCD_WR_DATA8(0x00); + LCD_WR_DATA8(0x00); + LCD_WR_DATA8(0x01); + LCD_WR_DATA8(0x54); + LCD_WR_DATA8(0x10); + LCD_WR_DATA8(0x32); + LCD_WR_DATA8(0x98); + + LCD_WR_REG(0x74); + LCD_WR_DATA8(0x10); + LCD_WR_DATA8(0x85); + LCD_WR_DATA8(0x80); + LCD_WR_DATA8(0x00); + LCD_WR_DATA8(0x00); + LCD_WR_DATA8(0x4E); + LCD_WR_DATA8(0x00); + + LCD_WR_REG(0x98); + LCD_WR_DATA8(0x3e); + LCD_WR_DATA8(0x07); + + LCD_WR_REG(0x35); + LCD_WR_REG(0x21); + + LCD_WR_REG(0x11); + hdl_delay_ms(120); + LCD_WR_REG(0x29); + hdl_delay_ms(20); +} diff --git a/hdl/hdl_lcd.h b/hdl/hdl_lcd.h new file mode 100644 index 0000000..1052dce --- /dev/null +++ b/hdl/hdl_lcd.h @@ -0,0 +1,99 @@ +#ifndef ____HDL_LCD_H_ +#define ____HDL_LCD_H_ + +#include "hc32_ll.h" +#include "hdl_clk.h" + +#include "lvgl.h" + +/* lcdË¢ÆÁ¶¨Ê±Æ÷´¦Àí */ +#define LCD_TIM_UINT CM_TMR0_1 +#define LCD_TIM_CLK FCG2_PERIPH_TMR0_1 +#define LCD_TIM_CH TMR0_CH_B +#define LCD_TIM_TRIG_CH AOS_TMR0 +#define LCD_TIM_CH_INT TMR0_INT_CMP_B +#define LCD_TIM_CH_FLAG TMR0_FLAG_CMP_B +#define LCD_TIM_INT_SRC INT_SRC_TMR0_1_CMP_B +#define LCD_TIM_IRQn INT007_IRQn + +#define LCD_TIME_CMP_VALUE (1563) + +#define USE_HORIZONTAL 0 //ÉèÖúáÆÁ»òÕßÊúÆÁÏÔʾ 0»ò1ΪÊúÆÁ 2»ò3ΪºáÆÁ + +#define LCD_W 240 +#define LCD_H 240 + +#define LCD_SPI_UINT CM_SPI3 +#define LCD_SPI_CLK FCG1_PERIPH_SPI3 +#define LCD_SPI_TX_EVT_SRC EVT_SRC_SPI3_SPTI +#define LCD_SCL_PORT GPIO_PORT_B +#define LCD_SCL_PIN GPIO_PIN_07 +#define LCD_SCL_FUNC GPIO_FUNC_43 +#define LCD_SDA_PORT GPIO_PORT_B +#define LCD_SDA_PIN GPIO_PIN_06 +#define LCD_SDA_FUNC GPIO_FUNC_40 + +#define LCD_DMA_UNIT CM_DMA1 +#define LCD_DMA_CLK (FCG0_PERIPH_DMA1 | FCG0_PERIPH_AOS) +#define LCD_DMA_TX_CH DMA_CH0 +#define LCD_DMA_TX_TRIG_CH AOS_DMA1_0 +#define LCD_DMA_TX_INT_CH DMA_INT_TC_CH0 +#define LCD_DMA_TX_INT_SRC INT_SRC_DMA1_TC0 +#define LCD_DMA_TX_IRQ_NUM INT006_IRQn + + +#define LCD_RES_PORT GPIO_PORT_B +#define LCD_RES_PIN GPIO_PIN_05 +#define LCD_DC_PORT GPIO_PORT_B +#define LCD_DC_PIN GPIO_PIN_04 +#define LCD_RES_SET() GPIO_SetPins(LCD_RES_PORT, LCD_RES_PIN) +#define LCD_RES_CLR() GPIO_ResetPins(LCD_RES_PORT, LCD_RES_PIN) +#define LCD_DC_SET() GPIO_SetPins(LCD_DC_PORT, LCD_DC_PIN) +#define LCD_DC_CLR() GPIO_ResetPins(LCD_DC_PORT, LCD_DC_PIN) + +#define LCD_SCLK_Clr() GPIO_ResetPins(GPIO_PORT_B,GPIO_PIN_07)//SCL=SCLK +#define LCD_SCLK_Set() GPIO_SetPins(GPIO_PORT_B,GPIO_PIN_07) + +#define LCD_MOSI_Clr() GPIO_ResetPins(GPIO_PORT_B,GPIO_PIN_06)//SDA=MOSI +#define LCD_MOSI_Set() GPIO_SetPins(GPIO_PORT_B,GPIO_PIN_06) + +//»­±ÊÑÕÉ« +#define WHITE 0xFFFF +#define BLACK 0x0000 +#define BLUE 0x001F +#define BRED 0XF81F +#define GRED 0XFFE0 +#define GBLUE 0X07FF +#define RED 0xF800 +#define MAGENTA 0xF81F +#define GREEN 0x07E0 +#define CYAN 0x7FFF +#define YELLOW 0xFFE0 +#define BROWN 0XBC40 //×ØÉ« +#define BRRED 0XFC07 //×غìÉ« +#define GRAY 0X8430 //»ÒÉ« +#define DARKBLUE 0X01CF //ÉîÀ¶É« +#define LIGHTBLUE 0X7D7C //dzÀ¶É« +#define GRAYBLUE 0X5458 //»ÒÀ¶É« +#define LIGHTGREEN 0X841F //dzÂÌÉ« +#define LGRAY 0XC618 //dz»ÒÉ«(PANNEL),´°Ìå±³¾°É« +#define LGRAYBLUE 0XA651 //dz»ÒÀ¶É«(Öмä²ãÑÕÉ«) +#define LBBLUE 0X2B12 //dz×ØÀ¶É«(Ñ¡ÔñÌõÄ¿µÄ·´É«) + +typedef void (*lcd_dma_callback_t)(void); +typedef void (*lcd_timer_callback_t)(void); + +void hdl_lcd_init(void); + +void hdl_lcd_send(uint8_t *data, uint16_t len); + +void LCD_Address_Set(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2); + +void LCD_DrawPoint(uint16_t x,uint16_t y,uint16_t color); + +void hdl_lcd_fill(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2, uint8_t *color); + +void hdl_lcd_dma_callback_register(lcd_dma_callback_t pCBS); +void hdl_lcd_timer_callback_register(lcd_timer_callback_t pCBS); + +#endif diff --git a/hdl/hdl_led.c b/hdl/hdl_led.c new file mode 100644 index 0000000..a031178 --- /dev/null +++ b/hdl/hdl_led.c @@ -0,0 +1,40 @@ +#include "hdl_led.h" + +#define LED_PORT (GPIO_PORT_H) +#define LED_PIN (GPIO_PIN_02) + +void hdl_led_init(void){ + + LL_PERIPH_WE(LL_PERIPH_GPIO); + + stc_gpio_init_t stcGpioInit={0}; + + //GPIO_StructInit(&stcGpioInit); + + stcGpioInit.u16PinDir = PIN_DIR_OUT; + + stcGpioInit.u16PinState = PIN_STAT_SET; + + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + + (void)GPIO_Init( LED_PORT ,LED_PIN, &stcGpioInit); + + LL_PERIPH_WP(LL_PERIPH_GPIO); + +} + +void hdl_led_on(hdl_led_id_t id){ + + GPIO_SetPins(LED_PORT ,LED_PIN ); +} + +void hdl_led_off(hdl_led_id_t id){ + + GPIO_ResetPins(LED_PORT ,LED_PIN); +} + +void hdl_led_toggle(hdl_led_id_t id){ + + GPIO_ResetPins(LED_PORT ,LED_PIN); +} + diff --git a/hdl/hdl_led.h b/hdl/hdl_led.h new file mode 100644 index 0000000..f0b6b3d --- /dev/null +++ b/hdl/hdl_led.h @@ -0,0 +1,26 @@ +#ifndef _HDL_LED_H_ +#define _HDL_LED_H_ +#include "hc32_ll.h" +#include "stdint.h" + +typedef enum +{ + HDL_LED_ID_0, + HDL_LED_ID_MAX, +}hdl_led_id_t; + +typedef struct +{ + uint8_t port; + uint16_t pin; +}hdl_led_t; + +extern void hdl_led_init(void); + +extern void hdl_led_on(hdl_led_id_t id); + +extern void hdl_led_off(hdl_led_id_t id); + +extern void hdl_led_toggle(hdl_led_id_t id); + +#endif diff --git a/hdl/hdl_pwm.c b/hdl/hdl_pwm.c new file mode 100644 index 0000000..3fe6bca --- /dev/null +++ b/hdl/hdl_pwm.c @@ -0,0 +1,89 @@ +#include "hdl_pwm.h" + +/*unit 0.01us*/ +static void TmrAConfig(uint32_t t) +{ + + stc_clock_freq_t sysFrq; + + CLK_GetClockFreq(&sysFrq); + + uint32_t peroid = 1.0 *sysFrq.u32Pclk1Freq / t; + + stc_tmra_init_t stcTmraInit; + stc_tmra_pwm_init_t stcPwmInit; + + /* 1. Enable TimerA peripheral clock. */ + FCG_Fcg2PeriphClockCmd(TMRA_PERIPH_CLK, ENABLE); + + /* 2. Set a default initialization value for stcTmraInit. */ + (void)TMRA_StructInit(&stcTmraInit); + + /* 3. Modifies the initialization values depends on the application. */ + stcTmraInit.sw_count.u8CountMode = TMRA_MD; + stcTmraInit.sw_count.u8CountDir = TMRA_DIR; + stcTmraInit.u32PeriodValue = (peroid-1); + (void)TMRA_Init(TMRA_UNIT, &stcTmraInit); + + /* 4. Set the comparison reference value. */ +#if (APP_FUNC == APP_FUNC_NORMAL_SINGLE_PWM) + (void)TMRA_PWM_StructInit(&stcPwmInit); + + stcPwmInit.u32CompareValue = 0; + stcPwmInit.u16PeriodMatchPolarity = TMRA_PWM_HIGH; + GPIO_SetFunc(TMRA_PWM_PORT, TMRA_PWM_PIN, TMRA_PWM_PIN_FUNC); + (void)TMRA_PWM_Init(TMRA_UNIT, TMRA_PWM_CH, &stcPwmInit); + TMRA_PWM_OutputCmd(TMRA_UNIT, TMRA_PWM_CH, ENABLE); +#endif + +} + + +void hdl_pwm_init(int frq){ + + /* MCU Peripheral registers write unprotected. */ + LL_PERIPH_WE(LL_PERIPH_GPIO | LL_PERIPH_FCG | LL_PERIPH_PWC_CLK_RMU); + + /* Configures TimerA. */ + TmrAConfig( frq); + + /* MCU Peripheral registers write protected. */ + LL_PERIPH_WP(LL_PERIPH_GPIO | LL_PERIPH_FCG | LL_PERIPH_PWC_CLK_RMU); + +} + +void hdl_pwm_enable(void){ + + /* Starts TimerA. */ + TMRA_Start(TMRA_UNIT); +} + +void hdl_pwm_disable(void){ + + /* Starts TimerA. */ + TMRA_Stop(TMRA_UNIT); +} + +void hdl_pwm_set_duty(int duty){ + + uint32_t period = TMRA_GetPeriodValue(TMRA_UNIT)+1; + + uint32_t val = duty*0.01*period; + + if(val <1){ + val =1; + } + + if(val >period){ + val =period; + } + + TMRA_Stop(TMRA_UNIT); + TMRA_SetCountValue(TMRA_UNIT,0); + TMRA_SetCompareValue(TMRA_UNIT,TMRA_PWM_CH,val-1); + TMRA_Start(TMRA_UNIT); +} + + + + diff --git a/hdl/hdl_pwm.h b/hdl/hdl_pwm.h new file mode 100644 index 0000000..abe681b --- /dev/null +++ b/hdl/hdl_pwm.h @@ -0,0 +1,26 @@ +#ifndef ____HDL_PWM_H_ +#define ____HDL_PWM_H_ + +#include "hc32_ll.h" + +#define TMRA_UNIT (CM_TMRA_1) +#define TMRA_PERIPH_CLK (FCG2_PERIPH_TMRA_1) +#define TMRA_PWM_CH (TMRA_CH1) + +#define TMRA_PWM_PORT (GPIO_PORT_A) +#define TMRA_PWM_PIN (GPIO_PIN_08) +#define TMRA_PWM_PIN_FUNC (GPIO_FUNC_4) + +#define TMRA_MD (TMRA_MD_SAWTOOTH) +#define TMRA_DIR (TMRA_DIR_UP) + +void hdl_pwm_init(int frq); + +void hdl_pwm_enable(void); + +void hdl_pwm_disable(void); + +void hdl_pwm_set_duty(int duty); + +#endif + diff --git a/hdl/hdl_spi.c b/hdl/hdl_spi.c new file mode 100644 index 0000000..1b8d797 --- /dev/null +++ b/hdl/hdl_spi.c @@ -0,0 +1,216 @@ +#include "hdl_spi.h" + +void hdl_spi1_init(void) +{ + stc_spi_init_t stcSpiInit; + stc_gpio_init_t stcGpioInit; + + LL_PERIPH_WE(LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM); + + /* é…ç½®SPI引脚 */ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + + (void)GPIO_Init(SPI1_SCLK_PORT, SPI1_SCLK_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit); + + GPIO_SetFunc(SPI1_SCLK_PORT, SPI1_SCLK_PIN, SPI1_SCLK_FUNC); + GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC); + GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC); + + /* é…ç½®SPIå‚æ•° */ + SPI_StructInit(&stcSpiInit); + + FCG_Fcg1PeriphClockCmd(SPI1_CLOCK, ENABLE); + + stcSpiInit.u32WireMode = SPI_3_WIRE; //3线SPI + stcSpiInit.u32TransMode = SPI_FULL_DUPLEX; //å…¨åŒå·¥ + stcSpiInit.u32MasterSlave = SPI_MASTER; //主机 + stcSpiInit.u32ModeFaultDetect = SPI_MD_FAULT_DETECT_DISABLE; // ç¦ç”¨æ¨¡å¼æ•…障检测 + stcSpiInit.u32Parity = SPI_PARITY_INVD; //无奇å¶æ ¡éªŒ + stcSpiInit.u32SpiMode = SPI_MD_3; //SPI模å¼3 + stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV64; //预分频 + stcSpiInit.u32DataBits = SPI_DATA_SIZE_8BIT; //æ•°æ®å®½åº¦ + stcSpiInit.u32FirstBit = SPI_FIRST_MSB; //MSB高ä½æœ‰æ•ˆ + (void)SPI_Init(SPI1_INSTANCE, &stcSpiInit); + SPI_Cmd(SPI1_INSTANCE, ENABLE); + + LL_PERIPH_WP(LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM); + +} + +uint8_t hdl_spi1_txrx(uint8_t w_data) +{ + uint8_t r_data = 0; + uint16_t retry = 0; + + while (RESET == SPI_GetStatus(SPI1_INSTANCE, SPI_FLAG_TX_BUF_EMPTY)) + { + retry++; + if(retry > 200) + { + return 0; + } + } + SPI_WriteData(SPI1_INSTANCE, (uint32_t)w_data); + + while (RESET == SPI_GetStatus(SPI1_INSTANCE, SPI_FLAG_RX_BUF_FULL)) + { + retry++; + if(retry > 200) + { + return 0; + } + } + r_data = SPI_ReadData(SPI1_INSTANCE); + + return r_data; +} + + +void hdl_spi2_init(void) +{ + stc_spi_init_t stcSpiInit; + stc_gpio_init_t stcGpioInit; + + LL_PERIPH_WE(LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM); + + /* é…ç½®SPI引脚 */ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + + (void)GPIO_Init(SPI2_SCLK_PORT, SPI2_SCLK_PIN, &stcGpioInit); + (void)GPIO_Init(SPI2_MOSI_PORT, SPI2_MOSI_PIN, &stcGpioInit); + (void)GPIO_Init(SPI2_MISO_PORT, SPI2_MISO_PIN, &stcGpioInit); + + GPIO_SetFunc(SPI2_SCLK_PORT, SPI2_SCLK_PIN, SPI2_SCLK_FUNC); + GPIO_SetFunc(SPI2_MOSI_PORT, SPI2_MOSI_PIN, SPI2_MOSI_FUNC); + GPIO_SetFunc(SPI2_MISO_PORT, SPI2_MISO_PIN, SPI2_MISO_FUNC); + + /* é…ç½®SPIå‚æ•° */ + SPI_StructInit(&stcSpiInit); + + FCG_Fcg1PeriphClockCmd(SPI2_CLOCK, ENABLE); + + stcSpiInit.u32WireMode = SPI_3_WIRE; //3线SPI + stcSpiInit.u32TransMode = SPI_FULL_DUPLEX; //å…¨åŒå·¥ + stcSpiInit.u32MasterSlave = SPI_MASTER; //主机 + stcSpiInit.u32ModeFaultDetect = SPI_MD_FAULT_DETECT_DISABLE; // ç¦ç”¨æ¨¡å¼æ•…障检测 + stcSpiInit.u32Parity = SPI_PARITY_INVD; //无奇å¶æ ¡éªŒ + stcSpiInit.u32SpiMode = SPI_MD_3; //SPI模å¼3 + stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV64; //预分频 + stcSpiInit.u32DataBits = SPI_DATA_SIZE_8BIT; //æ•°æ®å®½åº¦ + stcSpiInit.u32FirstBit = SPI_FIRST_MSB; //MSB高ä½æœ‰æ•ˆ + (void)SPI_Init(SPI2_INSTANCE, &stcSpiInit); + SPI_Cmd(SPI2_INSTANCE, ENABLE); + + LL_PERIPH_WP(LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM); + +} + +uint8_t hdl_spi2_txrx(uint8_t w_data) +{ + uint8_t r_data = 0; + uint16_t retry = 0; + + while (RESET == SPI_GetStatus(SPI2_INSTANCE, SPI_FLAG_TX_BUF_EMPTY)) + { + retry++; + if(retry > 200) + { + return 0; + } + } + SPI_WriteData(SPI2_INSTANCE, (uint32_t)w_data); + + while (RESET == SPI_GetStatus(SPI2_INSTANCE, SPI_FLAG_RX_BUF_FULL)) + { + retry++; + if(retry > 200) + { + return 0; + } + } + r_data = SPI_ReadData(SPI2_INSTANCE); + + return r_data; +} + + + +void hdl_spi3_init(void) +{ + stc_spi_init_t stcSpiInit; + stc_gpio_init_t stcGpioInit; + + LL_PERIPH_WE(LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM); + + /* é…ç½®SPI引脚 */ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + + (void)GPIO_Init(SPI3_SCLK_PORT, SPI3_SCLK_PIN, &stcGpioInit); + (void)GPIO_Init(SPI3_MOSI_PORT, SPI3_MOSI_PIN, &stcGpioInit); + (void)GPIO_Init(SPI3_MISO_PORT, SPI3_MISO_PIN, &stcGpioInit); + + GPIO_SetFunc(SPI3_SCLK_PORT, SPI3_SCLK_PIN, SPI3_SCLK_FUNC); + GPIO_SetFunc(SPI3_MOSI_PORT, SPI3_MOSI_PIN, SPI3_MOSI_FUNC); + GPIO_SetFunc(SPI3_MISO_PORT, SPI3_MISO_PIN, SPI3_MISO_FUNC); + + /* é…ç½®SPIå‚æ•° */ + SPI_StructInit(&stcSpiInit); + + FCG_Fcg1PeriphClockCmd(SPI3_CLOCK, ENABLE); + + stcSpiInit.u32WireMode = SPI_3_WIRE; //3线SPI + stcSpiInit.u32TransMode = SPI_FULL_DUPLEX; //å…¨åŒå·¥ + stcSpiInit.u32MasterSlave = SPI_MASTER; //主机 + stcSpiInit.u32ModeFaultDetect = SPI_MD_FAULT_DETECT_DISABLE; // ç¦ç”¨æ¨¡å¼æ•…障检测 + stcSpiInit.u32Parity = SPI_PARITY_INVD; //无奇å¶æ ¡éªŒ + stcSpiInit.u32SpiMode = SPI_MD_3; //SPI模å¼3 + stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV64; //预分频 + stcSpiInit.u32DataBits = SPI_DATA_SIZE_8BIT; //æ•°æ®å®½åº¦ + stcSpiInit.u32FirstBit = SPI_FIRST_MSB; //MSB高ä½æœ‰æ•ˆ + (void)SPI_Init(SPI3_INSTANCE, &stcSpiInit); + SPI_Cmd(SPI3_INSTANCE, ENABLE); + + LL_PERIPH_WP(LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM); + +} + +uint8_t hdl_spi3_txrx(uint8_t w_data) +{ + uint8_t r_data = 0; + uint16_t retry = 0; + + while (RESET == SPI_GetStatus(SPI3_INSTANCE, SPI_FLAG_TX_BUF_EMPTY)) + { + retry++; + if(retry > 200) + { + return 0; + } + } + SPI_WriteData(SPI3_INSTANCE, (uint32_t)w_data); + + while (RESET == SPI_GetStatus(SPI3_INSTANCE, SPI_FLAG_RX_BUF_FULL)) + { + retry++; + if(retry > 200) + { + return 0; + } + } + r_data = SPI_ReadData(SPI3_INSTANCE); + + return r_data; +} + + diff --git a/hdl/hdl_spi.h b/hdl/hdl_spi.h new file mode 100644 index 0000000..0bdf17c --- /dev/null +++ b/hdl/hdl_spi.h @@ -0,0 +1,80 @@ +#ifndef __HDL_SPI_H_ +#define __HDL_SPI_H_ + +#include "hc32_ll.h" +#include "hdl_clk.h" + + +//logic spi1 +#define SPI1_CLOCK FCG1_PERIPH_SPI1 +#define SPI1_INSTANCE CM_SPI1 + +#define SPI1_SCLK_FUNC GPIO_FUNC_43 +#define SPI1_SCLK_PORT GPIO_PORT_A +#define SPI1_SCLK_PIN GPIO_PIN_00 + + +#define SPI1_MISO_FUNC GPIO_FUNC_41 +#define SPI1_MISO_PORT GPIO_PORT_A +#define SPI1_MISO_PIN GPIO_PIN_02 + + +#define SPI1_MOSI_FUNC GPIO_FUNC_40 +#define SPI1_MOSI_PORT GPIO_PORT_A +#define SPI1_MOSI_PIN GPIO_PIN_03 + + + +//logic spi2 +#define SPI2_CLOCK FCG1_PERIPH_SPI4 +#define SPI2_INSTANCE CM_SPI4 + + +#define SPI2_SCLK_FUNC GPIO_FUNC_47 +#define SPI2_SCLK_PORT GPIO_PORT_B +#define SPI2_SCLK_PIN GPIO_PIN_13 + +#define SPI2_MISO_FUNC GPIO_FUNC_45 +#define SPI2_MISO_PORT GPIO_PORT_B +#define SPI2_MISO_PIN GPIO_PIN_14 + +#define SPI2_MOSI_FUNC GPIO_FUNC_44 +#define SPI2_MOSI_PORT GPIO_PORT_B +#define SPI2_MOSI_PIN GPIO_PIN_15 + + + +//logic spi3 +#define SPI3_CLOCK FCG1_PERIPH_SPI3 +#define SPI3_INSTANCE CM_SPI3 + +#define SPI3_SCLK_PORT GPIO_PORT_B +#define SPI3_SCLK_PIN GPIO_PIN_06 +#define SPI3_SCLK_FUNC GPIO_FUNC_43 + +#define SPI3_MISO_PORT GPIO_PORT_B +#define SPI3_MISO_PIN GPIO_PIN_07 +#define SPI3_MISO_FUNC GPIO_FUNC_41 + +#define SPI3_MOSI_PORT GPIO_PORT_B +#define SPI3_MOSI_PIN GPIO_PIN_08 +#define SPI3_MOSI_FUNC GPIO_FUNC_40 + + +void hdl_spi1_init(void); + +uint8_t hdl_spi1_txrx(uint8_t w_data); + +void hdl_spi2_init(void); + +uint8_t hdl_spi2_txrx(uint8_t w_data); + +void hdl_spi3_init(void); + +uint8_t hdl_spi3_txrx(uint8_t w_data); + +#endif + + + + diff --git a/hdl/hdl_spi4.c b/hdl/hdl_spi4.c new file mode 100644 index 0000000..0db8068 --- /dev/null +++ b/hdl/hdl_spi4.c @@ -0,0 +1,71 @@ +#include "hdl_spi4.h" + +void hdl_spi4_init(void) +{ + stc_spi_init_t stcSpiInit; + stc_gpio_init_t stcGpioInit; + + LL_PERIPH_WE(LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM); + + /* é…ç½®SPI引脚 */ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + + (void)GPIO_Init(SPI4_SCLK_PORT, SPI4_SCLK_PIN, &stcGpioInit); + (void)GPIO_Init(SPI4_MOSI_PORT, SPI4_MOSI_PIN, &stcGpioInit); + (void)GPIO_Init(SPI4_MISO_PORT, SPI4_MISO_PIN, &stcGpioInit); + + GPIO_SetFunc(SPI4_SCLK_PORT, SPI4_SCLK_PIN, SPI4_SCLK_FUNC); + GPIO_SetFunc(SPI4_MOSI_PORT, SPI4_MOSI_PIN, SPI4_MOSI_FUNC); + GPIO_SetFunc(SPI4_MISO_PORT, SPI4_MISO_PIN, SPI4_MISO_FUNC); + + /* é…ç½®SPIå‚æ•° */ + SPI_StructInit(&stcSpiInit); + + FCG_Fcg1PeriphClockCmd(SPI4_CLOCK, ENABLE); + + stcSpiInit.u32WireMode = SPI_3_WIRE; //3线SPI + stcSpiInit.u32TransMode = SPI_FULL_DUPLEX; //å…¨åŒå·¥ + stcSpiInit.u32MasterSlave = SPI_MASTER; //主机 + stcSpiInit.u32ModeFaultDetect = SPI_MD_FAULT_DETECT_DISABLE; // ç¦ç”¨æ¨¡å¼æ•…障检测 + stcSpiInit.u32Parity = SPI_PARITY_INVD; //无奇å¶æ ¡éªŒ + stcSpiInit.u32SpiMode = SPI_MD_3; //SPI模å¼3 + stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV64; //预分频 + stcSpiInit.u32DataBits = SPI_DATA_SIZE_8BIT; //æ•°æ®å®½åº¦ + stcSpiInit.u32FirstBit = SPI_FIRST_MSB; //MSB高ä½æœ‰æ•ˆ + (void)SPI_Init(SPI4_INSTANCE, &stcSpiInit); + SPI_Cmd(SPI4_INSTANCE, ENABLE); + + LL_PERIPH_WP(LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM); + +} + +uint8_t hdl_spi4_txrx(uint8_t w_data) +{ + uint8_t r_data = 0; + uint16_t retry = 0; + + while (RESET == SPI_GetStatus(SPI4_INSTANCE, SPI_FLAG_TX_BUF_EMPTY)) + { + retry++; + if(retry > 200) + { + return 0; + } + } + SPI_WriteData(SPI4_INSTANCE, (uint32_t)w_data); + + while (RESET == SPI_GetStatus(SPI4_INSTANCE, SPI_FLAG_RX_BUF_FULL)) + { + retry++; + if(retry > 200) + { + return 0; + } + } + r_data = SPI_ReadData(SPI4_INSTANCE); + + return r_data; +} diff --git a/hdl/hdl_spi4.h b/hdl/hdl_spi4.h new file mode 100644 index 0000000..3f03620 --- /dev/null +++ b/hdl/hdl_spi4.h @@ -0,0 +1,29 @@ +#ifndef __HDL_SPI4_H_ +#define __HDL_SPI4_H_ + +#include "hc32_ll.h" +#include "hdl_clk.h" + +//logic spi4 +#define SPI4_CLOCK FCG1_PERIPH_SPI1 +#define SPI4_INSTANCE CM_SPI1 + +#define SPI4_SCLK_PORT GPIO_PORT_A +#define SPI4_SCLK_PIN GPIO_PIN_03 +#define SPI4_SCLK_FUNC GPIO_FUNC_43 + +#define SPI4_MISO_PORT GPIO_PORT_A +#define SPI4_MISO_PIN GPIO_PIN_01 +#define SPI4_MISO_FUNC GPIO_FUNC_41 + +#define SPI4_MOSI_PORT GPIO_PORT_A +#define SPI4_MOSI_PIN GPIO_PIN_04 +#define SPI4_MOSI_FUNC GPIO_FUNC_40 + +void hdl_spi4_init(void); + +uint8_t hdl_spi4_txrx(uint8_t w_data); + +#endif + + diff --git a/hdl/hdl_usart.c b/hdl/hdl_usart.c new file mode 100644 index 0000000..18cedcd --- /dev/null +++ b/hdl/hdl_usart.c @@ -0,0 +1,210 @@ +#include "stdio.h" +#include +#include +#include +#include +#include "hdl_usart.h" + + +//定义数æ®èŽ·å–回调函数 +static hdl_debug_uart_rx_cb_t debug_rx_callback_cbs; +static com_rx_callback com_rx_callback_cbs; + +//接收中断 +static void COM_Rx_IrqCallback(void); +static void COM_RxErr_IrqCallback(void); + +static void INTC_IrqInstalHandler(const stc_irq_signin_config_t* pstcConfig, uint32_t u32Priority) +{ + if (NULL != pstcConfig) + { + (void)INTC_IrqSignIn(pstcConfig); + NVIC_ClearPendingIRQ(pstcConfig->enIRQn); + NVIC_SetPriority(pstcConfig->enIRQn, u32Priority); + NVIC_EnableIRQ(pstcConfig->enIRQn); + } +} + +//è°ƒè¯•ä¸²å£ +static void DEBUG_RxErr_IrqCallback(void) +{ + (void)USART_ReadData(DEBUG_UART); + + USART_ClearStatus(DEBUG_UART, (USART_FLAG_PARITY_ERR | USART_FLAG_FRAME_ERR | USART_FLAG_OVERRUN)); +} + +static void DEBUG_Rx_IrqCallback(void) +{ + uint8_t r_data = 0; + + r_data = USART_ReadData(DEBUG_UART); + + if (debug_rx_callback_cbs) + { + debug_rx_callback_cbs(r_data); + } +} + +void hdl_debug_uart_rx_reg(hdl_debug_uart_rx_cb_t pCBS) +{ + if (debug_rx_callback_cbs == 0) + { + debug_rx_callback_cbs = pCBS; + } +} + +void hdl_debug_uart_init(void) +{ + stc_usart_uart_init_t stcUartInit; + + debug_rx_callback_cbs = 0; + + LL_PERIPH_WE( + LL_PERIPH_GPIO | + LL_PERIPH_FCG | + LL_PERIPH_PWC_CLK_RMU | + LL_PERIPH_EFM | + LL_PERIPH_SRAM + ); + + GPIO_SetDebugPort(GPIO_PIN_TRST, DISABLE); + + GPIO_SetFunc(DEBUG_UART_RX_PORT, DEBUG_UART_RX_PIN, DEBUG_UART_RX_GPIO_FUNC); + GPIO_SetFunc(DEBUG_UART_TX_PORT, DEBUG_UART_TX_PIN, DEBUG_UART_TX_GPIO_FUNC); + + FCG_Fcg1PeriphClockCmd(DEBUG_UART_CLK, ENABLE); + + (void)USART_UART_StructInit(&stcUartInit); + stcUartInit.u32ClockDiv = USART_CLK_DIV1; + stcUartInit.u32Baudrate = 115200UL; + stcUartInit.u32OverSampleBit = USART_OVER_SAMPLE_8BIT; + USART_UART_Init(DEBUG_UART, &stcUartInit, NULL); + + //接收中断é…ç½® + stc_irq_signin_config_t stcIrqSigninConfig; + stcIrqSigninConfig.enIRQn = DEBUG_UART_INT_EI_IRQ; + stcIrqSigninConfig.enIntSrc = DEBUG_UART_INT_EI; + stcIrqSigninConfig.pfnCallback = &DEBUG_RxErr_IrqCallback; + INTC_IrqInstalHandler(&stcIrqSigninConfig, DDL_IRQ_PRIO_DEFAULT); + + stcIrqSigninConfig.enIRQn = DEBUG_UART_INT_RI_IRQ; + stcIrqSigninConfig.enIntSrc = DEBUG_UART_INT_RI; + stcIrqSigninConfig.pfnCallback = &DEBUG_Rx_IrqCallback; + INTC_IrqInstalHandler(&stcIrqSigninConfig, DDL_IRQ_PRIO_DEFAULT); + + LL_PERIPH_WP( + LL_PERIPH_GPIO | + LL_PERIPH_FCG | + LL_PERIPH_PWC_CLK_RMU | + LL_PERIPH_EFM | + LL_PERIPH_SRAM + ); + + USART_FuncCmd(DEBUG_UART, (USART_TX | USART_RX | USART_INT_RX), ENABLE); + //USART_FuncCmd(DEBUG_UART, (USART_TX | USART_RX ), ENABLE); +} + +void hdl_debug_uart_putc(uint8_t ch) +{ + while (USART_GetStatus(DEBUG_UART, USART_FLAG_TX_EMPTY) == RESET); + + USART_WriteData(DEBUG_UART, ch); + +} + +int hdl_debug_uart_getc(int *ch) +{ + if(USART_GetStatus(DEBUG_UART, USART_FLAG_RX_FULL) ==SET){ + + *ch = USART_ReadData(DEBUG_UART); + + return 0; + + }else{ + + return -1; + } + +} + +//通信模å—串å£åˆå§‹åŒ– +void hdl_com_uart_init(void) +{ + stc_usart_uart_init_t stcUartInit={0}; + stc_irq_signin_config_t stcIrqSigninConfig; + + com_rx_callback_cbs = 0; + + LL_PERIPH_WE(LL_PERIPH_GPIO | LL_PERIPH_FCG | LL_PERIPH_PWC_CLK_RMU | \ + LL_PERIPH_EFM | LL_PERIPH_SRAM); + + GPIO_SetFunc(COM_RX_PORT, COM_RX_PIN, COM_RX_GPIO_FUNC); + GPIO_SetFunc(COM_TX_PORT, COM_TX_PIN, COM_TX_GPIO_FUNC); + + FCG_Fcg1PeriphClockCmd(COM_UART_CLK, ENABLE); + + (void)USART_UART_StructInit(&stcUartInit); + stcUartInit.u32ClockDiv = USART_CLK_DIV1; + stcUartInit.u32Baudrate = 500000UL; + stcUartInit.u32OverSampleBit = USART_OVER_SAMPLE_8BIT; + USART_UART_Init(COM_UART, &stcUartInit, NULL); + + //接收中断é…ç½® + stcIrqSigninConfig.enIRQn = COM_INT_EI_IRQ; + stcIrqSigninConfig.enIntSrc = COM_INT_EI; + stcIrqSigninConfig.pfnCallback = &COM_RxErr_IrqCallback; + INTC_IrqInstalHandler(&stcIrqSigninConfig, DDL_IRQ_PRIO_DEFAULT); + + stcIrqSigninConfig.enIRQn = COM_INT_RI_IRQ; + stcIrqSigninConfig.enIntSrc = COM_INT_RI; + stcIrqSigninConfig.pfnCallback = &COM_Rx_IrqCallback; + INTC_IrqInstalHandler(&stcIrqSigninConfig, DDL_IRQ_PRIO_DEFAULT); + + USART_FuncCmd(COM_UART, (USART_TX | USART_RX | USART_INT_RX), ENABLE); + + LL_PERIPH_WP(LL_PERIPH_GPIO | LL_PERIPH_FCG | LL_PERIPH_PWC_CLK_RMU | \ + LL_PERIPH_EFM | LL_PERIPH_SRAM); + +} + +//通信å‘é€æ•°æ® +void hdl_com_uart_send(uint8_t* w_buf, uint16_t len) +{ + uint8_t i; + + for (i = 0; i < len; i++) + { + USART_WriteData(COM_UART, w_buf[i]); + + while (USART_GetStatus(COM_UART, USART_FLAG_TX_CPLT) == RESET); + } +} + +//通信回调函数注册 +void hdl_com_uart_rx_register(com_rx_callback pCBS) +{ + if (com_rx_callback_cbs == 0) + { + com_rx_callback_cbs = pCBS; + } +} + +//通信接收中断 +static void COM_Rx_IrqCallback(void) +{ + uint8_t r_data = 0; + + r_data = USART_ReadData(COM_UART); + + if (com_rx_callback_cbs) + { + com_rx_callback_cbs(r_data); + } +} + +static void COM_RxErr_IrqCallback(void) +{ + (void)USART_ReadData(COM_UART); + + USART_ClearStatus(COM_UART, (USART_FLAG_PARITY_ERR | USART_FLAG_FRAME_ERR | USART_FLAG_OVERRUN)); +} diff --git a/hdl/hdl_usart.h b/hdl/hdl_usart.h new file mode 100644 index 0000000..f3e1a4b --- /dev/null +++ b/hdl/hdl_usart.h @@ -0,0 +1,60 @@ +#ifndef _HDL_USART_H_ +#define _HDL_USART_H_ + +#include "hc32_ll.h" + + +#define DEBUG_UART (CM_USART1) +#define DEBUG_UART_CLK (FCG1_PERIPH_USART1) + +#define DEBUG_UART_RX_PORT (GPIO_PORT_A) /* PA11: USART2_RX */ +#define DEBUG_UART_RX_PIN (GPIO_PIN_11) +#define DEBUG_UART_RX_GPIO_FUNC (GPIO_FUNC_33) + +#define DEBUG_UART_TX_PORT (GPIO_PORT_A) /* PA12: USART2_TX */ +#define DEBUG_UART_TX_PIN (GPIO_PIN_12) +#define DEBUG_UART_TX_GPIO_FUNC (GPIO_FUNC_32) + +#define DEBUG_UART_INT_EI (INT_SRC_USART1_EI) +#define DEBUG_UART_INT_EI_IRQ (INT000_IRQn) +#define DEBUG_UART_INT_RI (INT_SRC_USART1_RI) +#define DEBUG_UART_INT_RI_IRQ (INT001_IRQn) + +typedef void (*hdl_debug_uart_rx_cb_t)(uint8_t data); + + +void hdl_debug_uart_init(void); + +int hdl_debug_uart_getc(int *ch); + +void hdl_debug_uart_putc(uint8_t ch); + +void hdl_debug_uart_rx_reg(hdl_debug_uart_rx_cb_t pCBS); + + +#define COM_UART (CM_USART2) +#define COM_UART_CLK (FCG1_PERIPH_USART2) +#define COM_RX_PORT (GPIO_PORT_A) +#define COM_RX_PIN (GPIO_PIN_10) +#define COM_RX_GPIO_FUNC (GPIO_FUNC_37) + +#define COM_TX_PORT (GPIO_PORT_A) +#define COM_TX_PIN (GPIO_PIN_08) +#define COM_TX_GPIO_FUNC (GPIO_FUNC_36) + +#define COM_INT_EI (INT_SRC_USART2_EI) +#define COM_INT_EI_IRQ (INT011_IRQn) +#define COM_INT_RI (INT_SRC_USART2_RI) +#define COM_INT_RI_IRQ (INT012_IRQn) + + + +typedef void (*com_rx_callback)(uint8_t data); + +void hdl_com_uart_init(void); + +void hdl_com_uart_rx_register(com_rx_callback pCBS); + +void hdl_com_uart_send(uint8_t *w_buf,uint16_t len); + +#endif diff --git a/hdl/hdl_usb.c b/hdl/hdl_usb.c new file mode 100644 index 0000000..c4f7148 --- /dev/null +++ b/hdl/hdl_usb.c @@ -0,0 +1,51 @@ +#include "hdl_usb.h" + +static void USB_IRQ_Handler(void) +{ + extern void USBD_IRQHandler(uint8_t busid); + + USBD_IRQHandler(0); +} + +void hdl_usb_init(void) +{ + stc_clock_pllx_init_t stcUpllInit; + stc_gpio_init_t stcGpioCfg; + stc_irq_signin_config_t stcIrqRegiConf; + + LL_PERIPH_WE(LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_GPIO | LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM); + + /* 时钟é…ç½® */ + (void)CLK_PLLxStructInit(&stcUpllInit); + stcUpllInit.u8PLLState = CLK_PLLX_ON; + stcUpllInit.PLLCFGR = 0UL; + stcUpllInit.PLLCFGR_f.PLLM = (4UL - 1UL); + stcUpllInit.PLLCFGR_f.PLLN = (84UL - 1UL); + stcUpllInit.PLLCFGR_f.PLLR = (7UL - 1UL); + stcUpllInit.PLLCFGR_f.PLLQ = (7UL - 1UL); + stcUpllInit.PLLCFGR_f.PLLP = (7UL - 1UL); //48M + (void)CLK_PLLxInit(&stcUpllInit); + CLK_SetUSBClockSrc(CLK_USBCLK_PLLXP); + + /* 引脚é…ç½® */ + (void)GPIO_StructInit(&stcGpioCfg); + + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USB_DM_PORT, USB_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USB_DP_PORT, USB_DP_PIN, &stcGpioCfg); +// GPIO_SetFunc(USB_DM_PORT, USB_DM_PIN, GPIO_FUNC_10); +// GPIO_SetFunc(USB_DP_PORT, USB_DP_PIN, GPIO_FUNC_10); +// GPIO_SetFunc(USB_VBUS_PORT, USB_VBUS_PIN, GPIO_FUNC_10); /* VBUS */ + FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_USBFS, ENABLE); + + /* 中断é…ç½® */ + stcIrqRegiConf.enIRQn = INT030_IRQn; + stcIrqRegiConf.enIntSrc = INT_SRC_USBFS_GLB; + stcIrqRegiConf.pfnCallback = &USB_IRQ_Handler; // 添加中断函数 + (void)INTC_IrqSignIn(&stcIrqRegiConf); + NVIC_ClearPendingIRQ(stcIrqRegiConf.enIRQn); + NVIC_SetPriority(stcIrqRegiConf.enIRQn, DDL_IRQ_PRIO_15); + NVIC_EnableIRQ(stcIrqRegiConf.enIRQn); + + LL_PERIPH_WP(LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM); +} diff --git a/hdl/hdl_usb.h b/hdl/hdl_usb.h new file mode 100644 index 0000000..bbd0b41 --- /dev/null +++ b/hdl/hdl_usb.h @@ -0,0 +1,18 @@ +#ifndef ____HDL_USB_H_ +#define ____HDL_USB_H_ + +#include "hc32_ll.h" +#include "hdl_clk.h" + +#define USB_DP_PORT (GPIO_PORT_A) +#define USB_DP_PIN (GPIO_PIN_12) +#define USB_DM_PORT (GPIO_PORT_A) +#define USB_DM_PIN (GPIO_PIN_11) +#define USB_VBUS_PORT (GPIO_PORT_A) +#define USB_VBUS_PIN (GPIO_PIN_09) +#define USB_SOF_PORT (GPIO_PORT_A) +#define USB_SOF_PIN (GPIO_PIN_08) + +void hdl_usb_init(void); + +#endif diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Include/hc32f460.h b/mcu/cmsis/Device/HDSC/hc32f4xx/Include/hc32f460.h new file mode 100644 index 0000000..dbfec11 --- /dev/null +++ b/mcu/cmsis/Device/HDSC/hc32f4xx/Include/hc32f460.h @@ -0,0 +1,12466 @@ +/** + ******************************************************************************* + * @file HC32F460.h + * @brief Headerfile for HC32F460 series MCU + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-01-15 CDT Modify headfile based on reference manual Rev1.5 + 2023-09-30 CDT Modify headfile based on reference manual Rev1.6 + Optimze for the unused bit definitions + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + **/ + +#ifndef __HC32F460_H__ +#define __HC32F460_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Configuration of the Cortex-M4 Processor and Core Peripherals + ******************************************************************************/ +#define __MPU_PRESENT 1 /*!< HC32F460 provides MPU */ +#define __VTOR_PRESENT 1 /*!< HC32F460 supported vector table registers */ +#define __NVIC_PRIO_BITS 4 /*!< HC32F460 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/******************************************************************************* + * Interrupt Number Definition + ******************************************************************************/ +typedef enum { + NMI_IRQn = -14, /* Non Maskable */ + HardFault_IRQn = -13, /* Hard Fault */ + MemManageFault_IRQn = -12, /* MemManage Fault */ + BusFault_IRQn = -11, /* Bus Fault */ + UsageFault_IRQn = -10, /* Usage Fault */ + SVC_IRQn = -5, /* SVCall */ + DebugMonitor_IRQn = -4, /* DebugMonitor */ + PendSV_IRQn = -2, /* Pend SV */ + SysTick_IRQn = -1, /* System Tick */ + INT000_IRQn = 0, + INT001_IRQn = 1, + INT002_IRQn = 2, + INT003_IRQn = 3, + INT004_IRQn = 4, + INT005_IRQn = 5, + INT006_IRQn = 6, + INT007_IRQn = 7, + INT008_IRQn = 8, + INT009_IRQn = 9, + INT010_IRQn = 10, + INT011_IRQn = 11, + INT012_IRQn = 12, + INT013_IRQn = 13, + INT014_IRQn = 14, + INT015_IRQn = 15, + INT016_IRQn = 16, + INT017_IRQn = 17, + INT018_IRQn = 18, + INT019_IRQn = 19, + INT020_IRQn = 20, + INT021_IRQn = 21, + INT022_IRQn = 22, + INT023_IRQn = 23, + INT024_IRQn = 24, + INT025_IRQn = 25, + INT026_IRQn = 26, + INT027_IRQn = 27, + INT028_IRQn = 28, + INT029_IRQn = 29, + INT030_IRQn = 30, + INT031_IRQn = 31, + INT032_IRQn = 32, + INT033_IRQn = 33, + INT034_IRQn = 34, + INT035_IRQn = 35, + INT036_IRQn = 36, + INT037_IRQn = 37, + INT038_IRQn = 38, + INT039_IRQn = 39, + INT040_IRQn = 40, + INT041_IRQn = 41, + INT042_IRQn = 42, + INT043_IRQn = 43, + INT044_IRQn = 44, + INT045_IRQn = 45, + INT046_IRQn = 46, + INT047_IRQn = 47, + INT048_IRQn = 48, + INT049_IRQn = 49, + INT050_IRQn = 50, + INT051_IRQn = 51, + INT052_IRQn = 52, + INT053_IRQn = 53, + INT054_IRQn = 54, + INT055_IRQn = 55, + INT056_IRQn = 56, + INT057_IRQn = 57, + INT058_IRQn = 58, + INT059_IRQn = 59, + INT060_IRQn = 60, + INT061_IRQn = 61, + INT062_IRQn = 62, + INT063_IRQn = 63, + INT064_IRQn = 64, + INT065_IRQn = 65, + INT066_IRQn = 66, + INT067_IRQn = 67, + INT068_IRQn = 68, + INT069_IRQn = 69, + INT070_IRQn = 70, + INT071_IRQn = 71, + INT072_IRQn = 72, + INT073_IRQn = 73, + INT074_IRQn = 74, + INT075_IRQn = 75, + INT076_IRQn = 76, + INT077_IRQn = 77, + INT078_IRQn = 78, + INT079_IRQn = 79, + INT080_IRQn = 80, + INT081_IRQn = 81, + INT082_IRQn = 82, + INT083_IRQn = 83, + INT084_IRQn = 84, + INT085_IRQn = 85, + INT086_IRQn = 86, + INT087_IRQn = 87, + INT088_IRQn = 88, + INT089_IRQn = 89, + INT090_IRQn = 90, + INT091_IRQn = 91, + INT092_IRQn = 92, + INT093_IRQn = 93, + INT094_IRQn = 94, + INT095_IRQn = 95, + INT096_IRQn = 96, + INT097_IRQn = 97, + INT098_IRQn = 98, + INT099_IRQn = 99, + INT100_IRQn = 100, + INT101_IRQn = 101, + INT102_IRQn = 102, + INT103_IRQn = 103, + INT104_IRQn = 104, + INT105_IRQn = 105, + INT106_IRQn = 106, + INT107_IRQn = 107, + INT108_IRQn = 108, + INT109_IRQn = 109, + INT110_IRQn = 110, + INT111_IRQn = 111, + INT112_IRQn = 112, + INT113_IRQn = 113, + INT114_IRQn = 114, + INT115_IRQn = 115, + INT116_IRQn = 116, + INT117_IRQn = 117, + INT118_IRQn = 118, + INT119_IRQn = 119, + INT120_IRQn = 120, + INT121_IRQn = 121, + INT122_IRQn = 122, + INT123_IRQn = 123, + INT124_IRQn = 124, + INT125_IRQn = 125, + INT126_IRQn = 126, + INT127_IRQn = 127, + INT128_IRQn = 128, + INT129_IRQn = 129, + INT130_IRQn = 130, + INT131_IRQn = 131, + INT132_IRQn = 132, + INT133_IRQn = 133, + INT134_IRQn = 134, + INT135_IRQn = 135, + INT136_IRQn = 136, + INT137_IRQn = 137, + INT138_IRQn = 138, + INT139_IRQn = 139, + INT140_IRQn = 140, + INT141_IRQn = 141, + INT142_IRQn = 142, + INT143_IRQn = 143, + +} IRQn_Type; + +#include +#include + +/** + ******************************************************************************* + ** \brief Event number enumeration + ******************************************************************************/ +typedef enum { + EVT_SRC_SWI_IRQ0 = 0U, /* SWI_IRQ0 */ + EVT_SRC_SWI_IRQ1 = 1U, /* SWI_IRQ1 */ + EVT_SRC_SWI_IRQ2 = 2U, /* SWI_IRQ2 */ + EVT_SRC_SWI_IRQ3 = 3U, /* SWI_IRQ3 */ + EVT_SRC_SWI_IRQ4 = 4U, /* SWI_IRQ4 */ + EVT_SRC_SWI_IRQ5 = 5U, /* SWI_IRQ5 */ + EVT_SRC_SWI_IRQ6 = 6U, /* SWI_IRQ6 */ + EVT_SRC_SWI_IRQ7 = 7U, /* SWI_IRQ7 */ + EVT_SRC_SWI_IRQ8 = 8U, /* SWI_IRQ8 */ + EVT_SRC_SWI_IRQ9 = 9U, /* SWI_IRQ9 */ + EVT_SRC_SWI_IRQ10 = 10U, /* SWI_IRQ10 */ + EVT_SRC_SWI_IRQ11 = 11U, /* SWI_IRQ11 */ + EVT_SRC_SWI_IRQ12 = 12U, /* SWI_IRQ12 */ + EVT_SRC_SWI_IRQ13 = 13U, /* SWI_IRQ13 */ + EVT_SRC_SWI_IRQ14 = 14U, /* SWI_IRQ14 */ + EVT_SRC_SWI_IRQ15 = 15U, /* SWI_IRQ15 */ + EVT_SRC_SWI_IRQ16 = 16U, /* SWI_IRQ16 */ + EVT_SRC_SWI_IRQ17 = 17U, /* SWI_IRQ17 */ + EVT_SRC_SWI_IRQ18 = 18U, /* SWI_IRQ18 */ + EVT_SRC_SWI_IRQ19 = 19U, /* SWI_IRQ19 */ + EVT_SRC_SWI_IRQ20 = 20U, /* SWI_IRQ20 */ + EVT_SRC_SWI_IRQ21 = 21U, /* SWI_IRQ21 */ + EVT_SRC_SWI_IRQ22 = 22U, /* SWI_IRQ22 */ + EVT_SRC_SWI_IRQ23 = 23U, /* SWI_IRQ23 */ + EVT_SRC_SWI_IRQ24 = 24U, /* SWI_IRQ24 */ + EVT_SRC_SWI_IRQ25 = 25U, /* SWI_IRQ25 */ + EVT_SRC_SWI_IRQ26 = 26U, /* SWI_IRQ26 */ + EVT_SRC_SWI_IRQ27 = 27U, /* SWI_IRQ27 */ + EVT_SRC_SWI_IRQ28 = 28U, /* SWI_IRQ28 */ + EVT_SRC_SWI_IRQ29 = 29U, /* SWI_IRQ29 */ + EVT_SRC_SWI_IRQ30 = 30U, /* SWI_IRQ30 */ + EVT_SRC_SWI_IRQ31 = 31U, /* SWI_IRQ31 */ + + /* External Interrupt. */ + EVT_SRC_PORT_EIRQ0 = 0U, /* PORT_EIRQ0 */ + EVT_SRC_PORT_EIRQ1 = 1U, /* PORT_EIRQ1 */ + EVT_SRC_PORT_EIRQ2 = 2U, /* PORT_EIRQ2 */ + EVT_SRC_PORT_EIRQ3 = 3U, /* PORT_EIRQ3 */ + EVT_SRC_PORT_EIRQ4 = 4U, /* PORT_EIRQ4 */ + EVT_SRC_PORT_EIRQ5 = 5U, /* PORT_EIRQ5 */ + EVT_SRC_PORT_EIRQ6 = 6U, /* PORT_EIRQ6 */ + EVT_SRC_PORT_EIRQ7 = 7U, /* PORT_EIRQ7 */ + EVT_SRC_PORT_EIRQ8 = 8U, /* PORT_EIRQ8 */ + EVT_SRC_PORT_EIRQ9 = 9U, /* PORT_EIRQ9 */ + EVT_SRC_PORT_EIRQ10 = 10U, /* PORT_EIRQ10 */ + EVT_SRC_PORT_EIRQ11 = 11U, /* PORT_EIRQ11 */ + EVT_SRC_PORT_EIRQ12 = 12U, /* PORT_EIRQ12 */ + EVT_SRC_PORT_EIRQ13 = 13U, /* PORT_EIRQ13 */ + EVT_SRC_PORT_EIRQ14 = 14U, /* PORT_EIRQ14 */ + EVT_SRC_PORT_EIRQ15 = 15U, /* PORT_EIRQ15 */ + + /* DMAC */ + EVT_SRC_DMA1_TC0 = 32U, /* DMA1_TC0 */ + EVT_SRC_DMA1_TC1 = 33U, /* DMA1_TC1 */ + EVT_SRC_DMA1_TC2 = 34U, /* DMA1_TC2 */ + EVT_SRC_DMA1_TC3 = 35U, /* DMA1_TC3 */ + EVT_SRC_DMA2_TC0 = 36U, /* DMA2_TC0 */ + EVT_SRC_DMA2_TC1 = 37U, /* DMA2_TC1 */ + EVT_SRC_DMA2_TC2 = 38U, /* DMA2_TC2 */ + EVT_SRC_DMA2_TC3 = 39U, /* DMA2_TC3 */ + EVT_SRC_DMA1_BTC0 = 40U, /* DMA1_BTC0 */ + EVT_SRC_DMA1_BTC1 = 41U, /* DMA1_BTC1 */ + EVT_SRC_DMA1_BTC2 = 42U, /* DMA1_BTC2 */ + EVT_SRC_DMA1_BTC3 = 43U, /* DMA1_BTC3 */ + EVT_SRC_DMA2_BTC0 = 44U, /* DMA2_BTC0 */ + EVT_SRC_DMA2_BTC1 = 45U, /* DMA2_BTC1 */ + EVT_SRC_DMA2_BTC2 = 46U, /* DMA2_BTC2 */ + EVT_SRC_DMA2_BTC3 = 47U, /* DMA2_BTC3 */ + + /* EFM */ + EVT_SRC_EFM_OPTEND = 52U, /* EFM_OPTEND */ + + /* USB SOF */ + EVT_SRC_USBFS_SOF = 53U, /* USBFS_SOF */ + + /* DCU */ + EVT_SRC_DCU1 = 55U, /* DCU1 */ + EVT_SRC_DCU2 = 56U, /* DCU2 */ + EVT_SRC_DCU3 = 57U, /* DCU3 */ + EVT_SRC_DCU4 = 58U, /* DCU4 */ + + /* TIMER 0 */ + EVT_SRC_TMR0_1_CMP_A = 64U, /* TMR01_GCMA */ + EVT_SRC_TMR0_1_CMP_B = 65U, /* TMR01_GCMB */ + EVT_SRC_TMR0_2_CMP_A = 66U, /* TMR02_GCMA */ + EVT_SRC_TMR0_2_CMP_B = 67U, /* TMR02_GCMB */ + + /* RTC */ + EVT_SRC_RTC_ALM = 81U, /* RTC_ALM */ + EVT_SRC_RTC_PRD = 82U, /* RTC_PRD */ + + /* TIMER 6 */ + EVT_SRC_TMR6_1_GCMP_A = 96U, /* TMR61_GCMA */ + EVT_SRC_TMR6_1_GCMP_B = 97U, /* TMR61_GCMB */ + EVT_SRC_TMR6_1_GCMP_C = 98U, /* TMR61_GCMC */ + EVT_SRC_TMR6_1_GCMP_D = 99U, /* TMR61_GCMD */ + EVT_SRC_TMR6_1_GCMP_E = 100U, /* TMR61_GCME */ + EVT_SRC_TMR6_1_GCMP_F = 101U, /* TMR61_GCMF */ + EVT_SRC_TMR6_1_OVF = 102U, /* TMR61_GOVF */ + EVT_SRC_TMR6_1_UDF = 103U, /* TMR61_GUDF */ + EVT_SRC_TMR6_1_SCMP_A = 107U, /* TMR61_SCMA */ + EVT_SRC_TMR6_1_SCMP_B = 108U, /* TMR61_SCMB */ + EVT_SRC_TMR6_2_GCMP_A = 112U, /* TMR62_GCMA */ + EVT_SRC_TMR6_2_GCMP_B = 113U, /* TMR62_GCMB */ + EVT_SRC_TMR6_2_GCMP_C = 114U, /* TMR62_GCMC */ + EVT_SRC_TMR6_2_GCMP_D = 115U, /* TMR62_GCMD */ + EVT_SRC_TMR6_2_GCMP_E = 116U, /* TMR62_GCME */ + EVT_SRC_TMR6_2_GCMP_F = 117U, /* TMR62_GCMF */ + EVT_SRC_TMR6_2_OVF = 118U, /* TMR62_GOVF */ + EVT_SRC_TMR6_2_UDF = 119U, /* TMR62_GUDF */ + EVT_SRC_TMR6_2_SCMP_A = 123U, /* TMR62_SCMA */ + EVT_SRC_TMR6_2_SCMP_B = 124U, /* TMR62_SCMB */ + EVT_SRC_TMR6_3_GCMP_A = 128U, /* TMR63_GCMA */ + EVT_SRC_TMR6_3_GCMP_B = 129U, /* TMR63_GCMB */ + EVT_SRC_TMR6_3_GCMP_C = 130U, /* TMR63_GCMC */ + EVT_SRC_TMR6_3_GCMP_D = 131U, /* TMR63_GCMD */ + EVT_SRC_TMR6_3_GCMP_E = 132U, /* TMR63_GCME */ + EVT_SRC_TMR6_3_GCMP_F = 133U, /* TMR63_GCMF */ + EVT_SRC_TMR6_3_OVF = 134U, /* TMR63_GOVF */ + EVT_SRC_TMR6_3_UDF = 135U, /* TMR63_GUDF */ + EVT_SRC_TMR6_3_SCMP_A = 139U, /* TMR63_SCMA */ + EVT_SRC_TMR6_3_SCMP_B = 140U, /* TMR63_SCMB */ + + /* TIMER A */ + EVT_SRC_TMRA_1_OVF = 256U, /* TMRA1_OVF */ + EVT_SRC_TMRA_1_UDF = 257U, /* TMRA1_UDF */ + EVT_SRC_TMRA_1_CMP = 258U, /* TMRA1_CMP */ + EVT_SRC_TMRA_2_OVF = 259U, /* TMRA2_OVF */ + EVT_SRC_TMRA_2_UDF = 260U, /* TMRA2_UDF */ + EVT_SRC_TMRA_2_CMP = 261U, /* TMRA2_CMP */ + EVT_SRC_TMRA_3_OVF = 262U, /* TMRA3_OVF */ + EVT_SRC_TMRA_3_UDF = 263U, /* TMRA3_UDF */ + EVT_SRC_TMRA_3_CMP = 264U, /* TMRA3_CMP */ + EVT_SRC_TMRA_4_OVF = 265U, /* TMRA4_OVF */ + EVT_SRC_TMRA_4_UDF = 266U, /* TMRA4_UDF */ + EVT_SRC_TMRA_4_CMP = 267U, /* TMRA4_CMP */ + EVT_SRC_TMRA_5_OVF = 268U, /* TMRA5_OVF */ + EVT_SRC_TMRA_5_UDF = 269U, /* TMRA5_UDF */ + EVT_SRC_TMRA_5_CMP = 270U, /* TMRA5_CMP */ + EVT_SRC_TMRA_6_OVF = 272U, /* TMRA6_OVF */ + EVT_SRC_TMRA_6_UDF = 273U, /* TMRA6_UDF */ + EVT_SRC_TMRA_6_CMP = 274U, /* TMRA6_CMP */ + + /* USART */ + EVT_SRC_USART1_EI = 278U, /* USART1_EI */ + EVT_SRC_USART1_RI = 279U, /* USART1_RI */ + EVT_SRC_USART1_TI = 280U, /* USART1_TI */ + EVT_SRC_USART1_TCI = 281U, /* USART1_TCI */ + EVT_SRC_USART1_RTO = 282U, /* USART1_RTO */ + EVT_SRC_USART2_EI = 283U, /* USART2_EI */ + EVT_SRC_USART2_RI = 284U, /* USART2_RI */ + EVT_SRC_USART2_TI = 285U, /* USART2_TI */ + EVT_SRC_USART2_TCI = 286U, /* USART2_TCI */ + EVT_SRC_USART2_RTO = 287U, /* USART2_RTO */ + EVT_SRC_USART3_EI = 288U, /* USART3_EI */ + EVT_SRC_USART3_RI = 289U, /* USART3_RI */ + EVT_SRC_USART3_TI = 290U, /* USART3_TI */ + EVT_SRC_USART3_TCI = 291U, /* USART3_TCI */ + EVT_SRC_USART3_RTO = 292U, /* USART3_RTO */ + EVT_SRC_USART4_EI = 293U, /* USART4_EI */ + EVT_SRC_USART4_RI = 294U, /* USART4_RI */ + EVT_SRC_USART4_TI = 295U, /* USART4_TI */ + EVT_SRC_USART4_TCI = 296U, /* USART4_TCI */ + EVT_SRC_USART4_RTO = 297U, /* USART4_RTO */ + + /* SPI */ + EVT_SRC_SPI1_SPRI = 299U, /* SPI1_SPRI */ + EVT_SRC_SPI1_SPTI = 300U, /* SPI1_SPTI */ + EVT_SRC_SPI1_SPII = 301U, /* SPI1_SPII */ + EVT_SRC_SPI1_SPEI = 302U, /* SPI1_SPEI */ + EVT_SRC_SPI1_SPTEND = 303U, /* SPI1_SPTEND */ + EVT_SRC_SPI2_SPRI = 304U, /* SPI2_SPRI */ + EVT_SRC_SPI2_SPTI = 305U, /* SPI2_SPTI */ + EVT_SRC_SPI2_SPII = 306U, /* SPI2_SPII */ + EVT_SRC_SPI2_SPEI = 307U, /* SPI2_SPEI */ + EVT_SRC_SPI2_SPTEND = 308U, /* SPI2_SPTEND */ + EVT_SRC_SPI3_SPRI = 309U, /* SPI3_SPRI */ + EVT_SRC_SPI3_SPTI = 310U, /* SPI3_SPTI */ + EVT_SRC_SPI3_SPII = 311U, /* SPI3_SPII */ + EVT_SRC_SPI3_SPEI = 312U, /* SPI3_SPEI */ + EVT_SRC_SPI3_SPTEND = 313U, /* SPI3_SPTEND */ + EVT_SRC_SPI4_SPRI = 314U, /* SPI4_SPRI */ + EVT_SRC_SPI4_SPTI = 315U, /* SPI4_SPTI */ + EVT_SRC_SPI4_SPII = 316U, /* SPI4_SPII */ + EVT_SRC_SPI4_SPEI = 317U, /* SPI4_SPEI */ + EVT_SRC_SPI4_SPTEND = 318U, /* SPI4_SPTEND */ + + /* AOS */ + EVT_SRC_AOS_STRG = 319U, /* AOS_STRG */ + + /* TIMER 4 */ + EVT_SRC_TMR4_1_SCMP0 = 368U, /* TMR41_SCM0 */ + EVT_SRC_TMR4_1_SCMP1 = 369U, /* TMR41_SCM1 */ + EVT_SRC_TMR4_1_SCMP2 = 370U, /* TMR41_SCM2 */ + EVT_SRC_TMR4_1_SCMP3 = 371U, /* TMR41_SCM3 */ + EVT_SRC_TMR4_1_SCMP4 = 372U, /* TMR41_SCM4 */ + EVT_SRC_TMR4_1_SCMP5 = 373U, /* TMR41_SCM5 */ + EVT_SRC_TMR4_2_SCMP0 = 374U, /* TMR42_SCM0 */ + EVT_SRC_TMR4_2_SCMP1 = 375U, /* TMR42_SCM1 */ + EVT_SRC_TMR4_2_SCMP2 = 376U, /* TMR42_SCM2 */ + EVT_SRC_TMR4_2_SCMP3 = 377U, /* TMR42_SCM3 */ + EVT_SRC_TMR4_2_SCMP4 = 378U, /* TMR42_SCM4 */ + EVT_SRC_TMR4_2_SCMP5 = 379U, /* TMR42_SCM5 */ + EVT_SRC_TMR4_3_SCMP0 = 384U, /* TMR43_SCM0 */ + EVT_SRC_TMR4_3_SCMP1 = 385U, /* TMR43_SCM1 */ + EVT_SRC_TMR4_3_SCMP2 = 386U, /* TMR43_SCM2 */ + EVT_SRC_TMR4_3_SCMP3 = 387U, /* TMR43_SCM3 */ + EVT_SRC_TMR4_3_SCMP4 = 388U, /* TMR43_SCM4 */ + EVT_SRC_TMR4_3_SCMP5 = 389U, /* TMR43_SCM5 */ + + /* EVENT PORT */ + EVT_SRC_EVENT_PORT1 = 394U, /* EVENT_PORT1 */ + EVT_SRC_EVENT_PORT2 = 395U, /* EVENT_PORT2 */ + EVT_SRC_EVENT_PORT3 = 396U, /* EVENT_PORT3 */ + EVT_SRC_EVENT_PORT4 = 397U, /* EVENT_PORT4 */ + + /* I2S */ + EVT_SRC_I2S1_TXIRQOUT = 400U, /* I2S1_TXIRQOUT */ + EVT_SRC_I2S1_RXIRQOUT = 401U, /* I2S1_RXIRQOUT */ + EVT_SRC_I2S2_TXIRQOUT = 403U, /* I2S2_TXIRQOUT */ + EVT_SRC_I2S2_RXIRQOUT = 404U, /* I2S2_RXIRQOUT */ + EVT_SRC_I2S3_TXIRQOUT = 406U, /* I2S3_TXIRQOUT */ + EVT_SRC_I2S3_RXIRQOUT = 407U, /* I2S3_RXIRQOUT */ + EVT_SRC_I2S4_TXIRQOUT = 409U, /* I2S4_TXIRQOUT */ + EVT_SRC_I2S4_RXIRQOUT = 410U, /* I2S4_RXIRQOUT */ + + /* COMPARATOR */ + EVT_SRC_CMP1 = 416U, /* ACMP1 */ + EVT_SRC_CMP2 = 417U, /* ACMP1 */ + EVT_SRC_CMP3 = 418U, /* ACMP1 */ + + /* I2C */ + EVT_SRC_I2C1_RXI = 420U, /* I2C1_RXI */ + EVT_SRC_I2C1_TXI = 421U, /* I2C1_TXI */ + EVT_SRC_I2C1_TEI = 422U, /* I2C1_TEI */ + EVT_SRC_I2C1_EEI = 423U, /* I2C1_EEI */ + EVT_SRC_I2C2_RXI = 424U, /* I2C2_RXI */ + EVT_SRC_I2C2_TXI = 425U, /* I2C2_TXI */ + EVT_SRC_I2C2_TEI = 426U, /* I2C2_TEI */ + EVT_SRC_I2C2_EEI = 427U, /* I2C2_EEI */ + EVT_SRC_I2C3_RXI = 428U, /* I2C3_RXI */ + EVT_SRC_I2C3_TXI = 429U, /* I2C3_TXI */ + EVT_SRC_I2C3_TEI = 430U, /* I2C3_TEI */ + EVT_SRC_I2C3_EEI = 431U, /* I2C3_EEI */ + + /* LVD */ + EVT_SRC_LVD1 = 433U, /* LVD1 */ + EVT_SRC_LVD2 = 434U, /* LVD2 */ + + /* OTS */ + EVT_SRC_OTS = 435U, /* OTS */ + + /* WDT */ + EVT_SRC_WDT_REFUDF = 439U, /* WDT_REFUDF */ + + /* ADC */ + EVT_SRC_ADC1_EOCA = 448U, /* ADC1_EOCA */ + EVT_SRC_ADC1_EOCB = 449U, /* ADC1_EOCB */ + EVT_SRC_ADC1_CHCMP = 450U, /* ADC1_CHCMP */ + EVT_SRC_ADC1_SEQCMP = 451U, /* ADC1_SEQCMP */ + EVT_SRC_ADC2_EOCA = 452U, /* ADC2_EOCA */ + EVT_SRC_ADC2_EOCB = 453U, /* ADC2_EOCB */ + EVT_SRC_ADC2_CHCMP = 454U, /* ADC2_CHCMP */ + EVT_SRC_ADC2_SEQCMP = 455U, /* ADC2_SEQCMP */ + + /* TRNG */ + EVT_SRC_TRNG_END = 456U, /* TRNG_END */ + + /* SDIO */ + EVT_SRC_SDIOC1_DMAR = 480U, /* SDIOC1_DMAR */ + EVT_SRC_SDIOC1_DMAW = 481U, /* SDIOC1_DMAW */ + EVT_SRC_SDIOC2_DMAR = 483U, /* SDIOC2_DMAR */ + EVT_SRC_SDIOC2_DMAW = 484U, /* SDIOC2_DMAW */ + EVT_SRC_MAX = 511U, +} en_event_src_t; + +/** + ******************************************************************************* + ** \brief Interrupt number enumeration + ******************************************************************************/ +typedef enum { + INT_SRC_SWI_IRQ0 = 0U, /* SWI_IRQ0 */ + INT_SRC_SWI_IRQ1 = 1U, /* SWI_IRQ1 */ + INT_SRC_SWI_IRQ2 = 2U, /* SWI_IRQ2 */ + INT_SRC_SWI_IRQ3 = 3U, /* SWI_IRQ3 */ + INT_SRC_SWI_IRQ4 = 4U, /* SWI_IRQ4 */ + INT_SRC_SWI_IRQ5 = 5U, /* SWI_IRQ5 */ + INT_SRC_SWI_IRQ6 = 6U, /* SWI_IRQ6 */ + INT_SRC_SWI_IRQ7 = 7U, /* SWI_IRQ7 */ + INT_SRC_SWI_IRQ8 = 8U, /* SWI_IRQ8 */ + INT_SRC_SWI_IRQ9 = 9U, /* SWI_IRQ9 */ + INT_SRC_SWI_IRQ10 = 10U, /* SWI_IRQ10 */ + INT_SRC_SWI_IRQ11 = 11U, /* SWI_IRQ11 */ + INT_SRC_SWI_IRQ12 = 12U, /* SWI_IRQ12 */ + INT_SRC_SWI_IRQ13 = 13U, /* SWI_IRQ13 */ + INT_SRC_SWI_IRQ14 = 14U, /* SWI_IRQ14 */ + INT_SRC_SWI_IRQ15 = 15U, /* SWI_IRQ15 */ + INT_SRC_SWI_IRQ16 = 16U, /* SWI_IRQ16 */ + INT_SRC_SWI_IRQ17 = 17U, /* SWI_IRQ17 */ + INT_SRC_SWI_IRQ18 = 18U, /* SWI_IRQ18 */ + INT_SRC_SWI_IRQ19 = 19U, /* SWI_IRQ19 */ + INT_SRC_SWI_IRQ20 = 20U, /* SWI_IRQ20 */ + INT_SRC_SWI_IRQ21 = 21U, /* SWI_IRQ21 */ + INT_SRC_SWI_IRQ22 = 22U, /* SWI_IRQ22 */ + INT_SRC_SWI_IRQ23 = 23U, /* SWI_IRQ23 */ + INT_SRC_SWI_IRQ24 = 24U, /* SWI_IRQ24 */ + INT_SRC_SWI_IRQ25 = 25U, /* SWI_IRQ25 */ + INT_SRC_SWI_IRQ26 = 26U, /* SWI_IRQ26 */ + INT_SRC_SWI_IRQ27 = 27U, /* SWI_IRQ27 */ + INT_SRC_SWI_IRQ28 = 28U, /* SWI_IRQ28 */ + INT_SRC_SWI_IRQ29 = 29U, /* SWI_IRQ29 */ + INT_SRC_SWI_IRQ30 = 30U, /* SWI_IRQ30 */ + INT_SRC_SWI_IRQ31 = 31U, /* SWI_IRQ31 */ + + /* External Interrupt. */ + INT_SRC_PORT_EIRQ0 = 0U, /* PORT_EIRQ0 */ + INT_SRC_PORT_EIRQ1 = 1U, /* PORT_EIRQ1 */ + INT_SRC_PORT_EIRQ2 = 2U, /* PORT_EIRQ2 */ + INT_SRC_PORT_EIRQ3 = 3U, /* PORT_EIRQ3 */ + INT_SRC_PORT_EIRQ4 = 4U, /* PORT_EIRQ4 */ + INT_SRC_PORT_EIRQ5 = 5U, /* PORT_EIRQ5 */ + INT_SRC_PORT_EIRQ6 = 6U, /* PORT_EIRQ6 */ + INT_SRC_PORT_EIRQ7 = 7U, /* PORT_EIRQ7 */ + INT_SRC_PORT_EIRQ8 = 8U, /* PORT_EIRQ8 */ + INT_SRC_PORT_EIRQ9 = 9U, /* PORT_EIRQ9 */ + INT_SRC_PORT_EIRQ10 = 10U, /* PORT_EIRQ10 */ + INT_SRC_PORT_EIRQ11 = 11U, /* PORT_EIRQ11 */ + INT_SRC_PORT_EIRQ12 = 12U, /* PORT_EIRQ12 */ + INT_SRC_PORT_EIRQ13 = 13U, /* PORT_EIRQ13 */ + INT_SRC_PORT_EIRQ14 = 14U, /* PORT_EIRQ14 */ + INT_SRC_PORT_EIRQ15 = 15U, /* PORT_EIRQ15 */ + + /* DMAC */ + INT_SRC_DMA1_TC0 = 32U, /* DMA1_TC0 */ + INT_SRC_DMA1_TC1 = 33U, /* DMA1_TC1 */ + INT_SRC_DMA1_TC2 = 34U, /* DMA1_TC2 */ + INT_SRC_DMA1_TC3 = 35U, /* DMA1_TC3 */ + INT_SRC_DMA2_TC0 = 36U, /* DMA2_TC0 */ + INT_SRC_DMA2_TC1 = 37U, /* DMA2_TC1 */ + INT_SRC_DMA2_TC2 = 38U, /* DMA2_TC2 */ + INT_SRC_DMA2_TC3 = 39U, /* DMA2_TC3 */ + INT_SRC_DMA1_BTC0 = 40U, /* DMA1_BTC0 */ + INT_SRC_DMA1_BTC1 = 41U, /* DMA1_BTC1 */ + INT_SRC_DMA1_BTC2 = 42U, /* DMA1_BTC2 */ + INT_SRC_DMA1_BTC3 = 43U, /* DMA1_BTC3 */ + INT_SRC_DMA2_BTC0 = 44U, /* DMA2_BTC0 */ + INT_SRC_DMA2_BTC1 = 45U, /* DMA2_BTC1 */ + INT_SRC_DMA2_BTC2 = 46U, /* DMA2_BTC2 */ + INT_SRC_DMA2_BTC3 = 47U, /* DMA2_BTC3 */ + INT_SRC_DMA1_ERR = 48U, /* DMA1_ERR */ + INT_SRC_DMA2_ERR = 49U, /* DMA2_ERR */ + + /* EFM */ + INT_SRC_EFM_PEERR = 50U, /* EFM_PEERR */ + INT_SRC_EFM_COLERR = 51U, /* EFM_COLERR */ + INT_SRC_EFM_OPTEND = 52U, /* EFM_OPTEND */ + + /* QSPI */ + INT_SRC_QSPI_INTR = 54U, /* QSPI_INTR */ + + /* DCU */ + INT_SRC_DCU1 = 55U, /* DCU1 */ + INT_SRC_DCU2 = 56U, /* DCU2 */ + INT_SRC_DCU3 = 57U, /* DCU3 */ + INT_SRC_DCU4 = 58U, /* DCU4 */ + + /* TIMER 0 */ + INT_SRC_TMR0_1_CMP_A = 64U, /* TMR01_GCMA */ + INT_SRC_TMR0_1_CMP_B = 65U, /* TMR01_GCMB */ + INT_SRC_TMR0_2_CMP_A = 66U, /* TMR02_GCMA */ + INT_SRC_TMR0_2_CMP_B = 67U, /* TMR02_GCMB */ + + /* RTC */ + INT_SRC_RTC_ALM = 81U, /* RTC_ALM */ + INT_SRC_RTC_PRD = 82U, /* RTC_PRD */ + + /* XTAL32 stop */ + INT_SRC_XTAL32_STOP = 84U, /* XTAL32_STOP */ + + /* XTAL stop */ + INT_SRC_XTAL_STOP = 85U, /* XTAL_STOP */ + + /* wake-up timer */ + INT_SRC_WKTM_PRD = 86U, /* WKTM_PRD */ + + /* SWDT */ + INT_SRC_SWDT_REFUDF = 87U, /* SWDT_REFUDF */ + + /* TIMER 6 */ + INT_SRC_TMR6_1_GCMP_A = 96U, /* TMR61_GCMA */ + INT_SRC_TMR6_1_GCMP_B = 97U, /* TMR61_GCMB */ + INT_SRC_TMR6_1_GCMP_C = 98U, /* TMR61_GCMC */ + INT_SRC_TMR6_1_GCMP_D = 99U, /* TMR61_GCMD */ + INT_SRC_TMR6_1_GCMP_E = 100U, /* TMR61_GCME */ + INT_SRC_TMR6_1_GCMP_F = 101U, /* TMR61_GCMF */ + INT_SRC_TMR6_1_OVF = 102U, /* TMR61_GOVF */ + INT_SRC_TMR6_1_UDF = 103U, /* TMR61_GUDF */ + INT_SRC_TMR6_1_DTE = 104U, /* TMR61_GDTE */ + INT_SRC_TMR6_1_SCMP_A = 107U, /* TMR61_SCMA */ + INT_SRC_TMR6_1_SCMP_B = 108U, /* TMR61_SCMB */ + INT_SRC_TMR6_2_GCMP_A = 112U, /* TMR62_GCMA */ + INT_SRC_TMR6_2_GCMP_B = 113U, /* TMR62_GCMB */ + INT_SRC_TMR6_2_GCMP_C = 114U, /* TMR62_GCMC */ + INT_SRC_TMR6_2_GCMP_D = 115U, /* TMR62_GCMD */ + INT_SRC_TMR6_2_GCMP_E = 116U, /* TMR62_GCME */ + INT_SRC_TMR6_2_GCMP_F = 117U, /* TMR62_GCMF */ + INT_SRC_TMR6_2_OVF = 118U, /* TMR62_GOVF */ + INT_SRC_TMR6_2_UDF = 119U, /* TMR62_GUDF */ + INT_SRC_TMR6_2_DTE = 120U, /* TMR62_GDTE */ + INT_SRC_TMR6_2_SCMP_A = 123U, /* TMR62_SCMA */ + INT_SRC_TMR6_2_SCMP_B = 124U, /* TMR62_SCMB */ + INT_SRC_TMR6_3_GCMP_A = 128U, /* TMR63_GCMA */ + INT_SRC_TMR6_3_GCMP_B = 129U, /* TMR63_GCMB */ + INT_SRC_TMR6_3_GCMP_C = 130U, /* TMR63_GCMC */ + INT_SRC_TMR6_3_GCMP_D = 131U, /* TMR63_GCMD */ + INT_SRC_TMR6_3_GCMP_E = 132U, /* TMR63_GCME */ + INT_SRC_TMR6_3_GCMP_F = 133U, /* TMR63_GCMF */ + INT_SRC_TMR6_3_OVF = 134U, /* TMR63_GOVF */ + INT_SRC_TMR6_3_UDF = 135U, /* TMR63_GUDF */ + INT_SRC_TMR6_3_DTE = 136U, /* TMR63_GDTE */ + INT_SRC_TMR6_3_SCMP_A = 139U, /* TMR63_SCMA */ + INT_SRC_TMR6_3_SCMP_B = 140U, /* TMR63_SCMB */ + + /* TIMER A */ + INT_SRC_TMRA_1_OVF = 256U, /* TMRA1_OVF */ + INT_SRC_TMRA_1_UDF = 257U, /* TMRA1_UDF */ + INT_SRC_TMRA_1_CMP = 258U, /* TMRA1_CMP */ + INT_SRC_TMRA_2_OVF = 259U, /* TMRA2_OVF */ + INT_SRC_TMRA_2_UDF = 260U, /* TMRA2_UDF */ + INT_SRC_TMRA_2_CMP = 261U, /* TMRA2_CMP */ + INT_SRC_TMRA_3_OVF = 262U, /* TMRA3_OVF */ + INT_SRC_TMRA_3_UDF = 263U, /* TMRA3_UDF */ + INT_SRC_TMRA_3_CMP = 264U, /* TMRA3_CMP */ + INT_SRC_TMRA_4_OVF = 265U, /* TMRA4_OVF */ + INT_SRC_TMRA_4_UDF = 266U, /* TMRA4_UDF */ + INT_SRC_TMRA_4_CMP = 267U, /* TMRA4_CMP */ + INT_SRC_TMRA_5_OVF = 268U, /* TMRA5_OVF */ + INT_SRC_TMRA_5_UDF = 269U, /* TMRA5_UDF */ + INT_SRC_TMRA_5_CMP = 270U, /* TMRA5_CMP */ + INT_SRC_TMRA_6_OVF = 272U, /* TMRA6_OVF */ + INT_SRC_TMRA_6_UDF = 273U, /* TMRA6_UDF */ + INT_SRC_TMRA_6_CMP = 274U, /* TMRA6_CMP */ + + /* USB FS */ + INT_SRC_USBFS_GLB = 275U, /* USBFS_GLB */ + + /* USRAT */ + INT_SRC_USART1_EI = 278U, /* USART1_EI */ + INT_SRC_USART1_RI = 279U, /* USART1_RI */ + INT_SRC_USART1_TI = 280U, /* USART1_TI */ + INT_SRC_USART1_TCI = 281U, /* USART1_TCI */ + INT_SRC_USART1_RTO = 282U, /* USART1_RTO */ + INT_SRC_USART1_WUPI = 432U, /* USART1_WUPI */ + INT_SRC_USART2_EI = 283U, /* USART2_EI */ + INT_SRC_USART2_RI = 284U, /* USART2_RI */ + INT_SRC_USART2_TI = 285U, /* USART2_TI */ + INT_SRC_USART2_TCI = 286U, /* USART2_TCI */ + INT_SRC_USART2_RTO = 287U, /* USART2_RTO */ + INT_SRC_USART3_EI = 288U, /* USART3_EI */ + INT_SRC_USART3_RI = 289U, /* USART3_RI */ + INT_SRC_USART3_TI = 290U, /* USART3_TI */ + INT_SRC_USART3_TCI = 291U, /* USART3_TCI */ + INT_SRC_USART3_RTO = 292U, /* USART3_RTO */ + INT_SRC_USART4_EI = 293U, /* USART4_EI */ + INT_SRC_USART4_RI = 294U, /* USART4_RI */ + INT_SRC_USART4_TI = 295U, /* USART4_TI */ + INT_SRC_USART4_TCI = 296U, /* USART4_TCI */ + INT_SRC_USART4_RTO = 297U, /* USART4_RTO */ + + /* SPI */ + INT_SRC_SPI1_SPRI = 299U, /* SPI1_SPRI */ + INT_SRC_SPI1_SPTI = 300U, /* SPI1_SPTI */ + INT_SRC_SPI1_SPII = 301U, /* SPI1_SPII */ + INT_SRC_SPI1_SPEI = 302U, /* SPI1_SPEI */ + INT_SRC_SPI2_SPRI = 304U, /* SPI2_SPRI */ + INT_SRC_SPI2_SPTI = 305U, /* SPI2_SPTI */ + INT_SRC_SPI2_SPII = 306U, /* SPI2_SPII */ + INT_SRC_SPI2_SPEI = 307U, /* SPI2_SPEI */ + INT_SRC_SPI3_SPRI = 309U, /* SPI3_SPRI */ + INT_SRC_SPI3_SPTI = 310U, /* SPI3_SPTI */ + INT_SRC_SPI3_SPII = 311U, /* SPI3_SPII */ + INT_SRC_SPI3_SPEI = 312U, /* SPI3_SPEI */ + INT_SRC_SPI4_SPRI = 314U, /* SPI4_SPRI */ + INT_SRC_SPI4_SPTI = 315U, /* SPI4_SPTI */ + INT_SRC_SPI4_SPII = 316U, /* SPI4_SPII */ + INT_SRC_SPI4_SPEI = 317U, /* SPI4_SPEI */ + + /* TIMER 4 */ + INT_SRC_TMR4_1_GCMP_UH = 320U, /* TMR41_GCMUH */ + INT_SRC_TMR4_1_GCMP_UL = 321U, /* TMR41_GCMUL */ + INT_SRC_TMR4_1_GCMP_VH = 322U, /* TMR41_GCMVH */ + INT_SRC_TMR4_1_GCMP_VL = 323U, /* TMR41_GCMVL */ + INT_SRC_TMR4_1_GCMP_WH = 324U, /* TMR41_GCMWH */ + INT_SRC_TMR4_1_GCMP_WL = 325U, /* TMR41_GCMWL */ + INT_SRC_TMR4_1_OVF = 326U, /* TMR41_GOVF */ + INT_SRC_TMR4_1_UDF = 327U, /* TMR41_GUDF */ + INT_SRC_TMR4_1_RELOAD_U = 328U, /* TMR41_RLOU */ + INT_SRC_TMR4_1_RELOAD_V = 329U, /* TMR41_RLOV */ + INT_SRC_TMR4_1_RELOAD_W = 330U, /* TMR41_RLOW */ + INT_SRC_TMR4_2_GCMP_UH = 336U, /* TMR42_GCMUH */ + INT_SRC_TMR4_2_GCMP_UL = 337U, /* TMR42_GCMUL */ + INT_SRC_TMR4_2_GCMP_VH = 338U, /* TMR42_GCMVH */ + INT_SRC_TMR4_2_GCMP_VL = 339U, /* TMR42_GCMVL */ + INT_SRC_TMR4_2_GCMP_WH = 340U, /* TMR42_GCMWH */ + INT_SRC_TMR4_2_GCMP_WL = 341U, /* TMR42_GCMWL */ + INT_SRC_TMR4_2_OVF = 342U, /* TMR42_GOVF */ + INT_SRC_TMR4_2_UDF = 343U, /* TMR42_GUDF */ + INT_SRC_TMR4_2_RELOAD_U = 344U, /* TMR42_RLOU */ + INT_SRC_TMR4_2_RELOAD_V = 345U, /* TMR42_RLOV */ + INT_SRC_TMR4_2_RELOAD_W = 346U, /* TMR42_RLOW */ + INT_SRC_TMR4_3_GCMP_UH = 352U, /* TMR43_GCMUH */ + INT_SRC_TMR4_3_GCMP_UL = 353U, /* TMR43_GCMUL */ + INT_SRC_TMR4_3_GCMP_VH = 354U, /* TMR43_GCMVH */ + INT_SRC_TMR4_3_GCMP_VL = 355U, /* TMR43_GCMVL */ + INT_SRC_TMR4_3_GCMP_WH = 356U, /* TMR43_GCMWH */ + INT_SRC_TMR4_3_GCMP_WL = 357U, /* TMR43_GCMWL */ + INT_SRC_TMR4_3_OVF = 358U, /* TMR43_GOVF */ + INT_SRC_TMR4_3_UDF = 359U, /* TMR43_GUDF */ + INT_SRC_TMR4_3_RELOAD_U = 360U, /* TMR43_RLOU */ + INT_SRC_TMR4_3_RELOAD_V = 361U, /* TMR43_RLOV */ + INT_SRC_TMR4_3_RELOAD_W = 362U, /* TMR43_RLOW */ + + /* EMB */ + INT_SRC_EMB_GR0 = 390U, /* EMB_GR0 */ + INT_SRC_EMB_GR1 = 391U, /* EMB_GR1 */ + INT_SRC_EMB_GR2 = 392U, /* EMB_GR2 */ + INT_SRC_EMB_GR3 = 393U, /* EMB_GR3 */ + + /* EVENT PORT */ + INT_SRC_EVENT_PORT1 = 394U, /* EVENT_PORT1 */ + INT_SRC_EVENT_PORT2 = 395U, /* EVENT_PORT2 */ + INT_SRC_EVENT_PORT3 = 396U, /* EVENT_PORT3 */ + INT_SRC_EVENT_PORT4 = 397U, /* EVENT_PORT4 */ + + /* I2S */ + INT_SRC_I2S1_TXIRQOUT = 400U, /* I2S1_TXIRQOUT */ + INT_SRC_I2S1_RXIRQOUT = 401U, /* I2S1_RXIRQOUT */ + INT_SRC_I2S1_ERRIRQOUT = 402U, /* I2S1_ERRIRQOUT */ + INT_SRC_I2S2_TXIRQOUT = 403U, /* I2S2_TXIRQOUT */ + INT_SRC_I2S2_RXIRQOUT = 404U, /* I2S2_RXIRQOUT */ + INT_SRC_I2S2_ERRIRQOUT = 405U, /* I2S2_ERRIRQOUT */ + INT_SRC_I2S3_TXIRQOUT = 406U, /* I2S3_TXIRQOUT */ + INT_SRC_I2S3_RXIRQOUT = 407U, /* I2S3_RXIRQOUT */ + INT_SRC_I2S3_ERRIRQOUT = 408U, /* I2S3_ERRIRQOUT */ + INT_SRC_I2S4_TXIRQOUT = 409U, /* I2S4_TXIRQOUT */ + INT_SRC_I2S4_RXIRQOUT = 410U, /* I2S4_RXIRQOUT */ + INT_SRC_I2S4_ERRIRQOUT = 411U, /* I2S4_ERRIRQOUT */ + + /* COMPARATOR */ + INT_SRC_CMP1 = 416U, /* ACMP1 */ + INT_SRC_CMP2 = 417U, /* ACMP2 */ + INT_SRC_CMP3 = 418U, /* ACMP3 */ + + /* I2C */ + INT_SRC_I2C1_RXI = 420U, /* I2C1_RXI */ + INT_SRC_I2C1_TXI = 421U, /* I2C1_TXI */ + INT_SRC_I2C1_TEI = 422U, /* I2C1_TEI */ + INT_SRC_I2C1_EEI = 423U, /* I2C1_EEI */ + INT_SRC_I2C2_RXI = 424U, /* I2C2_RXI */ + INT_SRC_I2C2_TXI = 425U, /* I2C2_TXI */ + INT_SRC_I2C2_TEI = 426U, /* I2C2_TEI */ + INT_SRC_I2C2_EEI = 427U, /* I2C2_EEI */ + INT_SRC_I2C3_RXI = 428U, /* I2C3_RXI */ + INT_SRC_I2C3_TXI = 429U, /* I2C3_TXI */ + INT_SRC_I2C3_TEI = 430U, /* I2C3_TEI */ + INT_SRC_I2C3_EEI = 431U, /* I2C3_EEI */ + + /* LVD */ + INT_SRC_LVD1 = 433U, /* LVD1 */ + INT_SRC_LVD2 = 434U, /* LVD2 */ + + /* Temp. sensor */ + INT_SRC_OTS = 435U, /* OTS */ + + /* FCM */ + INT_SRC_FCMFERRI = 436U, /* FCMFERRI */ + INT_SRC_FCMMENDI = 437U, /* FCMMENDI */ + INT_SRC_FCMCOVFI = 438U, /* FCMCOVFI */ + + /* WDT */ + INT_SRC_WDT_REFUDF = 439U, /* WDT_REFUDF */ + + /* ADC */ + INT_SRC_ADC1_EOCA = 448U, /* ADC1_EOCA */ + INT_SRC_ADC1_EOCB = 449U, /* ADC1_EOCB */ + INT_SRC_ADC1_CHCMP = 450U, /* ADC1_CHCMP */ + INT_SRC_ADC1_SEQCMP = 451U, /* ADC1_SEQCMP */ + INT_SRC_ADC2_EOCA = 452U, /* ADC2_EOCA */ + INT_SRC_ADC2_EOCB = 453U, /* ADC2_EOCB */ + INT_SRC_ADC2_CHCMP = 454U, /* ADC2_CHCMP */ + INT_SRC_ADC2_SEQCMP = 455U, /* ADC2_SEQCMP */ + + /* TRNG */ + INT_SRC_TRNG_END = 456U, /* TRNG_END */ + + /* SDIOC */ + INT_SRC_SDIOC1_SD = 482U, /* SDIOC1_SD */ + INT_SRC_SDIOC2_SD = 485U, /* SDIOC2_SD */ + + /* CAN */ + INT_SRC_CAN_INT = 486U, /* CAN_INT */ + + INT_SRC_MAX = 511U, +} en_int_src_t; + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif +/** + * @brief ADC + */ +typedef struct { + __IO uint8_t STR; + uint8_t RESERVED0[1]; + __IO uint16_t CR0; + __IO uint16_t CR1; + uint8_t RESERVED1[4]; + __IO uint16_t TRGSR; + __IO uint32_t CHSELRA; + __IO uint32_t CHSELRB; + __IO uint32_t AVCHSELR; + uint8_t RESERVED2[8]; + __IO uint8_t SSTR0; + __IO uint8_t SSTR1; + __IO uint8_t SSTR2; + __IO uint8_t SSTR3; + __IO uint8_t SSTR4; + __IO uint8_t SSTR5; + __IO uint8_t SSTR6; + __IO uint8_t SSTR7; + __IO uint8_t SSTR8; + __IO uint8_t SSTR9; + __IO uint8_t SSTR10; + __IO uint8_t SSTR11; + __IO uint8_t SSTR12; + __IO uint8_t SSTR13; + __IO uint8_t SSTR14; + __IO uint8_t SSTR15; + __IO uint8_t SSTRL; + uint8_t RESERVED3[7]; + __IO uint16_t CHMUXR0; + __IO uint16_t CHMUXR1; + __IO uint16_t CHMUXR2; + __IO uint16_t CHMUXR3; + uint8_t RESERVED4[6]; + __IO uint8_t ISR; + __IO uint8_t ICR; + uint8_t RESERVED5[4]; + __IO uint16_t SYNCCR; + uint8_t RESERVED6[2]; + __I uint16_t DR0; + __I uint16_t DR1; + __I uint16_t DR2; + __I uint16_t DR3; + __I uint16_t DR4; + __I uint16_t DR5; + __I uint16_t DR6; + __I uint16_t DR7; + __I uint16_t DR8; + __I uint16_t DR9; + __I uint16_t DR10; + __I uint16_t DR11; + __I uint16_t DR12; + __I uint16_t DR13; + __I uint16_t DR14; + __I uint16_t DR15; + __I uint16_t DR16; + uint8_t RESERVED7[46]; + __IO uint16_t AWDCR; + uint8_t RESERVED8[2]; + __IO uint16_t AWDDR0; + __IO uint16_t AWDDR1; + uint8_t RESERVED9[4]; + __IO uint32_t AWDCHSR; + __IO uint32_t AWDSR; + uint8_t RESERVED10[12]; + __IO uint16_t PGACR; + __IO uint16_t PGAGSR; + uint8_t RESERVED11[8]; + __IO uint16_t PGAINSR0; + __IO uint16_t PGAINSR1; +} CM_ADC_TypeDef; + +/** + * @brief AES + */ +typedef struct { + __IO uint32_t CR; + uint8_t RESERVED0[12]; + __IO uint32_t DR0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t KR0; + __IO uint32_t KR1; + __IO uint32_t KR2; + __IO uint32_t KR3; +} CM_AES_TypeDef; + +/** + * @brief AOS + */ +typedef struct { + __O uint32_t INTSFTTRG; + __IO uint32_t DCU_TRGSEL1; + __IO uint32_t DCU_TRGSEL2; + __IO uint32_t DCU_TRGSEL3; + __IO uint32_t DCU_TRGSEL4; + __IO uint32_t DMA1_TRGSEL0; + __IO uint32_t DMA1_TRGSEL1; + __IO uint32_t DMA1_TRGSEL2; + __IO uint32_t DMA1_TRGSEL3; + __IO uint32_t DMA2_TRGSEL0; + __IO uint32_t DMA2_TRGSEL1; + __IO uint32_t DMA2_TRGSEL2; + __IO uint32_t DMA2_TRGSEL3; + __IO uint32_t DMA_RC_TRGSEL; + __IO uint32_t TMR6_TRGSEL0; + __IO uint32_t TMR6_TRGSEL1; + __IO uint32_t TMR0_TRGSEL; + __IO uint32_t PEVNT_TRGSEL12; + __IO uint32_t PEVNT_TRGSEL34; + __IO uint32_t TMRA_TRGSEL0; + __IO uint32_t TMRA_TRGSEL1; + __IO uint32_t OTS_TRGSEL; + __IO uint32_t ADC1_TRGSEL0; + __IO uint32_t ADC1_TRGSEL1; + __IO uint32_t ADC2_TRGSEL0; + __IO uint32_t ADC2_TRGSEL1; + __IO uint32_t COMTRG1; + __IO uint32_t COMTRG2; + uint8_t RESERVED0[144]; + __IO uint32_t PEVNTDIRR1; + __I uint32_t PEVNTIDR1; + __IO uint32_t PEVNTODR1; + __IO uint32_t PEVNTORR1; + __IO uint32_t PEVNTOSR1; + __IO uint32_t PEVNTRISR1; + __IO uint32_t PEVNTFALR1; + __IO uint32_t PEVNTDIRR2; + __I uint32_t PEVNTIDR2; + __IO uint32_t PEVNTODR2; + __IO uint32_t PEVNTORR2; + __IO uint32_t PEVNTOSR2; + __IO uint32_t PEVNTRISR2; + __IO uint32_t PEVNTFALR2; + __IO uint32_t PEVNTDIRR3; + __I uint32_t PEVNTIDR3; + __IO uint32_t PEVNTODR3; + __IO uint32_t PEVNTORR3; + __IO uint32_t PEVNTOSR3; + __IO uint32_t PEVNTRISR3; + __IO uint32_t PEVNTFALR3; + __IO uint32_t PEVNTDIRR4; + __I uint32_t PEVNTIDR4; + __IO uint32_t PEVNTODR4; + __IO uint32_t PEVNTORR4; + __IO uint32_t PEVNTOSR4; + __IO uint32_t PEVNTRISR4; + __IO uint32_t PEVNTFALR4; + __IO uint32_t PEVNTNFCR; +} CM_AOS_TypeDef; + +/** + * @brief CAN + */ +typedef struct { + __I uint32_t RBUF; + uint8_t RESERVED0[76]; + __IO uint32_t TBUF; + uint8_t RESERVED1[76]; + __IO uint8_t CFG_STAT; + __IO uint8_t TCMD; + __IO uint8_t TCTRL; + __IO uint8_t RCTRL; + __IO uint8_t RTIE; + __IO uint8_t RTIF; + __IO uint8_t ERRINT; + __IO uint8_t LIMIT; + __IO uint32_t SBT; + uint8_t RESERVED2[4]; + __I uint8_t EALCAP; + uint8_t RESERVED3[1]; + __IO uint8_t RECNT; + __IO uint8_t TECNT; + __IO uint8_t ACFCTRL; + uint8_t RESERVED4[1]; + __IO uint8_t ACFEN; + uint8_t RESERVED5[1]; + __IO uint32_t ACF; + uint8_t RESERVED6[2]; + __IO uint8_t TBSLOT; + __IO uint8_t TTCFG; + __IO uint32_t REF_MSG; + __IO uint16_t TRG_CFG; + __IO uint16_t TT_TRIG; + __IO uint16_t TT_WTRIG; +} CM_CAN_TypeDef; + +/** + * @brief CMP + */ +typedef struct { + __IO uint16_t CTRL; + __IO uint16_t VLTSEL; + __I uint16_t OUTMON; + __IO uint16_t CVSSTB; + __IO uint16_t CVSPRD; +} CM_CMP_TypeDef; + +/** + * @brief CMPCR + */ +typedef struct { + uint8_t RESERVED0[256]; + __IO uint16_t DADR1; + __IO uint16_t DADR2; + uint8_t RESERVED1[4]; + __IO uint16_t DACR; + uint8_t RESERVED2[2]; + __IO uint16_t RVADC; +} CM_CMPCR_TypeDef; + +/** + * @brief CMU + */ +typedef struct { + uint8_t RESERVED0[16]; + __IO uint16_t PERICKSEL; + __IO uint16_t I2SCKSEL; + uint8_t RESERVED1[12]; + __IO uint32_t SCFGR; + __IO uint8_t USBCKCFGR; + uint8_t RESERVED2[1]; + __IO uint8_t CKSWR; + uint8_t RESERVED3[3]; + __IO uint8_t PLLCR; + uint8_t RESERVED4[3]; + __IO uint8_t UPLLCR; + uint8_t RESERVED5[3]; + __IO uint8_t XTALCR; + uint8_t RESERVED6[3]; + __IO uint8_t HRCCR; + uint8_t RESERVED7[1]; + __IO uint8_t MRCCR; + uint8_t RESERVED8[3]; + __IO uint8_t OSCSTBSR; + __IO uint8_t MCO1CFGR; + __IO uint8_t MCO2CFGR; + __IO uint8_t TPIUCKCFGR; + __IO uint8_t XTALSTDCR; + __IO uint8_t XTALSTDSR; + uint8_t RESERVED9[31]; + __IO uint8_t MRCTRM; + __IO uint8_t HRCTRM; + uint8_t RESERVED10[63]; + __IO uint8_t XTALSTBCR; + uint8_t RESERVED11[93]; + __IO uint32_t PLLCFGR; + __IO uint32_t UPLLCFGR; + uint8_t RESERVED12[776]; + __IO uint8_t XTALCFGR; + uint8_t RESERVED13[15]; + __IO uint8_t XTAL32CR; + __IO uint8_t XTAL32CFGR; + uint8_t RESERVED14[3]; + __IO uint8_t XTAL32NFR; + uint8_t RESERVED15[1]; + __IO uint8_t LRCCR; + uint8_t RESERVED16[1]; + __IO uint8_t LRCTRM; +} CM_CMU_TypeDef; + +/** + * @brief CRC + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t RESLT; + uint8_t RESERVED0[4]; + __I uint32_t FLG; + uint8_t RESERVED1[112]; + __I uint32_t DAT0; + __I uint32_t DAT1; + __I uint32_t DAT2; + __I uint32_t DAT3; + __I uint32_t DAT4; + __I uint32_t DAT5; + __I uint32_t DAT6; + __I uint32_t DAT7; + __I uint32_t DAT8; + __I uint32_t DAT9; + __I uint32_t DAT10; + __I uint32_t DAT11; + __I uint32_t DAT12; + __I uint32_t DAT13; + __I uint32_t DAT14; + __I uint32_t DAT15; + __I uint32_t DAT16; + __I uint32_t DAT17; + __I uint32_t DAT18; + __I uint32_t DAT19; + __I uint32_t DAT20; + __I uint32_t DAT21; + __I uint32_t DAT22; + __I uint32_t DAT23; + __I uint32_t DAT24; + __I uint32_t DAT25; + __I uint32_t DAT26; + __I uint32_t DAT27; + __I uint32_t DAT28; + __I uint32_t DAT29; + __I uint32_t DAT30; + __I uint32_t DAT31; +} CM_CRC_TypeDef; + +/** + * @brief DBGC + */ +typedef struct { + __IO uint32_t AUTHID0; + __IO uint32_t AUTHID1; + __IO uint32_t AUTHID2; + uint8_t RESERVED0[4]; + __IO uint32_t MCUSTAT; + uint8_t RESERVED1[4]; + __IO uint32_t FERSCTL; + __IO uint32_t MCUDBGSTAT; + __IO uint32_t MCUSTPCTL; + __IO uint32_t MCUTRACECTL; +} CM_DBGC_TypeDef; + +/** + * @brief DCU + */ +typedef struct { + __IO uint32_t CTL; + __I uint32_t FLAG; + __IO uint32_t DATA0; + __IO uint32_t DATA1; + __IO uint32_t DATA2; + __O uint32_t FLAGCLR; + __IO uint32_t INTEVTSEL; +} CM_DCU_TypeDef; + +/** + * @brief DMA + */ +typedef struct { + __IO uint32_t EN; + __I uint32_t INTSTAT0; + __I uint32_t INTSTAT1; + __IO uint32_t INTMASK0; + __IO uint32_t INTMASK1; + __O uint32_t INTCLR0; + __O uint32_t INTCLR1; + __IO uint32_t CHEN; + __I uint32_t REQSTAT; + __I uint32_t CHSTAT; + uint8_t RESERVED0[4]; + __IO uint32_t RCFGCTL; + uint8_t RESERVED1[16]; + __IO uint32_t SAR0; + __IO uint32_t DAR0; + __IO uint32_t DTCTL0; + union { + __IO uint32_t RPT0; + __IO uint32_t RPTB0; + }; + union { + __IO uint32_t SNSEQCTL0; + __IO uint32_t SNSEQCTLB0; + }; + union { + __IO uint32_t DNSEQCTL0; + __IO uint32_t DNSEQCTLB0; + }; + __IO uint32_t LLP0; + __IO uint32_t CHCTL0; + __I uint32_t MONSAR0; + __I uint32_t MONDAR0; + __I uint32_t MONDTCTL0; + __I uint32_t MONRPT0; + __I uint32_t MONSNSEQCTL0; + __I uint32_t MONDNSEQCTL0; + uint8_t RESERVED2[8]; + __IO uint32_t SAR1; + __IO uint32_t DAR1; + __IO uint32_t DTCTL1; + union { + __IO uint32_t RPT1; + __IO uint32_t RPTB1; + }; + union { + __IO uint32_t SNSEQCTL1; + __IO uint32_t SNSEQCTLB1; + }; + union { + __IO uint32_t DNSEQCTL1; + __IO uint32_t DNSEQCTLB1; + }; + __IO uint32_t LLP1; + __IO uint32_t CHCTL1; + __I uint32_t MONSAR1; + __I uint32_t MONDAR1; + __I uint32_t MONDTCTL1; + __I uint32_t MONRPT1; + __I uint32_t MONSNSEQCTL1; + __I uint32_t MONDNSEQCTL1; + uint8_t RESERVED3[8]; + __IO uint32_t SAR2; + __IO uint32_t DAR2; + __IO uint32_t DTCTL2; + union { + __IO uint32_t RPT2; + __IO uint32_t RPTB2; + }; + union { + __IO uint32_t SNSEQCTL2; + __IO uint32_t SNSEQCTLB2; + }; + union { + __IO uint32_t DNSEQCTL2; + __IO uint32_t DNSEQCTLB2; + }; + __IO uint32_t LLP2; + __IO uint32_t CHCTL2; + __I uint32_t MONSAR2; + __I uint32_t MONDAR2; + __I uint32_t MONDTCTL2; + __I uint32_t MONRPT2; + __I uint32_t MONSNSEQCTL2; + __I uint32_t MONDNSEQCTL2; + uint8_t RESERVED4[8]; + __IO uint32_t SAR3; + __IO uint32_t DAR3; + __IO uint32_t DTCTL3; + union { + __IO uint32_t RPT3; + __IO uint32_t RPTB3; + }; + union { + __IO uint32_t SNSEQCTL3; + __IO uint32_t SNSEQCTLB3; + }; + union { + __IO uint32_t DNSEQCTL3; + __IO uint32_t DNSEQCTLB3; + }; + __IO uint32_t LLP3; + __IO uint32_t CHCTL3; + __I uint32_t MONSAR3; + __I uint32_t MONDAR3; + __I uint32_t MONDTCTL3; + __I uint32_t MONRPT3; + __I uint32_t MONSNSEQCTL3; + __I uint32_t MONDNSEQCTL3; +} CM_DMA_TypeDef; + +/** + * @brief EFM + */ +typedef struct { + __IO uint32_t FAPRT; + __IO uint32_t FSTP; + __IO uint32_t FRMC; + __IO uint32_t FWMC; + __I uint32_t FSR; + __IO uint32_t FSCLR; + __IO uint32_t FITE; + __I uint32_t FSWP; + __IO uint32_t FPMTSW; + __IO uint32_t FPMTEW; + uint8_t RESERVED0[40]; + __I uint32_t UQID0; + __I uint32_t UQID1; + __I uint32_t UQID2; + uint8_t RESERVED1[164]; + __IO uint32_t MMF_REMPRT; + __IO uint32_t MMF_REMCR0; + __IO uint32_t MMF_REMCR1; +} CM_EFM_TypeDef; + +/** + * @brief EMB + */ +typedef struct { + __IO uint32_t CTL; + __IO uint32_t PWMLV; + __IO uint32_t SOE; + __I uint32_t STAT; + __O uint32_t STATCLR; + __IO uint32_t INTEN; +} CM_EMB_TypeDef; + +/** + * @brief FCM + */ +typedef struct { + __IO uint32_t LVR; + __IO uint32_t UVR; + __I uint32_t CNTR; + __IO uint32_t STR; + __IO uint32_t MCCR; + __IO uint32_t RCCR; + __IO uint32_t RIER; + __I uint32_t SR; + __O uint32_t CLR; +} CM_FCM_TypeDef; + +/** + * @brief GPIO + */ +typedef struct { + __I uint16_t PIDRA; + uint8_t RESERVED0[2]; + __IO uint16_t PODRA; + __IO uint16_t POERA; + __IO uint16_t POSRA; + __IO uint16_t PORRA; + __IO uint16_t POTRA; + uint8_t RESERVED1[2]; + __I uint16_t PIDRB; + uint8_t RESERVED2[2]; + __IO uint16_t PODRB; + __IO uint16_t POERB; + __IO uint16_t POSRB; + __IO uint16_t PORRB; + __IO uint16_t POTRB; + uint8_t RESERVED3[2]; + __I uint16_t PIDRC; + uint8_t RESERVED4[2]; + __IO uint16_t PODRC; + __IO uint16_t POERC; + __IO uint16_t POSRC; + __IO uint16_t PORRC; + __IO uint16_t POTRC; + uint8_t RESERVED5[2]; + __I uint16_t PIDRD; + uint8_t RESERVED6[2]; + __IO uint16_t PODRD; + __IO uint16_t POERD; + __IO uint16_t POSRD; + __IO uint16_t PORRD; + __IO uint16_t POTRD; + uint8_t RESERVED7[2]; + __I uint16_t PIDRE; + uint8_t RESERVED8[2]; + __IO uint16_t PODRE; + __IO uint16_t POERE; + __IO uint16_t POSRE; + __IO uint16_t PORRE; + __IO uint16_t POTRE; + uint8_t RESERVED9[2]; + __I uint16_t PIDRH; + uint8_t RESERVED10[2]; + __IO uint16_t PODRH; + __IO uint16_t POERH; + __IO uint16_t POSRH; + __IO uint16_t PORRH; + __IO uint16_t POTRH; + uint8_t RESERVED11[918]; + __IO uint16_t PSPCR; + uint8_t RESERVED12[2]; + __IO uint16_t PCCR; + __IO uint16_t PINAER; + __IO uint16_t PWPR; + uint8_t RESERVED13[2]; + __IO uint16_t PCRA0; + __IO uint16_t PFSRA0; + __IO uint16_t PCRA1; + __IO uint16_t PFSRA1; + __IO uint16_t PCRA2; + __IO uint16_t PFSRA2; + __IO uint16_t PCRA3; + __IO uint16_t PFSRA3; + __IO uint16_t PCRA4; + __IO uint16_t PFSRA4; + __IO uint16_t PCRA5; + __IO uint16_t PFSRA5; + __IO uint16_t PCRA6; + __IO uint16_t PFSRA6; + __IO uint16_t PCRA7; + __IO uint16_t PFSRA7; + __IO uint16_t PCRA8; + __IO uint16_t PFSRA8; + __IO uint16_t PCRA9; + __IO uint16_t PFSRA9; + __IO uint16_t PCRA10; + __IO uint16_t PFSRA10; + __IO uint16_t PCRA11; + __IO uint16_t PFSRA11; + __IO uint16_t PCRA12; + __IO uint16_t PFSRA12; + __IO uint16_t PCRA13; + __IO uint16_t PFSRA13; + __IO uint16_t PCRA14; + __IO uint16_t PFSRA14; + __IO uint16_t PCRA15; + __IO uint16_t PFSRA15; + __IO uint16_t PCRB0; + __IO uint16_t PFSRB0; + __IO uint16_t PCRB1; + __IO uint16_t PFSRB1; + __IO uint16_t PCRB2; + __IO uint16_t PFSRB2; + __IO uint16_t PCRB3; + __IO uint16_t PFSRB3; + __IO uint16_t PCRB4; + __IO uint16_t PFSRB4; + __IO uint16_t PCRB5; + __IO uint16_t PFSRB5; + __IO uint16_t PCRB6; + __IO uint16_t PFSRB6; + __IO uint16_t PCRB7; + __IO uint16_t PFSRB7; + __IO uint16_t PCRB8; + __IO uint16_t PFSRB8; + __IO uint16_t PCRB9; + __IO uint16_t PFSRB9; + __IO uint16_t PCRB10; + __IO uint16_t PFSRB10; + __IO uint16_t PCRB11; + __IO uint16_t PFSRB11; + __IO uint16_t PCRB12; + __IO uint16_t PFSRB12; + __IO uint16_t PCRB13; + __IO uint16_t PFSRB13; + __IO uint16_t PCRB14; + __IO uint16_t PFSRB14; + __IO uint16_t PCRB15; + __IO uint16_t PFSRB15; + __IO uint16_t PCRC0; + __IO uint16_t PFSRC0; + __IO uint16_t PCRC1; + __IO uint16_t PFSRC1; + __IO uint16_t PCRC2; + __IO uint16_t PFSRC2; + __IO uint16_t PCRC3; + __IO uint16_t PFSRC3; + __IO uint16_t PCRC4; + __IO uint16_t PFSRC4; + __IO uint16_t PCRC5; + __IO uint16_t PFSRC5; + __IO uint16_t PCRC6; + __IO uint16_t PFSRC6; + __IO uint16_t PCRC7; + __IO uint16_t PFSRC7; + __IO uint16_t PCRC8; + __IO uint16_t PFSRC8; + __IO uint16_t PCRC9; + __IO uint16_t PFSRC9; + __IO uint16_t PCRC10; + __IO uint16_t PFSRC10; + __IO uint16_t PCRC11; + __IO uint16_t PFSRC11; + __IO uint16_t PCRC12; + __IO uint16_t PFSRC12; + __IO uint16_t PCRC13; + __IO uint16_t PFSRC13; + __IO uint16_t PCRC14; + __IO uint16_t PFSRC14; + __IO uint16_t PCRC15; + __IO uint16_t PFSRC15; + __IO uint16_t PCRD0; + __IO uint16_t PFSRD0; + __IO uint16_t PCRD1; + __IO uint16_t PFSRD1; + __IO uint16_t PCRD2; + __IO uint16_t PFSRD2; + __IO uint16_t PCRD3; + __IO uint16_t PFSRD3; + __IO uint16_t PCRD4; + __IO uint16_t PFSRD4; + __IO uint16_t PCRD5; + __IO uint16_t PFSRD5; + __IO uint16_t PCRD6; + __IO uint16_t PFSRD6; + __IO uint16_t PCRD7; + __IO uint16_t PFSRD7; + __IO uint16_t PCRD8; + __IO uint16_t PFSRD8; + __IO uint16_t PCRD9; + __IO uint16_t PFSRD9; + __IO uint16_t PCRD10; + __IO uint16_t PFSRD10; + __IO uint16_t PCRD11; + __IO uint16_t PFSRD11; + __IO uint16_t PCRD12; + __IO uint16_t PFSRD12; + __IO uint16_t PCRD13; + __IO uint16_t PFSRD13; + __IO uint16_t PCRD14; + __IO uint16_t PFSRD14; + __IO uint16_t PCRD15; + __IO uint16_t PFSRD15; + __IO uint16_t PCRE0; + __IO uint16_t PFSRE0; + __IO uint16_t PCRE1; + __IO uint16_t PFSRE1; + __IO uint16_t PCRE2; + __IO uint16_t PFSRE2; + __IO uint16_t PCRE3; + __IO uint16_t PFSRE3; + __IO uint16_t PCRE4; + __IO uint16_t PFSRE4; + __IO uint16_t PCRE5; + __IO uint16_t PFSRE5; + __IO uint16_t PCRE6; + __IO uint16_t PFSRE6; + __IO uint16_t PCRE7; + __IO uint16_t PFSRE7; + __IO uint16_t PCRE8; + __IO uint16_t PFSRE8; + __IO uint16_t PCRE9; + __IO uint16_t PFSRE9; + __IO uint16_t PCRE10; + __IO uint16_t PFSRE10; + __IO uint16_t PCRE11; + __IO uint16_t PFSRE11; + __IO uint16_t PCRE12; + __IO uint16_t PFSRE12; + __IO uint16_t PCRE13; + __IO uint16_t PFSRE13; + __IO uint16_t PCRE14; + __IO uint16_t PFSRE14; + __IO uint16_t PCRE15; + __IO uint16_t PFSRE15; + __IO uint16_t PCRH0; + __IO uint16_t PFSRH0; + __IO uint16_t PCRH1; + __IO uint16_t PFSRH1; + __IO uint16_t PCRH2; + __IO uint16_t PFSRH2; +} CM_GPIO_TypeDef; + +/** + * @brief HASH + */ +typedef struct { + __IO uint32_t CR; + uint8_t RESERVED0[12]; + __IO uint32_t HR7; + __IO uint32_t HR6; + __IO uint32_t HR5; + __IO uint32_t HR4; + __IO uint32_t HR3; + __IO uint32_t HR2; + __IO uint32_t HR1; + __IO uint32_t HR0; + uint8_t RESERVED1[16]; + __IO uint32_t DR15; + __IO uint32_t DR14; + __IO uint32_t DR13; + __IO uint32_t DR12; + __IO uint32_t DR11; + __IO uint32_t DR10; + __IO uint32_t DR9; + __IO uint32_t DR8; + __IO uint32_t DR7; + __IO uint32_t DR6; + __IO uint32_t DR5; + __IO uint32_t DR4; + __IO uint32_t DR3; + __IO uint32_t DR2; + __IO uint32_t DR1; + __IO uint32_t DR0; +} CM_HASH_TypeDef; + +/** + * @brief I2C + */ +typedef struct { + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t CR3; + __IO uint32_t CR4; + __IO uint32_t SLR0; + __IO uint32_t SLR1; + __IO uint32_t SLTR; + __IO uint32_t SR; + __O uint32_t CLR; + __O uint8_t DTR; + uint8_t RESERVED0[3]; + __I uint8_t DRR; + uint8_t RESERVED1[3]; + __IO uint32_t CCR; + __IO uint32_t FLTR; +} CM_I2C_TypeDef; + +/** + * @brief I2S + */ +typedef struct { + __IO uint32_t CTRL; + __I uint32_t SR; + __IO uint32_t ER; + __IO uint32_t CFGR; + __O uint32_t TXBUF; + __I uint32_t RXBUF; + __IO uint32_t PR; +} CM_I2S_TypeDef; + +/** + * @brief ICG + */ +typedef struct { + __I uint32_t ICG0; + __I uint32_t ICG1; + __I uint32_t ICG2; + __I uint32_t ICG3; + __I uint32_t ICG4; + __I uint32_t ICG5; + __I uint32_t ICG6; + __I uint32_t ICG7; +} CM_ICG_TypeDef; + +/** + * @brief INTC + */ +typedef struct { + __IO uint32_t NMICR; + __IO uint32_t NMIENR; + __IO uint32_t NMIFR; + __IO uint32_t NMICFR; + __IO uint32_t EIRQCR0; + __IO uint32_t EIRQCR1; + __IO uint32_t EIRQCR2; + __IO uint32_t EIRQCR3; + __IO uint32_t EIRQCR4; + __IO uint32_t EIRQCR5; + __IO uint32_t EIRQCR6; + __IO uint32_t EIRQCR7; + __IO uint32_t EIRQCR8; + __IO uint32_t EIRQCR9; + __IO uint32_t EIRQCR10; + __IO uint32_t EIRQCR11; + __IO uint32_t EIRQCR12; + __IO uint32_t EIRQCR13; + __IO uint32_t EIRQCR14; + __IO uint32_t EIRQCR15; + __IO uint32_t WUPEN; + __IO uint32_t EIFR; + __IO uint32_t EIFCR; + __IO uint32_t SEL0; + __IO uint32_t SEL1; + __IO uint32_t SEL2; + __IO uint32_t SEL3; + __IO uint32_t SEL4; + __IO uint32_t SEL5; + __IO uint32_t SEL6; + __IO uint32_t SEL7; + __IO uint32_t SEL8; + __IO uint32_t SEL9; + __IO uint32_t SEL10; + __IO uint32_t SEL11; + __IO uint32_t SEL12; + __IO uint32_t SEL13; + __IO uint32_t SEL14; + __IO uint32_t SEL15; + __IO uint32_t SEL16; + __IO uint32_t SEL17; + __IO uint32_t SEL18; + __IO uint32_t SEL19; + __IO uint32_t SEL20; + __IO uint32_t SEL21; + __IO uint32_t SEL22; + __IO uint32_t SEL23; + __IO uint32_t SEL24; + __IO uint32_t SEL25; + __IO uint32_t SEL26; + __IO uint32_t SEL27; + __IO uint32_t SEL28; + __IO uint32_t SEL29; + __IO uint32_t SEL30; + __IO uint32_t SEL31; + __IO uint32_t SEL32; + __IO uint32_t SEL33; + __IO uint32_t SEL34; + __IO uint32_t SEL35; + __IO uint32_t SEL36; + __IO uint32_t SEL37; + __IO uint32_t SEL38; + __IO uint32_t SEL39; + __IO uint32_t SEL40; + __IO uint32_t SEL41; + __IO uint32_t SEL42; + __IO uint32_t SEL43; + __IO uint32_t SEL44; + __IO uint32_t SEL45; + __IO uint32_t SEL46; + __IO uint32_t SEL47; + __IO uint32_t SEL48; + __IO uint32_t SEL49; + __IO uint32_t SEL50; + __IO uint32_t SEL51; + __IO uint32_t SEL52; + __IO uint32_t SEL53; + __IO uint32_t SEL54; + __IO uint32_t SEL55; + __IO uint32_t SEL56; + __IO uint32_t SEL57; + __IO uint32_t SEL58; + __IO uint32_t SEL59; + __IO uint32_t SEL60; + __IO uint32_t SEL61; + __IO uint32_t SEL62; + __IO uint32_t SEL63; + __IO uint32_t SEL64; + __IO uint32_t SEL65; + __IO uint32_t SEL66; + __IO uint32_t SEL67; + __IO uint32_t SEL68; + __IO uint32_t SEL69; + __IO uint32_t SEL70; + __IO uint32_t SEL71; + __IO uint32_t SEL72; + __IO uint32_t SEL73; + __IO uint32_t SEL74; + __IO uint32_t SEL75; + __IO uint32_t SEL76; + __IO uint32_t SEL77; + __IO uint32_t SEL78; + __IO uint32_t SEL79; + __IO uint32_t SEL80; + __IO uint32_t SEL81; + __IO uint32_t SEL82; + __IO uint32_t SEL83; + __IO uint32_t SEL84; + __IO uint32_t SEL85; + __IO uint32_t SEL86; + __IO uint32_t SEL87; + __IO uint32_t SEL88; + __IO uint32_t SEL89; + __IO uint32_t SEL90; + __IO uint32_t SEL91; + __IO uint32_t SEL92; + __IO uint32_t SEL93; + __IO uint32_t SEL94; + __IO uint32_t SEL95; + __IO uint32_t SEL96; + __IO uint32_t SEL97; + __IO uint32_t SEL98; + __IO uint32_t SEL99; + __IO uint32_t SEL100; + __IO uint32_t SEL101; + __IO uint32_t SEL102; + __IO uint32_t SEL103; + __IO uint32_t SEL104; + __IO uint32_t SEL105; + __IO uint32_t SEL106; + __IO uint32_t SEL107; + __IO uint32_t SEL108; + __IO uint32_t SEL109; + __IO uint32_t SEL110; + __IO uint32_t SEL111; + __IO uint32_t SEL112; + __IO uint32_t SEL113; + __IO uint32_t SEL114; + __IO uint32_t SEL115; + __IO uint32_t SEL116; + __IO uint32_t SEL117; + __IO uint32_t SEL118; + __IO uint32_t SEL119; + __IO uint32_t SEL120; + __IO uint32_t SEL121; + __IO uint32_t SEL122; + __IO uint32_t SEL123; + __IO uint32_t SEL124; + __IO uint32_t SEL125; + __IO uint32_t SEL126; + __IO uint32_t SEL127; + __IO uint32_t VSSEL128; + __IO uint32_t VSSEL129; + __IO uint32_t VSSEL130; + __IO uint32_t VSSEL131; + __IO uint32_t VSSEL132; + __IO uint32_t VSSEL133; + __IO uint32_t VSSEL134; + __IO uint32_t VSSEL135; + __IO uint32_t VSSEL136; + __IO uint32_t VSSEL137; + __IO uint32_t VSSEL138; + __IO uint32_t VSSEL139; + __IO uint32_t VSSEL140; + __IO uint32_t VSSEL141; + __IO uint32_t VSSEL142; + __IO uint32_t VSSEL143; + __IO uint32_t SWIER; + __IO uint32_t EVTER; + __IO uint32_t IER; +} CM_INTC_TypeDef; + +/** + * @brief KEYSCAN + */ +typedef struct { + __IO uint32_t SCR; + __IO uint32_t SER; + __IO uint32_t SSR; +} CM_KEYSCAN_TypeDef; + +/** + * @brief MPU + */ +typedef struct { + __IO uint32_t RGD0; + __IO uint32_t RGD1; + __IO uint32_t RGD2; + __IO uint32_t RGD3; + __IO uint32_t RGD4; + __IO uint32_t RGD5; + __IO uint32_t RGD6; + __IO uint32_t RGD7; + __IO uint32_t RGD8; + __IO uint32_t RGD9; + __IO uint32_t RGD10; + __IO uint32_t RGD11; + __IO uint32_t RGD12; + __IO uint32_t RGD13; + __IO uint32_t RGD14; + __IO uint32_t RGD15; + __IO uint32_t RGCR0; + __IO uint32_t RGCR1; + __IO uint32_t RGCR2; + __IO uint32_t RGCR3; + __IO uint32_t RGCR4; + __IO uint32_t RGCR5; + __IO uint32_t RGCR6; + __IO uint32_t RGCR7; + __IO uint32_t RGCR8; + __IO uint32_t RGCR9; + __IO uint32_t RGCR10; + __IO uint32_t RGCR11; + __IO uint32_t RGCR12; + __IO uint32_t RGCR13; + __IO uint32_t RGCR14; + __IO uint32_t RGCR15; + __IO uint32_t CR; + __I uint32_t SR; + __O uint32_t ECLR; + __IO uint32_t WP; + uint8_t RESERVED0[16268]; + __IO uint32_t IPPR; +} CM_MPU_TypeDef; + +/** + * @brief OTS + */ +typedef struct { + __IO uint16_t CTL; + __IO uint16_t DR1; + __IO uint16_t DR2; + __IO uint16_t ECR; +} CM_OTS_TypeDef; + +/** + * @brief PERIC + */ +typedef struct { + __IO uint32_t USBFS_SYCTLREG; + __IO uint32_t SDIOC_SYCTLREG; +} CM_PERIC_TypeDef; + +/** + * @brief PWC + */ +typedef struct { + __IO uint32_t FCG0; + __IO uint32_t FCG1; + __IO uint32_t FCG2; + __IO uint32_t FCG3; + __IO uint32_t FCG0PC; + uint8_t RESERVED0[17388]; + __IO uint16_t WKTCR; + uint8_t RESERVED1[31754]; + __IO uint16_t STPMCR; + uint8_t RESERVED2[6]; + __IO uint32_t RAMPC0; + __IO uint16_t RAMOPM; + uint8_t RESERVED3[198]; + __IO uint8_t PVDICR; + __IO uint8_t PVDDSR; + uint8_t RESERVED4[796]; + __IO uint16_t FPRC; + __IO uint8_t PWRC0; + __IO uint8_t PWRC1; + __IO uint8_t PWRC2; + __IO uint8_t PWRC3; + __IO uint8_t PDWKE0; + __IO uint8_t PDWKE1; + __IO uint8_t PDWKE2; + __IO uint8_t PDWKES; + __IO uint8_t PDWKF0; + __IO uint8_t PDWKF1; + __IO uint8_t PWCMR; + uint8_t RESERVED5[4]; + __IO uint8_t MDSWCR; + uint8_t RESERVED6[2]; + __IO uint8_t PVDCR0; + __IO uint8_t PVDCR1; + __IO uint8_t PVDFCR; + __IO uint8_t PVDLCR; + uint8_t RESERVED7[21]; + __IO uint8_t XTAL32CS; +} CM_PWC_TypeDef; + +/** + * @brief QSPI + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t CSCR; + __IO uint32_t FCR; + __IO uint32_t SR; + __IO uint32_t DCOM; + __IO uint32_t CCMD; + __IO uint32_t XCMD; + uint8_t RESERVED0[8]; + __O uint32_t SR2; + uint8_t RESERVED1[2012]; + __IO uint32_t EXAR; +} CM_QSPI_TypeDef; + +/** + * @brief RMU + */ +typedef struct { + __IO uint16_t RSTF0; +} CM_RMU_TypeDef; + +/** + * @brief RTC + */ +typedef struct { + __IO uint8_t CR0; + uint8_t RESERVED0[3]; + __IO uint8_t CR1; + uint8_t RESERVED1[3]; + __IO uint8_t CR2; + uint8_t RESERVED2[3]; + __IO uint8_t CR3; + uint8_t RESERVED3[3]; + __IO uint8_t SEC; + uint8_t RESERVED4[3]; + __IO uint8_t MIN; + uint8_t RESERVED5[3]; + __IO uint8_t HOUR; + uint8_t RESERVED6[3]; + __IO uint8_t WEEK; + uint8_t RESERVED7[3]; + __IO uint8_t DAY; + uint8_t RESERVED8[3]; + __IO uint8_t MON; + uint8_t RESERVED9[3]; + __IO uint8_t YEAR; + uint8_t RESERVED10[3]; + __IO uint8_t ALMMIN; + uint8_t RESERVED11[3]; + __IO uint8_t ALMHOUR; + uint8_t RESERVED12[3]; + __IO uint8_t ALMWEEK; + uint8_t RESERVED13[3]; + __IO uint8_t ERRCRH; + uint8_t RESERVED14[3]; + __IO uint8_t ERRCRL; +} CM_RTC_TypeDef; + +/** + * @brief SDIOC + */ +typedef struct { + uint8_t RESERVED0[4]; + __IO uint16_t BLKSIZE; + __IO uint16_t BLKCNT; + __IO uint16_t ARG0; + __IO uint16_t ARG1; + __IO uint16_t TRANSMODE; + __IO uint16_t CMD; + __I uint16_t RESP0; + __I uint16_t RESP1; + __I uint16_t RESP2; + __I uint16_t RESP3; + __I uint16_t RESP4; + __I uint16_t RESP5; + __I uint16_t RESP6; + __I uint16_t RESP7; + __IO uint16_t BUF0; + __IO uint16_t BUF1; + __I uint32_t PSTAT; + __IO uint8_t HOSTCON; + __IO uint8_t PWRCON; + __IO uint8_t BLKGPCON; + uint8_t RESERVED1[1]; + __IO uint16_t CLKCON; + __IO uint8_t TOUTCON; + __IO uint8_t SFTRST; + __IO uint16_t NORINTST; + __IO uint16_t ERRINTST; + __IO uint16_t NORINTSTEN; + __IO uint16_t ERRINTSTEN; + __IO uint16_t NORINTSGEN; + __IO uint16_t ERRINTSGEN; + __I uint16_t ATCERRST; + uint8_t RESERVED2[18]; + __O uint16_t FEA; + __O uint16_t FEE; +} CM_SDIOC_TypeDef; + +/** + * @brief SPI + */ +typedef struct { + __IO uint32_t DR; + __IO uint32_t CR1; + uint8_t RESERVED0[4]; + __IO uint32_t CFG1; + uint8_t RESERVED1[4]; + __IO uint32_t SR; + __IO uint32_t CFG2; +} CM_SPI_TypeDef; + +/** + * @brief SRAMC + */ +typedef struct { + __IO uint32_t WTCR; + __IO uint32_t WTPR; + __IO uint32_t CKCR; + __IO uint32_t CKPR; + __IO uint32_t CKSR; +} CM_SRAMC_TypeDef; + +/** + * @brief SWDT + */ +typedef struct { + uint8_t RESERVED0[4]; + __IO uint32_t SR; + __IO uint32_t RR; +} CM_SWDT_TypeDef; + +/** + * @brief TMR0 + */ +typedef struct { + __IO uint32_t CNTAR; + __IO uint32_t CNTBR; + __IO uint32_t CMPAR; + __IO uint32_t CMPBR; + __IO uint32_t BCONR; + __IO uint32_t STFLR; +} CM_TMR0_TypeDef; + +/** + * @brief TMR4 + */ +typedef struct { + uint8_t RESERVED0[2]; + __IO uint16_t OCCRUH; + uint8_t RESERVED1[2]; + __IO uint16_t OCCRUL; + uint8_t RESERVED2[2]; + __IO uint16_t OCCRVH; + uint8_t RESERVED3[2]; + __IO uint16_t OCCRVL; + uint8_t RESERVED4[2]; + __IO uint16_t OCCRWH; + uint8_t RESERVED5[2]; + __IO uint16_t OCCRWL; + __IO uint16_t OCSRU; + __IO uint16_t OCERU; + __IO uint16_t OCSRV; + __IO uint16_t OCERV; + __IO uint16_t OCSRW; + __IO uint16_t OCERW; + __IO uint16_t OCMRHUH; + uint8_t RESERVED6[2]; + __IO uint32_t OCMRLUL; + __IO uint16_t OCMRHVH; + uint8_t RESERVED7[2]; + __IO uint32_t OCMRLVL; + __IO uint16_t OCMRHWH; + uint8_t RESERVED8[2]; + __IO uint32_t OCMRLWL; + uint8_t RESERVED9[6]; + __IO uint16_t CPSR; + uint8_t RESERVED10[2]; + __IO uint16_t CNTR; + __IO uint16_t CCSR; + __IO uint16_t CVPR; + uint8_t RESERVED11[54]; + __IO uint16_t PFSRU; + __IO uint16_t PDARU; + __IO uint16_t PDBRU; + uint8_t RESERVED12[2]; + __IO uint16_t PFSRV; + __IO uint16_t PDARV; + __IO uint16_t PDBRV; + uint8_t RESERVED13[2]; + __IO uint16_t PFSRW; + __IO uint16_t PDARW; + __IO uint16_t PDBRW; + __IO uint16_t POCRU; + uint8_t RESERVED14[2]; + __IO uint16_t POCRV; + uint8_t RESERVED15[2]; + __IO uint16_t POCRW; + uint8_t RESERVED16[2]; + __IO uint16_t RCSR; + uint8_t RESERVED17[12]; + __IO uint16_t SCCRUH; + uint8_t RESERVED18[2]; + __IO uint16_t SCCRUL; + uint8_t RESERVED19[2]; + __IO uint16_t SCCRVH; + uint8_t RESERVED20[2]; + __IO uint16_t SCCRVL; + uint8_t RESERVED21[2]; + __IO uint16_t SCCRWH; + uint8_t RESERVED22[2]; + __IO uint16_t SCCRWL; + __IO uint16_t SCSRUH; + __IO uint16_t SCMRUH; + __IO uint16_t SCSRUL; + __IO uint16_t SCMRUL; + __IO uint16_t SCSRVH; + __IO uint16_t SCMRVH; + __IO uint16_t SCSRVL; + __IO uint16_t SCMRVL; + __IO uint16_t SCSRWH; + __IO uint16_t SCMRWH; + __IO uint16_t SCSRWL; + __IO uint16_t SCMRWL; + uint8_t RESERVED23[16]; + __IO uint16_t ECSR; +} CM_TMR4_TypeDef; + +/** + * @brief TMR4CR + */ +typedef struct { + __IO uint32_t ECER1; + __IO uint32_t ECER2; + __IO uint32_t ECER3; +} CM_TMR4CR_TypeDef; + +/** + * @brief TMR6 + */ +typedef struct { + __IO uint32_t CNTER; + __IO uint32_t PERAR; + __IO uint32_t PERBR; + __IO uint32_t PERCR; + __IO uint32_t GCMAR; + __IO uint32_t GCMBR; + __IO uint32_t GCMCR; + __IO uint32_t GCMDR; + __IO uint32_t GCMER; + __IO uint32_t GCMFR; + __IO uint32_t SCMAR; + __IO uint32_t SCMBR; + __IO uint32_t SCMCR; + __IO uint32_t SCMDR; + __IO uint32_t SCMER; + __IO uint32_t SCMFR; + __IO uint32_t DTUAR; + __IO uint32_t DTDAR; + __IO uint32_t DTUBR; + __IO uint32_t DTDBR; + __IO uint32_t GCONR; + __IO uint32_t ICONR; + __IO uint32_t PCONR; + __IO uint32_t BCONR; + __IO uint32_t DCONR; + uint8_t RESERVED0[4]; + __IO uint32_t FCONR; + __IO uint32_t VPERR; + __IO uint32_t STFLR; + __IO uint32_t HSTAR; + __IO uint32_t HSTPR; + __IO uint32_t HCLRR; + __IO uint32_t HCPAR; + __IO uint32_t HCPBR; + __IO uint32_t HCUPR; + __IO uint32_t HCDOR; +} CM_TMR6_TypeDef; + +/** + * @brief TMR6CR + */ +typedef struct { + uint8_t RESERVED0[1012]; + __IO uint32_t SSTAR; + __IO uint32_t SSTPR; + __IO uint32_t SCLRR; +} CM_TMR6CR_TypeDef; + +/** + * @brief TMRA + */ +typedef struct { + __IO uint16_t CNTER; + uint8_t RESERVED0[2]; + __IO uint16_t PERAR; + uint8_t RESERVED1[58]; + __IO uint16_t CMPAR1; + uint8_t RESERVED2[2]; + __IO uint16_t CMPAR2; + uint8_t RESERVED3[2]; + __IO uint16_t CMPAR3; + uint8_t RESERVED4[2]; + __IO uint16_t CMPAR4; + uint8_t RESERVED5[2]; + __IO uint16_t CMPAR5; + uint8_t RESERVED6[2]; + __IO uint16_t CMPAR6; + uint8_t RESERVED7[2]; + __IO uint16_t CMPAR7; + uint8_t RESERVED8[2]; + __IO uint16_t CMPAR8; + uint8_t RESERVED9[34]; + __IO uint8_t BCSTRL; + __IO uint8_t BCSTRH; + uint8_t RESERVED10[2]; + __IO uint16_t HCONR; + uint8_t RESERVED11[2]; + __IO uint16_t HCUPR; + uint8_t RESERVED12[2]; + __IO uint16_t HCDOR; + uint8_t RESERVED13[2]; + __IO uint16_t ICONR; + uint8_t RESERVED14[2]; + __IO uint16_t ECONR; + uint8_t RESERVED15[2]; + __IO uint16_t FCONR; + uint8_t RESERVED16[2]; + __IO uint16_t STFLR; + uint8_t RESERVED17[34]; + __IO uint16_t BCONR1; + uint8_t RESERVED18[6]; + __IO uint16_t BCONR2; + uint8_t RESERVED19[6]; + __IO uint16_t BCONR3; + uint8_t RESERVED20[6]; + __IO uint16_t BCONR4; + uint8_t RESERVED21[38]; + __IO uint16_t CCONR1; + uint8_t RESERVED22[2]; + __IO uint16_t CCONR2; + uint8_t RESERVED23[2]; + __IO uint16_t CCONR3; + uint8_t RESERVED24[2]; + __IO uint16_t CCONR4; + uint8_t RESERVED25[2]; + __IO uint16_t CCONR5; + uint8_t RESERVED26[2]; + __IO uint16_t CCONR6; + uint8_t RESERVED27[2]; + __IO uint16_t CCONR7; + uint8_t RESERVED28[2]; + __IO uint16_t CCONR8; + uint8_t RESERVED29[34]; + __IO uint16_t PCONR1; + uint8_t RESERVED30[2]; + __IO uint16_t PCONR2; + uint8_t RESERVED31[2]; + __IO uint16_t PCONR3; + uint8_t RESERVED32[2]; + __IO uint16_t PCONR4; + uint8_t RESERVED33[2]; + __IO uint16_t PCONR5; + uint8_t RESERVED34[2]; + __IO uint16_t PCONR6; + uint8_t RESERVED35[2]; + __IO uint16_t PCONR7; + uint8_t RESERVED36[2]; + __IO uint16_t PCONR8; +} CM_TMRA_TypeDef; + +/** + * @brief TRNG + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t MR; + uint8_t RESERVED0[4]; + __I uint32_t DR0; + __I uint32_t DR1; +} CM_TRNG_TypeDef; + +/** + * @brief USART + */ +typedef struct { + __I uint32_t SR; + __IO uint16_t TDR; + __I uint16_t RDR; + __IO uint32_t BRR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t CR3; + __IO uint32_t PR; +} CM_USART_TypeDef; + +/** + * @brief USBFS + */ +typedef struct { + __IO uint32_t GVBUSCFG; + uint8_t RESERVED0[4]; + __IO uint32_t GAHBCFG; + __IO uint32_t GUSBCFG; + __IO uint32_t GRSTCTL; + __IO uint32_t GINTSTS; + __IO uint32_t GINTMSK; + __I uint32_t GRXSTSR; + __I uint32_t GRXSTSP; + __IO uint32_t GRXFSIZ; + __IO uint32_t HNPTXFSIZ; + __I uint32_t HNPTXSTS; + uint8_t RESERVED1[12]; + __IO uint32_t CID; + uint8_t RESERVED2[192]; + __IO uint32_t HPTXFSIZ; + __IO uint32_t DIEPTXF1; + __IO uint32_t DIEPTXF2; + __IO uint32_t DIEPTXF3; + __IO uint32_t DIEPTXF4; + __IO uint32_t DIEPTXF5; + uint8_t RESERVED3[744]; + __IO uint32_t HCFG; + __IO uint32_t HFIR; + __I uint32_t HFNUM; + uint8_t RESERVED4[4]; + __I uint32_t HPTXSTS; + __I uint32_t HAINT; + __IO uint32_t HAINTMSK; + uint8_t RESERVED5[36]; + __IO uint32_t HPRT; + uint8_t RESERVED6[188]; + __IO uint32_t HCCHAR0; + uint8_t RESERVED7[4]; + __IO uint32_t HCINT0; + __IO uint32_t HCINTMSK0; + __IO uint32_t HCTSIZ0; + __IO uint32_t HCDMA0; + uint8_t RESERVED8[8]; + __IO uint32_t HCCHAR1; + uint8_t RESERVED9[4]; + __IO uint32_t HCINT1; + __IO uint32_t HCINTMSK1; + __IO uint32_t HCTSIZ1; + __IO uint32_t HCDMA1; + uint8_t RESERVED10[8]; + __IO uint32_t HCCHAR2; + uint8_t RESERVED11[4]; + __IO uint32_t HCINT2; + __IO uint32_t HCINTMSK2; + __IO uint32_t HCTSIZ2; + __IO uint32_t HCDMA2; + uint8_t RESERVED12[8]; + __IO uint32_t HCCHAR3; + uint8_t RESERVED13[4]; + __IO uint32_t HCINT3; + __IO uint32_t HCINTMSK3; + __IO uint32_t HCTSIZ3; + __IO uint32_t HCDMA3; + uint8_t RESERVED14[8]; + __IO uint32_t HCCHAR4; + uint8_t RESERVED15[4]; + __IO uint32_t HCINT4; + __IO uint32_t HCINTMSK4; + __IO uint32_t HCTSIZ4; + __IO uint32_t HCDMA4; + uint8_t RESERVED16[8]; + __IO uint32_t HCCHAR5; + uint8_t RESERVED17[4]; + __IO uint32_t HCINT5; + __IO uint32_t HCINTMSK5; + __IO uint32_t HCTSIZ5; + __IO uint32_t HCDMA5; + uint8_t RESERVED18[8]; + __IO uint32_t HCCHAR6; + uint8_t RESERVED19[4]; + __IO uint32_t HCINT6; + __IO uint32_t HCINTMSK6; + __IO uint32_t HCTSIZ6; + __IO uint32_t HCDMA6; + uint8_t RESERVED20[8]; + __IO uint32_t HCCHAR7; + uint8_t RESERVED21[4]; + __IO uint32_t HCINT7; + __IO uint32_t HCINTMSK7; + __IO uint32_t HCTSIZ7; + __IO uint32_t HCDMA7; + uint8_t RESERVED22[8]; + __IO uint32_t HCCHAR8; + uint8_t RESERVED23[4]; + __IO uint32_t HCINT8; + __IO uint32_t HCINTMSK8; + __IO uint32_t HCTSIZ8; + __IO uint32_t HCDMA8; + uint8_t RESERVED24[8]; + __IO uint32_t HCCHAR9; + uint8_t RESERVED25[4]; + __IO uint32_t HCINT9; + __IO uint32_t HCINTMSK9; + __IO uint32_t HCTSIZ9; + __IO uint32_t HCDMA9; + uint8_t RESERVED26[8]; + __IO uint32_t HCCHAR10; + uint8_t RESERVED27[4]; + __IO uint32_t HCINT10; + __IO uint32_t HCINTMSK10; + __IO uint32_t HCTSIZ10; + __IO uint32_t HCDMA10; + uint8_t RESERVED28[8]; + __IO uint32_t HCCHAR11; + uint8_t RESERVED29[4]; + __IO uint32_t HCINT11; + __IO uint32_t HCINTMSK11; + __IO uint32_t HCTSIZ11; + __IO uint32_t HCDMA11; + uint8_t RESERVED30[392]; + __IO uint32_t DCFG; + __IO uint32_t DCTL; + __I uint32_t DSTS; + uint8_t RESERVED31[4]; + __IO uint32_t DIEPMSK; + __IO uint32_t DOEPMSK; + __IO uint32_t DAINT; + __IO uint32_t DAINTMSK; + uint8_t RESERVED32[20]; + __IO uint32_t DIEPEMPMSK; + uint8_t RESERVED33[200]; + __IO uint32_t DIEPCTL0; + uint8_t RESERVED34[4]; + __IO uint32_t DIEPINT0; + uint8_t RESERVED35[4]; + __IO uint32_t DIEPTSIZ0; + __IO uint32_t DIEPDMA0; + __I uint32_t DTXFSTS0; + uint8_t RESERVED36[4]; + __IO uint32_t DIEPCTL1; + uint8_t RESERVED37[4]; + __IO uint32_t DIEPINT1; + uint8_t RESERVED38[4]; + __IO uint32_t DIEPTSIZ1; + __IO uint32_t DIEPDMA1; + __I uint32_t DTXFSTS1; + uint8_t RESERVED39[4]; + __IO uint32_t DIEPCTL2; + uint8_t RESERVED40[4]; + __IO uint32_t DIEPINT2; + uint8_t RESERVED41[4]; + __IO uint32_t DIEPTSIZ2; + __IO uint32_t DIEPDMA2; + __I uint32_t DTXFSTS2; + uint8_t RESERVED42[4]; + __IO uint32_t DIEPCTL3; + uint8_t RESERVED43[4]; + __IO uint32_t DIEPINT3; + uint8_t RESERVED44[4]; + __IO uint32_t DIEPTSIZ3; + __IO uint32_t DIEPDMA3; + __I uint32_t DTXFSTS3; + uint8_t RESERVED45[4]; + __IO uint32_t DIEPCTL4; + uint8_t RESERVED46[4]; + __IO uint32_t DIEPINT4; + uint8_t RESERVED47[4]; + __IO uint32_t DIEPTSIZ4; + __IO uint32_t DIEPDMA4; + __I uint32_t DTXFSTS4; + uint8_t RESERVED48[4]; + __IO uint32_t DIEPCTL5; + uint8_t RESERVED49[4]; + __IO uint32_t DIEPINT5; + uint8_t RESERVED50[4]; + __IO uint32_t DIEPTSIZ5; + __IO uint32_t DIEPDMA5; + __I uint32_t DTXFSTS5; + uint8_t RESERVED51[324]; + __IO uint32_t DOEPCTL0; + uint8_t RESERVED52[4]; + __IO uint32_t DOEPINT0; + uint8_t RESERVED53[4]; + __IO uint32_t DOEPTSIZ0; + __IO uint32_t DOEPDMA0; + uint8_t RESERVED54[8]; + __IO uint32_t DOEPCTL1; + uint8_t RESERVED55[4]; + __IO uint32_t DOEPINT1; + uint8_t RESERVED56[4]; + __IO uint32_t DOEPTSIZ1; + __IO uint32_t DOEPDMA1; + uint8_t RESERVED57[8]; + __IO uint32_t DOEPCTL2; + uint8_t RESERVED58[4]; + __IO uint32_t DOEPINT2; + uint8_t RESERVED59[4]; + __IO uint32_t DOEPTSIZ2; + __IO uint32_t DOEPDMA2; + uint8_t RESERVED60[8]; + __IO uint32_t DOEPCTL3; + uint8_t RESERVED61[4]; + __IO uint32_t DOEPINT3; + uint8_t RESERVED62[4]; + __IO uint32_t DOEPTSIZ3; + __IO uint32_t DOEPDMA3; + uint8_t RESERVED63[8]; + __IO uint32_t DOEPCTL4; + uint8_t RESERVED64[4]; + __IO uint32_t DOEPINT4; + uint8_t RESERVED65[4]; + __IO uint32_t DOEPTSIZ4; + __IO uint32_t DOEPDMA4; + uint8_t RESERVED66[8]; + __IO uint32_t DOEPCTL5; + uint8_t RESERVED67[4]; + __IO uint32_t DOEPINT5; + uint8_t RESERVED68[4]; + __IO uint32_t DOEPTSIZ5; + __IO uint32_t DOEPDMA5; + uint8_t RESERVED69[584]; + __IO uint32_t GCCTL; +} CM_USBFS_TypeDef; + +/** + * @brief WDT + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t SR; + __IO uint32_t RR; +} CM_WDT_TypeDef; + +/******************************************************************************/ +/* Memory Base Address */ +/******************************************************************************/ +#define EFM_BASE (0x00000000UL) /*!< EFM base address in the alias region */ +#define SRAM_BASE (0x1FFF8000UL) /*!< SRAM base address in the alias region */ +#define QSPI_BASE (0x98000000UL) /*!< QSPI base address in the alias region */ + +/******************************************************************************/ +/* Device Specific Peripheral Base Address */ +/******************************************************************************/ +#define CM_ADC1_BASE (0x40040000UL) +#define CM_ADC2_BASE (0x40040400UL) +#define CM_AES_BASE (0x40008000UL) +#define CM_AOS_BASE (0x40010800UL) +#define CM_CAN_BASE (0x40070400UL) +#define CM_CMP1_BASE (0x4004A000UL) +#define CM_CMP2_BASE (0x4004A010UL) +#define CM_CMP3_BASE (0x4004A020UL) +#define CM_CMPCR_BASE (0x4004A000UL) +#define CM_CMU_BASE (0x40054000UL) +#define CM_CRC_BASE (0x40008C00UL) +#define CM_DBGC_BASE (0xE0042000UL) +#define CM_DCU1_BASE (0x40052000UL) +#define CM_DCU2_BASE (0x40052400UL) +#define CM_DCU3_BASE (0x40052800UL) +#define CM_DCU4_BASE (0x40052C00UL) +#define CM_DMA1_BASE (0x40053000UL) +#define CM_DMA2_BASE (0x40053400UL) +#define CM_EFM_BASE (0x40010400UL) +#define CM_EMB0_BASE (0x40017C00UL) +#define CM_EMB1_BASE (0x40017C20UL) +#define CM_EMB2_BASE (0x40017C40UL) +#define CM_EMB3_BASE (0x40017C60UL) +#define CM_FCM_BASE (0x40048400UL) +#define CM_GPIO_BASE (0x40053800UL) +#define CM_HASH_BASE (0x40008400UL) +#define CM_I2C1_BASE (0x4004E000UL) +#define CM_I2C2_BASE (0x4004E400UL) +#define CM_I2C3_BASE (0x4004E800UL) +#define CM_I2S1_BASE (0x4001E000UL) +#define CM_I2S2_BASE (0x4001E400UL) +#define CM_I2S3_BASE (0x40022000UL) +#define CM_I2S4_BASE (0x40022400UL) +#define CM_ICG_BASE (0x00000400UL) +#define CM_INTC_BASE (0x40051000UL) +#define CM_KEYSCAN_BASE (0x40050C00UL) +#define CM_MPU_BASE (0x40050000UL) +#define CM_OTS_BASE (0x4004A400UL) +#define CM_PERIC_BASE (0x40055400UL) +#define CM_PWC_BASE (0x40048000UL) +#define CM_QSPI_BASE (0x9C000000UL) +#define CM_RMU_BASE (0x400540C0UL) +#define CM_RTC_BASE (0x4004C000UL) +#define CM_SDIOC1_BASE (0x4006FC00UL) +#define CM_SDIOC2_BASE (0x40070000UL) +#define CM_SPI1_BASE (0x4001C000UL) +#define CM_SPI2_BASE (0x4001C400UL) +#define CM_SPI3_BASE (0x40020000UL) +#define CM_SPI4_BASE (0x40020400UL) +#define CM_SRAMC_BASE (0x40050800UL) +#define CM_SWDT_BASE (0x40049400UL) +#define CM_TMR0_1_BASE (0x40024000UL) +#define CM_TMR0_2_BASE (0x40024400UL) +#define CM_TMR4_1_BASE (0x40017000UL) +#define CM_TMR4_2_BASE (0x40024800UL) +#define CM_TMR4_3_BASE (0x40024C00UL) +#define CM_TMR4CR_BASE (0x40055408UL) +#define CM_TMR6_1_BASE (0x40018000UL) +#define CM_TMR6_2_BASE (0x40018400UL) +#define CM_TMR6_3_BASE (0x40018800UL) +#define CM_TMR6CR_BASE (0x40018000UL) +#define CM_TMRA_1_BASE (0x40015000UL) +#define CM_TMRA_2_BASE (0x40015400UL) +#define CM_TMRA_3_BASE (0x40015800UL) +#define CM_TMRA_4_BASE (0x40015C00UL) +#define CM_TMRA_5_BASE (0x40016000UL) +#define CM_TMRA_6_BASE (0x40016400UL) +#define CM_TRNG_BASE (0x40041000UL) +#define CM_USART1_BASE (0x4001D000UL) +#define CM_USART2_BASE (0x4001D400UL) +#define CM_USART3_BASE (0x40021000UL) +#define CM_USART4_BASE (0x40021400UL) +#define CM_USBFS_BASE (0x400C0000UL) +#define CM_WDT_BASE (0x40049000UL) + +/******************************************************************************/ +/* Device Specific Peripheral declaration & memory map */ +/******************************************************************************/ +#define CM_ADC1 ((CM_ADC_TypeDef *)CM_ADC1_BASE) +#define CM_ADC2 ((CM_ADC_TypeDef *)CM_ADC2_BASE) +#define CM_AES ((CM_AES_TypeDef *)CM_AES_BASE) +#define CM_AOS ((CM_AOS_TypeDef *)CM_AOS_BASE) +#define CM_CAN ((CM_CAN_TypeDef *)CM_CAN_BASE) +#define CM_CMP1 ((CM_CMP_TypeDef *)CM_CMP1_BASE) +#define CM_CMP2 ((CM_CMP_TypeDef *)CM_CMP2_BASE) +#define CM_CMP3 ((CM_CMP_TypeDef *)CM_CMP3_BASE) +#define CM_CMPCR ((CM_CMPCR_TypeDef *)CM_CMPCR_BASE) +#define CM_CMU ((CM_CMU_TypeDef *)CM_CMU_BASE) +#define CM_CRC ((CM_CRC_TypeDef *)CM_CRC_BASE) +#define CM_DBGC ((CM_DBGC_TypeDef *)CM_DBGC_BASE) +#define CM_DCU1 ((CM_DCU_TypeDef *)CM_DCU1_BASE) +#define CM_DCU2 ((CM_DCU_TypeDef *)CM_DCU2_BASE) +#define CM_DCU3 ((CM_DCU_TypeDef *)CM_DCU3_BASE) +#define CM_DCU4 ((CM_DCU_TypeDef *)CM_DCU4_BASE) +#define CM_DMA1 ((CM_DMA_TypeDef *)CM_DMA1_BASE) +#define CM_DMA2 ((CM_DMA_TypeDef *)CM_DMA2_BASE) +#define CM_EFM ((CM_EFM_TypeDef *)CM_EFM_BASE) +#define CM_EMB0 ((CM_EMB_TypeDef *)CM_EMB0_BASE) +#define CM_EMB1 ((CM_EMB_TypeDef *)CM_EMB1_BASE) +#define CM_EMB2 ((CM_EMB_TypeDef *)CM_EMB2_BASE) +#define CM_EMB3 ((CM_EMB_TypeDef *)CM_EMB3_BASE) +#define CM_FCM ((CM_FCM_TypeDef *)CM_FCM_BASE) +#define CM_GPIO ((CM_GPIO_TypeDef *)CM_GPIO_BASE) +#define CM_HASH ((CM_HASH_TypeDef *)CM_HASH_BASE) +#define CM_I2C1 ((CM_I2C_TypeDef *)CM_I2C1_BASE) +#define CM_I2C2 ((CM_I2C_TypeDef *)CM_I2C2_BASE) +#define CM_I2C3 ((CM_I2C_TypeDef *)CM_I2C3_BASE) +#define CM_I2S1 ((CM_I2S_TypeDef *)CM_I2S1_BASE) +#define CM_I2S2 ((CM_I2S_TypeDef *)CM_I2S2_BASE) +#define CM_I2S3 ((CM_I2S_TypeDef *)CM_I2S3_BASE) +#define CM_I2S4 ((CM_I2S_TypeDef *)CM_I2S4_BASE) +#define CM_ICG ((CM_ICG_TypeDef *)CM_ICG_BASE) +#define CM_INTC ((CM_INTC_TypeDef *)CM_INTC_BASE) +#define CM_KEYSCAN ((CM_KEYSCAN_TypeDef *)CM_KEYSCAN_BASE) +#define CM_MPU ((CM_MPU_TypeDef *)CM_MPU_BASE) +#define CM_OTS ((CM_OTS_TypeDef *)CM_OTS_BASE) +#define CM_PERIC ((CM_PERIC_TypeDef *)CM_PERIC_BASE) +#define CM_PWC ((CM_PWC_TypeDef *)CM_PWC_BASE) +#define CM_QSPI ((CM_QSPI_TypeDef *)CM_QSPI_BASE) +#define CM_RMU ((CM_RMU_TypeDef *)CM_RMU_BASE) +#define CM_RTC ((CM_RTC_TypeDef *)CM_RTC_BASE) +#define CM_SDIOC1 ((CM_SDIOC_TypeDef *)CM_SDIOC1_BASE) +#define CM_SDIOC2 ((CM_SDIOC_TypeDef *)CM_SDIOC2_BASE) +#define CM_SPI1 ((CM_SPI_TypeDef *)CM_SPI1_BASE) +#define CM_SPI2 ((CM_SPI_TypeDef *)CM_SPI2_BASE) +#define CM_SPI3 ((CM_SPI_TypeDef *)CM_SPI3_BASE) +#define CM_SPI4 ((CM_SPI_TypeDef *)CM_SPI4_BASE) +#define CM_SRAMC ((CM_SRAMC_TypeDef *)CM_SRAMC_BASE) +#define CM_SWDT ((CM_SWDT_TypeDef *)CM_SWDT_BASE) +#define CM_TMR0_1 ((CM_TMR0_TypeDef *)CM_TMR0_1_BASE) +#define CM_TMR0_2 ((CM_TMR0_TypeDef *)CM_TMR0_2_BASE) +#define CM_TMR4_1 ((CM_TMR4_TypeDef *)CM_TMR4_1_BASE) +#define CM_TMR4_2 ((CM_TMR4_TypeDef *)CM_TMR4_2_BASE) +#define CM_TMR4_3 ((CM_TMR4_TypeDef *)CM_TMR4_3_BASE) +#define CM_TMR4CR ((CM_TMR4CR_TypeDef *)CM_TMR4CR_BASE) +#define CM_TMR6_1 ((CM_TMR6_TypeDef *)CM_TMR6_1_BASE) +#define CM_TMR6_2 ((CM_TMR6_TypeDef *)CM_TMR6_2_BASE) +#define CM_TMR6_3 ((CM_TMR6_TypeDef *)CM_TMR6_3_BASE) +#define CM_TMR6CR ((CM_TMR6CR_TypeDef *)CM_TMR6CR_BASE) +#define CM_TMRA_1 ((CM_TMRA_TypeDef *)CM_TMRA_1_BASE) +#define CM_TMRA_2 ((CM_TMRA_TypeDef *)CM_TMRA_2_BASE) +#define CM_TMRA_3 ((CM_TMRA_TypeDef *)CM_TMRA_3_BASE) +#define CM_TMRA_4 ((CM_TMRA_TypeDef *)CM_TMRA_4_BASE) +#define CM_TMRA_5 ((CM_TMRA_TypeDef *)CM_TMRA_5_BASE) +#define CM_TMRA_6 ((CM_TMRA_TypeDef *)CM_TMRA_6_BASE) +#define CM_TRNG ((CM_TRNG_TypeDef *)CM_TRNG_BASE) +#define CM_USART1 ((CM_USART_TypeDef *)CM_USART1_BASE) +#define CM_USART2 ((CM_USART_TypeDef *)CM_USART2_BASE) +#define CM_USART3 ((CM_USART_TypeDef *)CM_USART3_BASE) +#define CM_USART4 ((CM_USART_TypeDef *)CM_USART4_BASE) +#define CM_USBFS ((CM_USBFS_TypeDef *)CM_USBFS_BASE) +#define CM_WDT ((CM_WDT_TypeDef *)CM_WDT_BASE) + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************* + Bit definition for Peripheral ADC +*******************************************************************************/ +/* Bit definition for ADC_STR register */ +#define ADC_STR_STRT (0x01U) + +/* Bit definition for ADC_CR0 register */ +#define ADC_CR0_MS_POS (0U) +#define ADC_CR0_MS (0x0003U) +#define ADC_CR0_MS_0 (0x0001U) +#define ADC_CR0_MS_1 (0x0002U) +#define ADC_CR0_ACCSEL_POS (4U) +#define ADC_CR0_ACCSEL (0x0030U) +#define ADC_CR0_ACCSEL_0 (0x0010U) +#define ADC_CR0_ACCSEL_1 (0x0020U) +#define ADC_CR0_CLREN_POS (6U) +#define ADC_CR0_CLREN (0x0040U) +#define ADC_CR0_DFMT_POS (7U) +#define ADC_CR0_DFMT (0x0080U) +#define ADC_CR0_AVCNT_POS (8U) +#define ADC_CR0_AVCNT (0x0700U) + +/* Bit definition for ADC_CR1 register */ +#define ADC_CR1_RSCHSEL_POS (2U) +#define ADC_CR1_RSCHSEL (0x0004U) + +/* Bit definition for ADC_TRGSR register */ +#define ADC_TRGSR_TRGSELA_POS (0U) +#define ADC_TRGSR_TRGSELA (0x0003U) +#define ADC_TRGSR_TRGSELA_0 (0x0001U) +#define ADC_TRGSR_TRGSELA_1 (0x0002U) +#define ADC_TRGSR_TRGENA_POS (7U) +#define ADC_TRGSR_TRGENA (0x0080U) +#define ADC_TRGSR_TRGSELB_POS (8U) +#define ADC_TRGSR_TRGSELB (0x0300U) +#define ADC_TRGSR_TRGSELB_0 (0x0100U) +#define ADC_TRGSR_TRGSELB_1 (0x0200U) +#define ADC_TRGSR_TRGENB_POS (15U) +#define ADC_TRGSR_TRGENB (0x8000U) + +/* Bit definition for ADC_CHSELRA register */ +#define ADC_CHSELRA_CHSELA (0x0001FFFFUL) + +/* Bit definition for ADC_CHSELRB register */ +#define ADC_CHSELRB_CHSELB (0x0001FFFFUL) + +/* Bit definition for ADC_AVCHSELR register */ +#define ADC_AVCHSELR_AVCHSEL (0x0001FFFFUL) + +/* Bit definition for ADC_SSTR0 register */ +#define ADC_SSTR0 (0xFFU) + +/* Bit definition for ADC_SSTR1 register */ +#define ADC_SSTR1 (0xFFU) + +/* Bit definition for ADC_SSTR2 register */ +#define ADC_SSTR2 (0xFFU) + +/* Bit definition for ADC_SSTR3 register */ +#define ADC_SSTR3 (0xFFU) + +/* Bit definition for ADC_SSTR4 register */ +#define ADC_SSTR4 (0xFFU) + +/* Bit definition for ADC_SSTR5 register */ +#define ADC_SSTR5 (0xFFU) + +/* Bit definition for ADC_SSTR6 register */ +#define ADC_SSTR6 (0xFFU) + +/* Bit definition for ADC_SSTR7 register */ +#define ADC_SSTR7 (0xFFU) + +/* Bit definition for ADC_SSTR8 register */ +#define ADC_SSTR8 (0xFFU) + +/* Bit definition for ADC_SSTR9 register */ +#define ADC_SSTR9 (0xFFU) + +/* Bit definition for ADC_SSTR10 register */ +#define ADC_SSTR10 (0xFFU) + +/* Bit definition for ADC_SSTR11 register */ +#define ADC_SSTR11 (0xFFU) + +/* Bit definition for ADC_SSTR12 register */ +#define ADC_SSTR12 (0xFFU) + +/* Bit definition for ADC_SSTR13 register */ +#define ADC_SSTR13 (0xFFU) + +/* Bit definition for ADC_SSTR14 register */ +#define ADC_SSTR14 (0xFFU) + +/* Bit definition for ADC_SSTR15 register */ +#define ADC_SSTR15 (0xFFU) + +/* Bit definition for ADC_SSTRL register */ +#define ADC_SSTRL (0xFFU) + +/* Bit definition for ADC_CHMUXR0 register */ +#define ADC_CHMUXR0_CH00MUX_POS (0U) +#define ADC_CHMUXR0_CH00MUX (0x000FU) +#define ADC_CHMUXR0_CH01MUX_POS (4U) +#define ADC_CHMUXR0_CH01MUX (0x00F0U) +#define ADC_CHMUXR0_CH02MUX_POS (8U) +#define ADC_CHMUXR0_CH02MUX (0x0F00U) +#define ADC_CHMUXR0_CH03MUX_POS (12U) +#define ADC_CHMUXR0_CH03MUX (0xF000U) + +/* Bit definition for ADC_CHMUXR1 register */ +#define ADC_CHMUXR1_CH04MUX_POS (0U) +#define ADC_CHMUXR1_CH04MUX (0x000FU) +#define ADC_CHMUXR1_CH05MUX_POS (4U) +#define ADC_CHMUXR1_CH05MUX (0x00F0U) +#define ADC_CHMUXR1_CH06MUX_POS (8U) +#define ADC_CHMUXR1_CH06MUX (0x0F00U) +#define ADC_CHMUXR1_CH07MUX_POS (12U) +#define ADC_CHMUXR1_CH07MUX (0xF000U) + +/* Bit definition for ADC_CHMUXR2 register */ +#define ADC_CHMUXR2_CH08MUX_POS (0U) +#define ADC_CHMUXR2_CH08MUX (0x000FU) +#define ADC_CHMUXR2_CH09MUX_POS (4U) +#define ADC_CHMUXR2_CH09MUX (0x00F0U) +#define ADC_CHMUXR2_CH10MUX_POS (8U) +#define ADC_CHMUXR2_CH10MUX (0x0F00U) +#define ADC_CHMUXR2_CH11MUX_POS (12U) +#define ADC_CHMUXR2_CH11MUX (0xF000U) + +/* Bit definition for ADC_CHMUXR3 register */ +#define ADC_CHMUXR3_CH12MUX_POS (0U) +#define ADC_CHMUXR3_CH12MUX (0x000FU) +#define ADC_CHMUXR3_CH13MUX_POS (4U) +#define ADC_CHMUXR3_CH13MUX (0x00F0U) +#define ADC_CHMUXR3_CH14MUX_POS (8U) +#define ADC_CHMUXR3_CH14MUX (0x0F00U) +#define ADC_CHMUXR3_CH15MUX_POS (12U) +#define ADC_CHMUXR3_CH15MUX (0xF000U) + +/* Bit definition for ADC_ISR register */ +#define ADC_ISR_EOCAF_POS (0U) +#define ADC_ISR_EOCAF (0x01U) +#define ADC_ISR_EOCBF_POS (1U) +#define ADC_ISR_EOCBF (0x02U) + +/* Bit definition for ADC_ICR register */ +#define ADC_ICR_EOCAIEN_POS (0U) +#define ADC_ICR_EOCAIEN (0x01U) +#define ADC_ICR_EOCBIEN_POS (1U) +#define ADC_ICR_EOCBIEN (0x02U) + +/* Bit definition for ADC_SYNCCR register */ +#define ADC_SYNCCR_SYNCEN_POS (0U) +#define ADC_SYNCCR_SYNCEN (0x0001U) +#define ADC_SYNCCR_SYNCMD_POS (4U) +#define ADC_SYNCCR_SYNCMD (0x0070U) +#define ADC_SYNCCR_SYNCDLY_POS (8U) +#define ADC_SYNCCR_SYNCDLY (0xFF00U) + +/* Bit definition for ADC_DR0 register */ +#define ADC_DR0 (0xFFFFU) + +/* Bit definition for ADC_DR1 register */ +#define ADC_DR1 (0xFFFFU) + +/* Bit definition for ADC_DR2 register */ +#define ADC_DR2 (0xFFFFU) + +/* Bit definition for ADC_DR3 register */ +#define ADC_DR3 (0xFFFFU) + +/* Bit definition for ADC_DR4 register */ +#define ADC_DR4 (0xFFFFU) + +/* Bit definition for ADC_DR5 register */ +#define ADC_DR5 (0xFFFFU) + +/* Bit definition for ADC_DR6 register */ +#define ADC_DR6 (0xFFFFU) + +/* Bit definition for ADC_DR7 register */ +#define ADC_DR7 (0xFFFFU) + +/* Bit definition for ADC_DR8 register */ +#define ADC_DR8 (0xFFFFU) + +/* Bit definition for ADC_DR9 register */ +#define ADC_DR9 (0xFFFFU) + +/* Bit definition for ADC_DR10 register */ +#define ADC_DR10 (0xFFFFU) + +/* Bit definition for ADC_DR11 register */ +#define ADC_DR11 (0xFFFFU) + +/* Bit definition for ADC_DR12 register */ +#define ADC_DR12 (0xFFFFU) + +/* Bit definition for ADC_DR13 register */ +#define ADC_DR13 (0xFFFFU) + +/* Bit definition for ADC_DR14 register */ +#define ADC_DR14 (0xFFFFU) + +/* Bit definition for ADC_DR15 register */ +#define ADC_DR15 (0xFFFFU) + +/* Bit definition for ADC_DR16 register */ +#define ADC_DR16 (0xFFFFU) + +/* Bit definition for ADC_AWDCR register */ +#define ADC_AWDCR_AWDEN_POS (0U) +#define ADC_AWDCR_AWDEN (0x0001U) +#define ADC_AWDCR_AWDMD_POS (4U) +#define ADC_AWDCR_AWDMD (0x0010U) +#define ADC_AWDCR_AWDSS_POS (6U) +#define ADC_AWDCR_AWDSS (0x00C0U) +#define ADC_AWDCR_AWDSS_0 (0x0040U) +#define ADC_AWDCR_AWDSS_1 (0x0080U) +#define ADC_AWDCR_AWDIEN_POS (8U) +#define ADC_AWDCR_AWDIEN (0x0100U) + +/* Bit definition for ADC_AWDDR0 register */ +#define ADC_AWDDR0 (0xFFFFU) + +/* Bit definition for ADC_AWDDR1 register */ +#define ADC_AWDDR1 (0xFFFFU) + +/* Bit definition for ADC_AWDCHSR register */ +#define ADC_AWDCHSR_AWDCH (0x0001FFFFUL) + +/* Bit definition for ADC_AWDSR register */ +#define ADC_AWDSR_AWDF (0x0001FFFFUL) + +/* Bit definition for ADC_PGACR register */ +#define ADC_PGACR_PGACTL (0x000FU) + +/* Bit definition for ADC_PGAGSR register */ +#define ADC_PGAGSR_GAIN (0x000FU) + +/* Bit definition for ADC_PGAINSR0 register */ +#define ADC_PGAINSR0_PGAINSEL (0x01FFU) +#define ADC_PGAINSR0_PGAINSEL_0 (0x0001U) +#define ADC_PGAINSR0_PGAINSEL_1 (0x0002U) +#define ADC_PGAINSR0_PGAINSEL_2 (0x0004U) +#define ADC_PGAINSR0_PGAINSEL_3 (0x0008U) +#define ADC_PGAINSR0_PGAINSEL_4 (0x0010U) +#define ADC_PGAINSR0_PGAINSEL_5 (0x0020U) +#define ADC_PGAINSR0_PGAINSEL_6 (0x0040U) +#define ADC_PGAINSR0_PGAINSEL_7 (0x0080U) +#define ADC_PGAINSR0_PGAINSEL_8 (0x0100U) + +/* Bit definition for ADC_PGAINSR1 register */ +#define ADC_PGAINSR1_PGAVSSEN (0x0001U) + +/******************************************************************************* + Bit definition for Peripheral AES +*******************************************************************************/ +/* Bit definition for AES_CR register */ +#define AES_CR_START_POS (0U) +#define AES_CR_START (0x00000001UL) +#define AES_CR_MODE_POS (1U) +#define AES_CR_MODE (0x00000002UL) + +/* Bit definition for AES_DR0 register */ +#define AES_DR0 (0xFFFFFFFFUL) + +/* Bit definition for AES_DR1 register */ +#define AES_DR1 (0xFFFFFFFFUL) + +/* Bit definition for AES_DR2 register */ +#define AES_DR2 (0xFFFFFFFFUL) + +/* Bit definition for AES_DR3 register */ +#define AES_DR3 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR0 register */ +#define AES_KR0 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR1 register */ +#define AES_KR1 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR2 register */ +#define AES_KR2 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR3 register */ +#define AES_KR3 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral AOS +*******************************************************************************/ +/* Bit definition for AOS_INTSFTTRG register */ +#define AOS_INTSFTTRG_STRG (0x00000001UL) + +/* Bit definition for AOS_DCU_TRGSEL register */ +#define AOS_DCU_TRGSEL_TRGSEL_POS (0U) +#define AOS_DCU_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DCU_TRGSEL_COMEN_POS (30U) +#define AOS_DCU_TRGSEL_COMEN (0xC0000000UL) +#define AOS_DCU_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_DCU_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_DMA1_TRGSEL register */ +#define AOS_DMA1_TRGSEL_TRGSEL_POS (0U) +#define AOS_DMA1_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DMA1_TRGSEL_COMEN_POS (30U) +#define AOS_DMA1_TRGSEL_COMEN (0xC0000000UL) +#define AOS_DMA1_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_DMA1_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_DMA2_TRGSEL register */ +#define AOS_DMA2_TRGSEL_TRGSEL_POS (0U) +#define AOS_DMA2_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DMA2_TRGSEL_COMEN_POS (30U) +#define AOS_DMA2_TRGSEL_COMEN (0xC0000000UL) +#define AOS_DMA2_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_DMA2_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_DMA_RC_TRGSEL register */ +#define AOS_DMA_RC_TRGSEL_TRGSEL_POS (0U) +#define AOS_DMA_RC_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DMA_RC_TRGSEL_COMEN_POS (30U) +#define AOS_DMA_RC_TRGSEL_COMEN (0xC0000000UL) +#define AOS_DMA_RC_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_DMA_RC_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_TMR6_TRGSEL register */ +#define AOS_TMR6_TRGSEL_TRGSEL_POS (0U) +#define AOS_TMR6_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_TMR6_TRGSEL_COMEN_POS (30U) +#define AOS_TMR6_TRGSEL_COMEN (0xC0000000UL) +#define AOS_TMR6_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_TMR6_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_TMR0_TRGSEL register */ +#define AOS_TMR0_TRGSEL_TRGSEL_POS (0U) +#define AOS_TMR0_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_TMR0_TRGSEL_COMEN_POS (30U) +#define AOS_TMR0_TRGSEL_COMEN (0xC0000000UL) +#define AOS_TMR0_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_TMR0_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_PEVNT_TRGSEL register */ +#define AOS_PEVNT_TRGSEL_TRGSEL_POS (0U) +#define AOS_PEVNT_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_PEVNT_TRGSEL_COMEN_POS (30U) +#define AOS_PEVNT_TRGSEL_COMEN (0xC0000000UL) +#define AOS_PEVNT_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_PEVNT_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_TMRA_TRGSEL register */ +#define AOS_TMRA_TRGSEL_TRGSEL_POS (0U) +#define AOS_TMRA_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_TMRA_TRGSEL_COMEN_POS (30U) +#define AOS_TMRA_TRGSEL_COMEN (0xC0000000UL) +#define AOS_TMRA_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_TMRA_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_OTS_TRGSEL register */ +#define AOS_OTS_TRGSEL_TRGSEL_POS (0U) +#define AOS_OTS_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_OTS_TRGSEL_COMEN_POS (30U) +#define AOS_OTS_TRGSEL_COMEN (0xC0000000UL) +#define AOS_OTS_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_OTS_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_ADC1_TRGSEL register */ +#define AOS_ADC1_TRGSEL_TRGSEL_POS (0U) +#define AOS_ADC1_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_ADC1_TRGSEL_COMEN_POS (30U) +#define AOS_ADC1_TRGSEL_COMEN (0xC0000000UL) +#define AOS_ADC1_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_ADC1_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_ADC2_TRGSEL register */ +#define AOS_ADC2_TRGSEL_TRGSEL_POS (0U) +#define AOS_ADC2_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_ADC2_TRGSEL_COMEN_POS (30U) +#define AOS_ADC2_TRGSEL_COMEN (0xC0000000UL) +#define AOS_ADC2_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_ADC2_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_COMTRG1 register */ +#define AOS_COMTRG1_COMTRG (0x000001FFUL) + +/* Bit definition for AOS_COMTRG2 register */ +#define AOS_COMTRG2_COMTRG (0x000001FFUL) + +/* Bit definition for AOS_PEVNTDIRR register */ +#define AOS_PEVNTDIRR_PDIR (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTIDR register */ +#define AOS_PEVNTIDR_PIN (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTODR register */ +#define AOS_PEVNTODR_POUT (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTORR register */ +#define AOS_PEVNTORR_POR (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTOSR register */ +#define AOS_PEVNTOSR_POS (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTRISR register */ +#define AOS_PEVNTRISR_RIS (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTFALR register */ +#define AOS_PEVNTFALR_FAL (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTNFCR register */ +#define AOS_PEVNTNFCR_NFEN1_POS (0U) +#define AOS_PEVNTNFCR_NFEN1 (0x00000001UL) +#define AOS_PEVNTNFCR_DIVS1_POS (1U) +#define AOS_PEVNTNFCR_DIVS1 (0x00000006UL) +#define AOS_PEVNTNFCR_NFEN2_POS (8U) +#define AOS_PEVNTNFCR_NFEN2 (0x00000100UL) +#define AOS_PEVNTNFCR_DIVS2_POS (9U) +#define AOS_PEVNTNFCR_DIVS2 (0x00000600UL) +#define AOS_PEVNTNFCR_NFEN3_POS (16U) +#define AOS_PEVNTNFCR_NFEN3 (0x00010000UL) +#define AOS_PEVNTNFCR_DIVS3_POS (17U) +#define AOS_PEVNTNFCR_DIVS3 (0x00060000UL) +#define AOS_PEVNTNFCR_NFEN4_POS (24U) +#define AOS_PEVNTNFCR_NFEN4 (0x01000000UL) +#define AOS_PEVNTNFCR_DIVS4_POS (25U) +#define AOS_PEVNTNFCR_DIVS4 (0x06000000UL) + +/******************************************************************************* + Bit definition for Peripheral CAN +*******************************************************************************/ +/* Bit definition for CAN_RBUF register */ +#define CAN_RBUF (0xFFFFFFFFUL) + +/* Bit definition for CAN_TBUF register */ +#define CAN_TBUF (0xFFFFFFFFUL) + +/* Bit definition for CAN_CFG_STAT register */ +#define CAN_CFG_STAT_BUSOFF_POS (0U) +#define CAN_CFG_STAT_BUSOFF (0x01U) +#define CAN_CFG_STAT_TACTIVE_POS (1U) +#define CAN_CFG_STAT_TACTIVE (0x02U) +#define CAN_CFG_STAT_RACTIVE_POS (2U) +#define CAN_CFG_STAT_RACTIVE (0x04U) +#define CAN_CFG_STAT_TSSS_POS (3U) +#define CAN_CFG_STAT_TSSS (0x08U) +#define CAN_CFG_STAT_TPSS_POS (4U) +#define CAN_CFG_STAT_TPSS (0x10U) +#define CAN_CFG_STAT_LBMI_POS (5U) +#define CAN_CFG_STAT_LBMI (0x20U) +#define CAN_CFG_STAT_LBME_POS (6U) +#define CAN_CFG_STAT_LBME (0x40U) +#define CAN_CFG_STAT_RESET_POS (7U) +#define CAN_CFG_STAT_RESET (0x80U) + +/* Bit definition for CAN_TCMD register */ +#define CAN_TCMD_TSA_POS (0U) +#define CAN_TCMD_TSA (0x01U) +#define CAN_TCMD_TSALL_POS (1U) +#define CAN_TCMD_TSALL (0x02U) +#define CAN_TCMD_TSONE_POS (2U) +#define CAN_TCMD_TSONE (0x04U) +#define CAN_TCMD_TPA_POS (3U) +#define CAN_TCMD_TPA (0x08U) +#define CAN_TCMD_TPE_POS (4U) +#define CAN_TCMD_TPE (0x10U) +#define CAN_TCMD_LOM_POS (6U) +#define CAN_TCMD_LOM (0x40U) +#define CAN_TCMD_TBSEL_POS (7U) +#define CAN_TCMD_TBSEL (0x80U) + +/* Bit definition for CAN_TCTRL register */ +#define CAN_TCTRL_TSSTAT_POS (0U) +#define CAN_TCTRL_TSSTAT (0x03U) +#define CAN_TCTRL_TSSTAT_0 (0x01U) +#define CAN_TCTRL_TSSTAT_1 (0x02U) +#define CAN_TCTRL_TTTBM_POS (4U) +#define CAN_TCTRL_TTTBM (0x10U) +#define CAN_TCTRL_TSMODE_POS (5U) +#define CAN_TCTRL_TSMODE (0x20U) +#define CAN_TCTRL_TSNEXT_POS (6U) +#define CAN_TCTRL_TSNEXT (0x40U) + +/* Bit definition for CAN_RCTRL register */ +#define CAN_RCTRL_RSTAT_POS (0U) +#define CAN_RCTRL_RSTAT (0x03U) +#define CAN_RCTRL_RSTAT_0 (0x01U) +#define CAN_RCTRL_RSTAT_1 (0x02U) +#define CAN_RCTRL_RBALL_POS (3U) +#define CAN_RCTRL_RBALL (0x08U) +#define CAN_RCTRL_RREL_POS (4U) +#define CAN_RCTRL_RREL (0x10U) +#define CAN_RCTRL_ROV_POS (5U) +#define CAN_RCTRL_ROV (0x20U) +#define CAN_RCTRL_ROM_POS (6U) +#define CAN_RCTRL_ROM (0x40U) +#define CAN_RCTRL_SACK_POS (7U) +#define CAN_RCTRL_SACK (0x80U) + +/* Bit definition for CAN_RTIE register */ +#define CAN_RTIE_TSFF_POS (0U) +#define CAN_RTIE_TSFF (0x01U) +#define CAN_RTIE_EIE_POS (1U) +#define CAN_RTIE_EIE (0x02U) +#define CAN_RTIE_TSIE_POS (2U) +#define CAN_RTIE_TSIE (0x04U) +#define CAN_RTIE_TPIE_POS (3U) +#define CAN_RTIE_TPIE (0x08U) +#define CAN_RTIE_RAFIE_POS (4U) +#define CAN_RTIE_RAFIE (0x10U) +#define CAN_RTIE_RFIE_POS (5U) +#define CAN_RTIE_RFIE (0x20U) +#define CAN_RTIE_ROIE_POS (6U) +#define CAN_RTIE_ROIE (0x40U) +#define CAN_RTIE_RIE_POS (7U) +#define CAN_RTIE_RIE (0x80U) + +/* Bit definition for CAN_RTIF register */ +#define CAN_RTIF_AIF_POS (0U) +#define CAN_RTIF_AIF (0x01U) +#define CAN_RTIF_EIF_POS (1U) +#define CAN_RTIF_EIF (0x02U) +#define CAN_RTIF_TSIF_POS (2U) +#define CAN_RTIF_TSIF (0x04U) +#define CAN_RTIF_TPIF_POS (3U) +#define CAN_RTIF_TPIF (0x08U) +#define CAN_RTIF_RAFIF_POS (4U) +#define CAN_RTIF_RAFIF (0x10U) +#define CAN_RTIF_RFIF_POS (5U) +#define CAN_RTIF_RFIF (0x20U) +#define CAN_RTIF_ROIF_POS (6U) +#define CAN_RTIF_ROIF (0x40U) +#define CAN_RTIF_RIF_POS (7U) +#define CAN_RTIF_RIF (0x80U) + +/* Bit definition for CAN_ERRINT register */ +#define CAN_ERRINT_BEIF_POS (0U) +#define CAN_ERRINT_BEIF (0x01U) +#define CAN_ERRINT_BEIE_POS (1U) +#define CAN_ERRINT_BEIE (0x02U) +#define CAN_ERRINT_ALIF_POS (2U) +#define CAN_ERRINT_ALIF (0x04U) +#define CAN_ERRINT_ALIE_POS (3U) +#define CAN_ERRINT_ALIE (0x08U) +#define CAN_ERRINT_EPIF_POS (4U) +#define CAN_ERRINT_EPIF (0x10U) +#define CAN_ERRINT_EPIE_POS (5U) +#define CAN_ERRINT_EPIE (0x20U) +#define CAN_ERRINT_EPASS_POS (6U) +#define CAN_ERRINT_EPASS (0x40U) +#define CAN_ERRINT_EWARN_POS (7U) +#define CAN_ERRINT_EWARN (0x80U) + +/* Bit definition for CAN_LIMIT register */ +#define CAN_LIMIT_EWL_POS (0U) +#define CAN_LIMIT_EWL (0x0FU) +#define CAN_LIMIT_AFWL_POS (4U) +#define CAN_LIMIT_AFWL (0xF0U) + +/* Bit definition for CAN_SBT register */ +#define CAN_SBT_S_SEG_1_POS (0U) +#define CAN_SBT_S_SEG_1 (0x000000FFUL) +#define CAN_SBT_S_SEG_2_POS (8U) +#define CAN_SBT_S_SEG_2 (0x00007F00UL) +#define CAN_SBT_S_SJW_POS (16U) +#define CAN_SBT_S_SJW (0x007F0000UL) +#define CAN_SBT_S_PRESC_POS (24U) +#define CAN_SBT_S_PRESC (0xFF000000UL) + +/* Bit definition for CAN_EALCAP register */ +#define CAN_EALCAP_ALC_POS (0U) +#define CAN_EALCAP_ALC (0x1FU) +#define CAN_EALCAP_KOER_POS (5U) +#define CAN_EALCAP_KOER (0xE0U) + +/* Bit definition for CAN_RECNT register */ +#define CAN_RECNT (0xFFU) + +/* Bit definition for CAN_TECNT register */ +#define CAN_TECNT (0xFFU) + +/* Bit definition for CAN_ACFCTRL register */ +#define CAN_ACFCTRL_ACFADR_POS (0U) +#define CAN_ACFCTRL_ACFADR (0x0FU) +#define CAN_ACFCTRL_SELMASK_POS (5U) +#define CAN_ACFCTRL_SELMASK (0x20U) + +/* Bit definition for CAN_ACFEN register */ +#define CAN_ACFEN_AE_1_POS (0U) +#define CAN_ACFEN_AE_1 (0x01U) +#define CAN_ACFEN_AE_2_POS (1U) +#define CAN_ACFEN_AE_2 (0x02U) +#define CAN_ACFEN_AE_3_POS (2U) +#define CAN_ACFEN_AE_3 (0x04U) +#define CAN_ACFEN_AE_4_POS (3U) +#define CAN_ACFEN_AE_4 (0x08U) +#define CAN_ACFEN_AE_5_POS (4U) +#define CAN_ACFEN_AE_5 (0x10U) +#define CAN_ACFEN_AE_6_POS (5U) +#define CAN_ACFEN_AE_6 (0x20U) +#define CAN_ACFEN_AE_7_POS (6U) +#define CAN_ACFEN_AE_7 (0x40U) +#define CAN_ACFEN_AE_8_POS (7U) +#define CAN_ACFEN_AE_8 (0x80U) + +/* Bit definition for CAN_ACF register */ +#define CAN_ACF_ACODEORAMASK_POS (0U) +#define CAN_ACF_ACODEORAMASK (0x1FFFFFFFUL) +#define CAN_ACF_AIDE_POS (29U) +#define CAN_ACF_AIDE (0x20000000UL) +#define CAN_ACF_AIDEE_POS (30U) +#define CAN_ACF_AIDEE (0x40000000UL) + +/* Bit definition for CAN_TBSLOT register */ +#define CAN_TBSLOT_TBPTR_POS (0U) +#define CAN_TBSLOT_TBPTR (0x3FU) +#define CAN_TBSLOT_TBF_POS (6U) +#define CAN_TBSLOT_TBF (0x40U) +#define CAN_TBSLOT_TBE_POS (7U) +#define CAN_TBSLOT_TBE (0x80U) + +/* Bit definition for CAN_TTCFG register */ +#define CAN_TTCFG_TTEN_POS (0U) +#define CAN_TTCFG_TTEN (0x01U) +#define CAN_TTCFG_T_PRESC_POS (1U) +#define CAN_TTCFG_T_PRESC (0x06U) +#define CAN_TTCFG_T_PRESC_0 (0x02U) +#define CAN_TTCFG_T_PRESC_1 (0x04U) +#define CAN_TTCFG_TTIF_POS (3U) +#define CAN_TTCFG_TTIF (0x08U) +#define CAN_TTCFG_TTIE_POS (4U) +#define CAN_TTCFG_TTIE (0x10U) +#define CAN_TTCFG_TEIF_POS (5U) +#define CAN_TTCFG_TEIF (0x20U) +#define CAN_TTCFG_WTIF_POS (6U) +#define CAN_TTCFG_WTIF (0x40U) +#define CAN_TTCFG_WTIE_POS (7U) +#define CAN_TTCFG_WTIE (0x80U) + +/* Bit definition for CAN_REF_MSG register */ +#define CAN_REF_MSG_REF_ID_POS (0U) +#define CAN_REF_MSG_REF_ID (0x1FFFFFFFUL) +#define CAN_REF_MSG_REF_IDE_POS (31U) +#define CAN_REF_MSG_REF_IDE (0x80000000UL) + +/* Bit definition for CAN_TRG_CFG register */ +#define CAN_TRG_CFG_TTPTR_POS (0U) +#define CAN_TRG_CFG_TTPTR (0x003FU) +#define CAN_TRG_CFG_TTYPE_POS (8U) +#define CAN_TRG_CFG_TTYPE (0x0700U) +#define CAN_TRG_CFG_TTYPE_0 (0x0100U) +#define CAN_TRG_CFG_TTYPE_1 (0x0200U) +#define CAN_TRG_CFG_TTYPE_2 (0x0400U) +#define CAN_TRG_CFG_TEW_POS (12U) +#define CAN_TRG_CFG_TEW (0xF000U) + +/* Bit definition for CAN_TT_TRIG register */ +#define CAN_TT_TRIG (0xFFFFU) + +/* Bit definition for CAN_TT_WTRIG register */ +#define CAN_TT_WTRIG (0xFFFFU) + +/******************************************************************************* + Bit definition for Peripheral CMP +*******************************************************************************/ +/* Bit definition for CMP_CTRL register */ +#define CMP_CTRL_FLTSL_POS (0U) +#define CMP_CTRL_FLTSL (0x0007U) +#define CMP_CTRL_EDGSL_POS (5U) +#define CMP_CTRL_EDGSL (0x0060U) +#define CMP_CTRL_EDGSL_0 (0x0020U) +#define CMP_CTRL_EDGSL_1 (0x0040U) +#define CMP_CTRL_IEN_POS (7U) +#define CMP_CTRL_IEN (0x0080U) +#define CMP_CTRL_CVSEN_POS (8U) +#define CMP_CTRL_CVSEN (0x0100U) +#define CMP_CTRL_OUTEN_POS (12U) +#define CMP_CTRL_OUTEN (0x1000U) +#define CMP_CTRL_INV_POS (13U) +#define CMP_CTRL_INV (0x2000U) +#define CMP_CTRL_CMPOE_POS (14U) +#define CMP_CTRL_CMPOE (0x4000U) +#define CMP_CTRL_CMPON_POS (15U) +#define CMP_CTRL_CMPON (0x8000U) + +/* Bit definition for CMP_VLTSEL register */ +#define CMP_VLTSEL_RVSL_POS (0U) +#define CMP_VLTSEL_RVSL (0x000FU) +#define CMP_VLTSEL_RVSL_0 (0x0001U) +#define CMP_VLTSEL_RVSL_1 (0x0002U) +#define CMP_VLTSEL_RVSL_2 (0x0004U) +#define CMP_VLTSEL_RVSL_3 (0x0008U) +#define CMP_VLTSEL_CVSL_POS (8U) +#define CMP_VLTSEL_CVSL (0x0F00U) +#define CMP_VLTSEL_CVSL_0 (0x0100U) +#define CMP_VLTSEL_CVSL_1 (0x0200U) +#define CMP_VLTSEL_CVSL_2 (0x0400U) +#define CMP_VLTSEL_CVSL_3 (0x0800U) +#define CMP_VLTSEL_C4SL_POS (12U) +#define CMP_VLTSEL_C4SL (0x7000U) +#define CMP_VLTSEL_C4SL_0 (0x1000U) +#define CMP_VLTSEL_C4SL_1 (0x2000U) +#define CMP_VLTSEL_C4SL_2 (0x4000U) + +/* Bit definition for CMP_OUTMON register */ +#define CMP_OUTMON_OMON_POS (0U) +#define CMP_OUTMON_OMON (0x0001U) +#define CMP_OUTMON_CVST_POS (8U) +#define CMP_OUTMON_CVST (0x0F00U) + +/* Bit definition for CMP_CVSSTB register */ +#define CMP_CVSSTB_STB (0x000FU) + +/* Bit definition for CMP_CVSPRD register */ +#define CMP_CVSPRD_PRD (0x00FFU) + +/******************************************************************************* + Bit definition for Peripheral CMPCR +*******************************************************************************/ +/* Bit definition for CMPCR_DADR1 register */ +#define CMPCR_DADR1_DATA (0x00FFU) + +/* Bit definition for CMPCR_DADR2 register */ +#define CMPCR_DADR2_DATA (0x00FFU) + +/* Bit definition for CMPCR_DACR register */ +#define CMPCR_DACR_DA1EN_POS (0U) +#define CMPCR_DACR_DA1EN (0x0001U) +#define CMPCR_DACR_DA2EN_POS (1U) +#define CMPCR_DACR_DA2EN (0x0002U) + +/* Bit definition for CMPCR_RVADC register */ +#define CMPCR_RVADC_DA1SW_POS (0U) +#define CMPCR_RVADC_DA1SW (0x0001U) +#define CMPCR_RVADC_DA2SW_POS (1U) +#define CMPCR_RVADC_DA2SW (0x0002U) +#define CMPCR_RVADC_VREFSW_POS (4U) +#define CMPCR_RVADC_VREFSW (0x0010U) +#define CMPCR_RVADC_WPRT_POS (8U) +#define CMPCR_RVADC_WPRT (0xFF00U) + +/******************************************************************************* + Bit definition for Peripheral CMU +*******************************************************************************/ +/* Bit definition for CMU_PERICKSEL register */ +#define CMU_PERICKSEL_PERICKSEL (0x000FU) + +/* Bit definition for CMU_I2SCKSEL register */ +#define CMU_I2SCKSEL_I2S1CKSEL_POS (0U) +#define CMU_I2SCKSEL_I2S1CKSEL (0x000FU) +#define CMU_I2SCKSEL_I2S2CKSEL_POS (4U) +#define CMU_I2SCKSEL_I2S2CKSEL (0x00F0U) +#define CMU_I2SCKSEL_I2S3CKSEL_POS (8U) +#define CMU_I2SCKSEL_I2S3CKSEL (0x0F00U) +#define CMU_I2SCKSEL_I2S4CKSEL_POS (12U) +#define CMU_I2SCKSEL_I2S4CKSEL (0xF000U) + +/* Bit definition for CMU_SCFGR register */ +#define CMU_SCFGR_PCLK0S_POS (0U) +#define CMU_SCFGR_PCLK0S (0x00000007UL) +#define CMU_SCFGR_PCLK1S_POS (4U) +#define CMU_SCFGR_PCLK1S (0x00000070UL) +#define CMU_SCFGR_PCLK2S_POS (8U) +#define CMU_SCFGR_PCLK2S (0x00000700UL) +#define CMU_SCFGR_PCLK3S_POS (12U) +#define CMU_SCFGR_PCLK3S (0x00007000UL) +#define CMU_SCFGR_PCLK4S_POS (16U) +#define CMU_SCFGR_PCLK4S (0x00070000UL) +#define CMU_SCFGR_EXCKS_POS (20U) +#define CMU_SCFGR_EXCKS (0x00700000UL) +#define CMU_SCFGR_HCLKS_POS (24U) +#define CMU_SCFGR_HCLKS (0x07000000UL) + +/* Bit definition for CMU_USBCKCFGR register */ +#define CMU_USBCKCFGR_USBCKS_POS (4U) +#define CMU_USBCKCFGR_USBCKS (0xF0U) + +/* Bit definition for CMU_CKSWR register */ +#define CMU_CKSWR_CKSW (0x07U) + +/* Bit definition for CMU_PLLCR register */ +#define CMU_PLLCR_MPLLOFF (0x01U) + +/* Bit definition for CMU_UPLLCR register */ +#define CMU_UPLLCR_UPLLOFF (0x01U) + +/* Bit definition for CMU_XTALCR register */ +#define CMU_XTALCR_XTALSTP (0x01U) + +/* Bit definition for CMU_HRCCR register */ +#define CMU_HRCCR_HRCSTP (0x01U) + +/* Bit definition for CMU_MRCCR register */ +#define CMU_MRCCR_MRCSTP (0x01U) + +/* Bit definition for CMU_OSCSTBSR register */ +#define CMU_OSCSTBSR_HRCSTBF_POS (0U) +#define CMU_OSCSTBSR_HRCSTBF (0x01U) +#define CMU_OSCSTBSR_XTALSTBF_POS (3U) +#define CMU_OSCSTBSR_XTALSTBF (0x08U) +#define CMU_OSCSTBSR_MPLLSTBF_POS (5U) +#define CMU_OSCSTBSR_MPLLSTBF (0x20U) +#define CMU_OSCSTBSR_UPLLSTBF_POS (6U) +#define CMU_OSCSTBSR_UPLLSTBF (0x40U) + +/* Bit definition for CMU_MCOCFGR register */ +#define CMU_MCOCFGR_MCOSEL_POS (0U) +#define CMU_MCOCFGR_MCOSEL (0x0FU) +#define CMU_MCOCFGR_MCODIV_POS (4U) +#define CMU_MCOCFGR_MCODIV (0x70U) +#define CMU_MCOCFGR_MCOEN_POS (7U) +#define CMU_MCOCFGR_MCOEN (0x80U) + +/* Bit definition for CMU_TPIUCKCFGR register */ +#define CMU_TPIUCKCFGR_TPIUCKS_POS (0U) +#define CMU_TPIUCKCFGR_TPIUCKS (0x03U) +#define CMU_TPIUCKCFGR_TPIUCKS_0 (0x01U) +#define CMU_TPIUCKCFGR_TPIUCKS_1 (0x02U) +#define CMU_TPIUCKCFGR_TPIUCKOE_POS (7U) +#define CMU_TPIUCKCFGR_TPIUCKOE (0x80U) + +/* Bit definition for CMU_XTALSTDCR register */ +#define CMU_XTALSTDCR_XTALSTDIE_POS (0U) +#define CMU_XTALSTDCR_XTALSTDIE (0x01U) +#define CMU_XTALSTDCR_XTALSTDRE_POS (1U) +#define CMU_XTALSTDCR_XTALSTDRE (0x02U) +#define CMU_XTALSTDCR_XTALSTDRIS_POS (2U) +#define CMU_XTALSTDCR_XTALSTDRIS (0x04U) +#define CMU_XTALSTDCR_XTALSTDE_POS (7U) +#define CMU_XTALSTDCR_XTALSTDE (0x80U) + +/* Bit definition for CMU_XTALSTDSR register */ +#define CMU_XTALSTDSR_XTALSTDF (0x01U) + +/* Bit definition for CMU_MRCTRM register */ +#define CMU_MRCTRM (0xFFU) + +/* Bit definition for CMU_HRCTRM register */ +#define CMU_HRCTRM (0xFFU) + +/* Bit definition for CMU_XTALSTBCR register */ +#define CMU_XTALSTBCR_XTALSTB (0x0FU) +#define CMU_XTALSTBCR_XTALSTB_0 (0x01U) +#define CMU_XTALSTBCR_XTALSTB_1 (0x02U) +#define CMU_XTALSTBCR_XTALSTB_2 (0x04U) +#define CMU_XTALSTBCR_XTALSTB_3 (0x08U) + +/* Bit definition for CMU_PLLCFGR register */ +#define CMU_PLLCFGR_MPLLM_POS (0U) +#define CMU_PLLCFGR_MPLLM (0x0000001FUL) +#define CMU_PLLCFGR_PLLSRC_POS (7U) +#define CMU_PLLCFGR_PLLSRC (0x00000080UL) +#define CMU_PLLCFGR_MPLLN_POS (8U) +#define CMU_PLLCFGR_MPLLN (0x0001FF00UL) +#define CMU_PLLCFGR_MPLLR_POS (20U) +#define CMU_PLLCFGR_MPLLR (0x00F00000UL) +#define CMU_PLLCFGR_MPLLQ_POS (24U) +#define CMU_PLLCFGR_MPLLQ (0x0F000000UL) +#define CMU_PLLCFGR_MPLLP_POS (28U) +#define CMU_PLLCFGR_MPLLP (0xF0000000UL) + +/* Bit definition for CMU_UPLLCFGR register */ +#define CMU_UPLLCFGR_UPLLM_POS (0U) +#define CMU_UPLLCFGR_UPLLM (0x0000001FUL) +#define CMU_UPLLCFGR_UPLLN_POS (8U) +#define CMU_UPLLCFGR_UPLLN (0x0001FF00UL) +#define CMU_UPLLCFGR_UPLLR_POS (20U) +#define CMU_UPLLCFGR_UPLLR (0x00F00000UL) +#define CMU_UPLLCFGR_UPLLQ_POS (24U) +#define CMU_UPLLCFGR_UPLLQ (0x0F000000UL) +#define CMU_UPLLCFGR_UPLLP_POS (28U) +#define CMU_UPLLCFGR_UPLLP (0xF0000000UL) + +/* Bit definition for CMU_XTALCFGR register */ +#define CMU_XTALCFGR_XTALDRV_POS (4U) +#define CMU_XTALCFGR_XTALDRV (0x30U) +#define CMU_XTALCFGR_XTALDRV_0 (0x10U) +#define CMU_XTALCFGR_XTALDRV_1 (0x20U) +#define CMU_XTALCFGR_XTALMS_POS (6U) +#define CMU_XTALCFGR_XTALMS (0x40U) +#define CMU_XTALCFGR_SUPDRV_POS (7U) +#define CMU_XTALCFGR_SUPDRV (0x80U) + +/* Bit definition for CMU_XTAL32CR register */ +#define CMU_XTAL32CR_XTAL32STP (0x01U) + +/* Bit definition for CMU_XTAL32CFGR register */ +#define CMU_XTAL32CFGR_XTAL32DRV (0x07U) +#define CMU_XTAL32CFGR_XTAL32DRV_0 (0x01U) +#define CMU_XTAL32CFGR_XTAL32DRV_1 (0x02U) +#define CMU_XTAL32CFGR_XTAL32DRV_2 (0x04U) + +/* Bit definition for CMU_XTAL32NFR register */ +#define CMU_XTAL32NFR_XTAL32NF (0x03U) +#define CMU_XTAL32NFR_XTAL32NF_0 (0x01U) +#define CMU_XTAL32NFR_XTAL32NF_1 (0x02U) + +/* Bit definition for CMU_LRCCR register */ +#define CMU_LRCCR_LRCSTP (0x01U) + +/* Bit definition for CMU_LRCTRM register */ +#define CMU_LRCTRM (0xFFU) + +/******************************************************************************* + Bit definition for Peripheral CRC +*******************************************************************************/ +/* Bit definition for CRC_CR register */ +#define CRC_CR_CR_POS (1U) +#define CRC_CR_CR (0x00000002UL) +#define CRC_CR_REFIN_POS (2U) +#define CRC_CR_REFIN (0x00000004UL) +#define CRC_CR_REFOUT_POS (3U) +#define CRC_CR_REFOUT (0x00000008UL) +#define CRC_CR_XOROUT_POS (4U) +#define CRC_CR_XOROUT (0x00000010UL) + +/* Bit definition for CRC_RESLT register */ +#define CRC_RESLT_CRC_REG_POS (0U) +#define CRC_RESLT_CRC_REG (0x0000FFFFUL) +#define CRC_RESLT_CRCFLAG_16_POS (16U) +#define CRC_RESLT_CRCFLAG_16 (0x00010000UL) + +/* Bit definition for CRC_FLG register */ +#define CRC_FLG_CRCFLAG_32 (0x00000001UL) + +/* Bit definition for CRC_DAT0 register */ +#define CRC_DAT0 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT1 register */ +#define CRC_DAT1 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT2 register */ +#define CRC_DAT2 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT3 register */ +#define CRC_DAT3 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT4 register */ +#define CRC_DAT4 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT5 register */ +#define CRC_DAT5 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT6 register */ +#define CRC_DAT6 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT7 register */ +#define CRC_DAT7 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT8 register */ +#define CRC_DAT8 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT9 register */ +#define CRC_DAT9 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT10 register */ +#define CRC_DAT10 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT11 register */ +#define CRC_DAT11 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT12 register */ +#define CRC_DAT12 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT13 register */ +#define CRC_DAT13 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT14 register */ +#define CRC_DAT14 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT15 register */ +#define CRC_DAT15 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT16 register */ +#define CRC_DAT16 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT17 register */ +#define CRC_DAT17 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT18 register */ +#define CRC_DAT18 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT19 register */ +#define CRC_DAT19 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT20 register */ +#define CRC_DAT20 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT21 register */ +#define CRC_DAT21 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT22 register */ +#define CRC_DAT22 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT23 register */ +#define CRC_DAT23 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT24 register */ +#define CRC_DAT24 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT25 register */ +#define CRC_DAT25 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT26 register */ +#define CRC_DAT26 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT27 register */ +#define CRC_DAT27 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT28 register */ +#define CRC_DAT28 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT29 register */ +#define CRC_DAT29 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT30 register */ +#define CRC_DAT30 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT31 register */ +#define CRC_DAT31 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral DBGC +*******************************************************************************/ +/* Bit definition for DBGC_AUTHID0 register */ +#define DBGC_AUTHID0 (0xFFFFFFFFUL) + +/* Bit definition for DBGC_AUTHID1 register */ +#define DBGC_AUTHID1 (0xFFFFFFFFUL) + +/* Bit definition for DBGC_AUTHID2 register */ +#define DBGC_AUTHID2 (0xFFFFFFFFUL) + +/* Bit definition for DBGC_MCUSTAT register */ +#define DBGC_MCUSTAT_AUTHFG_POS (0U) +#define DBGC_MCUSTAT_AUTHFG (0x00000001UL) +#define DBGC_MCUSTAT_PRTLV1_POS (2U) +#define DBGC_MCUSTAT_PRTLV1 (0x00000004UL) +#define DBGC_MCUSTAT_PRTLV2_POS (3U) +#define DBGC_MCUSTAT_PRTLV2 (0x00000008UL) + +/* Bit definition for DBGC_FERSCTL register */ +#define DBGC_FERSCTL_ERASEREQ_POS (0U) +#define DBGC_FERSCTL_ERASEREQ (0x00000001UL) +#define DBGC_FERSCTL_ERASEACK_POS (1U) +#define DBGC_FERSCTL_ERASEACK (0x00000002UL) +#define DBGC_FERSCTL_ERASEERR_POS (2U) +#define DBGC_FERSCTL_ERASEERR (0x00000004UL) + +/* Bit definition for DBGC_MCUDBGSTAT register */ +#define DBGC_MCUDBGSTAT_CDBGPWRUPREQ_POS (0U) +#define DBGC_MCUDBGSTAT_CDBGPWRUPREQ (0x00000001UL) +#define DBGC_MCUDBGSTAT_CDBGPWRUPACK_POS (1U) +#define DBGC_MCUDBGSTAT_CDBGPWRUPACK (0x00000002UL) + +/* Bit definition for DBGC_MCUSTPCTL register */ +#define DBGC_MCUSTPCTL_SWDTSTP_POS (0U) +#define DBGC_MCUSTPCTL_SWDTSTP (0x00000001UL) +#define DBGC_MCUSTPCTL_WDTSTP_POS (1U) +#define DBGC_MCUSTPCTL_WDTSTP (0x00000002UL) +#define DBGC_MCUSTPCTL_RTCSTP_POS (2U) +#define DBGC_MCUSTPCTL_RTCSTP (0x00000004UL) +#define DBGC_MCUSTPCTL_TMR01STP_POS (14U) +#define DBGC_MCUSTPCTL_TMR01STP (0x00004000UL) +#define DBGC_MCUSTPCTL_TMR02STP_POS (15U) +#define DBGC_MCUSTPCTL_TMR02STP (0x00008000UL) +#define DBGC_MCUSTPCTL_TMR41STP_POS (20U) +#define DBGC_MCUSTPCTL_TMR41STP (0x00100000UL) +#define DBGC_MCUSTPCTL_TMR42STP_POS (21U) +#define DBGC_MCUSTPCTL_TMR42STP (0x00200000UL) +#define DBGC_MCUSTPCTL_TMR43STP_POS (22U) +#define DBGC_MCUSTPCTL_TMR43STP (0x00400000UL) +#define DBGC_MCUSTPCTL_TM61STP_POS (23U) +#define DBGC_MCUSTPCTL_TM61STP (0x00800000UL) +#define DBGC_MCUSTPCTL_TM62STP_POS (24U) +#define DBGC_MCUSTPCTL_TM62STP (0x01000000UL) +#define DBGC_MCUSTPCTL_TMR63STP_POS (25U) +#define DBGC_MCUSTPCTL_TMR63STP (0x02000000UL) +#define DBGC_MCUSTPCTL_TMRA1STP_POS (26U) +#define DBGC_MCUSTPCTL_TMRA1STP (0x04000000UL) +#define DBGC_MCUSTPCTL_TMRA2STP_POS (27U) +#define DBGC_MCUSTPCTL_TMRA2STP (0x08000000UL) +#define DBGC_MCUSTPCTL_TMRA3STP_POS (28U) +#define DBGC_MCUSTPCTL_TMRA3STP (0x10000000UL) +#define DBGC_MCUSTPCTL_TMRA4STP_POS (29U) +#define DBGC_MCUSTPCTL_TMRA4STP (0x20000000UL) +#define DBGC_MCUSTPCTL_TMRA5STP_POS (30U) +#define DBGC_MCUSTPCTL_TMRA5STP (0x40000000UL) +#define DBGC_MCUSTPCTL_TMRA6STP_POS (31U) +#define DBGC_MCUSTPCTL_TMRA6STP (0x80000000UL) + +/* Bit definition for DBGC_MCUTRACECTL register */ +#define DBGC_MCUTRACECTL_TRACEMODE_POS (0U) +#define DBGC_MCUTRACECTL_TRACEMODE (0x00000003UL) +#define DBGC_MCUTRACECTL_TRACEMODE_0 (0x00000001UL) +#define DBGC_MCUTRACECTL_TRACEMODE_1 (0x00000002UL) +#define DBGC_MCUTRACECTL_TRACEIOEN_POS (2U) +#define DBGC_MCUTRACECTL_TRACEIOEN (0x00000004UL) + +/******************************************************************************* + Bit definition for Peripheral DCU +*******************************************************************************/ +/* Bit definition for DCU_CTL register */ +#define DCU_CTL_MODE_POS (0U) +#define DCU_CTL_MODE (0x00000007UL) +#define DCU_CTL_DATASIZE_POS (3U) +#define DCU_CTL_DATASIZE (0x00000018UL) +#define DCU_CTL_DATASIZE_0 (0x00000008UL) +#define DCU_CTL_DATASIZE_1 (0x00000010UL) +#define DCU_CTL_COMPTRG_POS (8U) +#define DCU_CTL_COMPTRG (0x00000100UL) +#define DCU_CTL_INTEN_POS (31U) +#define DCU_CTL_INTEN (0x80000000UL) + +/* Bit definition for DCU_FLAG register */ +#define DCU_FLAG_FLAG_OP_POS (0U) +#define DCU_FLAG_FLAG_OP (0x00000001UL) +#define DCU_FLAG_FLAG_LS2_POS (1U) +#define DCU_FLAG_FLAG_LS2 (0x00000002UL) +#define DCU_FLAG_FLAG_EQ2_POS (2U) +#define DCU_FLAG_FLAG_EQ2 (0x00000004UL) +#define DCU_FLAG_FLAG_GT2_POS (3U) +#define DCU_FLAG_FLAG_GT2 (0x00000008UL) +#define DCU_FLAG_FLAG_LS1_POS (4U) +#define DCU_FLAG_FLAG_LS1 (0x00000010UL) +#define DCU_FLAG_FLAG_EQ1_POS (5U) +#define DCU_FLAG_FLAG_EQ1 (0x00000020UL) +#define DCU_FLAG_FLAG_GT1_POS (6U) +#define DCU_FLAG_FLAG_GT1 (0x00000040UL) + +/* Bit definition for DCU_DATA0 register */ +#define DCU_DATA0 (0xFFFFFFFFUL) + +/* Bit definition for DCU_DATA1 register */ +#define DCU_DATA1 (0xFFFFFFFFUL) + +/* Bit definition for DCU_DATA2 register */ +#define DCU_DATA2 (0xFFFFFFFFUL) + +/* Bit definition for DCU_FLAGCLR register */ +#define DCU_FLAGCLR_CLR_OP_POS (0U) +#define DCU_FLAGCLR_CLR_OP (0x00000001UL) +#define DCU_FLAGCLR_CLR_LS2_POS (1U) +#define DCU_FLAGCLR_CLR_LS2 (0x00000002UL) +#define DCU_FLAGCLR_CLR_EQ2_POS (2U) +#define DCU_FLAGCLR_CLR_EQ2 (0x00000004UL) +#define DCU_FLAGCLR_CLR_GT2_POS (3U) +#define DCU_FLAGCLR_CLR_GT2 (0x00000008UL) +#define DCU_FLAGCLR_CLR_LS1_POS (4U) +#define DCU_FLAGCLR_CLR_LS1 (0x00000010UL) +#define DCU_FLAGCLR_CLR_EQ1_POS (5U) +#define DCU_FLAGCLR_CLR_EQ1 (0x00000020UL) +#define DCU_FLAGCLR_CLR_GT1_POS (6U) +#define DCU_FLAGCLR_CLR_GT1 (0x00000040UL) + +/* Bit definition for DCU_INTEVTSEL register */ +#define DCU_INTEVTSEL_SEL_OP_POS (0U) +#define DCU_INTEVTSEL_SEL_OP (0x00000001UL) +#define DCU_INTEVTSEL_SEL_LS2_POS (1U) +#define DCU_INTEVTSEL_SEL_LS2 (0x00000002UL) +#define DCU_INTEVTSEL_SEL_EQ2_POS (2U) +#define DCU_INTEVTSEL_SEL_EQ2 (0x00000004UL) +#define DCU_INTEVTSEL_SEL_GT2_POS (3U) +#define DCU_INTEVTSEL_SEL_GT2 (0x00000008UL) +#define DCU_INTEVTSEL_SEL_LS1_POS (4U) +#define DCU_INTEVTSEL_SEL_LS1 (0x00000010UL) +#define DCU_INTEVTSEL_SEL_EQ1_POS (5U) +#define DCU_INTEVTSEL_SEL_EQ1 (0x00000020UL) +#define DCU_INTEVTSEL_SEL_GT1_POS (6U) +#define DCU_INTEVTSEL_SEL_GT1 (0x00000040UL) +#define DCU_INTEVTSEL_SEL_WIN_POS (7U) +#define DCU_INTEVTSEL_SEL_WIN (0x00000180UL) +#define DCU_INTEVTSEL_SEL_WIN_0 (0x00000080UL) +#define DCU_INTEVTSEL_SEL_WIN_1 (0x00000100UL) + +/******************************************************************************* + Bit definition for Peripheral DMA +*******************************************************************************/ +/* Bit definition for DMA_EN register */ +#define DMA_EN_EN (0x00000001UL) + +/* Bit definition for DMA_INTSTAT0 register */ +#define DMA_INTSTAT0_TRNERR_POS (0U) +#define DMA_INTSTAT0_TRNERR (0x0000000FUL) +#define DMA_INTSTAT0_TRNERR_0 (0x00000001UL) +#define DMA_INTSTAT0_TRNERR_1 (0x00000002UL) +#define DMA_INTSTAT0_TRNERR_2 (0x00000004UL) +#define DMA_INTSTAT0_TRNERR_3 (0x00000008UL) +#define DMA_INTSTAT0_REQERR_POS (16U) +#define DMA_INTSTAT0_REQERR (0x000F0000UL) +#define DMA_INTSTAT0_REQERR_0 (0x00010000UL) +#define DMA_INTSTAT0_REQERR_1 (0x00020000UL) +#define DMA_INTSTAT0_REQERR_2 (0x00040000UL) +#define DMA_INTSTAT0_REQERR_3 (0x00080000UL) + +/* Bit definition for DMA_INTSTAT1 register */ +#define DMA_INTSTAT1_TC_POS (0U) +#define DMA_INTSTAT1_TC (0x0000000FUL) +#define DMA_INTSTAT1_TC_0 (0x00000001UL) +#define DMA_INTSTAT1_TC_1 (0x00000002UL) +#define DMA_INTSTAT1_TC_2 (0x00000004UL) +#define DMA_INTSTAT1_TC_3 (0x00000008UL) +#define DMA_INTSTAT1_BTC_POS (16U) +#define DMA_INTSTAT1_BTC (0x000F0000UL) +#define DMA_INTSTAT1_BTC_0 (0x00010000UL) +#define DMA_INTSTAT1_BTC_1 (0x00020000UL) +#define DMA_INTSTAT1_BTC_2 (0x00040000UL) +#define DMA_INTSTAT1_BTC_3 (0x00080000UL) + +/* Bit definition for DMA_INTMASK0 register */ +#define DMA_INTMASK0_MSKTRNERR_POS (0U) +#define DMA_INTMASK0_MSKTRNERR (0x0000000FUL) +#define DMA_INTMASK0_MSKTRNERR_0 (0x00000001UL) +#define DMA_INTMASK0_MSKTRNERR_1 (0x00000002UL) +#define DMA_INTMASK0_MSKTRNERR_2 (0x00000004UL) +#define DMA_INTMASK0_MSKTRNERR_3 (0x00000008UL) +#define DMA_INTMASK0_MSKREQERR_POS (16U) +#define DMA_INTMASK0_MSKREQERR (0x000F0000UL) +#define DMA_INTMASK0_MSKREQERR_0 (0x00010000UL) +#define DMA_INTMASK0_MSKREQERR_1 (0x00020000UL) +#define DMA_INTMASK0_MSKREQERR_2 (0x00040000UL) +#define DMA_INTMASK0_MSKREQERR_3 (0x00080000UL) + +/* Bit definition for DMA_INTMASK1 register */ +#define DMA_INTMASK1_MSKTC_POS (0U) +#define DMA_INTMASK1_MSKTC (0x0000000FUL) +#define DMA_INTMASK1_MSKTC_0 (0x00000001UL) +#define DMA_INTMASK1_MSKTC_1 (0x00000002UL) +#define DMA_INTMASK1_MSKTC_2 (0x00000004UL) +#define DMA_INTMASK1_MSKTC_3 (0x00000008UL) +#define DMA_INTMASK1_MSKBTC_POS (16U) +#define DMA_INTMASK1_MSKBTC (0x000F0000UL) +#define DMA_INTMASK1_MSKBTC_0 (0x00010000UL) +#define DMA_INTMASK1_MSKBTC_1 (0x00020000UL) +#define DMA_INTMASK1_MSKBTC_2 (0x00040000UL) +#define DMA_INTMASK1_MSKBTC_3 (0x00080000UL) + +/* Bit definition for DMA_INTCLR0 register */ +#define DMA_INTCLR0_CLRTRNERR_POS (0U) +#define DMA_INTCLR0_CLRTRNERR (0x0000000FUL) +#define DMA_INTCLR0_CLRTRNERR_0 (0x00000001UL) +#define DMA_INTCLR0_CLRTRNERR_1 (0x00000002UL) +#define DMA_INTCLR0_CLRTRNERR_2 (0x00000004UL) +#define DMA_INTCLR0_CLRTRNERR_3 (0x00000008UL) +#define DMA_INTCLR0_CLRREQERR_POS (16U) +#define DMA_INTCLR0_CLRREQERR (0x000F0000UL) +#define DMA_INTCLR0_CLRREQERR_0 (0x00010000UL) +#define DMA_INTCLR0_CLRREQERR_1 (0x00020000UL) +#define DMA_INTCLR0_CLRREQERR_2 (0x00040000UL) +#define DMA_INTCLR0_CLRREQERR_3 (0x00080000UL) + +/* Bit definition for DMA_INTCLR1 register */ +#define DMA_INTCLR1_CLRTC_POS (0U) +#define DMA_INTCLR1_CLRTC (0x0000000FUL) +#define DMA_INTCLR1_CLRTC_0 (0x00000001UL) +#define DMA_INTCLR1_CLRTC_1 (0x00000002UL) +#define DMA_INTCLR1_CLRTC_2 (0x00000004UL) +#define DMA_INTCLR1_CLRTC_3 (0x00000008UL) +#define DMA_INTCLR1_CLRBTC_POS (16U) +#define DMA_INTCLR1_CLRBTC (0x000F0000UL) +#define DMA_INTCLR1_CLRBTC_0 (0x00010000UL) +#define DMA_INTCLR1_CLRBTC_1 (0x00020000UL) +#define DMA_INTCLR1_CLRBTC_2 (0x00040000UL) +#define DMA_INTCLR1_CLRBTC_3 (0x00080000UL) + +/* Bit definition for DMA_CHEN register */ +#define DMA_CHEN_CHEN (0x0000000FUL) +#define DMA_CHEN_CHEN_0 (0x00000001UL) +#define DMA_CHEN_CHEN_1 (0x00000002UL) +#define DMA_CHEN_CHEN_2 (0x00000004UL) +#define DMA_CHEN_CHEN_3 (0x00000008UL) + +/* Bit definition for DMA_REQSTAT register */ +#define DMA_REQSTAT_CHREQ_POS (0U) +#define DMA_REQSTAT_CHREQ (0x0000000FUL) +#define DMA_REQSTAT_CHREQ_0 (0x00000001UL) +#define DMA_REQSTAT_CHREQ_1 (0x00000002UL) +#define DMA_REQSTAT_CHREQ_2 (0x00000004UL) +#define DMA_REQSTAT_CHREQ_3 (0x00000008UL) +#define DMA_REQSTAT_RCFGREQ_POS (15U) +#define DMA_REQSTAT_RCFGREQ (0x00008000UL) + +/* Bit definition for DMA_CHSTAT register */ +#define DMA_CHSTAT_DMAACT_POS (0U) +#define DMA_CHSTAT_DMAACT (0x00000001UL) +#define DMA_CHSTAT_RCFGACT_POS (1U) +#define DMA_CHSTAT_RCFGACT (0x00000002UL) +#define DMA_CHSTAT_CHACT_POS (16U) +#define DMA_CHSTAT_CHACT (0x000F0000UL) +#define DMA_CHSTAT_CHACT_0 (0x00010000UL) +#define DMA_CHSTAT_CHACT_1 (0x00020000UL) +#define DMA_CHSTAT_CHACT_2 (0x00040000UL) +#define DMA_CHSTAT_CHACT_3 (0x00080000UL) + +/* Bit definition for DMA_RCFGCTL register */ +#define DMA_RCFGCTL_RCFGEN_POS (0U) +#define DMA_RCFGCTL_RCFGEN (0x00000001UL) +#define DMA_RCFGCTL_RCFGLLP_POS (1U) +#define DMA_RCFGCTL_RCFGLLP (0x00000002UL) +#define DMA_RCFGCTL_RCFGCHS_POS (8U) +#define DMA_RCFGCTL_RCFGCHS (0x00000F00UL) +#define DMA_RCFGCTL_RCFGCHS_0 (0x00000100UL) +#define DMA_RCFGCTL_RCFGCHS_1 (0x00000200UL) +#define DMA_RCFGCTL_RCFGCHS_2 (0x00000400UL) +#define DMA_RCFGCTL_RCFGCHS_3 (0x00000800UL) +#define DMA_RCFGCTL_SARMD_POS (16U) +#define DMA_RCFGCTL_SARMD (0x00030000UL) +#define DMA_RCFGCTL_SARMD_0 (0x00010000UL) +#define DMA_RCFGCTL_SARMD_1 (0x00020000UL) +#define DMA_RCFGCTL_DARMD_POS (18U) +#define DMA_RCFGCTL_DARMD (0x000C0000UL) +#define DMA_RCFGCTL_DARMD_0 (0x00040000UL) +#define DMA_RCFGCTL_DARMD_1 (0x00080000UL) +#define DMA_RCFGCTL_CNTMD_POS (20U) +#define DMA_RCFGCTL_CNTMD (0x00300000UL) +#define DMA_RCFGCTL_CNTMD_0 (0x00100000UL) +#define DMA_RCFGCTL_CNTMD_1 (0x00200000UL) + +/* Bit definition for DMA_SAR register */ +#define DMA_SAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_DAR register */ +#define DMA_DAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_DTCTL register */ +#define DMA_DTCTL_BLKSIZE_POS (0U) +#define DMA_DTCTL_BLKSIZE (0x000003FFUL) +#define DMA_DTCTL_CNT_POS (16U) +#define DMA_DTCTL_CNT (0xFFFF0000UL) + +/* Bit definition for DMA_RPT register */ +#define DMA_RPT_SRPT_POS (0U) +#define DMA_RPT_SRPT (0x000003FFUL) +#define DMA_RPT_DRPT_POS (16U) +#define DMA_RPT_DRPT (0x03FF0000UL) + +/* Bit definition for DMA_RPTB register */ +#define DMA_RPTB_SRPTB_POS (0U) +#define DMA_RPTB_SRPTB (0x000003FFUL) +#define DMA_RPTB_SRPTB_0 (0x00000001UL) +#define DMA_RPTB_SRPTB_1 (0x00000002UL) +#define DMA_RPTB_SRPTB_2 (0x00000004UL) +#define DMA_RPTB_SRPTB_3 (0x00000008UL) +#define DMA_RPTB_SRPTB_4 (0x00000010UL) +#define DMA_RPTB_SRPTB_5 (0x00000020UL) +#define DMA_RPTB_SRPTB_6 (0x00000040UL) +#define DMA_RPTB_SRPTB_7 (0x00000080UL) +#define DMA_RPTB_SRPTB_8 (0x00000100UL) +#define DMA_RPTB_SRPTB_9 (0x00000200UL) +#define DMA_RPTB_DRPTB_POS (16U) +#define DMA_RPTB_DRPTB (0x03FF0000UL) +#define DMA_RPTB_DRPTB_0 (0x00010000UL) +#define DMA_RPTB_DRPTB_1 (0x00020000UL) +#define DMA_RPTB_DRPTB_2 (0x00040000UL) +#define DMA_RPTB_DRPTB_3 (0x00080000UL) +#define DMA_RPTB_DRPTB_4 (0x00100000UL) +#define DMA_RPTB_DRPTB_5 (0x00200000UL) +#define DMA_RPTB_DRPTB_6 (0x00400000UL) +#define DMA_RPTB_DRPTB_7 (0x00800000UL) +#define DMA_RPTB_DRPTB_8 (0x01000000UL) +#define DMA_RPTB_DRPTB_9 (0x02000000UL) + +/* Bit definition for DMA_SNSEQCTL register */ +#define DMA_SNSEQCTL_SOFFSET_POS (0U) +#define DMA_SNSEQCTL_SOFFSET (0x000FFFFFUL) +#define DMA_SNSEQCTL_SNSCNT_POS (20U) +#define DMA_SNSEQCTL_SNSCNT (0xFFF00000UL) + +/* Bit definition for DMA_SNSEQCTLB register */ +#define DMA_SNSEQCTLB_SNSDIST_POS (0U) +#define DMA_SNSEQCTLB_SNSDIST (0x000FFFFFUL) +#define DMA_SNSEQCTLB_SNSDIST_0 (0x00000001UL) +#define DMA_SNSEQCTLB_SNSDIST_1 (0x00000002UL) +#define DMA_SNSEQCTLB_SNSDIST_2 (0x00000004UL) +#define DMA_SNSEQCTLB_SNSDIST_3 (0x00000008UL) +#define DMA_SNSEQCTLB_SNSDIST_4 (0x00000010UL) +#define DMA_SNSEQCTLB_SNSDIST_5 (0x00000020UL) +#define DMA_SNSEQCTLB_SNSDIST_6 (0x00000040UL) +#define DMA_SNSEQCTLB_SNSDIST_7 (0x00000080UL) +#define DMA_SNSEQCTLB_SNSDIST_8 (0x00000100UL) +#define DMA_SNSEQCTLB_SNSDIST_9 (0x00000200UL) +#define DMA_SNSEQCTLB_SNSDIST_10 (0x00000400UL) +#define DMA_SNSEQCTLB_SNSDIST_11 (0x00000800UL) +#define DMA_SNSEQCTLB_SNSDIST_12 (0x00001000UL) +#define DMA_SNSEQCTLB_SNSDIST_13 (0x00002000UL) +#define DMA_SNSEQCTLB_SNSDIST_14 (0x00004000UL) +#define DMA_SNSEQCTLB_SNSDIST_15 (0x00008000UL) +#define DMA_SNSEQCTLB_SNSDIST_16 (0x00010000UL) +#define DMA_SNSEQCTLB_SNSDIST_17 (0x00020000UL) +#define DMA_SNSEQCTLB_SNSDIST_18 (0x00040000UL) +#define DMA_SNSEQCTLB_SNSDIST_19 (0x00080000UL) +#define DMA_SNSEQCTLB_SNSCNTB_POS (20U) +#define DMA_SNSEQCTLB_SNSCNTB (0xFFF00000UL) +#define DMA_SNSEQCTLB_SNSCNTB_0 (0x00100000UL) +#define DMA_SNSEQCTLB_SNSCNTB_1 (0x00200000UL) +#define DMA_SNSEQCTLB_SNSCNTB_2 (0x00400000UL) +#define DMA_SNSEQCTLB_SNSCNTB_3 (0x00800000UL) +#define DMA_SNSEQCTLB_SNSCNTB_4 (0x01000000UL) +#define DMA_SNSEQCTLB_SNSCNTB_5 (0x02000000UL) +#define DMA_SNSEQCTLB_SNSCNTB_6 (0x04000000UL) +#define DMA_SNSEQCTLB_SNSCNTB_7 (0x08000000UL) +#define DMA_SNSEQCTLB_SNSCNTB_8 (0x10000000UL) +#define DMA_SNSEQCTLB_SNSCNTB_9 (0x20000000UL) +#define DMA_SNSEQCTLB_SNSCNTB_10 (0x40000000UL) +#define DMA_SNSEQCTLB_SNSCNTB_11 (0x80000000UL) + +/* Bit definition for DMA_DNSEQCTL register */ +#define DMA_DNSEQCTL_DOFFSET_POS (0U) +#define DMA_DNSEQCTL_DOFFSET (0x000FFFFFUL) +#define DMA_DNSEQCTL_DNSCNT_POS (20U) +#define DMA_DNSEQCTL_DNSCNT (0xFFF00000UL) + +/* Bit definition for DMA_DNSEQCTLB register */ +#define DMA_DNSEQCTLB_DNSDIST_POS (0U) +#define DMA_DNSEQCTLB_DNSDIST (0x000FFFFFUL) +#define DMA_DNSEQCTLB_DNSDIST_0 (0x00000001UL) +#define DMA_DNSEQCTLB_DNSDIST_1 (0x00000002UL) +#define DMA_DNSEQCTLB_DNSDIST_2 (0x00000004UL) +#define DMA_DNSEQCTLB_DNSDIST_3 (0x00000008UL) +#define DMA_DNSEQCTLB_DNSDIST_4 (0x00000010UL) +#define DMA_DNSEQCTLB_DNSDIST_5 (0x00000020UL) +#define DMA_DNSEQCTLB_DNSDIST_6 (0x00000040UL) +#define DMA_DNSEQCTLB_DNSDIST_7 (0x00000080UL) +#define DMA_DNSEQCTLB_DNSDIST_8 (0x00000100UL) +#define DMA_DNSEQCTLB_DNSDIST_9 (0x00000200UL) +#define DMA_DNSEQCTLB_DNSDIST_10 (0x00000400UL) +#define DMA_DNSEQCTLB_DNSDIST_11 (0x00000800UL) +#define DMA_DNSEQCTLB_DNSDIST_12 (0x00001000UL) +#define DMA_DNSEQCTLB_DNSDIST_13 (0x00002000UL) +#define DMA_DNSEQCTLB_DNSDIST_14 (0x00004000UL) +#define DMA_DNSEQCTLB_DNSDIST_15 (0x00008000UL) +#define DMA_DNSEQCTLB_DNSDIST_16 (0x00010000UL) +#define DMA_DNSEQCTLB_DNSDIST_17 (0x00020000UL) +#define DMA_DNSEQCTLB_DNSDIST_18 (0x00040000UL) +#define DMA_DNSEQCTLB_DNSDIST_19 (0x00080000UL) +#define DMA_DNSEQCTLB_DNSCNTB_POS (20U) +#define DMA_DNSEQCTLB_DNSCNTB (0xFFF00000UL) +#define DMA_DNSEQCTLB_DNSCNTB_0 (0x00100000UL) +#define DMA_DNSEQCTLB_DNSCNTB_1 (0x00200000UL) +#define DMA_DNSEQCTLB_DNSCNTB_2 (0x00400000UL) +#define DMA_DNSEQCTLB_DNSCNTB_3 (0x00800000UL) +#define DMA_DNSEQCTLB_DNSCNTB_4 (0x01000000UL) +#define DMA_DNSEQCTLB_DNSCNTB_5 (0x02000000UL) +#define DMA_DNSEQCTLB_DNSCNTB_6 (0x04000000UL) +#define DMA_DNSEQCTLB_DNSCNTB_7 (0x08000000UL) +#define DMA_DNSEQCTLB_DNSCNTB_8 (0x10000000UL) +#define DMA_DNSEQCTLB_DNSCNTB_9 (0x20000000UL) +#define DMA_DNSEQCTLB_DNSCNTB_10 (0x40000000UL) +#define DMA_DNSEQCTLB_DNSCNTB_11 (0x80000000UL) + +/* Bit definition for DMA_LLP register */ +#define DMA_LLP_LLP_POS (2U) +#define DMA_LLP_LLP (0xFFFFFFFCUL) + +/* Bit definition for DMA_CHCTL register */ +#define DMA_CHCTL_SINC_POS (0U) +#define DMA_CHCTL_SINC (0x00000003UL) +#define DMA_CHCTL_SINC_0 (0x00000001UL) +#define DMA_CHCTL_SINC_1 (0x00000002UL) +#define DMA_CHCTL_DINC_POS (2U) +#define DMA_CHCTL_DINC (0x0000000CUL) +#define DMA_CHCTL_DINC_0 (0x00000004UL) +#define DMA_CHCTL_DINC_1 (0x00000008UL) +#define DMA_CHCTL_SRPTEN_POS (4U) +#define DMA_CHCTL_SRPTEN (0x00000010UL) +#define DMA_CHCTL_DRPTEN_POS (5U) +#define DMA_CHCTL_DRPTEN (0x00000020UL) +#define DMA_CHCTL_SNSEQEN_POS (6U) +#define DMA_CHCTL_SNSEQEN (0x00000040UL) +#define DMA_CHCTL_DNSEQEN_POS (7U) +#define DMA_CHCTL_DNSEQEN (0x00000080UL) +#define DMA_CHCTL_HSIZE_POS (8U) +#define DMA_CHCTL_HSIZE (0x00000300UL) +#define DMA_CHCTL_HSIZE_0 (0x00000100UL) +#define DMA_CHCTL_HSIZE_1 (0x00000200UL) +#define DMA_CHCTL_LLPEN_POS (10U) +#define DMA_CHCTL_LLPEN (0x00000400UL) +#define DMA_CHCTL_LLPRUN_POS (11U) +#define DMA_CHCTL_LLPRUN (0x00000800UL) +#define DMA_CHCTL_IE_POS (12U) +#define DMA_CHCTL_IE (0x00001000UL) + +/* Bit definition for DMA_MONSAR register */ +#define DMA_MONSAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_MONDAR register */ +#define DMA_MONDAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_MONDTCTL register */ +#define DMA_MONDTCTL_BLKSIZE_POS (0U) +#define DMA_MONDTCTL_BLKSIZE (0x000003FFUL) +#define DMA_MONDTCTL_CNT_POS (16U) +#define DMA_MONDTCTL_CNT (0xFFFF0000UL) + +/* Bit definition for DMA_MONRPT register */ +#define DMA_MONRPT_SRPT_POS (0U) +#define DMA_MONRPT_SRPT (0x000003FFUL) +#define DMA_MONRPT_DRPT_POS (16U) +#define DMA_MONRPT_DRPT (0x03FF0000UL) + +/* Bit definition for DMA_MONSNSEQCTL register */ +#define DMA_MONSNSEQCTL_SOFFSET_POS (0U) +#define DMA_MONSNSEQCTL_SOFFSET (0x000FFFFFUL) +#define DMA_MONSNSEQCTL_SNSCNT_POS (20U) +#define DMA_MONSNSEQCTL_SNSCNT (0xFFF00000UL) + +/* Bit definition for DMA_MONDNSEQCTL register */ +#define DMA_MONDNSEQCTL_DOFFSET_POS (0U) +#define DMA_MONDNSEQCTL_DOFFSET (0x000FFFFFUL) +#define DMA_MONDNSEQCTL_DNSCNT_POS (20U) +#define DMA_MONDNSEQCTL_DNSCNT (0xFFF00000UL) + +/******************************************************************************* + Bit definition for Peripheral EFM +*******************************************************************************/ +/* Bit definition for EFM_FAPRT register */ +#define EFM_FAPRT_FAPRT (0x0000FFFFUL) + +/* Bit definition for EFM_FSTP register */ +#define EFM_FSTP_FSTP (0x00000001UL) + +/* Bit definition for EFM_FRMC register */ +#define EFM_FRMC_SLPMD_POS (0U) +#define EFM_FRMC_SLPMD (0x00000001UL) +#define EFM_FRMC_FLWT_POS (4U) +#define EFM_FRMC_FLWT (0x000000F0UL) +#define EFM_FRMC_LVM_POS (8U) +#define EFM_FRMC_LVM (0x00000100UL) +#define EFM_FRMC_CACHE_POS (16U) +#define EFM_FRMC_CACHE (0x00010000UL) +#define EFM_FRMC_CRST_POS (24U) +#define EFM_FRMC_CRST (0x01000000UL) + +/* Bit definition for EFM_FWMC register */ +#define EFM_FWMC_PEMODE_POS (0U) +#define EFM_FWMC_PEMODE (0x00000001UL) +#define EFM_FWMC_PEMOD_POS (4U) +#define EFM_FWMC_PEMOD (0x00000070UL) +#define EFM_FWMC_BUSHLDCTL_POS (8U) +#define EFM_FWMC_BUSHLDCTL (0x00000100UL) + +/* Bit definition for EFM_FSR register */ +#define EFM_FSR_PEWERR_POS (0U) +#define EFM_FSR_PEWERR (0x00000001UL) +#define EFM_FSR_PEPRTERR_POS (1U) +#define EFM_FSR_PEPRTERR (0x00000002UL) +#define EFM_FSR_PGSZERR_POS (2U) +#define EFM_FSR_PGSZERR (0x00000004UL) +#define EFM_FSR_PGMISMTCH_POS (3U) +#define EFM_FSR_PGMISMTCH (0x00000008UL) +#define EFM_FSR_OPTEND_POS (4U) +#define EFM_FSR_OPTEND (0x00000010UL) +#define EFM_FSR_COLERR_POS (5U) +#define EFM_FSR_COLERR (0x00000020UL) +#define EFM_FSR_RDY_POS (8U) +#define EFM_FSR_RDY (0x00000100UL) + +/* Bit definition for EFM_FSCLR register */ +#define EFM_FSCLR_PEWERRCLR_POS (0U) +#define EFM_FSCLR_PEWERRCLR (0x00000001UL) +#define EFM_FSCLR_PEPRTERRCLR_POS (1U) +#define EFM_FSCLR_PEPRTERRCLR (0x00000002UL) +#define EFM_FSCLR_PGSZERRCLR_POS (2U) +#define EFM_FSCLR_PGSZERRCLR (0x00000004UL) +#define EFM_FSCLR_PGMISMTCHCLR_POS (3U) +#define EFM_FSCLR_PGMISMTCHCLR (0x00000008UL) +#define EFM_FSCLR_OPTENDCLR_POS (4U) +#define EFM_FSCLR_OPTENDCLR (0x00000010UL) +#define EFM_FSCLR_COLERRCLR_POS (5U) +#define EFM_FSCLR_COLERRCLR (0x00000020UL) + +/* Bit definition for EFM_FITE register */ +#define EFM_FITE_PEERRITE_POS (0U) +#define EFM_FITE_PEERRITE (0x00000001UL) +#define EFM_FITE_OPTENDITE_POS (1U) +#define EFM_FITE_OPTENDITE (0x00000002UL) +#define EFM_FITE_COLERRITE_POS (2U) +#define EFM_FITE_COLERRITE (0x00000004UL) + +/* Bit definition for EFM_FSWP register */ +#define EFM_FSWP_FSWP (0x00000001UL) + +/* Bit definition for EFM_FPMTSW register */ +#define EFM_FPMTSW_FPMTSW (0x0007FFFFUL) + +/* Bit definition for EFM_FPMTEW register */ +#define EFM_FPMTEW_FPMTEW (0x0007FFFFUL) + +/* Bit definition for EFM_UQID0 register */ +#define EFM_UQID0 (0xFFFFFFFFUL) + +/* Bit definition for EFM_UQID1 register */ +#define EFM_UQID1 (0xFFFFFFFFUL) + +/* Bit definition for EFM_UQID2 register */ +#define EFM_UQID2 (0xFFFFFFFFUL) + +/* Bit definition for EFM_MMF_REMPRT register */ +#define EFM_MMF_REMPRT_REMPRT (0x0000FFFFUL) + +/* Bit definition for EFM_MMF_REMCR register */ +#define EFM_MMF_REMCR_RMSIZE_POS (0U) +#define EFM_MMF_REMCR_RMSIZE (0x0000001FUL) +#define EFM_MMF_REMCR_RMTADDR_POS (12U) +#define EFM_MMF_REMCR_RMTADDR (0x1FFFF000UL) +#define EFM_MMF_REMCR_EN_POS (31U) +#define EFM_MMF_REMCR_EN (0x80000000UL) + +/******************************************************************************* + Bit definition for Peripheral EMB +*******************************************************************************/ +/* Bit definition for EMB_CTL register */ +#define EMB_CTL_PORTINEN_POS (0U) +#define EMB_CTL_PORTINEN (0x00000001UL) +#define EMB_CTL_CMPEN1_POS (1U) +#define EMB_CTL_CMPEN1 (0x00000002UL) +#define EMB_CTL_CMPEN2_POS (2U) +#define EMB_CTL_CMPEN2 (0x00000004UL) +#define EMB_CTL_CMPEN3_POS (3U) +#define EMB_CTL_CMPEN3 (0x00000008UL) +#define EMB_CTL_OSCSTPEN_POS (5U) +#define EMB_CTL_OSCSTPEN (0x00000020UL) +#define EMB_CTL_PWMSEN0_POS (6U) +#define EMB_CTL_PWMSEN0 (0x00000040UL) +#define EMB_CTL_PWMSEN1_POS (7U) +#define EMB_CTL_PWMSEN1 (0x00000080UL) +#define EMB_CTL_PWMSEN2_POS (8U) +#define EMB_CTL_PWMSEN2 (0x00000100UL) +#define EMB_CTL_NFSEL_POS (28U) +#define EMB_CTL_NFSEL (0x30000000UL) +#define EMB_CTL_NFEN_POS (30U) +#define EMB_CTL_NFEN (0x40000000UL) +#define EMB_CTL_INVSEL_POS (31U) +#define EMB_CTL_INVSEL (0x80000000UL) + +/* Bit definition for EMB_PWMLV register */ +#define EMB_PWMLV_PWMLV0_POS (0U) +#define EMB_PWMLV_PWMLV0 (0x00000001UL) +#define EMB_PWMLV_PWMLV1_POS (1U) +#define EMB_PWMLV_PWMLV1 (0x00000002UL) +#define EMB_PWMLV_PWMLV2_POS (2U) +#define EMB_PWMLV_PWMLV2 (0x00000004UL) + +/* Bit definition for EMB_SOE register */ +#define EMB_SOE_SOE (0x00000001UL) + +/* Bit definition for EMB_STAT register */ +#define EMB_STAT_PORTINF_POS (0U) +#define EMB_STAT_PORTINF (0x00000001UL) +#define EMB_STAT_PWMSF_POS (1U) +#define EMB_STAT_PWMSF (0x00000002UL) +#define EMB_STAT_CMPF_POS (2U) +#define EMB_STAT_CMPF (0x00000004UL) +#define EMB_STAT_OSF_POS (3U) +#define EMB_STAT_OSF (0x00000008UL) +#define EMB_STAT_PORTINST_POS (4U) +#define EMB_STAT_PORTINST (0x00000010UL) +#define EMB_STAT_PWMST_POS (5U) +#define EMB_STAT_PWMST (0x00000020UL) + +/* Bit definition for EMB_STATCLR register */ +#define EMB_STATCLR_PORTINFCLR_POS (0U) +#define EMB_STATCLR_PORTINFCLR (0x00000001UL) +#define EMB_STATCLR_PWMSFCLR_POS (1U) +#define EMB_STATCLR_PWMSFCLR (0x00000002UL) +#define EMB_STATCLR_CMPFCLR_POS (2U) +#define EMB_STATCLR_CMPFCLR (0x00000004UL) +#define EMB_STATCLR_OSFCLR_POS (3U) +#define EMB_STATCLR_OSFCLR (0x00000008UL) + +/* Bit definition for EMB_INTEN register */ +#define EMB_INTEN_PORTININTEN_POS (0U) +#define EMB_INTEN_PORTININTEN (0x00000001UL) +#define EMB_INTEN_PWMSINTEN_POS (1U) +#define EMB_INTEN_PWMSINTEN (0x00000002UL) +#define EMB_INTEN_CMPINTEN_POS (2U) +#define EMB_INTEN_CMPINTEN (0x00000004UL) +#define EMB_INTEN_OSINTEN_POS (3U) +#define EMB_INTEN_OSINTEN (0x00000008UL) + +/******************************************************************************* + Bit definition for Peripheral FCM +*******************************************************************************/ +/* Bit definition for FCM_LVR register */ +#define FCM_LVR_LVR (0x0000FFFFUL) + +/* Bit definition for FCM_UVR register */ +#define FCM_UVR_UVR (0x0000FFFFUL) + +/* Bit definition for FCM_CNTR register */ +#define FCM_CNTR_CNTR (0x0000FFFFUL) + +/* Bit definition for FCM_STR register */ +#define FCM_STR_START (0x00000001UL) + +/* Bit definition for FCM_MCCR register */ +#define FCM_MCCR_MDIVS_POS (0U) +#define FCM_MCCR_MDIVS (0x00000003UL) +#define FCM_MCCR_MDIVS_0 (0x00000001UL) +#define FCM_MCCR_MDIVS_1 (0x00000002UL) +#define FCM_MCCR_MCKS_POS (4U) +#define FCM_MCCR_MCKS (0x000000F0UL) + +/* Bit definition for FCM_RCCR register */ +#define FCM_RCCR_RDIVS_POS (0U) +#define FCM_RCCR_RDIVS (0x00000003UL) +#define FCM_RCCR_RDIVS_0 (0x00000001UL) +#define FCM_RCCR_RDIVS_1 (0x00000002UL) +#define FCM_RCCR_RCKS_POS (3U) +#define FCM_RCCR_RCKS (0x00000078UL) +#define FCM_RCCR_INEXS_POS (7U) +#define FCM_RCCR_INEXS (0x00000080UL) +#define FCM_RCCR_DNFS_POS (8U) +#define FCM_RCCR_DNFS (0x00000300UL) +#define FCM_RCCR_DNFS_0 (0x00000100UL) +#define FCM_RCCR_DNFS_1 (0x00000200UL) +#define FCM_RCCR_EDGES_POS (12U) +#define FCM_RCCR_EDGES (0x00003000UL) +#define FCM_RCCR_EDGES_0 (0x00001000UL) +#define FCM_RCCR_EDGES_1 (0x00002000UL) +#define FCM_RCCR_EXREFE_POS (15U) +#define FCM_RCCR_EXREFE (0x00008000UL) + +/* Bit definition for FCM_RIER register */ +#define FCM_RIER_ERRIE_POS (0U) +#define FCM_RIER_ERRIE (0x00000001UL) +#define FCM_RIER_MENDIE_POS (1U) +#define FCM_RIER_MENDIE (0x00000002UL) +#define FCM_RIER_OVFIE_POS (2U) +#define FCM_RIER_OVFIE (0x00000004UL) +#define FCM_RIER_ERRINTRS_POS (4U) +#define FCM_RIER_ERRINTRS (0x00000010UL) +#define FCM_RIER_ERRE_POS (7U) +#define FCM_RIER_ERRE (0x00000080UL) + +/* Bit definition for FCM_SR register */ +#define FCM_SR_ERRF_POS (0U) +#define FCM_SR_ERRF (0x00000001UL) +#define FCM_SR_MENDF_POS (1U) +#define FCM_SR_MENDF (0x00000002UL) +#define FCM_SR_OVF_POS (2U) +#define FCM_SR_OVF (0x00000004UL) + +/* Bit definition for FCM_CLR register */ +#define FCM_CLR_ERRFCLR_POS (0U) +#define FCM_CLR_ERRFCLR (0x00000001UL) +#define FCM_CLR_MENDFCLR_POS (1U) +#define FCM_CLR_MENDFCLR (0x00000002UL) +#define FCM_CLR_OVFCLR_POS (2U) +#define FCM_CLR_OVFCLR (0x00000004UL) + +/******************************************************************************* + Bit definition for Peripheral GPIO +*******************************************************************************/ +/* Bit definition for GPIO_PIDR register */ +#define GPIO_PIDR_PIN00_POS (0U) +#define GPIO_PIDR_PIN00 (0x0001U) +#define GPIO_PIDR_PIN01_POS (1U) +#define GPIO_PIDR_PIN01 (0x0002U) +#define GPIO_PIDR_PIN02_POS (2U) +#define GPIO_PIDR_PIN02 (0x0004U) +#define GPIO_PIDR_PIN03_POS (3U) +#define GPIO_PIDR_PIN03 (0x0008U) +#define GPIO_PIDR_PIN04_POS (4U) +#define GPIO_PIDR_PIN04 (0x0010U) +#define GPIO_PIDR_PIN05_POS (5U) +#define GPIO_PIDR_PIN05 (0x0020U) +#define GPIO_PIDR_PIN06_POS (6U) +#define GPIO_PIDR_PIN06 (0x0040U) +#define GPIO_PIDR_PIN07_POS (7U) +#define GPIO_PIDR_PIN07 (0x0080U) +#define GPIO_PIDR_PIN08_POS (8U) +#define GPIO_PIDR_PIN08 (0x0100U) +#define GPIO_PIDR_PIN09_POS (9U) +#define GPIO_PIDR_PIN09 (0x0200U) +#define GPIO_PIDR_PIN10_POS (10U) +#define GPIO_PIDR_PIN10 (0x0400U) +#define GPIO_PIDR_PIN11_POS (11U) +#define GPIO_PIDR_PIN11 (0x0800U) +#define GPIO_PIDR_PIN12_POS (12U) +#define GPIO_PIDR_PIN12 (0x1000U) +#define GPIO_PIDR_PIN13_POS (13U) +#define GPIO_PIDR_PIN13 (0x2000U) +#define GPIO_PIDR_PIN14_POS (14U) +#define GPIO_PIDR_PIN14 (0x4000U) +#define GPIO_PIDR_PIN15_POS (15U) +#define GPIO_PIDR_PIN15 (0x8000U) + +/* Bit definition for GPIO_PODR register */ +#define GPIO_PODR_POUT00_POS (0U) +#define GPIO_PODR_POUT00 (0x0001U) +#define GPIO_PODR_POUT01_POS (1U) +#define GPIO_PODR_POUT01 (0x0002U) +#define GPIO_PODR_POUT02_POS (2U) +#define GPIO_PODR_POUT02 (0x0004U) +#define GPIO_PODR_POUT03_POS (3U) +#define GPIO_PODR_POUT03 (0x0008U) +#define GPIO_PODR_POUT04_POS (4U) +#define GPIO_PODR_POUT04 (0x0010U) +#define GPIO_PODR_POUT05_POS (5U) +#define GPIO_PODR_POUT05 (0x0020U) +#define GPIO_PODR_POUT06_POS (6U) +#define GPIO_PODR_POUT06 (0x0040U) +#define GPIO_PODR_POUT07_POS (7U) +#define GPIO_PODR_POUT07 (0x0080U) +#define GPIO_PODR_POUT08_POS (8U) +#define GPIO_PODR_POUT08 (0x0100U) +#define GPIO_PODR_POUT09_POS (9U) +#define GPIO_PODR_POUT09 (0x0200U) +#define GPIO_PODR_POUT10_POS (10U) +#define GPIO_PODR_POUT10 (0x0400U) +#define GPIO_PODR_POUT11_POS (11U) +#define GPIO_PODR_POUT11 (0x0800U) +#define GPIO_PODR_POUT12_POS (12U) +#define GPIO_PODR_POUT12 (0x1000U) +#define GPIO_PODR_POUT13_POS (13U) +#define GPIO_PODR_POUT13 (0x2000U) +#define GPIO_PODR_POUT14_POS (14U) +#define GPIO_PODR_POUT14 (0x4000U) +#define GPIO_PODR_POUT15_POS (15U) +#define GPIO_PODR_POUT15 (0x8000U) + +/* Bit definition for GPIO_POER register */ +#define GPIO_POER_POUTE00_POS (0U) +#define GPIO_POER_POUTE00 (0x0001U) +#define GPIO_POER_POUTE01_POS (1U) +#define GPIO_POER_POUTE01 (0x0002U) +#define GPIO_POER_POUTE02_POS (2U) +#define GPIO_POER_POUTE02 (0x0004U) +#define GPIO_POER_POUTE03_POS (3U) +#define GPIO_POER_POUTE03 (0x0008U) +#define GPIO_POER_POUTE04_POS (4U) +#define GPIO_POER_POUTE04 (0x0010U) +#define GPIO_POER_POUTE05_POS (5U) +#define GPIO_POER_POUTE05 (0x0020U) +#define GPIO_POER_POUTE06_POS (6U) +#define GPIO_POER_POUTE06 (0x0040U) +#define GPIO_POER_POUTE07_POS (7U) +#define GPIO_POER_POUTE07 (0x0080U) +#define GPIO_POER_POUTE08_POS (8U) +#define GPIO_POER_POUTE08 (0x0100U) +#define GPIO_POER_POUTE09_POS (9U) +#define GPIO_POER_POUTE09 (0x0200U) +#define GPIO_POER_POUTE10_POS (10U) +#define GPIO_POER_POUTE10 (0x0400U) +#define GPIO_POER_POUTE11_POS (11U) +#define GPIO_POER_POUTE11 (0x0800U) +#define GPIO_POER_POUTE12_POS (12U) +#define GPIO_POER_POUTE12 (0x1000U) +#define GPIO_POER_POUTE13_POS (13U) +#define GPIO_POER_POUTE13 (0x2000U) +#define GPIO_POER_POUTE14_POS (14U) +#define GPIO_POER_POUTE14 (0x4000U) +#define GPIO_POER_POUTE15_POS (15U) +#define GPIO_POER_POUTE15 (0x8000U) + +/* Bit definition for GPIO_POSR register */ +#define GPIO_POSR_POS00_POS (0U) +#define GPIO_POSR_POS00 (0x0001U) +#define GPIO_POSR_POS01_POS (1U) +#define GPIO_POSR_POS01 (0x0002U) +#define GPIO_POSR_POS02_POS (2U) +#define GPIO_POSR_POS02 (0x0004U) +#define GPIO_POSR_POS03_POS (3U) +#define GPIO_POSR_POS03 (0x0008U) +#define GPIO_POSR_POS04_POS (4U) +#define GPIO_POSR_POS04 (0x0010U) +#define GPIO_POSR_POS05_POS (5U) +#define GPIO_POSR_POS05 (0x0020U) +#define GPIO_POSR_POS06_POS (6U) +#define GPIO_POSR_POS06 (0x0040U) +#define GPIO_POSR_POS07_POS (7U) +#define GPIO_POSR_POS07 (0x0080U) +#define GPIO_POSR_POS08_POS (8U) +#define GPIO_POSR_POS08 (0x0100U) +#define GPIO_POSR_POS09_POS (9U) +#define GPIO_POSR_POS09 (0x0200U) +#define GPIO_POSR_POS10_POS (10U) +#define GPIO_POSR_POS10 (0x0400U) +#define GPIO_POSR_POS11_POS (11U) +#define GPIO_POSR_POS11 (0x0800U) +#define GPIO_POSR_POS12_POS (12U) +#define GPIO_POSR_POS12 (0x1000U) +#define GPIO_POSR_POS13_POS (13U) +#define GPIO_POSR_POS13 (0x2000U) +#define GPIO_POSR_POS14_POS (14U) +#define GPIO_POSR_POS14 (0x4000U) +#define GPIO_POSR_POS15_POS (15U) +#define GPIO_POSR_POS15 (0x8000U) + +/* Bit definition for GPIO_PORR register */ +#define GPIO_PORR_POR00_POS (0U) +#define GPIO_PORR_POR00 (0x0001U) +#define GPIO_PORR_POR01_POS (1U) +#define GPIO_PORR_POR01 (0x0002U) +#define GPIO_PORR_POR02_POS (2U) +#define GPIO_PORR_POR02 (0x0004U) +#define GPIO_PORR_POR03_POS (3U) +#define GPIO_PORR_POR03 (0x0008U) +#define GPIO_PORR_POR04_POS (4U) +#define GPIO_PORR_POR04 (0x0010U) +#define GPIO_PORR_POR05_POS (5U) +#define GPIO_PORR_POR05 (0x0020U) +#define GPIO_PORR_POR06_POS (6U) +#define GPIO_PORR_POR06 (0x0040U) +#define GPIO_PORR_POR07_POS (7U) +#define GPIO_PORR_POR07 (0x0080U) +#define GPIO_PORR_POR08_POS (8U) +#define GPIO_PORR_POR08 (0x0100U) +#define GPIO_PORR_POR09_POS (9U) +#define GPIO_PORR_POR09 (0x0200U) +#define GPIO_PORR_POR10_POS (10U) +#define GPIO_PORR_POR10 (0x0400U) +#define GPIO_PORR_POR11_POS (11U) +#define GPIO_PORR_POR11 (0x0800U) +#define GPIO_PORR_POR12_POS (12U) +#define GPIO_PORR_POR12 (0x1000U) +#define GPIO_PORR_POR13_POS (13U) +#define GPIO_PORR_POR13 (0x2000U) +#define GPIO_PORR_POR14_POS (14U) +#define GPIO_PORR_POR14 (0x4000U) +#define GPIO_PORR_POR15_POS (15U) +#define GPIO_PORR_POR15 (0x8000U) + +/* Bit definition for GPIO_POTR register */ +#define GPIO_POTR_POT00_POS (0U) +#define GPIO_POTR_POT00 (0x0001U) +#define GPIO_POTR_POT01_POS (1U) +#define GPIO_POTR_POT01 (0x0002U) +#define GPIO_POTR_POT02_POS (2U) +#define GPIO_POTR_POT02 (0x0004U) +#define GPIO_POTR_POT03_POS (3U) +#define GPIO_POTR_POT03 (0x0008U) +#define GPIO_POTR_POT04_POS (4U) +#define GPIO_POTR_POT04 (0x0010U) +#define GPIO_POTR_POT05_POS (5U) +#define GPIO_POTR_POT05 (0x0020U) +#define GPIO_POTR_POT06_POS (6U) +#define GPIO_POTR_POT06 (0x0040U) +#define GPIO_POTR_POT07_POS (7U) +#define GPIO_POTR_POT07 (0x0080U) +#define GPIO_POTR_POT08_POS (8U) +#define GPIO_POTR_POT08 (0x0100U) +#define GPIO_POTR_POT09_POS (9U) +#define GPIO_POTR_POT09 (0x0200U) +#define GPIO_POTR_POT10_POS (10U) +#define GPIO_POTR_POT10 (0x0400U) +#define GPIO_POTR_POT11_POS (11U) +#define GPIO_POTR_POT11 (0x0800U) +#define GPIO_POTR_POT12_POS (12U) +#define GPIO_POTR_POT12 (0x1000U) +#define GPIO_POTR_POT13_POS (13U) +#define GPIO_POTR_POT13 (0x2000U) +#define GPIO_POTR_POT14_POS (14U) +#define GPIO_POTR_POT14 (0x4000U) +#define GPIO_POTR_POT15_POS (15U) +#define GPIO_POTR_POT15 (0x8000U) + +/* Bit definition for GPIO_PIDRH register */ +#define GPIO_PIDRH_PIN00_POS (0U) +#define GPIO_PIDRH_PIN00 (0x0001U) +#define GPIO_PIDRH_PIN01_POS (1U) +#define GPIO_PIDRH_PIN01 (0x0002U) +#define GPIO_PIDRH_PIN02_POS (2U) +#define GPIO_PIDRH_PIN02 (0x0004U) + +/* Bit definition for GPIO_PODRH register */ +#define GPIO_PODRH_POUT00_POS (0U) +#define GPIO_PODRH_POUT00 (0x0001U) +#define GPIO_PODRH_POUT01_POS (1U) +#define GPIO_PODRH_POUT01 (0x0002U) +#define GPIO_PODRH_POUT02_POS (2U) +#define GPIO_PODRH_POUT02 (0x0004U) + +/* Bit definition for GPIO_POERH register */ +#define GPIO_POERH_POUTE00_POS (0U) +#define GPIO_POERH_POUTE00 (0x0001U) +#define GPIO_POERH_POUTE01_POS (1U) +#define GPIO_POERH_POUTE01 (0x0002U) +#define GPIO_POERH_POUTE02_POS (2U) +#define GPIO_POERH_POUTE02 (0x0004U) + +/* Bit definition for GPIO_POSRH register */ +#define GPIO_POSRH_POS00_POS (0U) +#define GPIO_POSRH_POS00 (0x0001U) +#define GPIO_POSRH_POS01_POS (1U) +#define GPIO_POSRH_POS01 (0x0002U) +#define GPIO_POSRH_POS02_POS (2U) +#define GPIO_POSRH_POS02 (0x0004U) + +/* Bit definition for GPIO_PORRH register */ +#define GPIO_PORRH_POR00_POS (0U) +#define GPIO_PORRH_POR00 (0x0001U) +#define GPIO_PORRH_POR01_POS (1U) +#define GPIO_PORRH_POR01 (0x0002U) +#define GPIO_PORRH_POR02_POS (2U) +#define GPIO_PORRH_POR02 (0x0004U) + +/* Bit definition for GPIO_POTRH register */ +#define GPIO_POTRH_POT00_POS (0U) +#define GPIO_POTRH_POT00 (0x0001U) +#define GPIO_POTRH_POT01_POS (1U) +#define GPIO_POTRH_POT01 (0x0002U) +#define GPIO_POTRH_POT02_POS (2U) +#define GPIO_POTRH_POT02 (0x0004U) + +/* Bit definition for GPIO_PSPCR register */ +#define GPIO_PSPCR_SPFE (0x001FU) +#define GPIO_PSPCR_SPFE_0 (0x0001U) +#define GPIO_PSPCR_SPFE_1 (0x0002U) +#define GPIO_PSPCR_SPFE_2 (0x0004U) +#define GPIO_PSPCR_SPFE_3 (0x0008U) +#define GPIO_PSPCR_SPFE_4 (0x0010U) + +/* Bit definition for GPIO_PCCR register */ +#define GPIO_PCCR_BFSEL_POS (0U) +#define GPIO_PCCR_BFSEL (0x000FU) +#define GPIO_PCCR_BFSEL_0 (0x0001U) +#define GPIO_PCCR_BFSEL_1 (0x0002U) +#define GPIO_PCCR_BFSEL_2 (0x0004U) +#define GPIO_PCCR_BFSEL_3 (0x0008U) +#define GPIO_PCCR_RDWT_POS (14U) +#define GPIO_PCCR_RDWT (0xC000U) +#define GPIO_PCCR_RDWT_0 (0x4000U) +#define GPIO_PCCR_RDWT_1 (0x8000U) + +/* Bit definition for GPIO_PINAER register */ +#define GPIO_PINAER_PINAE (0x003FU) +#define GPIO_PINAER_PINAE_0 (0x0001U) +#define GPIO_PINAER_PINAE_1 (0x0002U) +#define GPIO_PINAER_PINAE_2 (0x0004U) +#define GPIO_PINAER_PINAE_3 (0x0008U) +#define GPIO_PINAER_PINAE_4 (0x0010U) +#define GPIO_PINAER_PINAE_5 (0x0020U) + +/* Bit definition for GPIO_PWPR register */ +#define GPIO_PWPR_WE_POS (0U) +#define GPIO_PWPR_WE (0x0001U) +#define GPIO_PWPR_WP_POS (8U) +#define GPIO_PWPR_WP (0xFF00U) +#define GPIO_PWPR_WP_0 (0x0100U) +#define GPIO_PWPR_WP_1 (0x0200U) +#define GPIO_PWPR_WP_2 (0x0400U) +#define GPIO_PWPR_WP_3 (0x0800U) +#define GPIO_PWPR_WP_4 (0x1000U) +#define GPIO_PWPR_WP_5 (0x2000U) +#define GPIO_PWPR_WP_6 (0x4000U) +#define GPIO_PWPR_WP_7 (0x8000U) + +/* Bit definition for GPIO_PCR register */ +#define GPIO_PCR_POUT_POS (0U) +#define GPIO_PCR_POUT (0x0001U) +#define GPIO_PCR_POUTE_POS (1U) +#define GPIO_PCR_POUTE (0x0002U) +#define GPIO_PCR_NOD_POS (2U) +#define GPIO_PCR_NOD (0x0004U) +#define GPIO_PCR_DRV_POS (4U) +#define GPIO_PCR_DRV (0x0030U) +#define GPIO_PCR_DRV_0 (0x0010U) +#define GPIO_PCR_DRV_1 (0x0020U) +#define GPIO_PCR_PUU_POS (6U) +#define GPIO_PCR_PUU (0x0040U) +#define GPIO_PCR_PIN_POS (8U) +#define GPIO_PCR_PIN (0x0100U) +#define GPIO_PCR_INVE_POS (9U) +#define GPIO_PCR_INVE (0x0200U) +#define GPIO_PCR_INTE_POS (12U) +#define GPIO_PCR_INTE (0x1000U) +#define GPIO_PCR_LTE_POS (14U) +#define GPIO_PCR_LTE (0x4000U) +#define GPIO_PCR_DDIS_POS (15U) +#define GPIO_PCR_DDIS (0x8000U) + +/* Bit definition for GPIO_PFSR register */ +#define GPIO_PFSR_FSEL_POS (0U) +#define GPIO_PFSR_FSEL (0x003FU) +#define GPIO_PFSR_FSEL_0 (0x0001U) +#define GPIO_PFSR_FSEL_1 (0x0002U) +#define GPIO_PFSR_FSEL_2 (0x0004U) +#define GPIO_PFSR_FSEL_3 (0x0008U) +#define GPIO_PFSR_FSEL_4 (0x0010U) +#define GPIO_PFSR_FSEL_5 (0x0020U) +#define GPIO_PFSR_BFE_POS (8U) +#define GPIO_PFSR_BFE (0x0100U) + +/******************************************************************************* + Bit definition for Peripheral HASH +*******************************************************************************/ +/* Bit definition for HASH_CR register */ +#define HASH_CR_START_POS (0U) +#define HASH_CR_START (0x00000001UL) +#define HASH_CR_FST_GRP_POS (1U) +#define HASH_CR_FST_GRP (0x00000002UL) + +/* Bit definition for HASH_HR7 register */ +#define HASH_HR7 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR6 register */ +#define HASH_HR6 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR5 register */ +#define HASH_HR5 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR4 register */ +#define HASH_HR4 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR3 register */ +#define HASH_HR3 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR2 register */ +#define HASH_HR2 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR1 register */ +#define HASH_HR1 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR0 register */ +#define HASH_HR0 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR15 register */ +#define HASH_DR15 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR14 register */ +#define HASH_DR14 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR13 register */ +#define HASH_DR13 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR12 register */ +#define HASH_DR12 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR11 register */ +#define HASH_DR11 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR10 register */ +#define HASH_DR10 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR9 register */ +#define HASH_DR9 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR8 register */ +#define HASH_DR8 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR7 register */ +#define HASH_DR7 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR6 register */ +#define HASH_DR6 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR5 register */ +#define HASH_DR5 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR4 register */ +#define HASH_DR4 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR3 register */ +#define HASH_DR3 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR2 register */ +#define HASH_DR2 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR1 register */ +#define HASH_DR1 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR0 register */ +#define HASH_DR0 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral I2C +*******************************************************************************/ +/* Bit definition for I2C_CR1 register */ +#define I2C_CR1_PE_POS (0U) +#define I2C_CR1_PE (0x00000001UL) +#define I2C_CR1_SMBUS_POS (1U) +#define I2C_CR1_SMBUS (0x00000002UL) +#define I2C_CR1_SMBALRTEN_POS (2U) +#define I2C_CR1_SMBALRTEN (0x00000004UL) +#define I2C_CR1_SMBDEFAULTEN_POS (3U) +#define I2C_CR1_SMBDEFAULTEN (0x00000008UL) +#define I2C_CR1_SMBHOSTEN_POS (4U) +#define I2C_CR1_SMBHOSTEN (0x00000010UL) +#define I2C_CR1_ENGC_POS (6U) +#define I2C_CR1_ENGC (0x00000040UL) +#define I2C_CR1_RESTART_POS (7U) +#define I2C_CR1_RESTART (0x00000080UL) +#define I2C_CR1_START_POS (8U) +#define I2C_CR1_START (0x00000100UL) +#define I2C_CR1_STOP_POS (9U) +#define I2C_CR1_STOP (0x00000200UL) +#define I2C_CR1_ACK_POS (10U) +#define I2C_CR1_ACK (0x00000400UL) +#define I2C_CR1_SWRST_POS (15U) +#define I2C_CR1_SWRST (0x00008000UL) + +/* Bit definition for I2C_CR2 register */ +#define I2C_CR2_STARTIE_POS (0U) +#define I2C_CR2_STARTIE (0x00000001UL) +#define I2C_CR2_SLADDR0IE_POS (1U) +#define I2C_CR2_SLADDR0IE (0x00000002UL) +#define I2C_CR2_SLADDR1IE_POS (2U) +#define I2C_CR2_SLADDR1IE (0x00000004UL) +#define I2C_CR2_TENDIE_POS (3U) +#define I2C_CR2_TENDIE (0x00000008UL) +#define I2C_CR2_STOPIE_POS (4U) +#define I2C_CR2_STOPIE (0x00000010UL) +#define I2C_CR2_RFULLIE_POS (6U) +#define I2C_CR2_RFULLIE (0x00000040UL) +#define I2C_CR2_TEMPTYIE_POS (7U) +#define I2C_CR2_TEMPTYIE (0x00000080UL) +#define I2C_CR2_ARLOIE_POS (9U) +#define I2C_CR2_ARLOIE (0x00000200UL) +#define I2C_CR2_NACKIE_POS (12U) +#define I2C_CR2_NACKIE (0x00001000UL) +#define I2C_CR2_TMOUTIE_POS (14U) +#define I2C_CR2_TMOUTIE (0x00004000UL) +#define I2C_CR2_GENCALLIE_POS (20U) +#define I2C_CR2_GENCALLIE (0x00100000UL) +#define I2C_CR2_SMBDEFAULTIE_POS (21U) +#define I2C_CR2_SMBDEFAULTIE (0x00200000UL) +#define I2C_CR2_SMBHOSTIE_POS (22U) +#define I2C_CR2_SMBHOSTIE (0x00400000UL) +#define I2C_CR2_SMBALRTIE_POS (23U) +#define I2C_CR2_SMBALRTIE (0x00800000UL) + +/* Bit definition for I2C_CR3 register */ +#define I2C_CR3_TMOUTEN_POS (0U) +#define I2C_CR3_TMOUTEN (0x00000001UL) +#define I2C_CR3_LTMOUT_POS (1U) +#define I2C_CR3_LTMOUT (0x00000002UL) +#define I2C_CR3_HTMOUT_POS (2U) +#define I2C_CR3_HTMOUT (0x00000004UL) +#define I2C_CR3_FACKEN_POS (7U) +#define I2C_CR3_FACKEN (0x00000080UL) + +/* Bit definition for I2C_CR4 register */ +#define I2C_CR4_BUSWAIT_POS (10U) +#define I2C_CR4_BUSWAIT (0x00000400UL) + +/* Bit definition for I2C_SLR0 register */ +#define I2C_SLR0_SLADDR0_POS (0U) +#define I2C_SLR0_SLADDR0 (0x000003FFUL) +#define I2C_SLR0_SLADDR0EN_POS (12U) +#define I2C_SLR0_SLADDR0EN (0x00001000UL) +#define I2C_SLR0_ADDRMOD0_POS (15U) +#define I2C_SLR0_ADDRMOD0 (0x00008000UL) + +/* Bit definition for I2C_SLR1 register */ +#define I2C_SLR1_SLADDR1_POS (0U) +#define I2C_SLR1_SLADDR1 (0x000003FFUL) +#define I2C_SLR1_SLADDR1EN_POS (12U) +#define I2C_SLR1_SLADDR1EN (0x00001000UL) +#define I2C_SLR1_ADDRMOD1_POS (15U) +#define I2C_SLR1_ADDRMOD1 (0x00008000UL) + +/* Bit definition for I2C_SLTR register */ +#define I2C_SLTR_TOUTLOW_POS (0U) +#define I2C_SLTR_TOUTLOW (0x0000FFFFUL) +#define I2C_SLTR_TOUTHIGH_POS (16U) +#define I2C_SLTR_TOUTHIGH (0xFFFF0000UL) + +/* Bit definition for I2C_SR register */ +#define I2C_SR_STARTF_POS (0U) +#define I2C_SR_STARTF (0x00000001UL) +#define I2C_SR_SLADDR0F_POS (1U) +#define I2C_SR_SLADDR0F (0x00000002UL) +#define I2C_SR_SLADDR1F_POS (2U) +#define I2C_SR_SLADDR1F (0x00000004UL) +#define I2C_SR_TENDF_POS (3U) +#define I2C_SR_TENDF (0x00000008UL) +#define I2C_SR_STOPF_POS (4U) +#define I2C_SR_STOPF (0x00000010UL) +#define I2C_SR_RFULLF_POS (6U) +#define I2C_SR_RFULLF (0x00000040UL) +#define I2C_SR_TEMPTYF_POS (7U) +#define I2C_SR_TEMPTYF (0x00000080UL) +#define I2C_SR_ARLOF_POS (9U) +#define I2C_SR_ARLOF (0x00000200UL) +#define I2C_SR_ACKRF_POS (10U) +#define I2C_SR_ACKRF (0x00000400UL) +#define I2C_SR_NACKF_POS (12U) +#define I2C_SR_NACKF (0x00001000UL) +#define I2C_SR_TMOUTF_POS (14U) +#define I2C_SR_TMOUTF (0x00004000UL) +#define I2C_SR_MSL_POS (16U) +#define I2C_SR_MSL (0x00010000UL) +#define I2C_SR_BUSY_POS (17U) +#define I2C_SR_BUSY (0x00020000UL) +#define I2C_SR_TRA_POS (18U) +#define I2C_SR_TRA (0x00040000UL) +#define I2C_SR_GENCALLF_POS (20U) +#define I2C_SR_GENCALLF (0x00100000UL) +#define I2C_SR_SMBDEFAULTF_POS (21U) +#define I2C_SR_SMBDEFAULTF (0x00200000UL) +#define I2C_SR_SMBHOSTF_POS (22U) +#define I2C_SR_SMBHOSTF (0x00400000UL) +#define I2C_SR_SMBALRTF_POS (23U) +#define I2C_SR_SMBALRTF (0x00800000UL) + +/* Bit definition for I2C_CLR register */ +#define I2C_CLR_STARTFCLR_POS (0U) +#define I2C_CLR_STARTFCLR (0x00000001UL) +#define I2C_CLR_SLADDR0FCLR_POS (1U) +#define I2C_CLR_SLADDR0FCLR (0x00000002UL) +#define I2C_CLR_SLADDR1FCLR_POS (2U) +#define I2C_CLR_SLADDR1FCLR (0x00000004UL) +#define I2C_CLR_TENDFCLR_POS (3U) +#define I2C_CLR_TENDFCLR (0x00000008UL) +#define I2C_CLR_STOPFCLR_POS (4U) +#define I2C_CLR_STOPFCLR (0x00000010UL) +#define I2C_CLR_RFULLFCLR_POS (6U) +#define I2C_CLR_RFULLFCLR (0x00000040UL) +#define I2C_CLR_TEMPTYFCLR_POS (7U) +#define I2C_CLR_TEMPTYFCLR (0x00000080UL) +#define I2C_CLR_ARLOFCLR_POS (9U) +#define I2C_CLR_ARLOFCLR (0x00000200UL) +#define I2C_CLR_NACKFCLR_POS (12U) +#define I2C_CLR_NACKFCLR (0x00001000UL) +#define I2C_CLR_TMOUTFCLR_POS (14U) +#define I2C_CLR_TMOUTFCLR (0x00004000UL) +#define I2C_CLR_GENCALLFCLR_POS (20U) +#define I2C_CLR_GENCALLFCLR (0x00100000UL) +#define I2C_CLR_SMBDEFAULTFCLR_POS (21U) +#define I2C_CLR_SMBDEFAULTFCLR (0x00200000UL) +#define I2C_CLR_SMBHOSTFCLR_POS (22U) +#define I2C_CLR_SMBHOSTFCLR (0x00400000UL) +#define I2C_CLR_SMBALRTFCLR_POS (23U) +#define I2C_CLR_SMBALRTFCLR (0x00800000UL) + +/* Bit definition for I2C_DTR register */ +#define I2C_DTR_DT (0xFFU) + +/* Bit definition for I2C_DRR register */ +#define I2C_DRR_DR (0xFFU) + +/* Bit definition for I2C_CCR register */ +#define I2C_CCR_SLOWW_POS (0U) +#define I2C_CCR_SLOWW (0x0000001FUL) +#define I2C_CCR_SHIGHW_POS (8U) +#define I2C_CCR_SHIGHW (0x00001F00UL) +#define I2C_CCR_FREQ_POS (16U) +#define I2C_CCR_FREQ (0x00070000UL) + +/* Bit definition for I2C_FLTR register */ +#define I2C_FLTR_DNF_POS (0U) +#define I2C_FLTR_DNF (0x00000003UL) +#define I2C_FLTR_DNF_0 (0x00000001UL) +#define I2C_FLTR_DNF_1 (0x00000002UL) +#define I2C_FLTR_DNFEN_POS (4U) +#define I2C_FLTR_DNFEN (0x00000010UL) +#define I2C_FLTR_ANFEN_POS (5U) +#define I2C_FLTR_ANFEN (0x00000020UL) + +/******************************************************************************* + Bit definition for Peripheral I2S +*******************************************************************************/ +/* Bit definition for I2S_CTRL register */ +#define I2S_CTRL_TXE_POS (0U) +#define I2S_CTRL_TXE (0x00000001UL) +#define I2S_CTRL_TXIE_POS (1U) +#define I2S_CTRL_TXIE (0x00000002UL) +#define I2S_CTRL_RXE_POS (2U) +#define I2S_CTRL_RXE (0x00000004UL) +#define I2S_CTRL_RXIE_POS (3U) +#define I2S_CTRL_RXIE (0x00000008UL) +#define I2S_CTRL_EIE_POS (4U) +#define I2S_CTRL_EIE (0x00000010UL) +#define I2S_CTRL_WMS_POS (5U) +#define I2S_CTRL_WMS (0x00000020UL) +#define I2S_CTRL_ODD_POS (6U) +#define I2S_CTRL_ODD (0x00000040UL) +#define I2S_CTRL_MCKOE_POS (7U) +#define I2S_CTRL_MCKOE (0x00000080UL) +#define I2S_CTRL_TXBIRQWL_POS (8U) +#define I2S_CTRL_TXBIRQWL (0x00000700UL) +#define I2S_CTRL_RXBIRQWL_POS (12U) +#define I2S_CTRL_RXBIRQWL (0x00007000UL) +#define I2S_CTRL_FIFOR_POS (16U) +#define I2S_CTRL_FIFOR (0x00010000UL) +#define I2S_CTRL_CODECRC_POS (17U) +#define I2S_CTRL_CODECRC (0x00020000UL) +#define I2S_CTRL_I2SPLLSEL_POS (18U) +#define I2S_CTRL_I2SPLLSEL (0x00040000UL) +#define I2S_CTRL_SDOE_POS (19U) +#define I2S_CTRL_SDOE (0x00080000UL) +#define I2S_CTRL_LRCKOE_POS (20U) +#define I2S_CTRL_LRCKOE (0x00100000UL) +#define I2S_CTRL_CKOE_POS (21U) +#define I2S_CTRL_CKOE (0x00200000UL) +#define I2S_CTRL_DUPLEX_POS (22U) +#define I2S_CTRL_DUPLEX (0x00400000UL) +#define I2S_CTRL_CLKSEL_POS (23U) +#define I2S_CTRL_CLKSEL (0x00800000UL) + +/* Bit definition for I2S_SR register */ +#define I2S_SR_TXBA_POS (0U) +#define I2S_SR_TXBA (0x00000001UL) +#define I2S_SR_RXBA_POS (1U) +#define I2S_SR_RXBA (0x00000002UL) +#define I2S_SR_TXBE_POS (2U) +#define I2S_SR_TXBE (0x00000004UL) +#define I2S_SR_TXBF_POS (3U) +#define I2S_SR_TXBF (0x00000008UL) +#define I2S_SR_RXBE_POS (4U) +#define I2S_SR_RXBE (0x00000010UL) +#define I2S_SR_RXBF_POS (5U) +#define I2S_SR_RXBF (0x00000020UL) + +/* Bit definition for I2S_ER register */ +#define I2S_ER_TXERR_POS (0U) +#define I2S_ER_TXERR (0x00000001UL) +#define I2S_ER_RXERR_POS (1U) +#define I2S_ER_RXERR (0x00000002UL) + +/* Bit definition for I2S_CFGR register */ +#define I2S_CFGR_I2SSTD_POS (0U) +#define I2S_CFGR_I2SSTD (0x00000003UL) +#define I2S_CFGR_I2SSTD_0 (0x00000001UL) +#define I2S_CFGR_I2SSTD_1 (0x00000002UL) +#define I2S_CFGR_DATLEN_POS (2U) +#define I2S_CFGR_DATLEN (0x0000000CUL) +#define I2S_CFGR_DATLEN_0 (0x00000004UL) +#define I2S_CFGR_DATLEN_1 (0x00000008UL) +#define I2S_CFGR_CHLEN_POS (4U) +#define I2S_CFGR_CHLEN (0x00000010UL) +#define I2S_CFGR_PCMSYNC_POS (5U) +#define I2S_CFGR_PCMSYNC (0x00000020UL) + +/* Bit definition for I2S_TXBUF register */ +#define I2S_TXBUF (0xFFFFFFFFUL) + +/* Bit definition for I2S_RXBUF register */ +#define I2S_RXBUF (0xFFFFFFFFUL) + +/* Bit definition for I2S_PR register */ +#define I2S_PR_I2SDIV (0x000000FFUL) + +/******************************************************************************* + Bit definition for Peripheral ICG +*******************************************************************************/ +/* Bit definition for ICG_ICG0 register */ +#define ICG_ICG0_SWDTAUTS_POS (0U) +#define ICG_ICG0_SWDTAUTS (0x00000001UL) +#define ICG_ICG0_SWDTITS_POS (1U) +#define ICG_ICG0_SWDTITS (0x00000002UL) +#define ICG_ICG0_SWDTPERI_POS (2U) +#define ICG_ICG0_SWDTPERI (0x0000000CUL) +#define ICG_ICG0_SWDTPERI_0 (0x00000004UL) +#define ICG_ICG0_SWDTPERI_1 (0x00000008UL) +#define ICG_ICG0_SWDTCKS_POS (4U) +#define ICG_ICG0_SWDTCKS (0x000000F0UL) +#define ICG_ICG0_SWDTWDPT_POS (8U) +#define ICG_ICG0_SWDTWDPT (0x00000F00UL) +#define ICG_ICG0_SWDTSLPOFF_POS (12U) +#define ICG_ICG0_SWDTSLPOFF (0x00001000UL) +#define ICG_ICG0_WDTAUTS_POS (16U) +#define ICG_ICG0_WDTAUTS (0x00010000UL) +#define ICG_ICG0_WDTITS_POS (17U) +#define ICG_ICG0_WDTITS (0x00020000UL) +#define ICG_ICG0_WDTPERI_POS (18U) +#define ICG_ICG0_WDTPERI (0x000C0000UL) +#define ICG_ICG0_WDTPERI_0 (0x00040000UL) +#define ICG_ICG0_WDTPERI_1 (0x00080000UL) +#define ICG_ICG0_WDTCKS_POS (20U) +#define ICG_ICG0_WDTCKS (0x00F00000UL) +#define ICG_ICG0_WDTWDPT_POS (24U) +#define ICG_ICG0_WDTWDPT (0x0F000000UL) +#define ICG_ICG0_WDTSLPOFF_POS (28U) +#define ICG_ICG0_WDTSLPOFF (0x10000000UL) + +/* Bit definition for ICG_ICG1 register */ +#define ICG_ICG1_HRCFREQSEL_POS (0U) +#define ICG_ICG1_HRCFREQSEL (0x00000001UL) +#define ICG_ICG1_HRCSTOP_POS (8U) +#define ICG_ICG1_HRCSTOP (0x00000100UL) +#define ICG_ICG1_BOR_LEV_POS (16U) +#define ICG_ICG1_BOR_LEV (0x00030000UL) +#define ICG_ICG1_BOR_LEV_0 (0x00010000UL) +#define ICG_ICG1_BOR_LEV_1 (0x00020000UL) +#define ICG_ICG1_BORDIS_POS (18U) +#define ICG_ICG1_BORDIS (0x00040000UL) +#define ICG_ICG1_SMPCLK_POS (26U) +#define ICG_ICG1_SMPCLK (0x0C000000UL) +#define ICG_ICG1_SMPCLK_0 (0x04000000UL) +#define ICG_ICG1_SMPCLK_1 (0x08000000UL) +#define ICG_ICG1_NMITRG_POS (28U) +#define ICG_ICG1_NMITRG (0x10000000UL) +#define ICG_ICG1_NMIEN_POS (29U) +#define ICG_ICG1_NMIEN (0x20000000UL) +#define ICG_ICG1_NFEN_POS (30U) +#define ICG_ICG1_NFEN (0x40000000UL) +#define ICG_ICG1_NMIICGEN_POS (31U) +#define ICG_ICG1_NMIICGEN (0x80000000UL) + +/* Bit definition for ICG_ICG2 register */ +#define ICG_ICG2 (0xFFFFFFFFUL) + +/* Bit definition for ICG_ICG3 register */ +#define ICG_ICG3 (0xFFFFFFFFUL) + +/* Bit definition for ICG_ICG4 register */ +#define ICG_ICG4 (0xFFFFFFFFUL) + +/* Bit definition for ICG_ICG5 register */ +#define ICG_ICG5 (0xFFFFFFFFUL) + +/* Bit definition for ICG_ICG6 register */ +#define ICG_ICG6 (0xFFFFFFFFUL) + +/* Bit definition for ICG_ICG7 register */ +#define ICG_ICG7 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral INTC +*******************************************************************************/ +/* Bit definition for INTC_NMICR register */ +#define INTC_NMICR_NMITRG_POS (0U) +#define INTC_NMICR_NMITRG (0x00000001UL) +#define INTC_NMICR_NSMPCLK_POS (4U) +#define INTC_NMICR_NSMPCLK (0x00000030UL) +#define INTC_NMICR_NSMPCLK_0 (0x00000010UL) +#define INTC_NMICR_NSMPCLK_1 (0x00000020UL) +#define INTC_NMICR_NFEN_POS (7U) +#define INTC_NMICR_NFEN (0x00000080UL) + +/* Bit definition for INTC_NMIENR register */ +#define INTC_NMIENR_NMIENR_POS (0U) +#define INTC_NMIENR_NMIENR (0x00000001UL) +#define INTC_NMIENR_SWDTENR_POS (1U) +#define INTC_NMIENR_SWDTENR (0x00000002UL) +#define INTC_NMIENR_PVD1ENR_POS (2U) +#define INTC_NMIENR_PVD1ENR (0x00000004UL) +#define INTC_NMIENR_PVD2ENR_POS (3U) +#define INTC_NMIENR_PVD2ENR (0x00000008UL) +#define INTC_NMIENR_XTALSTPENR_POS (5U) +#define INTC_NMIENR_XTALSTPENR (0x00000020UL) +#define INTC_NMIENR_REPENR_POS (8U) +#define INTC_NMIENR_REPENR (0x00000100UL) +#define INTC_NMIENR_RECCENR_POS (9U) +#define INTC_NMIENR_RECCENR (0x00000200UL) +#define INTC_NMIENR_BUSMENR_POS (10U) +#define INTC_NMIENR_BUSMENR (0x00000400UL) +#define INTC_NMIENR_WDTENR_POS (11U) +#define INTC_NMIENR_WDTENR (0x00000800UL) + +/* Bit definition for INTC_NMIFR register */ +#define INTC_NMIFR_NMIFR_POS (0U) +#define INTC_NMIFR_NMIFR (0x00000001UL) +#define INTC_NMIFR_SWDTFR_POS (1U) +#define INTC_NMIFR_SWDTFR (0x00000002UL) +#define INTC_NMIFR_PVD1FR_POS (2U) +#define INTC_NMIFR_PVD1FR (0x00000004UL) +#define INTC_NMIFR_PVD2FR_POS (3U) +#define INTC_NMIFR_PVD2FR (0x00000008UL) +#define INTC_NMIFR_XTALSTPFR_POS (5U) +#define INTC_NMIFR_XTALSTPFR (0x00000020UL) +#define INTC_NMIFR_REPFR_POS (8U) +#define INTC_NMIFR_REPFR (0x00000100UL) +#define INTC_NMIFR_RECCFR_POS (9U) +#define INTC_NMIFR_RECCFR (0x00000200UL) +#define INTC_NMIFR_BUSMFR_POS (10U) +#define INTC_NMIFR_BUSMFR (0x00000400UL) +#define INTC_NMIFR_WDTFR_POS (11U) +#define INTC_NMIFR_WDTFR (0x00000800UL) + +/* Bit definition for INTC_NMICFR register */ +#define INTC_NMICFR_NMICFR_POS (0U) +#define INTC_NMICFR_NMICFR (0x00000001UL) +#define INTC_NMICFR_SWDTCFR_POS (1U) +#define INTC_NMICFR_SWDTCFR (0x00000002UL) +#define INTC_NMICFR_PVD1CFR_POS (2U) +#define INTC_NMICFR_PVD1CFR (0x00000004UL) +#define INTC_NMICFR_PVD2CFR_POS (3U) +#define INTC_NMICFR_PVD2CFR (0x00000008UL) +#define INTC_NMICFR_XTALSTPCFR_POS (5U) +#define INTC_NMICFR_XTALSTPCFR (0x00000020UL) +#define INTC_NMICFR_REPCFR_POS (8U) +#define INTC_NMICFR_REPCFR (0x00000100UL) +#define INTC_NMICFR_RECCCFR_POS (9U) +#define INTC_NMICFR_RECCCFR (0x00000200UL) +#define INTC_NMICFR_BUSMCFR_POS (10U) +#define INTC_NMICFR_BUSMCFR (0x00000400UL) +#define INTC_NMICFR_WDTCFR_POS (11U) +#define INTC_NMICFR_WDTCFR (0x00000800UL) + +/* Bit definition for INTC_EIRQCR register */ +#define INTC_EIRQCR_EIRQTRG_POS (0U) +#define INTC_EIRQCR_EIRQTRG (0x00000003UL) +#define INTC_EIRQCR_EIRQTRG_0 (0x00000001UL) +#define INTC_EIRQCR_EIRQTRG_1 (0x00000002UL) +#define INTC_EIRQCR_EISMPCLK_POS (4U) +#define INTC_EIRQCR_EISMPCLK (0x00000030UL) +#define INTC_EIRQCR_EISMPCLK_0 (0x00000010UL) +#define INTC_EIRQCR_EISMPCLK_1 (0x00000020UL) +#define INTC_EIRQCR_EFEN_POS (7U) +#define INTC_EIRQCR_EFEN (0x00000080UL) + +/* Bit definition for INTC_WUPEN register */ +#define INTC_WUPEN_EIRQWUEN_POS (0U) +#define INTC_WUPEN_EIRQWUEN (0x0000FFFFUL) +#define INTC_WUPEN_EIRQWUEN_0 (0x00000001UL) +#define INTC_WUPEN_EIRQWUEN_1 (0x00000002UL) +#define INTC_WUPEN_EIRQWUEN_2 (0x00000004UL) +#define INTC_WUPEN_EIRQWUEN_3 (0x00000008UL) +#define INTC_WUPEN_EIRQWUEN_4 (0x00000010UL) +#define INTC_WUPEN_EIRQWUEN_5 (0x00000020UL) +#define INTC_WUPEN_EIRQWUEN_6 (0x00000040UL) +#define INTC_WUPEN_EIRQWUEN_7 (0x00000080UL) +#define INTC_WUPEN_EIRQWUEN_8 (0x00000100UL) +#define INTC_WUPEN_EIRQWUEN_9 (0x00000200UL) +#define INTC_WUPEN_EIRQWUEN_10 (0x00000400UL) +#define INTC_WUPEN_EIRQWUEN_11 (0x00000800UL) +#define INTC_WUPEN_EIRQWUEN_12 (0x00001000UL) +#define INTC_WUPEN_EIRQWUEN_13 (0x00002000UL) +#define INTC_WUPEN_EIRQWUEN_14 (0x00004000UL) +#define INTC_WUPEN_EIRQWUEN_15 (0x00008000UL) +#define INTC_WUPEN_SWDTWUEN_POS (16U) +#define INTC_WUPEN_SWDTWUEN (0x00010000UL) +#define INTC_WUPEN_PVD1WUEN_POS (17U) +#define INTC_WUPEN_PVD1WUEN (0x00020000UL) +#define INTC_WUPEN_PVD2WUEN_POS (18U) +#define INTC_WUPEN_PVD2WUEN (0x00040000UL) +#define INTC_WUPEN_CMPI0WUEN_POS (19U) +#define INTC_WUPEN_CMPI0WUEN (0x00080000UL) +#define INTC_WUPEN_WKTMWUEN_POS (20U) +#define INTC_WUPEN_WKTMWUEN (0x00100000UL) +#define INTC_WUPEN_RTCALMWUEN_POS (21U) +#define INTC_WUPEN_RTCALMWUEN (0x00200000UL) +#define INTC_WUPEN_RTCPRDWUEN_POS (22U) +#define INTC_WUPEN_RTCPRDWUEN (0x00400000UL) +#define INTC_WUPEN_TMR0WUEN_POS (23U) +#define INTC_WUPEN_TMR0WUEN (0x00800000UL) +#define INTC_WUPEN_RXWUEN_POS (25U) +#define INTC_WUPEN_RXWUEN (0x02000000UL) + +/* Bit definition for INTC_EIFR register */ +#define INTC_EIFR_EIFR0_POS (0U) +#define INTC_EIFR_EIFR0 (0x00000001UL) +#define INTC_EIFR_EIFR1_POS (1U) +#define INTC_EIFR_EIFR1 (0x00000002UL) +#define INTC_EIFR_EIFR2_POS (2U) +#define INTC_EIFR_EIFR2 (0x00000004UL) +#define INTC_EIFR_EIFR3_POS (3U) +#define INTC_EIFR_EIFR3 (0x00000008UL) +#define INTC_EIFR_EIFR4_POS (4U) +#define INTC_EIFR_EIFR4 (0x00000010UL) +#define INTC_EIFR_EIFR5_POS (5U) +#define INTC_EIFR_EIFR5 (0x00000020UL) +#define INTC_EIFR_EIFR6_POS (6U) +#define INTC_EIFR_EIFR6 (0x00000040UL) +#define INTC_EIFR_EIFR7_POS (7U) +#define INTC_EIFR_EIFR7 (0x00000080UL) +#define INTC_EIFR_EIFR8_POS (8U) +#define INTC_EIFR_EIFR8 (0x00000100UL) +#define INTC_EIFR_EIFR9_POS (9U) +#define INTC_EIFR_EIFR9 (0x00000200UL) +#define INTC_EIFR_EIFR10_POS (10U) +#define INTC_EIFR_EIFR10 (0x00000400UL) +#define INTC_EIFR_EIFR11_POS (11U) +#define INTC_EIFR_EIFR11 (0x00000800UL) +#define INTC_EIFR_EIFR12_POS (12U) +#define INTC_EIFR_EIFR12 (0x00001000UL) +#define INTC_EIFR_EIFR13_POS (13U) +#define INTC_EIFR_EIFR13 (0x00002000UL) +#define INTC_EIFR_EIFR14_POS (14U) +#define INTC_EIFR_EIFR14 (0x00004000UL) +#define INTC_EIFR_EIFR15_POS (15U) +#define INTC_EIFR_EIFR15 (0x00008000UL) + +/* Bit definition for INTC_EIFCR register */ +#define INTC_EIFCR_EIFCR0_POS (0U) +#define INTC_EIFCR_EIFCR0 (0x00000001UL) +#define INTC_EIFCR_EIFCR1_POS (1U) +#define INTC_EIFCR_EIFCR1 (0x00000002UL) +#define INTC_EIFCR_EIFCR2_POS (2U) +#define INTC_EIFCR_EIFCR2 (0x00000004UL) +#define INTC_EIFCR_EIFCR3_POS (3U) +#define INTC_EIFCR_EIFCR3 (0x00000008UL) +#define INTC_EIFCR_EIFCR4_POS (4U) +#define INTC_EIFCR_EIFCR4 (0x00000010UL) +#define INTC_EIFCR_EIFCR5_POS (5U) +#define INTC_EIFCR_EIFCR5 (0x00000020UL) +#define INTC_EIFCR_EIFCR6_POS (6U) +#define INTC_EIFCR_EIFCR6 (0x00000040UL) +#define INTC_EIFCR_EIFCR7_POS (7U) +#define INTC_EIFCR_EIFCR7 (0x00000080UL) +#define INTC_EIFCR_EIFCR8_POS (8U) +#define INTC_EIFCR_EIFCR8 (0x00000100UL) +#define INTC_EIFCR_EIFCR9_POS (9U) +#define INTC_EIFCR_EIFCR9 (0x00000200UL) +#define INTC_EIFCR_EIFCR10_POS (10U) +#define INTC_EIFCR_EIFCR10 (0x00000400UL) +#define INTC_EIFCR_EIFCR11_POS (11U) +#define INTC_EIFCR_EIFCR11 (0x00000800UL) +#define INTC_EIFCR_EIFCR12_POS (12U) +#define INTC_EIFCR_EIFCR12 (0x00001000UL) +#define INTC_EIFCR_EIFCR13_POS (13U) +#define INTC_EIFCR_EIFCR13 (0x00002000UL) +#define INTC_EIFCR_EIFCR14_POS (14U) +#define INTC_EIFCR_EIFCR14 (0x00004000UL) +#define INTC_EIFCR_EIFCR15_POS (15U) +#define INTC_EIFCR_EIFCR15 (0x00008000UL) + +/* Bit definition for INTC_SEL register */ +#define INTC_SEL_INTSEL (0x000001FFUL) +#define INTC_SEL_INTSEL_0 (0x00000001UL) +#define INTC_SEL_INTSEL_1 (0x00000002UL) +#define INTC_SEL_INTSEL_2 (0x00000004UL) +#define INTC_SEL_INTSEL_3 (0x00000008UL) +#define INTC_SEL_INTSEL_4 (0x00000010UL) +#define INTC_SEL_INTSEL_5 (0x00000020UL) +#define INTC_SEL_INTSEL_6 (0x00000040UL) +#define INTC_SEL_INTSEL_7 (0x00000080UL) +#define INTC_SEL_INTSEL_8 (0x00000100UL) + +/* Bit definition for INTC_VSSEL register */ +#define INTC_VSSEL_VSEL0_POS (0U) +#define INTC_VSSEL_VSEL0 (0x00000001UL) +#define INTC_VSSEL_VSEL1_POS (1U) +#define INTC_VSSEL_VSEL1 (0x00000002UL) +#define INTC_VSSEL_VSEL2_POS (2U) +#define INTC_VSSEL_VSEL2 (0x00000004UL) +#define INTC_VSSEL_VSEL3_POS (3U) +#define INTC_VSSEL_VSEL3 (0x00000008UL) +#define INTC_VSSEL_VSEL4_POS (4U) +#define INTC_VSSEL_VSEL4 (0x00000010UL) +#define INTC_VSSEL_VSEL5_POS (5U) +#define INTC_VSSEL_VSEL5 (0x00000020UL) +#define INTC_VSSEL_VSEL6_POS (6U) +#define INTC_VSSEL_VSEL6 (0x00000040UL) +#define INTC_VSSEL_VSEL7_POS (7U) +#define INTC_VSSEL_VSEL7 (0x00000080UL) +#define INTC_VSSEL_VSEL8_POS (8U) +#define INTC_VSSEL_VSEL8 (0x00000100UL) +#define INTC_VSSEL_VSEL9_POS (9U) +#define INTC_VSSEL_VSEL9 (0x00000200UL) +#define INTC_VSSEL_VSEL10_POS (10U) +#define INTC_VSSEL_VSEL10 (0x00000400UL) +#define INTC_VSSEL_VSEL11_POS (11U) +#define INTC_VSSEL_VSEL11 (0x00000800UL) +#define INTC_VSSEL_VSEL12_POS (12U) +#define INTC_VSSEL_VSEL12 (0x00001000UL) +#define INTC_VSSEL_VSEL13_POS (13U) +#define INTC_VSSEL_VSEL13 (0x00002000UL) +#define INTC_VSSEL_VSEL14_POS (14U) +#define INTC_VSSEL_VSEL14 (0x00004000UL) +#define INTC_VSSEL_VSEL15_POS (15U) +#define INTC_VSSEL_VSEL15 (0x00008000UL) +#define INTC_VSSEL_VSEL16_POS (16U) +#define INTC_VSSEL_VSEL16 (0x00010000UL) +#define INTC_VSSEL_VSEL17_POS (17U) +#define INTC_VSSEL_VSEL17 (0x00020000UL) +#define INTC_VSSEL_VSEL18_POS (18U) +#define INTC_VSSEL_VSEL18 (0x00040000UL) +#define INTC_VSSEL_VSEL19_POS (19U) +#define INTC_VSSEL_VSEL19 (0x00080000UL) +#define INTC_VSSEL_VSEL20_POS (20U) +#define INTC_VSSEL_VSEL20 (0x00100000UL) +#define INTC_VSSEL_VSEL21_POS (21U) +#define INTC_VSSEL_VSEL21 (0x00200000UL) +#define INTC_VSSEL_VSEL22_POS (22U) +#define INTC_VSSEL_VSEL22 (0x00400000UL) +#define INTC_VSSEL_VSEL23_POS (23U) +#define INTC_VSSEL_VSEL23 (0x00800000UL) +#define INTC_VSSEL_VSEL24_POS (24U) +#define INTC_VSSEL_VSEL24 (0x01000000UL) +#define INTC_VSSEL_VSEL25_POS (25U) +#define INTC_VSSEL_VSEL25 (0x02000000UL) +#define INTC_VSSEL_VSEL26_POS (26U) +#define INTC_VSSEL_VSEL26 (0x04000000UL) +#define INTC_VSSEL_VSEL27_POS (27U) +#define INTC_VSSEL_VSEL27 (0x08000000UL) +#define INTC_VSSEL_VSEL28_POS (28U) +#define INTC_VSSEL_VSEL28 (0x10000000UL) +#define INTC_VSSEL_VSEL29_POS (29U) +#define INTC_VSSEL_VSEL29 (0x20000000UL) +#define INTC_VSSEL_VSEL30_POS (30U) +#define INTC_VSSEL_VSEL30 (0x40000000UL) +#define INTC_VSSEL_VSEL31_POS (31U) +#define INTC_VSSEL_VSEL31 (0x80000000UL) + +/* Bit definition for INTC_SWIER register */ +#define INTC_SWIER_SWIE0_POS (0U) +#define INTC_SWIER_SWIE0 (0x00000001UL) +#define INTC_SWIER_SWIE1_POS (1U) +#define INTC_SWIER_SWIE1 (0x00000002UL) +#define INTC_SWIER_SWIE2_POS (2U) +#define INTC_SWIER_SWIE2 (0x00000004UL) +#define INTC_SWIER_SWIE3_POS (3U) +#define INTC_SWIER_SWIE3 (0x00000008UL) +#define INTC_SWIER_SWIE4_POS (4U) +#define INTC_SWIER_SWIE4 (0x00000010UL) +#define INTC_SWIER_SWIE5_POS (5U) +#define INTC_SWIER_SWIE5 (0x00000020UL) +#define INTC_SWIER_SWIE6_POS (6U) +#define INTC_SWIER_SWIE6 (0x00000040UL) +#define INTC_SWIER_SWIE7_POS (7U) +#define INTC_SWIER_SWIE7 (0x00000080UL) +#define INTC_SWIER_SWIE8_POS (8U) +#define INTC_SWIER_SWIE8 (0x00000100UL) +#define INTC_SWIER_SWIE9_POS (9U) +#define INTC_SWIER_SWIE9 (0x00000200UL) +#define INTC_SWIER_SWIE10_POS (10U) +#define INTC_SWIER_SWIE10 (0x00000400UL) +#define INTC_SWIER_SWIE11_POS (11U) +#define INTC_SWIER_SWIE11 (0x00000800UL) +#define INTC_SWIER_SWIE12_POS (12U) +#define INTC_SWIER_SWIE12 (0x00001000UL) +#define INTC_SWIER_SWIE13_POS (13U) +#define INTC_SWIER_SWIE13 (0x00002000UL) +#define INTC_SWIER_SWIE14_POS (14U) +#define INTC_SWIER_SWIE14 (0x00004000UL) +#define INTC_SWIER_SWIE15_POS (15U) +#define INTC_SWIER_SWIE15 (0x00008000UL) +#define INTC_SWIER_SWIE16_POS (16U) +#define INTC_SWIER_SWIE16 (0x00010000UL) +#define INTC_SWIER_SWIE17_POS (17U) +#define INTC_SWIER_SWIE17 (0x00020000UL) +#define INTC_SWIER_SWIE18_POS (18U) +#define INTC_SWIER_SWIE18 (0x00040000UL) +#define INTC_SWIER_SWIE19_POS (19U) +#define INTC_SWIER_SWIE19 (0x00080000UL) +#define INTC_SWIER_SWIE20_POS (20U) +#define INTC_SWIER_SWIE20 (0x00100000UL) +#define INTC_SWIER_SWIE21_POS (21U) +#define INTC_SWIER_SWIE21 (0x00200000UL) +#define INTC_SWIER_SWIE22_POS (22U) +#define INTC_SWIER_SWIE22 (0x00400000UL) +#define INTC_SWIER_SWIE23_POS (23U) +#define INTC_SWIER_SWIE23 (0x00800000UL) +#define INTC_SWIER_SWIE24_POS (24U) +#define INTC_SWIER_SWIE24 (0x01000000UL) +#define INTC_SWIER_SWIE25_POS (25U) +#define INTC_SWIER_SWIE25 (0x02000000UL) +#define INTC_SWIER_SWIE26_POS (26U) +#define INTC_SWIER_SWIE26 (0x04000000UL) +#define INTC_SWIER_SWIE27_POS (27U) +#define INTC_SWIER_SWIE27 (0x08000000UL) +#define INTC_SWIER_SWIE28_POS (28U) +#define INTC_SWIER_SWIE28 (0x10000000UL) +#define INTC_SWIER_SWIE29_POS (29U) +#define INTC_SWIER_SWIE29 (0x20000000UL) +#define INTC_SWIER_SWIE30_POS (30U) +#define INTC_SWIER_SWIE30 (0x40000000UL) +#define INTC_SWIER_SWIE31_POS (31U) +#define INTC_SWIER_SWIE31 (0x80000000UL) + +/* Bit definition for INTC_EVTER register */ +#define INTC_EVTER_EVTE0_POS (0U) +#define INTC_EVTER_EVTE0 (0x00000001UL) +#define INTC_EVTER_EVTE1_POS (1U) +#define INTC_EVTER_EVTE1 (0x00000002UL) +#define INTC_EVTER_EVTE2_POS (2U) +#define INTC_EVTER_EVTE2 (0x00000004UL) +#define INTC_EVTER_EVTE3_POS (3U) +#define INTC_EVTER_EVTE3 (0x00000008UL) +#define INTC_EVTER_EVTE4_POS (4U) +#define INTC_EVTER_EVTE4 (0x00000010UL) +#define INTC_EVTER_EVTE5_POS (5U) +#define INTC_EVTER_EVTE5 (0x00000020UL) +#define INTC_EVTER_EVTE6_POS (6U) +#define INTC_EVTER_EVTE6 (0x00000040UL) +#define INTC_EVTER_EVTE7_POS (7U) +#define INTC_EVTER_EVTE7 (0x00000080UL) +#define INTC_EVTER_EVTE8_POS (8U) +#define INTC_EVTER_EVTE8 (0x00000100UL) +#define INTC_EVTER_EVTE9_POS (9U) +#define INTC_EVTER_EVTE9 (0x00000200UL) +#define INTC_EVTER_EVTE10_POS (10U) +#define INTC_EVTER_EVTE10 (0x00000400UL) +#define INTC_EVTER_EVTE11_POS (11U) +#define INTC_EVTER_EVTE11 (0x00000800UL) +#define INTC_EVTER_EVTE12_POS (12U) +#define INTC_EVTER_EVTE12 (0x00001000UL) +#define INTC_EVTER_EVTE13_POS (13U) +#define INTC_EVTER_EVTE13 (0x00002000UL) +#define INTC_EVTER_EVTE14_POS (14U) +#define INTC_EVTER_EVTE14 (0x00004000UL) +#define INTC_EVTER_EVTE15_POS (15U) +#define INTC_EVTER_EVTE15 (0x00008000UL) +#define INTC_EVTER_EVTE16_POS (16U) +#define INTC_EVTER_EVTE16 (0x00010000UL) +#define INTC_EVTER_EVTE17_POS (17U) +#define INTC_EVTER_EVTE17 (0x00020000UL) +#define INTC_EVTER_EVTE18_POS (18U) +#define INTC_EVTER_EVTE18 (0x00040000UL) +#define INTC_EVTER_EVTE19_POS (19U) +#define INTC_EVTER_EVTE19 (0x00080000UL) +#define INTC_EVTER_EVTE20_POS (20U) +#define INTC_EVTER_EVTE20 (0x00100000UL) +#define INTC_EVTER_EVTE21_POS (21U) +#define INTC_EVTER_EVTE21 (0x00200000UL) +#define INTC_EVTER_EVTE22_POS (22U) +#define INTC_EVTER_EVTE22 (0x00400000UL) +#define INTC_EVTER_EVTE23_POS (23U) +#define INTC_EVTER_EVTE23 (0x00800000UL) +#define INTC_EVTER_EVTE24_POS (24U) +#define INTC_EVTER_EVTE24 (0x01000000UL) +#define INTC_EVTER_EVTE25_POS (25U) +#define INTC_EVTER_EVTE25 (0x02000000UL) +#define INTC_EVTER_EVTE26_POS (26U) +#define INTC_EVTER_EVTE26 (0x04000000UL) +#define INTC_EVTER_EVTE27_POS (27U) +#define INTC_EVTER_EVTE27 (0x08000000UL) +#define INTC_EVTER_EVTE28_POS (28U) +#define INTC_EVTER_EVTE28 (0x10000000UL) +#define INTC_EVTER_EVTE29_POS (29U) +#define INTC_EVTER_EVTE29 (0x20000000UL) +#define INTC_EVTER_EVTE30_POS (30U) +#define INTC_EVTER_EVTE30 (0x40000000UL) +#define INTC_EVTER_EVTE31_POS (31U) +#define INTC_EVTER_EVTE31 (0x80000000UL) + +/* Bit definition for INTC_IER register */ +#define INTC_IER_IER0_POS (0U) +#define INTC_IER_IER0 (0x00000001UL) +#define INTC_IER_IER1_POS (1U) +#define INTC_IER_IER1 (0x00000002UL) +#define INTC_IER_IER2_POS (2U) +#define INTC_IER_IER2 (0x00000004UL) +#define INTC_IER_IER3_POS (3U) +#define INTC_IER_IER3 (0x00000008UL) +#define INTC_IER_IER4_POS (4U) +#define INTC_IER_IER4 (0x00000010UL) +#define INTC_IER_IER5_POS (5U) +#define INTC_IER_IER5 (0x00000020UL) +#define INTC_IER_IER6_POS (6U) +#define INTC_IER_IER6 (0x00000040UL) +#define INTC_IER_IER7_POS (7U) +#define INTC_IER_IER7 (0x00000080UL) +#define INTC_IER_IER8_POS (8U) +#define INTC_IER_IER8 (0x00000100UL) +#define INTC_IER_IER9_POS (9U) +#define INTC_IER_IER9 (0x00000200UL) +#define INTC_IER_IER10_POS (10U) +#define INTC_IER_IER10 (0x00000400UL) +#define INTC_IER_IER11_POS (11U) +#define INTC_IER_IER11 (0x00000800UL) +#define INTC_IER_IER12_POS (12U) +#define INTC_IER_IER12 (0x00001000UL) +#define INTC_IER_IER13_POS (13U) +#define INTC_IER_IER13 (0x00002000UL) +#define INTC_IER_IER14_POS (14U) +#define INTC_IER_IER14 (0x00004000UL) +#define INTC_IER_IER15_POS (15U) +#define INTC_IER_IER15 (0x00008000UL) +#define INTC_IER_IER16_POS (16U) +#define INTC_IER_IER16 (0x00010000UL) +#define INTC_IER_IER17_POS (17U) +#define INTC_IER_IER17 (0x00020000UL) +#define INTC_IER_IER18_POS (18U) +#define INTC_IER_IER18 (0x00040000UL) +#define INTC_IER_IER19_POS (19U) +#define INTC_IER_IER19 (0x00080000UL) +#define INTC_IER_IER20_POS (20U) +#define INTC_IER_IER20 (0x00100000UL) +#define INTC_IER_IER21_POS (21U) +#define INTC_IER_IER21 (0x00200000UL) +#define INTC_IER_IER22_POS (22U) +#define INTC_IER_IER22 (0x00400000UL) +#define INTC_IER_IER23_POS (23U) +#define INTC_IER_IER23 (0x00800000UL) +#define INTC_IER_IER24_POS (24U) +#define INTC_IER_IER24 (0x01000000UL) +#define INTC_IER_IER25_POS (25U) +#define INTC_IER_IER25 (0x02000000UL) +#define INTC_IER_IER26_POS (26U) +#define INTC_IER_IER26 (0x04000000UL) +#define INTC_IER_IER27_POS (27U) +#define INTC_IER_IER27 (0x08000000UL) +#define INTC_IER_IER28_POS (28U) +#define INTC_IER_IER28 (0x10000000UL) +#define INTC_IER_IER29_POS (29U) +#define INTC_IER_IER29 (0x20000000UL) +#define INTC_IER_IER30_POS (30U) +#define INTC_IER_IER30 (0x40000000UL) +#define INTC_IER_IER31_POS (31U) +#define INTC_IER_IER31 (0x80000000UL) + +/******************************************************************************* + Bit definition for Peripheral KEYSCAN +*******************************************************************************/ +/* Bit definition for KEYSCAN_SCR register */ +#define KEYSCAN_SCR_KEYINSEL_POS (0U) +#define KEYSCAN_SCR_KEYINSEL (0x0000FFFFUL) +#define KEYSCAN_SCR_KEYOUTSEL_POS (16U) +#define KEYSCAN_SCR_KEYOUTSEL (0x00070000UL) +#define KEYSCAN_SCR_CKSEL_POS (20U) +#define KEYSCAN_SCR_CKSEL (0x00300000UL) +#define KEYSCAN_SCR_CKSEL_0 (0x00100000UL) +#define KEYSCAN_SCR_CKSEL_1 (0x00200000UL) +#define KEYSCAN_SCR_T_LLEVEL_POS (24U) +#define KEYSCAN_SCR_T_LLEVEL (0x1F000000UL) +#define KEYSCAN_SCR_T_HIZ_POS (29U) +#define KEYSCAN_SCR_T_HIZ (0xE0000000UL) + +/* Bit definition for KEYSCAN_SER register */ +#define KEYSCAN_SER_SEN (0x00000001UL) + +/* Bit definition for KEYSCAN_SSR register */ +#define KEYSCAN_SSR_INDEX (0x00000007UL) + +/******************************************************************************* + Bit definition for Peripheral MPU +*******************************************************************************/ +/* Bit definition for MPU_RGD register */ +#define MPU_RGD_MPURGSIZE_POS (0U) +#define MPU_RGD_MPURGSIZE (0x0000001FUL) +#define MPU_RGD_MPURGADDR_POS (5U) +#define MPU_RGD_MPURGADDR (0xFFFFFFE0UL) + +/* Bit definition for MPU_RGCR register */ +#define MPU_RGCR_S2RGRP_POS (0U) +#define MPU_RGCR_S2RGRP (0x00000001UL) +#define MPU_RGCR_S2RGWP_POS (1U) +#define MPU_RGCR_S2RGWP (0x00000002UL) +#define MPU_RGCR_S2RGE_POS (7U) +#define MPU_RGCR_S2RGE (0x00000080UL) +#define MPU_RGCR_S1RGRP_POS (8U) +#define MPU_RGCR_S1RGRP (0x00000100UL) +#define MPU_RGCR_S1RGWP_POS (9U) +#define MPU_RGCR_S1RGWP (0x00000200UL) +#define MPU_RGCR_S1RGE_POS (15U) +#define MPU_RGCR_S1RGE (0x00008000UL) +#define MPU_RGCR_FRGRP_POS (16U) +#define MPU_RGCR_FRGRP (0x00010000UL) +#define MPU_RGCR_FRGWP_POS (17U) +#define MPU_RGCR_FRGWP (0x00020000UL) +#define MPU_RGCR_FRGE_POS (23U) +#define MPU_RGCR_FRGE (0x00800000UL) + +/* Bit definition for MPU_CR register */ +#define MPU_CR_SMPU2BRP_POS (0U) +#define MPU_CR_SMPU2BRP (0x00000001UL) +#define MPU_CR_SMPU2BWP_POS (1U) +#define MPU_CR_SMPU2BWP (0x00000002UL) +#define MPU_CR_SMPU2ACT_POS (2U) +#define MPU_CR_SMPU2ACT (0x0000000CUL) +#define MPU_CR_SMPU2ACT_0 (0x00000004UL) +#define MPU_CR_SMPU2ACT_1 (0x00000008UL) +#define MPU_CR_SMPU2E_POS (7U) +#define MPU_CR_SMPU2E (0x00000080UL) +#define MPU_CR_SMPU1BRP_POS (8U) +#define MPU_CR_SMPU1BRP (0x00000100UL) +#define MPU_CR_SMPU1BWP_POS (9U) +#define MPU_CR_SMPU1BWP (0x00000200UL) +#define MPU_CR_SMPU1ACT_POS (10U) +#define MPU_CR_SMPU1ACT (0x00000C00UL) +#define MPU_CR_SMPU1ACT_0 (0x00000400UL) +#define MPU_CR_SMPU1ACT_1 (0x00000800UL) +#define MPU_CR_SMPU1E_POS (15U) +#define MPU_CR_SMPU1E (0x00008000UL) +#define MPU_CR_FMPUBRP_POS (16U) +#define MPU_CR_FMPUBRP (0x00010000UL) +#define MPU_CR_FMPUBWP_POS (17U) +#define MPU_CR_FMPUBWP (0x00020000UL) +#define MPU_CR_FMPUACT_POS (18U) +#define MPU_CR_FMPUACT (0x000C0000UL) +#define MPU_CR_FMPUACT_0 (0x00040000UL) +#define MPU_CR_FMPUACT_1 (0x00080000UL) +#define MPU_CR_FMPUE_POS (23U) +#define MPU_CR_FMPUE (0x00800000UL) + +/* Bit definition for MPU_SR register */ +#define MPU_SR_SMPU2EAF_POS (0U) +#define MPU_SR_SMPU2EAF (0x00000001UL) +#define MPU_SR_SMPU1EAF_POS (8U) +#define MPU_SR_SMPU1EAF (0x00000100UL) +#define MPU_SR_FMPUEAF_POS (16U) +#define MPU_SR_FMPUEAF (0x00010000UL) + +/* Bit definition for MPU_ECLR register */ +#define MPU_ECLR_SMPU2ECLR_POS (0U) +#define MPU_ECLR_SMPU2ECLR (0x00000001UL) +#define MPU_ECLR_SMPU1ECLR_POS (8U) +#define MPU_ECLR_SMPU1ECLR (0x00000100UL) +#define MPU_ECLR_FMPUECLR_POS (16U) +#define MPU_ECLR_FMPUECLR (0x00010000UL) + +/* Bit definition for MPU_WP register */ +#define MPU_WP_MPUWE_POS (0U) +#define MPU_WP_MPUWE (0x00000001UL) +#define MPU_WP_WKEY_POS (1U) +#define MPU_WP_WKEY (0x0000FFFEUL) + +/* Bit definition for MPU_IPPR register */ +#define MPU_IPPR_AESRDP_POS (0U) +#define MPU_IPPR_AESRDP (0x00000001UL) +#define MPU_IPPR_AESWRP_POS (1U) +#define MPU_IPPR_AESWRP (0x00000002UL) +#define MPU_IPPR_HASHRDP_POS (2U) +#define MPU_IPPR_HASHRDP (0x00000004UL) +#define MPU_IPPR_HASHWRP_POS (3U) +#define MPU_IPPR_HASHWRP (0x00000008UL) +#define MPU_IPPR_TRNGRDP_POS (4U) +#define MPU_IPPR_TRNGRDP (0x00000010UL) +#define MPU_IPPR_TRNGWRP_POS (5U) +#define MPU_IPPR_TRNGWRP (0x00000020UL) +#define MPU_IPPR_CRCRDP_POS (6U) +#define MPU_IPPR_CRCRDP (0x00000040UL) +#define MPU_IPPR_CRCWRP_POS (7U) +#define MPU_IPPR_CRCWRP (0x00000080UL) +#define MPU_IPPR_EFMRDP_POS (8U) +#define MPU_IPPR_EFMRDP (0x00000100UL) +#define MPU_IPPR_EFMWRP_POS (9U) +#define MPU_IPPR_EFMWRP (0x00000200UL) +#define MPU_IPPR_WDTRDP_POS (12U) +#define MPU_IPPR_WDTRDP (0x00001000UL) +#define MPU_IPPR_WDTWRP_POS (13U) +#define MPU_IPPR_WDTWRP (0x00002000UL) +#define MPU_IPPR_SWDTRDP_POS (14U) +#define MPU_IPPR_SWDTRDP (0x00004000UL) +#define MPU_IPPR_SWDTWRP_POS (15U) +#define MPU_IPPR_SWDTWRP (0x00008000UL) +#define MPU_IPPR_BKSRAMRDP_POS (16U) +#define MPU_IPPR_BKSRAMRDP (0x00010000UL) +#define MPU_IPPR_BKSRAMWRP_POS (17U) +#define MPU_IPPR_BKSRAMWRP (0x00020000UL) +#define MPU_IPPR_RTCRDP_POS (18U) +#define MPU_IPPR_RTCRDP (0x00040000UL) +#define MPU_IPPR_RTCWRP_POS (19U) +#define MPU_IPPR_RTCWRP (0x00080000UL) +#define MPU_IPPR_DMPURDP_POS (20U) +#define MPU_IPPR_DMPURDP (0x00100000UL) +#define MPU_IPPR_DMPUWRP_POS (21U) +#define MPU_IPPR_DMPUWRP (0x00200000UL) +#define MPU_IPPR_SRAMCRDP_POS (22U) +#define MPU_IPPR_SRAMCRDP (0x00400000UL) +#define MPU_IPPR_SRAMCWRP_POS (23U) +#define MPU_IPPR_SRAMCWRP (0x00800000UL) +#define MPU_IPPR_INTCRDP_POS (24U) +#define MPU_IPPR_INTCRDP (0x01000000UL) +#define MPU_IPPR_INTCWRP_POS (25U) +#define MPU_IPPR_INTCWRP (0x02000000UL) +#define MPU_IPPR_SYSCRDP_POS (26U) +#define MPU_IPPR_SYSCRDP (0x04000000UL) +#define MPU_IPPR_SYSCWRP_POS (27U) +#define MPU_IPPR_SYSCWRP (0x08000000UL) +#define MPU_IPPR_MSTPRDP_POS (28U) +#define MPU_IPPR_MSTPRDP (0x10000000UL) +#define MPU_IPPR_MSTPWRP_POS (29U) +#define MPU_IPPR_MSTPWRP (0x20000000UL) +#define MPU_IPPR_BUSERRE_POS (31U) +#define MPU_IPPR_BUSERRE (0x80000000UL) + +/******************************************************************************* + Bit definition for Peripheral OTS +*******************************************************************************/ +/* Bit definition for OTS_CTL register */ +#define OTS_CTL_OTSST_POS (0U) +#define OTS_CTL_OTSST (0x0001U) +#define OTS_CTL_OTSCK_POS (1U) +#define OTS_CTL_OTSCK (0x0002U) +#define OTS_CTL_OTSIE_POS (2U) +#define OTS_CTL_OTSIE (0x0004U) +#define OTS_CTL_TSSTP_POS (3U) +#define OTS_CTL_TSSTP (0x0008U) + +/* Bit definition for OTS_DR1 register */ +#define OTS_DR1 (0xFFFFU) + +/* Bit definition for OTS_DR2 register */ +#define OTS_DR2 (0xFFFFU) + +/* Bit definition for OTS_ECR register */ +#define OTS_ECR (0xFFFFU) + +/******************************************************************************* + Bit definition for Peripheral PERIC +*******************************************************************************/ +/* Bit definition for PERIC_USBFS_SYCTLREG register */ +#define PERIC_USBFS_SYCTLREG_DFB_POS (0U) +#define PERIC_USBFS_SYCTLREG_DFB (0x00000001UL) +#define PERIC_USBFS_SYCTLREG_SOFEN_POS (1U) +#define PERIC_USBFS_SYCTLREG_SOFEN (0x00000002UL) + +/* Bit definition for PERIC_SDIOC_SYCTLREG register */ +#define PERIC_SDIOC_SYCTLREG_SELMMC1_POS (1U) +#define PERIC_SDIOC_SYCTLREG_SELMMC1 (0x00000002UL) +#define PERIC_SDIOC_SYCTLREG_SELMMC2_POS (3U) +#define PERIC_SDIOC_SYCTLREG_SELMMC2 (0x00000008UL) + +/******************************************************************************* + Bit definition for Peripheral PWC +*******************************************************************************/ +/* Bit definition for PWC_FCG0 register */ +#define PWC_FCG0_SRAMH_POS (0U) +#define PWC_FCG0_SRAMH (0x00000001UL) +#define PWC_FCG0_SRAM12_POS (4U) +#define PWC_FCG0_SRAM12 (0x00000010UL) +#define PWC_FCG0_SRAM3_POS (8U) +#define PWC_FCG0_SRAM3 (0x00000100UL) +#define PWC_FCG0_SRAMRET_POS (10U) +#define PWC_FCG0_SRAMRET (0x00000400UL) +#define PWC_FCG0_DMA1_POS (14U) +#define PWC_FCG0_DMA1 (0x00004000UL) +#define PWC_FCG0_DMA2_POS (15U) +#define PWC_FCG0_DMA2 (0x00008000UL) +#define PWC_FCG0_FCM_POS (16U) +#define PWC_FCG0_FCM (0x00010000UL) +#define PWC_FCG0_AOS_POS (17U) +#define PWC_FCG0_AOS (0x00020000UL) +#define PWC_FCG0_AES_POS (20U) +#define PWC_FCG0_AES (0x00100000UL) +#define PWC_FCG0_HASH_POS (21U) +#define PWC_FCG0_HASH (0x00200000UL) +#define PWC_FCG0_TRNG_POS (22U) +#define PWC_FCG0_TRNG (0x00400000UL) +#define PWC_FCG0_CRC_POS (23U) +#define PWC_FCG0_CRC (0x00800000UL) +#define PWC_FCG0_DCU1_POS (24U) +#define PWC_FCG0_DCU1 (0x01000000UL) +#define PWC_FCG0_DCU2_POS (25U) +#define PWC_FCG0_DCU2 (0x02000000UL) +#define PWC_FCG0_DCU3_POS (26U) +#define PWC_FCG0_DCU3 (0x04000000UL) +#define PWC_FCG0_DCU4_POS (27U) +#define PWC_FCG0_DCU4 (0x08000000UL) +#define PWC_FCG0_KEY_POS (31U) +#define PWC_FCG0_KEY (0x80000000UL) + +/* Bit definition for PWC_FCG1 register */ +#define PWC_FCG1_CAN_POS (0U) +#define PWC_FCG1_CAN (0x00000001UL) +#define PWC_FCG1_QSPI_POS (3U) +#define PWC_FCG1_QSPI (0x00000008UL) +#define PWC_FCG1_I2C1_POS (4U) +#define PWC_FCG1_I2C1 (0x00000010UL) +#define PWC_FCG1_I2C2_POS (5U) +#define PWC_FCG1_I2C2 (0x00000020UL) +#define PWC_FCG1_I2C3_POS (6U) +#define PWC_FCG1_I2C3 (0x00000040UL) +#define PWC_FCG1_USBFS_POS (8U) +#define PWC_FCG1_USBFS (0x00000100UL) +#define PWC_FCG1_SDIOC1_POS (10U) +#define PWC_FCG1_SDIOC1 (0x00000400UL) +#define PWC_FCG1_SDIOC2_POS (11U) +#define PWC_FCG1_SDIOC2 (0x00000800UL) +#define PWC_FCG1_I2S1_POS (12U) +#define PWC_FCG1_I2S1 (0x00001000UL) +#define PWC_FCG1_I2S2_POS (13U) +#define PWC_FCG1_I2S2 (0x00002000UL) +#define PWC_FCG1_I2S3_POS (14U) +#define PWC_FCG1_I2S3 (0x00004000UL) +#define PWC_FCG1_I2S4_POS (15U) +#define PWC_FCG1_I2S4 (0x00008000UL) +#define PWC_FCG1_SPI1_POS (16U) +#define PWC_FCG1_SPI1 (0x00010000UL) +#define PWC_FCG1_SPI2_POS (17U) +#define PWC_FCG1_SPI2 (0x00020000UL) +#define PWC_FCG1_SPI3_POS (18U) +#define PWC_FCG1_SPI3 (0x00040000UL) +#define PWC_FCG1_SPI4_POS (19U) +#define PWC_FCG1_SPI4 (0x00080000UL) +#define PWC_FCG1_USART1_POS (24U) +#define PWC_FCG1_USART1 (0x01000000UL) +#define PWC_FCG1_USART2_POS (25U) +#define PWC_FCG1_USART2 (0x02000000UL) +#define PWC_FCG1_USART3_POS (26U) +#define PWC_FCG1_USART3 (0x04000000UL) +#define PWC_FCG1_USART4_POS (27U) +#define PWC_FCG1_USART4 (0x08000000UL) + +/* Bit definition for PWC_FCG2 register */ +#define PWC_FCG2_TIMER0_1_POS (0U) +#define PWC_FCG2_TIMER0_1 (0x00000001UL) +#define PWC_FCG2_TIMER0_2_POS (1U) +#define PWC_FCG2_TIMER0_2 (0x00000002UL) +#define PWC_FCG2_TIMERA_1_POS (2U) +#define PWC_FCG2_TIMERA_1 (0x00000004UL) +#define PWC_FCG2_TIMERA_2_POS (3U) +#define PWC_FCG2_TIMERA_2 (0x00000008UL) +#define PWC_FCG2_TIMERA_3_POS (4U) +#define PWC_FCG2_TIMERA_3 (0x00000010UL) +#define PWC_FCG2_TIMERA_4_POS (5U) +#define PWC_FCG2_TIMERA_4 (0x00000020UL) +#define PWC_FCG2_TIMERA_5_POS (6U) +#define PWC_FCG2_TIMERA_5 (0x00000040UL) +#define PWC_FCG2_TIMERA_6_POS (7U) +#define PWC_FCG2_TIMERA_6 (0x00000080UL) +#define PWC_FCG2_TIMER4_1_POS (8U) +#define PWC_FCG2_TIMER4_1 (0x00000100UL) +#define PWC_FCG2_TIMER4_2_POS (9U) +#define PWC_FCG2_TIMER4_2 (0x00000200UL) +#define PWC_FCG2_TIMER4_3_POS (10U) +#define PWC_FCG2_TIMER4_3 (0x00000400UL) +#define PWC_FCG2_EMB_POS (15U) +#define PWC_FCG2_EMB (0x00008000UL) +#define PWC_FCG2_TIMER6_1_POS (16U) +#define PWC_FCG2_TIMER6_1 (0x00010000UL) +#define PWC_FCG2_TIMER6_2_POS (17U) +#define PWC_FCG2_TIMER6_2 (0x00020000UL) +#define PWC_FCG2_TIMER6_3_POS (18U) +#define PWC_FCG2_TIMER6_3 (0x00040000UL) + +/* Bit definition for PWC_FCG3 register */ +#define PWC_FCG3_ADC1_POS (0U) +#define PWC_FCG3_ADC1 (0x00000001UL) +#define PWC_FCG3_ADC2_POS (1U) +#define PWC_FCG3_ADC2 (0x00000002UL) +#define PWC_FCG3_CMP_POS (8U) +#define PWC_FCG3_CMP (0x00000100UL) +#define PWC_FCG3_OTS_POS (12U) +#define PWC_FCG3_OTS (0x00001000UL) + +/* Bit definition for PWC_FCG0PC register */ +#define PWC_FCG0PC_PRT0_POS (0U) +#define PWC_FCG0PC_PRT0 (0x00000001UL) +#define PWC_FCG0PC_FCG0PCWE_POS (16U) +#define PWC_FCG0PC_FCG0PCWE (0xFFFF0000UL) + +/* Bit definition for PWC_WKTCR register */ +#define PWC_WKTCR_WKTMCMP_POS (0U) +#define PWC_WKTCR_WKTMCMP (0x0FFFU) +#define PWC_WKTCR_WKOVF_POS (12U) +#define PWC_WKTCR_WKOVF (0x1000U) +#define PWC_WKTCR_WKCKS_POS (13U) +#define PWC_WKTCR_WKCKS (0x6000U) +#define PWC_WKTCR_WKCKS_0 (0x2000U) +#define PWC_WKTCR_WKCKS_1 (0x4000U) +#define PWC_WKTCR_WKTCE_POS (15U) +#define PWC_WKTCR_WKTCE (0x8000U) + +/* Bit definition for PWC_STPMCR register */ +#define PWC_STPMCR_FLNWT_POS (0U) +#define PWC_STPMCR_FLNWT (0x0001U) +#define PWC_STPMCR_CKSMRC_POS (1U) +#define PWC_STPMCR_CKSMRC (0x0002U) +#define PWC_STPMCR_STOP_POS (15U) +#define PWC_STPMCR_STOP (0x8000U) + +/* Bit definition for PWC_RAMPC0 register */ +#define PWC_RAMPC0_RAMPDC0_POS (0U) +#define PWC_RAMPC0_RAMPDC0 (0x00000001UL) +#define PWC_RAMPC0_RAMPDC1_POS (1U) +#define PWC_RAMPC0_RAMPDC1 (0x00000002UL) +#define PWC_RAMPC0_RAMPDC2_POS (2U) +#define PWC_RAMPC0_RAMPDC2 (0x00000004UL) +#define PWC_RAMPC0_RAMPDC3_POS (3U) +#define PWC_RAMPC0_RAMPDC3 (0x00000008UL) +#define PWC_RAMPC0_RAMPDC4_POS (4U) +#define PWC_RAMPC0_RAMPDC4 (0x00000010UL) +#define PWC_RAMPC0_RAMPDC5_POS (5U) +#define PWC_RAMPC0_RAMPDC5 (0x00000020UL) +#define PWC_RAMPC0_RAMPDC6_POS (6U) +#define PWC_RAMPC0_RAMPDC6 (0x00000040UL) +#define PWC_RAMPC0_RAMPDC7_POS (7U) +#define PWC_RAMPC0_RAMPDC7 (0x00000080UL) +#define PWC_RAMPC0_RAMPDC8_POS (8U) +#define PWC_RAMPC0_RAMPDC8 (0x00000100UL) + +/* Bit definition for PWC_RAMOPM register */ +#define PWC_RAMOPM (0xFFFFU) + +/* Bit definition for PWC_PVDICR register */ +#define PWC_PVDICR_PVD1NMIS_POS (0U) +#define PWC_PVDICR_PVD1NMIS (0x01U) +#define PWC_PVDICR_PVD2NMIS_POS (4U) +#define PWC_PVDICR_PVD2NMIS (0x10U) + +/* Bit definition for PWC_PVDDSR register */ +#define PWC_PVDDSR_PVD1MON_POS (0U) +#define PWC_PVDDSR_PVD1MON (0x01U) +#define PWC_PVDDSR_PVD1DETFLG_POS (1U) +#define PWC_PVDDSR_PVD1DETFLG (0x02U) +#define PWC_PVDDSR_PVD2MON_POS (4U) +#define PWC_PVDDSR_PVD2MON (0x10U) +#define PWC_PVDDSR_PVD2DETFLG_POS (5U) +#define PWC_PVDDSR_PVD2DETFLG (0x20U) + +/* Bit definition for PWC_FPRC register */ +#define PWC_FPRC_FPRCB0_POS (0U) +#define PWC_FPRC_FPRCB0 (0x0001U) +#define PWC_FPRC_FPRCB1_POS (1U) +#define PWC_FPRC_FPRCB1 (0x0002U) +#define PWC_FPRC_FPRCB2_POS (2U) +#define PWC_FPRC_FPRCB2 (0x0004U) +#define PWC_FPRC_FPRCB3_POS (3U) +#define PWC_FPRC_FPRCB3 (0x0008U) +#define PWC_FPRC_FPRCWE_POS (8U) +#define PWC_FPRC_FPRCWE (0xFF00U) + +/* Bit definition for PWC_PWRC0 register */ +#define PWC_PWRC0_PDMDS_POS (0U) +#define PWC_PWRC0_PDMDS (0x03U) +#define PWC_PWRC0_PDMDS_0 (0x01U) +#define PWC_PWRC0_PDMDS_1 (0x02U) +#define PWC_PWRC0_VVDRSD_POS (2U) +#define PWC_PWRC0_VVDRSD (0x04U) +#define PWC_PWRC0_RETRAMSD_POS (3U) +#define PWC_PWRC0_RETRAMSD (0x08U) +#define PWC_PWRC0_IORTN_POS (4U) +#define PWC_PWRC0_IORTN (0x30U) +#define PWC_PWRC0_IORTN_0 (0x10U) +#define PWC_PWRC0_IORTN_1 (0x20U) +#define PWC_PWRC0_PWDN_POS (7U) +#define PWC_PWRC0_PWDN (0x80U) + +/* Bit definition for PWC_PWRC1 register */ +#define PWC_PWRC1_VPLLSD_POS (0U) +#define PWC_PWRC1_VPLLSD (0x01U) +#define PWC_PWRC1_VHRCSD_POS (1U) +#define PWC_PWRC1_VHRCSD (0x02U) +#define PWC_PWRC1_STPDAS_POS (6U) +#define PWC_PWRC1_STPDAS (0xC0U) +#define PWC_PWRC1_STPDAS_0 (0x40U) +#define PWC_PWRC1_STPDAS_1 (0x80U) + +/* Bit definition for PWC_PWRC2 register */ +#define PWC_PWRC2_DDAS_POS (0U) +#define PWC_PWRC2_DDAS (0x0FU) +#define PWC_PWRC2_DDAS_0 (0x01U) +#define PWC_PWRC2_DDAS_1 (0x02U) +#define PWC_PWRC2_DDAS_2 (0x04U) +#define PWC_PWRC2_DDAS_3 (0x08U) +#define PWC_PWRC2_DVS_POS (4U) +#define PWC_PWRC2_DVS (0x30U) +#define PWC_PWRC2_DVS_0 (0x10U) +#define PWC_PWRC2_DVS_1 (0x20U) + +/* Bit definition for PWC_PWRC3 register */ +#define PWC_PWRC3_PDTS_POS (2U) +#define PWC_PWRC3_PDTS (0x04U) + +/* Bit definition for PWC_PDWKE0 register */ +#define PWC_PDWKE0_WKE00_POS (0U) +#define PWC_PDWKE0_WKE00 (0x01U) +#define PWC_PDWKE0_WKE01_POS (1U) +#define PWC_PDWKE0_WKE01 (0x02U) +#define PWC_PDWKE0_WKE02_POS (2U) +#define PWC_PDWKE0_WKE02 (0x04U) +#define PWC_PDWKE0_WKE03_POS (3U) +#define PWC_PDWKE0_WKE03 (0x08U) +#define PWC_PDWKE0_WKE10_POS (4U) +#define PWC_PDWKE0_WKE10 (0x10U) +#define PWC_PDWKE0_WKE11_POS (5U) +#define PWC_PDWKE0_WKE11 (0x20U) +#define PWC_PDWKE0_WKE12_POS (6U) +#define PWC_PDWKE0_WKE12 (0x40U) +#define PWC_PDWKE0_WKE13_POS (7U) +#define PWC_PDWKE0_WKE13 (0x80U) + +/* Bit definition for PWC_PDWKE1 register */ +#define PWC_PDWKE1_WKE20_POS (0U) +#define PWC_PDWKE1_WKE20 (0x01U) +#define PWC_PDWKE1_WKE21_POS (1U) +#define PWC_PDWKE1_WKE21 (0x02U) +#define PWC_PDWKE1_WKE22_POS (2U) +#define PWC_PDWKE1_WKE22 (0x04U) +#define PWC_PDWKE1_WKE23_POS (3U) +#define PWC_PDWKE1_WKE23 (0x08U) +#define PWC_PDWKE1_WKE30_POS (4U) +#define PWC_PDWKE1_WKE30 (0x10U) +#define PWC_PDWKE1_WKE31_POS (5U) +#define PWC_PDWKE1_WKE31 (0x20U) +#define PWC_PDWKE1_WKE32_POS (6U) +#define PWC_PDWKE1_WKE32 (0x40U) +#define PWC_PDWKE1_WKE33_POS (7U) +#define PWC_PDWKE1_WKE33 (0x80U) + +/* Bit definition for PWC_PDWKE2 register */ +#define PWC_PDWKE2_VD1WKE_POS (0U) +#define PWC_PDWKE2_VD1WKE (0x01U) +#define PWC_PDWKE2_VD2WKE_POS (1U) +#define PWC_PDWKE2_VD2WKE (0x02U) +#define PWC_PDWKE2_NMIWKE_POS (2U) +#define PWC_PDWKE2_NMIWKE (0x04U) +#define PWC_PDWKE2_RTCPRDWKE_POS (4U) +#define PWC_PDWKE2_RTCPRDWKE (0x10U) +#define PWC_PDWKE2_RTCALMWKE_POS (5U) +#define PWC_PDWKE2_RTCALMWKE (0x20U) +#define PWC_PDWKE2_WKTMWKE_POS (7U) +#define PWC_PDWKE2_WKTMWKE (0x80U) + +/* Bit definition for PWC_PDWKES register */ +#define PWC_PDWKES_WK0EGS_POS (0U) +#define PWC_PDWKES_WK0EGS (0x01U) +#define PWC_PDWKES_WK1EGS_POS (1U) +#define PWC_PDWKES_WK1EGS (0x02U) +#define PWC_PDWKES_WK2EGS_POS (2U) +#define PWC_PDWKES_WK2EGS (0x04U) +#define PWC_PDWKES_WK3EGS_POS (3U) +#define PWC_PDWKES_WK3EGS (0x08U) +#define PWC_PDWKES_VD1EGS_POS (4U) +#define PWC_PDWKES_VD1EGS (0x10U) +#define PWC_PDWKES_VD2EGS_POS (5U) +#define PWC_PDWKES_VD2EGS (0x20U) +#define PWC_PDWKES_NMIEGS_POS (6U) +#define PWC_PDWKES_NMIEGS (0x40U) + +/* Bit definition for PWC_PDWKF0 register */ +#define PWC_PDWKF0_PTWK0F_POS (0U) +#define PWC_PDWKF0_PTWK0F (0x01U) +#define PWC_PDWKF0_PTWK1F_POS (1U) +#define PWC_PDWKF0_PTWK1F (0x02U) +#define PWC_PDWKF0_PTWK2F_POS (2U) +#define PWC_PDWKF0_PTWK2F (0x04U) +#define PWC_PDWKF0_PTWK3F_POS (3U) +#define PWC_PDWKF0_PTWK3F (0x08U) +#define PWC_PDWKF0_VD1WKF_POS (4U) +#define PWC_PDWKF0_VD1WKF (0x10U) +#define PWC_PDWKF0_VD2WKF_POS (5U) +#define PWC_PDWKF0_VD2WKF (0x20U) +#define PWC_PDWKF0_NMIWKF_POS (6U) +#define PWC_PDWKF0_NMIWKF (0x40U) + +/* Bit definition for PWC_PDWKF1 register */ +#define PWC_PDWKF1_RTCPRDWKF_POS (4U) +#define PWC_PDWKF1_RTCPRDWKF (0x10U) +#define PWC_PDWKF1_RTCALMWKF_POS (5U) +#define PWC_PDWKF1_RTCALMWKF (0x20U) +#define PWC_PDWKF1_WKTMWKF_POS (7U) +#define PWC_PDWKF1_WKTMWKF (0x80U) + +/* Bit definition for PWC_PWCMR register */ +#define PWC_PWCMR_ADBUFE_POS (7U) +#define PWC_PWCMR_ADBUFE (0x80U) + +/* Bit definition for PWC_MDSWCR register */ +#define PWC_MDSWCR (0xFFU) + +/* Bit definition for PWC_PVDCR0 register */ +#define PWC_PVDCR0_EXVCCINEN_POS (0U) +#define PWC_PVDCR0_EXVCCINEN (0x01U) +#define PWC_PVDCR0_PVD1EN_POS (5U) +#define PWC_PVDCR0_PVD1EN (0x20U) +#define PWC_PVDCR0_PVD2EN_POS (6U) +#define PWC_PVDCR0_PVD2EN (0x40U) + +/* Bit definition for PWC_PVDCR1 register */ +#define PWC_PVDCR1_PVD1IRE_POS (0U) +#define PWC_PVDCR1_PVD1IRE (0x01U) +#define PWC_PVDCR1_PVD1IRS_POS (1U) +#define PWC_PVDCR1_PVD1IRS (0x02U) +#define PWC_PVDCR1_PVD1CMPOE_POS (2U) +#define PWC_PVDCR1_PVD1CMPOE (0x04U) +#define PWC_PVDCR1_PVD2IRE_POS (4U) +#define PWC_PVDCR1_PVD2IRE (0x10U) +#define PWC_PVDCR1_PVD2IRS_POS (5U) +#define PWC_PVDCR1_PVD2IRS (0x20U) +#define PWC_PVDCR1_PVD2CMPOE_POS (6U) +#define PWC_PVDCR1_PVD2CMPOE (0x40U) + +/* Bit definition for PWC_PVDFCR register */ +#define PWC_PVDFCR_PVD1NFDIS_POS (0U) +#define PWC_PVDFCR_PVD1NFDIS (0x01U) +#define PWC_PVDFCR_PVD1NFCKS_POS (1U) +#define PWC_PVDFCR_PVD1NFCKS (0x06U) +#define PWC_PVDFCR_PVD1NFCKS_0 (0x02U) +#define PWC_PVDFCR_PVD1NFCKS_1 (0x04U) +#define PWC_PVDFCR_PVD2NFDIS_POS (4U) +#define PWC_PVDFCR_PVD2NFDIS (0x10U) +#define PWC_PVDFCR_PVD2NFCKS_POS (5U) +#define PWC_PVDFCR_PVD2NFCKS (0x60U) +#define PWC_PVDFCR_PVD2NFCKS_0 (0x20U) +#define PWC_PVDFCR_PVD2NFCKS_1 (0x40U) + +/* Bit definition for PWC_PVDLCR register */ +#define PWC_PVDLCR_PVD1LVL_POS (0U) +#define PWC_PVDLCR_PVD1LVL (0x07U) +#define PWC_PVDLCR_PVD1LVL_0 (0x01U) +#define PWC_PVDLCR_PVD1LVL_1 (0x02U) +#define PWC_PVDLCR_PVD1LVL_2 (0x04U) +#define PWC_PVDLCR_PVD2LVL_POS (4U) +#define PWC_PVDLCR_PVD2LVL (0x70U) +#define PWC_PVDLCR_PVD2LVL_0 (0x10U) +#define PWC_PVDLCR_PVD2LVL_1 (0x20U) +#define PWC_PVDLCR_PVD2LVL_2 (0x40U) + +/* Bit definition for PWC_XTAL32CS register */ +#define PWC_XTAL32CS_CSDIS_POS (7U) +#define PWC_XTAL32CS_CSDIS (0x80U) + +/******************************************************************************* + Bit definition for Peripheral QSPI +*******************************************************************************/ +/* Bit definition for QSPI_CR register */ +#define QSPI_CR_MDSEL_POS (0U) +#define QSPI_CR_MDSEL (0x00000007UL) +#define QSPI_CR_PFE_POS (3U) +#define QSPI_CR_PFE (0x00000008UL) +#define QSPI_CR_PFSAE_POS (4U) +#define QSPI_CR_PFSAE (0x00000010UL) +#define QSPI_CR_DCOME_POS (5U) +#define QSPI_CR_DCOME (0x00000020UL) +#define QSPI_CR_XIPE_POS (6U) +#define QSPI_CR_XIPE (0x00000040UL) +#define QSPI_CR_SPIMD3_POS (7U) +#define QSPI_CR_SPIMD3 (0x00000080UL) +#define QSPI_CR_IPRSL_POS (8U) +#define QSPI_CR_IPRSL (0x00000300UL) +#define QSPI_CR_IPRSL_0 (0x00000100UL) +#define QSPI_CR_IPRSL_1 (0x00000200UL) +#define QSPI_CR_APRSL_POS (10U) +#define QSPI_CR_APRSL (0x00000C00UL) +#define QSPI_CR_APRSL_0 (0x00000400UL) +#define QSPI_CR_APRSL_1 (0x00000800UL) +#define QSPI_CR_DPRSL_POS (12U) +#define QSPI_CR_DPRSL (0x00003000UL) +#define QSPI_CR_DPRSL_0 (0x00001000UL) +#define QSPI_CR_DPRSL_1 (0x00002000UL) +#define QSPI_CR_DIV_POS (16U) +#define QSPI_CR_DIV (0x003F0000UL) + +/* Bit definition for QSPI_CSCR register */ +#define QSPI_CSCR_SSHW_POS (0U) +#define QSPI_CSCR_SSHW (0x0000000FUL) +#define QSPI_CSCR_SSNW_POS (4U) +#define QSPI_CSCR_SSNW (0x00000030UL) +#define QSPI_CSCR_SSNW_0 (0x00000010UL) +#define QSPI_CSCR_SSNW_1 (0x00000020UL) + +/* Bit definition for QSPI_FCR register */ +#define QSPI_FCR_AWSL_POS (0U) +#define QSPI_FCR_AWSL (0x00000003UL) +#define QSPI_FCR_AWSL_0 (0x00000001UL) +#define QSPI_FCR_AWSL_1 (0x00000002UL) +#define QSPI_FCR_FOUR_BIC_POS (2U) +#define QSPI_FCR_FOUR_BIC (0x00000004UL) +#define QSPI_FCR_SSNHD_POS (4U) +#define QSPI_FCR_SSNHD (0x00000010UL) +#define QSPI_FCR_SSNLD_POS (5U) +#define QSPI_FCR_SSNLD (0x00000020UL) +#define QSPI_FCR_WPOL_POS (6U) +#define QSPI_FCR_WPOL (0x00000040UL) +#define QSPI_FCR_DMCYCN_POS (8U) +#define QSPI_FCR_DMCYCN (0x00000F00UL) +#define QSPI_FCR_DUTY_POS (15U) +#define QSPI_FCR_DUTY (0x00008000UL) + +/* Bit definition for QSPI_SR register */ +#define QSPI_SR_BUSY_POS (0U) +#define QSPI_SR_BUSY (0x00000001UL) +#define QSPI_SR_XIPF_POS (6U) +#define QSPI_SR_XIPF (0x00000040UL) +#define QSPI_SR_RAER_POS (7U) +#define QSPI_SR_RAER (0x00000080UL) +#define QSPI_SR_PFNUM_POS (8U) +#define QSPI_SR_PFNUM (0x00001F00UL) +#define QSPI_SR_PFFUL_POS (14U) +#define QSPI_SR_PFFUL (0x00004000UL) +#define QSPI_SR_PFAN_POS (15U) +#define QSPI_SR_PFAN (0x00008000UL) + +/* Bit definition for QSPI_DCOM register */ +#define QSPI_DCOM_DCOM (0x000000FFUL) + +/* Bit definition for QSPI_CCMD register */ +#define QSPI_CCMD_RIC (0x000000FFUL) + +/* Bit definition for QSPI_XCMD register */ +#define QSPI_XCMD_XIPMC (0x000000FFUL) + +/* Bit definition for QSPI_SR2 register */ +#define QSPI_SR2_RAERCLR_POS (7U) +#define QSPI_SR2_RAERCLR (0x00000080UL) + +/* Bit definition for QSPI_EXAR register */ +#define QSPI_EXAR_EXADR_POS (26U) +#define QSPI_EXAR_EXADR (0xFC000000UL) + +/******************************************************************************* + Bit definition for Peripheral RMU +*******************************************************************************/ +/* Bit definition for RMU_RSTF0 register */ +#define RMU_RSTF0_PORF_POS (0U) +#define RMU_RSTF0_PORF (0x0001U) +#define RMU_RSTF0_PINRF_POS (1U) +#define RMU_RSTF0_PINRF (0x0002U) +#define RMU_RSTF0_BORF_POS (2U) +#define RMU_RSTF0_BORF (0x0004U) +#define RMU_RSTF0_PVD1RF_POS (3U) +#define RMU_RSTF0_PVD1RF (0x0008U) +#define RMU_RSTF0_PVD2RF_POS (4U) +#define RMU_RSTF0_PVD2RF (0x0010U) +#define RMU_RSTF0_WDRF_POS (5U) +#define RMU_RSTF0_WDRF (0x0020U) +#define RMU_RSTF0_SWDRF_POS (6U) +#define RMU_RSTF0_SWDRF (0x0040U) +#define RMU_RSTF0_PDRF_POS (7U) +#define RMU_RSTF0_PDRF (0x0080U) +#define RMU_RSTF0_SWRF_POS (8U) +#define RMU_RSTF0_SWRF (0x0100U) +#define RMU_RSTF0_MPUERF_POS (9U) +#define RMU_RSTF0_MPUERF (0x0200U) +#define RMU_RSTF0_RAPERF_POS (10U) +#define RMU_RSTF0_RAPERF (0x0400U) +#define RMU_RSTF0_RAECRF_POS (11U) +#define RMU_RSTF0_RAECRF (0x0800U) +#define RMU_RSTF0_CKFERF_POS (12U) +#define RMU_RSTF0_CKFERF (0x1000U) +#define RMU_RSTF0_XTALERF_POS (13U) +#define RMU_RSTF0_XTALERF (0x2000U) +#define RMU_RSTF0_MULTIRF_POS (14U) +#define RMU_RSTF0_MULTIRF (0x4000U) +#define RMU_RSTF0_CLRF_POS (15U) +#define RMU_RSTF0_CLRF (0x8000U) + +/******************************************************************************* + Bit definition for Peripheral RTC +*******************************************************************************/ +/* Bit definition for RTC_CR0 register */ +#define RTC_CR0_RESET (0x01U) + +/* Bit definition for RTC_CR1 register */ +#define RTC_CR1_PRDS_POS (0U) +#define RTC_CR1_PRDS (0x07U) +#define RTC_CR1_AMPM_POS (3U) +#define RTC_CR1_AMPM (0x08U) +#define RTC_CR1_ALMFCLR_POS (4U) +#define RTC_CR1_ALMFCLR (0x10U) +#define RTC_CR1_ONEHZOE_POS (5U) +#define RTC_CR1_ONEHZOE (0x20U) +#define RTC_CR1_ONEHZSEL_POS (6U) +#define RTC_CR1_ONEHZSEL (0x40U) +#define RTC_CR1_START_POS (7U) +#define RTC_CR1_START (0x80U) + +/* Bit definition for RTC_CR2 register */ +#define RTC_CR2_RWREQ_POS (0U) +#define RTC_CR2_RWREQ (0x01U) +#define RTC_CR2_RWEN_POS (1U) +#define RTC_CR2_RWEN (0x02U) +#define RTC_CR2_ALMF_POS (3U) +#define RTC_CR2_ALMF (0x08U) +#define RTC_CR2_PRDIE_POS (5U) +#define RTC_CR2_PRDIE (0x20U) +#define RTC_CR2_ALMIE_POS (6U) +#define RTC_CR2_ALMIE (0x40U) +#define RTC_CR2_ALME_POS (7U) +#define RTC_CR2_ALME (0x80U) + +/* Bit definition for RTC_CR3 register */ +#define RTC_CR3_LRCEN_POS (4U) +#define RTC_CR3_LRCEN (0x10U) +#define RTC_CR3_RCKSEL_POS (7U) +#define RTC_CR3_RCKSEL (0x80U) + +/* Bit definition for RTC_SEC register */ +#define RTC_SEC_SECU_POS (0U) +#define RTC_SEC_SECU (0x0FU) +#define RTC_SEC_SECD_POS (4U) +#define RTC_SEC_SECD (0x70U) + +/* Bit definition for RTC_MIN register */ +#define RTC_MIN_MINU_POS (0U) +#define RTC_MIN_MINU (0x0FU) +#define RTC_MIN_MIND_POS (4U) +#define RTC_MIN_MIND (0x70U) + +/* Bit definition for RTC_HOUR register */ +#define RTC_HOUR_HOURU_POS (0U) +#define RTC_HOUR_HOURU (0x0FU) +#define RTC_HOUR_HOURU_0 (0x01U) +#define RTC_HOUR_HOURU_1 (0x02U) +#define RTC_HOUR_HOURU_2 (0x04U) +#define RTC_HOUR_HOURU_3 (0x08U) +#define RTC_HOUR_HOURD_POS (4U) +#define RTC_HOUR_HOURD (0x30U) +#define RTC_HOUR_HOURD_0 (0x10U) +#define RTC_HOUR_HOURD_1 (0x20U) + +/* Bit definition for RTC_WEEK register */ +#define RTC_WEEK_WEEK (0x07U) + +/* Bit definition for RTC_DAY register */ +#define RTC_DAY_DAYU_POS (0U) +#define RTC_DAY_DAYU (0x0FU) +#define RTC_DAY_DAYD_POS (4U) +#define RTC_DAY_DAYD (0x30U) + +/* Bit definition for RTC_MON register */ +#define RTC_MON_MON (0x1FU) + +/* Bit definition for RTC_YEAR register */ +#define RTC_YEAR_YEARU_POS (0U) +#define RTC_YEAR_YEARU (0x0FU) +#define RTC_YEAR_YEARD_POS (4U) +#define RTC_YEAR_YEARD (0xF0U) + +/* Bit definition for RTC_ALMMIN register */ +#define RTC_ALMMIN_ALMMINU_POS (0U) +#define RTC_ALMMIN_ALMMINU (0x0FU) +#define RTC_ALMMIN_ALMMIND_POS (4U) +#define RTC_ALMMIN_ALMMIND (0x70U) + +/* Bit definition for RTC_ALMHOUR register */ +#define RTC_ALMHOUR_ALMHOURU_POS (0U) +#define RTC_ALMHOUR_ALMHOURU (0x0FU) +#define RTC_ALMHOUR_ALMHOURD_POS (4U) +#define RTC_ALMHOUR_ALMHOURD (0x30U) +#define RTC_ALMHOUR_ALMHOURD_0 (0x10U) +#define RTC_ALMHOUR_ALMHOURD_1 (0x20U) + +/* Bit definition for RTC_ALMWEEK register */ +#define RTC_ALMWEEK_ALMWEEK (0x7FU) +#define RTC_ALMWEEK_ALMWEEK_0 (0x01U) +#define RTC_ALMWEEK_ALMWEEK_1 (0x02U) +#define RTC_ALMWEEK_ALMWEEK_2 (0x04U) +#define RTC_ALMWEEK_ALMWEEK_3 (0x08U) +#define RTC_ALMWEEK_ALMWEEK_4 (0x10U) +#define RTC_ALMWEEK_ALMWEEK_5 (0x20U) +#define RTC_ALMWEEK_ALMWEEK_6 (0x40U) + +/* Bit definition for RTC_ERRCRH register */ +#define RTC_ERRCRH_COMP8_POS (0U) +#define RTC_ERRCRH_COMP8 (0x01U) +#define RTC_ERRCRH_COMPEN_POS (7U) +#define RTC_ERRCRH_COMPEN (0x80U) + +/* Bit definition for RTC_ERRCRL register */ +#define RTC_ERRCRL_COMP (0xFFU) + +/******************************************************************************* + Bit definition for Peripheral SDIOC +*******************************************************************************/ +/* Bit definition for SDIOC_BLKSIZE register */ +#define SDIOC_BLKSIZE_TBS (0x0FFFU) + +/* Bit definition for SDIOC_BLKCNT register */ +#define SDIOC_BLKCNT (0xFFFFU) + +/* Bit definition for SDIOC_ARG0 register */ +#define SDIOC_ARG0 (0xFFFFU) + +/* Bit definition for SDIOC_ARG1 register */ +#define SDIOC_ARG1 (0xFFFFU) + +/* Bit definition for SDIOC_TRANSMODE register */ +#define SDIOC_TRANSMODE_BCE_POS (1U) +#define SDIOC_TRANSMODE_BCE (0x0002U) +#define SDIOC_TRANSMODE_ATCEN_POS (2U) +#define SDIOC_TRANSMODE_ATCEN (0x000CU) +#define SDIOC_TRANSMODE_ATCEN_0 (0x0004U) +#define SDIOC_TRANSMODE_ATCEN_1 (0x0008U) +#define SDIOC_TRANSMODE_DDIR_POS (4U) +#define SDIOC_TRANSMODE_DDIR (0x0010U) +#define SDIOC_TRANSMODE_MULB_POS (5U) +#define SDIOC_TRANSMODE_MULB (0x0020U) + +/* Bit definition for SDIOC_CMD register */ +#define SDIOC_CMD_RESTYP_POS (0U) +#define SDIOC_CMD_RESTYP (0x0003U) +#define SDIOC_CMD_RESTYP_0 (0x0001U) +#define SDIOC_CMD_RESTYP_1 (0x0002U) +#define SDIOC_CMD_CCE_POS (3U) +#define SDIOC_CMD_CCE (0x0008U) +#define SDIOC_CMD_ICE_POS (4U) +#define SDIOC_CMD_ICE (0x0010U) +#define SDIOC_CMD_DAT_POS (5U) +#define SDIOC_CMD_DAT (0x0020U) +#define SDIOC_CMD_TYP_POS (6U) +#define SDIOC_CMD_TYP (0x00C0U) +#define SDIOC_CMD_TYP_0 (0x0040U) +#define SDIOC_CMD_TYP_1 (0x0080U) +#define SDIOC_CMD_IDX_POS (8U) +#define SDIOC_CMD_IDX (0x3F00U) + +/* Bit definition for SDIOC_RESP0 register */ +#define SDIOC_RESP0 (0xFFFFU) + +/* Bit definition for SDIOC_RESP1 register */ +#define SDIOC_RESP1 (0xFFFFU) + +/* Bit definition for SDIOC_RESP2 register */ +#define SDIOC_RESP2 (0xFFFFU) + +/* Bit definition for SDIOC_RESP3 register */ +#define SDIOC_RESP3 (0xFFFFU) + +/* Bit definition for SDIOC_RESP4 register */ +#define SDIOC_RESP4 (0xFFFFU) + +/* Bit definition for SDIOC_RESP5 register */ +#define SDIOC_RESP5 (0xFFFFU) + +/* Bit definition for SDIOC_RESP6 register */ +#define SDIOC_RESP6 (0xFFFFU) + +/* Bit definition for SDIOC_RESP7 register */ +#define SDIOC_RESP7 (0xFFFFU) + +/* Bit definition for SDIOC_BUF0 register */ +#define SDIOC_BUF0 (0xFFFFU) + +/* Bit definition for SDIOC_BUF1 register */ +#define SDIOC_BUF1 (0xFFFFU) + +/* Bit definition for SDIOC_PSTAT register */ +#define SDIOC_PSTAT_CIC_POS (0U) +#define SDIOC_PSTAT_CIC (0x00000001UL) +#define SDIOC_PSTAT_CID_POS (1U) +#define SDIOC_PSTAT_CID (0x00000002UL) +#define SDIOC_PSTAT_DA_POS (2U) +#define SDIOC_PSTAT_DA (0x00000004UL) +#define SDIOC_PSTAT_WTA_POS (8U) +#define SDIOC_PSTAT_WTA (0x00000100UL) +#define SDIOC_PSTAT_RTA_POS (9U) +#define SDIOC_PSTAT_RTA (0x00000200UL) +#define SDIOC_PSTAT_BWE_POS (10U) +#define SDIOC_PSTAT_BWE (0x00000400UL) +#define SDIOC_PSTAT_BRE_POS (11U) +#define SDIOC_PSTAT_BRE (0x00000800UL) +#define SDIOC_PSTAT_CIN_POS (16U) +#define SDIOC_PSTAT_CIN (0x00010000UL) +#define SDIOC_PSTAT_CSS_POS (17U) +#define SDIOC_PSTAT_CSS (0x00020000UL) +#define SDIOC_PSTAT_CDL_POS (18U) +#define SDIOC_PSTAT_CDL (0x00040000UL) +#define SDIOC_PSTAT_WPL_POS (19U) +#define SDIOC_PSTAT_WPL (0x00080000UL) +#define SDIOC_PSTAT_DATL_POS (20U) +#define SDIOC_PSTAT_DATL (0x00F00000UL) +#define SDIOC_PSTAT_DATL_0 (0x00100000UL) +#define SDIOC_PSTAT_DATL_1 (0x00200000UL) +#define SDIOC_PSTAT_DATL_2 (0x00400000UL) +#define SDIOC_PSTAT_DATL_3 (0x00800000UL) +#define SDIOC_PSTAT_CMDL_POS (24U) +#define SDIOC_PSTAT_CMDL (0x01000000UL) + +/* Bit definition for SDIOC_HOSTCON register */ +#define SDIOC_HOSTCON_DW_POS (1U) +#define SDIOC_HOSTCON_DW (0x02U) +#define SDIOC_HOSTCON_HSEN_POS (2U) +#define SDIOC_HOSTCON_HSEN (0x04U) +#define SDIOC_HOSTCON_EXDW_POS (5U) +#define SDIOC_HOSTCON_EXDW (0x20U) +#define SDIOC_HOSTCON_CDTL_POS (6U) +#define SDIOC_HOSTCON_CDTL (0x40U) +#define SDIOC_HOSTCON_CDSS_POS (7U) +#define SDIOC_HOSTCON_CDSS (0x80U) + +/* Bit definition for SDIOC_PWRCON register */ +#define SDIOC_PWRCON_PWON (0x01U) + +/* Bit definition for SDIOC_BLKGPCON register */ +#define SDIOC_BLKGPCON_SABGR_POS (0U) +#define SDIOC_BLKGPCON_SABGR (0x01U) +#define SDIOC_BLKGPCON_CR_POS (1U) +#define SDIOC_BLKGPCON_CR (0x02U) +#define SDIOC_BLKGPCON_RWC_POS (2U) +#define SDIOC_BLKGPCON_RWC (0x04U) +#define SDIOC_BLKGPCON_IABG_POS (3U) +#define SDIOC_BLKGPCON_IABG (0x08U) + +/* Bit definition for SDIOC_CLKCON register */ +#define SDIOC_CLKCON_ICE_POS (0U) +#define SDIOC_CLKCON_ICE (0x0001U) +#define SDIOC_CLKCON_CE_POS (2U) +#define SDIOC_CLKCON_CE (0x0004U) +#define SDIOC_CLKCON_FS_POS (8U) +#define SDIOC_CLKCON_FS (0xFF00U) +#define SDIOC_CLKCON_FS_0 (0x0100U) +#define SDIOC_CLKCON_FS_1 (0x0200U) +#define SDIOC_CLKCON_FS_2 (0x0400U) +#define SDIOC_CLKCON_FS_3 (0x0800U) +#define SDIOC_CLKCON_FS_4 (0x1000U) +#define SDIOC_CLKCON_FS_5 (0x2000U) +#define SDIOC_CLKCON_FS_6 (0x4000U) +#define SDIOC_CLKCON_FS_7 (0x8000U) + +/* Bit definition for SDIOC_TOUTCON register */ +#define SDIOC_TOUTCON_DTO (0x0FU) + +/* Bit definition for SDIOC_SFTRST register */ +#define SDIOC_SFTRST_RSTA_POS (0U) +#define SDIOC_SFTRST_RSTA (0x01U) +#define SDIOC_SFTRST_RSTC_POS (1U) +#define SDIOC_SFTRST_RSTC (0x02U) +#define SDIOC_SFTRST_RSTD_POS (2U) +#define SDIOC_SFTRST_RSTD (0x04U) + +/* Bit definition for SDIOC_NORINTST register */ +#define SDIOC_NORINTST_CC_POS (0U) +#define SDIOC_NORINTST_CC (0x0001U) +#define SDIOC_NORINTST_TC_POS (1U) +#define SDIOC_NORINTST_TC (0x0002U) +#define SDIOC_NORINTST_BGE_POS (2U) +#define SDIOC_NORINTST_BGE (0x0004U) +#define SDIOC_NORINTST_BWR_POS (4U) +#define SDIOC_NORINTST_BWR (0x0010U) +#define SDIOC_NORINTST_BRR_POS (5U) +#define SDIOC_NORINTST_BRR (0x0020U) +#define SDIOC_NORINTST_CIST_POS (6U) +#define SDIOC_NORINTST_CIST (0x0040U) +#define SDIOC_NORINTST_CRM_POS (7U) +#define SDIOC_NORINTST_CRM (0x0080U) +#define SDIOC_NORINTST_CINT_POS (8U) +#define SDIOC_NORINTST_CINT (0x0100U) +#define SDIOC_NORINTST_EI_POS (15U) +#define SDIOC_NORINTST_EI (0x8000U) + +/* Bit definition for SDIOC_ERRINTST register */ +#define SDIOC_ERRINTST_CTOE_POS (0U) +#define SDIOC_ERRINTST_CTOE (0x0001U) +#define SDIOC_ERRINTST_CCE_POS (1U) +#define SDIOC_ERRINTST_CCE (0x0002U) +#define SDIOC_ERRINTST_CEBE_POS (2U) +#define SDIOC_ERRINTST_CEBE (0x0004U) +#define SDIOC_ERRINTST_CIE_POS (3U) +#define SDIOC_ERRINTST_CIE (0x0008U) +#define SDIOC_ERRINTST_DTOE_POS (4U) +#define SDIOC_ERRINTST_DTOE (0x0010U) +#define SDIOC_ERRINTST_DCE_POS (5U) +#define SDIOC_ERRINTST_DCE (0x0020U) +#define SDIOC_ERRINTST_DEBE_POS (6U) +#define SDIOC_ERRINTST_DEBE (0x0040U) +#define SDIOC_ERRINTST_ACE_POS (8U) +#define SDIOC_ERRINTST_ACE (0x0100U) + +/* Bit definition for SDIOC_NORINTSTEN register */ +#define SDIOC_NORINTSTEN_CCEN_POS (0U) +#define SDIOC_NORINTSTEN_CCEN (0x0001U) +#define SDIOC_NORINTSTEN_TCEN_POS (1U) +#define SDIOC_NORINTSTEN_TCEN (0x0002U) +#define SDIOC_NORINTSTEN_BGEEN_POS (2U) +#define SDIOC_NORINTSTEN_BGEEN (0x0004U) +#define SDIOC_NORINTSTEN_BWREN_POS (4U) +#define SDIOC_NORINTSTEN_BWREN (0x0010U) +#define SDIOC_NORINTSTEN_BRREN_POS (5U) +#define SDIOC_NORINTSTEN_BRREN (0x0020U) +#define SDIOC_NORINTSTEN_CISTEN_POS (6U) +#define SDIOC_NORINTSTEN_CISTEN (0x0040U) +#define SDIOC_NORINTSTEN_CRMEN_POS (7U) +#define SDIOC_NORINTSTEN_CRMEN (0x0080U) +#define SDIOC_NORINTSTEN_CINTEN_POS (8U) +#define SDIOC_NORINTSTEN_CINTEN (0x0100U) + +/* Bit definition for SDIOC_ERRINTSTEN register */ +#define SDIOC_ERRINTSTEN_CTOEEN_POS (0U) +#define SDIOC_ERRINTSTEN_CTOEEN (0x0001U) +#define SDIOC_ERRINTSTEN_CCEEN_POS (1U) +#define SDIOC_ERRINTSTEN_CCEEN (0x0002U) +#define SDIOC_ERRINTSTEN_CEBEEN_POS (2U) +#define SDIOC_ERRINTSTEN_CEBEEN (0x0004U) +#define SDIOC_ERRINTSTEN_CIEEN_POS (3U) +#define SDIOC_ERRINTSTEN_CIEEN (0x0008U) +#define SDIOC_ERRINTSTEN_DTOEEN_POS (4U) +#define SDIOC_ERRINTSTEN_DTOEEN (0x0010U) +#define SDIOC_ERRINTSTEN_DCEEN_POS (5U) +#define SDIOC_ERRINTSTEN_DCEEN (0x0020U) +#define SDIOC_ERRINTSTEN_DEBEEN_POS (6U) +#define SDIOC_ERRINTSTEN_DEBEEN (0x0040U) +#define SDIOC_ERRINTSTEN_ACEEN_POS (8U) +#define SDIOC_ERRINTSTEN_ACEEN (0x0100U) + +/* Bit definition for SDIOC_NORINTSGEN register */ +#define SDIOC_NORINTSGEN_CCSEN_POS (0U) +#define SDIOC_NORINTSGEN_CCSEN (0x0001U) +#define SDIOC_NORINTSGEN_TCSEN_POS (1U) +#define SDIOC_NORINTSGEN_TCSEN (0x0002U) +#define SDIOC_NORINTSGEN_BGESEN_POS (2U) +#define SDIOC_NORINTSGEN_BGESEN (0x0004U) +#define SDIOC_NORINTSGEN_BWRSEN_POS (4U) +#define SDIOC_NORINTSGEN_BWRSEN (0x0010U) +#define SDIOC_NORINTSGEN_BRRSEN_POS (5U) +#define SDIOC_NORINTSGEN_BRRSEN (0x0020U) +#define SDIOC_NORINTSGEN_CISTSEN_POS (6U) +#define SDIOC_NORINTSGEN_CISTSEN (0x0040U) +#define SDIOC_NORINTSGEN_CRMSEN_POS (7U) +#define SDIOC_NORINTSGEN_CRMSEN (0x0080U) +#define SDIOC_NORINTSGEN_CINTSEN_POS (8U) +#define SDIOC_NORINTSGEN_CINTSEN (0x0100U) + +/* Bit definition for SDIOC_ERRINTSGEN register */ +#define SDIOC_ERRINTSGEN_CTOESEN_POS (0U) +#define SDIOC_ERRINTSGEN_CTOESEN (0x0001U) +#define SDIOC_ERRINTSGEN_CCESEN_POS (1U) +#define SDIOC_ERRINTSGEN_CCESEN (0x0002U) +#define SDIOC_ERRINTSGEN_CEBESEN_POS (2U) +#define SDIOC_ERRINTSGEN_CEBESEN (0x0004U) +#define SDIOC_ERRINTSGEN_CIESEN_POS (3U) +#define SDIOC_ERRINTSGEN_CIESEN (0x0008U) +#define SDIOC_ERRINTSGEN_DTOESEN_POS (4U) +#define SDIOC_ERRINTSGEN_DTOESEN (0x0010U) +#define SDIOC_ERRINTSGEN_DCESEN_POS (5U) +#define SDIOC_ERRINTSGEN_DCESEN (0x0020U) +#define SDIOC_ERRINTSGEN_DEBESEN_POS (6U) +#define SDIOC_ERRINTSGEN_DEBESEN (0x0040U) +#define SDIOC_ERRINTSGEN_ACESEN_POS (8U) +#define SDIOC_ERRINTSGEN_ACESEN (0x0100U) + +/* Bit definition for SDIOC_ATCERRST register */ +#define SDIOC_ATCERRST_NE_POS (0U) +#define SDIOC_ATCERRST_NE (0x0001U) +#define SDIOC_ATCERRST_TOE_POS (1U) +#define SDIOC_ATCERRST_TOE (0x0002U) +#define SDIOC_ATCERRST_CE_POS (2U) +#define SDIOC_ATCERRST_CE (0x0004U) +#define SDIOC_ATCERRST_EBE_POS (3U) +#define SDIOC_ATCERRST_EBE (0x0008U) +#define SDIOC_ATCERRST_IE_POS (4U) +#define SDIOC_ATCERRST_IE (0x0010U) +#define SDIOC_ATCERRST_CMDE_POS (7U) +#define SDIOC_ATCERRST_CMDE (0x0080U) + +/* Bit definition for SDIOC_FEA register */ +#define SDIOC_FEA_FNE_POS (0U) +#define SDIOC_FEA_FNE (0x0001U) +#define SDIOC_FEA_FTOE_POS (1U) +#define SDIOC_FEA_FTOE (0x0002U) +#define SDIOC_FEA_FCE_POS (2U) +#define SDIOC_FEA_FCE (0x0004U) +#define SDIOC_FEA_FEBE_POS (3U) +#define SDIOC_FEA_FEBE (0x0008U) +#define SDIOC_FEA_FIE_POS (4U) +#define SDIOC_FEA_FIE (0x0010U) +#define SDIOC_FEA_FCMDE_POS (7U) +#define SDIOC_FEA_FCMDE (0x0080U) + +/* Bit definition for SDIOC_FEE register */ +#define SDIOC_FEE_FCTOE_POS (0U) +#define SDIOC_FEE_FCTOE (0x0001U) +#define SDIOC_FEE_FCCE_POS (1U) +#define SDIOC_FEE_FCCE (0x0002U) +#define SDIOC_FEE_FCEBE_POS (2U) +#define SDIOC_FEE_FCEBE (0x0004U) +#define SDIOC_FEE_FCIE_POS (3U) +#define SDIOC_FEE_FCIE (0x0008U) +#define SDIOC_FEE_FDTOE_POS (4U) +#define SDIOC_FEE_FDTOE (0x0010U) +#define SDIOC_FEE_FDCE_POS (5U) +#define SDIOC_FEE_FDCE (0x0020U) +#define SDIOC_FEE_FDEBE_POS (6U) +#define SDIOC_FEE_FDEBE (0x0040U) +#define SDIOC_FEE_FACE_POS (8U) +#define SDIOC_FEE_FACE (0x0100U) + +/******************************************************************************* + Bit definition for Peripheral SPI +*******************************************************************************/ +/* Bit definition for SPI_DR register */ +#define SPI_DR (0xFFFFFFFFUL) + +/* Bit definition for SPI_CR1 register */ +#define SPI_CR1_SPIMDS_POS (0U) +#define SPI_CR1_SPIMDS (0x00000001UL) +#define SPI_CR1_TXMDS_POS (1U) +#define SPI_CR1_TXMDS (0x00000002UL) +#define SPI_CR1_MSTR_POS (3U) +#define SPI_CR1_MSTR (0x00000008UL) +#define SPI_CR1_SPLPBK_POS (4U) +#define SPI_CR1_SPLPBK (0x00000010UL) +#define SPI_CR1_SPLPBK2_POS (5U) +#define SPI_CR1_SPLPBK2 (0x00000020UL) +#define SPI_CR1_SPE_POS (6U) +#define SPI_CR1_SPE (0x00000040UL) +#define SPI_CR1_CSUSPE_POS (7U) +#define SPI_CR1_CSUSPE (0x00000080UL) +#define SPI_CR1_EIE_POS (8U) +#define SPI_CR1_EIE (0x00000100UL) +#define SPI_CR1_TXIE_POS (9U) +#define SPI_CR1_TXIE (0x00000200UL) +#define SPI_CR1_RXIE_POS (10U) +#define SPI_CR1_RXIE (0x00000400UL) +#define SPI_CR1_IDIE_POS (11U) +#define SPI_CR1_IDIE (0x00000800UL) +#define SPI_CR1_MODFE_POS (12U) +#define SPI_CR1_MODFE (0x00001000UL) +#define SPI_CR1_PATE_POS (13U) +#define SPI_CR1_PATE (0x00002000UL) +#define SPI_CR1_PAOE_POS (14U) +#define SPI_CR1_PAOE (0x00004000UL) +#define SPI_CR1_PAE_POS (15U) +#define SPI_CR1_PAE (0x00008000UL) + +/* Bit definition for SPI_CFG1 register */ +#define SPI_CFG1_FTHLV_POS (0U) +#define SPI_CFG1_FTHLV (0x00000003UL) +#define SPI_CFG1_FTHLV_0 (0x00000001UL) +#define SPI_CFG1_FTHLV_1 (0x00000002UL) +#define SPI_CFG1_SPRDTD_POS (6U) +#define SPI_CFG1_SPRDTD (0x00000040UL) +#define SPI_CFG1_SS0PV_POS (8U) +#define SPI_CFG1_SS0PV (0x00000100UL) +#define SPI_CFG1_SS1PV_POS (9U) +#define SPI_CFG1_SS1PV (0x00000200UL) +#define SPI_CFG1_SS2PV_POS (10U) +#define SPI_CFG1_SS2PV (0x00000400UL) +#define SPI_CFG1_SS3PV_POS (11U) +#define SPI_CFG1_SS3PV (0x00000800UL) +#define SPI_CFG1_MSSI_POS (20U) +#define SPI_CFG1_MSSI (0x00700000UL) +#define SPI_CFG1_MSSDL_POS (24U) +#define SPI_CFG1_MSSDL (0x07000000UL) +#define SPI_CFG1_MIDI_POS (28U) +#define SPI_CFG1_MIDI (0x70000000UL) + +/* Bit definition for SPI_SR register */ +#define SPI_SR_OVRERF_POS (0U) +#define SPI_SR_OVRERF (0x00000001UL) +#define SPI_SR_IDLNF_POS (1U) +#define SPI_SR_IDLNF (0x00000002UL) +#define SPI_SR_MODFERF_POS (2U) +#define SPI_SR_MODFERF (0x00000004UL) +#define SPI_SR_PERF_POS (3U) +#define SPI_SR_PERF (0x00000008UL) +#define SPI_SR_UDRERF_POS (4U) +#define SPI_SR_UDRERF (0x00000010UL) +#define SPI_SR_TDEF_POS (5U) +#define SPI_SR_TDEF (0x00000020UL) +#define SPI_SR_RDFF_POS (7U) +#define SPI_SR_RDFF (0x00000080UL) + +/* Bit definition for SPI_CFG2 register */ +#define SPI_CFG2_CPHA_POS (0U) +#define SPI_CFG2_CPHA (0x00000001UL) +#define SPI_CFG2_CPOL_POS (1U) +#define SPI_CFG2_CPOL (0x00000002UL) +#define SPI_CFG2_MBR_POS (2U) +#define SPI_CFG2_MBR (0x0000001CUL) +#define SPI_CFG2_SSA_POS (5U) +#define SPI_CFG2_SSA (0x000000E0UL) +#define SPI_CFG2_SSA_0 (0x00000020UL) +#define SPI_CFG2_SSA_1 (0x00000040UL) +#define SPI_CFG2_SSA_2 (0x00000080UL) +#define SPI_CFG2_DSIZE_POS (8U) +#define SPI_CFG2_DSIZE (0x00000F00UL) +#define SPI_CFG2_LSBF_POS (12U) +#define SPI_CFG2_LSBF (0x00001000UL) +#define SPI_CFG2_MIDIE_POS (13U) +#define SPI_CFG2_MIDIE (0x00002000UL) +#define SPI_CFG2_MSSDLE_POS (14U) +#define SPI_CFG2_MSSDLE (0x00004000UL) +#define SPI_CFG2_MSSIE_POS (15U) +#define SPI_CFG2_MSSIE (0x00008000UL) + +/******************************************************************************* + Bit definition for Peripheral SRAMC +*******************************************************************************/ +/* Bit definition for SRAMC_WTCR register */ +#define SRAMC_WTCR_SRAM12_RWT_POS (0U) +#define SRAMC_WTCR_SRAM12_RWT (0x00000007UL) +#define SRAMC_WTCR_SRAM12_WWT_POS (4U) +#define SRAMC_WTCR_SRAM12_WWT (0x00000070UL) +#define SRAMC_WTCR_SRAM3_RWT_POS (8U) +#define SRAMC_WTCR_SRAM3_RWT (0x00000700UL) +#define SRAMC_WTCR_SRAM3_WWT_POS (12U) +#define SRAMC_WTCR_SRAM3_WWT (0x00007000UL) +#define SRAMC_WTCR_SRAMH_RWT_POS (16U) +#define SRAMC_WTCR_SRAMH_RWT (0x00070000UL) +#define SRAMC_WTCR_SRAMH_WWT_POS (20U) +#define SRAMC_WTCR_SRAMH_WWT (0x00700000UL) +#define SRAMC_WTCR_SRAMR_RWT_POS (24U) +#define SRAMC_WTCR_SRAMR_RWT (0x07000000UL) +#define SRAMC_WTCR_SRAMR_WWT_POS (28U) +#define SRAMC_WTCR_SRAMR_WWT (0x70000000UL) + +/* Bit definition for SRAMC_WTPR register */ +#define SRAMC_WTPR_WTPRC_POS (0U) +#define SRAMC_WTPR_WTPRC (0x00000001UL) +#define SRAMC_WTPR_WTPRKW_POS (1U) +#define SRAMC_WTPR_WTPRKW (0x000000FEUL) + +/* Bit definition for SRAMC_CKCR register */ +#define SRAMC_CKCR_PYOAD_POS (0U) +#define SRAMC_CKCR_PYOAD (0x00000001UL) +#define SRAMC_CKCR_ECCOAD_POS (16U) +#define SRAMC_CKCR_ECCOAD (0x00010000UL) +#define SRAMC_CKCR_ECCMOD_POS (24U) +#define SRAMC_CKCR_ECCMOD (0x03000000UL) +#define SRAMC_CKCR_ECCMOD_0 (0x01000000UL) +#define SRAMC_CKCR_ECCMOD_1 (0x02000000UL) + +/* Bit definition for SRAMC_CKPR register */ +#define SRAMC_CKPR_CKPRC_POS (0U) +#define SRAMC_CKPR_CKPRC (0x00000001UL) +#define SRAMC_CKPR_CKPRKW_POS (1U) +#define SRAMC_CKPR_CKPRKW (0x000000FEUL) + +/* Bit definition for SRAMC_CKSR register */ +#define SRAMC_CKSR_SRAM3_1ERR_POS (0U) +#define SRAMC_CKSR_SRAM3_1ERR (0x00000001UL) +#define SRAMC_CKSR_SRAM3_2ERR_POS (1U) +#define SRAMC_CKSR_SRAM3_2ERR (0x00000002UL) +#define SRAMC_CKSR_SRAM12_PYERR_POS (2U) +#define SRAMC_CKSR_SRAM12_PYERR (0x00000004UL) +#define SRAMC_CKSR_SRAMH_PYERR_POS (3U) +#define SRAMC_CKSR_SRAMH_PYERR (0x00000008UL) +#define SRAMC_CKSR_SRAMR_PYERR_POS (4U) +#define SRAMC_CKSR_SRAMR_PYERR (0x00000010UL) + +/******************************************************************************* + Bit definition for Peripheral SWDT +*******************************************************************************/ +/* Bit definition for SWDT_SR register */ +#define SWDT_SR_CNT_POS (0U) +#define SWDT_SR_CNT (0x0000FFFFUL) +#define SWDT_SR_UDF_POS (16U) +#define SWDT_SR_UDF (0x00010000UL) +#define SWDT_SR_REF_POS (17U) +#define SWDT_SR_REF (0x00020000UL) + +/* Bit definition for SWDT_RR register */ +#define SWDT_RR_RF (0x0000FFFFUL) + +/******************************************************************************* + Bit definition for Peripheral TMR0 +*******************************************************************************/ +/* Bit definition for TMR0_CNTAR register */ +#define TMR0_CNTAR_CNTA (0x0000FFFFUL) + +/* Bit definition for TMR0_CNTBR register */ +#define TMR0_CNTBR_CNTB (0x0000FFFFUL) + +/* Bit definition for TMR0_CMPAR register */ +#define TMR0_CMPAR_CMPA (0x0000FFFFUL) + +/* Bit definition for TMR0_CMPBR register */ +#define TMR0_CMPBR_CMPB (0x0000FFFFUL) + +/* Bit definition for TMR0_BCONR register */ +#define TMR0_BCONR_CSTA_POS (0U) +#define TMR0_BCONR_CSTA (0x00000001UL) +#define TMR0_BCONR_CAPMDA_POS (1U) +#define TMR0_BCONR_CAPMDA (0x00000002UL) +#define TMR0_BCONR_INTENA_POS (2U) +#define TMR0_BCONR_INTENA (0x00000004UL) +#define TMR0_BCONR_CKDIVA_POS (4U) +#define TMR0_BCONR_CKDIVA (0x000000F0UL) +#define TMR0_BCONR_SYNSA_POS (8U) +#define TMR0_BCONR_SYNSA (0x00000100UL) +#define TMR0_BCONR_SYNCLKA_POS (9U) +#define TMR0_BCONR_SYNCLKA (0x00000200UL) +#define TMR0_BCONR_ASYNCLKA_POS (10U) +#define TMR0_BCONR_ASYNCLKA (0x00000400UL) +#define TMR0_BCONR_HSTAA_POS (12U) +#define TMR0_BCONR_HSTAA (0x00001000UL) +#define TMR0_BCONR_HSTPA_POS (13U) +#define TMR0_BCONR_HSTPA (0x00002000UL) +#define TMR0_BCONR_HCLEA_POS (14U) +#define TMR0_BCONR_HCLEA (0x00004000UL) +#define TMR0_BCONR_HICPA_POS (15U) +#define TMR0_BCONR_HICPA (0x00008000UL) +#define TMR0_BCONR_CSTB_POS (16U) +#define TMR0_BCONR_CSTB (0x00010000UL) +#define TMR0_BCONR_CAPMDB_POS (17U) +#define TMR0_BCONR_CAPMDB (0x00020000UL) +#define TMR0_BCONR_INTENB_POS (18U) +#define TMR0_BCONR_INTENB (0x00040000UL) +#define TMR0_BCONR_CKDIVB_POS (20U) +#define TMR0_BCONR_CKDIVB (0x00F00000UL) +#define TMR0_BCONR_SYNSB_POS (24U) +#define TMR0_BCONR_SYNSB (0x01000000UL) +#define TMR0_BCONR_SYNCLKB_POS (25U) +#define TMR0_BCONR_SYNCLKB (0x02000000UL) +#define TMR0_BCONR_ASYNCLKB_POS (26U) +#define TMR0_BCONR_ASYNCLKB (0x04000000UL) +#define TMR0_BCONR_HSTAB_POS (28U) +#define TMR0_BCONR_HSTAB (0x10000000UL) +#define TMR0_BCONR_HSTPB_POS (29U) +#define TMR0_BCONR_HSTPB (0x20000000UL) +#define TMR0_BCONR_HCLEB_POS (30U) +#define TMR0_BCONR_HCLEB (0x40000000UL) +#define TMR0_BCONR_HICPB_POS (31U) +#define TMR0_BCONR_HICPB (0x80000000UL) + +/* Bit definition for TMR0_STFLR register */ +#define TMR0_STFLR_CMFA_POS (0U) +#define TMR0_STFLR_CMFA (0x00000001UL) +#define TMR0_STFLR_CMFB_POS (16U) +#define TMR0_STFLR_CMFB (0x00010000UL) + +/******************************************************************************* + Bit definition for Peripheral TMR4 +*******************************************************************************/ +/* Bit definition for TMR4_OCCRUH register */ +#define TMR4_OCCRUH (0xFFFFU) + +/* Bit definition for TMR4_OCCRUL register */ +#define TMR4_OCCRUL (0xFFFFU) + +/* Bit definition for TMR4_OCCRVH register */ +#define TMR4_OCCRVH (0xFFFFU) + +/* Bit definition for TMR4_OCCRVL register */ +#define TMR4_OCCRVL (0xFFFFU) + +/* Bit definition for TMR4_OCCRWH register */ +#define TMR4_OCCRWH (0xFFFFU) + +/* Bit definition for TMR4_OCCRWL register */ +#define TMR4_OCCRWL (0xFFFFU) + +/* Bit definition for TMR4_OCSR register */ +#define TMR4_OCSR_OCEH_POS (0U) +#define TMR4_OCSR_OCEH (0x0001U) +#define TMR4_OCSR_OCEL_POS (1U) +#define TMR4_OCSR_OCEL (0x0002U) +#define TMR4_OCSR_OCPH_POS (2U) +#define TMR4_OCSR_OCPH (0x0004U) +#define TMR4_OCSR_OCPL_POS (3U) +#define TMR4_OCSR_OCPL (0x0008U) +#define TMR4_OCSR_OCIEH_POS (4U) +#define TMR4_OCSR_OCIEH (0x0010U) +#define TMR4_OCSR_OCIEL_POS (5U) +#define TMR4_OCSR_OCIEL (0x0020U) +#define TMR4_OCSR_OCFH_POS (6U) +#define TMR4_OCSR_OCFH (0x0040U) +#define TMR4_OCSR_OCFL_POS (7U) +#define TMR4_OCSR_OCFL (0x0080U) + +/* Bit definition for TMR4_OCER register */ +#define TMR4_OCER_CHBUFEN_POS (0U) +#define TMR4_OCER_CHBUFEN (0x0003U) +#define TMR4_OCER_CHBUFEN_0 (0x0001U) +#define TMR4_OCER_CHBUFEN_1 (0x0002U) +#define TMR4_OCER_CLBUFEN_POS (2U) +#define TMR4_OCER_CLBUFEN (0x000CU) +#define TMR4_OCER_CLBUFEN_0 (0x0004U) +#define TMR4_OCER_CLBUFEN_1 (0x0008U) +#define TMR4_OCER_MHBUFEN_POS (4U) +#define TMR4_OCER_MHBUFEN (0x0030U) +#define TMR4_OCER_MHBUFEN_0 (0x0010U) +#define TMR4_OCER_MHBUFEN_1 (0x0020U) +#define TMR4_OCER_MLBUFEN_POS (6U) +#define TMR4_OCER_MLBUFEN (0x00C0U) +#define TMR4_OCER_MLBUFEN_0 (0x0040U) +#define TMR4_OCER_MLBUFEN_1 (0x0080U) +#define TMR4_OCER_LMCH_POS (8U) +#define TMR4_OCER_LMCH (0x0100U) +#define TMR4_OCER_LMCL_POS (9U) +#define TMR4_OCER_LMCL (0x0200U) +#define TMR4_OCER_LMMH_POS (10U) +#define TMR4_OCER_LMMH (0x0400U) +#define TMR4_OCER_LMML_POS (11U) +#define TMR4_OCER_LMML (0x0800U) +#define TMR4_OCER_MCECH_POS (12U) +#define TMR4_OCER_MCECH (0x1000U) +#define TMR4_OCER_MCECL_POS (13U) +#define TMR4_OCER_MCECL (0x2000U) + +/* Bit definition for TMR4_OCMRH register */ +#define TMR4_OCMRH_OCFDCH_POS (0U) +#define TMR4_OCMRH_OCFDCH (0x0001U) +#define TMR4_OCMRH_OCFPKH_POS (1U) +#define TMR4_OCMRH_OCFPKH (0x0002U) +#define TMR4_OCMRH_OCFUCH_POS (2U) +#define TMR4_OCMRH_OCFUCH (0x0004U) +#define TMR4_OCMRH_OCFZRH_POS (3U) +#define TMR4_OCMRH_OCFZRH (0x0008U) +#define TMR4_OCMRH_OPDCH_POS (4U) +#define TMR4_OCMRH_OPDCH (0x0030U) +#define TMR4_OCMRH_OPDCH_0 (0x0010U) +#define TMR4_OCMRH_OPDCH_1 (0x0020U) +#define TMR4_OCMRH_OPPKH_POS (6U) +#define TMR4_OCMRH_OPPKH (0x00C0U) +#define TMR4_OCMRH_OPPKH_0 (0x0040U) +#define TMR4_OCMRH_OPPKH_1 (0x0080U) +#define TMR4_OCMRH_OPUCH_POS (8U) +#define TMR4_OCMRH_OPUCH (0x0300U) +#define TMR4_OCMRH_OPUCH_0 (0x0100U) +#define TMR4_OCMRH_OPUCH_1 (0x0200U) +#define TMR4_OCMRH_OPZRH_POS (10U) +#define TMR4_OCMRH_OPZRH (0x0C00U) +#define TMR4_OCMRH_OPZRH_0 (0x0400U) +#define TMR4_OCMRH_OPZRH_1 (0x0800U) +#define TMR4_OCMRH_OPNPKH_POS (12U) +#define TMR4_OCMRH_OPNPKH (0x3000U) +#define TMR4_OCMRH_OPNPKH_0 (0x1000U) +#define TMR4_OCMRH_OPNPKH_1 (0x2000U) +#define TMR4_OCMRH_OPNZRH_POS (14U) +#define TMR4_OCMRH_OPNZRH (0xC000U) +#define TMR4_OCMRH_OPNZRH_0 (0x4000U) +#define TMR4_OCMRH_OPNZRH_1 (0x8000U) + +/* Bit definition for TMR4_OCMRL register */ +#define TMR4_OCMRL_OCFDCL_POS (0U) +#define TMR4_OCMRL_OCFDCL (0x00000001UL) +#define TMR4_OCMRL_OCFPKL_POS (1U) +#define TMR4_OCMRL_OCFPKL (0x00000002UL) +#define TMR4_OCMRL_OCFUCL_POS (2U) +#define TMR4_OCMRL_OCFUCL (0x00000004UL) +#define TMR4_OCMRL_OCFZRL_POS (3U) +#define TMR4_OCMRL_OCFZRL (0x00000008UL) +#define TMR4_OCMRL_OPDCL_POS (4U) +#define TMR4_OCMRL_OPDCL (0x00000030UL) +#define TMR4_OCMRL_OPDCL_0 (0x00000010UL) +#define TMR4_OCMRL_OPDCL_1 (0x00000020UL) +#define TMR4_OCMRL_OPPKL_POS (6U) +#define TMR4_OCMRL_OPPKL (0x000000C0UL) +#define TMR4_OCMRL_OPPKL_0 (0x00000040UL) +#define TMR4_OCMRL_OPPKL_1 (0x00000080UL) +#define TMR4_OCMRL_OPUCL_POS (8U) +#define TMR4_OCMRL_OPUCL (0x00000300UL) +#define TMR4_OCMRL_OPUCL_0 (0x00000100UL) +#define TMR4_OCMRL_OPUCL_1 (0x00000200UL) +#define TMR4_OCMRL_OPZRL_POS (10U) +#define TMR4_OCMRL_OPZRL (0x00000C00UL) +#define TMR4_OCMRL_OPZRL_0 (0x00000400UL) +#define TMR4_OCMRL_OPZRL_1 (0x00000800UL) +#define TMR4_OCMRL_OPNPKL_POS (12U) +#define TMR4_OCMRL_OPNPKL (0x00003000UL) +#define TMR4_OCMRL_OPNPKL_0 (0x00001000UL) +#define TMR4_OCMRL_OPNPKL_1 (0x00002000UL) +#define TMR4_OCMRL_OPNZRL_POS (14U) +#define TMR4_OCMRL_OPNZRL (0x0000C000UL) +#define TMR4_OCMRL_OPNZRL_0 (0x00004000UL) +#define TMR4_OCMRL_OPNZRL_1 (0x00008000UL) +#define TMR4_OCMRL_EOPNDCL_POS (16U) +#define TMR4_OCMRL_EOPNDCL (0x00030000UL) +#define TMR4_OCMRL_EOPNDCL_0 (0x00010000UL) +#define TMR4_OCMRL_EOPNDCL_1 (0x00020000UL) +#define TMR4_OCMRL_EOPNUCL_POS (18U) +#define TMR4_OCMRL_EOPNUCL (0x000C0000UL) +#define TMR4_OCMRL_EOPNUCL_0 (0x00040000UL) +#define TMR4_OCMRL_EOPNUCL_1 (0x00080000UL) +#define TMR4_OCMRL_EOPDCL_POS (20U) +#define TMR4_OCMRL_EOPDCL (0x00300000UL) +#define TMR4_OCMRL_EOPDCL_0 (0x00100000UL) +#define TMR4_OCMRL_EOPDCL_1 (0x00200000UL) +#define TMR4_OCMRL_EOPPKL_POS (22U) +#define TMR4_OCMRL_EOPPKL (0x00C00000UL) +#define TMR4_OCMRL_EOPPKL_0 (0x00400000UL) +#define TMR4_OCMRL_EOPPKL_1 (0x00800000UL) +#define TMR4_OCMRL_EOPUCL_POS (24U) +#define TMR4_OCMRL_EOPUCL (0x03000000UL) +#define TMR4_OCMRL_EOPUCL_0 (0x01000000UL) +#define TMR4_OCMRL_EOPUCL_1 (0x02000000UL) +#define TMR4_OCMRL_EOPZRL_POS (26U) +#define TMR4_OCMRL_EOPZRL (0x0C000000UL) +#define TMR4_OCMRL_EOPZRL_0 (0x04000000UL) +#define TMR4_OCMRL_EOPZRL_1 (0x08000000UL) +#define TMR4_OCMRL_EOPNPKL_POS (28U) +#define TMR4_OCMRL_EOPNPKL (0x30000000UL) +#define TMR4_OCMRL_EOPNPKL_0 (0x10000000UL) +#define TMR4_OCMRL_EOPNPKL_1 (0x20000000UL) +#define TMR4_OCMRL_EOPNZRL_POS (30U) +#define TMR4_OCMRL_EOPNZRL (0xC0000000UL) +#define TMR4_OCMRL_EOPNZRL_0 (0x40000000UL) +#define TMR4_OCMRL_EOPNZRL_1 (0x80000000UL) + +/* Bit definition for TMR4_CPSR register */ +#define TMR4_CPSR (0xFFFFU) + +/* Bit definition for TMR4_CNTR register */ +#define TMR4_CNTR (0xFFFFU) + +/* Bit definition for TMR4_CCSR register */ +#define TMR4_CCSR_CKDIV_POS (0U) +#define TMR4_CCSR_CKDIV (0x000FU) +#define TMR4_CCSR_CLEAR_POS (4U) +#define TMR4_CCSR_CLEAR (0x0010U) +#define TMR4_CCSR_MODE_POS (5U) +#define TMR4_CCSR_MODE (0x0020U) +#define TMR4_CCSR_STOP_POS (6U) +#define TMR4_CCSR_STOP (0x0040U) +#define TMR4_CCSR_BUFEN_POS (7U) +#define TMR4_CCSR_BUFEN (0x0080U) +#define TMR4_CCSR_IRQPEN_POS (8U) +#define TMR4_CCSR_IRQPEN (0x0100U) +#define TMR4_CCSR_IRQPF_POS (9U) +#define TMR4_CCSR_IRQPF (0x0200U) +#define TMR4_CCSR_IRQZEN_POS (13U) +#define TMR4_CCSR_IRQZEN (0x2000U) +#define TMR4_CCSR_IRQZF_POS (14U) +#define TMR4_CCSR_IRQZF (0x4000U) +#define TMR4_CCSR_ECKEN_POS (15U) +#define TMR4_CCSR_ECKEN (0x8000U) + +/* Bit definition for TMR4_CVPR register */ +#define TMR4_CVPR_ZIM_POS (0U) +#define TMR4_CVPR_ZIM (0x000FU) +#define TMR4_CVPR_PIM_POS (4U) +#define TMR4_CVPR_PIM (0x00F0U) +#define TMR4_CVPR_ZIC_POS (8U) +#define TMR4_CVPR_ZIC (0x0F00U) +#define TMR4_CVPR_PIC_POS (12U) +#define TMR4_CVPR_PIC (0xF000U) + +/* Bit definition for TMR4_PFSRU register */ +#define TMR4_PFSRU (0xFFFFU) + +/* Bit definition for TMR4_PDARU register */ +#define TMR4_PDARU (0xFFFFU) + +/* Bit definition for TMR4_PDBRU register */ +#define TMR4_PDBRU (0xFFFFU) + +/* Bit definition for TMR4_PFSRV register */ +#define TMR4_PFSRV (0xFFFFU) + +/* Bit definition for TMR4_PDARV register */ +#define TMR4_PDARV (0xFFFFU) + +/* Bit definition for TMR4_PDBRV register */ +#define TMR4_PDBRV (0xFFFFU) + +/* Bit definition for TMR4_PFSRW register */ +#define TMR4_PFSRW (0xFFFFU) + +/* Bit definition for TMR4_PDARW register */ +#define TMR4_PDARW (0xFFFFU) + +/* Bit definition for TMR4_PDBRW register */ +#define TMR4_PDBRW (0xFFFFU) + +/* Bit definition for TMR4_POCR register */ +#define TMR4_POCR_DIVCK_POS (0U) +#define TMR4_POCR_DIVCK (0x0007U) +#define TMR4_POCR_PWMMD_POS (4U) +#define TMR4_POCR_PWMMD (0x0030U) +#define TMR4_POCR_PWMMD_0 (0x0010U) +#define TMR4_POCR_PWMMD_1 (0x0020U) +#define TMR4_POCR_LVLS_POS (6U) +#define TMR4_POCR_LVLS (0x00C0U) +#define TMR4_POCR_LVLS_0 (0x0040U) +#define TMR4_POCR_LVLS_1 (0x0080U) + +/* Bit definition for TMR4_RCSR register */ +#define TMR4_RCSR_RTIDU_POS (0U) +#define TMR4_RCSR_RTIDU (0x0001U) +#define TMR4_RCSR_RTIDV_POS (1U) +#define TMR4_RCSR_RTIDV (0x0002U) +#define TMR4_RCSR_RTIDW_POS (2U) +#define TMR4_RCSR_RTIDW (0x0004U) +#define TMR4_RCSR_RTIFU_POS (4U) +#define TMR4_RCSR_RTIFU (0x0010U) +#define TMR4_RCSR_RTICU_POS (5U) +#define TMR4_RCSR_RTICU (0x0020U) +#define TMR4_RCSR_RTEU_POS (6U) +#define TMR4_RCSR_RTEU (0x0040U) +#define TMR4_RCSR_RTSU_POS (7U) +#define TMR4_RCSR_RTSU (0x0080U) +#define TMR4_RCSR_RTIFV_POS (8U) +#define TMR4_RCSR_RTIFV (0x0100U) +#define TMR4_RCSR_RTICV_POS (9U) +#define TMR4_RCSR_RTICV (0x0200U) +#define TMR4_RCSR_RTEV_POS (10U) +#define TMR4_RCSR_RTEV (0x0400U) +#define TMR4_RCSR_RTSV_POS (11U) +#define TMR4_RCSR_RTSV (0x0800U) +#define TMR4_RCSR_RTIFW_POS (12U) +#define TMR4_RCSR_RTIFW (0x1000U) +#define TMR4_RCSR_RTICW_POS (13U) +#define TMR4_RCSR_RTICW (0x2000U) +#define TMR4_RCSR_RTEW_POS (14U) +#define TMR4_RCSR_RTEW (0x4000U) +#define TMR4_RCSR_RTSW_POS (15U) +#define TMR4_RCSR_RTSW (0x8000U) + +/* Bit definition for TMR4_SCCRUH register */ +#define TMR4_SCCRUH (0xFFFFU) + +/* Bit definition for TMR4_SCCRUL register */ +#define TMR4_SCCRUL (0xFFFFU) + +/* Bit definition for TMR4_SCCRVH register */ +#define TMR4_SCCRVH (0xFFFFU) + +/* Bit definition for TMR4_SCCRVL register */ +#define TMR4_SCCRVL (0xFFFFU) + +/* Bit definition for TMR4_SCCRWH register */ +#define TMR4_SCCRWH (0xFFFFU) + +/* Bit definition for TMR4_SCCRWL register */ +#define TMR4_SCCRWL (0xFFFFU) + +/* Bit definition for TMR4_SCSR register */ +#define TMR4_SCSR_BUFEN_POS (0U) +#define TMR4_SCSR_BUFEN (0x0003U) +#define TMR4_SCSR_BUFEN_0 (0x0001U) +#define TMR4_SCSR_BUFEN_1 (0x0002U) +#define TMR4_SCSR_EVTOS_POS (2U) +#define TMR4_SCSR_EVTOS (0x001CU) +#define TMR4_SCSR_LMC_POS (5U) +#define TMR4_SCSR_LMC (0x0020U) +#define TMR4_SCSR_EVTMS_POS (8U) +#define TMR4_SCSR_EVTMS (0x0100U) +#define TMR4_SCSR_EVTDS_POS (9U) +#define TMR4_SCSR_EVTDS (0x0200U) +#define TMR4_SCSR_DEN_POS (12U) +#define TMR4_SCSR_DEN (0x1000U) +#define TMR4_SCSR_PEN_POS (13U) +#define TMR4_SCSR_PEN (0x2000U) +#define TMR4_SCSR_UEN_POS (14U) +#define TMR4_SCSR_UEN (0x4000U) +#define TMR4_SCSR_ZEN_POS (15U) +#define TMR4_SCSR_ZEN (0x8000U) + +/* Bit definition for TMR4_SCMR register */ +#define TMR4_SCMR_AMC_POS (0U) +#define TMR4_SCMR_AMC (0x000FU) +#define TMR4_SCMR_MZCE_POS (6U) +#define TMR4_SCMR_MZCE (0x0040U) +#define TMR4_SCMR_MPCE_POS (7U) +#define TMR4_SCMR_MPCE (0x0080U) + +/* Bit definition for TMR4_ECSR register */ +#define TMR4_ECSR_HOLD_POS (7U) +#define TMR4_ECSR_HOLD (0x0080U) + +/******************************************************************************* + Bit definition for Peripheral TMR4CR +*******************************************************************************/ +/* Bit definition for TMR4CR_ECER1 register */ +#define TMR4CR_ECER1_EMBVAL (0x00000003UL) +#define TMR4CR_ECER1_EMBVAL_0 (0x00000001UL) +#define TMR4CR_ECER1_EMBVAL_1 (0x00000002UL) + +/* Bit definition for TMR4CR_ECER2 register */ +#define TMR4CR_ECER2_EMBVAL (0x00000003UL) +#define TMR4CR_ECER2_EMBVAL_0 (0x00000001UL) +#define TMR4CR_ECER2_EMBVAL_1 (0x00000002UL) + +/* Bit definition for TMR4CR_ECER3 register */ +#define TMR4CR_ECER3_EMBVAL (0x00000003UL) +#define TMR4CR_ECER3_EMBVAL_0 (0x00000001UL) +#define TMR4CR_ECER3_EMBVAL_1 (0x00000002UL) + +/******************************************************************************* + Bit definition for Peripheral TMR6 +*******************************************************************************/ +/* Bit definition for TMR6_CNTER register */ +#define TMR6_CNTER_CNT (0x0000FFFFUL) + +/* Bit definition for TMR6_PERAR register */ +#define TMR6_PERAR_PERA (0x0000FFFFUL) + +/* Bit definition for TMR6_PERBR register */ +#define TMR6_PERBR_PERB (0x0000FFFFUL) + +/* Bit definition for TMR6_PERCR register */ +#define TMR6_PERCR_PERC (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMAR register */ +#define TMR6_GCMAR_GCMA (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMBR register */ +#define TMR6_GCMBR_GCMB (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMCR register */ +#define TMR6_GCMCR_GCMC (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMDR register */ +#define TMR6_GCMDR_GCMD (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMER register */ +#define TMR6_GCMER_GCME (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMFR register */ +#define TMR6_GCMFR_GCMF (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMAR register */ +#define TMR6_SCMAR_SCMA (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMBR register */ +#define TMR6_SCMBR_SCMB (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMCR register */ +#define TMR6_SCMCR_SCMC (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMDR register */ +#define TMR6_SCMDR_SCMD (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMER register */ +#define TMR6_SCMER_SCME (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMFR register */ +#define TMR6_SCMFR_SCMF (0x0000FFFFUL) + +/* Bit definition for TMR6_DTUAR register */ +#define TMR6_DTUAR_DTUA (0x0000FFFFUL) + +/* Bit definition for TMR6_DTDAR register */ +#define TMR6_DTDAR_DTDA (0x0000FFFFUL) + +/* Bit definition for TMR6_DTUBR register */ +#define TMR6_DTUBR_DTUB (0x0000FFFFUL) + +/* Bit definition for TMR6_DTDBR register */ +#define TMR6_DTDBR_DTDB (0x0000FFFFUL) + +/* Bit definition for TMR6_GCONR register */ +#define TMR6_GCONR_START_POS (0U) +#define TMR6_GCONR_START (0x00000001UL) +#define TMR6_GCONR_MODE_POS (1U) +#define TMR6_GCONR_MODE (0x0000000EUL) +#define TMR6_GCONR_CKDIV_POS (4U) +#define TMR6_GCONR_CKDIV (0x00000070UL) +#define TMR6_GCONR_DIR_POS (8U) +#define TMR6_GCONR_DIR (0x00000100UL) +#define TMR6_GCONR_ZMSKREV_POS (16U) +#define TMR6_GCONR_ZMSKREV (0x00010000UL) +#define TMR6_GCONR_ZMSKPOS_POS (17U) +#define TMR6_GCONR_ZMSKPOS (0x00020000UL) +#define TMR6_GCONR_ZMSKVAL_POS (18U) +#define TMR6_GCONR_ZMSKVAL (0x000C0000UL) +#define TMR6_GCONR_ZMSKVAL_0 (0x00040000UL) +#define TMR6_GCONR_ZMSKVAL_1 (0x00080000UL) + +/* Bit definition for TMR6_ICONR register */ +#define TMR6_ICONR_INTENA_POS (0U) +#define TMR6_ICONR_INTENA (0x00000001UL) +#define TMR6_ICONR_INTENB_POS (1U) +#define TMR6_ICONR_INTENB (0x00000002UL) +#define TMR6_ICONR_INTENC_POS (2U) +#define TMR6_ICONR_INTENC (0x00000004UL) +#define TMR6_ICONR_INTEND_POS (3U) +#define TMR6_ICONR_INTEND (0x00000008UL) +#define TMR6_ICONR_INTENE_POS (4U) +#define TMR6_ICONR_INTENE (0x00000010UL) +#define TMR6_ICONR_INTENF_POS (5U) +#define TMR6_ICONR_INTENF (0x00000020UL) +#define TMR6_ICONR_INTENOVF_POS (6U) +#define TMR6_ICONR_INTENOVF (0x00000040UL) +#define TMR6_ICONR_INTENUDF_POS (7U) +#define TMR6_ICONR_INTENUDF (0x00000080UL) +#define TMR6_ICONR_INTENDTE_POS (8U) +#define TMR6_ICONR_INTENDTE (0x00000100UL) +#define TMR6_ICONR_INTENSAU_POS (16U) +#define TMR6_ICONR_INTENSAU (0x00010000UL) +#define TMR6_ICONR_INTENSAD_POS (17U) +#define TMR6_ICONR_INTENSAD (0x00020000UL) +#define TMR6_ICONR_INTENSBU_POS (18U) +#define TMR6_ICONR_INTENSBU (0x00040000UL) +#define TMR6_ICONR_INTENSBD_POS (19U) +#define TMR6_ICONR_INTENSBD (0x00080000UL) + +/* Bit definition for TMR6_PCONR register */ +#define TMR6_PCONR_CAPMDA_POS (0U) +#define TMR6_PCONR_CAPMDA (0x00000001UL) +#define TMR6_PCONR_STACA_POS (1U) +#define TMR6_PCONR_STACA (0x00000002UL) +#define TMR6_PCONR_STPCA_POS (2U) +#define TMR6_PCONR_STPCA (0x00000004UL) +#define TMR6_PCONR_STASTPSA_POS (3U) +#define TMR6_PCONR_STASTPSA (0x00000008UL) +#define TMR6_PCONR_CMPCA_POS (4U) +#define TMR6_PCONR_CMPCA (0x00000030UL) +#define TMR6_PCONR_CMPCA_0 (0x00000010UL) +#define TMR6_PCONR_CMPCA_1 (0x00000020UL) +#define TMR6_PCONR_PERCA_POS (6U) +#define TMR6_PCONR_PERCA (0x000000C0UL) +#define TMR6_PCONR_PERCA_0 (0x00000040UL) +#define TMR6_PCONR_PERCA_1 (0x00000080UL) +#define TMR6_PCONR_OUTENA_POS (8U) +#define TMR6_PCONR_OUTENA (0x00000100UL) +#define TMR6_PCONR_EMBVALA_POS (11U) +#define TMR6_PCONR_EMBVALA (0x00001800UL) +#define TMR6_PCONR_EMBVALA_0 (0x00000800UL) +#define TMR6_PCONR_EMBVALA_1 (0x00001000UL) +#define TMR6_PCONR_CAPMDB_POS (16U) +#define TMR6_PCONR_CAPMDB (0x00010000UL) +#define TMR6_PCONR_STACB_POS (17U) +#define TMR6_PCONR_STACB (0x00020000UL) +#define TMR6_PCONR_STPCB_POS (18U) +#define TMR6_PCONR_STPCB (0x00040000UL) +#define TMR6_PCONR_STASTPSB_POS (19U) +#define TMR6_PCONR_STASTPSB (0x00080000UL) +#define TMR6_PCONR_CMPCB_POS (20U) +#define TMR6_PCONR_CMPCB (0x00300000UL) +#define TMR6_PCONR_CMPCB_0 (0x00100000UL) +#define TMR6_PCONR_CMPCB_1 (0x00200000UL) +#define TMR6_PCONR_PERCB_POS (22U) +#define TMR6_PCONR_PERCB (0x00C00000UL) +#define TMR6_PCONR_PERCB_0 (0x00400000UL) +#define TMR6_PCONR_PERCB_1 (0x00800000UL) +#define TMR6_PCONR_OUTENB_POS (24U) +#define TMR6_PCONR_OUTENB (0x01000000UL) +#define TMR6_PCONR_EMBVALB_POS (27U) +#define TMR6_PCONR_EMBVALB (0x18000000UL) +#define TMR6_PCONR_EMBVALB_0 (0x08000000UL) +#define TMR6_PCONR_EMBVALB_1 (0x10000000UL) + +/* Bit definition for TMR6_BCONR register */ +#define TMR6_BCONR_BENA_POS (0U) +#define TMR6_BCONR_BENA (0x00000001UL) +#define TMR6_BCONR_BSEA_POS (1U) +#define TMR6_BCONR_BSEA (0x00000002UL) +#define TMR6_BCONR_BENB_POS (2U) +#define TMR6_BCONR_BENB (0x00000004UL) +#define TMR6_BCONR_BSEB_POS (3U) +#define TMR6_BCONR_BSEB (0x00000008UL) +#define TMR6_BCONR_BENP_POS (8U) +#define TMR6_BCONR_BENP (0x00000100UL) +#define TMR6_BCONR_BSEP_POS (9U) +#define TMR6_BCONR_BSEP (0x00000200UL) +#define TMR6_BCONR_BENSPA_POS (16U) +#define TMR6_BCONR_BENSPA (0x00010000UL) +#define TMR6_BCONR_BSESPA_POS (17U) +#define TMR6_BCONR_BSESPA (0x00020000UL) +#define TMR6_BCONR_BTRUSPA_POS (20U) +#define TMR6_BCONR_BTRUSPA (0x00100000UL) +#define TMR6_BCONR_BTRDSPA_POS (21U) +#define TMR6_BCONR_BTRDSPA (0x00200000UL) +#define TMR6_BCONR_BENSPB_POS (24U) +#define TMR6_BCONR_BENSPB (0x01000000UL) +#define TMR6_BCONR_BSESPB_POS (25U) +#define TMR6_BCONR_BSESPB (0x02000000UL) +#define TMR6_BCONR_BTRUSPB_POS (28U) +#define TMR6_BCONR_BTRUSPB (0x10000000UL) +#define TMR6_BCONR_BTRDSPB_POS (29U) +#define TMR6_BCONR_BTRDSPB (0x20000000UL) + +/* Bit definition for TMR6_DCONR register */ +#define TMR6_DCONR_DTCEN_POS (0U) +#define TMR6_DCONR_DTCEN (0x00000001UL) +#define TMR6_DCONR_DTBENU_POS (4U) +#define TMR6_DCONR_DTBENU (0x00000010UL) +#define TMR6_DCONR_DTBEND_POS (5U) +#define TMR6_DCONR_DTBEND (0x00000020UL) +#define TMR6_DCONR_SEPA_POS (8U) +#define TMR6_DCONR_SEPA (0x00000100UL) + +/* Bit definition for TMR6_FCONR register */ +#define TMR6_FCONR_NOFIENGA_POS (0U) +#define TMR6_FCONR_NOFIENGA (0x00000001UL) +#define TMR6_FCONR_NOFICKGA_POS (1U) +#define TMR6_FCONR_NOFICKGA (0x00000006UL) +#define TMR6_FCONR_NOFICKGA_0 (0x00000002UL) +#define TMR6_FCONR_NOFICKGA_1 (0x00000004UL) +#define TMR6_FCONR_NOFIENGB_POS (4U) +#define TMR6_FCONR_NOFIENGB (0x00000010UL) +#define TMR6_FCONR_NOFICKGB_POS (5U) +#define TMR6_FCONR_NOFICKGB (0x00000060UL) +#define TMR6_FCONR_NOFICKGB_0 (0x00000020UL) +#define TMR6_FCONR_NOFICKGB_1 (0x00000040UL) +#define TMR6_FCONR_NOFIENTA_POS (16U) +#define TMR6_FCONR_NOFIENTA (0x00010000UL) +#define TMR6_FCONR_NOFICKTA_POS (17U) +#define TMR6_FCONR_NOFICKTA (0x00060000UL) +#define TMR6_FCONR_NOFICKTA_0 (0x00020000UL) +#define TMR6_FCONR_NOFICKTA_1 (0x00040000UL) +#define TMR6_FCONR_NOFIENTB_POS (20U) +#define TMR6_FCONR_NOFIENTB (0x00100000UL) +#define TMR6_FCONR_NOFICKTB_POS (21U) +#define TMR6_FCONR_NOFICKTB (0x00600000UL) +#define TMR6_FCONR_NOFICKTB_0 (0x00200000UL) +#define TMR6_FCONR_NOFICKTB_1 (0x00400000UL) + +/* Bit definition for TMR6_VPERR register */ +#define TMR6_VPERR_SPPERIA_POS (8U) +#define TMR6_VPERR_SPPERIA (0x00000100UL) +#define TMR6_VPERR_SPPERIB_POS (9U) +#define TMR6_VPERR_SPPERIB (0x00000200UL) +#define TMR6_VPERR_PCNTE_POS (16U) +#define TMR6_VPERR_PCNTE (0x00030000UL) +#define TMR6_VPERR_PCNTE_0 (0x00010000UL) +#define TMR6_VPERR_PCNTE_1 (0x00020000UL) +#define TMR6_VPERR_PCNTS_POS (18U) +#define TMR6_VPERR_PCNTS (0x001C0000UL) + +/* Bit definition for TMR6_STFLR register */ +#define TMR6_STFLR_CMAF_POS (0U) +#define TMR6_STFLR_CMAF (0x00000001UL) +#define TMR6_STFLR_CMBF_POS (1U) +#define TMR6_STFLR_CMBF (0x00000002UL) +#define TMR6_STFLR_CMCF_POS (2U) +#define TMR6_STFLR_CMCF (0x00000004UL) +#define TMR6_STFLR_CMDF_POS (3U) +#define TMR6_STFLR_CMDF (0x00000008UL) +#define TMR6_STFLR_CMEF_POS (4U) +#define TMR6_STFLR_CMEF (0x00000010UL) +#define TMR6_STFLR_CMFF_POS (5U) +#define TMR6_STFLR_CMFF (0x00000020UL) +#define TMR6_STFLR_OVFF_POS (6U) +#define TMR6_STFLR_OVFF (0x00000040UL) +#define TMR6_STFLR_UDFF_POS (7U) +#define TMR6_STFLR_UDFF (0x00000080UL) +#define TMR6_STFLR_DTEF_POS (8U) +#define TMR6_STFLR_DTEF (0x00000100UL) +#define TMR6_STFLR_CMSAUF_POS (9U) +#define TMR6_STFLR_CMSAUF (0x00000200UL) +#define TMR6_STFLR_CMSADF_POS (10U) +#define TMR6_STFLR_CMSADF (0x00000400UL) +#define TMR6_STFLR_CMSBUF_POS (11U) +#define TMR6_STFLR_CMSBUF (0x00000800UL) +#define TMR6_STFLR_CMSBDF_POS (12U) +#define TMR6_STFLR_CMSBDF (0x00001000UL) +#define TMR6_STFLR_VPERNUM_POS (21U) +#define TMR6_STFLR_VPERNUM (0x00E00000UL) +#define TMR6_STFLR_DIRF_POS (31U) +#define TMR6_STFLR_DIRF (0x80000000UL) + +/* Bit definition for TMR6_HSTAR register */ +#define TMR6_HSTAR_HSTA0_POS (0U) +#define TMR6_HSTAR_HSTA0 (0x00000001UL) +#define TMR6_HSTAR_HSTA1_POS (1U) +#define TMR6_HSTAR_HSTA1 (0x00000002UL) +#define TMR6_HSTAR_HSTA4_POS (4U) +#define TMR6_HSTAR_HSTA4 (0x00000010UL) +#define TMR6_HSTAR_HSTA5_POS (5U) +#define TMR6_HSTAR_HSTA5 (0x00000020UL) +#define TMR6_HSTAR_HSTA6_POS (6U) +#define TMR6_HSTAR_HSTA6 (0x00000040UL) +#define TMR6_HSTAR_HSTA7_POS (7U) +#define TMR6_HSTAR_HSTA7 (0x00000080UL) +#define TMR6_HSTAR_HSTA8_POS (8U) +#define TMR6_HSTAR_HSTA8 (0x00000100UL) +#define TMR6_HSTAR_HSTA9_POS (9U) +#define TMR6_HSTAR_HSTA9 (0x00000200UL) +#define TMR6_HSTAR_HSTA10_POS (10U) +#define TMR6_HSTAR_HSTA10 (0x00000400UL) +#define TMR6_HSTAR_HSTA11_POS (11U) +#define TMR6_HSTAR_HSTA11 (0x00000800UL) +#define TMR6_HSTAR_STAS_POS (31U) +#define TMR6_HSTAR_STAS (0x80000000UL) + +/* Bit definition for TMR6_HSTPR register */ +#define TMR6_HSTPR_HSTP0_POS (0U) +#define TMR6_HSTPR_HSTP0 (0x00000001UL) +#define TMR6_HSTPR_HSTP1_POS (1U) +#define TMR6_HSTPR_HSTP1 (0x00000002UL) +#define TMR6_HSTPR_HSTP4_POS (4U) +#define TMR6_HSTPR_HSTP4 (0x00000010UL) +#define TMR6_HSTPR_HSTP5_POS (5U) +#define TMR6_HSTPR_HSTP5 (0x00000020UL) +#define TMR6_HSTPR_HSTP6_POS (6U) +#define TMR6_HSTPR_HSTP6 (0x00000040UL) +#define TMR6_HSTPR_HSTP7_POS (7U) +#define TMR6_HSTPR_HSTP7 (0x00000080UL) +#define TMR6_HSTPR_HSTP8_POS (8U) +#define TMR6_HSTPR_HSTP8 (0x00000100UL) +#define TMR6_HSTPR_HSTP9_POS (9U) +#define TMR6_HSTPR_HSTP9 (0x00000200UL) +#define TMR6_HSTPR_HSTP10_POS (10U) +#define TMR6_HSTPR_HSTP10 (0x00000400UL) +#define TMR6_HSTPR_HSTP11_POS (11U) +#define TMR6_HSTPR_HSTP11 (0x00000800UL) +#define TMR6_HSTPR_STPS_POS (31U) +#define TMR6_HSTPR_STPS (0x80000000UL) + +/* Bit definition for TMR6_HCLRR register */ +#define TMR6_HCLRR_HCLE0_POS (0U) +#define TMR6_HCLRR_HCLE0 (0x00000001UL) +#define TMR6_HCLRR_HCLE1_POS (1U) +#define TMR6_HCLRR_HCLE1 (0x00000002UL) +#define TMR6_HCLRR_HCLE4_POS (4U) +#define TMR6_HCLRR_HCLE4 (0x00000010UL) +#define TMR6_HCLRR_HCLE5_POS (5U) +#define TMR6_HCLRR_HCLE5 (0x00000020UL) +#define TMR6_HCLRR_HCLE6_POS (6U) +#define TMR6_HCLRR_HCLE6 (0x00000040UL) +#define TMR6_HCLRR_HCLE7_POS (7U) +#define TMR6_HCLRR_HCLE7 (0x00000080UL) +#define TMR6_HCLRR_HCLE8_POS (8U) +#define TMR6_HCLRR_HCLE8 (0x00000100UL) +#define TMR6_HCLRR_HCLE9_POS (9U) +#define TMR6_HCLRR_HCLE9 (0x00000200UL) +#define TMR6_HCLRR_HCLE10_POS (10U) +#define TMR6_HCLRR_HCLE10 (0x00000400UL) +#define TMR6_HCLRR_HCLE11_POS (11U) +#define TMR6_HCLRR_HCLE11 (0x00000800UL) +#define TMR6_HCLRR_CLES_POS (31U) +#define TMR6_HCLRR_CLES (0x80000000UL) + +/* Bit definition for TMR6_HCPAR register */ +#define TMR6_HCPAR_HCPA0_POS (0U) +#define TMR6_HCPAR_HCPA0 (0x00000001UL) +#define TMR6_HCPAR_HCPA1_POS (1U) +#define TMR6_HCPAR_HCPA1 (0x00000002UL) +#define TMR6_HCPAR_HCPA4_POS (4U) +#define TMR6_HCPAR_HCPA4 (0x00000010UL) +#define TMR6_HCPAR_HCPA5_POS (5U) +#define TMR6_HCPAR_HCPA5 (0x00000020UL) +#define TMR6_HCPAR_HCPA6_POS (6U) +#define TMR6_HCPAR_HCPA6 (0x00000040UL) +#define TMR6_HCPAR_HCPA7_POS (7U) +#define TMR6_HCPAR_HCPA7 (0x00000080UL) +#define TMR6_HCPAR_HCPA8_POS (8U) +#define TMR6_HCPAR_HCPA8 (0x00000100UL) +#define TMR6_HCPAR_HCPA9_POS (9U) +#define TMR6_HCPAR_HCPA9 (0x00000200UL) +#define TMR6_HCPAR_HCPA10_POS (10U) +#define TMR6_HCPAR_HCPA10 (0x00000400UL) +#define TMR6_HCPAR_HCPA11_POS (11U) +#define TMR6_HCPAR_HCPA11 (0x00000800UL) + +/* Bit definition for TMR6_HCPBR register */ +#define TMR6_HCPBR_HCPB0_POS (0U) +#define TMR6_HCPBR_HCPB0 (0x00000001UL) +#define TMR6_HCPBR_HCPB1_POS (1U) +#define TMR6_HCPBR_HCPB1 (0x00000002UL) +#define TMR6_HCPBR_HCPB4_POS (4U) +#define TMR6_HCPBR_HCPB4 (0x00000010UL) +#define TMR6_HCPBR_HCPB5_POS (5U) +#define TMR6_HCPBR_HCPB5 (0x00000020UL) +#define TMR6_HCPBR_HCPB6_POS (6U) +#define TMR6_HCPBR_HCPB6 (0x00000040UL) +#define TMR6_HCPBR_HCPB7_POS (7U) +#define TMR6_HCPBR_HCPB7 (0x00000080UL) +#define TMR6_HCPBR_HCPB8_POS (8U) +#define TMR6_HCPBR_HCPB8 (0x00000100UL) +#define TMR6_HCPBR_HCPB9_POS (9U) +#define TMR6_HCPBR_HCPB9 (0x00000200UL) +#define TMR6_HCPBR_HCPB10_POS (10U) +#define TMR6_HCPBR_HCPB10 (0x00000400UL) +#define TMR6_HCPBR_HCPB11_POS (11U) +#define TMR6_HCPBR_HCPB11 (0x00000800UL) + +/* Bit definition for TMR6_HCUPR register */ +#define TMR6_HCUPR_HCUP0_POS (0U) +#define TMR6_HCUPR_HCUP0 (0x00000001UL) +#define TMR6_HCUPR_HCUP1_POS (1U) +#define TMR6_HCUPR_HCUP1 (0x00000002UL) +#define TMR6_HCUPR_HCUP2_POS (2U) +#define TMR6_HCUPR_HCUP2 (0x00000004UL) +#define TMR6_HCUPR_HCUP3_POS (3U) +#define TMR6_HCUPR_HCUP3 (0x00000008UL) +#define TMR6_HCUPR_HCUP4_POS (4U) +#define TMR6_HCUPR_HCUP4 (0x00000010UL) +#define TMR6_HCUPR_HCUP5_POS (5U) +#define TMR6_HCUPR_HCUP5 (0x00000020UL) +#define TMR6_HCUPR_HCUP6_POS (6U) +#define TMR6_HCUPR_HCUP6 (0x00000040UL) +#define TMR6_HCUPR_HCUP7_POS (7U) +#define TMR6_HCUPR_HCUP7 (0x00000080UL) +#define TMR6_HCUPR_HCUP8_POS (8U) +#define TMR6_HCUPR_HCUP8 (0x00000100UL) +#define TMR6_HCUPR_HCUP9_POS (9U) +#define TMR6_HCUPR_HCUP9 (0x00000200UL) +#define TMR6_HCUPR_HCUP10_POS (10U) +#define TMR6_HCUPR_HCUP10 (0x00000400UL) +#define TMR6_HCUPR_HCUP11_POS (11U) +#define TMR6_HCUPR_HCUP11 (0x00000800UL) +#define TMR6_HCUPR_HCUP16_POS (16U) +#define TMR6_HCUPR_HCUP16 (0x00010000UL) +#define TMR6_HCUPR_HCUP17_POS (17U) +#define TMR6_HCUPR_HCUP17 (0x00020000UL) + +/* Bit definition for TMR6_HCDOR register */ +#define TMR6_HCDOR_HCDO0_POS (0U) +#define TMR6_HCDOR_HCDO0 (0x00000001UL) +#define TMR6_HCDOR_HCDO1_POS (1U) +#define TMR6_HCDOR_HCDO1 (0x00000002UL) +#define TMR6_HCDOR_HCDO2_POS (2U) +#define TMR6_HCDOR_HCDO2 (0x00000004UL) +#define TMR6_HCDOR_HCDO3_POS (3U) +#define TMR6_HCDOR_HCDO3 (0x00000008UL) +#define TMR6_HCDOR_HCDO4_POS (4U) +#define TMR6_HCDOR_HCDO4 (0x00000010UL) +#define TMR6_HCDOR_HCDO5_POS (5U) +#define TMR6_HCDOR_HCDO5 (0x00000020UL) +#define TMR6_HCDOR_HCDO6_POS (6U) +#define TMR6_HCDOR_HCDO6 (0x00000040UL) +#define TMR6_HCDOR_HCDO7_POS (7U) +#define TMR6_HCDOR_HCDO7 (0x00000080UL) +#define TMR6_HCDOR_HCDO8_POS (8U) +#define TMR6_HCDOR_HCDO8 (0x00000100UL) +#define TMR6_HCDOR_HCDO9_POS (9U) +#define TMR6_HCDOR_HCDO9 (0x00000200UL) +#define TMR6_HCDOR_HCDO10_POS (10U) +#define TMR6_HCDOR_HCDO10 (0x00000400UL) +#define TMR6_HCDOR_HCDO11_POS (11U) +#define TMR6_HCDOR_HCDO11 (0x00000800UL) +#define TMR6_HCDOR_HCDO16_POS (16U) +#define TMR6_HCDOR_HCDO16 (0x00010000UL) +#define TMR6_HCDOR_HCDO17_POS (17U) +#define TMR6_HCDOR_HCDO17 (0x00020000UL) + +/******************************************************************************* + Bit definition for Peripheral TMR6CR +*******************************************************************************/ +/* Bit definition for TMR6CR_SSTAR register */ +#define TMR6CR_SSTAR_SSTA1_POS (0U) +#define TMR6CR_SSTAR_SSTA1 (0x00000001UL) +#define TMR6CR_SSTAR_SSTA2_POS (1U) +#define TMR6CR_SSTAR_SSTA2 (0x00000002UL) +#define TMR6CR_SSTAR_SSTA3_POS (2U) +#define TMR6CR_SSTAR_SSTA3 (0x00000004UL) + +/* Bit definition for TMR6CR_SSTPR register */ +#define TMR6CR_SSTPR_SSTP1_POS (0U) +#define TMR6CR_SSTPR_SSTP1 (0x00000001UL) +#define TMR6CR_SSTPR_SSTP2_POS (1U) +#define TMR6CR_SSTPR_SSTP2 (0x00000002UL) +#define TMR6CR_SSTPR_SSTP3_POS (2U) +#define TMR6CR_SSTPR_SSTP3 (0x00000004UL) + +/* Bit definition for TMR6CR_SCLRR register */ +#define TMR6CR_SCLRR_SCLE1_POS (0U) +#define TMR6CR_SCLRR_SCLE1 (0x00000001UL) +#define TMR6CR_SCLRR_SCLE2_POS (1U) +#define TMR6CR_SCLRR_SCLE2 (0x00000002UL) +#define TMR6CR_SCLRR_SCLE3_POS (2U) +#define TMR6CR_SCLRR_SCLE3 (0x00000004UL) + +/******************************************************************************* + Bit definition for Peripheral TMRA +*******************************************************************************/ +/* Bit definition for TMRA_CNTER register */ +#define TMRA_CNTER_CNT (0xFFFFU) + +/* Bit definition for TMRA_PERAR register */ +#define TMRA_PERAR_PER (0xFFFFU) + +/* Bit definition for TMRA_CMPAR register */ +#define TMRA_CMPAR_CMP (0xFFFFU) + +/* Bit definition for TMRA_BCSTRL register */ +#define TMRA_BCSTRL_START_POS (0U) +#define TMRA_BCSTRL_START (0x01U) +#define TMRA_BCSTRL_DIR_POS (1U) +#define TMRA_BCSTRL_DIR (0x02U) +#define TMRA_BCSTRL_MODE_POS (2U) +#define TMRA_BCSTRL_MODE (0x04U) +#define TMRA_BCSTRL_SYNST_POS (3U) +#define TMRA_BCSTRL_SYNST (0x08U) +#define TMRA_BCSTRL_CKDIV_POS (4U) +#define TMRA_BCSTRL_CKDIV (0xF0U) + +/* Bit definition for TMRA_BCSTRH register */ +#define TMRA_BCSTRH_OVSTP_POS (0U) +#define TMRA_BCSTRH_OVSTP (0x01U) +#define TMRA_BCSTRH_ITENOVF_POS (4U) +#define TMRA_BCSTRH_ITENOVF (0x10U) +#define TMRA_BCSTRH_ITENUDF_POS (5U) +#define TMRA_BCSTRH_ITENUDF (0x20U) +#define TMRA_BCSTRH_OVFF_POS (6U) +#define TMRA_BCSTRH_OVFF (0x40U) +#define TMRA_BCSTRH_UDFF_POS (7U) +#define TMRA_BCSTRH_UDFF (0x80U) + +/* Bit definition for TMRA_HCONR register */ +#define TMRA_HCONR_HSTA0_POS (0U) +#define TMRA_HCONR_HSTA0 (0x0001U) +#define TMRA_HCONR_HSTA1_POS (1U) +#define TMRA_HCONR_HSTA1 (0x0002U) +#define TMRA_HCONR_HSTA2_POS (2U) +#define TMRA_HCONR_HSTA2 (0x0004U) +#define TMRA_HCONR_HSTP0_POS (4U) +#define TMRA_HCONR_HSTP0 (0x0010U) +#define TMRA_HCONR_HSTP1_POS (5U) +#define TMRA_HCONR_HSTP1 (0x0020U) +#define TMRA_HCONR_HSTP2_POS (6U) +#define TMRA_HCONR_HSTP2 (0x0040U) +#define TMRA_HCONR_HCLE0_POS (8U) +#define TMRA_HCONR_HCLE0 (0x0100U) +#define TMRA_HCONR_HCLE1_POS (9U) +#define TMRA_HCONR_HCLE1 (0x0200U) +#define TMRA_HCONR_HCLE2_POS (10U) +#define TMRA_HCONR_HCLE2 (0x0400U) +#define TMRA_HCONR_HCLE3_POS (12U) +#define TMRA_HCONR_HCLE3 (0x1000U) +#define TMRA_HCONR_HCLE4_POS (13U) +#define TMRA_HCONR_HCLE4 (0x2000U) +#define TMRA_HCONR_HCLE5_POS (14U) +#define TMRA_HCONR_HCLE5 (0x4000U) +#define TMRA_HCONR_HCLE6_POS (15U) +#define TMRA_HCONR_HCLE6 (0x8000U) + +/* Bit definition for TMRA_HCUPR register */ +#define TMRA_HCUPR_HCUP0_POS (0U) +#define TMRA_HCUPR_HCUP0 (0x0001U) +#define TMRA_HCUPR_HCUP1_POS (1U) +#define TMRA_HCUPR_HCUP1 (0x0002U) +#define TMRA_HCUPR_HCUP2_POS (2U) +#define TMRA_HCUPR_HCUP2 (0x0004U) +#define TMRA_HCUPR_HCUP3_POS (3U) +#define TMRA_HCUPR_HCUP3 (0x0008U) +#define TMRA_HCUPR_HCUP4_POS (4U) +#define TMRA_HCUPR_HCUP4 (0x0010U) +#define TMRA_HCUPR_HCUP5_POS (5U) +#define TMRA_HCUPR_HCUP5 (0x0020U) +#define TMRA_HCUPR_HCUP6_POS (6U) +#define TMRA_HCUPR_HCUP6 (0x0040U) +#define TMRA_HCUPR_HCUP7_POS (7U) +#define TMRA_HCUPR_HCUP7 (0x0080U) +#define TMRA_HCUPR_HCUP8_POS (8U) +#define TMRA_HCUPR_HCUP8 (0x0100U) +#define TMRA_HCUPR_HCUP9_POS (9U) +#define TMRA_HCUPR_HCUP9 (0x0200U) +#define TMRA_HCUPR_HCUP10_POS (10U) +#define TMRA_HCUPR_HCUP10 (0x0400U) +#define TMRA_HCUPR_HCUP11_POS (11U) +#define TMRA_HCUPR_HCUP11 (0x0800U) +#define TMRA_HCUPR_HCUP12_POS (12U) +#define TMRA_HCUPR_HCUP12 (0x1000U) + +/* Bit definition for TMRA_HCDOR register */ +#define TMRA_HCDOR_HCDO0_POS (0U) +#define TMRA_HCDOR_HCDO0 (0x0001U) +#define TMRA_HCDOR_HCDO1_POS (1U) +#define TMRA_HCDOR_HCDO1 (0x0002U) +#define TMRA_HCDOR_HCDO2_POS (2U) +#define TMRA_HCDOR_HCDO2 (0x0004U) +#define TMRA_HCDOR_HCDO3_POS (3U) +#define TMRA_HCDOR_HCDO3 (0x0008U) +#define TMRA_HCDOR_HCDO4_POS (4U) +#define TMRA_HCDOR_HCDO4 (0x0010U) +#define TMRA_HCDOR_HCDO5_POS (5U) +#define TMRA_HCDOR_HCDO5 (0x0020U) +#define TMRA_HCDOR_HCDO6_POS (6U) +#define TMRA_HCDOR_HCDO6 (0x0040U) +#define TMRA_HCDOR_HCDO7_POS (7U) +#define TMRA_HCDOR_HCDO7 (0x0080U) +#define TMRA_HCDOR_HCDO8_POS (8U) +#define TMRA_HCDOR_HCDO8 (0x0100U) +#define TMRA_HCDOR_HCDO9_POS (9U) +#define TMRA_HCDOR_HCDO9 (0x0200U) +#define TMRA_HCDOR_HCDO10_POS (10U) +#define TMRA_HCDOR_HCDO10 (0x0400U) +#define TMRA_HCDOR_HCDO11_POS (11U) +#define TMRA_HCDOR_HCDO11 (0x0800U) +#define TMRA_HCDOR_HCDO12_POS (12U) +#define TMRA_HCDOR_HCDO12 (0x1000U) + +/* Bit definition for TMRA_ICONR register */ +#define TMRA_ICONR_ITEN1_POS (0U) +#define TMRA_ICONR_ITEN1 (0x0001U) +#define TMRA_ICONR_ITEN2_POS (1U) +#define TMRA_ICONR_ITEN2 (0x0002U) +#define TMRA_ICONR_ITEN3_POS (2U) +#define TMRA_ICONR_ITEN3 (0x0004U) +#define TMRA_ICONR_ITEN4_POS (3U) +#define TMRA_ICONR_ITEN4 (0x0008U) +#define TMRA_ICONR_ITEN5_POS (4U) +#define TMRA_ICONR_ITEN5 (0x0010U) +#define TMRA_ICONR_ITEN6_POS (5U) +#define TMRA_ICONR_ITEN6 (0x0020U) +#define TMRA_ICONR_ITEN7_POS (6U) +#define TMRA_ICONR_ITEN7 (0x0040U) +#define TMRA_ICONR_ITEN8_POS (7U) +#define TMRA_ICONR_ITEN8 (0x0080U) + +/* Bit definition for TMRA_ECONR register */ +#define TMRA_ECONR_ETEN1_POS (0U) +#define TMRA_ECONR_ETEN1 (0x0001U) +#define TMRA_ECONR_ETEN2_POS (1U) +#define TMRA_ECONR_ETEN2 (0x0002U) +#define TMRA_ECONR_ETEN3_POS (2U) +#define TMRA_ECONR_ETEN3 (0x0004U) +#define TMRA_ECONR_ETEN4_POS (3U) +#define TMRA_ECONR_ETEN4 (0x0008U) +#define TMRA_ECONR_ETEN5_POS (4U) +#define TMRA_ECONR_ETEN5 (0x0010U) +#define TMRA_ECONR_ETEN6_POS (5U) +#define TMRA_ECONR_ETEN6 (0x0020U) +#define TMRA_ECONR_ETEN7_POS (6U) +#define TMRA_ECONR_ETEN7 (0x0040U) +#define TMRA_ECONR_ETEN8_POS (7U) +#define TMRA_ECONR_ETEN8 (0x0080U) + +/* Bit definition for TMRA_FCONR register */ +#define TMRA_FCONR_NOFIENTG_POS (0U) +#define TMRA_FCONR_NOFIENTG (0x0001U) +#define TMRA_FCONR_NOFICKTG_POS (1U) +#define TMRA_FCONR_NOFICKTG (0x0006U) +#define TMRA_FCONR_NOFIENCA_POS (8U) +#define TMRA_FCONR_NOFIENCA (0x0100U) +#define TMRA_FCONR_NOFICKCA_POS (9U) +#define TMRA_FCONR_NOFICKCA (0x0600U) +#define TMRA_FCONR_NOFIENCB_POS (12U) +#define TMRA_FCONR_NOFIENCB (0x1000U) +#define TMRA_FCONR_NOFICKCB_POS (13U) +#define TMRA_FCONR_NOFICKCB (0x6000U) + +/* Bit definition for TMRA_STFLR register */ +#define TMRA_STFLR_CMPF1_POS (0U) +#define TMRA_STFLR_CMPF1 (0x0001U) +#define TMRA_STFLR_CMPF2_POS (1U) +#define TMRA_STFLR_CMPF2 (0x0002U) +#define TMRA_STFLR_CMPF3_POS (2U) +#define TMRA_STFLR_CMPF3 (0x0004U) +#define TMRA_STFLR_CMPF4_POS (3U) +#define TMRA_STFLR_CMPF4 (0x0008U) +#define TMRA_STFLR_CMPF5_POS (4U) +#define TMRA_STFLR_CMPF5 (0x0010U) +#define TMRA_STFLR_CMPF6_POS (5U) +#define TMRA_STFLR_CMPF6 (0x0020U) +#define TMRA_STFLR_CMPF7_POS (6U) +#define TMRA_STFLR_CMPF7 (0x0040U) +#define TMRA_STFLR_CMPF8_POS (7U) +#define TMRA_STFLR_CMPF8 (0x0080U) + +/* Bit definition for TMRA_BCONR register */ +#define TMRA_BCONR_BEN_POS (0U) +#define TMRA_BCONR_BEN (0x0001U) +#define TMRA_BCONR_BSE0_POS (1U) +#define TMRA_BCONR_BSE0 (0x0002U) +#define TMRA_BCONR_BSE1_POS (2U) +#define TMRA_BCONR_BSE1 (0x0004U) + +/* Bit definition for TMRA_CCONR register */ +#define TMRA_CCONR_CAPMD_POS (0U) +#define TMRA_CCONR_CAPMD (0x0001U) +#define TMRA_CCONR_HICP0_POS (4U) +#define TMRA_CCONR_HICP0 (0x0010U) +#define TMRA_CCONR_HICP1_POS (5U) +#define TMRA_CCONR_HICP1 (0x0020U) +#define TMRA_CCONR_HICP2_POS (6U) +#define TMRA_CCONR_HICP2 (0x0040U) +#define TMRA_CCONR_HICP3_POS (8U) +#define TMRA_CCONR_HICP3 (0x0100U) +#define TMRA_CCONR_HICP4_POS (9U) +#define TMRA_CCONR_HICP4 (0x0200U) +#define TMRA_CCONR_NOFIENCP_POS (12U) +#define TMRA_CCONR_NOFIENCP (0x1000U) +#define TMRA_CCONR_NOFICKCP_POS (13U) +#define TMRA_CCONR_NOFICKCP (0x6000U) +#define TMRA_CCONR_NOFICKCP_0 (0x2000U) +#define TMRA_CCONR_NOFICKCP_1 (0x4000U) + +/* Bit definition for TMRA_PCONR register */ +#define TMRA_PCONR_STAC_POS (0U) +#define TMRA_PCONR_STAC (0x0003U) +#define TMRA_PCONR_STAC_0 (0x0001U) +#define TMRA_PCONR_STAC_1 (0x0002U) +#define TMRA_PCONR_STPC_POS (2U) +#define TMRA_PCONR_STPC (0x000CU) +#define TMRA_PCONR_STPC_0 (0x0004U) +#define TMRA_PCONR_STPC_1 (0x0008U) +#define TMRA_PCONR_CMPC_POS (4U) +#define TMRA_PCONR_CMPC (0x0030U) +#define TMRA_PCONR_CMPC_0 (0x0010U) +#define TMRA_PCONR_CMPC_1 (0x0020U) +#define TMRA_PCONR_PERC_POS (6U) +#define TMRA_PCONR_PERC (0x00C0U) +#define TMRA_PCONR_PERC_0 (0x0040U) +#define TMRA_PCONR_PERC_1 (0x0080U) +#define TMRA_PCONR_FORC_POS (8U) +#define TMRA_PCONR_FORC (0x0300U) +#define TMRA_PCONR_FORC_0 (0x0100U) +#define TMRA_PCONR_FORC_1 (0x0200U) +#define TMRA_PCONR_OUTEN_POS (12U) +#define TMRA_PCONR_OUTEN (0x1000U) + +/******************************************************************************* + Bit definition for Peripheral TRNG +*******************************************************************************/ +/* Bit definition for TRNG_CR register */ +#define TRNG_CR_EN_POS (0U) +#define TRNG_CR_EN (0x00000001UL) +#define TRNG_CR_RUN_POS (1U) +#define TRNG_CR_RUN (0x00000002UL) + +/* Bit definition for TRNG_MR register */ +#define TRNG_MR_LOAD_POS (0U) +#define TRNG_MR_LOAD (0x00000001UL) +#define TRNG_MR_CNT_POS (2U) +#define TRNG_MR_CNT (0x0000001CUL) + +/* Bit definition for TRNG_DR0 register */ +#define TRNG_DR0 (0xFFFFFFFFUL) + +/* Bit definition for TRNG_DR1 register */ +#define TRNG_DR1 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral USART +*******************************************************************************/ +/* Bit definition for USART_SR register */ +#define USART_SR_PE_POS (0U) +#define USART_SR_PE (0x00000001UL) +#define USART_SR_FE_POS (1U) +#define USART_SR_FE (0x00000002UL) +#define USART_SR_ORE_POS (3U) +#define USART_SR_ORE (0x00000008UL) +#define USART_SR_RXNE_POS (5U) +#define USART_SR_RXNE (0x00000020UL) +#define USART_SR_TC_POS (6U) +#define USART_SR_TC (0x00000040UL) +#define USART_SR_TXE_POS (7U) +#define USART_SR_TXE (0x00000080UL) +#define USART_SR_RTOF_POS (8U) +#define USART_SR_RTOF (0x00000100UL) +#define USART_SR_MPB_POS (16U) +#define USART_SR_MPB (0x00010000UL) + +/* Bit definition for USART_TDR register */ +#define USART_TDR_TDR_POS (0U) +#define USART_TDR_TDR (0x01FFU) +#define USART_TDR_MPID_POS (9U) +#define USART_TDR_MPID (0x0200U) + +/* Bit definition for USART_RDR register */ +#define USART_RDR_RDR (0x01FFU) + +/* Bit definition for USART_BRR register */ +#define USART_BRR_DIV_FRACTION_POS (0U) +#define USART_BRR_DIV_FRACTION (0x0000007FUL) +#define USART_BRR_DIV_INTEGER_POS (8U) +#define USART_BRR_DIV_INTEGER (0x0000FF00UL) + +/* Bit definition for USART_CR1 register */ +#define USART_CR1_RTOE_POS (0U) +#define USART_CR1_RTOE (0x00000001UL) +#define USART_CR1_RTOIE_POS (1U) +#define USART_CR1_RTOIE (0x00000002UL) +#define USART_CR1_RE_POS (2U) +#define USART_CR1_RE (0x00000004UL) +#define USART_CR1_TE_POS (3U) +#define USART_CR1_TE (0x00000008UL) +#define USART_CR1_SLME_POS (4U) +#define USART_CR1_SLME (0x00000010UL) +#define USART_CR1_RIE_POS (5U) +#define USART_CR1_RIE (0x00000020UL) +#define USART_CR1_TCIE_POS (6U) +#define USART_CR1_TCIE (0x00000040UL) +#define USART_CR1_TXEIE_POS (7U) +#define USART_CR1_TXEIE (0x00000080UL) +#define USART_CR1_PS_POS (9U) +#define USART_CR1_PS (0x00000200UL) +#define USART_CR1_PCE_POS (10U) +#define USART_CR1_PCE (0x00000400UL) +#define USART_CR1_M_POS (12U) +#define USART_CR1_M (0x00001000UL) +#define USART_CR1_OVER8_POS (15U) +#define USART_CR1_OVER8 (0x00008000UL) +#define USART_CR1_CPE_POS (16U) +#define USART_CR1_CPE (0x00010000UL) +#define USART_CR1_CFE_POS (17U) +#define USART_CR1_CFE (0x00020000UL) +#define USART_CR1_CORE_POS (19U) +#define USART_CR1_CORE (0x00080000UL) +#define USART_CR1_CRTOF_POS (20U) +#define USART_CR1_CRTOF (0x00100000UL) +#define USART_CR1_MS_POS (24U) +#define USART_CR1_MS (0x01000000UL) +#define USART_CR1_ML_POS (28U) +#define USART_CR1_ML (0x10000000UL) +#define USART_CR1_FBME_POS (29U) +#define USART_CR1_FBME (0x20000000UL) +#define USART_CR1_NFE_POS (30U) +#define USART_CR1_NFE (0x40000000UL) +#define USART_CR1_SBS_POS (31U) +#define USART_CR1_SBS (0x80000000UL) + +/* Bit definition for USART_CR2 register */ +#define USART_CR2_MPE_POS (0U) +#define USART_CR2_MPE (0x00000001UL) +#define USART_CR2_CLKC_POS (11U) +#define USART_CR2_CLKC (0x00001800UL) +#define USART_CR2_CLKC_0 (0x00000800UL) +#define USART_CR2_CLKC_1 (0x00001000UL) +#define USART_CR2_STOP_POS (13U) +#define USART_CR2_STOP (0x00002000UL) + +/* Bit definition for USART_CR3 register */ +#define USART_CR3_SCEN_POS (5U) +#define USART_CR3_SCEN (0x00000020UL) +#define USART_CR3_CTSE_POS (9U) +#define USART_CR3_CTSE (0x00000200UL) +#define USART_CR3_BCN_POS (21U) +#define USART_CR3_BCN (0x00E00000UL) + +/* Bit definition for USART_PR register */ +#define USART_PR_PSC (0x00000003UL) +#define USART_PR_PSC_0 (0x00000001UL) +#define USART_PR_PSC_1 (0x00000002UL) + +/******************************************************************************* + Bit definition for Peripheral USBFS +*******************************************************************************/ +/* Bit definition for USBFS_GVBUSCFG register */ +#define USBFS_GVBUSCFG_VBUSOVEN_POS (6U) +#define USBFS_GVBUSCFG_VBUSOVEN (0x00000040UL) +#define USBFS_GVBUSCFG_VBUSVAL_POS (7U) +#define USBFS_GVBUSCFG_VBUSVAL (0x00000080UL) + +/* Bit definition for USBFS_GAHBCFG register */ +#define USBFS_GAHBCFG_GINTMSK_POS (0U) +#define USBFS_GAHBCFG_GINTMSK (0x00000001UL) +#define USBFS_GAHBCFG_HBSTLEN_POS (1U) +#define USBFS_GAHBCFG_HBSTLEN (0x0000001EUL) +#define USBFS_GAHBCFG_DMAEN_POS (5U) +#define USBFS_GAHBCFG_DMAEN (0x00000020UL) +#define USBFS_GAHBCFG_TXFELVL_POS (7U) +#define USBFS_GAHBCFG_TXFELVL (0x00000080UL) +#define USBFS_GAHBCFG_PTXFELVL_POS (8U) +#define USBFS_GAHBCFG_PTXFELVL (0x00000100UL) + +/* Bit definition for USBFS_GUSBCFG register */ +#define USBFS_GUSBCFG_TOCAL_POS (0U) +#define USBFS_GUSBCFG_TOCAL (0x00000007UL) +#define USBFS_GUSBCFG_PHYSEL_POS (6U) +#define USBFS_GUSBCFG_PHYSEL (0x00000040UL) +#define USBFS_GUSBCFG_TRDT_POS (10U) +#define USBFS_GUSBCFG_TRDT (0x00003C00UL) +#define USBFS_GUSBCFG_FHMOD_POS (29U) +#define USBFS_GUSBCFG_FHMOD (0x20000000UL) +#define USBFS_GUSBCFG_FDMOD_POS (30U) +#define USBFS_GUSBCFG_FDMOD (0x40000000UL) + +/* Bit definition for USBFS_GRSTCTL register */ +#define USBFS_GRSTCTL_CSRST_POS (0U) +#define USBFS_GRSTCTL_CSRST (0x00000001UL) +#define USBFS_GRSTCTL_HSRST_POS (1U) +#define USBFS_GRSTCTL_HSRST (0x00000002UL) +#define USBFS_GRSTCTL_FCRST_POS (2U) +#define USBFS_GRSTCTL_FCRST (0x00000004UL) +#define USBFS_GRSTCTL_RXFFLSH_POS (4U) +#define USBFS_GRSTCTL_RXFFLSH (0x00000010UL) +#define USBFS_GRSTCTL_TXFFLSH_POS (5U) +#define USBFS_GRSTCTL_TXFFLSH (0x00000020UL) +#define USBFS_GRSTCTL_TXFNUM_POS (6U) +#define USBFS_GRSTCTL_TXFNUM (0x000007C0UL) +#define USBFS_GRSTCTL_DMAREQ_POS (30U) +#define USBFS_GRSTCTL_DMAREQ (0x40000000UL) +#define USBFS_GRSTCTL_AHBIDL_POS (31U) +#define USBFS_GRSTCTL_AHBIDL (0x80000000UL) + +/* Bit definition for USBFS_GINTSTS register */ +#define USBFS_GINTSTS_CMOD_POS (0U) +#define USBFS_GINTSTS_CMOD (0x00000001UL) +#define USBFS_GINTSTS_MMIS_POS (1U) +#define USBFS_GINTSTS_MMIS (0x00000002UL) +#define USBFS_GINTSTS_SOF_POS (3U) +#define USBFS_GINTSTS_SOF (0x00000008UL) +#define USBFS_GINTSTS_RXFNE_POS (4U) +#define USBFS_GINTSTS_RXFNE (0x00000010UL) +#define USBFS_GINTSTS_NPTXFE_POS (5U) +#define USBFS_GINTSTS_NPTXFE (0x00000020UL) +#define USBFS_GINTSTS_GINAKEFF_POS (6U) +#define USBFS_GINTSTS_GINAKEFF (0x00000040UL) +#define USBFS_GINTSTS_GONAKEFF_POS (7U) +#define USBFS_GINTSTS_GONAKEFF (0x00000080UL) +#define USBFS_GINTSTS_ESUSP_POS (10U) +#define USBFS_GINTSTS_ESUSP (0x00000400UL) +#define USBFS_GINTSTS_USBSUSP_POS (11U) +#define USBFS_GINTSTS_USBSUSP (0x00000800UL) +#define USBFS_GINTSTS_USBRST_POS (12U) +#define USBFS_GINTSTS_USBRST (0x00001000UL) +#define USBFS_GINTSTS_ENUMDNE_POS (13U) +#define USBFS_GINTSTS_ENUMDNE (0x00002000UL) +#define USBFS_GINTSTS_ISOODRP_POS (14U) +#define USBFS_GINTSTS_ISOODRP (0x00004000UL) +#define USBFS_GINTSTS_EOPF_POS (15U) +#define USBFS_GINTSTS_EOPF (0x00008000UL) +#define USBFS_GINTSTS_IEPINT_POS (18U) +#define USBFS_GINTSTS_IEPINT (0x00040000UL) +#define USBFS_GINTSTS_OEPINT_POS (19U) +#define USBFS_GINTSTS_OEPINT (0x00080000UL) +#define USBFS_GINTSTS_IISOIXFR_POS (20U) +#define USBFS_GINTSTS_IISOIXFR (0x00100000UL) +#define USBFS_GINTSTS_IPXFR_INCOMPISOOUT_POS (21U) +#define USBFS_GINTSTS_IPXFR_INCOMPISOOUT (0x00200000UL) +#define USBFS_GINTSTS_DATAFSUSP_POS (22U) +#define USBFS_GINTSTS_DATAFSUSP (0x00400000UL) +#define USBFS_GINTSTS_HPRTINT_POS (24U) +#define USBFS_GINTSTS_HPRTINT (0x01000000UL) +#define USBFS_GINTSTS_HCINT_POS (25U) +#define USBFS_GINTSTS_HCINT (0x02000000UL) +#define USBFS_GINTSTS_PTXFE_POS (26U) +#define USBFS_GINTSTS_PTXFE (0x04000000UL) +#define USBFS_GINTSTS_CIDSCHG_POS (28U) +#define USBFS_GINTSTS_CIDSCHG (0x10000000UL) +#define USBFS_GINTSTS_DISCINT_POS (29U) +#define USBFS_GINTSTS_DISCINT (0x20000000UL) +#define USBFS_GINTSTS_VBUSVINT_POS (30U) +#define USBFS_GINTSTS_VBUSVINT (0x40000000UL) +#define USBFS_GINTSTS_WKUINT_POS (31U) +#define USBFS_GINTSTS_WKUINT (0x80000000UL) + +/* Bit definition for USBFS_GINTMSK register */ +#define USBFS_GINTMSK_MMISM_POS (1U) +#define USBFS_GINTMSK_MMISM (0x00000002UL) +#define USBFS_GINTMSK_SOFM_POS (3U) +#define USBFS_GINTMSK_SOFM (0x00000008UL) +#define USBFS_GINTMSK_RXFNEM_POS (4U) +#define USBFS_GINTMSK_RXFNEM (0x00000010UL) +#define USBFS_GINTMSK_NPTXFEM_POS (5U) +#define USBFS_GINTMSK_NPTXFEM (0x00000020UL) +#define USBFS_GINTMSK_GINAKEFFM_POS (6U) +#define USBFS_GINTMSK_GINAKEFFM (0x00000040UL) +#define USBFS_GINTMSK_GONAKEFFM_POS (7U) +#define USBFS_GINTMSK_GONAKEFFM (0x00000080UL) +#define USBFS_GINTMSK_ESUSPM_POS (10U) +#define USBFS_GINTMSK_ESUSPM (0x00000400UL) +#define USBFS_GINTMSK_USBSUSPM_POS (11U) +#define USBFS_GINTMSK_USBSUSPM (0x00000800UL) +#define USBFS_GINTMSK_USBRSTM_POS (12U) +#define USBFS_GINTMSK_USBRSTM (0x00001000UL) +#define USBFS_GINTMSK_ENUMDNEM_POS (13U) +#define USBFS_GINTMSK_ENUMDNEM (0x00002000UL) +#define USBFS_GINTMSK_ISOODRPM_POS (14U) +#define USBFS_GINTMSK_ISOODRPM (0x00004000UL) +#define USBFS_GINTMSK_EOPFM_POS (15U) +#define USBFS_GINTMSK_EOPFM (0x00008000UL) +#define USBFS_GINTMSK_IEPIM_POS (18U) +#define USBFS_GINTMSK_IEPIM (0x00040000UL) +#define USBFS_GINTMSK_OEPIM_POS (19U) +#define USBFS_GINTMSK_OEPIM (0x00080000UL) +#define USBFS_GINTMSK_IISOIXFRM_POS (20U) +#define USBFS_GINTMSK_IISOIXFRM (0x00100000UL) +#define USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM_POS (21U) +#define USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM (0x00200000UL) +#define USBFS_GINTMSK_DATAFSUSPM_POS (22U) +#define USBFS_GINTMSK_DATAFSUSPM (0x00400000UL) +#define USBFS_GINTMSK_HPRTIM_POS (24U) +#define USBFS_GINTMSK_HPRTIM (0x01000000UL) +#define USBFS_GINTMSK_HCIM_POS (25U) +#define USBFS_GINTMSK_HCIM (0x02000000UL) +#define USBFS_GINTMSK_PTXFEM_POS (26U) +#define USBFS_GINTMSK_PTXFEM (0x04000000UL) +#define USBFS_GINTMSK_CIDSCHGM_POS (28U) +#define USBFS_GINTMSK_CIDSCHGM (0x10000000UL) +#define USBFS_GINTMSK_DISCIM_POS (29U) +#define USBFS_GINTMSK_DISCIM (0x20000000UL) +#define USBFS_GINTMSK_VBUSVIM_POS (30U) +#define USBFS_GINTMSK_VBUSVIM (0x40000000UL) +#define USBFS_GINTMSK_WKUIM_POS (31U) +#define USBFS_GINTMSK_WKUIM (0x80000000UL) + +/* Bit definition for USBFS_GRXSTSR register */ +#define USBFS_GRXSTSR_CHNUM_EPNUM_POS (0U) +#define USBFS_GRXSTSR_CHNUM_EPNUM (0x0000000FUL) +#define USBFS_GRXSTSR_BCNT_POS (4U) +#define USBFS_GRXSTSR_BCNT (0x00007FF0UL) +#define USBFS_GRXSTSR_DPID_POS (15U) +#define USBFS_GRXSTSR_DPID (0x00018000UL) +#define USBFS_GRXSTSR_PKTSTS_POS (17U) +#define USBFS_GRXSTSR_PKTSTS (0x001E0000UL) + +/* Bit definition for USBFS_GRXSTSP register */ +#define USBFS_GRXSTSP_CHNUM_EPNUM_POS (0U) +#define USBFS_GRXSTSP_CHNUM_EPNUM (0x0000000FUL) +#define USBFS_GRXSTSP_BCNT_POS (4U) +#define USBFS_GRXSTSP_BCNT (0x00007FF0UL) +#define USBFS_GRXSTSP_DPID_POS (15U) +#define USBFS_GRXSTSP_DPID (0x00018000UL) +#define USBFS_GRXSTSP_PKTSTS_POS (17U) +#define USBFS_GRXSTSP_PKTSTS (0x001E0000UL) + +/* Bit definition for USBFS_GRXFSIZ register */ +#define USBFS_GRXFSIZ_RXFD (0x000007FFUL) + +/* Bit definition for USBFS_HNPTXFSIZ register */ +#define USBFS_HNPTXFSIZ_NPTXFSA_POS (0U) +#define USBFS_HNPTXFSIZ_NPTXFSA (0x0000FFFFUL) +#define USBFS_HNPTXFSIZ_NPTXFD_POS (16U) +#define USBFS_HNPTXFSIZ_NPTXFD (0xFFFF0000UL) + +/* Bit definition for USBFS_HNPTXSTS register */ +#define USBFS_HNPTXSTS_NPTXFSAV_POS (0U) +#define USBFS_HNPTXSTS_NPTXFSAV (0x0000FFFFUL) +#define USBFS_HNPTXSTS_NPTQXSAV_POS (16U) +#define USBFS_HNPTXSTS_NPTQXSAV (0x00FF0000UL) +#define USBFS_HNPTXSTS_NPTXQTOP_POS (24U) +#define USBFS_HNPTXSTS_NPTXQTOP (0x7F000000UL) + +/* Bit definition for USBFS_CID register */ +#define USBFS_CID (0xFFFFFFFFUL) + +/* Bit definition for USBFS_HPTXFSIZ register */ +#define USBFS_HPTXFSIZ_PTXSA_POS (0U) +#define USBFS_HPTXFSIZ_PTXSA (0x00000FFFUL) +#define USBFS_HPTXFSIZ_PTXFD_POS (16U) +#define USBFS_HPTXFSIZ_PTXFD (0x07FF0000UL) + +/* Bit definition for USBFS_DIEPTXF register */ +#define USBFS_DIEPTXF_INEPTXSA_POS (0U) +#define USBFS_DIEPTXF_INEPTXSA (0x00000FFFUL) +#define USBFS_DIEPTXF_INEPTXFD_POS (16U) +#define USBFS_DIEPTXF_INEPTXFD (0x03FF0000UL) + +/* Bit definition for USBFS_HCFG register */ +#define USBFS_HCFG_FSLSPCS_POS (0U) +#define USBFS_HCFG_FSLSPCS (0x00000003UL) +#define USBFS_HCFG_FSLSS_POS (2U) +#define USBFS_HCFG_FSLSS (0x00000004UL) + +/* Bit definition for USBFS_HFIR register */ +#define USBFS_HFIR_FRIVL (0x0000FFFFUL) + +/* Bit definition for USBFS_HFNUM register */ +#define USBFS_HFNUM_FRNUM_POS (0U) +#define USBFS_HFNUM_FRNUM (0x0000FFFFUL) +#define USBFS_HFNUM_FTREM_POS (16U) +#define USBFS_HFNUM_FTREM (0xFFFF0000UL) + +/* Bit definition for USBFS_HPTXSTS register */ +#define USBFS_HPTXSTS_PTXFSAVL_POS (0U) +#define USBFS_HPTXSTS_PTXFSAVL (0x0000FFFFUL) +#define USBFS_HPTXSTS_PTXQSAV_POS (16U) +#define USBFS_HPTXSTS_PTXQSAV (0x00FF0000UL) +#define USBFS_HPTXSTS_PTXQTOP_POS (24U) +#define USBFS_HPTXSTS_PTXQTOP (0xFF000000UL) + +/* Bit definition for USBFS_HAINT register */ +#define USBFS_HAINT_HAINT (0x00000FFFUL) + +/* Bit definition for USBFS_HAINTMSK register */ +#define USBFS_HAINTMSK_HAINTM (0x00000FFFUL) + +/* Bit definition for USBFS_HPRT register */ +#define USBFS_HPRT_PCSTS_POS (0U) +#define USBFS_HPRT_PCSTS (0x00000001UL) +#define USBFS_HPRT_PCDET_POS (1U) +#define USBFS_HPRT_PCDET (0x00000002UL) +#define USBFS_HPRT_PENA_POS (2U) +#define USBFS_HPRT_PENA (0x00000004UL) +#define USBFS_HPRT_PENCHNG_POS (3U) +#define USBFS_HPRT_PENCHNG (0x00000008UL) +#define USBFS_HPRT_PRES_POS (6U) +#define USBFS_HPRT_PRES (0x00000040UL) +#define USBFS_HPRT_PSUSP_POS (7U) +#define USBFS_HPRT_PSUSP (0x00000080UL) +#define USBFS_HPRT_PRST_POS (8U) +#define USBFS_HPRT_PRST (0x00000100UL) +#define USBFS_HPRT_PLSTS_POS (10U) +#define USBFS_HPRT_PLSTS (0x00000C00UL) +#define USBFS_HPRT_PWPR_POS (12U) +#define USBFS_HPRT_PWPR (0x00001000UL) +#define USBFS_HPRT_PSPD_POS (17U) +#define USBFS_HPRT_PSPD (0x00060000UL) + +/* Bit definition for USBFS_HCCHAR register */ +#define USBFS_HCCHAR_MPSIZ_POS (0U) +#define USBFS_HCCHAR_MPSIZ (0x000007FFUL) +#define USBFS_HCCHAR_EPNUM_POS (11U) +#define USBFS_HCCHAR_EPNUM (0x00007800UL) +#define USBFS_HCCHAR_EPDIR_POS (15U) +#define USBFS_HCCHAR_EPDIR (0x00008000UL) +#define USBFS_HCCHAR_LSDEV_POS (17U) +#define USBFS_HCCHAR_LSDEV (0x00020000UL) +#define USBFS_HCCHAR_EPTYP_POS (18U) +#define USBFS_HCCHAR_EPTYP (0x000C0000UL) +#define USBFS_HCCHAR_DAD_POS (22U) +#define USBFS_HCCHAR_DAD (0x1FC00000UL) +#define USBFS_HCCHAR_ODDFRM_POS (29U) +#define USBFS_HCCHAR_ODDFRM (0x20000000UL) +#define USBFS_HCCHAR_CHDIS_POS (30U) +#define USBFS_HCCHAR_CHDIS (0x40000000UL) +#define USBFS_HCCHAR_CHENA_POS (31U) +#define USBFS_HCCHAR_CHENA (0x80000000UL) + +/* Bit definition for USBFS_HCINT register */ +#define USBFS_HCINT_XFRC_POS (0U) +#define USBFS_HCINT_XFRC (0x00000001UL) +#define USBFS_HCINT_CHH_POS (1U) +#define USBFS_HCINT_CHH (0x00000002UL) +#define USBFS_HCINT_STALL_POS (3U) +#define USBFS_HCINT_STALL (0x00000008UL) +#define USBFS_HCINT_NAK_POS (4U) +#define USBFS_HCINT_NAK (0x00000010UL) +#define USBFS_HCINT_ACK_POS (5U) +#define USBFS_HCINT_ACK (0x00000020UL) +#define USBFS_HCINT_TXERR_POS (7U) +#define USBFS_HCINT_TXERR (0x00000080UL) +#define USBFS_HCINT_BBERR_POS (8U) +#define USBFS_HCINT_BBERR (0x00000100UL) +#define USBFS_HCINT_FRMOR_POS (9U) +#define USBFS_HCINT_FRMOR (0x00000200UL) +#define USBFS_HCINT_DTERR_POS (10U) +#define USBFS_HCINT_DTERR (0x00000400UL) + +/* Bit definition for USBFS_HCINTMSK register */ +#define USBFS_HCINTMSK_XFRCM_POS (0U) +#define USBFS_HCINTMSK_XFRCM (0x00000001UL) +#define USBFS_HCINTMSK_CHHM_POS (1U) +#define USBFS_HCINTMSK_CHHM (0x00000002UL) +#define USBFS_HCINTMSK_STALLM_POS (3U) +#define USBFS_HCINTMSK_STALLM (0x00000008UL) +#define USBFS_HCINTMSK_NAKM_POS (4U) +#define USBFS_HCINTMSK_NAKM (0x00000010UL) +#define USBFS_HCINTMSK_ACKM_POS (5U) +#define USBFS_HCINTMSK_ACKM (0x00000020UL) +#define USBFS_HCINTMSK_TXERRM_POS (7U) +#define USBFS_HCINTMSK_TXERRM (0x00000080UL) +#define USBFS_HCINTMSK_BBERRM_POS (8U) +#define USBFS_HCINTMSK_BBERRM (0x00000100UL) +#define USBFS_HCINTMSK_FRMORM_POS (9U) +#define USBFS_HCINTMSK_FRMORM (0x00000200UL) +#define USBFS_HCINTMSK_DTERRM_POS (10U) +#define USBFS_HCINTMSK_DTERRM (0x00000400UL) + +/* Bit definition for USBFS_HCTSIZ register */ +#define USBFS_HCTSIZ_XFRSIZ_POS (0U) +#define USBFS_HCTSIZ_XFRSIZ (0x0007FFFFUL) +#define USBFS_HCTSIZ_PKTCNT_POS (19U) +#define USBFS_HCTSIZ_PKTCNT (0x1FF80000UL) +#define USBFS_HCTSIZ_DPID_POS (29U) +#define USBFS_HCTSIZ_DPID (0x60000000UL) + +/* Bit definition for USBFS_HCDMA register */ +#define USBFS_HCDMA (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DCFG register */ +#define USBFS_DCFG_DSPD_POS (0U) +#define USBFS_DCFG_DSPD (0x00000003UL) +#define USBFS_DCFG_NZLSOHSK_POS (2U) +#define USBFS_DCFG_NZLSOHSK (0x00000004UL) +#define USBFS_DCFG_DAD_POS (4U) +#define USBFS_DCFG_DAD (0x000007F0UL) +#define USBFS_DCFG_PFIVL_POS (11U) +#define USBFS_DCFG_PFIVL (0x00001800UL) + +/* Bit definition for USBFS_DCTL register */ +#define USBFS_DCTL_RWUSIG_POS (0U) +#define USBFS_DCTL_RWUSIG (0x00000001UL) +#define USBFS_DCTL_SDIS_POS (1U) +#define USBFS_DCTL_SDIS (0x00000002UL) +#define USBFS_DCTL_GINSTS_POS (2U) +#define USBFS_DCTL_GINSTS (0x00000004UL) +#define USBFS_DCTL_GONSTS_POS (3U) +#define USBFS_DCTL_GONSTS (0x00000008UL) +#define USBFS_DCTL_SGINAK_POS (7U) +#define USBFS_DCTL_SGINAK (0x00000080UL) +#define USBFS_DCTL_CGINAK_POS (8U) +#define USBFS_DCTL_CGINAK (0x00000100UL) +#define USBFS_DCTL_SGONAK_POS (9U) +#define USBFS_DCTL_SGONAK (0x00000200UL) +#define USBFS_DCTL_CGONAK_POS (10U) +#define USBFS_DCTL_CGONAK (0x00000400UL) +#define USBFS_DCTL_POPRGDNE_POS (11U) +#define USBFS_DCTL_POPRGDNE (0x00000800UL) + +/* Bit definition for USBFS_DSTS register */ +#define USBFS_DSTS_SUSPSTS_POS (0U) +#define USBFS_DSTS_SUSPSTS (0x00000001UL) +#define USBFS_DSTS_ENUMSPD_POS (1U) +#define USBFS_DSTS_ENUMSPD (0x00000006UL) +#define USBFS_DSTS_EERR_POS (3U) +#define USBFS_DSTS_EERR (0x00000008UL) +#define USBFS_DSTS_FNSOF_POS (8U) +#define USBFS_DSTS_FNSOF (0x003FFF00UL) + +/* Bit definition for USBFS_DIEPMSK register */ +#define USBFS_DIEPMSK_XFRCM_POS (0U) +#define USBFS_DIEPMSK_XFRCM (0x00000001UL) +#define USBFS_DIEPMSK_EPDM_POS (1U) +#define USBFS_DIEPMSK_EPDM (0x00000002UL) +#define USBFS_DIEPMSK_TOM_POS (3U) +#define USBFS_DIEPMSK_TOM (0x00000008UL) +#define USBFS_DIEPMSK_TTXFEMSK_POS (4U) +#define USBFS_DIEPMSK_TTXFEMSK (0x00000010UL) +#define USBFS_DIEPMSK_INEPNMM_POS (5U) +#define USBFS_DIEPMSK_INEPNMM (0x00000020UL) +#define USBFS_DIEPMSK_INEPNEM_POS (6U) +#define USBFS_DIEPMSK_INEPNEM (0x00000040UL) + +/* Bit definition for USBFS_DOEPMSK register */ +#define USBFS_DOEPMSK_XFRCM_POS (0U) +#define USBFS_DOEPMSK_XFRCM (0x00000001UL) +#define USBFS_DOEPMSK_EPDM_POS (1U) +#define USBFS_DOEPMSK_EPDM (0x00000002UL) +#define USBFS_DOEPMSK_STUPM_POS (3U) +#define USBFS_DOEPMSK_STUPM (0x00000008UL) +#define USBFS_DOEPMSK_OTEPDM_POS (4U) +#define USBFS_DOEPMSK_OTEPDM (0x00000010UL) + +/* Bit definition for USBFS_DAINT register */ +#define USBFS_DAINT_IEPINT_POS (0U) +#define USBFS_DAINT_IEPINT (0x0000003FUL) +#define USBFS_DAINT_OEPINT_POS (16U) +#define USBFS_DAINT_OEPINT (0x003F0000UL) + +/* Bit definition for USBFS_DAINTMSK register */ +#define USBFS_DAINTMSK_IEPINTM_POS (0U) +#define USBFS_DAINTMSK_IEPINTM (0x0000003FUL) +#define USBFS_DAINTMSK_OEPINTM_POS (16U) +#define USBFS_DAINTMSK_OEPINTM (0x003F0000UL) + +/* Bit definition for USBFS_DIEPEMPMSK register */ +#define USBFS_DIEPEMPMSK_INEPTXFEM (0x0000003FUL) + +/* Bit definition for USBFS_DIEPCTL0 register */ +#define USBFS_DIEPCTL0_MPSIZ_POS (0U) +#define USBFS_DIEPCTL0_MPSIZ (0x00000003UL) +#define USBFS_DIEPCTL0_USBAEP_POS (15U) +#define USBFS_DIEPCTL0_USBAEP (0x00008000UL) +#define USBFS_DIEPCTL0_NAKSTS_POS (17U) +#define USBFS_DIEPCTL0_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL0_EPTYP_POS (18U) +#define USBFS_DIEPCTL0_EPTYP (0x000C0000UL) +#define USBFS_DIEPCTL0_STALL_POS (21U) +#define USBFS_DIEPCTL0_STALL (0x00200000UL) +#define USBFS_DIEPCTL0_TXFNUM_POS (22U) +#define USBFS_DIEPCTL0_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL0_CNAK_POS (26U) +#define USBFS_DIEPCTL0_CNAK (0x04000000UL) +#define USBFS_DIEPCTL0_SNAK_POS (27U) +#define USBFS_DIEPCTL0_SNAK (0x08000000UL) +#define USBFS_DIEPCTL0_EPDIS_POS (30U) +#define USBFS_DIEPCTL0_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL0_EPENA_POS (31U) +#define USBFS_DIEPCTL0_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPINT register */ +#define USBFS_DIEPINT_XFRC_POS (0U) +#define USBFS_DIEPINT_XFRC (0x00000001UL) +#define USBFS_DIEPINT_EPDISD_POS (1U) +#define USBFS_DIEPINT_EPDISD (0x00000002UL) +#define USBFS_DIEPINT_TOC_POS (3U) +#define USBFS_DIEPINT_TOC (0x00000008UL) +#define USBFS_DIEPINT_TTXFE_POS (4U) +#define USBFS_DIEPINT_TTXFE (0x00000010UL) +#define USBFS_DIEPINT_INEPNE_POS (6U) +#define USBFS_DIEPINT_INEPNE (0x00000040UL) +#define USBFS_DIEPINT_TXFE_POS (7U) +#define USBFS_DIEPINT_TXFE (0x00000080UL) + +/* Bit definition for USBFS_DIEPTSIZ0 register */ +#define USBFS_DIEPTSIZ0_XFRSIZ_POS (0U) +#define USBFS_DIEPTSIZ0_XFRSIZ (0x0000007FUL) +#define USBFS_DIEPTSIZ0_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ0_PKTCNT (0x00180000UL) + +/* Bit definition for USBFS_DIEPDMA register */ +#define USBFS_DIEPDMA (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DTXFSTS register */ +#define USBFS_DTXFSTS_INEPTFSAV (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL register */ +#define USBFS_DIEPCTL_MPSIZ_POS (0U) +#define USBFS_DIEPCTL_MPSIZ (0x000007FFUL) +#define USBFS_DIEPCTL_USBAEP_POS (15U) +#define USBFS_DIEPCTL_USBAEP (0x00008000UL) +#define USBFS_DIEPCTL_EONUM_DPID_POS (16U) +#define USBFS_DIEPCTL_EONUM_DPID (0x00010000UL) +#define USBFS_DIEPCTL_NAKSTS_POS (17U) +#define USBFS_DIEPCTL_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL_EPTYP_POS (18U) +#define USBFS_DIEPCTL_EPTYP (0x000C0000UL) +#define USBFS_DIEPCTL_STALL_POS (21U) +#define USBFS_DIEPCTL_STALL (0x00200000UL) +#define USBFS_DIEPCTL_TXFNUM_POS (22U) +#define USBFS_DIEPCTL_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL_CNAK_POS (26U) +#define USBFS_DIEPCTL_CNAK (0x04000000UL) +#define USBFS_DIEPCTL_SNAK_POS (27U) +#define USBFS_DIEPCTL_SNAK (0x08000000UL) +#define USBFS_DIEPCTL_SD0PID_SEVNFRM_POS (28U) +#define USBFS_DIEPCTL_SD0PID_SEVNFRM (0x10000000UL) +#define USBFS_DIEPCTL_SODDFRM_POS (29U) +#define USBFS_DIEPCTL_SODDFRM (0x20000000UL) +#define USBFS_DIEPCTL_EPDIS_POS (30U) +#define USBFS_DIEPCTL_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL_EPENA_POS (31U) +#define USBFS_DIEPCTL_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPTSIZ register */ +#define USBFS_DIEPTSIZ_XFRSIZ_POS (0U) +#define USBFS_DIEPTSIZ_XFRSIZ (0x0007FFFFUL) +#define USBFS_DIEPTSIZ_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ_PKTCNT (0x1FF80000UL) + +/* Bit definition for USBFS_DOEPCTL0 register */ +#define USBFS_DOEPCTL0_MPSIZ_POS (0U) +#define USBFS_DOEPCTL0_MPSIZ (0x00000003UL) +#define USBFS_DOEPCTL0_USBAEP_POS (15U) +#define USBFS_DOEPCTL0_USBAEP (0x00008000UL) +#define USBFS_DOEPCTL0_NAKSTS_POS (17U) +#define USBFS_DOEPCTL0_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL0_EPTYP_POS (18U) +#define USBFS_DOEPCTL0_EPTYP (0x000C0000UL) +#define USBFS_DOEPCTL0_SNPM_POS (20U) +#define USBFS_DOEPCTL0_SNPM (0x00100000UL) +#define USBFS_DOEPCTL0_STALL_POS (21U) +#define USBFS_DOEPCTL0_STALL (0x00200000UL) +#define USBFS_DOEPCTL0_CNAK_POS (26U) +#define USBFS_DOEPCTL0_CNAK (0x04000000UL) +#define USBFS_DOEPCTL0_SNAK_POS (27U) +#define USBFS_DOEPCTL0_SNAK (0x08000000UL) +#define USBFS_DOEPCTL0_EPDIS_POS (30U) +#define USBFS_DOEPCTL0_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL0_EPENA_POS (31U) +#define USBFS_DOEPCTL0_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPINT register */ +#define USBFS_DOEPINT_XFRC_POS (0U) +#define USBFS_DOEPINT_XFRC (0x00000001UL) +#define USBFS_DOEPINT_EPDISD_POS (1U) +#define USBFS_DOEPINT_EPDISD (0x00000002UL) +#define USBFS_DOEPINT_STUP_POS (3U) +#define USBFS_DOEPINT_STUP (0x00000008UL) +#define USBFS_DOEPINT_OTEPDIS_POS (4U) +#define USBFS_DOEPINT_OTEPDIS (0x00000010UL) +#define USBFS_DOEPINT_B2BSTUP_POS (6U) +#define USBFS_DOEPINT_B2BSTUP (0x00000040UL) + +/* Bit definition for USBFS_DOEPTSIZ0 register */ +#define USBFS_DOEPTSIZ0_XFRSIZ_POS (0U) +#define USBFS_DOEPTSIZ0_XFRSIZ (0x0000007FUL) +#define USBFS_DOEPTSIZ0_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ0_PKTCNT (0x00080000UL) +#define USBFS_DOEPTSIZ0_STUPCNT_POS (29U) +#define USBFS_DOEPTSIZ0_STUPCNT (0x60000000UL) + +/* Bit definition for USBFS_DOEPDMA register */ +#define USBFS_DOEPDMA (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DOEPCTL register */ +#define USBFS_DOEPCTL_MPSIZ_POS (0U) +#define USBFS_DOEPCTL_MPSIZ (0x000007FFUL) +#define USBFS_DOEPCTL_USBAEP_POS (15U) +#define USBFS_DOEPCTL_USBAEP (0x00008000UL) +#define USBFS_DOEPCTL_DPID_POS (16U) +#define USBFS_DOEPCTL_DPID (0x00010000UL) +#define USBFS_DOEPCTL_NAKSTS_POS (17U) +#define USBFS_DOEPCTL_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL_EPTYP_POS (18U) +#define USBFS_DOEPCTL_EPTYP (0x000C0000UL) +#define USBFS_DOEPCTL_SNPM_POS (20U) +#define USBFS_DOEPCTL_SNPM (0x00100000UL) +#define USBFS_DOEPCTL_STALL_POS (21U) +#define USBFS_DOEPCTL_STALL (0x00200000UL) +#define USBFS_DOEPCTL_CNAK_POS (26U) +#define USBFS_DOEPCTL_CNAK (0x04000000UL) +#define USBFS_DOEPCTL_SNAK_POS (27U) +#define USBFS_DOEPCTL_SNAK (0x08000000UL) +#define USBFS_DOEPCTL_SD0PID_POS (28U) +#define USBFS_DOEPCTL_SD0PID (0x10000000UL) +#define USBFS_DOEPCTL_SD1PID_POS (29U) +#define USBFS_DOEPCTL_SD1PID (0x20000000UL) +#define USBFS_DOEPCTL_EPDIS_POS (30U) +#define USBFS_DOEPCTL_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL_EPENA_POS (31U) +#define USBFS_DOEPCTL_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPTSIZ register */ +#define USBFS_DOEPTSIZ_XFRSIZ_POS (0U) +#define USBFS_DOEPTSIZ_XFRSIZ (0x0007FFFFUL) +#define USBFS_DOEPTSIZ_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ_PKTCNT (0x1FF80000UL) + +/* Bit definition for USBFS_GCCTL register */ +#define USBFS_GCCTL_STPPCLK_POS (0U) +#define USBFS_GCCTL_STPPCLK (0x00000001UL) +#define USBFS_GCCTL_GATEHCLK_POS (1U) +#define USBFS_GCCTL_GATEHCLK (0x00000002UL) + +/******************************************************************************* + Bit definition for Peripheral WDT +*******************************************************************************/ +/* Bit definition for WDT_CR register */ +#define WDT_CR_PERI_POS (0U) +#define WDT_CR_PERI (0x00000003UL) +#define WDT_CR_PERI_0 (0x00000001UL) +#define WDT_CR_PERI_1 (0x00000002UL) +#define WDT_CR_CKS_POS (4U) +#define WDT_CR_CKS (0x000000F0UL) +#define WDT_CR_WDPT_POS (8U) +#define WDT_CR_WDPT (0x00000F00UL) +#define WDT_CR_SLPOFF_POS (16U) +#define WDT_CR_SLPOFF (0x00010000UL) +#define WDT_CR_ITS_POS (31U) +#define WDT_CR_ITS (0x80000000UL) + +/* Bit definition for WDT_SR register */ +#define WDT_SR_CNT_POS (0U) +#define WDT_SR_CNT (0x0000FFFFUL) +#define WDT_SR_UDF_POS (16U) +#define WDT_SR_UDF (0x00010000UL) +#define WDT_SR_REF_POS (17U) +#define WDT_SR_REF (0x00020000UL) + +/* Bit definition for WDT_RR register */ +#define WDT_RR_RF (0x0000FFFFUL) + +/******************************************************************************/ +/* Device Specific Registers bit_band structure */ +/******************************************************************************/ + +typedef struct { + __IO uint32_t STRT; + uint32_t RESERVED0[7]; +} stc_adc_str_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t CLREN; + __IO uint32_t DFMT; + uint32_t RESERVED1[8]; +} stc_adc_cr0_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t RSCHSEL; + uint32_t RESERVED1[13]; +} stc_adc_cr1_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t TRGENA; + uint32_t RESERVED1[7]; + __IO uint32_t TRGENB; +} stc_adc_trgsr_bit_t; + +typedef struct { + __IO uint32_t EOCAF; + __IO uint32_t EOCBF; + uint32_t RESERVED0[6]; +} stc_adc_isr_bit_t; + +typedef struct { + __IO uint32_t EOCAIEN; + __IO uint32_t EOCBIEN; + uint32_t RESERVED0[6]; +} stc_adc_icr_bit_t; + +typedef struct { + __IO uint32_t SYNCEN; + uint32_t RESERVED0[15]; +} stc_adc_synccr_bit_t; + +typedef struct { + __IO uint32_t AWDEN; + uint32_t RESERVED0[3]; + __IO uint32_t AWDMD; + uint32_t RESERVED1[3]; + __IO uint32_t AWDIEN; + uint32_t RESERVED2[7]; +} stc_adc_awdcr_bit_t; + +typedef struct { + __IO uint32_t PGAVSSEN; + uint32_t RESERVED0[15]; +} stc_adc_pgainsr1_bit_t; + +typedef struct { + __IO uint32_t START; + __IO uint32_t MODE; + uint32_t RESERVED0[30]; +} stc_aes_cr_bit_t; + +typedef struct { + __O uint32_t STRG; + uint32_t RESERVED0[31]; +} stc_aos_intsfttrg_bit_t; + +typedef struct { + __IO uint32_t NFEN1; + uint32_t RESERVED0[7]; + __IO uint32_t NFEN2; + uint32_t RESERVED1[7]; + __IO uint32_t NFEN3; + uint32_t RESERVED2[7]; + __IO uint32_t NFEN4; + uint32_t RESERVED3[7]; +} stc_aos_pevntnfcr_bit_t; + +typedef struct { + __IO uint32_t BUSOFF; + __I uint32_t TACTIVE; + __I uint32_t RACTIVE; + __IO uint32_t TSSS; + __IO uint32_t TPSS; + __IO uint32_t LBMI; + __IO uint32_t LBME; + __IO uint32_t RESET; +} stc_can_cfg_stat_bit_t; + +typedef struct { + __IO uint32_t TSA; + __IO uint32_t TSALL; + __IO uint32_t TSONE; + __IO uint32_t TPA; + __IO uint32_t TPE; + uint32_t RESERVED0[1]; + __IO uint32_t LOM; + __IO uint32_t TBSEL; +} stc_can_tcmd_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t TTTBM; + __IO uint32_t TSMODE; + __IO uint32_t TSNEXT; + uint32_t RESERVED1[1]; +} stc_can_tctrl_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t RBALL; + __IO uint32_t RREL; + __I uint32_t ROV; + __IO uint32_t ROM; + __IO uint32_t SACK; +} stc_can_rctrl_bit_t; + +typedef struct { + __I uint32_t TSFF; + __IO uint32_t EIE; + __IO uint32_t TSIE; + __IO uint32_t TPIE; + __IO uint32_t RAFIE; + __IO uint32_t RFIE; + __IO uint32_t ROIE; + __IO uint32_t RIE; +} stc_can_rtie_bit_t; + +typedef struct { + __IO uint32_t AIF; + __IO uint32_t EIF; + __IO uint32_t TSIF; + __IO uint32_t TPIF; + __IO uint32_t RAFIF; + __IO uint32_t RFIF; + __IO uint32_t ROIF; + __IO uint32_t RIF; +} stc_can_rtif_bit_t; + +typedef struct { + __IO uint32_t BEIF; + __IO uint32_t BEIE; + __IO uint32_t ALIF; + __IO uint32_t ALIE; + __IO uint32_t EPIF; + __IO uint32_t EPIE; + __I uint32_t EPASS; + __I uint32_t EWARN; +} stc_can_errint_bit_t; + +typedef struct { + uint32_t RESERVED0[5]; + __IO uint32_t SELMASK; + uint32_t RESERVED1[2]; +} stc_can_acfctrl_bit_t; + +typedef struct { + __IO uint32_t AE_1; + __IO uint32_t AE_2; + __IO uint32_t AE_3; + __IO uint32_t AE_4; + __IO uint32_t AE_5; + __IO uint32_t AE_6; + __IO uint32_t AE_7; + __IO uint32_t AE_8; +} stc_can_acfen_bit_t; + +typedef struct { + uint32_t RESERVED0[29]; + __IO uint32_t AIDE; + __IO uint32_t AIDEE; + uint32_t RESERVED1[1]; +} stc_can_acf_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t TBF; + __IO uint32_t TBE; +} stc_can_tbslot_bit_t; + +typedef struct { + __IO uint32_t TTEN; + uint32_t RESERVED0[2]; + __IO uint32_t TTIF; + __IO uint32_t TTIE; + __IO uint32_t TEIF; + __IO uint32_t WTIF; + __IO uint32_t WTIE; +} stc_can_ttcfg_bit_t; + +typedef struct { + uint32_t RESERVED0[31]; + __IO uint32_t REF_IDE; +} stc_can_ref_msg_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t IEN; + __IO uint32_t CVSEN; + uint32_t RESERVED1[3]; + __IO uint32_t OUTEN; + __IO uint32_t INV; + __IO uint32_t CMPOE; + __IO uint32_t CMPON; +} stc_cmp_ctrl_bit_t; + +typedef struct { + __IO uint32_t RVSL0; + __IO uint32_t RVSL1; + __IO uint32_t RVSL2; + __IO uint32_t RVSL3; + uint32_t RESERVED0[4]; + __IO uint32_t CVSL0; + __IO uint32_t CVSL1; + __IO uint32_t CVSL2; + __IO uint32_t CVSL3; + __IO uint32_t C4SL0; + __IO uint32_t C4SL1; + __IO uint32_t C4SL2; + uint32_t RESERVED1[1]; +} stc_cmp_vltsel_bit_t; + +typedef struct { + __I uint32_t OMON; + uint32_t RESERVED0[15]; +} stc_cmp_outmon_bit_t; + +typedef struct { + __IO uint32_t DA1EN; + __IO uint32_t DA2EN; + uint32_t RESERVED0[14]; +} stc_cmpcr_dacr_bit_t; + +typedef struct { + __IO uint32_t DA1SW; + __IO uint32_t DA2SW; + uint32_t RESERVED0[2]; + __IO uint32_t VREFSW; + uint32_t RESERVED1[11]; +} stc_cmpcr_rvadc_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t CR; + __IO uint32_t REFIN; + __IO uint32_t REFOUT; + __IO uint32_t XOROUT; + uint32_t RESERVED1[27]; +} stc_crc_cr_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __I uint32_t CRCFLAG_16; + uint32_t RESERVED1[15]; +} stc_crc_reslt_bit_t; + +typedef struct { + __I uint32_t CRCFLAG_32; + uint32_t RESERVED0[31]; +} stc_crc_flg_bit_t; + +typedef struct { + __IO uint32_t AUTHFG; + uint32_t RESERVED0[1]; + __IO uint32_t PRTLV1; + __IO uint32_t PRTLV2; + uint32_t RESERVED1[28]; +} stc_dbgc_mcustat_bit_t; + +typedef struct { + __IO uint32_t ERASEREQ; + __IO uint32_t ERASEACK; + __IO uint32_t ERASEERR; + uint32_t RESERVED0[29]; +} stc_dbgc_fersctl_bit_t; + +typedef struct { + __IO uint32_t CDBGPWRUPREQ; + __IO uint32_t CDBGPWRUPACK; + uint32_t RESERVED0[30]; +} stc_dbgc_mcudbgstat_bit_t; + +typedef struct { + __IO uint32_t SWDTSTP; + __IO uint32_t WDTSTP; + __IO uint32_t RTCSTP; + uint32_t RESERVED0[11]; + __IO uint32_t TMR01STP; + __IO uint32_t TMR02STP; + uint32_t RESERVED1[4]; + __IO uint32_t TMR41STP; + __IO uint32_t TMR42STP; + __IO uint32_t TMR43STP; + __IO uint32_t TM61STP; + __IO uint32_t TM62STP; + __IO uint32_t TMR63STP; + __IO uint32_t TMRA1STP; + __IO uint32_t TMRA2STP; + __IO uint32_t TMRA3STP; + __IO uint32_t TMRA4STP; + __IO uint32_t TMRA5STP; + __IO uint32_t TMRA6STP; +} stc_dbgc_mcustpctl_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t TRACEIOEN; + uint32_t RESERVED1[29]; +} stc_dbgc_mcutracectl_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t COMPTRG; + uint32_t RESERVED1[22]; + __IO uint32_t INTEN; +} stc_dcu_ctl_bit_t; + +typedef struct { + __I uint32_t FLAG_OP; + __I uint32_t FLAG_LS2; + __I uint32_t FLAG_EQ2; + __I uint32_t FLAG_GT2; + __I uint32_t FLAG_LS1; + __I uint32_t FLAG_EQ1; + __I uint32_t FLAG_GT1; + uint32_t RESERVED0[25]; +} stc_dcu_flag_bit_t; + +typedef struct { + __O uint32_t CLR_OP; + __O uint32_t CLR_LS2; + __O uint32_t CLR_EQ2; + __O uint32_t CLR_GT2; + __O uint32_t CLR_LS1; + __O uint32_t CLR_EQ1; + __O uint32_t CLR_GT1; + uint32_t RESERVED0[25]; +} stc_dcu_flagclr_bit_t; + +typedef struct { + __IO uint32_t SEL_OP; + __IO uint32_t SEL_LS2; + __IO uint32_t SEL_EQ2; + __IO uint32_t SEL_GT2; + __IO uint32_t SEL_LS1; + __IO uint32_t SEL_EQ1; + __IO uint32_t SEL_GT1; + uint32_t RESERVED0[25]; +} stc_dcu_intevtsel_bit_t; + +typedef struct { + __IO uint32_t EN; + uint32_t RESERVED0[31]; +} stc_dma_en_bit_t; + +typedef struct { + __I uint32_t TRNERR0; + __I uint32_t TRNERR1; + __I uint32_t TRNERR2; + __I uint32_t TRNERR3; + uint32_t RESERVED0[12]; + __I uint32_t REQERR0; + __I uint32_t REQERR1; + __I uint32_t REQERR2; + __I uint32_t REQERR3; + uint32_t RESERVED1[12]; +} stc_dma_intstat0_bit_t; + +typedef struct { + __I uint32_t TC0; + __I uint32_t TC1; + __I uint32_t TC2; + __I uint32_t TC3; + uint32_t RESERVED0[12]; + __I uint32_t BTC0; + __I uint32_t BTC1; + __I uint32_t BTC2; + __I uint32_t BTC3; + uint32_t RESERVED1[12]; +} stc_dma_intstat1_bit_t; + +typedef struct { + __IO uint32_t MSKTRNERR0; + __IO uint32_t MSKTRNERR1; + __IO uint32_t MSKTRNERR2; + __IO uint32_t MSKTRNERR3; + uint32_t RESERVED0[12]; + __IO uint32_t MSKREQERR0; + __IO uint32_t MSKREQERR1; + __IO uint32_t MSKREQERR2; + __IO uint32_t MSKREQERR3; + uint32_t RESERVED1[12]; +} stc_dma_intmask0_bit_t; + +typedef struct { + __IO uint32_t MSKTC0; + __IO uint32_t MSKTC1; + __IO uint32_t MSKTC2; + __IO uint32_t MSKTC3; + uint32_t RESERVED0[12]; + __IO uint32_t MSKBTC0; + __IO uint32_t MSKBTC1; + __IO uint32_t MSKBTC2; + __IO uint32_t MSKBTC3; + uint32_t RESERVED1[12]; +} stc_dma_intmask1_bit_t; + +typedef struct { + __O uint32_t CLRTRNERR0; + __O uint32_t CLRTRNERR1; + __O uint32_t CLRTRNERR2; + __O uint32_t CLRTRNERR3; + uint32_t RESERVED0[12]; + __O uint32_t CLRREQERR0; + __O uint32_t CLRREQERR1; + __O uint32_t CLRREQERR2; + __O uint32_t CLRREQERR3; + uint32_t RESERVED1[12]; +} stc_dma_intclr0_bit_t; + +typedef struct { + __O uint32_t CLRTC0; + __O uint32_t CLRTC1; + __O uint32_t CLRTC2; + __O uint32_t CLRTC3; + uint32_t RESERVED0[12]; + __O uint32_t CLRBTC0; + __O uint32_t CLRBTC1; + __O uint32_t CLRBTC2; + __O uint32_t CLRBTC3; + uint32_t RESERVED1[12]; +} stc_dma_intclr1_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __I uint32_t RCFGREQ; + uint32_t RESERVED1[16]; +} stc_dma_reqstat_bit_t; + +typedef struct { + __I uint32_t DMAACT; + __I uint32_t RCFGACT; + uint32_t RESERVED0[30]; +} stc_dma_chstat_bit_t; + +typedef struct { + __IO uint32_t RCFGEN; + __IO uint32_t RCFGLLP; + uint32_t RESERVED0[30]; +} stc_dma_rcfgctl_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t SRPTEN; + __IO uint32_t DRPTEN; + __IO uint32_t SNSEQEN; + __IO uint32_t DNSEQEN; + uint32_t RESERVED1[2]; + __IO uint32_t LLPEN; + __IO uint32_t LLPRUN; + __IO uint32_t IE; + uint32_t RESERVED2[19]; +} stc_dma_chctl_bit_t; + +typedef struct { + __IO uint32_t FSTP; + uint32_t RESERVED0[31]; +} stc_efm_fstp_bit_t; + +typedef struct { + __IO uint32_t SLPMD; + uint32_t RESERVED0[7]; + __IO uint32_t LVM; + uint32_t RESERVED1[7]; + __IO uint32_t CACHE; + uint32_t RESERVED2[7]; + __IO uint32_t CRST; + uint32_t RESERVED3[7]; +} stc_efm_frmc_bit_t; + +typedef struct { + __IO uint32_t PEMODE; + uint32_t RESERVED0[7]; + __IO uint32_t BUSHLDCTL; + uint32_t RESERVED1[23]; +} stc_efm_fwmc_bit_t; + +typedef struct { + __I uint32_t PEWERR; + __I uint32_t PEPRTERR; + __I uint32_t PGSZERR; + __I uint32_t PGMISMTCH; + __I uint32_t OPTEND; + __I uint32_t COLERR; + uint32_t RESERVED0[2]; + __I uint32_t RDY; + uint32_t RESERVED1[23]; +} stc_efm_fsr_bit_t; + +typedef struct { + __IO uint32_t PEWERRCLR; + __IO uint32_t PEPRTERRCLR; + __IO uint32_t PGSZERRCLR; + __IO uint32_t PGMISMTCHCLR; + __IO uint32_t OPTENDCLR; + __IO uint32_t COLERRCLR; + uint32_t RESERVED0[26]; +} stc_efm_fsclr_bit_t; + +typedef struct { + __IO uint32_t PEERRITE; + __IO uint32_t OPTENDITE; + __IO uint32_t COLERRITE; + uint32_t RESERVED0[29]; +} stc_efm_fite_bit_t; + +typedef struct { + __I uint32_t FSWP; + uint32_t RESERVED0[31]; +} stc_efm_fswp_bit_t; + +typedef struct { + uint32_t RESERVED0[31]; + __IO uint32_t EN; +} stc_efm_mmf_remcr_bit_t; + +typedef struct { + __IO uint32_t PORTINEN; + __IO uint32_t CMPEN1; + __IO uint32_t CMPEN2; + __IO uint32_t CMPEN3; + uint32_t RESERVED0[1]; + __IO uint32_t OSCSTPEN; + __IO uint32_t PWMSEN0; + __IO uint32_t PWMSEN1; + __IO uint32_t PWMSEN2; + uint32_t RESERVED1[21]; + __IO uint32_t NFEN; + __IO uint32_t INVSEL; +} stc_emb_ctl_bit_t; + +typedef struct { + __IO uint32_t PWMLV0; + __IO uint32_t PWMLV1; + __IO uint32_t PWMLV2; + uint32_t RESERVED0[29]; +} stc_emb_pwmlv_bit_t; + +typedef struct { + __IO uint32_t SOE; + uint32_t RESERVED0[31]; +} stc_emb_soe_bit_t; + +typedef struct { + __I uint32_t PORTINF; + __I uint32_t PWMSF; + __I uint32_t CMPF; + __I uint32_t OSF; + __I uint32_t PORTINST; + __I uint32_t PWMST; + uint32_t RESERVED0[26]; +} stc_emb_stat_bit_t; + +typedef struct { + __O uint32_t PORTINFCLR; + __O uint32_t PWMSFCLR; + __O uint32_t CMPFCLR; + __O uint32_t OSFCLR; + uint32_t RESERVED0[28]; +} stc_emb_statclr_bit_t; + +typedef struct { + __IO uint32_t PORTININTEN; + __IO uint32_t PWMSINTEN; + __IO uint32_t CMPINTEN; + __IO uint32_t OSINTEN; + uint32_t RESERVED0[28]; +} stc_emb_inten_bit_t; + +typedef struct { + __IO uint32_t START; + uint32_t RESERVED0[31]; +} stc_fcm_str_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t INEXS; + uint32_t RESERVED1[7]; + __IO uint32_t EXREFE; + uint32_t RESERVED2[16]; +} stc_fcm_rccr_bit_t; + +typedef struct { + __IO uint32_t ERRIE; + __IO uint32_t MENDIE; + __IO uint32_t OVFIE; + uint32_t RESERVED0[1]; + __IO uint32_t ERRINTRS; + uint32_t RESERVED1[2]; + __IO uint32_t ERRE; + uint32_t RESERVED2[24]; +} stc_fcm_rier_bit_t; + +typedef struct { + __I uint32_t ERRF; + __I uint32_t MENDF; + __I uint32_t OVF; + uint32_t RESERVED0[29]; +} stc_fcm_sr_bit_t; + +typedef struct { + __O uint32_t ERRFCLR; + __O uint32_t MENDFCLR; + __O uint32_t OVFCLR; + uint32_t RESERVED0[29]; +} stc_fcm_clr_bit_t; + +typedef struct { + __I uint32_t PIN00; + __I uint32_t PIN01; + __I uint32_t PIN02; + __I uint32_t PIN03; + __I uint32_t PIN04; + __I uint32_t PIN05; + __I uint32_t PIN06; + __I uint32_t PIN07; + __I uint32_t PIN08; + __I uint32_t PIN09; + __I uint32_t PIN10; + __I uint32_t PIN11; + __I uint32_t PIN12; + __I uint32_t PIN13; + __I uint32_t PIN14; + __I uint32_t PIN15; +} stc_gpio_pidr_bit_t; + +typedef struct { + __IO uint32_t POUT00; + __IO uint32_t POUT01; + __IO uint32_t POUT02; + __IO uint32_t POUT03; + __IO uint32_t POUT04; + __IO uint32_t POUT05; + __IO uint32_t POUT06; + __IO uint32_t POUT07; + __IO uint32_t POUT08; + __IO uint32_t POUT09; + __IO uint32_t POUT10; + __IO uint32_t POUT11; + __IO uint32_t POUT12; + __IO uint32_t POUT13; + __IO uint32_t POUT14; + __IO uint32_t POUT15; +} stc_gpio_podr_bit_t; + +typedef struct { + __IO uint32_t POUTE00; + __IO uint32_t POUTE01; + __IO uint32_t POUTE02; + __IO uint32_t POUTE03; + __IO uint32_t POUTE04; + __IO uint32_t POUTE05; + __IO uint32_t POUTE06; + __IO uint32_t POUTE07; + __IO uint32_t POUTE08; + __IO uint32_t POUTE09; + __IO uint32_t POUTE10; + __IO uint32_t POUTE11; + __IO uint32_t POUTE12; + __IO uint32_t POUTE13; + __IO uint32_t POUTE14; + __IO uint32_t POUTE15; +} stc_gpio_poer_bit_t; + +typedef struct { + __IO uint32_t POS00; + __IO uint32_t POS01; + __IO uint32_t POS02; + __IO uint32_t POS03; + __IO uint32_t POS04; + __IO uint32_t POS05; + __IO uint32_t POS06; + __IO uint32_t POS07; + __IO uint32_t POS08; + __IO uint32_t POS09; + __IO uint32_t POS10; + __IO uint32_t POS11; + __IO uint32_t POS12; + __IO uint32_t POS13; + __IO uint32_t POS14; + __IO uint32_t POS15; +} stc_gpio_posr_bit_t; + +typedef struct { + __IO uint32_t POR00; + __IO uint32_t POR01; + __IO uint32_t POR02; + __IO uint32_t POR03; + __IO uint32_t POR04; + __IO uint32_t POR05; + __IO uint32_t POR06; + __IO uint32_t POR07; + __IO uint32_t POR08; + __IO uint32_t POR09; + __IO uint32_t POR10; + __IO uint32_t POR11; + __IO uint32_t POR12; + __IO uint32_t POR13; + __IO uint32_t POR14; + __IO uint32_t POR15; +} stc_gpio_porr_bit_t; + +typedef struct { + __IO uint32_t POT00; + __IO uint32_t POT01; + __IO uint32_t POT02; + __IO uint32_t POT03; + __IO uint32_t POT04; + __IO uint32_t POT05; + __IO uint32_t POT06; + __IO uint32_t POT07; + __IO uint32_t POT08; + __IO uint32_t POT09; + __IO uint32_t POT10; + __IO uint32_t POT11; + __IO uint32_t POT12; + __IO uint32_t POT13; + __IO uint32_t POT14; + __IO uint32_t POT15; +} stc_gpio_potr_bit_t; + +typedef struct { + __I uint32_t PIN00; + __I uint32_t PIN01; + __I uint32_t PIN02; + uint32_t RESERVED0[13]; +} stc_gpio_pidrh_bit_t; + +typedef struct { + __IO uint32_t POUT00; + __IO uint32_t POUT01; + __IO uint32_t POUT02; + uint32_t RESERVED0[13]; +} stc_gpio_podrh_bit_t; + +typedef struct { + __IO uint32_t POUTE00; + __IO uint32_t POUTE01; + __IO uint32_t POUTE02; + uint32_t RESERVED0[13]; +} stc_gpio_poerh_bit_t; + +typedef struct { + __IO uint32_t POS00; + __IO uint32_t POS01; + __IO uint32_t POS02; + uint32_t RESERVED0[13]; +} stc_gpio_posrh_bit_t; + +typedef struct { + __IO uint32_t POR00; + __IO uint32_t POR01; + __IO uint32_t POR02; + uint32_t RESERVED0[13]; +} stc_gpio_porrh_bit_t; + +typedef struct { + __IO uint32_t POT00; + __IO uint32_t POT01; + __IO uint32_t POT02; + uint32_t RESERVED0[13]; +} stc_gpio_potrh_bit_t; + +typedef struct { + __IO uint32_t WE; + uint32_t RESERVED0[15]; +} stc_gpio_pwpr_bit_t; + +typedef struct { + __IO uint32_t POUT; + __IO uint32_t POUTE; + __IO uint32_t NOD; + uint32_t RESERVED0[3]; + __IO uint32_t PUU; + uint32_t RESERVED1[1]; + __I uint32_t PIN; + __IO uint32_t INVE; + uint32_t RESERVED2[2]; + __IO uint32_t INTE; + uint32_t RESERVED3[1]; + __IO uint32_t LTE; + __IO uint32_t DDIS; +} stc_gpio_pcr_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t BFE; + uint32_t RESERVED1[7]; +} stc_gpio_pfsr_bit_t; + +typedef struct { + __IO uint32_t START; + __IO uint32_t FST_GRP; + uint32_t RESERVED0[30]; +} stc_hash_cr_bit_t; + +typedef struct { + __IO uint32_t PE; + __IO uint32_t SMBUS; + __IO uint32_t SMBALRTEN; + __IO uint32_t SMBDEFAULTEN; + __IO uint32_t SMBHOSTEN; + uint32_t RESERVED0[1]; + __IO uint32_t ENGC; + __IO uint32_t RESTART; + __IO uint32_t START; + __IO uint32_t STOP; + __IO uint32_t ACK; + uint32_t RESERVED1[4]; + __IO uint32_t SWRST; + uint32_t RESERVED2[16]; +} stc_i2c_cr1_bit_t; + +typedef struct { + __IO uint32_t STARTIE; + __IO uint32_t SLADDR0IE; + __IO uint32_t SLADDR1IE; + __IO uint32_t TENDIE; + __IO uint32_t STOPIE; + uint32_t RESERVED0[1]; + __IO uint32_t RFULLIE; + __IO uint32_t TEMPTYIE; + uint32_t RESERVED1[1]; + __IO uint32_t ARLOIE; + uint32_t RESERVED2[2]; + __IO uint32_t NACKIE; + uint32_t RESERVED3[1]; + __IO uint32_t TMOUTIE; + uint32_t RESERVED4[5]; + __IO uint32_t GENCALLIE; + __IO uint32_t SMBDEFAULTIE; + __IO uint32_t SMBHOSTIE; + __IO uint32_t SMBALRTIE; + uint32_t RESERVED5[8]; +} stc_i2c_cr2_bit_t; + +typedef struct { + __IO uint32_t TMOUTEN; + __IO uint32_t LTMOUT; + __IO uint32_t HTMOUT; + uint32_t RESERVED0[4]; + __IO uint32_t FACKEN; + uint32_t RESERVED1[24]; +} stc_i2c_cr3_bit_t; + +typedef struct { + uint32_t RESERVED0[10]; + __IO uint32_t BUSWAIT; + uint32_t RESERVED1[21]; +} stc_i2c_cr4_bit_t; + +typedef struct { + uint32_t RESERVED0[12]; + __IO uint32_t SLADDR0EN; + uint32_t RESERVED1[2]; + __IO uint32_t ADDRMOD0; + uint32_t RESERVED2[16]; +} stc_i2c_slr0_bit_t; + +typedef struct { + uint32_t RESERVED0[12]; + __IO uint32_t SLADDR1EN; + uint32_t RESERVED1[2]; + __IO uint32_t ADDRMOD1; + uint32_t RESERVED2[16]; +} stc_i2c_slr1_bit_t; + +typedef struct { + __IO uint32_t STARTF; + __IO uint32_t SLADDR0F; + __IO uint32_t SLADDR1F; + __IO uint32_t TENDF; + __IO uint32_t STOPF; + uint32_t RESERVED0[1]; + __IO uint32_t RFULLF; + __IO uint32_t TEMPTYF; + uint32_t RESERVED1[1]; + __IO uint32_t ARLOF; + __IO uint32_t ACKRF; + uint32_t RESERVED2[1]; + __IO uint32_t NACKF; + uint32_t RESERVED3[1]; + __IO uint32_t TMOUTF; + uint32_t RESERVED4[1]; + __IO uint32_t MSL; + __IO uint32_t BUSY; + __IO uint32_t TRA; + uint32_t RESERVED5[1]; + __IO uint32_t GENCALLF; + __IO uint32_t SMBDEFAULTF; + __IO uint32_t SMBHOSTF; + __IO uint32_t SMBALRTF; + uint32_t RESERVED6[8]; +} stc_i2c_sr_bit_t; + +typedef struct { + __O uint32_t STARTFCLR; + __O uint32_t SLADDR0FCLR; + __O uint32_t SLADDR1FCLR; + __O uint32_t TENDFCLR; + __O uint32_t STOPFCLR; + uint32_t RESERVED0[1]; + __O uint32_t RFULLFCLR; + __O uint32_t TEMPTYFCLR; + uint32_t RESERVED1[1]; + __O uint32_t ARLOFCLR; + uint32_t RESERVED2[2]; + __O uint32_t NACKFCLR; + uint32_t RESERVED3[1]; + __O uint32_t TMOUTFCLR; + uint32_t RESERVED4[5]; + __O uint32_t GENCALLFCLR; + __O uint32_t SMBDEFAULTFCLR; + __O uint32_t SMBHOSTFCLR; + __O uint32_t SMBALRTFCLR; + uint32_t RESERVED5[8]; +} stc_i2c_clr_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t DNFEN; + __IO uint32_t ANFEN; + uint32_t RESERVED1[26]; +} stc_i2c_fltr_bit_t; + +typedef struct { + __IO uint32_t TXE; + __IO uint32_t TXIE; + __IO uint32_t RXE; + __IO uint32_t RXIE; + __IO uint32_t EIE; + __IO uint32_t WMS; + __IO uint32_t ODD; + __IO uint32_t MCKOE; + uint32_t RESERVED0[8]; + __IO uint32_t FIFOR; + __IO uint32_t CODECRC; + __IO uint32_t I2SPLLSEL; + __IO uint32_t SDOE; + __IO uint32_t LRCKOE; + __IO uint32_t CKOE; + __IO uint32_t DUPLEX; + __IO uint32_t CLKSEL; + uint32_t RESERVED1[8]; +} stc_i2s_ctrl_bit_t; + +typedef struct { + __I uint32_t TXBA; + __I uint32_t RXBA; + __I uint32_t TXBE; + __I uint32_t TXBF; + __I uint32_t RXBE; + __I uint32_t RXBF; + uint32_t RESERVED0[26]; +} stc_i2s_sr_bit_t; + +typedef struct { + __IO uint32_t TXERR; + __IO uint32_t RXERR; + uint32_t RESERVED0[30]; +} stc_i2s_er_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t CHLEN; + __IO uint32_t PCMSYNC; + uint32_t RESERVED1[26]; +} stc_i2s_cfgr_bit_t; + +typedef struct { + __I uint32_t SWDTAUTS; + __I uint32_t SWDTITS; + uint32_t RESERVED0[10]; + __I uint32_t SWDTSLPOFF; + uint32_t RESERVED1[3]; + __I uint32_t WDTAUTS; + __I uint32_t WDTITS; + uint32_t RESERVED2[10]; + __I uint32_t WDTSLPOFF; + uint32_t RESERVED3[3]; +} stc_icg_icg0_bit_t; + +typedef struct { + __I uint32_t HRCFREQSEL; + uint32_t RESERVED0[7]; + __I uint32_t HRCSTOP; + uint32_t RESERVED1[9]; + __I uint32_t BORDIS; + uint32_t RESERVED2[9]; + __I uint32_t NMITRG; + __I uint32_t NMIEN; + __I uint32_t NFEN; + __I uint32_t NMIICGEN; +} stc_icg_icg1_bit_t; + +typedef struct { + __IO uint32_t NMITRG; + uint32_t RESERVED0[6]; + __IO uint32_t NFEN; + uint32_t RESERVED1[24]; +} stc_intc_nmicr_bit_t; + +typedef struct { + __IO uint32_t NMIENR; + __IO uint32_t SWDTENR; + __IO uint32_t PVD1ENR; + __IO uint32_t PVD2ENR; + uint32_t RESERVED0[1]; + __IO uint32_t XTALSTPENR; + uint32_t RESERVED1[2]; + __IO uint32_t REPENR; + __IO uint32_t RECCENR; + __IO uint32_t BUSMENR; + __IO uint32_t WDTENR; + uint32_t RESERVED2[20]; +} stc_intc_nmienr_bit_t; + +typedef struct { + __IO uint32_t NMIFR; + __IO uint32_t SWDTFR; + __IO uint32_t PVD1FR; + __IO uint32_t PVD2FR; + uint32_t RESERVED0[1]; + __IO uint32_t XTALSTPFR; + uint32_t RESERVED1[2]; + __IO uint32_t REPFR; + __IO uint32_t RECCFR; + __IO uint32_t BUSMFR; + __IO uint32_t WDTFR; + uint32_t RESERVED2[20]; +} stc_intc_nmifr_bit_t; + +typedef struct { + __IO uint32_t NMICFR; + __IO uint32_t SWDTCFR; + __IO uint32_t PVD1CFR; + __IO uint32_t PVD2CFR; + uint32_t RESERVED0[1]; + __IO uint32_t XTALSTPCFR; + uint32_t RESERVED1[2]; + __IO uint32_t REPCFR; + __IO uint32_t RECCCFR; + __IO uint32_t BUSMCFR; + __IO uint32_t WDTCFR; + uint32_t RESERVED2[20]; +} stc_intc_nmicfr_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t EFEN; + uint32_t RESERVED1[24]; +} stc_intc_eirqcr_bit_t; + +typedef struct { + __IO uint32_t EIRQWUEN0; + __IO uint32_t EIRQWUEN1; + __IO uint32_t EIRQWUEN2; + __IO uint32_t EIRQWUEN3; + __IO uint32_t EIRQWUEN4; + __IO uint32_t EIRQWUEN5; + __IO uint32_t EIRQWUEN6; + __IO uint32_t EIRQWUEN7; + __IO uint32_t EIRQWUEN8; + __IO uint32_t EIRQWUEN9; + __IO uint32_t EIRQWUEN10; + __IO uint32_t EIRQWUEN11; + __IO uint32_t EIRQWUEN12; + __IO uint32_t EIRQWUEN13; + __IO uint32_t EIRQWUEN14; + __IO uint32_t EIRQWUEN15; + __IO uint32_t SWDTWUEN; + __IO uint32_t PVD1WUEN; + __IO uint32_t PVD2WUEN; + __IO uint32_t CMPI0WUEN; + __IO uint32_t WKTMWUEN; + __IO uint32_t RTCALMWUEN; + __IO uint32_t RTCPRDWUEN; + __IO uint32_t TMR0WUEN; + uint32_t RESERVED0[1]; + __IO uint32_t RXWUEN; + uint32_t RESERVED1[6]; +} stc_intc_wupen_bit_t; + +typedef struct { + __IO uint32_t EIFR0; + __IO uint32_t EIFR1; + __IO uint32_t EIFR2; + __IO uint32_t EIFR3; + __IO uint32_t EIFR4; + __IO uint32_t EIFR5; + __IO uint32_t EIFR6; + __IO uint32_t EIFR7; + __IO uint32_t EIFR8; + __IO uint32_t EIFR9; + __IO uint32_t EIFR10; + __IO uint32_t EIFR11; + __IO uint32_t EIFR12; + __IO uint32_t EIFR13; + __IO uint32_t EIFR14; + __IO uint32_t EIFR15; + uint32_t RESERVED0[16]; +} stc_intc_eifr_bit_t; + +typedef struct { + __IO uint32_t EIFCR0; + __IO uint32_t EIFCR1; + __IO uint32_t EIFCR2; + __IO uint32_t EIFCR3; + __IO uint32_t EIFCR4; + __IO uint32_t EIFCR5; + __IO uint32_t EIFCR6; + __IO uint32_t EIFCR7; + __IO uint32_t EIFCR8; + __IO uint32_t EIFCR9; + __IO uint32_t EIFCR10; + __IO uint32_t EIFCR11; + __IO uint32_t EIFCR12; + __IO uint32_t EIFCR13; + __IO uint32_t EIFCR14; + __IO uint32_t EIFCR15; + uint32_t RESERVED0[16]; +} stc_intc_eifcr_bit_t; + +typedef struct { + __IO uint32_t VSEL0; + __IO uint32_t VSEL1; + __IO uint32_t VSEL2; + __IO uint32_t VSEL3; + __IO uint32_t VSEL4; + __IO uint32_t VSEL5; + __IO uint32_t VSEL6; + __IO uint32_t VSEL7; + __IO uint32_t VSEL8; + __IO uint32_t VSEL9; + __IO uint32_t VSEL10; + __IO uint32_t VSEL11; + __IO uint32_t VSEL12; + __IO uint32_t VSEL13; + __IO uint32_t VSEL14; + __IO uint32_t VSEL15; + __IO uint32_t VSEL16; + __IO uint32_t VSEL17; + __IO uint32_t VSEL18; + __IO uint32_t VSEL19; + __IO uint32_t VSEL20; + __IO uint32_t VSEL21; + __IO uint32_t VSEL22; + __IO uint32_t VSEL23; + __IO uint32_t VSEL24; + __IO uint32_t VSEL25; + __IO uint32_t VSEL26; + __IO uint32_t VSEL27; + __IO uint32_t VSEL28; + __IO uint32_t VSEL29; + __IO uint32_t VSEL30; + __IO uint32_t VSEL31; +} stc_intc_vssel_bit_t; + +typedef struct { + __IO uint32_t SWIE0; + __IO uint32_t SWIE1; + __IO uint32_t SWIE2; + __IO uint32_t SWIE3; + __IO uint32_t SWIE4; + __IO uint32_t SWIE5; + __IO uint32_t SWIE6; + __IO uint32_t SWIE7; + __IO uint32_t SWIE8; + __IO uint32_t SWIE9; + __IO uint32_t SWIE10; + __IO uint32_t SWIE11; + __IO uint32_t SWIE12; + __IO uint32_t SWIE13; + __IO uint32_t SWIE14; + __IO uint32_t SWIE15; + __IO uint32_t SWIE16; + __IO uint32_t SWIE17; + __IO uint32_t SWIE18; + __IO uint32_t SWIE19; + __IO uint32_t SWIE20; + __IO uint32_t SWIE21; + __IO uint32_t SWIE22; + __IO uint32_t SWIE23; + __IO uint32_t SWIE24; + __IO uint32_t SWIE25; + __IO uint32_t SWIE26; + __IO uint32_t SWIE27; + __IO uint32_t SWIE28; + __IO uint32_t SWIE29; + __IO uint32_t SWIE30; + __IO uint32_t SWIE31; +} stc_intc_swier_bit_t; + +typedef struct { + __IO uint32_t EVTE0; + __IO uint32_t EVTE1; + __IO uint32_t EVTE2; + __IO uint32_t EVTE3; + __IO uint32_t EVTE4; + __IO uint32_t EVTE5; + __IO uint32_t EVTE6; + __IO uint32_t EVTE7; + __IO uint32_t EVTE8; + __IO uint32_t EVTE9; + __IO uint32_t EVTE10; + __IO uint32_t EVTE11; + __IO uint32_t EVTE12; + __IO uint32_t EVTE13; + __IO uint32_t EVTE14; + __IO uint32_t EVTE15; + __IO uint32_t EVTE16; + __IO uint32_t EVTE17; + __IO uint32_t EVTE18; + __IO uint32_t EVTE19; + __IO uint32_t EVTE20; + __IO uint32_t EVTE21; + __IO uint32_t EVTE22; + __IO uint32_t EVTE23; + __IO uint32_t EVTE24; + __IO uint32_t EVTE25; + __IO uint32_t EVTE26; + __IO uint32_t EVTE27; + __IO uint32_t EVTE28; + __IO uint32_t EVTE29; + __IO uint32_t EVTE30; + __IO uint32_t EVTE31; +} stc_intc_evter_bit_t; + +typedef struct { + __IO uint32_t IER0; + __IO uint32_t IER1; + __IO uint32_t IER2; + __IO uint32_t IER3; + __IO uint32_t IER4; + __IO uint32_t IER5; + __IO uint32_t IER6; + __IO uint32_t IER7; + __IO uint32_t IER8; + __IO uint32_t IER9; + __IO uint32_t IER10; + __IO uint32_t IER11; + __IO uint32_t IER12; + __IO uint32_t IER13; + __IO uint32_t IER14; + __IO uint32_t IER15; + __IO uint32_t IER16; + __IO uint32_t IER17; + __IO uint32_t IER18; + __IO uint32_t IER19; + __IO uint32_t IER20; + __IO uint32_t IER21; + __IO uint32_t IER22; + __IO uint32_t IER23; + __IO uint32_t IER24; + __IO uint32_t IER25; + __IO uint32_t IER26; + __IO uint32_t IER27; + __IO uint32_t IER28; + __IO uint32_t IER29; + __IO uint32_t IER30; + __IO uint32_t IER31; +} stc_intc_ier_bit_t; + +typedef struct { + __IO uint32_t SEN; + uint32_t RESERVED0[31]; +} stc_keyscan_ser_bit_t; + +typedef struct { + __IO uint32_t S2RGRP; + __IO uint32_t S2RGWP; + uint32_t RESERVED0[5]; + __IO uint32_t S2RGE; + __IO uint32_t S1RGRP; + __IO uint32_t S1RGWP; + uint32_t RESERVED1[5]; + __IO uint32_t S1RGE; + __IO uint32_t FRGRP; + __IO uint32_t FRGWP; + uint32_t RESERVED2[5]; + __IO uint32_t FRGE; + uint32_t RESERVED3[8]; +} stc_mpu_rgcr_bit_t; + +typedef struct { + __IO uint32_t SMPU2BRP; + __IO uint32_t SMPU2BWP; + uint32_t RESERVED0[5]; + __IO uint32_t SMPU2E; + __IO uint32_t SMPU1BRP; + __IO uint32_t SMPU1BWP; + uint32_t RESERVED1[5]; + __IO uint32_t SMPU1E; + __IO uint32_t FMPUBRP; + __IO uint32_t FMPUBWP; + uint32_t RESERVED2[5]; + __IO uint32_t FMPUE; + uint32_t RESERVED3[8]; +} stc_mpu_cr_bit_t; + +typedef struct { + __I uint32_t SMPU2EAF; + uint32_t RESERVED0[7]; + __I uint32_t SMPU1EAF; + uint32_t RESERVED1[7]; + __I uint32_t FMPUEAF; + uint32_t RESERVED2[15]; +} stc_mpu_sr_bit_t; + +typedef struct { + __O uint32_t SMPU2ECLR; + uint32_t RESERVED0[7]; + __O uint32_t SMPU1ECLR; + uint32_t RESERVED1[7]; + __O uint32_t FMPUECLR; + uint32_t RESERVED2[15]; +} stc_mpu_eclr_bit_t; + +typedef struct { + __IO uint32_t MPUWE; + uint32_t RESERVED0[31]; +} stc_mpu_wp_bit_t; + +typedef struct { + __IO uint32_t AESRDP; + __IO uint32_t AESWRP; + __IO uint32_t HASHRDP; + __IO uint32_t HASHWRP; + __IO uint32_t TRNGRDP; + __IO uint32_t TRNGWRP; + __IO uint32_t CRCRDP; + __IO uint32_t CRCWRP; + __IO uint32_t EFMRDP; + __IO uint32_t EFMWRP; + uint32_t RESERVED0[2]; + __IO uint32_t WDTRDP; + __IO uint32_t WDTWRP; + __IO uint32_t SWDTRDP; + __IO uint32_t SWDTWRP; + __IO uint32_t BKSRAMRDP; + __IO uint32_t BKSRAMWRP; + __IO uint32_t RTCRDP; + __IO uint32_t RTCWRP; + __IO uint32_t DMPURDP; + __IO uint32_t DMPUWRP; + __IO uint32_t SRAMCRDP; + __IO uint32_t SRAMCWRP; + __IO uint32_t INTCRDP; + __IO uint32_t INTCWRP; + __IO uint32_t SYSCRDP; + __IO uint32_t SYSCWRP; + __IO uint32_t MSTPRDP; + __IO uint32_t MSTPWRP; + uint32_t RESERVED1[1]; + __IO uint32_t BUSERRE; +} stc_mpu_ippr_bit_t; + +typedef struct { + __IO uint32_t OTSST; + __IO uint32_t OTSCK; + __IO uint32_t OTSIE; + __IO uint32_t TSSTP; + uint32_t RESERVED0[12]; +} stc_ots_ctl_bit_t; + +typedef struct { + __IO uint32_t DFB; + __IO uint32_t SOFEN; + uint32_t RESERVED0[30]; +} stc_peric_usbfs_syctlreg_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t SELMMC1; + uint32_t RESERVED1[1]; + __IO uint32_t SELMMC2; + uint32_t RESERVED2[28]; +} stc_peric_sdioc_syctlreg_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t PFE; + __IO uint32_t PFSAE; + __IO uint32_t DCOME; + __IO uint32_t XIPE; + __IO uint32_t SPIMD3; + uint32_t RESERVED1[24]; +} stc_qspi_cr_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t FOUR_BIC; + uint32_t RESERVED1[1]; + __IO uint32_t SSNHD; + __IO uint32_t SSNLD; + __IO uint32_t WPOL; + uint32_t RESERVED2[8]; + __IO uint32_t DUTY; + uint32_t RESERVED3[16]; +} stc_qspi_fcr_bit_t; + +typedef struct { + __IO uint32_t BUSY; + uint32_t RESERVED0[5]; + __IO uint32_t XIPF; + __IO uint32_t RAER; + uint32_t RESERVED1[6]; + __IO uint32_t PFFUL; + __IO uint32_t PFAN; + uint32_t RESERVED2[16]; +} stc_qspi_sr_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __O uint32_t RAERCLR; + uint32_t RESERVED1[24]; +} stc_qspi_sr2_bit_t; + +typedef struct { + __IO uint32_t PORF; + __IO uint32_t PINRF; + __IO uint32_t BORF; + __IO uint32_t PVD1RF; + __IO uint32_t PVD2RF; + __IO uint32_t WDRF; + __IO uint32_t SWDRF; + __IO uint32_t PDRF; + __IO uint32_t SWRF; + __IO uint32_t MPUERF; + __IO uint32_t RAPERF; + __IO uint32_t RAECRF; + __IO uint32_t CKFERF; + __IO uint32_t XTALERF; + __IO uint32_t MULTIRF; + __IO uint32_t CLRF; +} stc_rmu_rstf0_bit_t; + +typedef struct { + __IO uint32_t RESET; + uint32_t RESERVED0[7]; +} stc_rtc_cr0_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t AMPM; + __IO uint32_t ALMFCLR; + __IO uint32_t ONEHZOE; + __IO uint32_t ONEHZSEL; + __IO uint32_t START; +} stc_rtc_cr1_bit_t; + +typedef struct { + __IO uint32_t RWREQ; + __IO uint32_t RWEN; + uint32_t RESERVED0[1]; + __IO uint32_t ALMF; + uint32_t RESERVED1[1]; + __IO uint32_t PRDIE; + __IO uint32_t ALMIE; + __IO uint32_t ALME; +} stc_rtc_cr2_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t LRCEN; + uint32_t RESERVED1[2]; + __IO uint32_t RCKSEL; +} stc_rtc_cr3_bit_t; + +typedef struct { + __IO uint32_t COMP8; + uint32_t RESERVED0[6]; + __IO uint32_t COMPEN; +} stc_rtc_errcrh_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t BCE; + uint32_t RESERVED1[2]; + __IO uint32_t DDIR; + __IO uint32_t MULB; + uint32_t RESERVED2[10]; +} stc_sdioc_transmode_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t CCE; + __IO uint32_t ICE; + __IO uint32_t DAT; + uint32_t RESERVED1[10]; +} stc_sdioc_cmd_bit_t; + +typedef struct { + __I uint32_t CIC; + __I uint32_t CID; + __I uint32_t DA; + uint32_t RESERVED0[5]; + __I uint32_t WTA; + __I uint32_t RTA; + __I uint32_t BWE; + __I uint32_t BRE; + uint32_t RESERVED1[4]; + __I uint32_t CIN; + __I uint32_t CSS; + __I uint32_t CDL; + __I uint32_t WPL; + uint32_t RESERVED2[4]; + __I uint32_t CMDL; + uint32_t RESERVED3[7]; +} stc_sdioc_pstat_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t DW; + __IO uint32_t HSEN; + uint32_t RESERVED1[2]; + __IO uint32_t EXDW; + __IO uint32_t CDTL; + __IO uint32_t CDSS; +} stc_sdioc_hostcon_bit_t; + +typedef struct { + __IO uint32_t PWON; + uint32_t RESERVED0[7]; +} stc_sdioc_pwrcon_bit_t; + +typedef struct { + __IO uint32_t SABGR; + __IO uint32_t CR; + __IO uint32_t RWC; + __IO uint32_t IABG; + uint32_t RESERVED0[4]; +} stc_sdioc_blkgpcon_bit_t; + +typedef struct { + __IO uint32_t ICE; + uint32_t RESERVED0[1]; + __IO uint32_t CE; + uint32_t RESERVED1[13]; +} stc_sdioc_clkcon_bit_t; + +typedef struct { + __IO uint32_t RSTA; + __IO uint32_t RSTC; + __IO uint32_t RSTD; + uint32_t RESERVED0[5]; +} stc_sdioc_sftrst_bit_t; + +typedef struct { + __IO uint32_t CC; + __IO uint32_t TC; + __IO uint32_t BGE; + uint32_t RESERVED0[1]; + __IO uint32_t BWR; + __IO uint32_t BRR; + __IO uint32_t CIST; + __IO uint32_t CRM; + __I uint32_t CINT; + uint32_t RESERVED1[6]; + __I uint32_t EI; +} stc_sdioc_norintst_bit_t; + +typedef struct { + __IO uint32_t CTOE; + __IO uint32_t CCE; + __IO uint32_t CEBE; + __IO uint32_t CIE; + __IO uint32_t DTOE; + __IO uint32_t DCE; + __IO uint32_t DEBE; + uint32_t RESERVED0[1]; + __IO uint32_t ACE; + uint32_t RESERVED1[7]; +} stc_sdioc_errintst_bit_t; + +typedef struct { + __IO uint32_t CCEN; + __IO uint32_t TCEN; + __IO uint32_t BGEEN; + uint32_t RESERVED0[1]; + __IO uint32_t BWREN; + __IO uint32_t BRREN; + __IO uint32_t CISTEN; + __IO uint32_t CRMEN; + __IO uint32_t CINTEN; + uint32_t RESERVED1[7]; +} stc_sdioc_norintsten_bit_t; + +typedef struct { + __IO uint32_t CTOEEN; + __IO uint32_t CCEEN; + __IO uint32_t CEBEEN; + __IO uint32_t CIEEN; + __IO uint32_t DTOEEN; + __IO uint32_t DCEEN; + __IO uint32_t DEBEEN; + uint32_t RESERVED0[1]; + __IO uint32_t ACEEN; + uint32_t RESERVED1[7]; +} stc_sdioc_errintsten_bit_t; + +typedef struct { + __IO uint32_t CCSEN; + __IO uint32_t TCSEN; + __IO uint32_t BGESEN; + uint32_t RESERVED0[1]; + __IO uint32_t BWRSEN; + __IO uint32_t BRRSEN; + __IO uint32_t CISTSEN; + __IO uint32_t CRMSEN; + __IO uint32_t CINTSEN; + uint32_t RESERVED1[7]; +} stc_sdioc_norintsgen_bit_t; + +typedef struct { + __IO uint32_t CTOESEN; + __IO uint32_t CCESEN; + __IO uint32_t CEBESEN; + __IO uint32_t CIESEN; + __IO uint32_t DTOESEN; + __IO uint32_t DCESEN; + __IO uint32_t DEBESEN; + uint32_t RESERVED0[1]; + __IO uint32_t ACESEN; + uint32_t RESERVED1[7]; +} stc_sdioc_errintsgen_bit_t; + +typedef struct { + __I uint32_t NE; + __I uint32_t TOE; + __I uint32_t CE; + __I uint32_t EBE; + __I uint32_t IE; + uint32_t RESERVED0[2]; + __I uint32_t CMDE; + uint32_t RESERVED1[8]; +} stc_sdioc_atcerrst_bit_t; + +typedef struct { + __O uint32_t FNE; + __O uint32_t FTOE; + __O uint32_t FCE; + __O uint32_t FEBE; + __O uint32_t FIE; + uint32_t RESERVED0[2]; + __O uint32_t FCMDE; + uint32_t RESERVED1[8]; +} stc_sdioc_fea_bit_t; + +typedef struct { + __O uint32_t FCTOE; + __O uint32_t FCCE; + __O uint32_t FCEBE; + __O uint32_t FCIE; + __O uint32_t FDTOE; + __O uint32_t FDCE; + __O uint32_t FDEBE; + uint32_t RESERVED0[1]; + __O uint32_t FACE; + uint32_t RESERVED1[7]; +} stc_sdioc_fee_bit_t; + +typedef struct { + __IO uint32_t SPIMDS; + __IO uint32_t TXMDS; + uint32_t RESERVED0[1]; + __IO uint32_t MSTR; + __IO uint32_t SPLPBK; + __IO uint32_t SPLPBK2; + __IO uint32_t SPE; + __IO uint32_t CSUSPE; + __IO uint32_t EIE; + __IO uint32_t TXIE; + __IO uint32_t RXIE; + __IO uint32_t IDIE; + __IO uint32_t MODFE; + __IO uint32_t PATE; + __IO uint32_t PAOE; + __IO uint32_t PAE; + uint32_t RESERVED1[16]; +} stc_spi_cr1_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t SPRDTD; + uint32_t RESERVED1[1]; + __IO uint32_t SS0PV; + __IO uint32_t SS1PV; + __IO uint32_t SS2PV; + __IO uint32_t SS3PV; + uint32_t RESERVED2[20]; +} stc_spi_cfg1_bit_t; + +typedef struct { + __IO uint32_t OVRERF; + __I uint32_t IDLNF; + __IO uint32_t MODFERF; + __IO uint32_t PERF; + __IO uint32_t UDRERF; + __IO uint32_t TDEF; + uint32_t RESERVED0[1]; + __IO uint32_t RDFF; + uint32_t RESERVED1[24]; +} stc_spi_sr_bit_t; + +typedef struct { + __IO uint32_t CPHA; + __IO uint32_t CPOL; + uint32_t RESERVED0[10]; + __IO uint32_t LSBF; + __IO uint32_t MIDIE; + __IO uint32_t MSSDLE; + __IO uint32_t MSSIE; + uint32_t RESERVED1[16]; +} stc_spi_cfg2_bit_t; + +typedef struct { + __IO uint32_t WTPRC; + uint32_t RESERVED0[31]; +} stc_sramc_wtpr_bit_t; + +typedef struct { + __IO uint32_t PYOAD; + uint32_t RESERVED0[15]; + __IO uint32_t ECCOAD; + uint32_t RESERVED1[15]; +} stc_sramc_ckcr_bit_t; + +typedef struct { + __IO uint32_t CKPRC; + uint32_t RESERVED0[31]; +} stc_sramc_ckpr_bit_t; + +typedef struct { + __IO uint32_t SRAM3_1ERR; + __IO uint32_t SRAM3_2ERR; + __IO uint32_t SRAM12_PYERR; + __IO uint32_t SRAMH_PYERR; + __IO uint32_t SRAMR_PYERR; + uint32_t RESERVED0[27]; +} stc_sramc_cksr_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __IO uint32_t UDF; + __IO uint32_t REF; + uint32_t RESERVED1[14]; +} stc_swdt_sr_bit_t; + +typedef struct { + __IO uint32_t CSTA; + __IO uint32_t CAPMDA; + __IO uint32_t INTENA; + uint32_t RESERVED0[5]; + __IO uint32_t SYNSA; + __IO uint32_t SYNCLKA; + __IO uint32_t ASYNCLKA; + uint32_t RESERVED1[1]; + __IO uint32_t HSTAA; + __IO uint32_t HSTPA; + __IO uint32_t HCLEA; + __IO uint32_t HICPA; + __IO uint32_t CSTB; + __IO uint32_t CAPMDB; + __IO uint32_t INTENB; + uint32_t RESERVED2[5]; + __IO uint32_t SYNSB; + __IO uint32_t SYNCLKB; + __IO uint32_t ASYNCLKB; + uint32_t RESERVED3[1]; + __IO uint32_t HSTAB; + __IO uint32_t HSTPB; + __IO uint32_t HCLEB; + __IO uint32_t HICPB; +} stc_tmr0_bconr_bit_t; + +typedef struct { + __IO uint32_t CMFA; + uint32_t RESERVED0[15]; + __IO uint32_t CMFB; + uint32_t RESERVED1[15]; +} stc_tmr0_stflr_bit_t; + +typedef struct { + __IO uint32_t OCEH; + __IO uint32_t OCEL; + __IO uint32_t OCPH; + __IO uint32_t OCPL; + __IO uint32_t OCIEH; + __IO uint32_t OCIEL; + __IO uint32_t OCFH; + __IO uint32_t OCFL; + uint32_t RESERVED0[8]; +} stc_tmr4_ocsr_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t LMCH; + __IO uint32_t LMCL; + __IO uint32_t LMMH; + __IO uint32_t LMML; + __IO uint32_t MCECH; + __IO uint32_t MCECL; + uint32_t RESERVED1[2]; +} stc_tmr4_ocer_bit_t; + +typedef struct { + __IO uint32_t OCFDCH; + __IO uint32_t OCFPKH; + __IO uint32_t OCFUCH; + __IO uint32_t OCFZRH; + uint32_t RESERVED0[12]; +} stc_tmr4_ocmrh_bit_t; + +typedef struct { + __IO uint32_t OCFDCL; + __IO uint32_t OCFPKL; + __IO uint32_t OCFUCL; + __IO uint32_t OCFZRL; + uint32_t RESERVED0[28]; +} stc_tmr4_ocmrl_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t CLEAR; + __IO uint32_t MODE; + __IO uint32_t STOP; + __IO uint32_t BUFEN; + __IO uint32_t IRQPEN; + __IO uint32_t IRQPF; + uint32_t RESERVED1[3]; + __IO uint32_t IRQZEN; + __IO uint32_t IRQZF; + __IO uint32_t ECKEN; +} stc_tmr4_ccsr_bit_t; + +typedef struct { + __IO uint32_t RTIDU; + __IO uint32_t RTIDV; + __IO uint32_t RTIDW; + uint32_t RESERVED0[1]; + __I uint32_t RTIFU; + __IO uint32_t RTICU; + __IO uint32_t RTEU; + __IO uint32_t RTSU; + __I uint32_t RTIFV; + __IO uint32_t RTICV; + __IO uint32_t RTEV; + __IO uint32_t RTSV; + __I uint32_t RTIFW; + __IO uint32_t RTICW; + __IO uint32_t RTEW; + __IO uint32_t RTSW; +} stc_tmr4_rcsr_bit_t; + +typedef struct { + uint32_t RESERVED0[5]; + __IO uint32_t LMC; + uint32_t RESERVED1[2]; + __IO uint32_t EVTMS; + __IO uint32_t EVTDS; + uint32_t RESERVED2[2]; + __IO uint32_t DEN; + __IO uint32_t PEN; + __IO uint32_t UEN; + __IO uint32_t ZEN; +} stc_tmr4_scsr_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t MZCE; + __IO uint32_t MPCE; + uint32_t RESERVED1[8]; +} stc_tmr4_scmr_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t HOLD; + uint32_t RESERVED1[8]; +} stc_tmr4_ecsr_bit_t; + +typedef struct { + __IO uint32_t START; + uint32_t RESERVED0[7]; + __IO uint32_t DIR; + uint32_t RESERVED1[7]; + __IO uint32_t ZMSKREV; + __IO uint32_t ZMSKPOS; + uint32_t RESERVED2[14]; +} stc_tmr6_gconr_bit_t; + +typedef struct { + __IO uint32_t INTENA; + __IO uint32_t INTENB; + __IO uint32_t INTENC; + __IO uint32_t INTEND; + __IO uint32_t INTENE; + __IO uint32_t INTENF; + __IO uint32_t INTENOVF; + __IO uint32_t INTENUDF; + __IO uint32_t INTENDTE; + uint32_t RESERVED0[7]; + __IO uint32_t INTENSAU; + __IO uint32_t INTENSAD; + __IO uint32_t INTENSBU; + __IO uint32_t INTENSBD; + uint32_t RESERVED1[12]; +} stc_tmr6_iconr_bit_t; + +typedef struct { + __IO uint32_t CAPMDA; + __IO uint32_t STACA; + __IO uint32_t STPCA; + __IO uint32_t STASTPSA; + uint32_t RESERVED0[4]; + __IO uint32_t OUTENA; + uint32_t RESERVED1[7]; + __IO uint32_t CAPMDB; + __IO uint32_t STACB; + __IO uint32_t STPCB; + __IO uint32_t STASTPSB; + uint32_t RESERVED2[4]; + __IO uint32_t OUTENB; + uint32_t RESERVED3[7]; +} stc_tmr6_pconr_bit_t; + +typedef struct { + __IO uint32_t BENA; + __IO uint32_t BSEA; + __IO uint32_t BENB; + __IO uint32_t BSEB; + uint32_t RESERVED0[4]; + __IO uint32_t BENP; + __IO uint32_t BSEP; + uint32_t RESERVED1[6]; + __IO uint32_t BENSPA; + __IO uint32_t BSESPA; + uint32_t RESERVED2[2]; + __IO uint32_t BTRUSPA; + __IO uint32_t BTRDSPA; + uint32_t RESERVED3[2]; + __IO uint32_t BENSPB; + __IO uint32_t BSESPB; + uint32_t RESERVED4[2]; + __IO uint32_t BTRUSPB; + __IO uint32_t BTRDSPB; + uint32_t RESERVED5[2]; +} stc_tmr6_bconr_bit_t; + +typedef struct { + __IO uint32_t DTCEN; + uint32_t RESERVED0[3]; + __IO uint32_t DTBENU; + __IO uint32_t DTBEND; + uint32_t RESERVED1[2]; + __IO uint32_t SEPA; + uint32_t RESERVED2[23]; +} stc_tmr6_dconr_bit_t; + +typedef struct { + __IO uint32_t NOFIENGA; + uint32_t RESERVED0[3]; + __IO uint32_t NOFIENGB; + uint32_t RESERVED1[11]; + __IO uint32_t NOFIENTA; + uint32_t RESERVED2[3]; + __IO uint32_t NOFIENTB; + uint32_t RESERVED3[11]; +} stc_tmr6_fconr_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t SPPERIA; + __IO uint32_t SPPERIB; + uint32_t RESERVED1[22]; +} stc_tmr6_vperr_bit_t; + +typedef struct { + __IO uint32_t CMAF; + __IO uint32_t CMBF; + __IO uint32_t CMCF; + __IO uint32_t CMDF; + __IO uint32_t CMEF; + __IO uint32_t CMFF; + __IO uint32_t OVFF; + __IO uint32_t UDFF; + __I uint32_t DTEF; + __IO uint32_t CMSAUF; + __IO uint32_t CMSADF; + __IO uint32_t CMSBUF; + __IO uint32_t CMSBDF; + uint32_t RESERVED0[18]; + __I uint32_t DIRF; +} stc_tmr6_stflr_bit_t; + +typedef struct { + __IO uint32_t HSTA0; + __IO uint32_t HSTA1; + uint32_t RESERVED0[2]; + __IO uint32_t HSTA4; + __IO uint32_t HSTA5; + __IO uint32_t HSTA6; + __IO uint32_t HSTA7; + __IO uint32_t HSTA8; + __IO uint32_t HSTA9; + __IO uint32_t HSTA10; + __IO uint32_t HSTA11; + uint32_t RESERVED1[19]; + __IO uint32_t STAS; +} stc_tmr6_hstar_bit_t; + +typedef struct { + __IO uint32_t HSTP0; + __IO uint32_t HSTP1; + uint32_t RESERVED0[2]; + __IO uint32_t HSTP4; + __IO uint32_t HSTP5; + __IO uint32_t HSTP6; + __IO uint32_t HSTP7; + __IO uint32_t HSTP8; + __IO uint32_t HSTP9; + __IO uint32_t HSTP10; + __IO uint32_t HSTP11; + uint32_t RESERVED1[19]; + __IO uint32_t STPS; +} stc_tmr6_hstpr_bit_t; + +typedef struct { + __IO uint32_t HCLE0; + __IO uint32_t HCLE1; + uint32_t RESERVED0[2]; + __IO uint32_t HCLE4; + __IO uint32_t HCLE5; + __IO uint32_t HCLE6; + __IO uint32_t HCLE7; + __IO uint32_t HCLE8; + __IO uint32_t HCLE9; + __IO uint32_t HCLE10; + __IO uint32_t HCLE11; + uint32_t RESERVED1[19]; + __IO uint32_t CLES; +} stc_tmr6_hclrr_bit_t; + +typedef struct { + __IO uint32_t HCPA0; + __IO uint32_t HCPA1; + uint32_t RESERVED0[2]; + __IO uint32_t HCPA4; + __IO uint32_t HCPA5; + __IO uint32_t HCPA6; + __IO uint32_t HCPA7; + __IO uint32_t HCPA8; + __IO uint32_t HCPA9; + __IO uint32_t HCPA10; + __IO uint32_t HCPA11; + uint32_t RESERVED1[20]; +} stc_tmr6_hcpar_bit_t; + +typedef struct { + __IO uint32_t HCPB0; + __IO uint32_t HCPB1; + uint32_t RESERVED0[2]; + __IO uint32_t HCPB4; + __IO uint32_t HCPB5; + __IO uint32_t HCPB6; + __IO uint32_t HCPB7; + __IO uint32_t HCPB8; + __IO uint32_t HCPB9; + __IO uint32_t HCPB10; + __IO uint32_t HCPB11; + uint32_t RESERVED1[20]; +} stc_tmr6_hcpbr_bit_t; + +typedef struct { + __IO uint32_t HCUP0; + __IO uint32_t HCUP1; + __IO uint32_t HCUP2; + __IO uint32_t HCUP3; + __IO uint32_t HCUP4; + __IO uint32_t HCUP5; + __IO uint32_t HCUP6; + __IO uint32_t HCUP7; + __IO uint32_t HCUP8; + __IO uint32_t HCUP9; + __IO uint32_t HCUP10; + __IO uint32_t HCUP11; + uint32_t RESERVED0[4]; + __IO uint32_t HCUP16; + __IO uint32_t HCUP17; + uint32_t RESERVED1[14]; +} stc_tmr6_hcupr_bit_t; + +typedef struct { + __IO uint32_t HCDO0; + __IO uint32_t HCDO1; + __IO uint32_t HCDO2; + __IO uint32_t HCDO3; + __IO uint32_t HCDO4; + __IO uint32_t HCDO5; + __IO uint32_t HCDO6; + __IO uint32_t HCDO7; + __IO uint32_t HCDO8; + __IO uint32_t HCDO9; + __IO uint32_t HCDO10; + __IO uint32_t HCDO11; + uint32_t RESERVED0[4]; + __IO uint32_t HCDO16; + __IO uint32_t HCDO17; + uint32_t RESERVED1[14]; +} stc_tmr6_hcdor_bit_t; + +typedef struct { + __IO uint32_t SSTA1; + __IO uint32_t SSTA2; + __IO uint32_t SSTA3; + uint32_t RESERVED0[29]; +} stc_tmr6cr_sstar_bit_t; + +typedef struct { + __IO uint32_t SSTP1; + __IO uint32_t SSTP2; + __IO uint32_t SSTP3; + uint32_t RESERVED0[29]; +} stc_tmr6cr_sstpr_bit_t; + +typedef struct { + __IO uint32_t SCLE1; + __IO uint32_t SCLE2; + __IO uint32_t SCLE3; + uint32_t RESERVED0[29]; +} stc_tmr6cr_sclrr_bit_t; + +typedef struct { + __IO uint32_t START; + __IO uint32_t DIR; + __IO uint32_t MODE; + __IO uint32_t SYNST; + uint32_t RESERVED0[4]; +} stc_tmra_bcstrl_bit_t; + +typedef struct { + __IO uint32_t OVSTP; + uint32_t RESERVED0[3]; + __IO uint32_t ITENOVF; + __IO uint32_t ITENUDF; + __IO uint32_t OVFF; + __IO uint32_t UDFF; +} stc_tmra_bcstrh_bit_t; + +typedef struct { + __IO uint32_t HSTA0; + __IO uint32_t HSTA1; + __IO uint32_t HSTA2; + uint32_t RESERVED0[1]; + __IO uint32_t HSTP0; + __IO uint32_t HSTP1; + __IO uint32_t HSTP2; + uint32_t RESERVED1[1]; + __IO uint32_t HCLE0; + __IO uint32_t HCLE1; + __IO uint32_t HCLE2; + uint32_t RESERVED2[1]; + __IO uint32_t HCLE3; + __IO uint32_t HCLE4; + __IO uint32_t HCLE5; + __IO uint32_t HCLE6; +} stc_tmra_hconr_bit_t; + +typedef struct { + __IO uint32_t HCUP0; + __IO uint32_t HCUP1; + __IO uint32_t HCUP2; + __IO uint32_t HCUP3; + __IO uint32_t HCUP4; + __IO uint32_t HCUP5; + __IO uint32_t HCUP6; + __IO uint32_t HCUP7; + __IO uint32_t HCUP8; + __IO uint32_t HCUP9; + __IO uint32_t HCUP10; + __IO uint32_t HCUP11; + __IO uint32_t HCUP12; + uint32_t RESERVED0[3]; +} stc_tmra_hcupr_bit_t; + +typedef struct { + __IO uint32_t HCDO0; + __IO uint32_t HCDO1; + __IO uint32_t HCDO2; + __IO uint32_t HCDO3; + __IO uint32_t HCDO4; + __IO uint32_t HCDO5; + __IO uint32_t HCDO6; + __IO uint32_t HCDO7; + __IO uint32_t HCDO8; + __IO uint32_t HCDO9; + __IO uint32_t HCDO10; + __IO uint32_t HCDO11; + __IO uint32_t HCDO12; + uint32_t RESERVED0[3]; +} stc_tmra_hcdor_bit_t; + +typedef struct { + __IO uint32_t ITEN1; + __IO uint32_t ITEN2; + __IO uint32_t ITEN3; + __IO uint32_t ITEN4; + __IO uint32_t ITEN5; + __IO uint32_t ITEN6; + __IO uint32_t ITEN7; + __IO uint32_t ITEN8; + uint32_t RESERVED0[8]; +} stc_tmra_iconr_bit_t; + +typedef struct { + __IO uint32_t ETEN1; + __IO uint32_t ETEN2; + __IO uint32_t ETEN3; + __IO uint32_t ETEN4; + __IO uint32_t ETEN5; + __IO uint32_t ETEN6; + __IO uint32_t ETEN7; + __IO uint32_t ETEN8; + uint32_t RESERVED0[8]; +} stc_tmra_econr_bit_t; + +typedef struct { + __IO uint32_t NOFIENTG; + uint32_t RESERVED0[7]; + __IO uint32_t NOFIENCA; + uint32_t RESERVED1[3]; + __IO uint32_t NOFIENCB; + uint32_t RESERVED2[3]; +} stc_tmra_fconr_bit_t; + +typedef struct { + __IO uint32_t CMPF1; + __IO uint32_t CMPF2; + __IO uint32_t CMPF3; + __IO uint32_t CMPF4; + __IO uint32_t CMPF5; + __IO uint32_t CMPF6; + __IO uint32_t CMPF7; + __IO uint32_t CMPF8; + uint32_t RESERVED0[8]; +} stc_tmra_stflr_bit_t; + +typedef struct { + __IO uint32_t BEN; + __IO uint32_t BSE0; + __IO uint32_t BSE1; + uint32_t RESERVED0[13]; +} stc_tmra_bconr_bit_t; + +typedef struct { + __IO uint32_t CAPMD; + uint32_t RESERVED0[3]; + __IO uint32_t HICP0; + __IO uint32_t HICP1; + __IO uint32_t HICP2; + uint32_t RESERVED1[1]; + __IO uint32_t HICP3; + __IO uint32_t HICP4; + uint32_t RESERVED2[2]; + __IO uint32_t NOFIENCP; + uint32_t RESERVED3[3]; +} stc_tmra_cconr_bit_t; + +typedef struct { + uint32_t RESERVED0[12]; + __IO uint32_t OUTEN; + uint32_t RESERVED1[3]; +} stc_tmra_pconr_bit_t; + +typedef struct { + __IO uint32_t EN; + __IO uint32_t RUN; + uint32_t RESERVED0[30]; +} stc_trng_cr_bit_t; + +typedef struct { + __IO uint32_t LOAD; + uint32_t RESERVED0[31]; +} stc_trng_mr_bit_t; + +typedef struct { + __I uint32_t PE; + __I uint32_t FE; + uint32_t RESERVED0[1]; + __I uint32_t ORE; + uint32_t RESERVED1[1]; + __I uint32_t RXNE; + __I uint32_t TC; + __I uint32_t TXE; + __I uint32_t RTOF; + uint32_t RESERVED2[7]; + __I uint32_t MPB; + uint32_t RESERVED3[15]; +} stc_usart_sr_bit_t; + +typedef struct { + uint32_t RESERVED0[9]; + __IO uint32_t MPID; + uint32_t RESERVED1[6]; +} stc_usart_tdr_bit_t; + +typedef struct { + __IO uint32_t RTOE; + __IO uint32_t RTOIE; + __IO uint32_t RE; + __IO uint32_t TE; + __IO uint32_t SLME; + __IO uint32_t RIE; + __IO uint32_t TCIE; + __IO uint32_t TXEIE; + uint32_t RESERVED0[1]; + __IO uint32_t PS; + __IO uint32_t PCE; + uint32_t RESERVED1[1]; + __IO uint32_t M; + uint32_t RESERVED2[2]; + __IO uint32_t OVER8; + __O uint32_t CPE; + __O uint32_t CFE; + uint32_t RESERVED3[1]; + __O uint32_t CORE; + __O uint32_t CRTOF; + uint32_t RESERVED4[3]; + __IO uint32_t MS; + uint32_t RESERVED5[3]; + __IO uint32_t ML; + __IO uint32_t FBME; + __IO uint32_t NFE; + __IO uint32_t SBS; +} stc_usart_cr1_bit_t; + +typedef struct { + __IO uint32_t MPE; + uint32_t RESERVED0[12]; + __IO uint32_t STOP; + uint32_t RESERVED1[18]; +} stc_usart_cr2_bit_t; + +typedef struct { + uint32_t RESERVED0[5]; + __IO uint32_t SCEN; + uint32_t RESERVED1[3]; + __IO uint32_t CTSE; + uint32_t RESERVED2[22]; +} stc_usart_cr3_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t VBUSOVEN; + __IO uint32_t VBUSVAL; + uint32_t RESERVED1[24]; +} stc_usbfs_gvbuscfg_bit_t; + +typedef struct { + __IO uint32_t GINTMSK; + uint32_t RESERVED0[4]; + __IO uint32_t DMAEN; + uint32_t RESERVED1[1]; + __IO uint32_t TXFELVL; + __IO uint32_t PTXFELVL; + uint32_t RESERVED2[23]; +} stc_usbfs_gahbcfg_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t PHYSEL; + uint32_t RESERVED1[22]; + __IO uint32_t FHMOD; + __IO uint32_t FDMOD; + uint32_t RESERVED2[1]; +} stc_usbfs_gusbcfg_bit_t; + +typedef struct { + __IO uint32_t CSRST; + __IO uint32_t HSRST; + __IO uint32_t FCRST; + uint32_t RESERVED0[1]; + __IO uint32_t RXFFLSH; + __IO uint32_t TXFFLSH; + uint32_t RESERVED1[24]; + __I uint32_t DMAREQ; + __I uint32_t AHBIDL; +} stc_usbfs_grstctl_bit_t; + +typedef struct { + __I uint32_t CMOD; + __IO uint32_t MMIS; + uint32_t RESERVED0[1]; + __IO uint32_t SOF; + __I uint32_t RXFNE; + __I uint32_t NPTXFE; + __I uint32_t GINAKEFF; + __I uint32_t GONAKEFF; + uint32_t RESERVED1[2]; + __IO uint32_t ESUSP; + __IO uint32_t USBSUSP; + __IO uint32_t USBRST; + __IO uint32_t ENUMDNE; + __IO uint32_t ISOODRP; + __IO uint32_t EOPF; + uint32_t RESERVED2[2]; + __I uint32_t IEPINT; + __I uint32_t OEPINT; + __IO uint32_t IISOIXFR; + __IO uint32_t IPXFR_INCOMPISOOUT; + __IO uint32_t DATAFSUSP; + uint32_t RESERVED3[1]; + __I uint32_t HPRTINT; + __I uint32_t HCINT; + __I uint32_t PTXFE; + uint32_t RESERVED4[1]; + __IO uint32_t CIDSCHG; + __IO uint32_t DISCINT; + __IO uint32_t VBUSVINT; + __IO uint32_t WKUINT; +} stc_usbfs_gintsts_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t MMISM; + uint32_t RESERVED1[1]; + __IO uint32_t SOFM; + __IO uint32_t RXFNEM; + __IO uint32_t NPTXFEM; + __IO uint32_t GINAKEFFM; + __IO uint32_t GONAKEFFM; + uint32_t RESERVED2[2]; + __IO uint32_t ESUSPM; + __IO uint32_t USBSUSPM; + __IO uint32_t USBRSTM; + __IO uint32_t ENUMDNEM; + __IO uint32_t ISOODRPM; + __IO uint32_t EOPFM; + uint32_t RESERVED3[2]; + __IO uint32_t IEPIM; + __IO uint32_t OEPIM; + __IO uint32_t IISOIXFRM; + __IO uint32_t IPXFRM_INCOMPISOOUTM; + __IO uint32_t DATAFSUSPM; + uint32_t RESERVED4[1]; + __IO uint32_t HPRTIM; + __IO uint32_t HCIM; + __IO uint32_t PTXFEM; + uint32_t RESERVED5[1]; + __IO uint32_t CIDSCHGM; + __IO uint32_t DISCIM; + __IO uint32_t VBUSVIM; + __IO uint32_t WKUIM; +} stc_usbfs_gintmsk_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t FSLSS; + uint32_t RESERVED1[29]; +} stc_usbfs_hcfg_bit_t; + +typedef struct { + __I uint32_t PCSTS; + __IO uint32_t PCDET; + __IO uint32_t PENA; + __IO uint32_t PENCHNG; + uint32_t RESERVED0[2]; + __IO uint32_t PRES; + __IO uint32_t PSUSP; + __IO uint32_t PRST; + uint32_t RESERVED1[3]; + __IO uint32_t PWPR; + uint32_t RESERVED2[19]; +} stc_usbfs_hprt_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSDEV; + uint32_t RESERVED2[11]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbfs_hcchar_bit_t; + +typedef struct { + __IO uint32_t XFRC; + __IO uint32_t CHH; + uint32_t RESERVED0[1]; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + uint32_t RESERVED1[1]; + __IO uint32_t TXERR; + __IO uint32_t BBERR; + __IO uint32_t FRMOR; + __IO uint32_t DTERR; + uint32_t RESERVED2[21]; +} stc_usbfs_hcint_bit_t; + +typedef struct { + __IO uint32_t XFRCM; + __IO uint32_t CHHM; + uint32_t RESERVED0[1]; + __IO uint32_t STALLM; + __IO uint32_t NAKM; + __IO uint32_t ACKM; + uint32_t RESERVED1[1]; + __IO uint32_t TXERRM; + __IO uint32_t BBERRM; + __IO uint32_t FRMORM; + __IO uint32_t DTERRM; + uint32_t RESERVED2[21]; +} stc_usbfs_hcintmsk_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t NZLSOHSK; + uint32_t RESERVED1[29]; +} stc_usbfs_dcfg_bit_t; + +typedef struct { + __IO uint32_t RWUSIG; + __IO uint32_t SDIS; + __I uint32_t GINSTS; + __I uint32_t GONSTS; + uint32_t RESERVED0[3]; + __O uint32_t SGINAK; + __O uint32_t CGINAK; + __O uint32_t SGONAK; + __O uint32_t CGONAK; + __IO uint32_t POPRGDNE; + uint32_t RESERVED1[20]; +} stc_usbfs_dctl_bit_t; + +typedef struct { + __I uint32_t SUSPSTS; + uint32_t RESERVED0[2]; + __I uint32_t EERR; + uint32_t RESERVED1[28]; +} stc_usbfs_dsts_bit_t; + +typedef struct { + __IO uint32_t XFRCM; + __IO uint32_t EPDM; + uint32_t RESERVED0[1]; + __IO uint32_t TOM; + __IO uint32_t TTXFEMSK; + __IO uint32_t INEPNMM; + __IO uint32_t INEPNEM; + uint32_t RESERVED1[25]; +} stc_usbfs_diepmsk_bit_t; + +typedef struct { + __IO uint32_t XFRCM; + __IO uint32_t EPDM; + uint32_t RESERVED0[1]; + __IO uint32_t STUPM; + __IO uint32_t OTEPDM; + uint32_t RESERVED1[27]; +} stc_usbfs_doepmsk_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __I uint32_t USBAEP; + uint32_t RESERVED1[1]; + __I uint32_t NAKSTS; + uint32_t RESERVED2[3]; + __IO uint32_t STALL; + uint32_t RESERVED3[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + uint32_t RESERVED4[2]; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl0_bit_t; + +typedef struct { + __IO uint32_t XFRC; + __IO uint32_t EPDISD; + uint32_t RESERVED0[1]; + __IO uint32_t TOC; + __IO uint32_t TTXFE; + uint32_t RESERVED1[1]; + __IO uint32_t INEPNE; + __I uint32_t TXFE; + uint32_t RESERVED2[24]; +} stc_usbfs_diepint_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __IO uint32_t USBAEP; + __I uint32_t EONUM_DPID; + __I uint32_t NAKSTS; + uint32_t RESERVED1[3]; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SD0PID_SEVNFRM; + __IO uint32_t SODDFRM; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __I uint32_t USBAEP; + uint32_t RESERVED1[1]; + __I uint32_t NAKSTS; + uint32_t RESERVED2[2]; + __IO uint32_t SNPM; + __IO uint32_t STALL; + uint32_t RESERVED3[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + uint32_t RESERVED4[2]; + __I uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl0_bit_t; + +typedef struct { + __IO uint32_t XFRC; + __IO uint32_t EPDISD; + uint32_t RESERVED0[1]; + __IO uint32_t STUP; + __IO uint32_t OTEPDIS; + uint32_t RESERVED1[1]; + __IO uint32_t B2BSTUP; + uint32_t RESERVED2[25]; +} stc_usbfs_doepint_bit_t; + +typedef struct { + uint32_t RESERVED0[19]; + __IO uint32_t PKTCNT; + uint32_t RESERVED1[12]; +} stc_usbfs_doeptsiz0_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __IO uint32_t USBAEP; + __I uint32_t DPID; + __I uint32_t NAKSTS; + uint32_t RESERVED1[2]; + __IO uint32_t SNPM; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SD0PID; + __IO uint32_t SD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl_bit_t; + +typedef struct { + __IO uint32_t STPPCLK; + __IO uint32_t GATEHCLK; + uint32_t RESERVED0[30]; +} stc_usbfs_gcctl_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __IO uint32_t SLPOFF; + uint32_t RESERVED1[14]; + __IO uint32_t ITS; +} stc_wdt_cr_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __IO uint32_t UDF; + __IO uint32_t REF; + uint32_t RESERVED1[14]; +} stc_wdt_sr_bit_t; + + +typedef struct { + stc_adc_str_bit_t STR_b; + uint32_t RESERVED0[8]; + stc_adc_cr0_bit_t CR0_b; + stc_adc_cr1_bit_t CR1_b; + uint32_t RESERVED1[32]; + stc_adc_trgsr_bit_t TRGSR_b; + uint32_t RESERVED2[464]; + stc_adc_isr_bit_t ISR_b; + stc_adc_icr_bit_t ICR_b; + uint32_t RESERVED3[32]; + stc_adc_synccr_bit_t SYNCCR_b; + uint32_t RESERVED4[656]; + stc_adc_awdcr_bit_t AWDCR_b; + uint32_t RESERVED5[352]; + stc_adc_pgainsr1_bit_t PGAINSR1_b; +} bCM_ADC_TypeDef; + +typedef struct { + stc_aes_cr_bit_t CR_b; +} bCM_AES_TypeDef; + +typedef struct { + stc_aos_intsfttrg_bit_t INTSFTTRG_b; + uint32_t RESERVED0[2912]; + stc_aos_pevntnfcr_bit_t PEVNTNFCR_b; +} bCM_AOS_TypeDef; + +typedef struct { + uint32_t RESERVED0[1280]; + stc_can_cfg_stat_bit_t CFG_STAT_b; + stc_can_tcmd_bit_t TCMD_b; + stc_can_tctrl_bit_t TCTRL_b; + stc_can_rctrl_bit_t RCTRL_b; + stc_can_rtie_bit_t RTIE_b; + stc_can_rtif_bit_t RTIF_b; + stc_can_errint_bit_t ERRINT_b; + uint32_t RESERVED1[104]; + stc_can_acfctrl_bit_t ACFCTRL_b; + uint32_t RESERVED2[8]; + stc_can_acfen_bit_t ACFEN_b; + uint32_t RESERVED3[8]; + stc_can_acf_bit_t ACF_b; + uint32_t RESERVED4[16]; + stc_can_tbslot_bit_t TBSLOT_b; + stc_can_ttcfg_bit_t TTCFG_b; + stc_can_ref_msg_bit_t REF_MSG_b; +} bCM_CAN_TypeDef; + +typedef struct { + stc_cmp_ctrl_bit_t CTRL_b; + stc_cmp_vltsel_bit_t VLTSEL_b; + stc_cmp_outmon_bit_t OUTMON_b; +} bCM_CMP_TypeDef; + +typedef struct { + uint32_t RESERVED0[2112]; + stc_cmpcr_dacr_bit_t DACR_b; + uint32_t RESERVED1[16]; + stc_cmpcr_rvadc_bit_t RVADC_b; +} bCM_CMPCR_TypeDef; + +typedef struct { + stc_crc_cr_bit_t CR_b; + stc_crc_reslt_bit_t RESLT_b; + uint32_t RESERVED0[32]; + stc_crc_flg_bit_t FLG_b; +} bCM_CRC_TypeDef; + +typedef struct { + uint32_t RESERVED0[128]; + stc_dbgc_mcustat_bit_t MCUSTAT_b; + uint32_t RESERVED1[32]; + stc_dbgc_fersctl_bit_t FERSCTL_b; + stc_dbgc_mcudbgstat_bit_t MCUDBGSTAT_b; + stc_dbgc_mcustpctl_bit_t MCUSTPCTL_b; + stc_dbgc_mcutracectl_bit_t MCUTRACECTL_b; +} bCM_DBGC_TypeDef; + +typedef struct { + stc_dcu_ctl_bit_t CTL_b; + stc_dcu_flag_bit_t FLAG_b; + uint32_t RESERVED0[96]; + stc_dcu_flagclr_bit_t FLAGCLR_b; + stc_dcu_intevtsel_bit_t INTEVTSEL_b; +} bCM_DCU_TypeDef; + +typedef struct { + stc_dma_en_bit_t EN_b; + stc_dma_intstat0_bit_t INTSTAT0_b; + stc_dma_intstat1_bit_t INTSTAT1_b; + stc_dma_intmask0_bit_t INTMASK0_b; + stc_dma_intmask1_bit_t INTMASK1_b; + stc_dma_intclr0_bit_t INTCLR0_b; + stc_dma_intclr1_bit_t INTCLR1_b; + uint32_t RESERVED0[32]; + stc_dma_reqstat_bit_t REQSTAT_b; + stc_dma_chstat_bit_t CHSTAT_b; + uint32_t RESERVED1[32]; + stc_dma_rcfgctl_bit_t RCFGCTL_b; + uint32_t RESERVED2[352]; + stc_dma_chctl_bit_t CHCTL0_b; + uint32_t RESERVED3[480]; + stc_dma_chctl_bit_t CHCTL1_b; + uint32_t RESERVED4[480]; + stc_dma_chctl_bit_t CHCTL2_b; + uint32_t RESERVED5[480]; + stc_dma_chctl_bit_t CHCTL3_b; +} bCM_DMA_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_efm_fstp_bit_t FSTP_b; + stc_efm_frmc_bit_t FRMC_b; + stc_efm_fwmc_bit_t FWMC_b; + stc_efm_fsr_bit_t FSR_b; + stc_efm_fsclr_bit_t FSCLR_b; + stc_efm_fite_bit_t FITE_b; + stc_efm_fswp_bit_t FSWP_b; + uint32_t RESERVED1[1824]; + stc_efm_mmf_remcr_bit_t MMF_REMCR0_b; + stc_efm_mmf_remcr_bit_t MMF_REMCR1_b; +} bCM_EFM_TypeDef; + +typedef struct { + stc_emb_ctl_bit_t CTL_b; + stc_emb_pwmlv_bit_t PWMLV_b; + stc_emb_soe_bit_t SOE_b; + stc_emb_stat_bit_t STAT_b; + stc_emb_statclr_bit_t STATCLR_b; + stc_emb_inten_bit_t INTEN_b; +} bCM_EMB_TypeDef; + +typedef struct { + uint32_t RESERVED0[96]; + stc_fcm_str_bit_t STR_b; + uint32_t RESERVED1[32]; + stc_fcm_rccr_bit_t RCCR_b; + stc_fcm_rier_bit_t RIER_b; + stc_fcm_sr_bit_t SR_b; + stc_fcm_clr_bit_t CLR_b; +} bCM_FCM_TypeDef; + +typedef struct { + stc_gpio_pidr_bit_t PIDRA_b; + uint32_t RESERVED0[16]; + stc_gpio_podr_bit_t PODRA_b; + stc_gpio_poer_bit_t POERA_b; + stc_gpio_posr_bit_t POSRA_b; + stc_gpio_porr_bit_t PORRA_b; + stc_gpio_potr_bit_t POTRA_b; + uint32_t RESERVED1[16]; + stc_gpio_pidr_bit_t PIDRB_b; + uint32_t RESERVED2[16]; + stc_gpio_podr_bit_t PODRB_b; + stc_gpio_poer_bit_t POERB_b; + stc_gpio_posr_bit_t POSRB_b; + stc_gpio_porr_bit_t PORRB_b; + stc_gpio_potr_bit_t POTRB_b; + uint32_t RESERVED3[16]; + stc_gpio_pidr_bit_t PIDRC_b; + uint32_t RESERVED4[16]; + stc_gpio_podr_bit_t PODRC_b; + stc_gpio_poer_bit_t POERC_b; + stc_gpio_posr_bit_t POSRC_b; + stc_gpio_porr_bit_t PORRC_b; + stc_gpio_potr_bit_t POTRC_b; + uint32_t RESERVED5[16]; + stc_gpio_pidr_bit_t PIDRD_b; + uint32_t RESERVED6[16]; + stc_gpio_podr_bit_t PODRD_b; + stc_gpio_poer_bit_t POERD_b; + stc_gpio_posr_bit_t POSRD_b; + stc_gpio_porr_bit_t PORRD_b; + stc_gpio_potr_bit_t POTRD_b; + uint32_t RESERVED7[16]; + stc_gpio_pidr_bit_t PIDRE_b; + uint32_t RESERVED8[16]; + stc_gpio_podr_bit_t PODRE_b; + stc_gpio_poer_bit_t POERE_b; + stc_gpio_posr_bit_t POSRE_b; + stc_gpio_porr_bit_t PORRE_b; + stc_gpio_potr_bit_t POTRE_b; + uint32_t RESERVED9[16]; + stc_gpio_pidrh_bit_t PIDRH_b; + uint32_t RESERVED10[16]; + stc_gpio_podrh_bit_t PODRH_b; + stc_gpio_poerh_bit_t POERH_b; + stc_gpio_posrh_bit_t POSRH_b; + stc_gpio_porrh_bit_t PORRH_b; + stc_gpio_potrh_bit_t POTRH_b; + uint32_t RESERVED11[7408]; + stc_gpio_pwpr_bit_t PWPR_b; + uint32_t RESERVED12[16]; + stc_gpio_pcr_bit_t PCRA0_b; + stc_gpio_pfsr_bit_t PFSRA0_b; + stc_gpio_pcr_bit_t PCRA1_b; + stc_gpio_pfsr_bit_t PFSRA1_b; + stc_gpio_pcr_bit_t PCRA2_b; + stc_gpio_pfsr_bit_t PFSRA2_b; + stc_gpio_pcr_bit_t PCRA3_b; + stc_gpio_pfsr_bit_t PFSRA3_b; + stc_gpio_pcr_bit_t PCRA4_b; + stc_gpio_pfsr_bit_t PFSRA4_b; + stc_gpio_pcr_bit_t PCRA5_b; + stc_gpio_pfsr_bit_t PFSRA5_b; + stc_gpio_pcr_bit_t PCRA6_b; + stc_gpio_pfsr_bit_t PFSRA6_b; + stc_gpio_pcr_bit_t PCRA7_b; + stc_gpio_pfsr_bit_t PFSRA7_b; + stc_gpio_pcr_bit_t PCRA8_b; + stc_gpio_pfsr_bit_t PFSRA8_b; + stc_gpio_pcr_bit_t PCRA9_b; + stc_gpio_pfsr_bit_t PFSRA9_b; + stc_gpio_pcr_bit_t PCRA10_b; + stc_gpio_pfsr_bit_t PFSRA10_b; + stc_gpio_pcr_bit_t PCRA11_b; + stc_gpio_pfsr_bit_t PFSRA11_b; + stc_gpio_pcr_bit_t PCRA12_b; + stc_gpio_pfsr_bit_t PFSRA12_b; + stc_gpio_pcr_bit_t PCRA13_b; + stc_gpio_pfsr_bit_t PFSRA13_b; + stc_gpio_pcr_bit_t PCRA14_b; + stc_gpio_pfsr_bit_t PFSRA14_b; + stc_gpio_pcr_bit_t PCRA15_b; + stc_gpio_pfsr_bit_t PFSRA15_b; + stc_gpio_pcr_bit_t PCRB0_b; + stc_gpio_pfsr_bit_t PFSRB0_b; + stc_gpio_pcr_bit_t PCRB1_b; + stc_gpio_pfsr_bit_t PFSRB1_b; + stc_gpio_pcr_bit_t PCRB2_b; + stc_gpio_pfsr_bit_t PFSRB2_b; + stc_gpio_pcr_bit_t PCRB3_b; + stc_gpio_pfsr_bit_t PFSRB3_b; + stc_gpio_pcr_bit_t PCRB4_b; + stc_gpio_pfsr_bit_t PFSRB4_b; + stc_gpio_pcr_bit_t PCRB5_b; + stc_gpio_pfsr_bit_t PFSRB5_b; + stc_gpio_pcr_bit_t PCRB6_b; + stc_gpio_pfsr_bit_t PFSRB6_b; + stc_gpio_pcr_bit_t PCRB7_b; + stc_gpio_pfsr_bit_t PFSRB7_b; + stc_gpio_pcr_bit_t PCRB8_b; + stc_gpio_pfsr_bit_t PFSRB8_b; + stc_gpio_pcr_bit_t PCRB9_b; + stc_gpio_pfsr_bit_t PFSRB9_b; + stc_gpio_pcr_bit_t PCRB10_b; + stc_gpio_pfsr_bit_t PFSRB10_b; + stc_gpio_pcr_bit_t PCRB11_b; + stc_gpio_pfsr_bit_t PFSRB11_b; + stc_gpio_pcr_bit_t PCRB12_b; + stc_gpio_pfsr_bit_t PFSRB12_b; + stc_gpio_pcr_bit_t PCRB13_b; + stc_gpio_pfsr_bit_t PFSRB13_b; + stc_gpio_pcr_bit_t PCRB14_b; + stc_gpio_pfsr_bit_t PFSRB14_b; + stc_gpio_pcr_bit_t PCRB15_b; + stc_gpio_pfsr_bit_t PFSRB15_b; + stc_gpio_pcr_bit_t PCRC0_b; + stc_gpio_pfsr_bit_t PFSRC0_b; + stc_gpio_pcr_bit_t PCRC1_b; + stc_gpio_pfsr_bit_t PFSRC1_b; + stc_gpio_pcr_bit_t PCRC2_b; + stc_gpio_pfsr_bit_t PFSRC2_b; + stc_gpio_pcr_bit_t PCRC3_b; + stc_gpio_pfsr_bit_t PFSRC3_b; + stc_gpio_pcr_bit_t PCRC4_b; + stc_gpio_pfsr_bit_t PFSRC4_b; + stc_gpio_pcr_bit_t PCRC5_b; + stc_gpio_pfsr_bit_t PFSRC5_b; + stc_gpio_pcr_bit_t PCRC6_b; + stc_gpio_pfsr_bit_t PFSRC6_b; + stc_gpio_pcr_bit_t PCRC7_b; + stc_gpio_pfsr_bit_t PFSRC7_b; + stc_gpio_pcr_bit_t PCRC8_b; + stc_gpio_pfsr_bit_t PFSRC8_b; + stc_gpio_pcr_bit_t PCRC9_b; + stc_gpio_pfsr_bit_t PFSRC9_b; + stc_gpio_pcr_bit_t PCRC10_b; + stc_gpio_pfsr_bit_t PFSRC10_b; + stc_gpio_pcr_bit_t PCRC11_b; + stc_gpio_pfsr_bit_t PFSRC11_b; + stc_gpio_pcr_bit_t PCRC12_b; + stc_gpio_pfsr_bit_t PFSRC12_b; + stc_gpio_pcr_bit_t PCRC13_b; + stc_gpio_pfsr_bit_t PFSRC13_b; + stc_gpio_pcr_bit_t PCRC14_b; + stc_gpio_pfsr_bit_t PFSRC14_b; + stc_gpio_pcr_bit_t PCRC15_b; + stc_gpio_pfsr_bit_t PFSRC15_b; + stc_gpio_pcr_bit_t PCRD0_b; + stc_gpio_pfsr_bit_t PFSRD0_b; + stc_gpio_pcr_bit_t PCRD1_b; + stc_gpio_pfsr_bit_t PFSRD1_b; + stc_gpio_pcr_bit_t PCRD2_b; + stc_gpio_pfsr_bit_t PFSRD2_b; + stc_gpio_pcr_bit_t PCRD3_b; + stc_gpio_pfsr_bit_t PFSRD3_b; + stc_gpio_pcr_bit_t PCRD4_b; + stc_gpio_pfsr_bit_t PFSRD4_b; + stc_gpio_pcr_bit_t PCRD5_b; + stc_gpio_pfsr_bit_t PFSRD5_b; + stc_gpio_pcr_bit_t PCRD6_b; + stc_gpio_pfsr_bit_t PFSRD6_b; + stc_gpio_pcr_bit_t PCRD7_b; + stc_gpio_pfsr_bit_t PFSRD7_b; + stc_gpio_pcr_bit_t PCRD8_b; + stc_gpio_pfsr_bit_t PFSRD8_b; + stc_gpio_pcr_bit_t PCRD9_b; + stc_gpio_pfsr_bit_t PFSRD9_b; + stc_gpio_pcr_bit_t PCRD10_b; + stc_gpio_pfsr_bit_t PFSRD10_b; + stc_gpio_pcr_bit_t PCRD11_b; + stc_gpio_pfsr_bit_t PFSRD11_b; + stc_gpio_pcr_bit_t PCRD12_b; + stc_gpio_pfsr_bit_t PFSRD12_b; + stc_gpio_pcr_bit_t PCRD13_b; + stc_gpio_pfsr_bit_t PFSRD13_b; + stc_gpio_pcr_bit_t PCRD14_b; + stc_gpio_pfsr_bit_t PFSRD14_b; + stc_gpio_pcr_bit_t PCRD15_b; + stc_gpio_pfsr_bit_t PFSRD15_b; + stc_gpio_pcr_bit_t PCRE0_b; + stc_gpio_pfsr_bit_t PFSRE0_b; + stc_gpio_pcr_bit_t PCRE1_b; + stc_gpio_pfsr_bit_t PFSRE1_b; + stc_gpio_pcr_bit_t PCRE2_b; + stc_gpio_pfsr_bit_t PFSRE2_b; + stc_gpio_pcr_bit_t PCRE3_b; + stc_gpio_pfsr_bit_t PFSRE3_b; + stc_gpio_pcr_bit_t PCRE4_b; + stc_gpio_pfsr_bit_t PFSRE4_b; + stc_gpio_pcr_bit_t PCRE5_b; + stc_gpio_pfsr_bit_t PFSRE5_b; + stc_gpio_pcr_bit_t PCRE6_b; + stc_gpio_pfsr_bit_t PFSRE6_b; + stc_gpio_pcr_bit_t PCRE7_b; + stc_gpio_pfsr_bit_t PFSRE7_b; + stc_gpio_pcr_bit_t PCRE8_b; + stc_gpio_pfsr_bit_t PFSRE8_b; + stc_gpio_pcr_bit_t PCRE9_b; + stc_gpio_pfsr_bit_t PFSRE9_b; + stc_gpio_pcr_bit_t PCRE10_b; + stc_gpio_pfsr_bit_t PFSRE10_b; + stc_gpio_pcr_bit_t PCRE11_b; + stc_gpio_pfsr_bit_t PFSRE11_b; + stc_gpio_pcr_bit_t PCRE12_b; + stc_gpio_pfsr_bit_t PFSRE12_b; + stc_gpio_pcr_bit_t PCRE13_b; + stc_gpio_pfsr_bit_t PFSRE13_b; + stc_gpio_pcr_bit_t PCRE14_b; + stc_gpio_pfsr_bit_t PFSRE14_b; + stc_gpio_pcr_bit_t PCRE15_b; + stc_gpio_pfsr_bit_t PFSRE15_b; + stc_gpio_pcr_bit_t PCRH0_b; + stc_gpio_pfsr_bit_t PFSRH0_b; + stc_gpio_pcr_bit_t PCRH1_b; + stc_gpio_pfsr_bit_t PFSRH1_b; + stc_gpio_pcr_bit_t PCRH2_b; + stc_gpio_pfsr_bit_t PFSRH2_b; +} bCM_GPIO_TypeDef; + +typedef struct { + stc_hash_cr_bit_t CR_b; +} bCM_HASH_TypeDef; + +typedef struct { + stc_i2c_cr1_bit_t CR1_b; + stc_i2c_cr2_bit_t CR2_b; + stc_i2c_cr3_bit_t CR3_b; + stc_i2c_cr4_bit_t CR4_b; + stc_i2c_slr0_bit_t SLR0_b; + stc_i2c_slr1_bit_t SLR1_b; + uint32_t RESERVED0[32]; + stc_i2c_sr_bit_t SR_b; + stc_i2c_clr_bit_t CLR_b; + uint32_t RESERVED1[96]; + stc_i2c_fltr_bit_t FLTR_b; +} bCM_I2C_TypeDef; + +typedef struct { + stc_i2s_ctrl_bit_t CTRL_b; + stc_i2s_sr_bit_t SR_b; + stc_i2s_er_bit_t ER_b; + stc_i2s_cfgr_bit_t CFGR_b; +} bCM_I2S_TypeDef; + +typedef struct { + stc_icg_icg0_bit_t ICG0_b; + stc_icg_icg1_bit_t ICG1_b; +} bCM_ICG_TypeDef; + +typedef struct { + stc_intc_nmicr_bit_t NMICR_b; + stc_intc_nmienr_bit_t NMIENR_b; + stc_intc_nmifr_bit_t NMIFR_b; + stc_intc_nmicfr_bit_t NMICFR_b; + stc_intc_eirqcr_bit_t EIRQCR0_b; + stc_intc_eirqcr_bit_t EIRQCR1_b; + stc_intc_eirqcr_bit_t EIRQCR2_b; + stc_intc_eirqcr_bit_t EIRQCR3_b; + stc_intc_eirqcr_bit_t EIRQCR4_b; + stc_intc_eirqcr_bit_t EIRQCR5_b; + stc_intc_eirqcr_bit_t EIRQCR6_b; + stc_intc_eirqcr_bit_t EIRQCR7_b; + stc_intc_eirqcr_bit_t EIRQCR8_b; + stc_intc_eirqcr_bit_t EIRQCR9_b; + stc_intc_eirqcr_bit_t EIRQCR10_b; + stc_intc_eirqcr_bit_t EIRQCR11_b; + stc_intc_eirqcr_bit_t EIRQCR12_b; + stc_intc_eirqcr_bit_t EIRQCR13_b; + stc_intc_eirqcr_bit_t EIRQCR14_b; + stc_intc_eirqcr_bit_t EIRQCR15_b; + stc_intc_wupen_bit_t WUPEN_b; + stc_intc_eifr_bit_t EIFR_b; + stc_intc_eifcr_bit_t EIFCR_b; + uint32_t RESERVED0[4096]; + stc_intc_vssel_bit_t VSSEL128_b; + stc_intc_vssel_bit_t VSSEL129_b; + stc_intc_vssel_bit_t VSSEL130_b; + stc_intc_vssel_bit_t VSSEL131_b; + stc_intc_vssel_bit_t VSSEL132_b; + stc_intc_vssel_bit_t VSSEL133_b; + stc_intc_vssel_bit_t VSSEL134_b; + stc_intc_vssel_bit_t VSSEL135_b; + stc_intc_vssel_bit_t VSSEL136_b; + stc_intc_vssel_bit_t VSSEL137_b; + stc_intc_vssel_bit_t VSSEL138_b; + stc_intc_vssel_bit_t VSSEL139_b; + stc_intc_vssel_bit_t VSSEL140_b; + stc_intc_vssel_bit_t VSSEL141_b; + stc_intc_vssel_bit_t VSSEL142_b; + stc_intc_vssel_bit_t VSSEL143_b; + stc_intc_swier_bit_t SWIER_b; + stc_intc_evter_bit_t EVTER_b; + stc_intc_ier_bit_t IER_b; +} bCM_INTC_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_keyscan_ser_bit_t SER_b; +} bCM_KEYSCAN_TypeDef; + +typedef struct { + uint32_t RESERVED0[512]; + stc_mpu_rgcr_bit_t RGCR0_b; + stc_mpu_rgcr_bit_t RGCR1_b; + stc_mpu_rgcr_bit_t RGCR2_b; + stc_mpu_rgcr_bit_t RGCR3_b; + stc_mpu_rgcr_bit_t RGCR4_b; + stc_mpu_rgcr_bit_t RGCR5_b; + stc_mpu_rgcr_bit_t RGCR6_b; + stc_mpu_rgcr_bit_t RGCR7_b; + stc_mpu_rgcr_bit_t RGCR8_b; + stc_mpu_rgcr_bit_t RGCR9_b; + stc_mpu_rgcr_bit_t RGCR10_b; + stc_mpu_rgcr_bit_t RGCR11_b; + stc_mpu_rgcr_bit_t RGCR12_b; + stc_mpu_rgcr_bit_t RGCR13_b; + stc_mpu_rgcr_bit_t RGCR14_b; + stc_mpu_rgcr_bit_t RGCR15_b; + stc_mpu_cr_bit_t CR_b; + stc_mpu_sr_bit_t SR_b; + stc_mpu_eclr_bit_t ECLR_b; + stc_mpu_wp_bit_t WP_b; + uint32_t RESERVED1[130144]; + stc_mpu_ippr_bit_t IPPR_b; +} bCM_MPU_TypeDef; + +typedef struct { + stc_ots_ctl_bit_t CTL_b; +} bCM_OTS_TypeDef; + +typedef struct { + stc_peric_usbfs_syctlreg_bit_t USBFS_SYCTLREG_b; + stc_peric_sdioc_syctlreg_bit_t SDIOC_SYCTLREG_b; +} bCM_PERIC_TypeDef; + +typedef struct { + stc_qspi_cr_bit_t CR_b; + uint32_t RESERVED0[32]; + stc_qspi_fcr_bit_t FCR_b; + stc_qspi_sr_bit_t SR_b; + uint32_t RESERVED1[160]; + stc_qspi_sr2_bit_t SR2_b; +} bCM_QSPI_TypeDef; + +typedef struct { + stc_rmu_rstf0_bit_t RSTF0_b; +} bCM_RMU_TypeDef; + +typedef struct { + stc_rtc_cr0_bit_t CR0_b; + uint32_t RESERVED0[24]; + stc_rtc_cr1_bit_t CR1_b; + uint32_t RESERVED1[24]; + stc_rtc_cr2_bit_t CR2_b; + uint32_t RESERVED2[24]; + stc_rtc_cr3_bit_t CR3_b; + uint32_t RESERVED3[344]; + stc_rtc_errcrh_bit_t ERRCRH_b; +} bCM_RTC_TypeDef; + +typedef struct { + uint32_t RESERVED0[96]; + stc_sdioc_transmode_bit_t TRANSMODE_b; + stc_sdioc_cmd_bit_t CMD_b; + uint32_t RESERVED1[160]; + stc_sdioc_pstat_bit_t PSTAT_b; + stc_sdioc_hostcon_bit_t HOSTCON_b; + stc_sdioc_pwrcon_bit_t PWRCON_b; + stc_sdioc_blkgpcon_bit_t BLKGPCON_b; + uint32_t RESERVED2[8]; + stc_sdioc_clkcon_bit_t CLKCON_b; + uint32_t RESERVED3[8]; + stc_sdioc_sftrst_bit_t SFTRST_b; + stc_sdioc_norintst_bit_t NORINTST_b; + stc_sdioc_errintst_bit_t ERRINTST_b; + stc_sdioc_norintsten_bit_t NORINTSTEN_b; + stc_sdioc_errintsten_bit_t ERRINTSTEN_b; + stc_sdioc_norintsgen_bit_t NORINTSGEN_b; + stc_sdioc_errintsgen_bit_t ERRINTSGEN_b; + stc_sdioc_atcerrst_bit_t ATCERRST_b; + uint32_t RESERVED4[144]; + stc_sdioc_fea_bit_t FEA_b; + stc_sdioc_fee_bit_t FEE_b; +} bCM_SDIOC_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_spi_cr1_bit_t CR1_b; + uint32_t RESERVED1[32]; + stc_spi_cfg1_bit_t CFG1_b; + uint32_t RESERVED2[32]; + stc_spi_sr_bit_t SR_b; + stc_spi_cfg2_bit_t CFG2_b; +} bCM_SPI_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_sramc_wtpr_bit_t WTPR_b; + stc_sramc_ckcr_bit_t CKCR_b; + stc_sramc_ckpr_bit_t CKPR_b; + stc_sramc_cksr_bit_t CKSR_b; +} bCM_SRAMC_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_swdt_sr_bit_t SR_b; +} bCM_SWDT_TypeDef; + +typedef struct { + uint32_t RESERVED0[128]; + stc_tmr0_bconr_bit_t BCONR_b; + stc_tmr0_stflr_bit_t STFLR_b; +} bCM_TMR0_TypeDef; + +typedef struct { + uint32_t RESERVED0[192]; + stc_tmr4_ocsr_bit_t OCSRU_b; + stc_tmr4_ocer_bit_t OCERU_b; + stc_tmr4_ocsr_bit_t OCSRV_b; + stc_tmr4_ocer_bit_t OCERV_b; + stc_tmr4_ocsr_bit_t OCSRW_b; + stc_tmr4_ocer_bit_t OCERW_b; + stc_tmr4_ocmrh_bit_t OCMRHUH_b; + uint32_t RESERVED1[16]; + stc_tmr4_ocmrl_bit_t OCMRLUL_b; + stc_tmr4_ocmrh_bit_t OCMRHVH_b; + uint32_t RESERVED2[16]; + stc_tmr4_ocmrl_bit_t OCMRLVL_b; + stc_tmr4_ocmrh_bit_t OCMRHWH_b; + uint32_t RESERVED3[16]; + stc_tmr4_ocmrl_bit_t OCMRLWL_b; + uint32_t RESERVED4[96]; + stc_tmr4_ccsr_bit_t CCSR_b; + uint32_t RESERVED5[720]; + stc_tmr4_rcsr_bit_t RCSR_b; + uint32_t RESERVED6[272]; + stc_tmr4_scsr_bit_t SCSRUH_b; + stc_tmr4_scmr_bit_t SCMRUH_b; + stc_tmr4_scsr_bit_t SCSRUL_b; + stc_tmr4_scmr_bit_t SCMRUL_b; + stc_tmr4_scsr_bit_t SCSRVH_b; + stc_tmr4_scmr_bit_t SCMRVH_b; + stc_tmr4_scsr_bit_t SCSRVL_b; + stc_tmr4_scmr_bit_t SCMRVL_b; + stc_tmr4_scsr_bit_t SCSRWH_b; + stc_tmr4_scmr_bit_t SCMRWH_b; + stc_tmr4_scsr_bit_t SCSRWL_b; + stc_tmr4_scmr_bit_t SCMRWL_b; + uint32_t RESERVED7[128]; + stc_tmr4_ecsr_bit_t ECSR_b; +} bCM_TMR4_TypeDef; + +typedef struct { + uint32_t RESERVED0[640]; + stc_tmr6_gconr_bit_t GCONR_b; + stc_tmr6_iconr_bit_t ICONR_b; + stc_tmr6_pconr_bit_t PCONR_b; + stc_tmr6_bconr_bit_t BCONR_b; + stc_tmr6_dconr_bit_t DCONR_b; + uint32_t RESERVED1[32]; + stc_tmr6_fconr_bit_t FCONR_b; + stc_tmr6_vperr_bit_t VPERR_b; + stc_tmr6_stflr_bit_t STFLR_b; + stc_tmr6_hstar_bit_t HSTAR_b; + stc_tmr6_hstpr_bit_t HSTPR_b; + stc_tmr6_hclrr_bit_t HCLRR_b; + stc_tmr6_hcpar_bit_t HCPAR_b; + stc_tmr6_hcpbr_bit_t HCPBR_b; + stc_tmr6_hcupr_bit_t HCUPR_b; + stc_tmr6_hcdor_bit_t HCDOR_b; +} bCM_TMR6_TypeDef; + +typedef struct { + uint32_t RESERVED0[8096]; + stc_tmr6cr_sstar_bit_t SSTAR_b; + stc_tmr6cr_sstpr_bit_t SSTPR_b; + stc_tmr6cr_sclrr_bit_t SCLRR_b; +} bCM_TMR6CR_TypeDef; + +typedef struct { + uint32_t RESERVED0[1024]; + stc_tmra_bcstrl_bit_t BCSTRL_b; + stc_tmra_bcstrh_bit_t BCSTRH_b; + uint32_t RESERVED1[16]; + stc_tmra_hconr_bit_t HCONR_b; + uint32_t RESERVED2[16]; + stc_tmra_hcupr_bit_t HCUPR_b; + uint32_t RESERVED3[16]; + stc_tmra_hcdor_bit_t HCDOR_b; + uint32_t RESERVED4[16]; + stc_tmra_iconr_bit_t ICONR_b; + uint32_t RESERVED5[16]; + stc_tmra_econr_bit_t ECONR_b; + uint32_t RESERVED6[16]; + stc_tmra_fconr_bit_t FCONR_b; + uint32_t RESERVED7[16]; + stc_tmra_stflr_bit_t STFLR_b; + uint32_t RESERVED8[272]; + stc_tmra_bconr_bit_t BCONR1_b; + uint32_t RESERVED9[48]; + stc_tmra_bconr_bit_t BCONR2_b; + uint32_t RESERVED10[48]; + stc_tmra_bconr_bit_t BCONR3_b; + uint32_t RESERVED11[48]; + stc_tmra_bconr_bit_t BCONR4_b; + uint32_t RESERVED12[304]; + stc_tmra_cconr_bit_t CCONR1_b; + uint32_t RESERVED13[16]; + stc_tmra_cconr_bit_t CCONR2_b; + uint32_t RESERVED14[16]; + stc_tmra_cconr_bit_t CCONR3_b; + uint32_t RESERVED15[16]; + stc_tmra_cconr_bit_t CCONR4_b; + uint32_t RESERVED16[16]; + stc_tmra_cconr_bit_t CCONR5_b; + uint32_t RESERVED17[16]; + stc_tmra_cconr_bit_t CCONR6_b; + uint32_t RESERVED18[16]; + stc_tmra_cconr_bit_t CCONR7_b; + uint32_t RESERVED19[16]; + stc_tmra_cconr_bit_t CCONR8_b; + uint32_t RESERVED20[272]; + stc_tmra_pconr_bit_t PCONR1_b; + uint32_t RESERVED21[16]; + stc_tmra_pconr_bit_t PCONR2_b; + uint32_t RESERVED22[16]; + stc_tmra_pconr_bit_t PCONR3_b; + uint32_t RESERVED23[16]; + stc_tmra_pconr_bit_t PCONR4_b; + uint32_t RESERVED24[16]; + stc_tmra_pconr_bit_t PCONR5_b; + uint32_t RESERVED25[16]; + stc_tmra_pconr_bit_t PCONR6_b; + uint32_t RESERVED26[16]; + stc_tmra_pconr_bit_t PCONR7_b; + uint32_t RESERVED27[16]; + stc_tmra_pconr_bit_t PCONR8_b; +} bCM_TMRA_TypeDef; + +typedef struct { + stc_trng_cr_bit_t CR_b; + stc_trng_mr_bit_t MR_b; +} bCM_TRNG_TypeDef; + +typedef struct { + stc_usart_sr_bit_t SR_b; + stc_usart_tdr_bit_t TDR_b; + uint32_t RESERVED0[48]; + stc_usart_cr1_bit_t CR1_b; + stc_usart_cr2_bit_t CR2_b; + stc_usart_cr3_bit_t CR3_b; +} bCM_USART_TypeDef; + +typedef struct { + stc_usbfs_gvbuscfg_bit_t GVBUSCFG_b; + uint32_t RESERVED0[32]; + stc_usbfs_gahbcfg_bit_t GAHBCFG_b; + stc_usbfs_gusbcfg_bit_t GUSBCFG_b; + stc_usbfs_grstctl_bit_t GRSTCTL_b; + stc_usbfs_gintsts_bit_t GINTSTS_b; + stc_usbfs_gintmsk_bit_t GINTMSK_b; + uint32_t RESERVED1[7968]; + stc_usbfs_hcfg_bit_t HCFG_b; + uint32_t RESERVED2[480]; + stc_usbfs_hprt_bit_t HPRT_b; + uint32_t RESERVED3[1504]; + stc_usbfs_hcchar_bit_t HCCHAR0_b; + uint32_t RESERVED4[32]; + stc_usbfs_hcint_bit_t HCINT0_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK0_b; + uint32_t RESERVED5[128]; + stc_usbfs_hcchar_bit_t HCCHAR1_b; + uint32_t RESERVED6[32]; + stc_usbfs_hcint_bit_t HCINT1_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK1_b; + uint32_t RESERVED7[128]; + stc_usbfs_hcchar_bit_t HCCHAR2_b; + uint32_t RESERVED8[32]; + stc_usbfs_hcint_bit_t HCINT2_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK2_b; + uint32_t RESERVED9[128]; + stc_usbfs_hcchar_bit_t HCCHAR3_b; + uint32_t RESERVED10[32]; + stc_usbfs_hcint_bit_t HCINT3_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK3_b; + uint32_t RESERVED11[128]; + stc_usbfs_hcchar_bit_t HCCHAR4_b; + uint32_t RESERVED12[32]; + stc_usbfs_hcint_bit_t HCINT4_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK4_b; + uint32_t RESERVED13[128]; + stc_usbfs_hcchar_bit_t HCCHAR5_b; + uint32_t RESERVED14[32]; + stc_usbfs_hcint_bit_t HCINT5_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK5_b; + uint32_t RESERVED15[128]; + stc_usbfs_hcchar_bit_t HCCHAR6_b; + uint32_t RESERVED16[32]; + stc_usbfs_hcint_bit_t HCINT6_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK6_b; + uint32_t RESERVED17[128]; + stc_usbfs_hcchar_bit_t HCCHAR7_b; + uint32_t RESERVED18[32]; + stc_usbfs_hcint_bit_t HCINT7_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK7_b; + uint32_t RESERVED19[128]; + stc_usbfs_hcchar_bit_t HCCHAR8_b; + uint32_t RESERVED20[32]; + stc_usbfs_hcint_bit_t HCINT8_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK8_b; + uint32_t RESERVED21[128]; + stc_usbfs_hcchar_bit_t HCCHAR9_b; + uint32_t RESERVED22[32]; + stc_usbfs_hcint_bit_t HCINT9_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK9_b; + uint32_t RESERVED23[128]; + stc_usbfs_hcchar_bit_t HCCHAR10_b; + uint32_t RESERVED24[32]; + stc_usbfs_hcint_bit_t HCINT10_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK10_b; + uint32_t RESERVED25[128]; + stc_usbfs_hcchar_bit_t HCCHAR11_b; + uint32_t RESERVED26[32]; + stc_usbfs_hcint_bit_t HCINT11_b; + stc_usbfs_hcintmsk_bit_t HCINTMSK11_b; + uint32_t RESERVED27[3200]; + stc_usbfs_dcfg_bit_t DCFG_b; + stc_usbfs_dctl_bit_t DCTL_b; + stc_usbfs_dsts_bit_t DSTS_b; + uint32_t RESERVED28[32]; + stc_usbfs_diepmsk_bit_t DIEPMSK_b; + stc_usbfs_doepmsk_bit_t DOEPMSK_b; + uint32_t RESERVED29[1856]; + stc_usbfs_diepctl0_bit_t DIEPCTL0_b; + uint32_t RESERVED30[32]; + stc_usbfs_diepint_bit_t DIEPINT0_b; + uint32_t RESERVED31[160]; + stc_usbfs_diepctl_bit_t DIEPCTL1_b; + uint32_t RESERVED32[32]; + stc_usbfs_diepint_bit_t DIEPINT1_b; + uint32_t RESERVED33[160]; + stc_usbfs_diepctl_bit_t DIEPCTL2_b; + uint32_t RESERVED34[32]; + stc_usbfs_diepint_bit_t DIEPINT2_b; + uint32_t RESERVED35[160]; + stc_usbfs_diepctl_bit_t DIEPCTL3_b; + uint32_t RESERVED36[32]; + stc_usbfs_diepint_bit_t DIEPINT3_b; + uint32_t RESERVED37[160]; + stc_usbfs_diepctl_bit_t DIEPCTL4_b; + uint32_t RESERVED38[32]; + stc_usbfs_diepint_bit_t DIEPINT4_b; + uint32_t RESERVED39[160]; + stc_usbfs_diepctl_bit_t DIEPCTL5_b; + uint32_t RESERVED40[32]; + stc_usbfs_diepint_bit_t DIEPINT5_b; + uint32_t RESERVED41[2720]; + stc_usbfs_doepctl0_bit_t DOEPCTL0_b; + uint32_t RESERVED42[32]; + stc_usbfs_doepint_bit_t DOEPINT0_b; + uint32_t RESERVED43[32]; + stc_usbfs_doeptsiz0_bit_t DOEPTSIZ0_b; + uint32_t RESERVED44[96]; + stc_usbfs_doepctl_bit_t DOEPCTL1_b; + uint32_t RESERVED45[32]; + stc_usbfs_doepint_bit_t DOEPINT1_b; + uint32_t RESERVED46[160]; + stc_usbfs_doepctl_bit_t DOEPCTL2_b; + uint32_t RESERVED47[32]; + stc_usbfs_doepint_bit_t DOEPINT2_b; + uint32_t RESERVED48[160]; + stc_usbfs_doepctl_bit_t DOEPCTL3_b; + uint32_t RESERVED49[32]; + stc_usbfs_doepint_bit_t DOEPINT3_b; + uint32_t RESERVED50[160]; + stc_usbfs_doepctl_bit_t DOEPCTL4_b; + uint32_t RESERVED51[32]; + stc_usbfs_doepint_bit_t DOEPINT4_b; + uint32_t RESERVED52[160]; + stc_usbfs_doepctl_bit_t DOEPCTL5_b; + uint32_t RESERVED53[32]; + stc_usbfs_doepint_bit_t DOEPINT5_b; + uint32_t RESERVED54[4768]; + stc_usbfs_gcctl_bit_t GCCTL_b; +} bCM_USBFS_TypeDef; + +typedef struct { + stc_wdt_cr_bit_t CR_b; + stc_wdt_sr_bit_t SR_b; +} bCM_WDT_TypeDef; + + +/******************************************************************************/ +/* Device Specific Peripheral bit_band declaration & memory map */ +/******************************************************************************/ +#define bCM_ADC1 ((bCM_ADC_TypeDef *)0x42800000UL) +#define bCM_ADC2 ((bCM_ADC_TypeDef *)0x42808000UL) +#define bCM_AES ((bCM_AES_TypeDef *)0x42100000UL) +#define bCM_AOS ((bCM_AOS_TypeDef *)0x42210000UL) +#define bCM_CAN ((bCM_CAN_TypeDef *)0x42E08000UL) +#define bCM_CMP1 ((bCM_CMP_TypeDef *)0x42940000UL) +#define bCM_CMP2 ((bCM_CMP_TypeDef *)0x42940200UL) +#define bCM_CMP3 ((bCM_CMP_TypeDef *)0x42940400UL) +#define bCM_CMPCR ((bCM_CMPCR_TypeDef *)0x42940000UL) +#define bCM_CMU ((bCM_CMU_TypeDef *)0x42A80000UL) +#define bCM_CRC ((bCM_CRC_TypeDef *)0x42118000UL) +#define bCM_DCU1 ((bCM_DCU_TypeDef *)0x42A40000UL) +#define bCM_DCU2 ((bCM_DCU_TypeDef *)0x42A48000UL) +#define bCM_DCU3 ((bCM_DCU_TypeDef *)0x42A50000UL) +#define bCM_DCU4 ((bCM_DCU_TypeDef *)0x42A58000UL) +#define bCM_DMA1 ((bCM_DMA_TypeDef *)0x42A60000UL) +#define bCM_DMA2 ((bCM_DMA_TypeDef *)0x42A68000UL) +#define bCM_EFM ((bCM_EFM_TypeDef *)0x42208000UL) +#define bCM_EMB0 ((bCM_EMB_TypeDef *)0x422F8000UL) +#define bCM_EMB1 ((bCM_EMB_TypeDef *)0x422F8400UL) +#define bCM_EMB2 ((bCM_EMB_TypeDef *)0x422F8800UL) +#define bCM_EMB3 ((bCM_EMB_TypeDef *)0x422F8C00UL) +#define bCM_FCM ((bCM_FCM_TypeDef *)0x42908000UL) +#define bCM_GPIO ((bCM_GPIO_TypeDef *)0x42A70000UL) +#define bCM_HASH ((bCM_HASH_TypeDef *)0x42108000UL) +#define bCM_I2C1 ((bCM_I2C_TypeDef *)0x429C0000UL) +#define bCM_I2C2 ((bCM_I2C_TypeDef *)0x429C8000UL) +#define bCM_I2C3 ((bCM_I2C_TypeDef *)0x429D0000UL) +#define bCM_I2S1 ((bCM_I2S_TypeDef *)0x423C0000UL) +#define bCM_I2S2 ((bCM_I2S_TypeDef *)0x423C8000UL) +#define bCM_I2S3 ((bCM_I2S_TypeDef *)0x42440000UL) +#define bCM_I2S4 ((bCM_I2S_TypeDef *)0x42448000UL) +#define bCM_INTC ((bCM_INTC_TypeDef *)0x42A20000UL) +#define bCM_KEYSCAN ((bCM_KEYSCAN_TypeDef *)0x42A18000UL) +#define bCM_MPU ((bCM_MPU_TypeDef *)0x42A00000UL) +#define bCM_OTS ((bCM_OTS_TypeDef *)0x42948000UL) +#define bCM_PERIC ((bCM_PERIC_TypeDef *)0x42AA8000UL) +#define bCM_PWC ((bCM_PWC_TypeDef *)0x42900000UL) +#define bCM_RMU ((bCM_RMU_TypeDef *)0x42A81800UL) +#define bCM_RTC ((bCM_RTC_TypeDef *)0x42980000UL) +#define bCM_SDIOC1 ((bCM_SDIOC_TypeDef *)0x42DF8000UL) +#define bCM_SDIOC2 ((bCM_SDIOC_TypeDef *)0x42E00000UL) +#define bCM_SPI1 ((bCM_SPI_TypeDef *)0x42380000UL) +#define bCM_SPI2 ((bCM_SPI_TypeDef *)0x42388000UL) +#define bCM_SPI3 ((bCM_SPI_TypeDef *)0x42400000UL) +#define bCM_SPI4 ((bCM_SPI_TypeDef *)0x42408000UL) +#define bCM_SRAMC ((bCM_SRAMC_TypeDef *)0x42A10000UL) +#define bCM_SWDT ((bCM_SWDT_TypeDef *)0x42928000UL) +#define bCM_TMR0_1 ((bCM_TMR0_TypeDef *)0x42480000UL) +#define bCM_TMR0_2 ((bCM_TMR0_TypeDef *)0x42488000UL) +#define bCM_TMR4_1 ((bCM_TMR4_TypeDef *)0x422E0000UL) +#define bCM_TMR4_2 ((bCM_TMR4_TypeDef *)0x42490000UL) +#define bCM_TMR4_3 ((bCM_TMR4_TypeDef *)0x42498000UL) +#define bCM_TMR4CR ((bCM_TMR4CR_TypeDef *)0x42AA8100UL) +#define bCM_TMR6_1 ((bCM_TMR6_TypeDef *)0x42300000UL) +#define bCM_TMR6_2 ((bCM_TMR6_TypeDef *)0x42308000UL) +#define bCM_TMR6_3 ((bCM_TMR6_TypeDef *)0x42310000UL) +#define bCM_TMR6CR ((bCM_TMR6CR_TypeDef *)0x42300000UL) +#define bCM_TMRA_1 ((bCM_TMRA_TypeDef *)0x422A0000UL) +#define bCM_TMRA_2 ((bCM_TMRA_TypeDef *)0x422A8000UL) +#define bCM_TMRA_3 ((bCM_TMRA_TypeDef *)0x422B0000UL) +#define bCM_TMRA_4 ((bCM_TMRA_TypeDef *)0x422B8000UL) +#define bCM_TMRA_5 ((bCM_TMRA_TypeDef *)0x422C0000UL) +#define bCM_TMRA_6 ((bCM_TMRA_TypeDef *)0x422C8000UL) +#define bCM_TRNG ((bCM_TRNG_TypeDef *)0x42820000UL) +#define bCM_USART1 ((bCM_USART_TypeDef *)0x423A0000UL) +#define bCM_USART2 ((bCM_USART_TypeDef *)0x423A8000UL) +#define bCM_USART3 ((bCM_USART_TypeDef *)0x42420000UL) +#define bCM_USART4 ((bCM_USART_TypeDef *)0x42428000UL) +#define bCM_USBFS ((bCM_USBFS_TypeDef *)0x43800000UL) +#define bCM_WDT ((bCM_WDT_TypeDef *)0x42920000UL) + + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_H__ */ diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Include/hc32f4xx.h b/mcu/cmsis/Device/HDSC/hc32f4xx/Include/hc32f4xx.h new file mode 100644 index 0000000..41bb08f --- /dev/null +++ b/mcu/cmsis/Device/HDSC/hc32f4xx/Include/hc32f4xx.h @@ -0,0 +1,66 @@ +/** + ******************************************************************************* + * @file hc32f4xx.h + * @brief This file contains the common part of the HC32 series. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4XX_H__ +#define __HC32F4XX_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +/** + * @brief HC32F4xx Device Include + */ +#if defined(HC32F460) +#include "hc32f460.h" +#include "system_hc32f460.h" +#else +#error "Please select first the target HC32xxxx device used in your application (in hc32xxxx.h file)" +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4XX_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Include/system_hc32f460.h b/mcu/cmsis/Device/HDSC/hc32f4xx/Include/system_hc32f460.h new file mode 100644 index 0000000..b8de595 --- /dev/null +++ b/mcu/cmsis/Device/HDSC/hc32f4xx/Include/system_hc32f460.h @@ -0,0 +1,140 @@ +/** + ******************************************************************************* + * @file system_hc32f460.h + * @brief This file contains all the functions prototypes of the HC32 System. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __SYSTEM_HC32F460_H__ +#define __SYSTEM_HC32F460_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup CMSIS + * @{ + */ + +/** + * @addtogroup HC32F460_System + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ +/** + * @addtogroup HC32F460_System_Global_Macros + * @{ + */ + +/** + * @addtogroup HC32F460_System_Clock_Source + * @{ + */ +#if !defined (MRC_VALUE) +#define MRC_VALUE (8000000UL) /*!< Internal middle speed RC freq. */ +#endif + +#if !defined (LRC_VALUE) +#define LRC_VALUE (32768UL) /*!< Internal low speed RC freq. */ +#endif + +#if !defined (SWDTLRC_VALUE) +#define SWDTLRC_VALUE (10000UL) /*!< Internal SWDT low speed RC freq. */ +#endif + +#if !defined (XTAL_VALUE) +#define XTAL_VALUE (8000000UL) /*!< External high speed OSC freq. */ +#endif + +#if !defined (XTAL32_VALUE) +#define XTAL32_VALUE (32768UL) /*!< External low speed OSC freq. */ +#endif + +#if !defined (HCLK_VALUE) +#define HCLK_VALUE (SystemCoreClock >> ((CM_CMU->SCFGR & CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS)) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +/** + * @addtogroup HC32F460_System_Exported_Variable + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System clock frequency (Core clock) */ +extern uint32_t HRC_VALUE; /*!< HRC frequency */ + +/** + * @} + */ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup HC32F460_System_Global_Functions + * @{ + */ + +extern void SystemInit(void); /*!< Initialize the system */ +extern void SystemCoreClockUpdate(void); /*!< Update SystemCoreClock variable */ + +#if defined (ROM_EXT_QSPI) +void SystemInit_QspiMem(void); +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_HC32F460_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F460_256K.FLM b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F460_256K.FLM new file mode 100644 index 0000000..cba0cea Binary files /dev/null and b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F460_256K.FLM differ diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F460_512K.FLM b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F460_512K.FLM new file mode 100644 index 0000000..1753fa4 Binary files /dev/null and b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F460_512K.FLM differ diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F460_RAM.FLM b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F460_RAM.FLM new file mode 100644 index 0000000..aa6fda2 Binary files /dev/null and b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F460_RAM.FLM differ diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F460_otp.FLM b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F460_otp.FLM new file mode 100644 index 0000000..7ec0d95 Binary files /dev/null and b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F460_otp.FLM differ diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/ram.ini b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/ram.ini new file mode 100644 index 0000000..58dccf9 --- /dev/null +++ b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/ram.ini @@ -0,0 +1,16 @@ +FUNC void Setup (void) { + + SP = _RDWORD(0x1FFE0000); + + PC = _RDWORD(0x1FFE0004); + + _WDWORD(0xE000ED08, 0x1FFE0000); + +} + + +LOAD .\output\release\efm_chip_erase.axf INCREMENTAL + +Setup(); + +g, main diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HC32F460.SFR b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HC32F460.SFR new file mode 100644 index 0000000..7408ef2 Binary files /dev/null and b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HC32F460.SFR differ diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f460.s b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f460.s new file mode 100644 index 0000000..748fefc --- /dev/null +++ b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f460.s @@ -0,0 +1,618 @@ +;/** +; ****************************************************************************** +; @file startup_hc32f460.s +; @brief Startup for MDK. +; verbatim +; Change Logs: +; Date Author Notes +; 2022-03-31 CDT First version +; endverbatim +; ***************************************************************************** +; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; ****************************************************************************** +; */ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Heap_Size EQU 0x00002000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Peripheral Interrupts + DCD IRQ000_Handler + DCD IRQ001_Handler + DCD IRQ002_Handler + DCD IRQ003_Handler + DCD IRQ004_Handler + DCD IRQ005_Handler + DCD IRQ006_Handler + DCD IRQ007_Handler + DCD IRQ008_Handler + DCD IRQ009_Handler + DCD IRQ010_Handler + DCD IRQ011_Handler + DCD IRQ012_Handler + DCD IRQ013_Handler + DCD IRQ014_Handler + DCD IRQ015_Handler + DCD IRQ016_Handler + DCD IRQ017_Handler + DCD IRQ018_Handler + DCD IRQ019_Handler + DCD IRQ020_Handler + DCD IRQ021_Handler + DCD IRQ022_Handler + DCD IRQ023_Handler + DCD IRQ024_Handler + DCD IRQ025_Handler + DCD IRQ026_Handler + DCD IRQ027_Handler + DCD IRQ028_Handler + DCD IRQ029_Handler + DCD IRQ030_Handler + DCD IRQ031_Handler + DCD IRQ032_Handler + DCD IRQ033_Handler + DCD IRQ034_Handler + DCD IRQ035_Handler + DCD IRQ036_Handler + DCD IRQ037_Handler + DCD IRQ038_Handler + DCD IRQ039_Handler + DCD IRQ040_Handler + DCD IRQ041_Handler + DCD IRQ042_Handler + DCD IRQ043_Handler + DCD IRQ044_Handler + DCD IRQ045_Handler + DCD IRQ046_Handler + DCD IRQ047_Handler + DCD IRQ048_Handler + DCD IRQ049_Handler + DCD IRQ050_Handler + DCD IRQ051_Handler + DCD IRQ052_Handler + DCD IRQ053_Handler + DCD IRQ054_Handler + DCD IRQ055_Handler + DCD IRQ056_Handler + DCD IRQ057_Handler + DCD IRQ058_Handler + DCD IRQ059_Handler + DCD IRQ060_Handler + DCD IRQ061_Handler + DCD IRQ062_Handler + DCD IRQ063_Handler + DCD IRQ064_Handler + DCD IRQ065_Handler + DCD IRQ066_Handler + DCD IRQ067_Handler + DCD IRQ068_Handler + DCD IRQ069_Handler + DCD IRQ070_Handler + DCD IRQ071_Handler + DCD IRQ072_Handler + DCD IRQ073_Handler + DCD IRQ074_Handler + DCD IRQ075_Handler + DCD IRQ076_Handler + DCD IRQ077_Handler + DCD IRQ078_Handler + DCD IRQ079_Handler + DCD IRQ080_Handler + DCD IRQ081_Handler + DCD IRQ082_Handler + DCD IRQ083_Handler + DCD IRQ084_Handler + DCD IRQ085_Handler + DCD IRQ086_Handler + DCD IRQ087_Handler + DCD IRQ088_Handler + DCD IRQ089_Handler + DCD IRQ090_Handler + DCD IRQ091_Handler + DCD IRQ092_Handler + DCD IRQ093_Handler + DCD IRQ094_Handler + DCD IRQ095_Handler + DCD IRQ096_Handler + DCD IRQ097_Handler + DCD IRQ098_Handler + DCD IRQ099_Handler + DCD IRQ100_Handler + DCD IRQ101_Handler + DCD IRQ102_Handler + DCD IRQ103_Handler + DCD IRQ104_Handler + DCD IRQ105_Handler + DCD IRQ106_Handler + DCD IRQ107_Handler + DCD IRQ108_Handler + DCD IRQ109_Handler + DCD IRQ110_Handler + DCD IRQ111_Handler + DCD IRQ112_Handler + DCD IRQ113_Handler + DCD IRQ114_Handler + DCD IRQ115_Handler + DCD IRQ116_Handler + DCD IRQ117_Handler + DCD IRQ118_Handler + DCD IRQ119_Handler + DCD IRQ120_Handler + DCD IRQ121_Handler + DCD IRQ122_Handler + DCD IRQ123_Handler + DCD IRQ124_Handler + DCD IRQ125_Handler + DCD IRQ126_Handler + DCD IRQ127_Handler + DCD IRQ128_Handler + DCD IRQ129_Handler + DCD IRQ130_Handler + DCD IRQ131_Handler + DCD IRQ132_Handler + DCD IRQ133_Handler + DCD IRQ134_Handler + DCD IRQ135_Handler + DCD IRQ136_Handler + DCD IRQ137_Handler + DCD IRQ138_Handler + DCD IRQ139_Handler + DCD IRQ140_Handler + DCD IRQ141_Handler + DCD IRQ142_Handler + DCD IRQ143_Handler + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main +SET_SRAM3_WAIT + LDR R0, =0x40050804 + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x40050800 + MOV R1, #0x1100 + STR R1, [R0] + + LDR R0, =0x40050804 + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT IRQ000_Handler [WEAK] + EXPORT IRQ001_Handler [WEAK] + EXPORT IRQ002_Handler [WEAK] + EXPORT IRQ003_Handler [WEAK] + EXPORT IRQ004_Handler [WEAK] + EXPORT IRQ005_Handler [WEAK] + EXPORT IRQ006_Handler [WEAK] + EXPORT IRQ007_Handler [WEAK] + EXPORT IRQ008_Handler [WEAK] + EXPORT IRQ009_Handler [WEAK] + EXPORT IRQ010_Handler [WEAK] + EXPORT IRQ011_Handler [WEAK] + EXPORT IRQ012_Handler [WEAK] + EXPORT IRQ013_Handler [WEAK] + EXPORT IRQ014_Handler [WEAK] + EXPORT IRQ015_Handler [WEAK] + EXPORT IRQ016_Handler [WEAK] + EXPORT IRQ017_Handler [WEAK] + EXPORT IRQ018_Handler [WEAK] + EXPORT IRQ019_Handler [WEAK] + EXPORT IRQ020_Handler [WEAK] + EXPORT IRQ021_Handler [WEAK] + EXPORT IRQ022_Handler [WEAK] + EXPORT IRQ023_Handler [WEAK] + EXPORT IRQ024_Handler [WEAK] + EXPORT IRQ025_Handler [WEAK] + EXPORT IRQ026_Handler [WEAK] + EXPORT IRQ027_Handler [WEAK] + EXPORT IRQ028_Handler [WEAK] + EXPORT IRQ029_Handler [WEAK] + EXPORT IRQ030_Handler [WEAK] + EXPORT IRQ031_Handler [WEAK] + EXPORT IRQ032_Handler [WEAK] + EXPORT IRQ033_Handler [WEAK] + EXPORT IRQ034_Handler [WEAK] + EXPORT IRQ035_Handler [WEAK] + EXPORT IRQ036_Handler [WEAK] + EXPORT IRQ037_Handler [WEAK] + EXPORT IRQ038_Handler [WEAK] + EXPORT IRQ039_Handler [WEAK] + EXPORT IRQ040_Handler [WEAK] + EXPORT IRQ041_Handler [WEAK] + EXPORT IRQ042_Handler [WEAK] + EXPORT IRQ043_Handler [WEAK] + EXPORT IRQ044_Handler [WEAK] + EXPORT IRQ045_Handler [WEAK] + EXPORT IRQ046_Handler [WEAK] + EXPORT IRQ047_Handler [WEAK] + EXPORT IRQ048_Handler [WEAK] + EXPORT IRQ049_Handler [WEAK] + EXPORT IRQ050_Handler [WEAK] + EXPORT IRQ051_Handler [WEAK] + EXPORT IRQ052_Handler [WEAK] + EXPORT IRQ053_Handler [WEAK] + EXPORT IRQ054_Handler [WEAK] + EXPORT IRQ055_Handler [WEAK] + EXPORT IRQ056_Handler [WEAK] + EXPORT IRQ057_Handler [WEAK] + EXPORT IRQ058_Handler [WEAK] + EXPORT IRQ059_Handler [WEAK] + EXPORT IRQ060_Handler [WEAK] + EXPORT IRQ061_Handler [WEAK] + EXPORT IRQ062_Handler [WEAK] + EXPORT IRQ063_Handler [WEAK] + EXPORT IRQ064_Handler [WEAK] + EXPORT IRQ065_Handler [WEAK] + EXPORT IRQ066_Handler [WEAK] + EXPORT IRQ067_Handler [WEAK] + EXPORT IRQ068_Handler [WEAK] + EXPORT IRQ069_Handler [WEAK] + EXPORT IRQ070_Handler [WEAK] + EXPORT IRQ071_Handler [WEAK] + EXPORT IRQ072_Handler [WEAK] + EXPORT IRQ073_Handler [WEAK] + EXPORT IRQ074_Handler [WEAK] + EXPORT IRQ075_Handler [WEAK] + EXPORT IRQ076_Handler [WEAK] + EXPORT IRQ077_Handler [WEAK] + EXPORT IRQ078_Handler [WEAK] + EXPORT IRQ079_Handler [WEAK] + EXPORT IRQ080_Handler [WEAK] + EXPORT IRQ081_Handler [WEAK] + EXPORT IRQ082_Handler [WEAK] + EXPORT IRQ083_Handler [WEAK] + EXPORT IRQ084_Handler [WEAK] + EXPORT IRQ085_Handler [WEAK] + EXPORT IRQ086_Handler [WEAK] + EXPORT IRQ087_Handler [WEAK] + EXPORT IRQ088_Handler [WEAK] + EXPORT IRQ089_Handler [WEAK] + EXPORT IRQ090_Handler [WEAK] + EXPORT IRQ091_Handler [WEAK] + EXPORT IRQ092_Handler [WEAK] + EXPORT IRQ093_Handler [WEAK] + EXPORT IRQ094_Handler [WEAK] + EXPORT IRQ095_Handler [WEAK] + EXPORT IRQ096_Handler [WEAK] + EXPORT IRQ097_Handler [WEAK] + EXPORT IRQ098_Handler [WEAK] + EXPORT IRQ099_Handler [WEAK] + EXPORT IRQ100_Handler [WEAK] + EXPORT IRQ101_Handler [WEAK] + EXPORT IRQ102_Handler [WEAK] + EXPORT IRQ103_Handler [WEAK] + EXPORT IRQ104_Handler [WEAK] + EXPORT IRQ105_Handler [WEAK] + EXPORT IRQ106_Handler [WEAK] + EXPORT IRQ107_Handler [WEAK] + EXPORT IRQ108_Handler [WEAK] + EXPORT IRQ109_Handler [WEAK] + EXPORT IRQ110_Handler [WEAK] + EXPORT IRQ111_Handler [WEAK] + EXPORT IRQ112_Handler [WEAK] + EXPORT IRQ113_Handler [WEAK] + EXPORT IRQ114_Handler [WEAK] + EXPORT IRQ115_Handler [WEAK] + EXPORT IRQ116_Handler [WEAK] + EXPORT IRQ117_Handler [WEAK] + EXPORT IRQ118_Handler [WEAK] + EXPORT IRQ119_Handler [WEAK] + EXPORT IRQ120_Handler [WEAK] + EXPORT IRQ121_Handler [WEAK] + EXPORT IRQ122_Handler [WEAK] + EXPORT IRQ123_Handler [WEAK] + EXPORT IRQ124_Handler [WEAK] + EXPORT IRQ125_Handler [WEAK] + EXPORT IRQ126_Handler [WEAK] + EXPORT IRQ127_Handler [WEAK] + EXPORT IRQ128_Handler [WEAK] + EXPORT IRQ129_Handler [WEAK] + EXPORT IRQ130_Handler [WEAK] + EXPORT IRQ131_Handler [WEAK] + EXPORT IRQ132_Handler [WEAK] + EXPORT IRQ133_Handler [WEAK] + EXPORT IRQ134_Handler [WEAK] + EXPORT IRQ135_Handler [WEAK] + EXPORT IRQ136_Handler [WEAK] + EXPORT IRQ137_Handler [WEAK] + EXPORT IRQ138_Handler [WEAK] + EXPORT IRQ139_Handler [WEAK] + EXPORT IRQ140_Handler [WEAK] + EXPORT IRQ141_Handler [WEAK] + EXPORT IRQ142_Handler [WEAK] + EXPORT IRQ143_Handler [WEAK] + +IRQ000_Handler +IRQ001_Handler +IRQ002_Handler +IRQ003_Handler +IRQ004_Handler +IRQ005_Handler +IRQ006_Handler +IRQ007_Handler +IRQ008_Handler +IRQ009_Handler +IRQ010_Handler +IRQ011_Handler +IRQ012_Handler +IRQ013_Handler +IRQ014_Handler +IRQ015_Handler +IRQ016_Handler +IRQ017_Handler +IRQ018_Handler +IRQ019_Handler +IRQ020_Handler +IRQ021_Handler +IRQ022_Handler +IRQ023_Handler +IRQ024_Handler +IRQ025_Handler +IRQ026_Handler +IRQ027_Handler +IRQ028_Handler +IRQ029_Handler +IRQ030_Handler +IRQ031_Handler +IRQ032_Handler +IRQ033_Handler +IRQ034_Handler +IRQ035_Handler +IRQ036_Handler +IRQ037_Handler +IRQ038_Handler +IRQ039_Handler +IRQ040_Handler +IRQ041_Handler +IRQ042_Handler +IRQ043_Handler +IRQ044_Handler +IRQ045_Handler +IRQ046_Handler +IRQ047_Handler +IRQ048_Handler +IRQ049_Handler +IRQ050_Handler +IRQ051_Handler +IRQ052_Handler +IRQ053_Handler +IRQ054_Handler +IRQ055_Handler +IRQ056_Handler +IRQ057_Handler +IRQ058_Handler +IRQ059_Handler +IRQ060_Handler +IRQ061_Handler +IRQ062_Handler +IRQ063_Handler +IRQ064_Handler +IRQ065_Handler +IRQ066_Handler +IRQ067_Handler +IRQ068_Handler +IRQ069_Handler +IRQ070_Handler +IRQ071_Handler +IRQ072_Handler +IRQ073_Handler +IRQ074_Handler +IRQ075_Handler +IRQ076_Handler +IRQ077_Handler +IRQ078_Handler +IRQ079_Handler +IRQ080_Handler +IRQ081_Handler +IRQ082_Handler +IRQ083_Handler +IRQ084_Handler +IRQ085_Handler +IRQ086_Handler +IRQ087_Handler +IRQ088_Handler +IRQ089_Handler +IRQ090_Handler +IRQ091_Handler +IRQ092_Handler +IRQ093_Handler +IRQ094_Handler +IRQ095_Handler +IRQ096_Handler +IRQ097_Handler +IRQ098_Handler +IRQ099_Handler +IRQ100_Handler +IRQ101_Handler +IRQ102_Handler +IRQ103_Handler +IRQ104_Handler +IRQ105_Handler +IRQ106_Handler +IRQ107_Handler +IRQ108_Handler +IRQ109_Handler +IRQ110_Handler +IRQ111_Handler +IRQ112_Handler +IRQ113_Handler +IRQ114_Handler +IRQ115_Handler +IRQ116_Handler +IRQ117_Handler +IRQ118_Handler +IRQ119_Handler +IRQ120_Handler +IRQ121_Handler +IRQ122_Handler +IRQ123_Handler +IRQ124_Handler +IRQ125_Handler +IRQ126_Handler +IRQ127_Handler +IRQ128_Handler +IRQ129_Handler +IRQ130_Handler +IRQ131_Handler +IRQ132_Handler +IRQ133_Handler +IRQ134_Handler +IRQ135_Handler +IRQ136_Handler +IRQ137_Handler +IRQ138_Handler +IRQ139_Handler +IRQ140_Handler +IRQ141_Handler +IRQ142_Handler +IRQ143_Handler + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F460xC.ld b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F460xC.ld new file mode 100644 index 0000000..4d4c1ef --- /dev/null +++ b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F460xC.ld @@ -0,0 +1,208 @@ +/****************************************************************************** + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + */ +/*****************************************************************************/ +/* File HC32F460xC.ld */ +/* Abstract Linker script for HC32F460 Device with */ +/* 256KByte FLASH, 192KByte RAM */ +/* Version V1.0 */ +/* Date 2022-03-31 */ +/*****************************************************************************/ + +/* Custom defines, according to section 7.7 of the user manual. + Take OTP sector 0 for example. */ +__OTP_DATA_START = 0x03000C00; +__OTP_DATA_SIZE = 64; +__OTP_LOCK_START = 0x03000FC0; +__OTP_LOCK_SIZE = 4; + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 256K + OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE + OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE + RAM (rwx): ORIGIN = 0x1FFF8000, LENGTH = 188K + RET_RAM (rwx): ORIGIN = 0x200F0000, LENGTH = 4K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP(*(.init)) + KEEP(*(.fini)) + . = ALIGN(4); + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_data_sec : + { + KEEP(*(.otp_data_sec)) + } >OTP_DATA + + .otp_lock_sec : + { + KEEP(*(.otp_lock_sec)) + } >OTP_LOCK + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + __etext_ret_ram = __etext + ALIGN (SIZEOF(.data), 4); + .ret_ram_data : AT (__etext_ret_ram) + { + . = ALIGN(4); + __data_start_ret_ram__ = .; + *(.ret_ram_data) + *(.ret_ram_data*) + . = ALIGN(4); + __data_end_ret_ram__ = .; + } >RET_RAM + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + } >RAM + + .ret_ram_bss : + { + . = ALIGN(4); + __bss_start_ret_ram__ = .; + *(.ret_ram_bss) + *(.ret_ram_bss*) + . = ALIGN(4); + __bss_end_ret_ram__ = .; + } >RET_RAM + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") +} diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F460xE.ld b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F460xE.ld new file mode 100644 index 0000000..8911a5a --- /dev/null +++ b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F460xE.ld @@ -0,0 +1,208 @@ +/****************************************************************************** + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + */ +/*****************************************************************************/ +/* File HC32F460xE.ld */ +/* Abstract Linker script for HC32F460 Device with */ +/* 512KByte FLASH, 192KByte RAM */ +/* Version V1.0 */ +/* Date 2022-03-31 */ +/*****************************************************************************/ + +/* Custom defines, according to section 7.7 of the user manual. + Take OTP sector 0 for example. */ +__OTP_DATA_START = 0x03000C00; +__OTP_DATA_SIZE = 64; +__OTP_LOCK_START = 0x03000FC0; +__OTP_LOCK_SIZE = 4; + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 512K + OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE + OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE + RAM (rwx): ORIGIN = 0x1FFF8000, LENGTH = 188K + RET_RAM (rwx): ORIGIN = 0x200F0000, LENGTH = 4K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP(*(.init)) + KEEP(*(.fini)) + . = ALIGN(4); + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_data_sec : + { + KEEP(*(.otp_data_sec)) + } >OTP_DATA + + .otp_lock_sec : + { + KEEP(*(.otp_lock_sec)) + } >OTP_LOCK + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + __etext_ret_ram = __etext + ALIGN (SIZEOF(.data), 4); + .ret_ram_data : AT (__etext_ret_ram) + { + . = ALIGN(4); + __data_start_ret_ram__ = .; + *(.ret_ram_data) + *(.ret_ram_data*) + . = ALIGN(4); + __data_end_ret_ram__ = .; + } >RET_RAM + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + } >RAM + + .ret_ram_bss : + { + . = ALIGN(4); + __bss_start_ret_ram__ = .; + *(.ret_ram_bss) + *(.ret_ram_bss*) + . = ALIGN(4); + __bss_end_ret_ram__ = .; + } >RET_RAM + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") +} diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f460.S b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f460.S new file mode 100644 index 0000000..e625714 --- /dev/null +++ b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f460.S @@ -0,0 +1,538 @@ +;/** +; ****************************************************************************** +; @file startup_hc32f460.S +; @brief Startup for GCC. +; verbatim +; Change Logs: +; Date Author Notes +; 2022-03-31 CDT First version +; endverbatim +; ***************************************************************************** +; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; ****************************************************************************** +; */ + +/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + .syntax unified + .arch armv7e-m + .cpu cortex-m4 + .fpu softvfp + .thumb + +/* +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +*/ + .equ Stack_Size, 0x00002000 + + .section .stack + .align 3 + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + +/* +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +*/ + .equ Heap_Size, 0x00002000 + + .if Heap_Size != 0 /* Heap is provided */ + .section .heap + .align 3 + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space Heap_Size + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + .endif + +/* +; Interrupt vector table start. +*/ + .section .vectors, "a", %progbits + .align 2 + .type __Vectors, %object + .globl __Vectors + .globl __Vectors_End + .globl __Vectors_Size +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* -14 NMI Handler */ + .long HardFault_Handler /* -13 Hard Fault Handler */ + .long MemManage_Handler /* -12 MPU Fault Handler */ + .long BusFault_Handler /* -11 Bus Fault Handler */ + .long UsageFault_Handler /* -10 Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* -5 SVCall Handler */ + .long DebugMon_Handler /* -4 Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* -2 PendSV Handler */ + .long SysTick_Handler /* -1 SysTick Handler */ + + /* Interrupts */ + .long IRQ000_Handler + .long IRQ001_Handler + .long IRQ002_Handler + .long IRQ003_Handler + .long IRQ004_Handler + .long IRQ005_Handler + .long IRQ006_Handler + .long IRQ007_Handler + .long IRQ008_Handler + .long IRQ009_Handler + .long IRQ010_Handler + .long IRQ011_Handler + .long IRQ012_Handler + .long IRQ013_Handler + .long IRQ014_Handler + .long IRQ015_Handler + .long IRQ016_Handler + .long IRQ017_Handler + .long IRQ018_Handler + .long IRQ019_Handler + .long IRQ020_Handler + .long IRQ021_Handler + .long IRQ022_Handler + .long IRQ023_Handler + .long IRQ024_Handler + .long IRQ025_Handler + .long IRQ026_Handler + .long IRQ027_Handler + .long IRQ028_Handler + .long IRQ029_Handler + .long IRQ030_Handler + .long IRQ031_Handler + .long IRQ032_Handler + .long IRQ033_Handler + .long IRQ034_Handler + .long IRQ035_Handler + .long IRQ036_Handler + .long IRQ037_Handler + .long IRQ038_Handler + .long IRQ039_Handler + .long IRQ040_Handler + .long IRQ041_Handler + .long IRQ042_Handler + .long IRQ043_Handler + .long IRQ044_Handler + .long IRQ045_Handler + .long IRQ046_Handler + .long IRQ047_Handler + .long IRQ048_Handler + .long IRQ049_Handler + .long IRQ050_Handler + .long IRQ051_Handler + .long IRQ052_Handler + .long IRQ053_Handler + .long IRQ054_Handler + .long IRQ055_Handler + .long IRQ056_Handler + .long IRQ057_Handler + .long IRQ058_Handler + .long IRQ059_Handler + .long IRQ060_Handler + .long IRQ061_Handler + .long IRQ062_Handler + .long IRQ063_Handler + .long IRQ064_Handler + .long IRQ065_Handler + .long IRQ066_Handler + .long IRQ067_Handler + .long IRQ068_Handler + .long IRQ069_Handler + .long IRQ070_Handler + .long IRQ071_Handler + .long IRQ072_Handler + .long IRQ073_Handler + .long IRQ074_Handler + .long IRQ075_Handler + .long IRQ076_Handler + .long IRQ077_Handler + .long IRQ078_Handler + .long IRQ079_Handler + .long IRQ080_Handler + .long IRQ081_Handler + .long IRQ082_Handler + .long IRQ083_Handler + .long IRQ084_Handler + .long IRQ085_Handler + .long IRQ086_Handler + .long IRQ087_Handler + .long IRQ088_Handler + .long IRQ089_Handler + .long IRQ090_Handler + .long IRQ091_Handler + .long IRQ092_Handler + .long IRQ093_Handler + .long IRQ094_Handler + .long IRQ095_Handler + .long IRQ096_Handler + .long IRQ097_Handler + .long IRQ098_Handler + .long IRQ099_Handler + .long IRQ100_Handler + .long IRQ101_Handler + .long IRQ102_Handler + .long IRQ103_Handler + .long IRQ104_Handler + .long IRQ105_Handler + .long IRQ106_Handler + .long IRQ107_Handler + .long IRQ108_Handler + .long IRQ109_Handler + .long IRQ110_Handler + .long IRQ111_Handler + .long IRQ112_Handler + .long IRQ113_Handler + .long IRQ114_Handler + .long IRQ115_Handler + .long IRQ116_Handler + .long IRQ117_Handler + .long IRQ118_Handler + .long IRQ119_Handler + .long IRQ120_Handler + .long IRQ121_Handler + .long IRQ122_Handler + .long IRQ123_Handler + .long IRQ124_Handler + .long IRQ125_Handler + .long IRQ126_Handler + .long IRQ127_Handler + .long IRQ128_Handler + .long IRQ129_Handler + .long IRQ130_Handler + .long IRQ131_Handler + .long IRQ132_Handler + .long IRQ133_Handler + .long IRQ134_Handler + .long IRQ135_Handler + .long IRQ136_Handler + .long IRQ137_Handler + .long IRQ138_Handler + .long IRQ139_Handler + .long IRQ140_Handler + .long IRQ141_Handler + .long IRQ142_Handler + .long IRQ143_Handler +__Vectors_End: + .equ __Vectors_Size, __Vectors_End - __Vectors + .size __Vectors, . - __Vectors +/* +; Interrupt vector table end. +*/ + +/* +; Reset handler start. +*/ + .section .text.Reset_Handler + .align 2 + .weak Reset_Handler + .type Reset_Handler, %function + .globl Reset_Handler +Reset_Handler: +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + /* Copy data from read only memory to RAM. */ +CopyData: + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ +CopyLoop: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt CopyLoop + +CopyData1: + ldr r1, =__etext_ret_ram + ldr r2, =__data_start_ret_ram__ + ldr r3, =__data_end_ret_ram__ +CopyLoop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt CopyLoop1 + +/* This part of work usually is done in C library startup code. + * Otherwise, define this macro to enable it in this startup. + * + * There are two schemes too. + * One can clear multiple BSS sections. Another can only clear one section. + * The former is more size expensive than the latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + /* Clear BSS section. */ +ClearBss: + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +ClearLoop: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt ClearLoop + +ClearBss1: + ldr r1, =__bss_start_ret_ram__ + ldr r2, =__bss_end_ret_ram__ + + movs r0, 0 +ClearLoop1: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt ClearLoop1 + +SetSRAM3Wait: + ldr r0, =0x40050804 + mov r1, #0x77 + str r1, [r0] + + ldr r0, =0x4005080C + mov r1, #0x77 + str r1, [r0] + + ldr r0, =0x40050800 + mov r1, #0x1100 + str r1, [r0] + + ldr r0, =0x40050804 + mov r1, #0x76 + str r1, [r0] + + ldr r0, =0x4005080C + mov r1, #0x76 + str r1, [r0] + + /* Call the clock system initialization function. */ + bl SystemInit + /* Call the application's entry point. */ + bl main + bx lr + .size Reset_Handler, . - Reset_Handler +/* +; Reset handler end. +*/ + +/* +; Default handler start. +*/ + .section .text.Default_Handler, "ax", %progbits + .align 2 +Default_Handler: + b . + .size Default_Handler, . - Default_Handler +/* +; Default handler end. +*/ + +/* Macro to define default exception/interrupt handlers. + * Default handler are weak symbols with an endless loop. + * They can be overwritten by real handlers. + */ + .macro Set_Default_Handler Handler_Name + .weak \Handler_Name + .set \Handler_Name, Default_Handler + .endm + +/* Default exception/interrupt handler */ + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler IRQ000_Handler + Set_Default_Handler IRQ001_Handler + Set_Default_Handler IRQ002_Handler + Set_Default_Handler IRQ003_Handler + Set_Default_Handler IRQ004_Handler + Set_Default_Handler IRQ005_Handler + Set_Default_Handler IRQ006_Handler + Set_Default_Handler IRQ007_Handler + Set_Default_Handler IRQ008_Handler + Set_Default_Handler IRQ009_Handler + Set_Default_Handler IRQ010_Handler + Set_Default_Handler IRQ011_Handler + Set_Default_Handler IRQ012_Handler + Set_Default_Handler IRQ013_Handler + Set_Default_Handler IRQ014_Handler + Set_Default_Handler IRQ015_Handler + Set_Default_Handler IRQ016_Handler + Set_Default_Handler IRQ017_Handler + Set_Default_Handler IRQ018_Handler + Set_Default_Handler IRQ019_Handler + Set_Default_Handler IRQ020_Handler + Set_Default_Handler IRQ021_Handler + Set_Default_Handler IRQ022_Handler + Set_Default_Handler IRQ023_Handler + Set_Default_Handler IRQ024_Handler + Set_Default_Handler IRQ025_Handler + Set_Default_Handler IRQ026_Handler + Set_Default_Handler IRQ027_Handler + Set_Default_Handler IRQ028_Handler + Set_Default_Handler IRQ029_Handler + Set_Default_Handler IRQ030_Handler + Set_Default_Handler IRQ031_Handler + Set_Default_Handler IRQ032_Handler + Set_Default_Handler IRQ033_Handler + Set_Default_Handler IRQ034_Handler + Set_Default_Handler IRQ035_Handler + Set_Default_Handler IRQ036_Handler + Set_Default_Handler IRQ037_Handler + Set_Default_Handler IRQ038_Handler + Set_Default_Handler IRQ039_Handler + Set_Default_Handler IRQ040_Handler + Set_Default_Handler IRQ041_Handler + Set_Default_Handler IRQ042_Handler + Set_Default_Handler IRQ043_Handler + Set_Default_Handler IRQ044_Handler + Set_Default_Handler IRQ045_Handler + Set_Default_Handler IRQ046_Handler + Set_Default_Handler IRQ047_Handler + Set_Default_Handler IRQ048_Handler + Set_Default_Handler IRQ049_Handler + Set_Default_Handler IRQ050_Handler + Set_Default_Handler IRQ051_Handler + Set_Default_Handler IRQ052_Handler + Set_Default_Handler IRQ053_Handler + Set_Default_Handler IRQ054_Handler + Set_Default_Handler IRQ055_Handler + Set_Default_Handler IRQ056_Handler + Set_Default_Handler IRQ057_Handler + Set_Default_Handler IRQ058_Handler + Set_Default_Handler IRQ059_Handler + Set_Default_Handler IRQ060_Handler + Set_Default_Handler IRQ061_Handler + Set_Default_Handler IRQ062_Handler + Set_Default_Handler IRQ063_Handler + Set_Default_Handler IRQ064_Handler + Set_Default_Handler IRQ065_Handler + Set_Default_Handler IRQ066_Handler + Set_Default_Handler IRQ067_Handler + Set_Default_Handler IRQ068_Handler + Set_Default_Handler IRQ069_Handler + Set_Default_Handler IRQ070_Handler + Set_Default_Handler IRQ071_Handler + Set_Default_Handler IRQ072_Handler + Set_Default_Handler IRQ073_Handler + Set_Default_Handler IRQ074_Handler + Set_Default_Handler IRQ075_Handler + Set_Default_Handler IRQ076_Handler + Set_Default_Handler IRQ077_Handler + Set_Default_Handler IRQ078_Handler + Set_Default_Handler IRQ079_Handler + Set_Default_Handler IRQ080_Handler + Set_Default_Handler IRQ081_Handler + Set_Default_Handler IRQ082_Handler + Set_Default_Handler IRQ083_Handler + Set_Default_Handler IRQ084_Handler + Set_Default_Handler IRQ085_Handler + Set_Default_Handler IRQ086_Handler + Set_Default_Handler IRQ087_Handler + Set_Default_Handler IRQ088_Handler + Set_Default_Handler IRQ089_Handler + Set_Default_Handler IRQ090_Handler + Set_Default_Handler IRQ091_Handler + Set_Default_Handler IRQ092_Handler + Set_Default_Handler IRQ093_Handler + Set_Default_Handler IRQ094_Handler + Set_Default_Handler IRQ095_Handler + Set_Default_Handler IRQ096_Handler + Set_Default_Handler IRQ097_Handler + Set_Default_Handler IRQ098_Handler + Set_Default_Handler IRQ099_Handler + Set_Default_Handler IRQ100_Handler + Set_Default_Handler IRQ101_Handler + Set_Default_Handler IRQ102_Handler + Set_Default_Handler IRQ103_Handler + Set_Default_Handler IRQ104_Handler + Set_Default_Handler IRQ105_Handler + Set_Default_Handler IRQ106_Handler + Set_Default_Handler IRQ107_Handler + Set_Default_Handler IRQ108_Handler + Set_Default_Handler IRQ109_Handler + Set_Default_Handler IRQ110_Handler + Set_Default_Handler IRQ111_Handler + Set_Default_Handler IRQ112_Handler + Set_Default_Handler IRQ113_Handler + Set_Default_Handler IRQ114_Handler + Set_Default_Handler IRQ115_Handler + Set_Default_Handler IRQ116_Handler + Set_Default_Handler IRQ117_Handler + Set_Default_Handler IRQ118_Handler + Set_Default_Handler IRQ119_Handler + Set_Default_Handler IRQ120_Handler + Set_Default_Handler IRQ121_Handler + Set_Default_Handler IRQ122_Handler + Set_Default_Handler IRQ123_Handler + Set_Default_Handler IRQ124_Handler + Set_Default_Handler IRQ125_Handler + Set_Default_Handler IRQ126_Handler + Set_Default_Handler IRQ127_Handler + Set_Default_Handler IRQ128_Handler + Set_Default_Handler IRQ129_Handler + Set_Default_Handler IRQ130_Handler + Set_Default_Handler IRQ131_Handler + Set_Default_Handler IRQ132_Handler + Set_Default_Handler IRQ133_Handler + Set_Default_Handler IRQ134_Handler + Set_Default_Handler IRQ135_Handler + Set_Default_Handler IRQ136_Handler + Set_Default_Handler IRQ137_Handler + Set_Default_Handler IRQ138_Handler + Set_Default_Handler IRQ139_Handler + Set_Default_Handler IRQ140_Handler + Set_Default_Handler IRQ141_Handler + Set_Default_Handler IRQ142_Handler + Set_Default_Handler IRQ143_Handler + + .end diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HC32F460.svd b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HC32F460.svd new file mode 100644 index 0000000..8805728 --- /dev/null +++ b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HC32F460.svd @@ -0,0 +1,51070 @@ + + + HC32F460 + 1.0 + HC32F460 + + CM4 + r0p1 + little + true + true + 4 + false + + 8 + 32 + 32 + 0x0 + 0xFFFFFFFF + + + ADC1 + desc ADC1 + 0x40040000 + + 0x0 + 0xD0 + registers + + + + STR + desc STR + 0x0 + 8 + read-write + 0x0 + 0x1 + + + STRT + desc STRT + 0 + 0 + read-write + + + + + CR0 + desc CR0 + 0x2 + 16 + read-write + 0x0 + 0x7F3 + + + MS + desc MS + 1 + 0 + read-write + + + ACCSEL + desc ACCSEL + 5 + 4 + read-write + + + CLREN + desc CLREN + 6 + 6 + read-write + + + DFMT + desc DFMT + 7 + 7 + read-write + + + AVCNT + desc AVCNT + 10 + 8 + read-write + + + + + CR1 + desc CR1 + 0x4 + 16 + read-write + 0x0 + 0x4 + + + RSCHSEL + desc RSCHSEL + 2 + 2 + read-write + + + + + TRGSR + desc TRGSR + 0xA + 16 + read-write + 0x0 + 0x8787 + + + TRGSELA + desc TRGSELA + 2 + 0 + read-write + + + TRGENA + desc TRGENA + 7 + 7 + read-write + + + TRGSELB + desc TRGSELB + 10 + 8 + read-write + + + TRGENB + desc TRGENB + 15 + 15 + read-write + + + + + CHSELRA + desc CHSELRA + 0xC + 32 + read-write + 0x0 + 0x1FFFF + + + CHSELA + desc CHSELA + 16 + 0 + read-write + + + + + CHSELRB + desc CHSELRB + 0x10 + 32 + read-write + 0x0 + 0x1FFFF + + + CHSELB + desc CHSELB + 16 + 0 + read-write + + + + + AVCHSELR + desc AVCHSELR + 0x14 + 32 + read-write + 0x0 + 0x1FFFF + + + AVCHSEL + desc AVCHSEL + 16 + 0 + read-write + + + + + SSTR0 + desc SSTR0 + 0x20 + 8 + read-write + 0xB + 0xFF + + + SSTR1 + desc SSTR1 + 0x21 + 8 + read-write + 0xB + 0xFF + + + SSTR2 + desc SSTR2 + 0x22 + 8 + read-write + 0xB + 0xFF + + + SSTR3 + desc SSTR3 + 0x23 + 8 + read-write + 0xB + 0xFF + + + SSTR4 + desc SSTR4 + 0x24 + 8 + read-write + 0xB + 0xFF + + + SSTR5 + desc SSTR5 + 0x25 + 8 + read-write + 0xB + 0xFF + + + SSTR6 + desc SSTR6 + 0x26 + 8 + read-write + 0xB + 0xFF + + + SSTR7 + desc SSTR7 + 0x27 + 8 + read-write + 0xB + 0xFF + + + SSTR8 + desc SSTR8 + 0x28 + 8 + read-write + 0xB + 0xFF + + + SSTR9 + desc SSTR9 + 0x29 + 8 + read-write + 0xB + 0xFF + + + SSTR10 + desc SSTR10 + 0x2A + 8 + read-write + 0xB + 0xFF + + + SSTR11 + desc SSTR11 + 0x2B + 8 + read-write + 0xB + 0xFF + + + SSTR12 + desc SSTR12 + 0x2C + 8 + read-write + 0xB + 0xFF + + + SSTR13 + desc SSTR13 + 0x2D + 8 + read-write + 0xB + 0xFF + + + SSTR14 + desc SSTR14 + 0x2E + 8 + read-write + 0xB + 0xFF + + + SSTR15 + desc SSTR15 + 0x2F + 8 + read-write + 0xB + 0xFF + + + SSTRL + desc SSTRL + 0x30 + 8 + read-write + 0xB + 0xFF + + + CHMUXR0 + desc CHMUXR0 + 0x38 + 16 + read-write + 0x3210 + 0xFFFF + + + CH00MUX + desc CH00MUX + 3 + 0 + read-write + + + CH01MUX + desc CH01MUX + 7 + 4 + read-write + + + CH02MUX + desc CH02MUX + 11 + 8 + read-write + + + CH03MUX + desc CH03MUX + 15 + 12 + read-write + + + + + CHMUXR1 + desc CHMUXR1 + 0x3A + 16 + read-write + 0x7654 + 0xFFFF + + + CH04MUX + desc CH04MUX + 3 + 0 + read-write + + + CH05MUX + desc CH05MUX + 7 + 4 + read-write + + + CH06MUX + desc CH06MUX + 11 + 8 + read-write + + + CH07MUX + desc CH07MUX + 15 + 12 + read-write + + + + + CHMUXR2 + desc CHMUXR2 + 0x3C + 16 + read-write + 0xBA98 + 0xFFFF + + + CH08MUX + desc CH08MUX + 3 + 0 + read-write + + + CH09MUX + desc CH09MUX + 7 + 4 + read-write + + + CH10MUX + desc CH10MUX + 11 + 8 + read-write + + + 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SEL29 + desc SEL29 + 0xD0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL30 + desc SEL30 + 0xD4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL31 + desc SEL31 + 0xD8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL32 + desc SEL32 + 0xDC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL33 + desc SEL33 + 0xE0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL34 + desc SEL34 + 0xE4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL35 + desc SEL35 + 0xE8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL36 + desc SEL36 + 0xEC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL37 + desc SEL37 + 0xF0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL38 + desc SEL38 + 0xF4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL39 + desc SEL39 + 0xF8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL40 + desc SEL40 + 0xFC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL41 + desc SEL41 + 0x100 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL42 + desc SEL42 + 0x104 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL43 + desc SEL43 + 0x108 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL44 + desc SEL44 + 0x10C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL45 + desc SEL45 + 0x110 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + 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VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL134 + desc VSSEL134 + 0x274 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + 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+ + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT3 + desc DIEPINT3 + 0x968 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ3 + desc DIEPTSIZ3 + 0x970 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DIEPDMA3 + desc DIEPDMA3 + 0x974 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS3 + desc DTXFSTS3 + 0x978 + 32 + read-only + 0x100 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL4 + desc DIEPCTL4 + 0x980 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT4 + desc DIEPINT4 + 0x988 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ4 + desc DIEPTSIZ4 + 0x990 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DIEPDMA4 + desc DIEPDMA4 + 0x994 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS4 + desc DTXFSTS4 + 0x998 + 32 + read-only + 0x100 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL5 + desc DIEPCTL5 + 0x9A0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT5 + desc DIEPINT5 + 0x9A8 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ5 + desc DIEPTSIZ5 + 0x9B0 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DIEPDMA5 + desc DIEPDMA5 + 0x9B4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS5 + desc DTXFSTS5 + 0x9B8 + 32 + read-only + 0x100 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DOEPCTL0 + desc DOEPCTL0 + 0xB00 + 32 + read-write + 0x8000 + 0xCC3E8003 + + + MPSIZ + desc MPSIZ + 1 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT0 + desc DOEPINT0 + 0xB08 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ0 + desc DOEPTSIZ0 + 0xB10 + 32 + read-write + 0x0 + 0x6008007F + + + XFRSIZ + desc XFRSIZ + 6 + 0 + read-write + + + PKTCNT + desc PKTCNT + 19 + 19 + read-write + + + STUPCNT + desc STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA0 + desc DOEPDMA0 + 0xB14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL1 + desc DOEPCTL1 + 0xB20 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT1 + desc DOEPINT1 + 0xB28 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ1 + desc DOEPTSIZ1 + 0xB30 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DOEPDMA1 + desc DOEPDMA1 + 0xB34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL2 + desc DOEPCTL2 + 0xB40 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT2 + desc DOEPINT2 + 0xB48 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ2 + desc DOEPTSIZ2 + 0xB50 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DOEPDMA2 + desc DOEPDMA2 + 0xB54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL3 + desc DOEPCTL3 + 0xB60 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT3 + desc DOEPINT3 + 0xB68 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ3 + desc DOEPTSIZ3 + 0xB70 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DOEPDMA3 + desc DOEPDMA3 + 0xB74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL4 + desc DOEPCTL4 + 0xB80 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT4 + desc DOEPINT4 + 0xB88 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ4 + desc DOEPTSIZ4 + 0xB90 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DOEPDMA4 + desc DOEPDMA4 + 0xB94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL5 + desc DOEPCTL5 + 0xBA0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT5 + desc DOEPINT5 + 0xBA8 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ5 + desc DOEPTSIZ5 + 0xBB0 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DOEPDMA5 + desc DOEPDMA5 + 0xBB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + GCCTL + desc GCCTL + 0xE00 + 32 + read-write + 0x0 + 0x3 + + + STPPCLK + desc STPPCLK + 0 + 0 + read-write + + + GATEHCLK + desc GATEHCLK + 1 + 1 + read-write + + + + + + + WDT + desc WDT + 0x40049000 + + 0x0 + 0xC + registers + + + + CR + desc CR + 0x0 + 32 + read-write + 0x80010FF3 + 0x80010FF3 + + + PERI + desc PERI + 1 + 0 + read-write + + + CKS + desc CKS + 7 + 4 + read-write + + + WDPT + desc WDPT + 11 + 8 + read-write + + + SLPOFF + desc SLPOFF + 16 + 16 + read-write + + + ITS + desc ITS + 31 + 31 + read-write + + + + + SR + desc SR + 0x4 + 32 + read-write + 0x0 + 0x3FFFF + + + CNT + desc CNT + 15 + 0 + read-only + + + UDF + desc UDF + 16 + 16 + read-write + + + REF + desc REF + 17 + 17 + read-write + + + + + RR + desc RR + 0x8 + 32 + read-write + 0x0 + 0xFFFF + + + RF + desc RF + 15 + 0 + read-write + + + + + + + diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460.mac b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460.mac new file mode 100644 index 0000000..e30bd40 --- /dev/null +++ b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460.mac @@ -0,0 +1,16 @@ +setup() +{ + ; +} + +execUserPreload() +{ + __message "----- Prepare hardware for Flashloader -----\n"; + setup(); +} +execUserFlashInit() // Called by debugger before loading flash loader in RAM. +{ + __message "----- Prepare hardware for Flashloader -----\n"; + setup(); +} + diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460_otp.mac b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460_otp.mac new file mode 100644 index 0000000..e30bd40 --- /dev/null +++ b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460_otp.mac @@ -0,0 +1,16 @@ +setup() +{ + ; +} + +execUserPreload() +{ + __message "----- Prepare hardware for Flashloader -----\n"; + setup(); +} +execUserFlashInit() // Called by debugger before loading flash loader in RAM. +{ + __message "----- Prepare hardware for Flashloader -----\n"; + setup(); +} + diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460_RAM.icf b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460_RAM.icf new file mode 100644 index 0000000..056f111 --- /dev/null +++ b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460_RAM.icf @@ -0,0 +1,56 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x1FFF8000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x1FFF8000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1FFFFFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x20000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x20020000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x20026FFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_IRAM3_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM4_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM4_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM5_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM5_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x100; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x100; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xC.icf b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xC.icf new file mode 100644 index 0000000..bce187e --- /dev/null +++ b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xC.icf @@ -0,0 +1,50 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x0003FFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x03000C00; +define symbol __ICFEDIT_region_IROM2_end__ = 0x03000FFB; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFF8000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x20026FFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xE.icf b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xE.icf new file mode 100644 index 0000000..46ffdd5 --- /dev/null +++ b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xE.icf @@ -0,0 +1,50 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x03000C00; +define symbol __ICFEDIT_region_IROM2_end__ = 0x03000FFB; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFF8000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x20026FFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f460.s b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f460.s new file mode 100644 index 0000000..75c08b1 --- /dev/null +++ b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f460.s @@ -0,0 +1,995 @@ +;/** +; ****************************************************************************** +; @file startup_hc32f460.s +; @brief Startup for IAR. +; verbatim +; Change Logs: +; Date Author Notes +; 2022-03-31 CDT First version +; endverbatim +; ***************************************************************************** +; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; ****************************************************************************** +; */ + + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Peripheral Interrupts + DCD IRQ000_Handler + DCD IRQ001_Handler + DCD IRQ002_Handler + DCD IRQ003_Handler + DCD IRQ004_Handler + DCD IRQ005_Handler + DCD IRQ006_Handler + DCD IRQ007_Handler + DCD IRQ008_Handler + DCD IRQ009_Handler + DCD IRQ010_Handler + DCD IRQ011_Handler + DCD IRQ012_Handler + DCD IRQ013_Handler + DCD IRQ014_Handler + DCD IRQ015_Handler + DCD IRQ016_Handler + DCD IRQ017_Handler + DCD IRQ018_Handler + DCD IRQ019_Handler + DCD IRQ020_Handler + DCD IRQ021_Handler + DCD IRQ022_Handler + DCD IRQ023_Handler + DCD IRQ024_Handler + DCD IRQ025_Handler + DCD IRQ026_Handler + DCD IRQ027_Handler + DCD IRQ028_Handler + DCD IRQ029_Handler + DCD IRQ030_Handler + DCD IRQ031_Handler + DCD IRQ032_Handler + DCD IRQ033_Handler + DCD IRQ034_Handler + DCD IRQ035_Handler + DCD IRQ036_Handler + DCD IRQ037_Handler + DCD IRQ038_Handler + DCD IRQ039_Handler + DCD IRQ040_Handler + DCD IRQ041_Handler + DCD IRQ042_Handler + DCD IRQ043_Handler + DCD IRQ044_Handler + DCD IRQ045_Handler + DCD IRQ046_Handler + DCD IRQ047_Handler + DCD IRQ048_Handler + DCD IRQ049_Handler + DCD IRQ050_Handler + DCD IRQ051_Handler + DCD IRQ052_Handler + DCD IRQ053_Handler + DCD IRQ054_Handler + DCD IRQ055_Handler + DCD IRQ056_Handler + DCD IRQ057_Handler + DCD IRQ058_Handler + DCD IRQ059_Handler + DCD IRQ060_Handler + DCD IRQ061_Handler + DCD IRQ062_Handler + DCD IRQ063_Handler + DCD IRQ064_Handler + DCD IRQ065_Handler + DCD IRQ066_Handler + DCD IRQ067_Handler + DCD IRQ068_Handler + DCD IRQ069_Handler + DCD IRQ070_Handler + DCD IRQ071_Handler + DCD IRQ072_Handler + DCD IRQ073_Handler + DCD IRQ074_Handler + DCD IRQ075_Handler + DCD IRQ076_Handler + DCD IRQ077_Handler + DCD IRQ078_Handler + DCD IRQ079_Handler + DCD IRQ080_Handler + DCD IRQ081_Handler + DCD IRQ082_Handler + DCD IRQ083_Handler + DCD IRQ084_Handler + DCD IRQ085_Handler + DCD IRQ086_Handler + DCD IRQ087_Handler + DCD IRQ088_Handler + DCD IRQ089_Handler + DCD IRQ090_Handler + DCD IRQ091_Handler + DCD IRQ092_Handler + DCD IRQ093_Handler + DCD IRQ094_Handler + DCD IRQ095_Handler + DCD IRQ096_Handler + DCD IRQ097_Handler + DCD IRQ098_Handler + DCD IRQ099_Handler + DCD IRQ100_Handler + DCD IRQ101_Handler + DCD IRQ102_Handler + DCD IRQ103_Handler + DCD IRQ104_Handler + DCD IRQ105_Handler + DCD IRQ106_Handler + DCD IRQ107_Handler + DCD IRQ108_Handler + DCD IRQ109_Handler + DCD IRQ110_Handler + DCD IRQ111_Handler + DCD IRQ112_Handler + DCD IRQ113_Handler + DCD IRQ114_Handler + DCD IRQ115_Handler + DCD IRQ116_Handler + DCD IRQ117_Handler + DCD IRQ118_Handler + DCD IRQ119_Handler + DCD IRQ120_Handler + DCD IRQ121_Handler + DCD IRQ122_Handler + DCD IRQ123_Handler + DCD IRQ124_Handler + DCD IRQ125_Handler + DCD IRQ126_Handler + DCD IRQ127_Handler + DCD IRQ128_Handler + DCD IRQ129_Handler + DCD IRQ130_Handler + DCD IRQ131_Handler + DCD IRQ132_Handler + DCD IRQ133_Handler + DCD IRQ134_Handler + DCD IRQ135_Handler + DCD IRQ136_Handler + DCD IRQ137_Handler + DCD IRQ138_Handler + DCD IRQ139_Handler + DCD IRQ140_Handler + DCD IRQ141_Handler + DCD IRQ142_Handler + DCD IRQ143_Handler + + THUMB +; Dummy Exception Handlers (infinite loops which can be modified) + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler +;SetSRAM3Wait + LDR R0, =0x40050804 + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x40050800 + MOV R1, #0x1100 + STR R1, [R0] + + LDR R0, =0x40050804 + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK IRQ000_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ000_Handler + B IRQ000_Handler + + PUBWEAK IRQ001_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ001_Handler + B IRQ001_Handler + + PUBWEAK IRQ002_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ002_Handler + B IRQ002_Handler + + PUBWEAK IRQ003_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ003_Handler + B IRQ003_Handler + + PUBWEAK IRQ004_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ004_Handler + B IRQ004_Handler + + PUBWEAK IRQ005_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ005_Handler + B IRQ005_Handler + + PUBWEAK IRQ006_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ006_Handler + B IRQ006_Handler + + PUBWEAK IRQ007_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ007_Handler + B IRQ007_Handler + + PUBWEAK IRQ008_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ008_Handler + B IRQ008_Handler + + PUBWEAK IRQ009_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ009_Handler + B IRQ009_Handler + + PUBWEAK IRQ010_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ010_Handler + B IRQ010_Handler + + PUBWEAK IRQ011_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ011_Handler + B IRQ011_Handler + + PUBWEAK IRQ012_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ012_Handler + B IRQ012_Handler + + PUBWEAK IRQ013_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ013_Handler + B IRQ013_Handler + + PUBWEAK IRQ014_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ014_Handler + B IRQ014_Handler + + PUBWEAK IRQ015_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ015_Handler + B IRQ015_Handler + + PUBWEAK IRQ016_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ016_Handler + B IRQ016_Handler + + PUBWEAK IRQ017_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ017_Handler + B IRQ017_Handler + + PUBWEAK IRQ018_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ018_Handler + B IRQ018_Handler + + PUBWEAK IRQ019_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ019_Handler + B IRQ019_Handler + + PUBWEAK IRQ020_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ020_Handler + B IRQ020_Handler + + PUBWEAK IRQ021_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ021_Handler + B IRQ021_Handler + + PUBWEAK IRQ022_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ022_Handler + B IRQ022_Handler + + PUBWEAK IRQ023_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ023_Handler + B IRQ023_Handler + + PUBWEAK IRQ024_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ024_Handler + B IRQ024_Handler + + PUBWEAK IRQ025_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ025_Handler + B IRQ025_Handler + + PUBWEAK IRQ026_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ026_Handler + B IRQ026_Handler + + PUBWEAK IRQ027_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ027_Handler + B IRQ027_Handler + + PUBWEAK IRQ028_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ028_Handler + B IRQ028_Handler + + PUBWEAK IRQ029_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ029_Handler + B IRQ029_Handler + + PUBWEAK IRQ030_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ030_Handler + B IRQ030_Handler + + PUBWEAK IRQ031_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ031_Handler + B IRQ031_Handler + + PUBWEAK IRQ032_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ032_Handler + B IRQ032_Handler + + PUBWEAK IRQ033_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ033_Handler + B IRQ033_Handler + + PUBWEAK IRQ034_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ034_Handler + B IRQ034_Handler + + PUBWEAK IRQ035_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ035_Handler + B IRQ035_Handler + + PUBWEAK IRQ036_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ036_Handler + B IRQ036_Handler + + PUBWEAK IRQ037_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ037_Handler + B IRQ037_Handler + + PUBWEAK IRQ038_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ038_Handler + B IRQ038_Handler + + PUBWEAK IRQ039_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ039_Handler + B IRQ039_Handler + + PUBWEAK IRQ040_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ040_Handler + B IRQ040_Handler + + PUBWEAK IRQ041_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ041_Handler + B IRQ041_Handler + + PUBWEAK IRQ042_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ042_Handler + B IRQ042_Handler + + PUBWEAK IRQ043_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ043_Handler + B IRQ043_Handler + + PUBWEAK IRQ044_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ044_Handler + B IRQ044_Handler + + PUBWEAK IRQ045_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ045_Handler + B IRQ045_Handler + + PUBWEAK IRQ046_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ046_Handler + B IRQ046_Handler + + PUBWEAK IRQ047_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ047_Handler + B IRQ047_Handler + + PUBWEAK IRQ048_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ048_Handler + B IRQ048_Handler + + PUBWEAK IRQ049_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ049_Handler + B IRQ049_Handler + + PUBWEAK IRQ050_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ050_Handler + B IRQ050_Handler + + PUBWEAK IRQ051_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ051_Handler + B IRQ051_Handler + + PUBWEAK IRQ052_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ052_Handler + B IRQ052_Handler + + PUBWEAK IRQ053_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ053_Handler + B IRQ053_Handler + + PUBWEAK IRQ054_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ054_Handler + B IRQ054_Handler + + PUBWEAK IRQ055_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ055_Handler + B IRQ055_Handler + + PUBWEAK IRQ056_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ056_Handler + B IRQ056_Handler + + PUBWEAK IRQ057_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ057_Handler + B IRQ057_Handler + + PUBWEAK IRQ058_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ058_Handler + B IRQ058_Handler + + PUBWEAK IRQ059_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ059_Handler + B IRQ059_Handler + + PUBWEAK IRQ060_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ060_Handler + B IRQ060_Handler + + PUBWEAK IRQ061_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ061_Handler + B IRQ061_Handler + + PUBWEAK IRQ062_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ062_Handler + B IRQ062_Handler + + PUBWEAK IRQ063_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ063_Handler + B IRQ063_Handler + + PUBWEAK IRQ064_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ064_Handler + B IRQ064_Handler + + PUBWEAK IRQ065_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ065_Handler + B IRQ065_Handler + + PUBWEAK IRQ066_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ066_Handler + B IRQ066_Handler + + PUBWEAK IRQ067_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ067_Handler + B IRQ067_Handler + + PUBWEAK IRQ068_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ068_Handler + B IRQ068_Handler + + PUBWEAK IRQ069_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ069_Handler + B IRQ069_Handler + + PUBWEAK IRQ070_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ070_Handler + B IRQ070_Handler + + PUBWEAK IRQ071_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ071_Handler + B IRQ071_Handler + + PUBWEAK IRQ072_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ072_Handler + B IRQ072_Handler + + PUBWEAK IRQ073_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ073_Handler + B IRQ073_Handler + + PUBWEAK IRQ074_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ074_Handler + B IRQ074_Handler + + PUBWEAK IRQ075_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ075_Handler + B IRQ075_Handler + + PUBWEAK IRQ076_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ076_Handler + B IRQ076_Handler + + PUBWEAK IRQ077_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ077_Handler + B IRQ077_Handler + + PUBWEAK IRQ078_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ078_Handler + B IRQ078_Handler + + PUBWEAK IRQ079_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ079_Handler + B IRQ079_Handler + + PUBWEAK IRQ080_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ080_Handler + B IRQ080_Handler + + PUBWEAK IRQ081_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ081_Handler + B IRQ081_Handler + + PUBWEAK IRQ082_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ082_Handler + B IRQ082_Handler + + PUBWEAK IRQ083_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ083_Handler + B IRQ083_Handler + + PUBWEAK IRQ084_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ084_Handler + B IRQ084_Handler + + PUBWEAK IRQ085_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ085_Handler + B IRQ085_Handler + + PUBWEAK IRQ086_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ086_Handler + B IRQ086_Handler + + PUBWEAK IRQ087_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ087_Handler + B IRQ087_Handler + + PUBWEAK IRQ088_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ088_Handler + B IRQ088_Handler + + PUBWEAK IRQ089_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ089_Handler + B IRQ089_Handler + + PUBWEAK IRQ090_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ090_Handler + B IRQ090_Handler + + PUBWEAK IRQ091_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ091_Handler + B IRQ091_Handler + + PUBWEAK IRQ092_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ092_Handler + B IRQ092_Handler + + PUBWEAK IRQ093_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ093_Handler + B IRQ093_Handler + + PUBWEAK IRQ094_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ094_Handler + B IRQ094_Handler + + PUBWEAK IRQ095_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ095_Handler + B IRQ095_Handler + + PUBWEAK IRQ096_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ096_Handler + B IRQ096_Handler + + PUBWEAK IRQ097_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ097_Handler + B IRQ097_Handler + + PUBWEAK IRQ098_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ098_Handler + B IRQ098_Handler + + PUBWEAK IRQ099_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ099_Handler + B IRQ099_Handler + + PUBWEAK IRQ100_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ100_Handler + B IRQ100_Handler + + PUBWEAK IRQ101_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ101_Handler + B IRQ101_Handler + + PUBWEAK IRQ102_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ102_Handler + B IRQ102_Handler + + PUBWEAK IRQ103_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ103_Handler + B IRQ103_Handler + + PUBWEAK IRQ104_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ104_Handler + B IRQ104_Handler + + PUBWEAK IRQ105_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ105_Handler + B IRQ105_Handler + + PUBWEAK IRQ106_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ106_Handler + B IRQ106_Handler + + PUBWEAK IRQ107_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ107_Handler + B IRQ107_Handler + + PUBWEAK IRQ108_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ108_Handler + B IRQ108_Handler + + PUBWEAK IRQ109_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ109_Handler + B IRQ109_Handler + + PUBWEAK IRQ110_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ110_Handler + B IRQ110_Handler + + PUBWEAK IRQ111_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ111_Handler + B IRQ111_Handler + + PUBWEAK IRQ112_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ112_Handler + B IRQ112_Handler + + PUBWEAK IRQ113_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ113_Handler + B IRQ113_Handler + + PUBWEAK IRQ114_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ114_Handler + B IRQ114_Handler + + PUBWEAK IRQ115_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ115_Handler + B IRQ115_Handler + + PUBWEAK IRQ116_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ116_Handler + B IRQ116_Handler + + PUBWEAK IRQ117_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ117_Handler + B IRQ117_Handler + + PUBWEAK IRQ118_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ118_Handler + B IRQ118_Handler + + PUBWEAK IRQ119_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ119_Handler + B IRQ119_Handler + + PUBWEAK IRQ120_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ120_Handler + B IRQ120_Handler + + PUBWEAK IRQ121_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ121_Handler + B IRQ121_Handler + + PUBWEAK IRQ122_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ122_Handler + B IRQ122_Handler + + PUBWEAK IRQ123_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ123_Handler + B IRQ123_Handler + + PUBWEAK IRQ124_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ124_Handler + B IRQ124_Handler + + PUBWEAK IRQ125_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ125_Handler + B IRQ125_Handler + + PUBWEAK IRQ126_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ126_Handler + B IRQ126_Handler + + PUBWEAK IRQ127_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ127_Handler + B IRQ127_Handler + + PUBWEAK IRQ128_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ128_Handler + B IRQ128_Handler + + PUBWEAK IRQ129_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ129_Handler + B IRQ129_Handler + + PUBWEAK IRQ130_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ130_Handler + B IRQ130_Handler + + PUBWEAK IRQ131_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ131_Handler + B IRQ131_Handler + + PUBWEAK IRQ132_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ132_Handler + B IRQ132_Handler + + PUBWEAK IRQ133_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ133_Handler + B IRQ133_Handler + + PUBWEAK IRQ134_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ134_Handler + B IRQ134_Handler + + PUBWEAK IRQ135_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ135_Handler + B IRQ135_Handler + + PUBWEAK IRQ136_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ136_Handler + B IRQ136_Handler + + PUBWEAK IRQ137_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ137_Handler + B IRQ137_Handler + + PUBWEAK IRQ138_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ138_Handler + B IRQ138_Handler + + PUBWEAK IRQ139_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ139_Handler + B IRQ139_Handler + + PUBWEAK IRQ140_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ140_Handler + B IRQ140_Handler + + PUBWEAK IRQ141_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ141_Handler + B IRQ141_Handler + + PUBWEAK IRQ142_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ142_Handler + B IRQ142_Handler + + PUBWEAK IRQ143_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ143_Handler + B IRQ143_Handler + + END diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F460.svd b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F460.svd new file mode 100644 index 0000000..8805728 --- /dev/null +++ b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F460.svd @@ -0,0 +1,51070 @@ + + + HC32F460 + 1.0 + HC32F460 + + CM4 + r0p1 + little + true + true + 4 + false + + 8 + 32 + 32 + 0x0 + 0xFFFFFFFF + + + ADC1 + desc ADC1 + 0x40040000 + + 0x0 + 0xD0 + registers + + + + STR + desc STR + 0x0 + 8 + read-write + 0x0 + 0x1 + + + STRT + desc STRT + 0 + 0 + read-write + + + + + CR0 + desc CR0 + 0x2 + 16 + read-write + 0x0 + 0x7F3 + + + MS + desc MS + 1 + 0 + read-write + + + ACCSEL + desc ACCSEL + 5 + 4 + read-write + + + CLREN + desc CLREN + 6 + 6 + read-write + + + DFMT + desc DFMT + 7 + 7 + read-write + + + AVCNT + desc AVCNT + 10 + 8 + read-write + + + + + CR1 + desc CR1 + 0x4 + 16 + read-write + 0x0 + 0x4 + + + RSCHSEL + desc RSCHSEL + 2 + 2 + read-write + + + + + TRGSR + desc TRGSR + 0xA + 16 + read-write + 0x0 + 0x8787 + + + TRGSELA + desc TRGSELA + 2 + 0 + read-write + + + TRGENA + desc TRGENA + 7 + 7 + read-write + + + TRGSELB + desc TRGSELB + 10 + 8 + read-write + + + TRGENB + desc TRGENB + 15 + 15 + read-write + + + + + CHSELRA + desc CHSELRA + 0xC + 32 + read-write + 0x0 + 0x1FFFF + + + CHSELA + desc CHSELA + 16 + 0 + read-write + + + + + CHSELRB + desc CHSELRB + 0x10 + 32 + read-write + 0x0 + 0x1FFFF + + + CHSELB + desc CHSELB + 16 + 0 + read-write + + + + + AVCHSELR + desc AVCHSELR + 0x14 + 32 + read-write + 0x0 + 0x1FFFF + + + AVCHSEL + desc AVCHSEL + 16 + 0 + read-write + + + + + SSTR0 + desc SSTR0 + 0x20 + 8 + read-write + 0xB + 0xFF + + + SSTR1 + desc SSTR1 + 0x21 + 8 + read-write + 0xB + 0xFF + + + SSTR2 + desc SSTR2 + 0x22 + 8 + read-write + 0xB + 0xFF + + + SSTR3 + desc SSTR3 + 0x23 + 8 + read-write + 0xB + 0xFF + + + SSTR4 + desc SSTR4 + 0x24 + 8 + read-write + 0xB + 0xFF + + + SSTR5 + desc SSTR5 + 0x25 + 8 + read-write + 0xB + 0xFF + + + SSTR6 + desc SSTR6 + 0x26 + 8 + read-write + 0xB + 0xFF + + + SSTR7 + desc SSTR7 + 0x27 + 8 + read-write + 0xB + 0xFF + + + SSTR8 + desc SSTR8 + 0x28 + 8 + read-write + 0xB + 0xFF + + + SSTR9 + desc SSTR9 + 0x29 + 8 + read-write + 0xB + 0xFF + + + SSTR10 + desc SSTR10 + 0x2A + 8 + read-write + 0xB + 0xFF + + + SSTR11 + desc SSTR11 + 0x2B + 8 + read-write + 0xB + 0xFF + + + SSTR12 + desc SSTR12 + 0x2C + 8 + read-write + 0xB + 0xFF + + + SSTR13 + desc SSTR13 + 0x2D + 8 + read-write + 0xB + 0xFF + + + SSTR14 + desc SSTR14 + 0x2E + 8 + read-write + 0xB + 0xFF + + + SSTR15 + desc SSTR15 + 0x2F + 8 + read-write + 0xB + 0xFF + + + SSTRL + desc SSTRL + 0x30 + 8 + read-write + 0xB + 0xFF + + + CHMUXR0 + desc CHMUXR0 + 0x38 + 16 + read-write + 0x3210 + 0xFFFF + + + CH00MUX + desc CH00MUX + 3 + 0 + read-write + + + CH01MUX + desc CH01MUX + 7 + 4 + read-write + + + CH02MUX + desc CH02MUX + 11 + 8 + read-write + + + CH03MUX + desc CH03MUX + 15 + 12 + read-write + + + + + CHMUXR1 + desc CHMUXR1 + 0x3A + 16 + read-write + 0x7654 + 0xFFFF + + + CH04MUX + desc CH04MUX + 3 + 0 + read-write + + + CH05MUX + desc CH05MUX + 7 + 4 + read-write + + + CH06MUX + desc CH06MUX + 11 + 8 + read-write + + + CH07MUX + desc CH07MUX + 15 + 12 + read-write + + + + + CHMUXR2 + desc CHMUXR2 + 0x3C + 16 + read-write + 0xBA98 + 0xFFFF + + + CH08MUX + desc CH08MUX + 3 + 0 + read-write + + + CH09MUX + desc CH09MUX + 7 + 4 + read-write + + + CH10MUX + desc CH10MUX + 11 + 8 + read-write + + + CH11MUX + desc CH11MUX + 15 + 12 + read-write + + + + + CHMUXR3 + desc CHMUXR3 + 0x3E + 16 + read-write + 0xFEDC + 0xFFFF + + + CH12MUX + desc CH12MUX + 3 + 0 + read-write + + + CH13MUX + desc CH13MUX + 7 + 4 + read-write + + + CH14MUX + desc CH14MUX + 11 + 8 + read-write + + + CH15MUX + desc CH15MUX + 15 + 12 + read-write + + + + + ISR + desc ISR + 0x46 + 8 + read-write + 0x0 + 0x3 + + + EOCAF + desc EOCAF + 0 + 0 + read-write + + + EOCBF + desc EOCBF + 1 + 1 + read-write + + + + + ICR + desc ICR + 0x47 + 8 + read-write + 0x0 + 0x3 + + + EOCAIEN + desc EOCAIEN + 0 + 0 + read-write + + + EOCBIEN + desc EOCBIEN + 1 + 1 + read-write + + + + + SYNCCR + desc SYNCCR + 0x4C + 16 + read-write + 0xC00 + 0xFF71 + + + SYNCEN + desc SYNCEN + 0 + 0 + read-write + + + SYNCMD + desc SYNCMD + 6 + 4 + read-write + + + SYNCDLY + desc SYNCDLY + 15 + 8 + read-write + + + + + DR0 + desc DR0 + 0x50 + 16 + read-only + 0x0 + 0xFFFF + + + DR1 + desc DR1 + 0x52 + 16 + read-only + 0x0 + 0xFFFF + + + DR2 + desc DR2 + 0x54 + 16 + read-only + 0x0 + 0xFFFF + + + DR3 + desc DR3 + 0x56 + 16 + read-only + 0x0 + 0xFFFF + + + DR4 + desc DR4 + 0x58 + 16 + read-only + 0x0 + 0xFFFF + + + DR5 + desc DR5 + 0x5A + 16 + read-only + 0x0 + 0xFFFF + + + DR6 + desc DR6 + 0x5C + 16 + read-only + 0x0 + 0xFFFF + + + DR7 + desc DR7 + 0x5E + 16 + read-only + 0x0 + 0xFFFF + + + DR8 + desc DR8 + 0x60 + 16 + read-only + 0x0 + 0xFFFF + + + DR9 + desc DR9 + 0x62 + 16 + read-only + 0x0 + 0xFFFF + + + DR10 + desc DR10 + 0x64 + 16 + read-only + 0x0 + 0xFFFF + + + DR11 + desc DR11 + 0x66 + 16 + read-only + 0x0 + 0xFFFF + + + DR12 + desc DR12 + 0x68 + 16 + read-only + 0x0 + 0xFFFF + + + DR13 + desc DR13 + 0x6A + 16 + read-only + 0x0 + 0xFFFF + + + DR14 + desc DR14 + 0x6C + 16 + read-only + 0x0 + 0xFFFF + + + DR15 + desc DR15 + 0x6E + 16 + read-only + 0x0 + 0xFFFF + + + DR16 + desc DR16 + 0x70 + 16 + read-only + 0x0 + 0xFFFF + + + AWDCR + desc AWDCR + 0xA0 + 16 + read-write + 0x0 + 0x1D1 + + + AWDEN + desc AWDEN + 0 + 0 + read-write + + + AWDMD + desc AWDMD + 4 + 4 + read-write + + + AWDSS + desc AWDSS + 7 + 6 + read-write + + + AWDIEN + desc AWDIEN + 8 + 8 + read-write + + + + + AWDDR0 + desc AWDDR0 + 0xA4 + 16 + read-write + 0x0 + 0xFFFF + + + AWDDR1 + desc AWDDR1 + 0xA6 + 16 + read-write + 0x0 + 0xFFFF + + + AWDCHSR + desc AWDCHSR + 0xAC + 32 + read-write + 0x0 + 0x1FFFF + + + AWDCH + desc AWDCH + 16 + 0 + read-write + + + + + AWDSR + desc AWDSR + 0xB0 + 32 + read-write + 0x0 + 0x1FFFF + + + AWDF + desc AWDF + 16 + 0 + read-write + + + + + PGACR + desc PGACR + 0xC0 + 16 + read-write + 0x0 + 0xF + + + PGACTL + desc PGACTL + 3 + 0 + read-write + + + + + PGAGSR + desc PGAGSR + 0xC2 + 16 + read-write + 0x0 + 0xF + + + GAIN + desc GAIN + 3 + 0 + read-write + + + + + PGAINSR0 + desc PGAINSR0 + 0xCC + 16 + read-write + 0x0 + 0x1FF + + + PGAINSEL + desc PGAINSEL + 8 + 0 + read-write + + + + + PGAINSR1 + desc PGAINSR1 + 0xCE + 16 + read-write + 0x0 + 0x1 + + + PGAVSSEN + desc PGAVSSEN + 0 + 0 + read-write + + + + + + + ADC2 + desc ADC2 + 0x40040400 + + 0x0 + 0xB2 + registers + + + + STR + desc STR + 0x0 + 8 + read-write + 0x0 + 0x1 + + + STRT + desc STRT + 0 + 0 + read-write + + + + + CR0 + desc CR0 + 0x2 + 16 + read-write + 0x0 + 0x7F3 + + + MS + desc MS + 1 + 0 + read-write + + + ACCSEL + desc ACCSEL + 5 + 4 + read-write + + + CLREN + desc CLREN + 6 + 6 + read-write + + + DFMT + desc DFMT + 7 + 7 + read-write + + + AVCNT + desc AVCNT + 10 + 8 + read-write + + + + + CR1 + desc CR1 + 0x4 + 16 + read-write + 0x0 + 0x4 + + + RSCHSEL + desc RSCHSEL + 2 + 2 + read-write + + + + + TRGSR + desc TRGSR + 0xA + 16 + read-write + 0x0 + 0x8787 + + + TRGSELA + desc TRGSELA + 2 + 0 + read-write + + + TRGENA + desc TRGENA + 7 + 7 + read-write + + + TRGSELB + desc TRGSELB + 10 + 8 + read-write + + + TRGENB + desc TRGENB + 15 + 15 + read-write + + + + + CHSELRA + desc CHSELRA + 0xC + 32 + read-write + 0x0 + 0x1FF + + + CHSELA + desc CHSELA + 8 + 0 + read-write + + + + + CHSELRB + desc CHSELRB + 0x10 + 32 + read-write + 0x0 + 0x1FF + + + CHSELB + desc CHSELB + 8 + 0 + read-write + + + + + AVCHSELR + desc AVCHSELR + 0x14 + 32 + read-write + 0x0 + 0x1FF + + + AVCHSEL + desc AVCHSEL + 8 + 0 + read-write + + + + + SSTR0 + desc SSTR0 + 0x20 + 8 + read-write + 0xB + 0xFF + + + SSTR1 + desc SSTR1 + 0x21 + 8 + read-write + 0xB + 0xFF + + + SSTR2 + desc SSTR2 + 0x22 + 8 + read-write + 0xB + 0xFF + + + SSTR3 + desc SSTR3 + 0x23 + 8 + read-write + 0xB + 0xFF + + + SSTR4 + desc SSTR4 + 0x24 + 8 + read-write + 0xB + 0xFF + + + SSTR5 + desc SSTR5 + 0x25 + 8 + read-write + 0xB + 0xFF + + + SSTR6 + desc SSTR6 + 0x26 + 8 + read-write + 0xB + 0xFF + + + SSTR7 + desc SSTR7 + 0x27 + 8 + read-write + 0xB + 0xFF + + + SSTR8 + desc SSTR8 + 0x28 + 8 + read-write + 0xB + 0xFF + + + CHMUXR0 + desc CHMUXR0 + 0x38 + 16 + read-write + 0x3210 + 0xFFFF + + + CH00MUX + desc CH00MUX + 3 + 0 + read-write + + + CH01MUX + desc CH01MUX + 7 + 4 + read-write + + + CH02MUX + desc CH02MUX + 11 + 8 + read-write + + + CH03MUX + desc CH03MUX + 15 + 12 + read-write + + + + + CHMUXR1 + desc CHMUXR1 + 0x3A + 16 + read-write + 0x7654 + 0xFFFF + + + CH04MUX + desc CH04MUX + 3 + 0 + read-write + + + CH05MUX + desc CH05MUX + 7 + 4 + read-write + + + CH06MUX + desc CH06MUX + 11 + 8 + read-write + + + CH07MUX + desc CH07MUX + 15 + 12 + read-write + + + + + CHMUXR2 + desc CHMUXR2 + 0x3C + 16 + read-write + 0xBA98 + 0xF + + + CH08MUX + desc CH08MUX + 3 + 0 + read-write + + + + + ISR + desc ISR + 0x46 + 8 + read-write + 0x0 + 0x3 + + + EOCAF + desc EOCAF + 0 + 0 + read-write + + + EOCBF + desc EOCBF + 1 + 1 + read-write + + + + + ICR + desc ICR + 0x47 + 8 + read-write + 0x0 + 0x3 + + + EOCAIEN + desc EOCAIEN + 0 + 0 + read-write + + + EOCBIEN + desc EOCBIEN + 1 + 1 + read-write + + + + + DR0 + desc DR0 + 0x50 + 16 + read-only + 0x0 + 0xFFFF + + + DR1 + desc DR1 + 0x52 + 16 + read-only + 0x0 + 0xFFFF + + + DR2 + desc DR2 + 0x54 + 16 + read-only + 0x0 + 0xFFFF + + + DR3 + desc DR3 + 0x56 + 16 + read-only + 0x0 + 0xFFFF + + + DR4 + desc DR4 + 0x58 + 16 + read-only + 0x0 + 0xFFFF + + + DR5 + desc DR5 + 0x5A + 16 + read-only + 0x0 + 0xFFFF + + + DR6 + desc DR6 + 0x5C + 16 + read-only + 0x0 + 0xFFFF + + + DR7 + desc DR7 + 0x5E + 16 + read-only + 0x0 + 0xFFFF + + + DR8 + desc DR8 + 0x60 + 16 + read-only + 0x0 + 0xFFFF + + + AWDCR + desc AWDCR + 0xA0 + 16 + read-write + 0x0 + 0x1D1 + + + AWDEN + desc AWDEN + 0 + 0 + read-write + + + AWDMD + desc AWDMD + 4 + 4 + read-write + + + AWDSS + desc AWDSS + 7 + 6 + read-write + + + AWDIEN + desc AWDIEN + 8 + 8 + read-write + + + + + AWDDR0 + desc AWDDR0 + 0xA4 + 16 + read-write + 0x0 + 0xFFFF + + + AWDDR1 + desc AWDDR1 + 0xA6 + 16 + read-write + 0x0 + 0xFFFF + + + AWDCHSR + desc AWDCHSR + 0xAC + 32 + read-write + 0x0 + 0x1FF + + + AWDCH + desc AWDCH + 8 + 0 + read-write + + + + + AWDSR + desc AWDSR + 0xB0 + 32 + read-write + 0x0 + 0x1FF + + + AWDF + desc AWDF + 8 + 0 + read-write + + + + + + + AES + desc AES + 0x40008000 + + 0x0 + 0x30 + registers + + + + CR + desc CR + 0x0 + 32 + read-write + 0x0 + 0x3 + + + START + desc START + 0 + 0 + read-write + + + MODE + desc MODE + 1 + 1 + read-write + + + + + DR0 + desc DR0 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR1 + desc DR1 + 0x14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR2 + desc DR2 + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR3 + desc DR3 + 0x1C + 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32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL33 + desc SEL33 + 0xE0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL34 + desc SEL34 + 0xE4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL35 + desc SEL35 + 0xE8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL36 + desc SEL36 + 0xEC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL37 + desc SEL37 + 0xF0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL38 + desc SEL38 + 0xF4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL39 + desc SEL39 + 0xF8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL40 + desc SEL40 + 0xFC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL41 + desc SEL41 + 0x100 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL42 + desc SEL42 + 0x104 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL43 + desc SEL43 + 0x108 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL44 + desc SEL44 + 0x10C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL45 + desc SEL45 + 0x110 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL46 + desc SEL46 + 0x114 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL47 + desc SEL47 + 0x118 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL48 + desc SEL48 + 0x11C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL49 + 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0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL58 + desc SEL58 + 0x144 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL59 + desc SEL59 + 0x148 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL60 + desc SEL60 + 0x14C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL61 + desc SEL61 + 0x150 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL62 + desc SEL62 + 0x154 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL63 + desc SEL63 + 0x158 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL64 + desc SEL64 + 0x15C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL65 + desc SEL65 + 0x160 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + 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SEL116 + desc SEL116 + 0x22C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL117 + desc SEL117 + 0x230 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL118 + desc SEL118 + 0x234 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL119 + desc SEL119 + 0x238 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL120 + desc SEL120 + 0x23C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL121 + desc SEL121 + 0x240 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL122 + desc SEL122 + 0x244 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL123 + desc SEL123 + 0x248 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL124 + desc SEL124 + 0x24C + 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VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL130 + desc VSSEL130 + 0x264 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 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GATEHCLK + desc GATEHCLK + 1 + 1 + read-write + + + + + + + WDT + desc WDT + 0x40049000 + + 0x0 + 0xC + registers + + + + CR + desc CR + 0x0 + 32 + read-write + 0x80010FF3 + 0x80010FF3 + + + PERI + desc PERI + 1 + 0 + read-write + + + CKS + desc CKS + 7 + 4 + read-write + + + WDPT + desc WDPT + 11 + 8 + read-write + + + SLPOFF + desc SLPOFF + 16 + 16 + read-write + + + ITS + desc ITS + 31 + 31 + read-write + + + + + SR + desc SR + 0x4 + 32 + read-write + 0x0 + 0x3FFFF + + + CNT + desc CNT + 15 + 0 + read-only + + + UDF + desc UDF + 16 + 16 + read-write + + + REF + desc REF + 17 + 17 + read-write + + + + + RR + desc RR + 0x8 + 32 + read-write + 0x0 + 0xFFFF + + + RF + desc RF + 15 + 0 + read-write + + + + + + + diff --git a/mcu/cmsis/Device/HDSC/hc32f4xx/Source/system_hc32f460.c b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/system_hc32f460.c new file mode 100644 index 0000000..be46aca --- /dev/null +++ b/mcu/cmsis/Device/HDSC/hc32f4xx/Source/system_hc32f460.c @@ -0,0 +1,215 @@ +/** + ******************************************************************************* + * @file system_hc32f460.c + * @brief This file provides two functions and two global variables to be called + * from user application. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-10-31 CDT Delete the __low_level_init function of IAR and $Sub$$main function of MDK + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "system_hc32f460.h" + +/** + * @addtogroup CMSIS + * @{ + */ + +/** + * @addtogroup HC32F460_System + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ +/** + * @defgroup HC32F460_System_Local_Macros HC32F460 System Local Macros + * @{ + */ +#define HRC_16MHz_VALUE (16000000UL) /*!< Internal high speed RC freq. */ +#define HRC_20MHz_VALUE (20000000UL) /*!< Internal high speed RC freq. */ +/* HRC select */ +#define HRC_FREQ_MON() (*((volatile uint32_t *)(0x40010684UL))) + +/* Vector Table base offset field */ +#ifndef VECT_TAB_OFFSET +#define VECT_TAB_OFFSET (0x0UL) /*!< This value must be a multiple of 0x400. */ +#endif +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +/** + * @addtogroup HC32F460_System_Global_Variable + * @{ + */ + +/*!< System clock frequency (Core clock) */ +__NO_INIT uint32_t SystemCoreClock; +/*!< High speed RC frequency (HCR clock) */ +__NO_INIT uint32_t HRC_VALUE; + +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @addtogroup HC32F460_System_Global_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. Initialize the System and update + * the SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Configure the Vector Table relocation */ + + extern unsigned char Image$$ER_IROM1$$Base; + + uint32_t rom_base =0u; + + rom_base= (uint32_t)&Image$$ER_IROM1$$Base; + + /* FPU settings */ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20) | (3UL << 22)); /* set CP10 and CP11 Full Access */ +#endif + SystemCoreClockUpdate(); +#if defined (ROM_EXT_QSPI) + SystemInit_QspiMem(); +#endif /* ROM_EXT_QSPI */ + + + SCB->VTOR = rom_base; /* Vector Table Relocation */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint8_t u8SysClkSrc; + uint32_t plln; + uint32_t pllp; + uint32_t pllm; + uint32_t u32PllSrcFreq; + + /* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */ + if (1UL == (HRC_FREQ_MON() & 1UL)) { + HRC_VALUE = HRC_16MHz_VALUE; + } else { + HRC_VALUE = HRC_20MHz_VALUE; + } + u8SysClkSrc = CM_CMU->CKSWR & CMU_CKSWR_CKSW; + switch (u8SysClkSrc) { + case 0x00U: /* use internal high speed RC */ + SystemCoreClock = HRC_VALUE; + break; + case 0x01U: /* use internal middle speed RC */ + SystemCoreClock = MRC_VALUE; + break; + case 0x02U: /* use internal low speed RC */ + SystemCoreClock = LRC_VALUE; + break; + case 0x03U: /* use external high speed OSC */ + SystemCoreClock = XTAL_VALUE; + break; + case 0x04U: /* use external low speed OSC */ + SystemCoreClock = XTAL32_VALUE; + break; + case 0x05U: /* use MPLL */ + /* PLLCLK = ((pllsrc / pllm) * plln) / pllp */ + plln = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLN) >> CMU_PLLCFGR_MPLLN_POS; + pllp = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLP) >> CMU_PLLCFGR_MPLLP_POS; + pllm = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLM) >> CMU_PLLCFGR_MPLLM_POS; + if (0UL == (CM_CMU->PLLCFGR & CMU_PLLCFGR_PLLSRC)) { /* use external highspeed OSC as PLL source */ + u32PllSrcFreq = XTAL_VALUE; + } else { /* use internal high RC as PLL source */ + u32PllSrcFreq = HRC_VALUE; + } + SystemCoreClock = u32PllSrcFreq / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL); + break; + default: + break; + } +} + +#if defined (ROM_EXT_QSPI) +/** + * @brief Initialize the QSPI memory. + * @param None + * @retval None + */ +__WEAKDEF void SystemInit_QspiMem(void) +{ + /* QSPI configure */ + CM_GPIO->PWPR = 0xA501U; + /* High driver */ + CM_GPIO->PCRC7 = 0x0120U; + CM_GPIO->PCRC6 = 0x0120U; + CM_GPIO->PCRD8 = 0x0120U; + CM_GPIO->PCRD9 = 0x0120U; + CM_GPIO->PCRD10 = 0x0120U; + CM_GPIO->PCRD11 = 0x0120U; + /* Set function */ + CM_GPIO->PFSRC7 = 0x07U; + CM_GPIO->PFSRC6 = 0x07U; + CM_GPIO->PFSRD8 = 0x07U; + CM_GPIO->PFSRD9 = 0x07U; + CM_GPIO->PFSRD10 = 0x07U; + CM_GPIO->PFSRD11 = 0x07U; + /* qspi configure */ + CM_PWC->FCG1 &= ~0x00000008UL; + CM_QSPI->CR = 0x0002000D; + CM_QSPI->CSCR = 0x00000001; + CM_QSPI->FCR = 0x00008332; +} +#endif /* ROM_EXT_QSPI */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/cmsis/Include/arm_common_tables.h b/mcu/cmsis/Include/arm_common_tables.h new file mode 100644 index 0000000..721b18d --- /dev/null +++ b/mcu/cmsis/Include/arm_common_tables.h @@ -0,0 +1,517 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + /* Double Precision Float CFFT twiddles */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + extern const uint16_t armBitRevTable[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_16) + extern const uint64_t twiddleCoefF64_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_32) + extern const uint64_t twiddleCoefF64_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_64) + extern const uint64_t twiddleCoefF64_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_128) + extern const uint64_t twiddleCoefF64_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_256) + extern const uint64_t twiddleCoefF64_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_512) + extern const uint64_t twiddleCoefF64_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_1024) + extern const uint64_t twiddleCoefF64_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_2048) + extern const uint64_t twiddleCoefF64_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_4096) + extern const uint64_t twiddleCoefF64_4096[8192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) + extern const float32_t twiddleCoef_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + extern const float32_t twiddleCoef_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) + extern const float32_t twiddleCoef_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + extern const float32_t twiddleCoef_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) + extern const float32_t twiddleCoef_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + extern const float32_t twiddleCoef_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) + extern const float32_t twiddleCoef_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + extern const float32_t twiddleCoef_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + extern const float32_t twiddleCoef_4096[8192]; + #define twiddleCoef twiddleCoef_4096 + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) + extern const q31_t twiddleCoef_16_q31[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + extern const q31_t twiddleCoef_32_q31[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) + extern const q31_t twiddleCoef_64_q31[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + extern const q31_t twiddleCoef_128_q31[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) + extern const q31_t twiddleCoef_256_q31[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + extern const q31_t twiddleCoef_512_q31[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) + extern const q31_t twiddleCoef_1024_q31[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + extern const q31_t twiddleCoef_2048_q31[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) + extern const q31_t twiddleCoef_4096_q31[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) + extern const q15_t twiddleCoef_16_q15[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + extern const q15_t twiddleCoef_32_q15[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) + extern const q15_t twiddleCoef_64_q15[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + extern const q15_t twiddleCoef_128_q15[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) + extern const q15_t twiddleCoef_256_q15[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + extern const q15_t twiddleCoef_512_q15[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) + extern const q15_t twiddleCoef_1024_q15[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + extern const q15_t twiddleCoef_2048_q15[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) + extern const q15_t twiddleCoef_4096_q15[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + /* Double Precision Float RFFT twiddles */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32) + extern const uint64_t twiddleCoefF64_rfft_32[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64) + extern const uint64_t twiddleCoefF64_rfft_64[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128) + extern const uint64_t twiddleCoefF64_rfft_128[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256) + extern const uint64_t twiddleCoefF64_rfft_256[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512) + extern const uint64_t twiddleCoefF64_rfft_512[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024) + extern const uint64_t twiddleCoefF64_rfft_1024[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048) + extern const uint64_t twiddleCoefF64_rfft_2048[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096) + extern const uint64_t twiddleCoefF64_rfft_4096[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32) + extern const float32_t twiddleCoef_rfft_32[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64) + extern const float32_t twiddleCoef_rfft_64[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128) + extern const float32_t twiddleCoef_rfft_128[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256) + extern const float32_t twiddleCoef_rfft_256[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512) + extern const float32_t twiddleCoef_rfft_512[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024) + extern const float32_t twiddleCoef_rfft_1024[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048) + extern const float32_t twiddleCoef_rfft_2048[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096) + extern const float32_t twiddleCoef_rfft_4096[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + /* Double precision floating-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_16) + #define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_32) + #define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_64) + #define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_128) + #define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_256) + #define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_512) + #define ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_1024) + #define ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_2048) + #define ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_4096) + #define ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + /* floating-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16) + #define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) + extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32) + #define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) + extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64) + #define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128) + #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) + extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256) + #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) + extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512) + #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) + extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024) + #define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) + extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048) + #define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) + extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096) + #define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + /* fixed-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16) + #define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32) + #define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64) + #define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128) + #define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256) + #define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512) + #define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024) + #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048) + #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096) + #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32) + extern const float32_t realCoefA[8192]; + extern const float32_t realCoefB[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31) + extern const q31_t realCoefAQ31[8192]; + extern const q31_t realCoefBQ31[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15) + extern const q15_t realCoefAQ15[8192]; + extern const q15_t realCoefBQ15[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128) + extern const float32_t Weights_128[256]; + extern const float32_t cos_factors_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512) + extern const float32_t Weights_512[1024]; + extern const float32_t cos_factors_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048) + extern const float32_t Weights_2048[4096]; + extern const float32_t cos_factors_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192) + extern const float32_t Weights_8192[16384]; + extern const float32_t cos_factors_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128) + extern const q15_t WeightsQ15_128[256]; + extern const q15_t cos_factorsQ15_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512) + extern const q15_t WeightsQ15_512[1024]; + extern const q15_t cos_factorsQ15_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048) + extern const q15_t WeightsQ15_2048[4096]; + extern const q15_t cos_factorsQ15_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192) + extern const q15_t WeightsQ15_8192[16384]; + extern const q15_t cos_factorsQ15_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128) + extern const q31_t WeightsQ31_128[256]; + extern const q31_t cos_factorsQ31_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512) + extern const q31_t WeightsQ31_512[1024]; + extern const q31_t cos_factorsQ31_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048) + extern const q31_t WeightsQ31_2048[4096]; + extern const q31_t cos_factorsQ31_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192) + extern const q31_t WeightsQ31_8192[16384]; + extern const q31_t cos_factorsQ31_8192[8192]; + #endif + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15) + extern const q15_t armRecipTableQ15[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31) + extern const q31_t armRecipTableQ31[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + /* Tables for Fast Math Sine and Cosine */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) + extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) + extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15) + extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if defined(ARM_MATH_MVEI) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) + extern const q31_t sqrtTable_Q31[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + #endif + + #if defined(ARM_MATH_MVEI) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) + extern const q15_t sqrtTable_Q15[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + #endif + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */ + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + extern const float32_t exp_tab[8]; + extern const float32_t __logf_lut_f32[8]; +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) +extern const unsigned char hwLUT[256]; +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ + +#endif /* ARM_COMMON_TABLES_H */ + diff --git a/mcu/cmsis/Include/arm_const_structs.h b/mcu/cmsis/Include/arm_const_structs.h new file mode 100644 index 0000000..83984c4 --- /dev/null +++ b/mcu/cmsis/Include/arm_const_structs.h @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len16; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len32; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len64; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len128; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len256; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len512; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096; + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/mcu/cmsis/Include/arm_helium_utils.h b/mcu/cmsis/Include/arm_helium_utils.h new file mode 100644 index 0000000..7609d32 --- /dev/null +++ b/mcu/cmsis/Include/arm_helium_utils.h @@ -0,0 +1,348 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_helium_utils.h + * Description: Utility functions for Helium development + * + * $Date: 09. September 2019 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_UTILS_HELIUM_H_ +#define _ARM_UTILS_HELIUM_H_ + +/*************************************** + +Definitions available for MVEF and MVEI + +***************************************/ +#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) + +#define INACTIVELANE 0 /* inactive lane content */ + + +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) */ + +/*************************************** + +Definitions available for MVEF only + +***************************************/ +#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) + +__STATIC_FORCEINLINE float32_t vecAddAcrossF32Mve(float32x4_t in) +{ + float32_t acc; + + acc = vgetq_lane(in, 0) + vgetq_lane(in, 1) + + vgetq_lane(in, 2) + vgetq_lane(in, 3); + + return acc; +} + +/* newton initial guess */ +#define INVSQRT_MAGIC_F32 0x5f3759df + +#define INVSQRT_NEWTON_MVE_F32(invSqrt, xHalf, xStart)\ +{ \ + float32x4_t tmp; \ + \ + /* tmp = xhalf * x * x */ \ + tmp = vmulq(xStart, xStart); \ + tmp = vmulq(tmp, xHalf); \ + /* (1.5f - xhalf * x * x) */ \ + tmp = vsubq(vdupq_n_f32(1.5f), tmp); \ + /* x = x*(1.5f-xhalf*x*x); */ \ + invSqrt = vmulq(tmp, xStart); \ +} +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) */ + +/*************************************** + +Definitions available for MVEI only + +***************************************/ +#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) + + +#include "arm_common_tables.h" + +/* Following functions are used to transpose matrix in f32 and q31 cases */ +__STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve( + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + static const uint32x4_t vecOffs = { 0, 2, 1, 3 }; + /* + * + * | 0 1 | => | 0 2 | + * | 2 3 | | 1 3 | + * + */ + uint32x4_t vecIn = vldrwq_u32((uint32_t const *)pDataSrc); + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs, vecIn); + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve( + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; + const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; + /* + * + * | 0 1 2 | | 0 3 6 | 4 x 32 flattened version | 0 3 6 1 | + * | 3 4 5 | => | 1 4 7 | => | 4 7 2 5 | + * | 6 7 8 | | 2 5 8 | (row major) | 8 . . . | + * + */ + uint32x4_t vecIn1 = vldrwq_u32((uint32_t const *) pDataSrc); + uint32x4_t vecIn2 = vldrwq_u32((uint32_t const *) &pDataSrc[4]); + + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs1, vecIn1); + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs2, vecIn2); + + pDataDest[8] = pDataSrc[8]; + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint32_t * pDataDest) +{ + /* + * 4x4 Matrix transposition + * is 4 x de-interleave operation + * + * 0 1 2 3 0 4 8 12 + * 4 5 6 7 1 5 9 13 + * 8 9 10 11 2 6 10 14 + * 12 13 14 15 3 7 11 15 + */ + + uint32x4x4_t vecIn; + + vecIn = vld4q((uint32_t const *) pDataSrc); + vstrwq(pDataDest, vecIn.val[0]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[1]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[2]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[3]); + + return (ARM_MATH_SUCCESS); +} + + +__STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve( + uint16_t srcRows, + uint16_t srcCols, + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + uint32x4_t vecOffs; + uint32_t i; + uint32_t blkCnt; + uint32_t const *pDataC; + uint32_t *pDataDestR; + uint32x4_t vecIn; + + vecOffs = vidupq_u32((uint32_t)0, 1); + vecOffs = vecOffs * srcCols; + + i = srcCols; + do + { + pDataC = (uint32_t const *) pDataSrc; + pDataDestR = pDataDest; + + blkCnt = srcRows >> 2; + while (blkCnt > 0U) + { + vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs); + vstrwq(pDataDestR, vecIn); + pDataDestR += 4; + pDataC = pDataC + srcCols * 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = srcRows & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs); + vstrwq_p(pDataDestR, vecIn, p0); + } + + pDataSrc += 1; + pDataDest += srcRows; + } + while (--i); + + return (ARM_MATH_SUCCESS); +} + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) +__STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn) +{ + q63x2_t vecTmpLL; + q31x4_t vecTmp0, vecTmp1; + q31_t scale; + q63_t tmp64; + q31x4_t vecNrm, vecDst, vecIdx, vecSignBits; + + + vecSignBits = vclsq(vecIn); + vecSignBits = vbicq(vecSignBits, 1); + /* + * in = in << no_of_sign_bits; + */ + vecNrm = vshlq(vecIn, vecSignBits); + /* + * index = in >> 24; + */ + vecIdx = vecNrm >> 24; + vecIdx = vecIdx << 1; + + vecTmp0 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, vecIdx); + + vecIdx = vecIdx + 1; + + vecTmp1 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, vecIdx); + + vecTmp1 = vqrdmulhq(vecTmp1, vecNrm); + vecTmp0 = vecTmp0 - vecTmp1; + vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0); + vecTmp1 = vqrdmulhq(vecNrm, vecTmp1); + vecTmp1 = vdupq_n_s32(0x18000000) - vecTmp1; + vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1); + vecTmpLL = vmullbq_int(vecNrm, vecTmp0); + + /* + * scale elements 0, 2 + */ + scale = 26 + (vecSignBits[0] >> 1); + tmp64 = asrl(vecTmpLL[0], scale); + vecDst[0] = (q31_t) tmp64; + + scale = 26 + (vecSignBits[2] >> 1); + tmp64 = asrl(vecTmpLL[1], scale); + vecDst[2] = (q31_t) tmp64; + + vecTmpLL = vmulltq_int(vecNrm, vecTmp0); + + /* + * scale elements 1, 3 + */ + scale = 26 + (vecSignBits[1] >> 1); + tmp64 = asrl(vecTmpLL[0], scale); + vecDst[1] = (q31_t) tmp64; + + scale = 26 + (vecSignBits[3] >> 1); + tmp64 = asrl(vecTmpLL[1], scale); + vecDst[3] = (q31_t) tmp64; + /* + * set negative values to 0 + */ + vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s32(vecIn, 0)); + + return vecDst; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) +__STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn) +{ + q31x4_t vecTmpLev, vecTmpLodd, vecSignL; + q15x8_t vecTmp0, vecTmp1; + q15x8_t vecNrm, vecDst, vecIdx, vecSignBits; + + vecDst = vuninitializedq_s16(); + + vecSignBits = vclsq(vecIn); + vecSignBits = vbicq(vecSignBits, 1); + /* + * in = in << no_of_sign_bits; + */ + vecNrm = vshlq(vecIn, vecSignBits); + + vecIdx = vecNrm >> 8; + vecIdx = vecIdx << 1; + + vecTmp0 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, vecIdx); + + vecIdx = vecIdx + 1; + + vecTmp1 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, vecIdx); + + vecTmp1 = vqrdmulhq(vecTmp1, vecNrm); + vecTmp0 = vecTmp0 - vecTmp1; + vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0); + vecTmp1 = vqrdmulhq(vecNrm, vecTmp1); + vecTmp1 = vdupq_n_s16(0x1800) - vecTmp1; + vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1); + + vecSignBits = vecSignBits >> 1; + + vecTmpLev = vmullbq_int(vecNrm, vecTmp0); + vecTmpLodd = vmulltq_int(vecNrm, vecTmp0); + + vecTmp0 = vecSignBits + 10; + /* + * negate sign to apply register based vshl + */ + vecTmp0 = -vecTmp0; + + /* + * shift even elements + */ + vecSignL = vmovlbq(vecTmp0); + vecTmpLev = vshlq(vecTmpLev, vecSignL); + /* + * shift odd elements + */ + vecSignL = vmovltq(vecTmp0); + vecTmpLodd = vshlq(vecTmpLodd, vecSignL); + /* + * merge and narrow odd and even parts + */ + vecDst = vmovnbq_s32(vecDst, vecTmpLev); + vecDst = vmovntq_s32(vecDst, vecTmpLodd); + /* + * set negative values to 0 + */ + vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s16(vecIn, 0)); + + return vecDst; +} +#endif + +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) */ + +#endif diff --git a/mcu/cmsis/Include/arm_math.h b/mcu/cmsis/Include/arm_math.h new file mode 100644 index 0000000..48bee62 --- /dev/null +++ b/mcu/cmsis/Include/arm_math.h @@ -0,0 +1,8970 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP Library + * @version V1.7.0 + * @date 18. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M and Cortex-A processor + * based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filtering functions + * - Matrix functions + * - Transform functions + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * - Support Vector Machine functions (SVM) + * - Bayes classifier functions + * - Distance functions + * + * The library has generally separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * + * Here is the list of pre-built libraries : + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library is now tested on Fast Models building with cmake. + * Core M0, M7, A5 are tested. + * + * + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP\\Projects\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * There is also a work in progress cmake build. The README file is giving more details. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_LOOPUNROLL: + * + * Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions + * + * - ARM_MATH_NEON: + * + * Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions. + * It is not enabled by default when Neon is available because performances are + * dependent on the compiler and target architecture. + * + * - ARM_MATH_NEON_EXPERIMENTAL: + * + * Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of + * of some DSP functions. Experimental Neon versions currently do not have better + * performances than the scalar versions. + * + * - ARM_MATH_HELIUM: + * + * It implies the flags ARM_MATH_MVEF and ARM_MATH_MVEI and ARM_MATH_FLOAT16. + * + * - ARM_MATH_MVEF: + * + * Select Helium versions of the f32 algorithms. + * It implies ARM_MATH_FLOAT16 and ARM_MATH_MVEI. + * + * - ARM_MATH_MVEI: + * + * Select Helium versions of the int and fixed point algorithms. + * + * - ARM_MATH_FLOAT16: + * + * Float16 implementations of some algorithms (Requires MVE extension). + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |---------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP\\DSP_Lib_TestSuite | DSP_Lib test suite | + * |\b CMSIS\\DSP\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP\\Include | DSP_Lib include files | + * |\b CMSIS\\DSP\\Lib | DSP_Lib binaries | + * |\b CMSIS\\DSP\\Projects | Projects to rebuild DSP_Lib binaries | + * |\b CMSIS\\DSP\\Source | DSP_Lib source files | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to \ref arm_mat_init_f32(), \ref arm_mat_init_q31() and \ref arm_mat_init_q15() + * for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ + +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ + +/** + * @defgroup groupSVM SVM Functions + * This set of functions is implementing SVM classification on 2 classes. + * The training must be done from scikit-learn. The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/SVM.py + * + * If more than 2 classes are needed, the functions in this folder + * will have to be used, as building blocks, to do multi-class classification. + * + * No multi-class classification is provided in this SVM folder. + * + */ + + +/** + * @defgroup groupBayes Bayesian estimators + * + * Implement the naive gaussian Bayes estimator. + * The training must be done from scikit-learn. + * + * The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/Bayes.py + */ + +/** + * @defgroup groupDistance Distance functions + * + * Distance functions for use with clustering algorithms. + * There are distance functions for float vectors and boolean vectors. + * + */ + + +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wsign-conversion" + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + + +/* Included for instrinsics definitions */ +#if defined (_MSC_VER ) +#include +#define __STATIC_FORCEINLINE static __forceinline +#define __STATIC_INLINE static __inline +#define __ALIGNED(x) __declspec(align(x)) + +#elif defined (__GNUC_PYTHON__) +#include +#define __ALIGNED(x) __attribute__((aligned(x))) +#define __STATIC_FORCEINLINE static __attribute__((inline)) +#define __STATIC_INLINE static __attribute__((inline)) +#pragma GCC diagnostic ignored "-Wunused-function" +#pragma GCC diagnostic ignored "-Wattributes" + +#else +#include "cmsis_compiler.h" +#endif + + + +#include +#include +#include +#include + + +#define F64_MAX ((float64_t)DBL_MAX) +#define F32_MAX ((float32_t)FLT_MAX) + +#if defined(ARM_MATH_FLOAT16) +#define F16_MAX ((float16_t)FLT_MAX) +#endif + +#define F64_MIN (-DBL_MAX) +#define F32_MIN (-FLT_MAX) + +#if defined(ARM_MATH_FLOAT16) +#define F16_MIN (-(float16_t)FLT_MAX) +#endif + +#define F64_ABSMAX ((float64_t)DBL_MAX) +#define F32_ABSMAX ((float32_t)FLT_MAX) + +#if defined(ARM_MATH_FLOAT16) +#define F16_ABSMAX ((float16_t)FLT_MAX) +#endif + +#define F64_ABSMIN ((float64_t)0.0) +#define F32_ABSMIN ((float32_t)0.0) + +#if defined(ARM_MATH_FLOAT16) +#define F16_ABSMIN ((float16_t)0.0) +#endif + +#define Q31_MAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_MAX ((q15_t)(0x7FFF)) +#define Q7_MAX ((q7_t)(0x7F)) +#define Q31_MIN ((q31_t)(0x80000000L)) +#define Q15_MIN ((q15_t)(0x8000)) +#define Q7_MIN ((q7_t)(0x80)) + +#define Q31_ABSMAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_ABSMAX ((q15_t)(0x7FFF)) +#define Q7_ABSMAX ((q7_t)(0x7F)) +#define Q31_ABSMIN ((q31_t)0) +#define Q15_ABSMIN ((q15_t)0) +#define Q7_ABSMIN ((q7_t)0) + +/* evaluate ARM DSP feature */ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define ARM_MATH_DSP 1 +#endif + +#if defined(ARM_MATH_NEON) +#include +#endif + +#if defined (ARM_MATH_HELIUM) + #define ARM_MATH_MVEF + #define ARM_MATH_FLOAT16 +#endif + +#if defined (ARM_MATH_MVEF) + #define ARM_MATH_MVEI + #define ARM_MATH_FLOAT16 +#endif + +#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) +#include +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 ((q31_t)(0x100)) +#define DELTA_Q15 ((q15_t)0x5) +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macros for complex numbers + */ + + /* Dimension C vector space */ + #define CMPLX_DIM 2 + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief vector types + */ +#if defined(ARM_MATH_NEON) || defined (ARM_MATH_MVEI) + /** + * @brief 64-bit fractional 128-bit vector data type in 1.63 format + */ + typedef int64x2_t q63x2_t; + + /** + * @brief 32-bit fractional 128-bit vector data type in 1.31 format. + */ + typedef int32x4_t q31x4_t; + + /** + * @brief 16-bit fractional 128-bit vector data type with 16-bit alignement in 1.15 format. + */ + typedef __ALIGNED(2) int16x8_t q15x8_t; + + /** + * @brief 8-bit fractional 128-bit vector data type with 8-bit alignement in 1.7 format. + */ + typedef __ALIGNED(1) int8x16_t q7x16_t; + + /** + * @brief 32-bit fractional 128-bit vector pair data type in 1.31 format. + */ + typedef int32x4x2_t q31x4x2_t; + + /** + * @brief 32-bit fractional 128-bit vector quadruplet data type in 1.31 format. + */ + typedef int32x4x4_t q31x4x4_t; + + /** + * @brief 16-bit fractional 128-bit vector pair data type in 1.15 format. + */ + typedef int16x8x2_t q15x8x2_t; + + /** + * @brief 16-bit fractional 128-bit vector quadruplet data type in 1.15 format. + */ + typedef int16x8x4_t q15x8x4_t; + + /** + * @brief 8-bit fractional 128-bit vector pair data type in 1.7 format. + */ + typedef int8x16x2_t q7x16x2_t; + + /** + * @brief 8-bit fractional 128-bit vector quadruplet data type in 1.7 format. + */ + typedef int8x16x4_t q7x16x4_t; + + /** + * @brief 32-bit fractional data type in 9.23 format. + */ + typedef int32_t q23_t; + + /** + * @brief 32-bit fractional 128-bit vector data type in 9.23 format. + */ + typedef int32x4_t q23x4_t; + + /** + * @brief 64-bit status 128-bit vector data type. + */ + typedef int64x2_t status64x2_t; + + /** + * @brief 32-bit status 128-bit vector data type. + */ + typedef int32x4_t status32x4_t; + + /** + * @brief 16-bit status 128-bit vector data type. + */ + typedef int16x8_t status16x8_t; + + /** + * @brief 8-bit status 128-bit vector data type. + */ + typedef int8x16_t status8x16_t; + + +#endif + +#if defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF) /* floating point vector*/ + /** + * @brief 32-bit floating-point 128-bit vector type + */ + typedef float32x4_t f32x4_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit floating-point 128-bit vector data type + */ + typedef __ALIGNED(2) float16x8_t f16x8_t; +#endif + + /** + * @brief 32-bit floating-point 128-bit vector pair data type + */ + typedef float32x4x2_t f32x4x2_t; + + /** + * @brief 32-bit floating-point 128-bit vector quadruplet data type + */ + typedef float32x4x4_t f32x4x4_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit floating-point 128-bit vector pair data type + */ + typedef float16x8x2_t f16x8x2_t; + + /** + * @brief 16-bit floating-point 128-bit vector quadruplet data type + */ + typedef float16x8x4_t f16x8x4_t; +#endif + + /** + * @brief 32-bit ubiquitous 128-bit vector data type + */ + typedef union _any32x4_t + { + float32x4_t f; + int32x4_t i; + } any32x4_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit ubiquitous 128-bit vector data type + */ + typedef union _any16x8_t + { + float16x8_t f; + int16x8_t i; + } any16x8_t; +#endif + +#endif + +#if defined(ARM_MATH_NEON) + /** + * @brief 32-bit fractional 64-bit vector data type in 1.31 format. + */ + typedef int32x2_t q31x2_t; + + /** + * @brief 16-bit fractional 64-bit vector data type in 1.15 format. + */ + typedef __ALIGNED(2) int16x4_t q15x4_t; + + /** + * @brief 8-bit fractional 64-bit vector data type in 1.7 format. + */ + typedef __ALIGNED(1) int8x8_t q7x8_t; + + /** + * @brief 32-bit float 64-bit vector data type. + */ + typedef float32x2_t f32x2_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit float 64-bit vector data type. + */ + typedef __ALIGNED(2) float16x4_t f16x4_t; +#endif + + /** + * @brief 32-bit floating-point 128-bit vector triplet data type + */ + typedef float32x4x3_t f32x4x3_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit floating-point 128-bit vector triplet data type + */ + typedef float16x8x3_t f16x8x3_t; +#endif + + /** + * @brief 32-bit fractional 128-bit vector triplet data type in 1.31 format + */ + typedef int32x4x3_t q31x4x3_t; + + /** + * @brief 16-bit fractional 128-bit vector triplet data type in 1.15 format + */ + typedef int16x8x3_t q15x8x3_t; + + /** + * @brief 8-bit fractional 128-bit vector triplet data type in 1.7 format + */ + typedef int8x16x3_t q7x16x3_t; + + /** + * @brief 32-bit floating-point 64-bit vector pair data type + */ + typedef float32x2x2_t f32x2x2_t; + + /** + * @brief 32-bit floating-point 64-bit vector triplet data type + */ + typedef float32x2x3_t f32x2x3_t; + + /** + * @brief 32-bit floating-point 64-bit vector quadruplet data type + */ + typedef float32x2x4_t f32x2x4_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit floating-point 64-bit vector pair data type + */ + typedef float16x4x2_t f16x4x2_t; + + /** + * @brief 16-bit floating-point 64-bit vector triplet data type + */ + typedef float16x4x3_t f16x4x3_t; + + /** + * @brief 16-bit floating-point 64-bit vector quadruplet data type + */ + typedef float16x4x4_t f16x4x4_t; +#endif + + /** + * @brief 32-bit fractional 64-bit vector pair data type in 1.31 format + */ + typedef int32x2x2_t q31x2x2_t; + + /** + * @brief 32-bit fractional 64-bit vector triplet data type in 1.31 format + */ + typedef int32x2x3_t q31x2x3_t; + + /** + * @brief 32-bit fractional 64-bit vector quadruplet data type in 1.31 format + */ + typedef int32x4x3_t q31x2x4_t; + + /** + * @brief 16-bit fractional 64-bit vector pair data type in 1.15 format + */ + typedef int16x4x2_t q15x4x2_t; + + /** + * @brief 16-bit fractional 64-bit vector triplet data type in 1.15 format + */ + typedef int16x4x2_t q15x4x3_t; + + /** + * @brief 16-bit fractional 64-bit vector quadruplet data type in 1.15 format + */ + typedef int16x4x3_t q15x4x4_t; + + /** + * @brief 8-bit fractional 64-bit vector pair data type in 1.7 format + */ + typedef int8x8x2_t q7x8x2_t; + + /** + * @brief 8-bit fractional 64-bit vector triplet data type in 1.7 format + */ + typedef int8x8x3_t q7x8x3_t; + + /** + * @brief 8-bit fractional 64-bit vector quadruplet data type in 1.7 format + */ + typedef int8x8x4_t q7x8x4_t; + + /** + * @brief 32-bit ubiquitous 64-bit vector data type + */ + typedef union _any32x2_t + { + float32x2_t f; + int32x2_t i; + } any32x2_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit ubiquitous 64-bit vector data type + */ + typedef union _any16x4_t + { + float16x4_t f; + int16x4_t i; + } any16x4_t; +#endif + + /** + * @brief 32-bit status 64-bit vector data type. + */ + typedef int32x4_t status32x2_t; + + /** + * @brief 16-bit status 64-bit vector data type. + */ + typedef int16x8_t status16x4_t; + + /** + * @brief 8-bit status 64-bit vector data type. + */ + typedef int8x16_t status8x8_t; + +#endif + + + +/** + @brief definition to read/write two 16 bit values. + @deprecated + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __un(aligned) int32_t +#elif defined(_MSC_VER ) + #define __SIMD32_TYPE int32_t +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr)) +#define __SIMD64(addr) (*( int64_t **) & (addr)) + +#define STEP(x) (x) <= 0 ? 0 : 1 +#define SQ(x) ((x) * (x)) + +/* SIMD replacement */ + + +/** + @brief Read 2 Q15 from Q15 pointer. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2 ( + q15_t * pQ15) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, pQ15, 4); +#else + val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ; +#endif + + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_ia ( + q15_t ** pQ15) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, *pQ15, 4); +#else + val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF); +#endif + + *pQ15 += 2; + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_da ( + q15_t ** pQ15) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, *pQ15, 4); +#else + val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF); +#endif + + *pQ15 -= 2; + return (val); +} + +/** + @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2_ia ( + q15_t ** pQ15, + q31_t value) +{ + q31_t val = value; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (*pQ15, &val, 4); +#else + (*pQ15)[0] = (val & 0x0FFFF); + (*pQ15)[1] = (val >> 16) & 0x0FFFF; +#endif + + *pQ15 += 2; +} + +/** + @brief Write 2 Q15 to Q15 pointer. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2 ( + q15_t * pQ15, + q31_t value) +{ + q31_t val = value; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (pQ15, &val, 4); +#else + pQ15[0] = val & 0x0FFFF; + pQ15[1] = val >> 16; +#endif +} + + +/** + @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_ia ( + q7_t ** pQ7) +{ + q31_t val; + + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, *pQ7, 4); +#else + val =(((*pQ7)[3] & 0x0FF) << 24) | (((*pQ7)[2] & 0x0FF) << 16) | (((*pQ7)[1] & 0x0FF) << 8) | ((*pQ7)[0] & 0x0FF); +#endif + + *pQ7 += 4; + + return (val); +} + +/** + @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_da ( + q7_t ** pQ7) +{ + q31_t val; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, *pQ7, 4); +#else + val = ((((*pQ7)[3]) & 0x0FF) << 24) | ((((*pQ7)[2]) & 0x0FF) << 16) | ((((*pQ7)[1]) & 0x0FF) << 8) | ((*pQ7)[0] & 0x0FF); +#endif + *pQ7 -= 4; + + return (val); +} + +/** + @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q7x4_ia ( + q7_t ** pQ7, + q31_t value) +{ + q31_t val = value; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (*pQ7, &val, 4); +#else + (*pQ7)[0] = val & 0x0FF; + (*pQ7)[1] = (val >> 8) & 0x0FF; + (*pQ7)[2] = (val >> 16) & 0x0FF; + (*pQ7)[3] = (val >> 24) & 0x0FF; + +#endif + *pQ7 += 4; +} + +/* + +Normally those kind of definitions are in a compiler file +in Core or Core_A. + +But for MSVC compiler it is a bit special. The goal is very specific +to CMSIS-DSP and only to allow the use of this library from other +systems like Python or Matlab. + +MSVC is not going to be used to cross-compile to ARM. So, having a MSVC +compiler file in Core or Core_A would not make sense. + +*/ +#if defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) + __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#ifndef ARM_MATH_DSP + /** + * @brief definition to pack two 16 bit values. + */ + #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) + #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) +#endif + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + __STATIC_FORCEINLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + __STATIC_FORCEINLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + __STATIC_FORCEINLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y) ) ); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + const q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + const q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + +/** + * @brief Integer exponentiation + * @param[in] x value + * @param[in] nb integer exponent >= 1 + * @return x^nb + * + */ +__STATIC_INLINE float32_t arm_exponent_f32(float32_t x, int32_t nb) +{ + float32_t r = x; + nb --; + while(nb > 0) + { + r = r * x; + nb--; + } + return(r); +} + +/** + * @brief 64-bit to 32-bit unsigned normalization + * @param[in] in is input unsigned long long value + * @param[out] normalized is the 32-bit normalized value + * @param[out] norm is norm scale + */ +__STATIC_INLINE void arm_norm_64_to_32u(uint64_t in, int32_t * normalized, int32_t *norm) +{ + int32_t n1; + int32_t hi = (int32_t) (in >> 32); + int32_t lo = (int32_t) ((in << 32) >> 32); + + n1 = __CLZ(hi) - 32; + if (!n1) + { + /* + * input fits in 32-bit + */ + n1 = __CLZ(lo); + if (!n1) + { + /* + * MSB set, need to scale down by 1 + */ + *norm = -1; + *normalized = (((uint32_t) lo) >> 1); + } else + { + if (n1 == 32) + { + /* + * input is zero + */ + *norm = 0; + *normalized = 0; + } else + { + /* + * 32-bit normalization + */ + *norm = n1 - 1; + *normalized = lo << *norm; + } + } + } else + { + /* + * input fits in 64-bit + */ + n1 = 1 - n1; + *norm = -n1; + /* + * 64 bit normalization + */ + *normalized = (((uint32_t) lo) >> n1) | (hi << (32 - n1)); + } +} + +__STATIC_INLINE q31_t arm_div_q63_to_q31(q63_t num, q31_t den) +{ + q31_t result; + uint64_t absNum; + int32_t normalized; + int32_t norm; + + /* + * if sum fits in 32bits + * avoid costly 64-bit division + */ + absNum = num > 0 ? num : -num; + arm_norm_64_to_32u(absNum, &normalized, &norm); + if (norm > 0) + /* + * 32-bit division + */ + result = (q31_t) num / den; + else + /* + * 64-bit division + */ + result = (q31_t) (num / den); + + return result; +} + + +/* + * @brief C custom defined intrinsic functions + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 + */ + __STATIC_FORCEINLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 + */ + __STATIC_FORCEINLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 + */ + __STATIC_FORCEINLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 + */ + __STATIC_FORCEINLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 + */ + __STATIC_FORCEINLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 + */ + __STATIC_FORCEINLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX + */ + __STATIC_FORCEINLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX + */ + __STATIC_FORCEINLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX + */ + __STATIC_FORCEINLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX + */ + __STATIC_FORCEINLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX + */ + __STATIC_FORCEINLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX + */ + __STATIC_FORCEINLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD + */ + __STATIC_FORCEINLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB + */ + __STATIC_FORCEINLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD + */ + __STATIC_FORCEINLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX + */ + __STATIC_FORCEINLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX + */ + __STATIC_FORCEINLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD + */ + __STATIC_FORCEINLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX + */ + __STATIC_FORCEINLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD + */ + __STATIC_FORCEINLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD + */ + __STATIC_FORCEINLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 + */ + __STATIC_FORCEINLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA + */ + __STATIC_FORCEINLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter (fast version). + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns either + * ARM_MATH_SUCCESS if initialization was successful or + * ARM_MATH_ARGUMENT_ERROR if numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter (fast version). + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + /** + * @brief Instance structure for the modified Biquad coefs required by vectorized code. + */ + typedef struct + { + float32_t coeffs[8][4]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */ + } arm_biquad_mod_coef_f32; +#endif + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + const q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pCoeffsMod points to the modified filter coefficients (only MVE version). + * @param[in] pState points to the state buffer. + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + void arm_biquad_cascade_df1_mve_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + arm_biquad_mod_coef_f32 * pCoeffsMod, + float32_t * pState); +#endif + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u16( + const uint16_t * pSrc, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u32( + const uint32_t * pSrc, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u8( + const uint8_t * pSrc, + uint8_t * pDst, + uint32_t blockSize); + +/** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Struct for specifying sorting algorithm + */ + typedef enum + { + ARM_SORT_BITONIC = 0, + /**< Bitonic sort */ + ARM_SORT_BUBBLE = 1, + /**< Bubble sort */ + ARM_SORT_HEAP = 2, + /**< Heap sort */ + ARM_SORT_INSERTION = 3, + /**< Insertion sort */ + ARM_SORT_QUICK = 4, + /**< Quick sort */ + ARM_SORT_SELECTION = 5 + /**< Selection sort */ + } arm_sort_alg; + + /** + * @brief Struct for specifying sorting algorithm + */ + typedef enum + { + ARM_SORT_DESCENDING = 0, + /**< Descending order (9 to 0) */ + ARM_SORT_ASCENDING = 1 + /**< Ascending order (0 to 9) */ + } arm_sort_dir; + + /** + * @brief Instance structure for the sorting algorithms. + */ + typedef struct + { + arm_sort_alg alg; /**< Sorting algorithm selected */ + arm_sort_dir dir; /**< Sorting order (direction) */ + } arm_sort_instance_f32; + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] alg Selected algorithm. + * @param[in] dir Sorting order. + */ + void arm_sort_init_f32( + arm_sort_instance_f32 * S, + arm_sort_alg alg, + arm_sort_dir dir); + + /** + * @brief Instance structure for the sorting algorithms. + */ + typedef struct + { + arm_sort_dir dir; /**< Sorting order (direction) */ + float32_t * buffer; /**< Working buffer */ + } arm_merge_sort_instance_f32; + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in,out] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_merge_sort_f32( + const arm_merge_sort_instance_f32 * S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] dir Sorting order. + * @param[in] buffer Working buffer. + */ + void arm_merge_sort_init_f32( + arm_merge_sort_instance_f32 * S, + arm_sort_dir dir, + float32_t * buffer); + + /** + * @brief Struct for specifying cubic spline type + */ + typedef enum + { + ARM_SPLINE_NATURAL = 0, /**< Natural spline */ + ARM_SPLINE_PARABOLIC_RUNOUT = 1 /**< Parabolic runout spline */ + } arm_spline_type; + + /** + * @brief Instance structure for the floating-point cubic spline interpolation. + */ + typedef struct + { + arm_spline_type type; /**< Type (boundary conditions) */ + const float32_t * x; /**< x values */ + const float32_t * y; /**< y values */ + uint32_t n_x; /**< Number of known data points */ + float32_t * coeffs; /**< Coefficients buffer (b,c, and d) */ + } arm_spline_instance_f32; + + /** + * @brief Processing function for the floating-point cubic spline interpolation. + * @param[in] S points to an instance of the floating-point spline structure. + * @param[in] xq points to the x values ot the interpolated data points. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples of output data. + */ + void arm_spline_f32( + arm_spline_instance_f32 * S, + const float32_t * xq, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point cubic spline interpolation. + * @param[in,out] S points to an instance of the floating-point spline structure. + * @param[in] type type of cubic spline interpolation (boundary conditions) + * @param[in] x points to the x values of the known data points. + * @param[in] y points to the y values of the known data points. + * @param[in] n number of known data points. + * @param[in] coeffs coefficients array for b, c, and d + * @param[in] tempBuffer buffer array for internal computations + */ + void arm_spline_init_f32( + arm_spline_instance_f32 * S, + arm_spline_type type, + const float32_t * x, + const float32_t * y, + uint32_t n, + float32_t * coeffs, + float32_t * tempBuffer); + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEI) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const q15_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const q15_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const q15_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_q15; + +arm_status arm_cfft_init_q15( + arm_cfft_instance_q15 * S, + uint16_t fftLen); + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEI) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const q31_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const q31_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const q31_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_q31; + +arm_status arm_cfft_init_q31( + arm_cfft_instance_q31 * S, + uint16_t fftLen); + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const float32_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const float32_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const float32_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_f32; + + + arm_status arm_cfft_init_f32( + arm_cfft_instance_f32 * S, + uint16_t fftLen); + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + + /** + * @brief Instance structure for the Double Precision Floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float64_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f64; + + void arm_cfft_f64( + const arm_cfft_instance_f64 * S, + float64_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ +#if defined(ARM_MATH_MVEI) + arm_cfft_instance_q15 cfftInst; +#else + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ +#endif + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ +#if defined(ARM_MATH_MVEI) + arm_cfft_instance_q31 cfftInst; +#else + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ +#endif + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the Double Precision Floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f64 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float64_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f64 ; + +arm_status arm_rfft_fast_init_f64 ( + arm_rfft_fast_instance_f64 * S, + uint16_t fftLen); + + +void arm_rfft_fast_f64( + arm_rfft_fast_instance_f64 * S, + float64_t * p, float64_t * pOut, + uint8_t ifftFlag); + + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + + + void arm_rfft_fast_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + const float32_t *pTwiddle; /**< points to the twiddle factor table. */ + const float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + const float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + const q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + const q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + +/** + @brief Instance structure for floating-point FIR decimator. + */ +typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + +/** + @brief Processing function for floating-point FIR decimator. + @param[in] S points to an instance of the floating-point FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + */ +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + @brief Initialization function for the floating-point FIR decimator. + @param[in,out] S points to an instance of the floating-point FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + */ +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + +#if defined(ARM_MATH_NEON) +void arm_biquad_cascade_df2T_compute_coefs_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs); +#endif + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + const float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + const q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + const q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + +/** + @brief Correlation of Q15 sequences + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +*/ +void arm_correlate_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ +void arm_correlate_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ +void arm_correlate_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + +/** + @brief Correlation of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+   *
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return processed output sample. + */ + __STATIC_FORCEINLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + +/** + @brief Process function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ +__STATIC_FORCEINLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + +/** + @brief Process function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ +__STATIC_FORCEINLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((q31_t)(acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @return none + */ + __STATIC_FORCEINLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + +/** + @brief Clarke transform for Q31 version + @param[in] Ia input three-phase coordinate a + @param[in] Ib input three-phase coordinate b + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + +/** + @brief Inverse Clarke transform for Q31 version + @param[in] Ialpha input two-phase orthogonal vector axis alpha + @param[in] Ibeta input two-phase orthogonal vector axis beta + @param[out] pIa points to output three-phase coordinate a + @param[out] pIb points to output three-phase coordinate b + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + * + * The function implements the forward Park transform. + * + */ + __STATIC_FORCEINLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + +/** + @brief Park transform for Q31 version + @param[in] Ialpha input two-phase vector coordinate alpha + @param[in] Ibeta input two-phase vector coordinate beta + @param[out] pId points to output rotor reference frame d + @param[out] pIq points to output rotor reference frame q + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + +/** + @brief Inverse Park transform for Q31 version + @param[in] Id input coordinate of rotor reference frame d + @param[in] Iq input coordinate of rotor reference frame q + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + __STATIC_FORCEINLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= (S->nValues - 1)) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + __STATIC_FORCEINLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + __STATIC_FORCEINLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + __STATIC_FORCEINLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + +/** + @brief Floating-point vector of log values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vlog_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +/** + @brief Floating-point vector of exp values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vexp_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + +/** + @brief Floating-point square root function. + @param[in] in input value + @param[out] pOut square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +__STATIC_FORCEINLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + *pOut = __sqrtf(in); + #else + *pOut = sqrtf(in); + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); + #else + *pOut = sqrtf(in); + #endif + +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + +/** + @brief Q31 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + +/** + @brief Q15 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @brief Vector Floating-point square root function. + * @param[in] pIn input vector. + * @param[out] pOut vector of square roots of input elements. + * @param[in] len length of input vector. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + void arm_vsqrt_f32( + float32_t * pIn, + float32_t * pOut, + uint16_t len); + + void arm_vsqrt_q31( + q31_t * pIn, + q31_t * pOut, + uint16_t len); + + void arm_vsqrt_q15( + q15_t * pIn, + q15_t * pOut, + uint16_t len); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset; + int32_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q15_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q7_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +/** + * @brief Struct for specifying SVM Kernel + */ +typedef enum +{ + ARM_ML_KERNEL_LINEAR = 0, + /**< Linear kernel */ + ARM_ML_KERNEL_POLYNOMIAL = 1, + /**< Polynomial kernel */ + ARM_ML_KERNEL_RBF = 2, + /**< Radial Basis Function kernel */ + ARM_ML_KERNEL_SIGMOID = 3 + /**< Sigmoid kernel */ +} arm_ml_kernel_type; + + +/** + * @brief Instance structure for linear SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ +} arm_svm_linear_instance_f32; + + +/** + * @brief Instance structure for polynomial SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + int32_t degree; /**< Polynomial degree */ + float32_t coef0; /**< Polynomial constant */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_polynomial_instance_f32; + +/** + * @brief Instance structure for rbf SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_rbf_instance_f32; + +/** + * @brief Instance structure for sigmoid SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t coef0; /**< Independant constant */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_sigmoid_instance_f32; + +/** + * @brief SVM linear instance init function + * @param[in] S Parameters for SVM functions + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes); + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +void arm_svm_linear_predict_f32(const arm_svm_linear_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief SVM polynomial instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + int32_t degree, + float32_t coef0, + float32_t gamma + ); + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_polynomial_predict_f32(const arm_svm_polynomial_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief SVM radial basis function instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t gamma + ); + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ +void arm_svm_rbf_predict_f32(const arm_svm_rbf_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + +/** + * @brief SVM sigmoid instance init function + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t coef0, + float32_t gamma + ); + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_sigmoid_predict_f32(const arm_svm_sigmoid_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + + +/** + * @brief Instance structure for Naive Gaussian Bayesian estimator. + */ +typedef struct +{ + uint32_t vectorDimension; /**< Dimension of vector space */ + uint32_t numberOfClasses; /**< Number of different classes */ + const float32_t *theta; /**< Mean values for the Gaussians */ + const float32_t *sigma; /**< Variances for the Gaussians */ + const float32_t *classPriors; /**< Class prior probabilities */ + float32_t epsilon; /**< Additive value to variances */ +} arm_gaussian_naive_bayes_instance_f32; + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] S points to a naive bayes instance structure + * @param[in] in points to the elements of the input vector. + * @param[in] pBuffer points to a buffer of length numberOfClasses + * @return The predicted class + * + */ + + +uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S, + const float32_t * in, + float32_t *pBuffer); + +/** + * @brief Computation of the LogSumExp + * + * In probabilistic computations, the dynamic of the probability values can be very + * wide because they come from gaussian functions. + * To avoid underflow and overflow issues, the values are represented by their log. + * In this representation, multiplying the original exp values is easy : their logs are added. + * But adding the original exp values is requiring some special handling and it is the + * goal of the LogSumExp function. + * + * If the values are x1...xn, the function is computing: + * + * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that + * rounding issues are minimised. + * + * The max xm of the values is extracted and the function is computing: + * xm + ln(exp(x1 - xm) + ... + exp(xn - xm)) + * + * @param[in] *in Pointer to an array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return LogSumExp + * + */ + + +float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize); + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product . + * + */ + + +float32_t arm_logsumexp_dot_prod_f32(const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t *pTmpBuffer); + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize); + + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float64_t arm_entropy_f64(const float64_t * pSrcA, uint32_t blockSize); + + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float32_t arm_kullback_leibler_f32(const float32_t * pSrcA + ,const float32_t * pSrcB + ,uint32_t blockSize); + + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, + const float64_t * pSrcB, + uint32_t blockSize); + + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ +float32_t arm_weighted_sum_f32(const float32_t *in + , const float32_t *weigths + , uint32_t blockSize); + + +/** + * @brief Barycenter + * + * + * @param[in] in List of vectors + * @param[in] weights Weights of the vectors + * @param[out] out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ +void arm_barycenter_f32(const float32_t *in + , const float32_t *weights + , float32_t *out + , uint32_t nbVectors + , uint32_t vecDim); + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize); + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x 0 and y 0, + * it will compute the right value (0) but a division per zero will occur + * and shoudl be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB,uint32_t blockSize); + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] n Norm order (>= 2) + * @param[in] blockSize vector length + * @return distance + * + */ + + + +float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize); + +/** + * @brief Dice distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] order Distance order + * @param[in] blockSize Number of samples + * @return distance + * + */ + + +float32_t arm_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Hamming distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Jaccard distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Kulsinski distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Roger Stanimoto distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Russell-Rao distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Sokal-Michener distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Sokal-Sneath distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Yule distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numCols - 2) || yIndex < 0 || yIndex > (S->numRows - 2)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex ) + (yIndex ) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex ) + (yIndex+1) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0x0FFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0x0FFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0x0FFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0x0FFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT +#endif + + + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/mcu/cmsis/Include/arm_mve_tables.h b/mcu/cmsis/Include/arm_mve_tables.h new file mode 100644 index 0000000..4d2c135 --- /dev/null +++ b/mcu/cmsis/Include/arm_mve_tables.h @@ -0,0 +1,235 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mve_tables.h + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * $Date: 08. January 2020 + * $Revision: V1.7.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #ifndef _ARM_MVE_TABLES_H + #define _ARM_MVE_TABLES_H + + #include "arm_math.h" + + + + + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2]; +extern float32_t rearranged_twiddle_stride1_16_f32[8]; +extern float32_t rearranged_twiddle_stride2_16_f32[8]; +extern float32_t rearranged_twiddle_stride3_16_f32[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3]; +extern float32_t rearranged_twiddle_stride1_64_f32[40]; +extern float32_t rearranged_twiddle_stride2_64_f32[40]; +extern float32_t rearranged_twiddle_stride3_64_f32[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4]; +extern float32_t rearranged_twiddle_stride1_256_f32[168]; +extern float32_t rearranged_twiddle_stride2_256_f32[168]; +extern float32_t rearranged_twiddle_stride3_256_f32[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5]; +extern float32_t rearranged_twiddle_stride1_1024_f32[680]; +extern float32_t rearranged_twiddle_stride2_1024_f32[680]; +extern float32_t rearranged_twiddle_stride3_1024_f32[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6]; +extern float32_t rearranged_twiddle_stride1_4096_f32[2728]; +extern float32_t rearranged_twiddle_stride2_4096_f32[2728]; +extern float32_t rearranged_twiddle_stride3_4096_f32[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + + +#if defined(ARM_MATH_MVEI) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2]; +extern q31_t rearranged_twiddle_stride1_16_q31[8]; +extern q31_t rearranged_twiddle_stride2_16_q31[8]; +extern q31_t rearranged_twiddle_stride3_16_q31[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3]; +extern q31_t rearranged_twiddle_stride1_64_q31[40]; +extern q31_t rearranged_twiddle_stride2_64_q31[40]; +extern q31_t rearranged_twiddle_stride3_64_q31[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4]; +extern q31_t rearranged_twiddle_stride1_256_q31[168]; +extern q31_t rearranged_twiddle_stride2_256_q31[168]; +extern q31_t rearranged_twiddle_stride3_256_q31[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5]; +extern q31_t rearranged_twiddle_stride1_1024_q31[680]; +extern q31_t rearranged_twiddle_stride2_1024_q31[680]; +extern q31_t rearranged_twiddle_stride3_1024_q31[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6]; +extern q31_t rearranged_twiddle_stride1_4096_q31[2728]; +extern q31_t rearranged_twiddle_stride2_4096_q31[2728]; +extern q31_t rearranged_twiddle_stride3_4096_q31[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#if defined(ARM_MATH_MVEI) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2]; +extern q15_t rearranged_twiddle_stride1_16_q15[8]; +extern q15_t rearranged_twiddle_stride2_16_q15[8]; +extern q15_t rearranged_twiddle_stride3_16_q15[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3]; +extern q15_t rearranged_twiddle_stride1_64_q15[40]; +extern q15_t rearranged_twiddle_stride2_64_q15[40]; +extern q15_t rearranged_twiddle_stride3_64_q15[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4]; +extern q15_t rearranged_twiddle_stride1_256_q15[168]; +extern q15_t rearranged_twiddle_stride2_256_q15[168]; +extern q15_t rearranged_twiddle_stride3_256_q15[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5]; +extern q15_t rearranged_twiddle_stride1_1024_q15[680]; +extern q15_t rearranged_twiddle_stride2_1024_q15[680]; +extern q15_t rearranged_twiddle_stride3_1024_q15[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6]; +extern q15_t rearranged_twiddle_stride1_4096_q15[2728]; +extern q15_t rearranged_twiddle_stride2_4096_q15[2728]; +extern q15_t rearranged_twiddle_stride3_4096_q15[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#if defined(ARM_MATH_MVEI) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#endif /*_ARM_MVE_TABLES_H*/ + diff --git a/mcu/cmsis/Include/arm_vec_math.h b/mcu/cmsis/Include/arm_vec_math.h new file mode 100644 index 0000000..0ce9464 --- /dev/null +++ b/mcu/cmsis/Include/arm_vec_math.h @@ -0,0 +1,372 @@ +/****************************************************************************** + * @file arm_vec_math.h + * @brief Public header file for CMSIS DSP Library + * @version V1.7.0 + * @date 15. October 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_VEC_MATH_H +#define _ARM_VEC_MATH_H + +#include "arm_math.h" +#include "arm_common_tables.h" +#include "arm_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define INV_NEWTON_INIT_F32 0x7EF127EA + +static const float32_t __logf_rng_f32=0.693147180f; + + +/* fast inverse approximation (3x newton) */ +__STATIC_INLINE f32x4_t vrecip_medprec_f32( + f32x4_t x) +{ + q31x4_t m; + f32x4_t b; + any32x4_t xinv; + f32x4_t ax = vabsq(x); + + xinv.f = ax; + m = 0x3F800000 - (xinv.i & 0x7F800000); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f - 0.47058824f * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f)); + + return xinv.f; +} + +/* fast inverse approximation (4x newton) */ +__STATIC_INLINE f32x4_t vrecip_hiprec_f32( + f32x4_t x) +{ + q31x4_t m; + f32x4_t b; + any32x4_t xinv; + f32x4_t ax = vabsq(x); + + xinv.f = ax; + + m = 0x3F800000 - (xinv.i & 0x7F800000); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f - 0.47058824f * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f)); + + return xinv.f; +} + +__STATIC_INLINE f32x4_t vdiv_f32( + f32x4_t num, f32x4_t den) +{ + return vmulq(num, vrecip_hiprec_f32(den)); +} + +/** + @brief Single-precision taylor dev. + @param[in] x f32 quad vector input + @param[in] coeffs f32 quad vector coeffs + @return destination f32 quad vector + */ + +__STATIC_INLINE f32x4_t vtaylor_polyq_f32( + f32x4_t x, + const float32_t * coeffs) +{ + f32x4_t A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]); + f32x4_t B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]); + f32x4_t C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]); + f32x4_t D = vfmasq(vdupq_n_f32(coeffs[7]), x, coeffs[3]); + f32x4_t x2 = vmulq(x, x); + f32x4_t x4 = vmulq(x2, x2); + f32x4_t res = vfmaq(vfmaq_f32(A, B, x2), vfmaq_f32(C, D, x2), x4); + + return res; +} + +__STATIC_INLINE f32x4_t vmant_exp_f32( + f32x4_t x, + int32x4_t * e) +{ + any32x4_t r; + int32x4_t n; + + r.f = x; + n = r.i >> 23; + n = n - 127; + r.i = r.i - (n << 23); + + *e = n; + return r.f; +} + + +__STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn) +{ + q31x4_t vecExpUnBiased; + f32x4_t vecTmpFlt0, vecTmpFlt1; + f32x4_t vecAcc0, vecAcc1, vecAcc2, vecAcc3; + f32x4_t vecExpUnBiasedFlt; + + /* + * extract exponent + */ + vecTmpFlt1 = vmant_exp_f32(vecIn, &vecExpUnBiased); + + vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1; + /* + * a = (__logf_lut_f32[4] * r.f) + (__logf_lut_f32[0]); + */ + vecAcc0 = vdupq_n_f32(__logf_lut_f32[0]); + vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f32[4]); + /* + * b = (__logf_lut_f32[6] * r.f) + (__logf_lut_f32[2]); + */ + vecAcc1 = vdupq_n_f32(__logf_lut_f32[2]); + vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f32[6]); + /* + * c = (__logf_lut_f32[5] * r.f) + (__logf_lut_f32[1]); + */ + vecAcc2 = vdupq_n_f32(__logf_lut_f32[1]); + vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f32[5]); + /* + * d = (__logf_lut_f32[7] * r.f) + (__logf_lut_f32[3]); + */ + vecAcc3 = vdupq_n_f32(__logf_lut_f32[3]); + vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f32[7]); + /* + * a = a + b * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0); + /* + * c = c + d * xx; + */ + vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0); + /* + * xx = xx * xx; + */ + vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0; + vecExpUnBiasedFlt = vcvtq_f32_s32(vecExpUnBiased); + /* + * r.f = a + c * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0); + /* + * add exponent + * r.f = r.f + ((float32_t) m) * __logf_rng_f32; + */ + vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f32); + // set log0 down to -inf + vecAcc0 = vdupq_m(vecAcc0, -INFINITY, vcmpeqq(vecIn, 0.0f)); + return vecAcc0; +} + +__STATIC_INLINE f32x4_t vexpq_f32( + f32x4_t x) +{ + // Perform range reduction [-log(2),log(2)] + int32x4_t m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f)); + f32x4_t val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f)); + + // Polynomial Approximation + f32x4_t poly = vtaylor_polyq_f32(val, exp_tab); + + // Reconstruct + poly = (f32x4_t) (vqaddq_s32((q31x4_t) (poly), vqshlq_n_s32(m, 23))); + + poly = vdupq_m(poly, 0.0f, vcmpltq_n_s32(m, -126)); + return poly; +} + +__STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb) +{ + f32x4_t r = x; + nb--; + while (nb > 0) { + r = vmulq(r, x); + nb--; + } + return (r); +} + +__STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn) +{ + f32x4_t vecSx, vecW, vecTmp; + any32x4_t v; + + vecSx = vabsq(vecIn); + + v.f = vecIn; + v.i = vsubq(vdupq_n_s32(INV_NEWTON_INIT_F32), v.i); + + vecW = vmulq(vecSx, v.f); + + // v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w))))))); + vecTmp = vsubq(vdupq_n_f32(8.0f), vecW); + vecTmp = vfmasq(vecW, vecTmp, -28.0f); + vecTmp = vfmasq(vecW, vecTmp, 56.0f); + vecTmp = vfmasq(vecW, vecTmp, -70.0f); + vecTmp = vfmasq(vecW, vecTmp, 56.0f); + vecTmp = vfmasq(vecW, vecTmp, -28.0f); + vecTmp = vfmasq(vecW, vecTmp, 8.0f); + v.f = vmulq(v.f, vecTmp); + + v.f = vdupq_m(v.f, INFINITY, vcmpeqq(vecIn, 0.0f)); + /* + * restore sign + */ + v.f = vnegq_m(v.f, v.f, vcmpltq(vecIn, 0.0f)); + return v.f; +} + +__STATIC_INLINE f32x4_t vtanhq_f32( + f32x4_t val) +{ + f32x4_t x = + vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f)); + f32x4_t exp2x = vexpq_f32(vmulq_n_f32(x, 2.f)); + f32x4_t num = vsubq_n_f32(exp2x, 1.f); + f32x4_t den = vaddq_n_f32(exp2x, 1.f); + f32x4_t tanh = vmulq_f32(num, vrecip_f32(den)); + return tanh; +} + +__STATIC_INLINE f32x4_t vpowq_f32( + f32x4_t val, + f32x4_t n) +{ + return vexpq_f32(vmulq_f32(n, vlogq_f32(val))); +} + +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "NEMath.h" +/** + * @brief Vectorized integer exponentiation + * @param[in] x value + * @param[in] nb integer exponent >= 1 + * @return x^nb + * + */ +__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb) +{ + float32x4_t r = x; + nb --; + while(nb > 0) + { + r = vmulq_f32(r , x); + nb--; + } + return(r); +} + + +__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x) +{ + float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN)); + float32x4_t e = vrsqrteq_f32(x1); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + return vmulq_f32(x, e); +} + +__STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec) +{ + float32x4_t tempF; + int32x4_t tempHI,tempLO; + + tempLO = vmovl_s16(vget_low_s16(vec)); + tempF = vcvtq_n_f32_s32(tempLO,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempLO = vcvtq_n_s32_f32(tempF,15); + + tempHI = vmovl_s16(vget_high_s16(vec)); + tempF = vcvtq_n_f32_s32(tempHI,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempHI = vcvtq_n_s32_f32(tempF,15); + + return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI))); +} + +__STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec) +{ + float32x4_t temp; + + temp = vcvtq_n_f32_s32(vec,31); + temp = __arm_vec_sqrt_f32_neon(temp); + return(vcvtq_n_s32_f32(temp,31)); +} + +#endif /* (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_VEC_MATH_H */ + +/** + * + * End of file. + */ diff --git a/mcu/cmsis/Include/cachel1_armv7.h b/mcu/cmsis/Include/cachel1_armv7.h new file mode 100644 index 0000000..d2c3e22 --- /dev/null +++ b/mcu/cmsis/Include/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.0 + * @date 03. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/mcu/cmsis/Include/cmsis_armcc.h b/mcu/cmsis/Include/cmsis_armcc.h new file mode 100644 index 0000000..237ff6e --- /dev/null +++ b/mcu/cmsis/Include/cmsis_armcc.h @@ -0,0 +1,885 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.2.1 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/mcu/cmsis/Include/cmsis_armclang.h b/mcu/cmsis/Include/cmsis_armclang.h new file mode 100644 index 0000000..90de9db --- /dev/null +++ b/mcu/cmsis/Include/cmsis_armclang.h @@ -0,0 +1,1467 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.3.1 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/mcu/cmsis/Include/cmsis_armclang_ltm.h b/mcu/cmsis/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000..0e5c734 --- /dev/null +++ b/mcu/cmsis/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1893 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.3.0 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/mcu/cmsis/Include/cmsis_compiler.h b/mcu/cmsis/Include/cmsis_compiler.h new file mode 100644 index 0000000..adbf296 --- /dev/null +++ b/mcu/cmsis/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/mcu/cmsis/Include/cmsis_gcc.h b/mcu/cmsis/Include/cmsis_gcc.h new file mode 100644 index 0000000..a2778f5 --- /dev/null +++ b/mcu/cmsis/Include/cmsis_gcc.h @@ -0,0 +1,2177 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.3.0 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/mcu/cmsis/Include/cmsis_iccarm.h b/mcu/cmsis/Include/cmsis_iccarm.h new file mode 100644 index 0000000..7eeffca --- /dev/null +++ b/mcu/cmsis/Include/cmsis_iccarm.h @@ -0,0 +1,968 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.2.0 + * @date 28. January 2020 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/mcu/cmsis/Include/cmsis_version.h b/mcu/cmsis/Include/cmsis_version.h new file mode 100644 index 0000000..2f048e4 --- /dev/null +++ b/mcu/cmsis/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.4 + * @date 23. July 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/mcu/cmsis/Include/core_armv81mml.h b/mcu/cmsis/Include/core_armv81mml.h new file mode 100644 index 0000000..1ad19e2 --- /dev/null +++ b/mcu/cmsis/Include/core_armv81mml.h @@ -0,0 +1,4191 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.3.1 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[4]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */ + uint32_t RESERVED14[3]; + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (16UL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (16UL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (8UL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (6UL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/mcu/cmsis/Include/core_armv8mbl.h b/mcu/cmsis/Include/core_armv8mbl.h new file mode 100644 index 0000000..932d3d1 --- /dev/null +++ b/mcu/cmsis/Include/core_armv8mbl.h @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/mcu/cmsis/Include/core_armv8mml.h b/mcu/cmsis/Include/core_armv8mml.h new file mode 100644 index 0000000..71f000b --- /dev/null +++ b/mcu/cmsis/Include/core_armv8mml.h @@ -0,0 +1,3196 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/mcu/cmsis/Include/core_cm0.h b/mcu/cmsis/Include/core_cm0.h new file mode 100644 index 0000000..6441ff3 --- /dev/null +++ b/mcu/cmsis/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/mcu/cmsis/Include/core_cm0plus.h b/mcu/cmsis/Include/core_cm0plus.h new file mode 100644 index 0000000..4e7179a --- /dev/null +++ b/mcu/cmsis/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/mcu/cmsis/Include/core_cm1.h b/mcu/cmsis/Include/core_cm1.h new file mode 100644 index 0000000..76b4569 --- /dev/null +++ b/mcu/cmsis/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/mcu/cmsis/Include/core_cm23.h b/mcu/cmsis/Include/core_cm23.h new file mode 100644 index 0000000..55fff99 --- /dev/null +++ b/mcu/cmsis/Include/core_cm23.h @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/mcu/cmsis/Include/core_cm3.h b/mcu/cmsis/Include/core_cm3.h new file mode 100644 index 0000000..24453a8 --- /dev/null +++ b/mcu/cmsis/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/mcu/cmsis/Include/core_cm33.h b/mcu/cmsis/Include/core_cm33.h new file mode 100644 index 0000000..13359be --- /dev/null +++ b/mcu/cmsis/Include/core_cm33.h @@ -0,0 +1,3264 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/mcu/cmsis/Include/core_cm35p.h b/mcu/cmsis/Include/core_cm35p.h new file mode 100644 index 0000000..6a5f6ad --- /dev/null +++ b/mcu/cmsis/Include/core_cm35p.h @@ -0,0 +1,3264 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/mcu/cmsis/Include/core_cm4.h b/mcu/cmsis/Include/core_cm4.h new file mode 100644 index 0000000..4e0e886 --- /dev/null +++ b/mcu/cmsis/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/mcu/cmsis/Include/core_cm55.h b/mcu/cmsis/Include/core_cm55.h new file mode 100644 index 0000000..6efaa3f --- /dev/null +++ b/mcu/cmsis/Include/core_cm55.h @@ -0,0 +1,4215 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_CM55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[4]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */ + uint32_t RESERVED14[3]; + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (16UL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (16UL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (8UL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (6UL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/mcu/cmsis/Include/core_cm7.h b/mcu/cmsis/Include/core_cm7.h new file mode 100644 index 0000000..e1c31c2 --- /dev/null +++ b/mcu/cmsis/Include/core_cm7.h @@ -0,0 +1,2362 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/mcu/cmsis/Include/core_sc000.h b/mcu/cmsis/Include/core_sc000.h new file mode 100644 index 0000000..dbc755f --- /dev/null +++ b/mcu/cmsis/Include/core_sc000.h @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/mcu/cmsis/Include/core_sc300.h b/mcu/cmsis/Include/core_sc300.h new file mode 100644 index 0000000..e8914ba --- /dev/null +++ b/mcu/cmsis/Include/core_sc300.h @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/mcu/cmsis/Include/mpu_armv7.h b/mcu/cmsis/Include/mpu_armv7.h new file mode 100644 index 0000000..791a8da --- /dev/null +++ b/mcu/cmsis/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.1 + * @date 10. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/mcu/cmsis/Include/mpu_armv8.h b/mcu/cmsis/Include/mpu_armv8.h new file mode 100644 index 0000000..ef44ad0 --- /dev/null +++ b/mcu/cmsis/Include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.2 + * @date 10. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/mcu/cmsis/Include/pmu_armv8.h b/mcu/cmsis/Include/pmu_armv8.h new file mode 100644 index 0000000..dbd39d2 --- /dev/null +++ b/mcu/cmsis/Include/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.0 + * @date 24. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/mcu/cmsis/Include/tz_context.h b/mcu/cmsis/Include/tz_context.h new file mode 100644 index 0000000..0d09749 --- /dev/null +++ b/mcu/cmsis/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/mcu/lib/inc/ddl_config.h b/mcu/lib/inc/ddl_config.h new file mode 100644 index 0000000..d727bbd --- /dev/null +++ b/mcu/lib/inc/ddl_config.h @@ -0,0 +1,160 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file ddl_config.h + ** + ** A detailed description is available at + ** @link DdlConfigGroup Ddl Config description @endlink + ** + ** - 2021-04-16 CDT First version for Device Driver Library config. + ** + ******************************************************************************/ +#ifndef __DDL_CONFIG_H__ +#define __DDL_CONFIG_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup DdlConfigGroup Device Driver Library config(DDLCONFIG) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Chip module on-off define */ +#define DDL_ON (1u) +#define DDL_OFF (0u) + +/** + ******************************************************************************* + ** \brief This is the list of modules to be used in the device driver library + ** Select the modules you need to use to DDL_ON. + ** + ** \note DDL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works + ** properly. + ** + ** \note DDL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver + ** Library. + ** + ** \note DDL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. + ******************************************************************************/ +#define DDL_ICG_ENABLE (DDL_ON) +#define DDL_UTILITY_ENABLE (DDL_ON) +#define DDL_PRINT_ENABLE (DDL_OFF) + +#define DDL_ADC_ENABLE (DDL_ON) +#define DDL_AES_ENABLE (DDL_OFF) +#define DDL_CAN_ENABLE (DDL_OFF) +#define DDL_CLK_ENABLE (DDL_ON) +#define DDL_CMP_ENABLE (DDL_OFF) +#define DDL_CRC_ENABLE (DDL_OFF) +#define DDL_DCU_ENABLE (DDL_OFF) +#define DDL_DMAC_ENABLE (DDL_ON) +#define DDL_EFM_ENABLE (DDL_ON) +#define DDL_EMB_ENABLE (DDL_OFF) +#define DDL_EVENT_PORT_ENABLE (DDL_OFF) +#define DDL_EXINT_NMI_SWI_ENABLE (DDL_ON) +#define DDL_GPIO_ENABLE (DDL_ON) +#define DDL_HASH_ENABLE (DDL_OFF) +#define DDL_I2C_ENABLE (DDL_OFF) +#define DDL_I2S_ENABLE (DDL_OFF) +#define DDL_INTERRUPTS_ENABLE (DDL_ON) +#define DDL_INTERRUPTS_SHARE_ENABLE (DDL_OFF) +#define DDL_KEYSCAN_ENABLE (DDL_OFF) +#define DDL_MPU_ENABLE (DDL_OFF) +#define DDL_OTS_ENABLE (DDL_OFF) +#define DDL_PWC_ENABLE (DDL_ON) +#define DDL_QSPI_ENABLE (DDL_OFF) +#define DDL_RMU_ENABLE (DDL_OFF) +#define DDL_RTC_ENABLE (DDL_ON) +#define DDL_SDIOC_ENABLE (DDL_ON) +#define DDL_SPI_ENABLE (DDL_ON) +#define DDL_SRAM_ENABLE (DDL_ON) +#define DDL_SWDT_ENABLE (DDL_ON) +#define DDL_TIMER0_ENABLE (DDL_OFF) +#define DDL_TIMER4_CNT_ENABLE (DDL_OFF) +#define DDL_TIMER4_EMB_ENABLE (DDL_OFF) +#define DDL_TIMER4_OCO_ENABLE (DDL_OFF) +#define DDL_TIMER4_PWM_ENABLE (DDL_OFF) +#define DDL_TIMER4_SEVT_ENABLE (DDL_OFF) +#define DDL_TIMER6_ENABLE (DDL_OFF) +#define DDL_TIMERA_ENABLE (DDL_OFF) +#define DDL_TRNG_ENABLE (DDL_OFF) +#define DDL_USART_ENABLE (DDL_ON) +#define DDL_USBFS_ENABLE (DDL_OFF) +#define DDL_WDT_ENABLE (DDL_OFF) + + +/*! Midware module on-off define */ +#define MW_ON (1u) +#define MW_OFF (0u) + +/** + ******************************************************************************* + ** \brief This is the list of Midware modules to use + ** Select the modules you need to use to MW_ON. + ******************************************************************************/ +#define MW_FS_ENABLE (MW_OFF) +#define MW_SD_CARD_ENABLE (MW_OFF) +#define MW_W25QXX_ENABLE (MW_OFF) +#define MW_WM8731_ENABLE (MW_OFF) + +/* BSP on-off define */ +#define BSP_ON (1u) +#define BSP_OFF (0u) + +/** + * @brief The following is a list of currently supported BSP boards. + */ +#define BSP_EV_HC32F460_LQFP100_V1 (1u) +#define BSP_EV_HC32F460_LQFP100_V2 (2u) + +/** + * @brief The macro BSP_EV_HC32F460 is used to specify the BSP board currently + * in use. + * The value should be set to one of the list of currently supported BSP boards. + * @note If there is no supported BSP board or the BSP function is not used, + * the value needs to be set to BSP_EV_HC32F460. + */ +#define BSP_EV_HC32F460 (BSP_EV_HC32F460_LQFP100_V2) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +//@} // DdlConfigGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __DDL_CONFIG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll.h b/mcu/lib/inc/hc32_ll.h new file mode 100644 index 0000000..9f42c56 --- /dev/null +++ b/mcu/lib/inc/hc32_ll.h @@ -0,0 +1,317 @@ +/** + ******************************************************************************* + * @file hc32_ll.h + * @brief This file contains HC32 Series Device Driver Library file call + * management. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-01-15 CDT Modify version as 3.1.0 + 2023-09-30 CDT Modify version as 3.2.0 + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_H__ +#define __HC32_LL_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_Global + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup LL_Global_Macros LL Global Macros + * @{ + */ + +/** + * @defgroup Peripheral_Register_WP_Global_Macros Peripheral Register Write Protection Global Macros + * @{ + */ +#define LL_PERIPH_EFM (1UL << 0U) +#define LL_PERIPH_FCG (1UL << 1U) +#define LL_PERIPH_GPIO (1UL << 2U) +#define LL_PERIPH_INTC (1UL << 3U) +#define LL_PERIPH_LVD (1UL << 4U) +#define LL_PERIPH_MPU (1UL << 5U) +#define LL_PERIPH_PWC_CLK_RMU (1UL << 6U) +#define LL_PERIPH_SRAM (1UL << 7U) +#define LL_PERIPH_ALL (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_GPIO | LL_PERIPH_INTC | \ + LL_PERIPH_LVD | LL_PERIPH_MPU | LL_PERIPH_SRAM | LL_PERIPH_PWC_CLK_RMU) +/** + * @} + */ + +/* Defined use Device Driver Library */ +#if !defined (USE_DDL_DRIVER) +/** + * @brief Comment the line below if you will not use the Device Driver Library. + * In this case, the application code will be based on direct access to + * peripherals registers. + */ +/* #define USE_DDL_DRIVER */ +#endif /* USE_DDL_DRIVER */ + +/** +* @defgroup HC32_Series_DDL_Release_Version HC32 Series DDL Release Version +* @{ +*/ +#define HC32_DDL_REV_MAIN 0x03U /*!< [31:24] main version */ +#define HC32_DDL_REV_SUB1 0x02U /*!< [23:16] sub1 version */ +#define HC32_DDL_REV_SUB2 0x00U /*!< [15:8] sub2 version */ +#define HC32_DDL_REV_PATCH 0x00U /*!< [7:0] patch version */ +#define HC32_DDL_REV ((HC32_DDL_REV_MAIN << 24) | (HC32_DDL_REV_SUB1 << 16) | \ + (HC32_DDL_REV_SUB2 << 8 ) | (HC32_DDL_REV_PATCH)) +/** + * @} + */ + +/** + * @} + */ + +/* Use Device Driver Library */ +#if defined (USE_DDL_DRIVER) + +/** + * @brief Include peripheral module's header file + */ +#if (LL_ADC_ENABLE == DDL_ON) +#include "hc32_ll_adc.h" +#endif /* LL_ADC_ENABLE */ + +#if (LL_AES_ENABLE == DDL_ON) +#include "hc32_ll_aes.h" +#endif /* LL_AES_ENABLE */ + +#if (LL_AOS_ENABLE == DDL_ON) +#include "hc32_ll_aos.h" +#endif /* LL_AOS_ENABLE */ + +#if (LL_CAN_ENABLE == DDL_ON) +#include "hc32_ll_can.h" +#endif /* LL_CAN_ENABLE */ + +#if (LL_CLK_ENABLE == DDL_ON) +#include "hc32_ll_clk.h" +#endif /* LL_CLK_ENABLE */ + +#if (LL_CMP_ENABLE == DDL_ON) +#include "hc32_ll_cmp.h" +#endif /* LL_CMP_ENABLE */ + +#if (LL_CRC_ENABLE == DDL_ON) +#include "hc32_ll_crc.h" +#endif /* LL_CRC_ENABLE */ + +#if (LL_DBGC_ENABLE == DDL_ON) +#include "hc32_ll_dbgc.h" +#endif /* LL_DBGC_ENABLE */ + +#if (LL_DCU_ENABLE == DDL_ON) +#include "hc32_ll_dcu.h" +#endif /* LL_DCU_ENABLE */ + +#if (LL_DMA_ENABLE == DDL_ON) +#include "hc32_ll_dma.h" +#endif /* LL_DMA_ENABLE */ + +#if (LL_EFM_ENABLE == DDL_ON) +#include "hc32_ll_efm.h" +#endif /* LL_EFM_ENABLE */ + +#if (LL_EMB_ENABLE == DDL_ON) +#include "hc32_ll_emb.h" +#endif /* LL_EMB_ENABLE */ + +#if (LL_EVENT_PORT_ENABLE == DDL_ON) +#include "hc32_ll_event_port.h" +#endif /* LL_EVENT_PORT_ENABLE */ + +#if (LL_FCG_ENABLE == DDL_ON) +#include "hc32_ll_fcg.h" +#endif /* LL_FCG_ENABLE */ + +#if (LL_FCM_ENABLE == DDL_ON) +#include "hc32_ll_fcm.h" +#endif /* LL_FCM_ENABLE */ + +#if (LL_GPIO_ENABLE == DDL_ON) +#include "hc32_ll_gpio.h" +#endif /* LL_GPIO_ENABLE */ + +#if (LL_HASH_ENABLE == DDL_ON) +#include "hc32_ll_hash.h" +#endif /* LL_HASH_ENABLE */ + +#if (LL_I2C_ENABLE == DDL_ON) +#include "hc32_ll_i2c.h" +#endif /* LL_I2C_ENABLE */ + +#if (LL_I2S_ENABLE == DDL_ON) +#include "hc32_ll_i2s.h" +#endif /* LL_I2S_ENABLE */ + +#if (LL_ICG_ENABLE == DDL_ON) +#include "hc32_ll_icg.h" +#endif /* LL_ICG_ENABLE */ + +#if (LL_INTERRUPTS_ENABLE == DDL_ON) +#include "hc32_ll_interrupts.h" +#endif /* LL_INTERRUPTS_ENABLE */ + +#if (LL_INTERRUPTS_SHARE_ENABLE == DDL_ON) +#include "hc32f460_ll_interrupts_share.h" +#endif /* LL_INTERRUPTS_ENABLE */ + +#if (LL_KEYSCAN_ENABLE == DDL_ON) +#include "hc32_ll_keyscan.h" +#endif /* LL_KEYSCAN_ENABLE */ + +#if (LL_MPU_ENABLE == DDL_ON) +#include "hc32_ll_mpu.h" +#endif /* LL_MPU_ENABLE */ + +#if (LL_OTS_ENABLE == DDL_ON) +#include "hc32_ll_ots.h" +#endif /* LL_OTS_ENABLE */ + +#if (LL_PWC_ENABLE == DDL_ON) +#include "hc32_ll_pwc.h" +#endif /* LL_PWC_ENABLE */ + +#if (LL_QSPI_ENABLE == DDL_ON) +#include "hc32_ll_qspi.h" +#endif /* LL_QSPI_ENABLE */ + +#if (LL_RMU_ENABLE == DDL_ON) +#include "hc32_ll_rmu.h" +#endif /* LL_RMU_ENABLE */ + +#if (LL_RTC_ENABLE == DDL_ON) +#include "hc32_ll_rtc.h" +#endif /* LL_RTC_ENABLE */ + +#if (LL_SDIOC_ENABLE == DDL_ON) +#include "hc32_ll_sdioc.h" +#endif /* LL_SDIOC_ENABLE */ + +#if (LL_SPI_ENABLE == DDL_ON) +#include "hc32_ll_spi.h" +#endif /* LL_SPI_ENABLE */ + +#if (LL_SRAM_ENABLE == DDL_ON) +#include "hc32_ll_sram.h" +#endif /* LL_SRAM_ENABLE */ + +#if (LL_SWDT_ENABLE == DDL_ON) +#include "hc32_ll_swdt.h" +#endif /* LL_SWDT_ENABLE */ + +#if (LL_TMR0_ENABLE == DDL_ON) +#include "hc32_ll_tmr0.h" +#endif /* LL_TMR0_ENABLE */ + +#if (LL_TMR4_ENABLE == DDL_ON) +#include "hc32_ll_tmr4.h" +#endif /* LL_TMR4_ENABLE */ + +#if (LL_TMR6_ENABLE == DDL_ON) +#include "hc32_ll_tmr6.h" +#endif /* LL_TMR6_ENABLE */ + +#if (LL_TMRA_ENABLE == DDL_ON) +#include "hc32_ll_tmra.h" +#endif /* LL_TMRA_ENABLE */ + +#if (LL_TRNG_ENABLE == DDL_ON) +#include "hc32_ll_trng.h" +#endif /* LL_TRNG_ENABLE */ + +#if (LL_USART_ENABLE == DDL_ON) +#include "hc32_ll_usart.h" +#endif /* LL_USART_ENABLE */ + +#if (LL_UTILITY_ENABLE == DDL_ON) +#include "hc32_ll_utility.h" +#endif /* LL_UTILITY_ENABLE */ + +#if (LL_USB_ENABLE == DDL_ON) +#include "hc32_ll_usb.h" +#endif /* LL_USB_ENABLE */ + +#if (LL_WDT_ENABLE == DDL_ON) +#include "hc32_ll_wdt.h" +#endif /* LL_WDT_ENABLE */ + +#endif /* USE_DDL_DRIVER */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup LL_Global_Functions + * @{ + */ +void LL_PERIPH_WE(uint32_t u32Peripheral); +void LL_PERIPH_WP(uint32_t u32Peripheral); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_DDL_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_adc.h b/mcu/lib/inc/hc32_ll_adc.h new file mode 100644 index 0000000..b552914 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_adc.h @@ -0,0 +1,499 @@ +/** + ******************************************************************************* + * @file hc32_ll_adc.h + * @brief This file contains all the functions prototypes of the ADC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-10-31 CDT Modify macro group definition: ADC_Scan_Mode, ADC_Sync_Unit, ADC_Sync_Mode + 2023-06-30 CDT Modify typo + API fixed: ADC_DeInit() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_ADC_H__ +#define __HC32_LL_ADC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_ADC + * @{ + */ + +#if (LL_ADC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup ADC_Global_Types ADC Global Types + * @{ + */ +/** + * @brief Structure definition of analog watchdog(AWD) configuration. + */ +typedef struct { + uint16_t u16WatchdogMode; /*!< Specifies the ADC analog watchdog mode. + This parameter can be a value of @ref ADC_AWD_Mode */ + uint16_t u16LowThreshold; /*!< Specifies the ADC analog watchdog Low threshold value. */ + uint16_t u16HighThreshold; /*!< Specifies the ADC analog watchdog High threshold value. */ +} stc_adc_awd_config_t; + +/** + * @brief Structure definition of ADC initialization. + */ +typedef struct { + uint16_t u16ScanMode; /*!< Specifies the ADC scan convert mode. + This parameter can be a value of @ref ADC_Scan_Mode */ + uint16_t u16Resolution; /*!< Specifies the ADC resolution. + This parameter can be a value of @ref ADC_Resolution */ + uint16_t u16DataAlign; /*!< Specifies ADC data alignment. + This parameter can be a value of @ref ADC_Data_Align */ +} stc_adc_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ADC_Global_Macros ADC Global Macros + * @{ + */ + +/** + * @defgroup ADC_Sequence ADC Sequence + * @{ + */ +#define ADC_SEQ_A (0U) /*!< ADC sequence A. */ +#define ADC_SEQ_B (1U) /*!< ADC sequence B. */ +/** + * @} + */ + +/** + * @defgroup ADC_Channel ADC Channel + * @{ + */ +#define ADC_CH0 (0U) /*!< Default input pin: PA0 for ADC1, PA4 for ADC2. */ +#define ADC_CH1 (1U) /*!< Default input pin: PA1 for ADC1, PA5 for ADC2. */ +#define ADC_CH2 (2U) /*!< Default input pin: PA2 for ADC1, PA6 for ADC2. */ +#define ADC_CH3 (3U) /*!< Default input pin: PA3 for ADC1, PA7 for ADC2. */ +#define ADC_CH4 (4U) /*!< Default input pin: PA4 for ADC1, PB0 for ADC2. */ +#define ADC_CH5 (5U) /*!< Default input pin: PA5 for ADC1, PB1 for ADC2. */ +#define ADC_CH6 (6U) /*!< Default input pin: PA6 for ADC1, PC0 for ADC2. */ +#define ADC_CH7 (7U) /*!< Default input pin: PA7 for ADC1, PC1 for ADC2. */ +#define ADC_CH8 (8U) /*!< Default input pin: PB0 for ADC1, internal analog signal for ADC2. */ +#define ADC_CH9 (9U) /*!< Default input pin: PB1 for ADC1, NOT support ADC2. */ +#define ADC_CH10 (10U) /*!< Default input pin: PC0 for ADC1, NOT support ADC2. */ +#define ADC_CH11 (11U) /*!< Default input pin: PC1 for ADC1, NOT support ADC2. */ +#define ADC_CH12 (12U) /*!< Default input pin: PC2 for ADC1, NOT support ADC2. */ +#define ADC_CH13 (13U) /*!< Default input pin: PC3 for ADC1, NOT support ADC2. */ +#define ADC_CH14 (14U) /*!< Default input pin: PC4 for ADC1, NOT support ADC2. */ +#define ADC_CH15 (15U) /*!< Default input pin: PC5 for ADC1, NOT support ADC2. */ +#define ADC_CH16 (16U) /*!< ADC1 extended channel, input source is internal analog signal */ + +#define ADC1_EXT_CH (ADC_CH16) /*!< ADC1 extended channel, input source is internal analog signal: + internal reference voltage or 8bit-DAC. */ +#define ADC2_EXT_CH (ADC_CH8) /*!< ADC2 extended channel, input source is internal analog signal: + internal reference voltage or 8bit-DAC. */ +/** + * @} + */ + +/** + * @defgroup ADC_Scan_Mode ADC Scan Convert Mode + * @{ + */ +#define ADC_MD_SEQA_SINGLESHOT (0x0U) /*!< Sequence A single shot. Sequence B is disabled. */ +#define ADC_MD_SEQA_CONT (0x1U << ADC_CR0_MS_POS) /*!< Sequence A continuous. Sequence B is disabled. */ +#define ADC_MD_SEQA_SEQB_SINGLESHOT (0x2U << ADC_CR0_MS_POS) /*!< Sequence A and B both single shot. */ +#define ADC_MD_SEQA_CONT_SEQB_SINGLESHOT (0x3U << ADC_CR0_MS_POS) /*!< Sequence A continuous and sequence B single shot. */ +/** + * @} + */ + +/** + * @defgroup ADC_Resolution ADC Resolution + * @{ + */ +#define ADC_RESOLUTION_12BIT (0x0U) /*!< Resolution is 12 bit. */ +#define ADC_RESOLUTION_10BIT (ADC_CR0_ACCSEL_0) /*!< Resolution is 10 bit. */ +#define ADC_RESOLUTION_8BIT (ADC_CR0_ACCSEL_1) /*!< Resolution is 8 bit. */ +/** + * @} + */ + +/** + * @defgroup ADC_Data_Align ADC Data Align + * @{ + */ +#define ADC_DATAALIGN_RIGHT (0x0U) /*!< Right alignment of converted data. */ +#define ADC_DATAALIGN_LEFT (ADC_CR0_DFMT) /*!< Left alignment of converted data. */ +/** + * @} + */ + +/** + * @defgroup ADC_Average_Count ADC Average Count + * @{ + */ +#define ADC_AVG_CNT2 (0x0U) /*!< 2 consecutive average conversions. */ +#define ADC_AVG_CNT4 (0x1U << ADC_CR0_AVCNT_POS) /*!< 4 consecutive average conversions. */ +#define ADC_AVG_CNT8 (0x2U << ADC_CR0_AVCNT_POS) /*!< 8 consecutive average conversions. */ +#define ADC_AVG_CNT16 (0x3U << ADC_CR0_AVCNT_POS) /*!< 16 consecutive average conversions. */ +#define ADC_AVG_CNT32 (0x4U << ADC_CR0_AVCNT_POS) /*!< 32 consecutive average conversions. */ +#define ADC_AVG_CNT64 (0x5U << ADC_CR0_AVCNT_POS) /*!< 64 consecutive average conversions. */ +#define ADC_AVG_CNT128 (0x6U << ADC_CR0_AVCNT_POS) /*!< 128 consecutive average conversions. */ +#define ADC_AVG_CNT256 (0x7U << ADC_CR0_AVCNT_POS) /*!< 256 consecutive average conversions. */ +/** + * @} + */ + +/** + * @defgroup ADC_SeqA_Resume_Mode ADC Sequence A Resume Mode + * @brief After interrupted by sequence B, sequence A continues to scan from the interrupt channel or the first channel. + * @{ + */ +#define ADC_SEQA_RESUME_SCAN_CONT (0U) /*!< Scanning will continue from the interrupted channel. */ +#define ADC_SEQA_RESUME_SCAN_RESTART (ADC_CR1_RSCHSEL) /*!< Scanning will start from the first channel. */ +/** + * @} + */ + +/** + * @defgroup ADC_Hard_Trigger_Sel ADC Hard Trigger Selection + * @{ + */ +#define ADC_HARDTRIG_ADTRG_PIN (0x0U) /*!< Selects the following edge of pin ADTRG as the trigger of ADC sequence. */ +#define ADC_HARDTRIG_EVT0 (ADC_TRGSR_TRGSELA_0) /*!< Selects an internal event as the trigger of ADC sequence. + This event is specified by register ADCx_TRGSEL0(x=(null), 1, 2, 3). */ +#define ADC_HARDTRIG_EVT1 (ADC_TRGSR_TRGSELA_1) /*!< Selects an internal event as the trigger of ADC sequence. + This event is specified by register ADCx_TRGSEL1(x=(null), 1, 2, 3). */ +#define ADC_HARDTRIG_EVT0_EVT1 (ADC_TRGSR_TRGSELA) /*!< Selects two internal events as the trigger of ADC sequence. + The two events are specified by register ADCx_TRGSEL0 and register ADCx_TRGSEL1. */ +/** + * @} + */ + +/** + * @defgroup ADC_Int_Type ADC Interrupt Type + * @{ + */ +#define ADC_INT_EOCA (ADC_ICR_EOCAIEN) /*!< Interrupt of the end of conversion of sequence A. */ +#define ADC_INT_EOCB (ADC_ICR_EOCBIEN) /*!< Interrupt of the end of conversion of sequence B. */ +#define ADC_INT_ALL (ADC_INT_EOCA | ADC_INT_EOCB) +/** + * @} + */ + +/** + * @defgroup ADC_Status_Flag ADC Status Flag + * @{ + */ +#define ADC_FLAG_EOCA (ADC_ISR_EOCAF) /*!< Status flag of the end of conversion of sequence A. */ +#define ADC_FLAG_EOCB (ADC_ISR_EOCBF) /*!< Status flag of the end of conversion of sequence B. */ +#define ADC_FLAG_ALL (ADC_FLAG_EOCA | ADC_FLAG_EOCB) +/** + * @} + */ + +/** + * @defgroup ADC_Sync_Unit ADC Synchronous Unit + * @{ + */ +#define ADC_SYNC_ADC1_ADC2 (0U) /*!< ADC1 and ADC2 work synchronously. */ +/** + * @} + */ + +/** + * @defgroup ADC_Sync_Mode ADC Synchronous Mode + * @{ + */ +#define ADC_SYNC_SINGLE_DELAY_TRIG (0U) /*!< Single shot delayed trigger mode. + When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has). + All ADCs scan once. */ +#define ADC_SYNC_SINGLE_PARALLEL_TRIG (0x2U << ADC_SYNCCR_SYNCMD_POS) /*!< Single shot parallel trigger mode. + When the trigger condition occurs, all ADCs start at the same time. + All ADCs scan once. */ +#define ADC_SYNC_CYCLIC_DELAY_TRIG (0x4U << ADC_SYNCCR_SYNCMD_POS) /*!< Cyclic delayed trigger mode. + When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has). + All ADCs scan cyclicly(keep scanning till you stop them). */ +#define ADC_SYNC_CYCLIC_PARALLEL_TRIG (0x6U << ADC_SYNCCR_SYNCMD_POS) /*!< Single shot parallel trigger mode. + When the trigger condition occurs, all ADCs start at the same time. + All ADCs scan cyclicly(keep scanning till you stop them). */ +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Unit ADC Analog Watchdog Unit + * @{ + */ +#define ADC_AWD0 (0U) /*!< ADC analog watchdog 0. */ +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Int_Type ADC AWD Interrupt Type + * @{ + */ +#define ADC_AWD_INT_SEQA (ADC_AWDCR_AWDSS_0) /*!< Interrupt of AWD sequence A. */ +#define ADC_AWD_INT_SEQB (ADC_AWDCR_AWDSS_1) /*!< Interrupt of AWD sequence B. */ +#define ADC_AWD_INT_ALL (ADC_AWDCR_AWDSS) +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Mode ADC Analog Watchdog Mode + * @{ + */ +#define ADC_AWD_MD_CMP_OUT (0x0U) /*!< ADCValue > HighThreshold or ADCValue < LowThreshold */ +#define ADC_AWD_MD_CMP_IN (0x1U) /*!< LowThreshold < ADCValue < HighThreshold */ +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Status_Flag ADC AWD Status Flag + * @{ + */ +#define ADC_AWD_FLAG_CH0 (1UL << ADC_CH0) +#define ADC_AWD_FLAG_CH1 (1UL << ADC_CH1) +#define ADC_AWD_FLAG_CH2 (1UL << ADC_CH2) +#define ADC_AWD_FLAG_CH3 (1UL << ADC_CH3) +#define ADC_AWD_FLAG_CH4 (1UL << ADC_CH4) +#define ADC_AWD_FLAG_CH5 (1UL << ADC_CH5) +#define ADC_AWD_FLAG_CH6 (1UL << ADC_CH6) +#define ADC_AWD_FLAG_CH7 (1UL << ADC_CH7) +#define ADC_AWD_FLAG_CH8 (1UL << ADC_CH8) +#define ADC_AWD_FLAG_CH9 (1UL << ADC_CH9) +#define ADC_AWD_FLAG_CH10 (1UL << ADC_CH10) +#define ADC_AWD_FLAG_CH11 (1UL << ADC_CH11) +#define ADC_AWD_FLAG_CH12 (1UL << ADC_CH12) +#define ADC_AWD_FLAG_CH13 (1UL << ADC_CH13) +#define ADC_AWD_FLAG_CH14 (1UL << ADC_CH14) +#define ADC_AWD_FLAG_CH15 (1UL << ADC_CH15) +#define ADC_AWD_FLAG_CH16 (1UL << ADC_CH16) +#define ADC1_AWD_FLAG_ALL (0x1FFFFUL) +#define ADC2_AWD_FLAG_ALL (0x1FFUL) +/** + * @} + */ + +/** + * @defgroup ADC_PGA_Unit ADC PGA Unit + * @{ + */ +#define ADC_PGA1 (0U) /*!< PGA1, belongs to ADC1. Input source can one of @ref ADC_PGA_Input_Src */ +/** + * @} + */ + +/** + * @defgroup ADC_PGA_Gain ADC PGA Gain Factor + * @{ + */ +#define ADC_PGA_GAIN_2 (0x0U) /*!< PGA gain factor is 2. */ +#define ADC_PGA_GAIN_2P133 (0x1U) /*!< PGA gain factor is 2.133. */ +#define ADC_PGA_GAIN_2P286 (0x2U) /*!< PGA gain factor is 2.286. */ +#define ADC_PGA_GAIN_2P667 (0x3U) /*!< PGA gain factor is 2.667. */ +#define ADC_PGA_GAIN_2P909 (0x4U) /*!< PGA gain factor is 2.909. */ +#define ADC_PGA_GAIN_3P2 (0x5U) /*!< PGA gain factor is 3.2. */ +#define ADC_PGA_GAIN_3P556 (0x6U) /*!< PGA gain factor is 2.556. */ +#define ADC_PGA_GAIN_4 (0x7U) /*!< PGA gain factor is 4. */ +#define ADC_PGA_GAIN_4P571 (0x8U) /*!< PGA gain factor is 4.571. */ +#define ADC_PGA_GAIN_5P333 (0x9U) /*!< PGA gain factor is 5.333. */ +#define ADC_PGA_GAIN_6P4 (0xAU) /*!< PGA gain factor is 6.4. */ +#define ADC_PGA_GAIN_8 (0xBU) /*!< PGA gain factor is 8. */ +#define ADC_PGA_GAIN_10P667 (0xCU) /*!< PGA gain factor is 10.667. */ +#define ADC_PGA_GAIN_16 (0xDU) /*!< PGA gain factor is 16. */ +#define ADC_PGA_GAIN_32 (0xEU) /*!< PGA gain factor is 32. */ +/** + * @} + */ + +/** + * @defgroup ADC_PGA_VSS ADC PGA VSS + * @{ + */ +#define ADC_PGA_VSS_PGAVSS (0U) /*!< Use pin PGAx_VSS as the reference GND of PGAx. */ +#define ADC_PGA_VSS_AVSS (1U) /*!< Use AVSS as the reference GND of PGAx. */ +/** + * @} + */ + +/** + * @defgroup ADC_PGA_Input_Src ADC PGA Input Source + * @{ + */ +#define ADC_PGA_PIN_ADC1_PA0 (ADC_PGAINSR0_PGAINSEL_0) /*!< ADC1 pin ADC1_IN0(PA0). */ +#define ADC_PGA_PIN_ADC1_PA1 (ADC_PGAINSR0_PGAINSEL_1) /*!< ADC1 pin ADC1_IN1(PA1). */ +#define ADC_PGA_PIN_ADC1_PA2 (ADC_PGAINSR0_PGAINSEL_2) /*!< ADC1 pin ADC1_IN2(PA2). */ +#define ADC_PGA_PIN_ADC1_PA3 (ADC_PGAINSR0_PGAINSEL_3) /*!< ADC1 pin ADC1_IN3(PA3). */ +#define ADC_PGA_PIN_ADC1_PA4 (ADC_PGAINSR0_PGAINSEL_4) /*!< ADC1 pin ADC12_IN4(PA4). */ +#define ADC_PGA_PIN_ADC1_PA5 (ADC_PGAINSR0_PGAINSEL_5) /*!< ADC1 pin ADC12_IN5(PA5). */ +#define ADC_PGA_PIN_ADC1_PA6 (ADC_PGAINSR0_PGAINSEL_6) /*!< ADC1 pin ADC12_IN6(PA6). */ +#define ADC_PGA_PIN_ADC1_PA7 (ADC_PGAINSR0_PGAINSEL_7) /*!< ADC1 pin ADC12_IN7(PA7). */ +#define ADC_PGA_8BIT_DAC (ADC_PGAINSR0_PGAINSEL_8) /*!< Internal 8bit-DAC to ADC1. */ +/** + * @} + */ + +/** + * @defgroup ADC_Remap_Pin ADC Remap Pin + * @{ + */ +#define ADC1_PIN_PA0 (0U) /*!< ADC1_IN0(PA0): default channel is ADC_CH0 of ADC1. */ +#define ADC1_PIN_PA1 (1U) /*!< ADC1_IN1(PA1): default channel is ADC_CH1 of ADC1. */ +#define ADC1_PIN_PA2 (2U) /*!< ADC1_IN2(PA2): default channel is ADC_CH2 of ADC1. */ +#define ADC1_PIN_PA3 (3U) /*!< ADC1_IN3(PA3): default channel is ADC_CH3 of ADC1. */ +#define ADC1_PIN_PA4 (4U) /*!< ADC12_IN4(PA4): default channel is ADC_CH4 of ADC1. */ +#define ADC1_PIN_PA5 (5U) /*!< ADC12_IN5(PA5): default channel is ADC_CH5 of ADC1. */ +#define ADC1_PIN_PA6 (6U) /*!< ADC12_IN6(PA6): default channel is ADC_CH6 of ADC1. */ +#define ADC1_PIN_PA7 (7U) /*!< ADC12_IN7(PA7): default channel is ADC_CH7 of ADC1. */ +#define ADC1_PIN_PB0 (8U) /*!< ADC12_IN8(PB0): default channel is ADC_CH8 of ADC1. */ +#define ADC1_PIN_PB1 (9U) /*!< ADC12_IN9(PB1): default channel is ADC_CH9 of ADC1. */ +#define ADC1_PIN_PC0 (10U) /*!< ADC12_IN10(PC0): default channel is ADC_CH10 of ADC1. */ +#define ADC1_PIN_PC1 (11U) /*!< ADC12_IN11(PC1): default channel is ADC_CH11 of ADC1. */ +#define ADC1_PIN_PC2 (12U) /*!< ADC1_IN12(PC2): default channel is ADC_CH12 of ADC1. */ +#define ADC1_PIN_PC3 (13U) /*!< ADC1_IN13(PC3): default channel is ADC_CH13 of ADC1. */ +#define ADC1_PIN_PC4 (14U) /*!< ADC1_IN14(PC4): default channel is ADC_CH14 of ADC1. */ +#define ADC1_PIN_PC5 (15U) /*!< ADC1_IN15(PC5): default channel is ADC_CH15 of ADC1. */ + +#define ADC2_PIN_PA4 (0U) /*!< ADC12_IN4(PA4): default channel is ADC_CH0 of ADC2 */ +#define ADC2_PIN_PA5 (1U) /*!< ADC12_IN5(PA5): default channel is ADC_CH1 of ADC2 */ +#define ADC2_PIN_PA6 (2U) /*!< ADC12_IN6(PA6): default channel is ADC_CH2 of ADC2 */ +#define ADC2_PIN_PA7 (3U) /*!< ADC12_IN7(PA7): default channel is ADC_CH3 of ADC2 */ +#define ADC2_PIN_PB0 (4U) /*!< ADC12_IN8(PB0): default channel is ADC_CH4 of ADC2 */ +#define ADC2_PIN_PB1 (5U) /*!< ADC12_IN9(PB1): default channel is ADC_CH5 of ADC2 */ +#define ADC2_PIN_PC0 (6U) /*!< ADC12_IN10(PC0): default channel is ADC_CH6 of ADC2 */ +#define ADC2_PIN_PC1 (7U) /*!< ADC12_IN11(PC1): default channel is ADC_CH7 of ADC2 */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup ADC_Global_Functions + * @{ + */ +/******************************************************************************* + Basic features + ******************************************************************************/ +int32_t ADC_Init(CM_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcAdcInit); +int32_t ADC_DeInit(CM_ADC_TypeDef *ADCx); +int32_t ADC_StructInit(stc_adc_init_t *pstcAdcInit); +void ADC_ChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint8_t u8Ch, en_functional_state_t enNewState); +void ADC_SetSampleTime(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8SampleTime); + +/* Conversion data average calculation function. */ +void ADC_ConvDataAverageConfig(CM_ADC_TypeDef *ADCx, uint16_t u16AverageCount); +void ADC_ConvDataAverageChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, en_functional_state_t enNewState); + +void ADC_TriggerConfig(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint16_t u16TriggerSel); +void ADC_TriggerCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enNewState); +void ADC_IntCmd(CM_ADC_TypeDef *ADCx, uint8_t u8IntType, en_functional_state_t enNewState); +void ADC_Start(CM_ADC_TypeDef *ADCx); +void ADC_Stop(CM_ADC_TypeDef *ADCx); +uint16_t ADC_GetValue(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch); +en_flag_status_t ADC_GetStatus(const CM_ADC_TypeDef *ADCx, uint8_t u8Flag); +void ADC_ClearStatus(CM_ADC_TypeDef *ADCx, uint8_t u8Flag); +/******************************************************************************* + Advanced features + ******************************************************************************/ +/* Channel remap. */ +void ADC_ChRemap(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8AdcPin); +uint8_t ADC_GetChPin(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch); +void ADC_ResetChMapping(CM_ADC_TypeDef *ADCx); + +/* Sync mode. */ +void ADC_SyncModeConfig(uint16_t u16SyncUnit, uint16_t u16SyncMode, uint8_t u8TriggerDelay); +void ADC_SyncModeCmd(en_functional_state_t enNewState); + +/* Analog watchdog */ +int32_t ADC_AWD_Config(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch, const stc_adc_awd_config_t *pstcAwd); +void ADC_AWD_SetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16WatchdogMode); +uint16_t ADC_AWD_GetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit); +void ADC_AWD_SetThreshold(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16LowThreshold, uint16_t u16HighThreshold); +void ADC_AWD_SelectCh(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch); +void ADC_AWD_DeselectCh(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch); +void ADC_AWD_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, en_functional_state_t enNewState); +void ADC_AWD_IntCmd(CM_ADC_TypeDef *ADCx, uint16_t u16IntType, en_functional_state_t enNewState); +en_flag_status_t ADC_AWD_GetStatus(const CM_ADC_TypeDef *ADCx, uint32_t u32Flag); +void ADC_AWD_ClearStatus(CM_ADC_TypeDef *ADCx, uint32_t u32Flag); + +/* PGA */ +void ADC_PGA_Config(CM_ADC_TypeDef *ADCx, uint8_t u8PgaUnit, uint8_t u8Gain, uint8_t u8PgaVss); +void ADC_PGA_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8PgaUnit, en_functional_state_t enNewState); +void ADC_PGA_SelectInputSrc(CM_ADC_TypeDef *ADCx, uint16_t u16PgaInputSrc); +void ADC_PGA_DeselectInputSrc(CM_ADC_TypeDef *ADCx); + +void ADC_DataRegAutoClearCmd(CM_ADC_TypeDef *ADCx, en_functional_state_t enNewState); +void ADC_SetSeqAResumeMode(CM_ADC_TypeDef *ADCx, uint16_t u16SeqAResumeMode); +/** + * @} + */ + +#endif /* LL_ADC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_ADC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_aes.h b/mcu/lib/inc/hc32_ll_aes.h new file mode 100644 index 0000000..b4216f2 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_aes.h @@ -0,0 +1,116 @@ +/** + ******************************************************************************* + * @file hc32_ll_aes.h + * @brief This file contains all the functions prototypes of the AES driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-06-30 CDT Add API AES_DeInit() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_AES_H__ +#define __HC32_LL_AES_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_AES + * @{ + */ + +#if (LL_AES_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup AES_Global_Macros AES Global Macros + * @{ + */ + +/** + * @defgroup AES_Key_Size AES Key Size + * @{ + */ +#define AES_KEY_SIZE_16BYTE (16U) +/** + * @} + */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup AES_Global_Functions + * @{ + */ +int32_t AES_Encrypt(const uint8_t *pu8Plaintext, uint32_t u32PlaintextSize, + const uint8_t *pu8Key, uint8_t u8KeySize, + uint8_t *pu8Ciphertext); + +int32_t AES_Decrypt(const uint8_t *pu8Ciphertext, uint32_t u32CiphertextSize, + const uint8_t *pu8Key, uint8_t u8KeySize, + uint8_t *pu8Plaintext); + +int32_t AES_DeInit(void); +/** + * @} + */ + +#endif /* LL_AES_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_AES_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_aos.h b/mcu/lib/inc/hc32_ll_aos.h new file mode 100644 index 0000000..b874967 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_aos.h @@ -0,0 +1,171 @@ +/** + ******************************************************************************* + * @file hc32_ll_aos.h + * @brief This file contains all the functions prototypes of the AOS driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-01-15 CDT Modified parameters name of API AOS_CommonTriggerCmd() and AOS_SetTriggerEventSrc() + 2023-09-30 CDT Modify for new head file + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_AOS_H__ +#define __HC32_LL_AOS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_AOS + * @{ + */ + +#if (LL_AOS_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup AOS_Global_Macros AOS Global Macros + * @{ + */ + +/** + * @defgroup AOS_Target_Select AOS Target Select + * @{ + */ +#define AOS_DCU1 (uint32_t)(&CM_AOS->DCU_TRGSEL1) +#define AOS_DCU2 (uint32_t)(&CM_AOS->DCU_TRGSEL2) +#define AOS_DCU3 (uint32_t)(&CM_AOS->DCU_TRGSEL3) +#define AOS_DCU4 (uint32_t)(&CM_AOS->DCU_TRGSEL4) +#define AOS_DMA1_0 (uint32_t)(&CM_AOS->DMA1_TRGSEL0) +#define AOS_DMA1_1 (uint32_t)(&CM_AOS->DMA1_TRGSEL1) +#define AOS_DMA1_2 (uint32_t)(&CM_AOS->DMA1_TRGSEL2) +#define AOS_DMA1_3 (uint32_t)(&CM_AOS->DMA1_TRGSEL3) +#define AOS_DMA2_0 (uint32_t)(&CM_AOS->DMA2_TRGSEL0) +#define AOS_DMA2_1 (uint32_t)(&CM_AOS->DMA2_TRGSEL1) +#define AOS_DMA2_2 (uint32_t)(&CM_AOS->DMA2_TRGSEL2) +#define AOS_DMA2_3 (uint32_t)(&CM_AOS->DMA2_TRGSEL3) +#define AOS_DMA_RC (uint32_t)(&CM_AOS->DMA_RC_TRGSEL) +#define AOS_TMR6_0 (uint32_t)(&CM_AOS->TMR6_TRGSEL0) +#define AOS_TMR6_1 (uint32_t)(&CM_AOS->TMR6_TRGSEL1) +#define AOS_TMR0 (uint32_t)(&CM_AOS->TMR0_TRGSEL) +#define AOS_EVTPORT12 (uint32_t)(&CM_AOS->PEVNT_TRGSEL12) +#define AOS_EVTPORT34 (uint32_t)(&CM_AOS->PEVNT_TRGSEL34) +#define AOS_TMRA_0 (uint32_t)(&CM_AOS->TMRA_TRGSEL0) +#define AOS_TMRA_1 (uint32_t)(&CM_AOS->TMRA_TRGSEL1) +#define AOS_OTS (uint32_t)(&CM_AOS->OTS_TRGSEL) +#define AOS_ADC1_0 (uint32_t)(&CM_AOS->ADC1_TRGSEL0) +#define AOS_ADC1_1 (uint32_t)(&CM_AOS->ADC1_TRGSEL1) +#define AOS_ADC2_0 (uint32_t)(&CM_AOS->ADC2_TRGSEL0) +#define AOS_ADC2_1 (uint32_t)(&CM_AOS->ADC2_TRGSEL1) +#define AOS_COMM_1 (uint32_t)(&CM_AOS->COMTRG1) +#define AOS_COMM_2 (uint32_t)(&CM_AOS->COMTRG2) + +/** + * @} + */ + +/** + * @defgroup AOS_Common_Trigger_ID AOS Common Trigger ID + * @{ + */ +#define AOS_COMM_TRIG1 (1UL << 30U) +#define AOS_COMM_TRIG2 (1UL << 31U) +#define AOS_COMM_TRIG_MASK (AOS_COMM_TRIG1 | AOS_COMM_TRIG2) + +/** + * @} + */ + +/** + * @defgroup AOS_Trigger_Select_Mask AOS Trigger Select Mask + * @{ + */ +#define AOS_TRIG_SEL_MASK (0x1FFUL) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup AOS_Global_Functions + * @{ + */ + +/** + * @brief AOS software trigger. + * @param None + * @retval None + */ +__STATIC_INLINE void AOS_SW_Trigger(void) +{ + WRITE_REG32(bCM_AOS->INTSFTTRG_b.STRG, SET); +} + +void AOS_CommonTriggerCmd(uint32_t u32Target, uint32_t u32CommonTrigger, en_functional_state_t enNewState); +void AOS_SetTriggerEventSrc(uint32_t u32Target, en_event_src_t enSource); +/** + * @} + */ + +#endif /* LL_AOS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_AOS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_can.h b/mcu/lib/inc/hc32_ll_can.h new file mode 100644 index 0000000..addc3bb --- /dev/null +++ b/mcu/lib/inc/hc32_ll_can.h @@ -0,0 +1,669 @@ +/** + ******************************************************************************* + * @file hc32_ll_can.h + * @brief This file contains all the functions prototypes of the CAN driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-10-31 CDT Deleted redundant comments + Remove CAN_FLAG_RX_BUF_OVF from CAN_FLAG_CLR_ALL + 2023-06-30 CDT Added 3 APIs for local-reset + Modify typo + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_CAN_H__ +#define __HC32_LL_CAN_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_CAN + * @{ + */ +#if (LL_CAN_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CAN_Global_Types CAN Global Types + * @{ + */ +/** + * @brief CAN bit time configuration structure. + * @note 1. TQ = u32Prescaler / CANClock. + * @note 2. Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ. + * @note 3. Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2)) + * @note 4. See user manual of the target MCU and ISO11898-1 for more details. + */ +typedef struct { + uint32_t u32Prescaler; /*!< Specifies the prescaler of CAN clock, [1, 256]. */ + uint32_t u32TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + u32TimeSeg1 Contains synchronization segment, + propagation time segment and phase buffer segment 1. */ + uint32_t u32TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + Phase buffer segment 2. */ + uint32_t u32SJW; /*!< Synchronization Jump Width. + Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. */ +} stc_can_bit_time_config_t; + +/** + * @brief CAN acceptance filter configuration structure. + */ +typedef struct { + uint32_t u32ID; /*!< Specifies the identifier(ID). 11 bits standard ID or 29 bits extended ID, depending on IDE. */ + uint32_t u32IDMask; /*!< Specifies the identifier(ID) mask. The mask bits of ID will be ignored by the acceptance filter. */ + uint32_t u32IDType; /*!< Specifies the identifier(ID) type. This parameter can be a value of @ref CAN_ID_Type */ +} stc_can_filter_config_t; + +/** + * @brief TTCAN configuration structure. + */ +typedef struct { + uint32_t u32RefMsgID; /*!< Reference message identifier. */ + uint32_t u32RefMsgIDE; /*!< Reference message identifier extension bit. + '1' to set the ID which is specified by parameter 'u32RefMsgID' as an extended ID while + '0' to set it as a standard ID. */ + uint8_t u8NTUPrescaler; /*!< Prescaler of NTU(network time unit). The source is the bit time which is defined by SBT. + This parameter can be a value of @ref TTCAN_NTU_Prescaler */ + uint8_t u8TxBufMode; /*!< TTCAN Transmit Buffer Mode. + This parameter can be a value of @ref TTCAN_Tx_Buf_Mode */ + uint16_t u16TriggerType; /*!< Trigger type of TTCAN. + This parameter can be a value of @ref TTCAN_Trigger_Type */ + uint16_t u16TxEnableWindow; /*!< Tx_Enable window. Time period within which the transmission of a message may be started. Range is [1, 16] */ + uint16_t u16TxTriggerTime; /*!< Specifies for the referred message the time window of the matrix cycle at which it is to be transmitted. Range is [0, 65535] */ + uint16_t u16WatchTriggerTime; /*!< Time mark used to check whether the time since the last valid reference message has been too long. Range is [0, 65535] */ +} stc_can_ttc_config_t; + +/** + * @brief CAN initialization structure. + */ +typedef struct { + stc_can_bit_time_config_t stcBitCfg; /*!< Bit time configuration of classical CAN bit. @ref stc_can_bit_time_config_t */ + stc_can_filter_config_t *pstcFilter; /*!< Pointer to a @ref stc_can_filter_config_t structure that + contains the configuration informations for the acceptance filters. */ + uint16_t u16FilterSelect; /*!< Selects acceptance filters. + This parameter can be values of @ref CAN_Acceptance_Filter */ + uint8_t u8WorkMode; /*!< Specifies the work mode of CAN. + This parameter can be a value of @ref CAN_Work_Mode */ + uint8_t u8PTBSingleShotTx; /*!< Enable or disable single shot transmission of PTB. + This parameter can be a value of @ref PTB_SingleShot_Tx_En */ + uint8_t u8STBSingleShotTx; /*!< Enable or disable single shot transmission of STB. + This parameter can be a value of @ref STB_SingleShot_Tx_En */ + uint8_t u8STBPrioMode; /*!< Enable or disable the priority decision mode of STB. + This parameter can be a value of @ref CAN_STB_Prio_Mode_En + NOTE: A frame in the PTB has always the highest priority regardless of the ID. */ + uint8_t u8RxWarnLimit; /*!< Specifies receive buffer almost full warning limit. Rang is [1, 8]. + Each CAN unit has 8 receive buffers. When the number of received frames reaches + the value specified by u8RxWarnLimit, register bit RTIF.RAFIF is set and the interrupt occurred + if it was enabled. */ + uint8_t u8ErrorWarnLimit; /*!< Specifies programmable error warning limit. Range is [0, 15]. + Error warning limit = (u8ErrorWarnLimit + 1) * 8. */ + uint8_t u8RxAllFrame; /*!< Enable or disable receive all frames(includes frames with error). + This parameter can be a value of @ref CAN_Rx_All_En */ + uint8_t u8RxOvfMode; /*!< Receive buffer overflow mode. In case of a full receive buffer when a new frame is received. + This parameter can be a value of @ref CAN_Rx_Ovf_Mode */ + uint8_t u8SelfAck; /*!< Enable or disable self-acknowledge. + This parameter can be a value of @ref CAN_Self_ACK_En */ + + stc_can_ttc_config_t *pstcCanTtc; /*!< Pointer to a TTCAN configuration structure. @ref stc_can_ttc_config_t + Set it to NULL if not needed TTCAN. */ +} stc_can_init_t; + +/** + * @brief CAN error information structure. + */ +typedef struct { + uint8_t u8ArbitrLostPos; /*!< Bit position in the frame where the arbitration has been lost. */ + uint8_t u8ErrorType; /*!< CAN error type. This parameter can be a value of @ref CAN_Err_Type */ + uint8_t u8RxErrorCount; /*!< Receive error count. */ + uint8_t u8TxErrorCount; /*!< Transmit error count. */ +} stc_can_error_info_t; + +/** + * @brief CAN TX frame data structure. + */ +typedef struct { + uint32_t u32ID; /*!< 11 bits standard ID or 29 bits extended ID, depending on IDE. */ + union { + uint32_t u32Ctrl; + struct { + uint32_t DLC: 4; /*!< Data length code. Length of the data segment of data frame. + It should be zero while the frame is remote frame. + This parameter can be a value of @ref CAN_Data_Length_Code */ + uint32_t BRS: 1; /*!< Bit rate switch. */ + uint32_t FDF: 1; /*!< CAN FD frame. */ + uint32_t RTR: 1; /*!< Remote transmission request bit. + It is used to distinguish between data frames and remote frames. */ + uint32_t IDE: 1; /*!< Identifier extension flag. + It is used to distinguish between standard format and extended format. + This parameter can be a 1 or 0. */ + uint32_t RSVD: 24; /*!< Reserved bits. */ + }; + }; + uint8_t au8Data[8U]; /*!< TX data payload. */ +} stc_can_tx_frame_t; + +/** + * @brief CAN RX frame data structure. + */ +typedef struct { + uint32_t u32ID; /*!< 11 bits standard ID or 29 bits extended ID, depending on IDE. */ + union { + uint32_t u32Ctrl; + struct { + uint32_t DLC: 4; /*!< Data length code. Length of the data segment of data frame. + It should be zero while the frame is remote frame. + This parameter can be a value of @ref CAN_Data_Length_Code */ + uint32_t BRS: 1; /*!< Bit rate switch. */ + uint32_t FDF: 1; /*!< CAN FD frame. */ + uint32_t RTR: 1; /*!< Remote transmission request bit. + It is used to distinguish between data frames and remote frames. */ + uint32_t IDE: 1; /*!< Identifier extension flag. + It is used to distinguish between standard format and extended format. + This parameter can be 1 or 0. */ + uint32_t RSVD: 4; /*!< Reserved bits. */ + uint32_t TX: 1; /*!< This bit is set to 1 when receiving self-transmitted data in loopback mode. */ + uint32_t ERRT: 3; /*!< Error type. */ + uint32_t CYCLE_TIME: 16; /*!< Cycle time of time-triggered communication(TTC). */ + }; + }; + uint8_t au8Data[8U]; /*!< RX data payload. */ +} stc_can_rx_frame_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CAN_Global_Macros CAN Global Macros + * @{ + */ + +/** + * @defgroup CAN_Work_Mode CAN Work Mode + * @{ + */ +#define CAN_WORK_MD_NORMAL (0U) /*!< Normal work mode. */ +#define CAN_WORK_MD_SILENT (1U) /*!< Silent work mode. Prohibit data transmission. */ +#define CAN_WORK_MD_ILB (2U) /*!< Internal loop back mode, just for self-test while developing. */ +#define CAN_WORK_MD_ELB (3U) /*!< External loop back mode, just for self-test while developing. */ +#define CAN_WORK_MD_ELB_SILENT (4U) /*!< External loop back silent mode, just for self-test while developing. + It is forbidden to respond to received frames and error frames, + but data can be transmitted. */ +/** + * @} + */ + +/** + * @defgroup CAN_Tx_Buf_Type CAN Transmit Buffer Type + * @{ + */ +#define CAN_TX_BUF_PTB (0U) /*!< Primary transmit buffer. */ +#define CAN_TX_BUF_STB (1U) /*!< Secondary transmit buffer. */ +/** + * @} + */ + +/** + * @defgroup CAN_Data_Length_Code CAN Data Length Code + * @{ + */ +#define CAN_DLC0 (0x0U) /*!< CAN2.0 and CAN FD: the size of data field is 0 bytes. */ +#define CAN_DLC1 (0x1U) /*!< CAN2.0 and CAN FD: the size of data field is 1 bytes. */ +#define CAN_DLC2 (0x2U) /*!< CAN2.0 and CAN FD: the size of data field is 2 bytes. */ +#define CAN_DLC3 (0x3U) /*!< CAN2.0 and CAN FD: the size of data field is 3 bytes. */ +#define CAN_DLC4 (0x4U) /*!< CAN2.0 and CAN FD: the size of data field is 4 bytes. */ +#define CAN_DLC5 (0x5U) /*!< CAN2.0 and CAN FD: the size of data field is 5 bytes. */ +#define CAN_DLC6 (0x6U) /*!< CAN2.0 and CAN FD: the size of data field is 6 bytes. */ +#define CAN_DLC7 (0x7U) /*!< CAN2.0 and CAN FD: the size of data field is 7 bytes. */ +#define CAN_DLC8 (0x8U) /*!< CAN2.0 and CAN FD: the size of data field is 8 bytes. */ +/** + * @} + */ + +/** + * @defgroup PTB_SingleShot_Tx_En PTB Single Shot Transmission Function Control + * @{ + */ +#define CAN_PTB_SINGLESHOT_TX_DISABLE (0x0U) /*!< Primary transmit buffer auto retransmit. */ +#define CAN_PTB_SINGLESHOT_TX_ENABLE (CAN_CFG_STAT_TPSS) /*!< Primary transmit buffer single short transmit. */ +/** + * @} + */ + +/** + * @defgroup STB_SingleShot_Tx_En STB Single Shot Transmission Function Control + * @{ + */ +#define CAN_STB_SINGLESHOT_TX_DISABLE (0x0U) /*!< Secondary transmit buffer auto retransmit. */ +#define CAN_STB_SINGLESHOT_TX_ENABLE (CAN_CFG_STAT_TSSS) /*!< Secondary transmit buffer single short transmit. */ +/** + * @} + */ + +/** + * @defgroup CAN_Tx_Request CAN Transmission Request + * @{ + */ +#define CAN_TX_REQ_STB_ONE (CAN_TCMD_TSONE) /*!< Transmit one STB frame. */ +#define CAN_TX_REQ_STB_ALL (CAN_TCMD_TSALL) /*!< Transmit all STB frames. */ +#define CAN_TX_REQ_PTB (CAN_TCMD_TPE) /*!< Transmit PTB frame. */ +/** + * @} + */ + +/** + * @defgroup CAN_STB_Prio_Mode_En CAN STB Priority Mode Function Control + * @note A frame in the PTB has always the highest priority regardless of the ID. + * @{ + */ +#define CAN_STB_PRIO_MD_DISABLE (0x0U) /*!< The frame first in will first be transmitted. */ +#define CAN_STB_PRIO_MD_ENABLE (CAN_TCTRL_TSMODE) /*!< The frame with lower ID will first be transmitted. */ +/** + * @} + */ + +/** + * @defgroup CAN_Tx_Buf_Status CAN Transmit Buffer Status + * @{ + */ +#define CAN_TX_BUF_EMPTY (0x0U) /*!< TTCAN is disabled(TTEN == 0): STB is empty. + TTCAN is disabled(TTEN == 1) and transmit buffer is specified by TBPTR and TTPTR(TTTBM == 1): + PTB and STB are both empty. */ +#define CAN_TX_BUF_NOT_MORE_THAN_HALF (0x1U) /*!< TTEN == 0: STB is less than or equal to half full; + TTEN == 1 && TTTBM == 1: PTB and STB are neither empty. */ +#define CAN_TX_BUF_MORE_THAN_HALF (0x2U) /*!< TTEN == 0: STB is more than half full; + TTEN == 1 && TTTBM == 1: reserved value. */ +#define CAN_TX_BUF_FULL (0x3U) /*!< TTEN == 0: STB is full; + TTEN == 1 && TTTBM == 1: PTB and STB are both full. */ +/** + * @} + */ + +/** + * @defgroup CAN_Rx_Buf_Status CAN Receive Buffer Status + * @{ + */ +#define CAN_RX_BUF_EMPTY (0x0U) /*!< Receive buffer is empty. */ +#define CAN_RX_BUF_NOT_WARN (0x1U) /*!< Receive buffer is not empty, but is less than almost full warning limit. */ +#define CAN_RX_BUF_WARN (0x2U) /*!< Receive buffer is not full and not overflow, but is more than or equal to almost full warning limit. */ +#define CAN_RX_BUF_FULL (0x3U) /*!< Receive buffer is full. */ +/** + * @} + */ + +/** + * @defgroup CAN_Rx_All_En CAN Receive All Frames + * @{ + */ +#define CAN_RX_ALL_FRAME_DISABLE (0x0U) /*!< Only receives correct frames. */ +#define CAN_RX_ALL_FRAME_ENABLE (CAN_RCTRL_RBALL) /*!< Receives all frames, including frames with error. */ +/** + * @} + */ + +/** + * @defgroup CAN_Rx_Ovf_Mode CAN Receive Buffer Overflow Mode + * @{ + */ +#define CAN_RX_OVF_SAVE_NEW (0x0U) /*!< Saves the newly received data and the oldest frame will be overwritten. */ +#define CAN_RX_OVF_DISCARD_NEW (CAN_RCTRL_ROM) /*!< Discard the newly received data. */ +/** + * @} + */ + +/** + * @defgroup CAN_Self_ACK_En CAN Self-ACK Function Control + * @{ + */ +#define CAN_SELF_ACK_DISABLE (0x0U) /*!< Disable self-acknowledge. */ +#define CAN_SELF_ACK_ENABLE (CAN_RCTRL_SACK) /*!< Enable self-acknowledge. */ +/** + * @} + */ + +/** + * @defgroup CAN_Interrupt_Type CAN Interrupt Type + * @{ + */ +#define CAN_INT_ERR_INT (1UL << 1U) /*!< Register bit RTIE.EIE. The interrupt RTIF.EIF will be set if enabled by RTIE.EIE under the following conditions: + The border of the error warning limit has been crossed in either direction by RECNT or TECNT or + the BUSOFF bit has been changed in either direction. */ +#define CAN_INT_STB_TX (1UL << 2U) /*!< Register bit RTIE.TSIE. STB was transmitted. */ +#define CAN_INT_PTB_TX (1UL << 3U) /*!< Register bit RTIE.TPIE. PTB was transmitted. */ +#define CAN_INT_RX_BUF_WARN (1UL << 4U) /*!< Register bit RTIE.RAFIE. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. */ +#define CAN_INT_RX_BUF_FULL (1UL << 5U) /*!< Register bit RTIE.RFIE. The FIFO of receive buffer is full. */ +#define CAN_INT_RX_OVERRUN (1UL << 6U) /*!< Register bit RTIE.ROIE. Receive buffers are full and there is a further message to be stored. */ +#define CAN_INT_RX (1UL << 7U) /*!< Register bit RTIE.RIE. Received a valid data frame or remote frame. */ +#define CAN_INT_BUS_ERR (1UL << 9U) /*!< Register bit ERRINT.BEIE. Each of the error defined by EALCAP.KOER can cause bus-error interrupt. */ +#define CAN_INT_ARBITR_LOST (1UL << 11U) /*!< Register bit ERRINT.ALIE. Arbitration lost. */ +#define CAN_INT_ERR_PASSIVE (1UL << 13U) /*!< Register bit ERRINT.EPIE. A change from error-passive to error-active or error-active to error-passive has occurred. */ + +#define CAN_INT_ALL (CAN_INT_ERR_INT | \ + CAN_INT_STB_TX | \ + CAN_INT_PTB_TX | \ + CAN_INT_RX_BUF_WARN | \ + CAN_INT_RX_BUF_FULL | \ + CAN_INT_RX_OVERRUN | \ + CAN_INT_RX | \ + CAN_INT_BUS_ERR | \ + CAN_INT_ARBITR_LOST | \ + CAN_INT_ERR_PASSIVE) +/** + * @} + */ + +/** + * @defgroup CAN_Status_Flag CAN Status Flag + * @{ + */ +#define CAN_FLAG_BUS_OFF (1UL << 0U) /*!< Register bit CFG_STAT.BUSOFF. CAN bus off. */ +#define CAN_FLAG_TX_GOING (1UL << 1U) /*!< Register bit CFG_STAT.TACTIVE. CAN bus is transmitting. */ +#define CAN_FLAG_RX_GOING (1UL << 2U) /*!< Register bit CFG_STAT.RACTIVE. CAN bus is receiving. */ +#define CAN_FLAG_RX_BUF_OVF (1UL << 5U) /*!< Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one frame will be lost. */ +#define CAN_FLAG_TX_BUF_FULL (1UL << 8U) /*!< Register bit RTIE.TSFF. Transmit buffers are all full. + TTCFG.TTEN == 0 or TCTRL.TTTEM == 0: ALL STB slots are filled. + TTCFG.TTEN == 1 and TCTRL.TTTEM == 1: Transmit buffer that pointed by TBSLOT.TBPTR is filled.*/ +#define CAN_FLAG_TX_ABORTED (1UL << 16U) /*!< Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled. */ +#define CAN_FLAG_ERR_INT (1UL << 17U) /*!< Register bit RTIF.EIF. The interrupt RTIF.EIF will be set if enabled by RTIE.EIE under the following conditions: + The border of the error warning limit has been crossed in either direction by RECNT or TECNT or + the BUSOFF bit has been changed in either direction. */ +#define CAN_FLAG_STB_TX (1UL << 18U) /*!< Register bit RTIF.TSIF. STB was transmitted. */ +#define CAN_FLAG_PTB_TX (1UL << 19U) /*!< Register bit RTIF.TPIF. PTB was transmitted. */ +#define CAN_FLAG_RX_BUF_WARN (1UL << 20U) /*!< Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. */ +#define CAN_FLAG_RX_BUF_FULL (1UL << 21U) /*!< Register bit RTIF.RFIF. The FIFO of receive buffer is full. */ +#define CAN_FLAG_RX_OVERRUN (1UL << 22U) /*!< Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored. */ +#define CAN_FLAG_RX (1UL << 23U) /*!< Register bit RTIF.RIF. Received a valid data frame or remote frame. */ +#define CAN_FLAG_BUS_ERR (1UL << 24U) /*!< Register bit ERRINT.BEIF. Each of the error defined by EALCAP.KOER can make this flag set. */ +#define CAN_FLAG_ARBITR_LOST (1UL << 26U) /*!< Register bit ERRINT.ALIF. Arbitration lost. */ +#define CAN_FLAG_ERR_PASSIVE (1UL << 28U) /*!< Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred. */ +#define CAN_FLAG_ERR_PASSIVE_NODE (1UL << 30U) /*!< Register bit ERRINT.EPASS. The node is an error-passive node. */ +#define CAN_FLAG_TEC_REC_WARN (1UL << 31U) /*!< Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value. */ + +#define CAN_FLAG_ALL (CAN_FLAG_BUS_OFF | \ + CAN_FLAG_TX_GOING | \ + CAN_FLAG_RX_GOING | \ + CAN_FLAG_RX_BUF_OVF | \ + CAN_FLAG_TX_BUF_FULL | \ + CAN_FLAG_TX_ABORTED | \ + CAN_FLAG_ERR_INT | \ + CAN_FLAG_STB_TX | \ + CAN_FLAG_PTB_TX | \ + CAN_FLAG_RX_BUF_WARN | \ + CAN_FLAG_RX_BUF_FULL | \ + CAN_FLAG_RX_OVERRUN | \ + CAN_FLAG_RX | \ + CAN_FLAG_BUS_ERR | \ + CAN_FLAG_ARBITR_LOST | \ + CAN_FLAG_ERR_PASSIVE | \ + CAN_FLAG_ERR_PASSIVE_NODE | \ + CAN_FLAG_TEC_REC_WARN) + +#define CAN_FLAG_CLR_ALL (CAN_FLAG_TX_ABORTED | \ + CAN_FLAG_ERR_INT | \ + CAN_FLAG_STB_TX | \ + CAN_FLAG_PTB_TX | \ + CAN_FLAG_RX_BUF_WARN | \ + CAN_FLAG_RX_BUF_FULL | \ + CAN_FLAG_RX_OVERRUN | \ + CAN_FLAG_RX | \ + CAN_FLAG_BUS_ERR | \ + CAN_FLAG_ARBITR_LOST | \ + CAN_FLAG_ERR_PASSIVE) +/** + * @} + */ + +/** + * @defgroup CAN_ID_Type CAN Identifier Type + * @{ + */ +#define CAN_ID_STD_EXT (0x0U) /*!< Acceptance filter accept frames with both standard ID and extended ID. */ +#define CAN_ID_STD (CAN_ACF_AIDEE) /*!< Acceptance filter accept frames with only standard ID. */ +#define CAN_ID_EXT (CAN_ACF_AIDEE | \ + CAN_ACF_AIDE) /*!< Acceptance filter accept frames with only extended ID. */ +/** + * @} + */ + +/** + * @defgroup CAN_Err_Type CAN Error Type + * @{ + */ +#define CAN_ERR_NONE (0U) /*!< No error. */ +#define CAN_ERR_BIT (0x1U) /*!< Error is bit error. */ +#define CAN_ERR_FORM (0x2U) /*!< Error is form error. */ +#define CAN_ERR_STUFF (0x3U) /*!< Error is stuff error. */ +#define CAN_ERR_ACK (0x4U) /*!< Error is ACK error. */ +#define CAN_ERR_CRC (0x5U) /*!< Error is CRC error. */ +#define CAN_ERR_OTHER (0x6U) /*!< Error is other error. + Dominant bits after own error flag, received active Error Flag too long, + dominant bit during Passive-Error-Flag after ACK error. */ +/** + * @} + */ + +/** + * @defgroup CAN_Acceptance_Filter CAN Acceptance Filter + * @{ + */ +#define CAN_FILTER1 (CAN_ACFEN_AE_1) /*!< Acceptance filter 1 select bit. */ +#define CAN_FILTER2 (CAN_ACFEN_AE_2) /*!< Acceptance filter 2 select bit. */ +#define CAN_FILTER3 (CAN_ACFEN_AE_3) /*!< Acceptance filter 3 select bit. */ +#define CAN_FILTER4 (CAN_ACFEN_AE_4) /*!< Acceptance filter 4 select bit. */ +#define CAN_FILTER5 (CAN_ACFEN_AE_5) /*!< Acceptance filter 5 select bit. */ +#define CAN_FILTER6 (CAN_ACFEN_AE_6) /*!< Acceptance filter 6 select bit. */ +#define CAN_FILTER7 (CAN_ACFEN_AE_7) /*!< Acceptance filter 7 select bit. */ +#define CAN_FILTER8 (CAN_ACFEN_AE_8) /*!< Acceptance filter 8 select bit. */ +#define CAN_FILTER_ALL (0xFFU) +/** + * @} + */ + +/** + * @defgroup TTCAN_Tx_Buf_Mode TTCAN Transmit Buffer Mode + * @{ + */ +#define CAN_TTC_TX_BUF_MD_CAN (0x0U) /*!< Normal CAN mode. TTCAN transmit buffer depends on the priority mode of STB which is defined by @ref CAN_STB_Prio_Mode_En */ +#define CAN_TTC_TX_BUF_MD_TTCAN (CAN_TCTRL_TTTBM) /*!< Full TTCAN mode. TTCAN transmit buffer is pointed by TBSLOT.TBPTR(for data filling) and + TRG_CFG.TTPTR(for data transmission). */ +/** + * @} + */ + +/** + * @defgroup TTCAN_Tx_Buf_Sel TTCAN Transmit Buffer Selection + * @{ + */ +#define CAN_TTC_TX_BUF_PTB (0x0U) /*!< Point to PTB. */ +#define CAN_TTC_TX_BUF_STB1 (0x1U) /*!< Point to STB slot 1. */ +#define CAN_TTC_TX_BUF_STB2 (0x2U) /*!< Point to STB slot 2. */ +#define CAN_TTC_TX_BUF_STB3 (0x3U) /*!< Point to STB slot 3. */ +#define CAN_TTC_TX_BUF_STB4 (0x4U) /*!< Point to STB slot 4. */ +/** + * @} + */ + +/** + * @defgroup TTCAN_Tx_Buf_Mark_State TTCAN Transmit Buffer Mark State + * @{ + */ +#define CAN_TTC_TX_BUF_MARK_EMPTY (CAN_TBSLOT_TBE) /*!< Marks the transmit buffer selected by TBSLOT.TBPTR as "empty". + TBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0. + If a transmission from this slot is active, then TBE stays set as long as either the + transmission completes or after a transmission error or arbitration loss the transmission + is not active any more. If both TBF and TBE are set, then TBE wins. */ +#define CAN_TTC_TX_BUF_MARK_FILLED (CAN_TBSLOT_TBF) /*!< Marks the transmit buffer selected by TBSLOT.TBPTR as "filled". + TBF is automatically reset to 0 as soon as the slot is marked as filled and RTIE.TSFF=1. + If both TBF and TBE are set, then TBE wins. */ +/** + * @} + */ + +/** + * @defgroup TTCAN_Interrupt_Type TTCAN Interrupt Type + * @{ + */ +#define CAN_TTC_INT_TIME_TRIG (CAN_TTCFG_TTIE) /*!< Time trigger interrupt. */ +#define CAN_TTC_INT_WATCH_TRIG (CAN_TTCFG_WTIE) /*!< Watch trigger interrupt. */ +#define CAN_TTC_INT_ALL (CAN_TTC_INT_TIME_TRIG | \ + CAN_TTC_INT_WATCH_TRIG) +/** + * @} + */ + +/** + * @defgroup TTCAN_Status_Flag TTCAN Status Flag + * @{ + */ +#define CAN_TTC_FLAG_TIME_TRIG (CAN_TTCFG_TTIF) /*!< Time trigger interrupt flag. */ +#define CAN_TTC_FLAG_TRIG_ERR (CAN_TTCFG_TEIF) /*!< Trigger error interrupt flag. */ +#define CAN_TTC_FLAG_WATCH_TRIG (CAN_TTCFG_WTIF) /*!< Watch trigger interrupt flag. */ + +#define CAN_TTC_FLAG_ALL (CAN_TTC_FLAG_TIME_TRIG | \ + CAN_TTC_FLAG_TRIG_ERR | \ + CAN_TTC_FLAG_WATCH_TRIG) +/** + * @} + */ + +/** + * @defgroup TTCAN_NTU_Prescaler TTCAN Network Time Unit Prescaler + * @{ + */ +#define CAN_TTC_NTU_PRESCALER1 (0x0U) /*!< NTU is SBT bit time * 1. */ +#define CAN_TTC_NTU_PRESCALER2 (CAN_TTCFG_T_PRESC_0) /*!< NTU is SBT bit time * 2. */ +#define CAN_TTC_NTU_PRESCALER4 (CAN_TTCFG_T_PRESC_1) /*!< NTU is SBT bit time * 4. */ +#define CAN_TTC_NTU_PRESCALER8 (CAN_TTCFG_T_PRESC) /*!< NTU is SBT bit time * 8. */ +/** + * @} + */ + +/** + * @defgroup TTCAN_Trigger_Type TTCAN Trigger Type + * @note Except for the immediate trigger, all triggers set TTIF if TTIE is enabled. + * @{ + */ +#define CAN_TTC_TRIG_IMMED_TRIG (0x0U) /*!< Immediate trigger for immediate transmission. */ +#define CAN_TTC_TRIG_TIME_TRIG (CAN_TRG_CFG_TTYPE_0) /*!< Time trigger for receive triggers. */ +#define CAN_TTC_TRIG_SINGLESHOT_TX_TRIG (CAN_TRG_CFG_TTYPE_1) /*!< Single shot transmit trigger for exclusive time windows. */ +#define CAN_TTC_TRIG_TX_START_TRIG (CAN_TRG_CFG_TTYPE_1 | \ + CAN_TRG_CFG_TTYPE_0) /*!< Transmit start trigger for merged arbitrating time windows. */ +#define CAN_TTC_TRIG_TX_STOP_TRIG (CAN_TRG_CFG_TTYPE_2) /*!< Transmit stop trigger for merged arbitrating time windows. */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CAN_Global_Functions + * @{ + */ +/* Classical CAN */ +int32_t CAN_Init(CM_CAN_TypeDef *CANx, const stc_can_init_t *pstcCanInit); +int32_t CAN_StructInit(stc_can_init_t *pstcCanInit); +void CAN_DeInit(CM_CAN_TypeDef *CANx); +void CAN_IntCmd(CM_CAN_TypeDef *CANx, uint32_t u32IntType, en_functional_state_t enNewState); +int32_t CAN_FillTxFrame(CM_CAN_TypeDef *CANx, uint8_t u8TxBufType, const stc_can_tx_frame_t *pstcTx); +void CAN_StartTx(CM_CAN_TypeDef *CANx, uint8_t u8TxRequest); +void CAN_AbortTx(CM_CAN_TypeDef *CANx, uint8_t u8TxBufType); +int32_t CAN_GetRxFrame(CM_CAN_TypeDef *CANx, stc_can_rx_frame_t *pstcRx); + +void CAN_EnterLocalReset(CM_CAN_TypeDef *CANx); +void CAN_ExitLocalReset(CM_CAN_TypeDef *CANx); +en_flag_status_t CAN_GetLocalResetStatus(CM_CAN_TypeDef *CANx); + +en_flag_status_t CAN_GetStatus(const CM_CAN_TypeDef *CANx, uint32_t u32Flag); +void CAN_ClearStatus(CM_CAN_TypeDef *CANx, uint32_t u32Flag); +uint32_t CAN_GetStatusValue(const CM_CAN_TypeDef *CANx); +int32_t CAN_GetErrorInfo(const CM_CAN_TypeDef *CANx, stc_can_error_info_t *pstcErr); +uint8_t CAN_GetTxBufStatus(const CM_CAN_TypeDef *CANx); +uint8_t CAN_GetRxBufStatus(const CM_CAN_TypeDef *CANx); +void CAN_FilterCmd(CM_CAN_TypeDef *CANx, uint16_t u16FilterSelect, en_functional_state_t enNewState); +void CAN_SetRxWarnLimit(CM_CAN_TypeDef *CANx, uint8_t u8RxWarnLimit); +void CAN_SetErrorWarnLimit(CM_CAN_TypeDef *CANx, uint8_t u8ErrorWarnLimit); + +/* TTCAN */ +int32_t CAN_TTC_StructInit(stc_can_ttc_config_t *pstcCanTtc); +int32_t CAN_TTC_Config(CM_CAN_TypeDef *CANx, const stc_can_ttc_config_t *pstcCanTtc); +void CAN_TTC_IntCmd(CM_CAN_TypeDef *CANx, uint8_t u8IntType, en_functional_state_t enNewState); +void CAN_TTC_Cmd(CM_CAN_TypeDef *CANx, en_functional_state_t enNewState); + +en_flag_status_t CAN_TTC_GetStatus(const CM_CAN_TypeDef *CANx, uint8_t u8Flag); +void CAN_TTC_ClearStatus(CM_CAN_TypeDef *CANx, uint8_t u8Flag); +uint8_t CAN_TTC_GetStatusValue(const CM_CAN_TypeDef *CANx); + +void CAN_TTC_SetTriggerType(CM_CAN_TypeDef *CANx, uint16_t u16TriggerType); +void CAN_TTC_SetTxEnableWindow(CM_CAN_TypeDef *CANx, uint16_t u16TxEnableWindow); +void CAN_TTC_SetTxTriggerTime(CM_CAN_TypeDef *CANx, uint16_t u16TxTriggerTime); +void CAN_TTC_SetWatchTriggerTime(CM_CAN_TypeDef *CANx, uint16_t u16WatchTriggerTime); + +int32_t CAN_TTC_FillTxFrame(CM_CAN_TypeDef *CANx, uint8_t u8CANTTCTxBuf, const stc_can_tx_frame_t *pstcTx); + +int32_t CAN_TTC_GetConfig(const CM_CAN_TypeDef *CANx, stc_can_ttc_config_t *pstcCanTtc); + +/** + * @} + */ + +#endif /* LL_CAN_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_CAN_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_clk.h b/mcu/lib/inc/hc32_ll_clk.h new file mode 100644 index 0000000..29b40e4 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_clk.h @@ -0,0 +1,714 @@ +/** + ******************************************************************************* + * @file hc32_ll_clk.h + * @brief This file contains all the functions prototypes of the CLK driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Refine stc_clock_freq_t + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_CLK_H__ +#define __HC32_LL_CLK_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_CLK + * @{ + */ + +#if (LL_CLK_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CLK_Global_Types CLK Global Types + * @{ + */ +/** + * @brief CLK XTAL configuration structure definition + */ +typedef struct { + uint8_t u8State; /*!< The new state of the XTAL. + This parameter can be a value of @ref CLK_XTAL_Config */ + uint8_t u8Drv; /*!< The XTAL drive ability. + This parameter can be a value of @ref CLK_XTAL_Config */ + uint8_t u8Mode; /*!< The XTAL mode selection osc or exclk. + This parameter can be a value of @ref CLK_XTAL_Config */ + uint8_t u8SuperDrv; /*!< The XTAL super drive on or off. + This parameter can be a value of @ref CLK_XTAL_Config */ + uint8_t u8StableTime; /*!< The XTAL stable time selection. + This parameter can be a value of @ref CLK_XTAL_Config */ +} stc_clock_xtal_init_t; + +/** + * @brief CLK XTAL fault detect configuration structure definition + */ +typedef struct { + uint8_t u8State; /*!< Specifies the new state of XTALSTD. + This parameter can be a value of @ref CLK_XTALSTD_Config */ + uint8_t u8Mode; /*!< Specifies the XTALSTD mode. + This parameter can be a value of @ref CLK_XTALSTD_Config */ + uint8_t u8Int; /*!< Specifies the XTALSTD interrupt on or off. + This parameter can be a value of @ref CLK_XTALSTD_Config */ + uint8_t u8Reset; /*!< Specifies the XTALSTD reset on or off. + This parameter can be a value of @ref CLK_XTALSTD_Config */ +} stc_clock_xtalstd_init_t; + +/** + * @brief CLK XTAL32 configuration structure definition + */ +typedef struct { + uint8_t u8State; /*!< Xtal32 new state, + @ref CLK_XTAL32_Config for details */ + uint8_t u8Drv; /*!< Xtal32 drive capacity setting, + @ref CLK_XTAL32_Config for details */ + uint8_t u8Filter; /*!< Xtal32 noise filter setting, + @ref CLK_XTAL32_Config for details */ +} stc_clock_xtal32_init_t; + +/** + * @brief CLK clock frequency configuration structure definition + */ +typedef struct { + union { + uint32_t SCFGR; /*!< clock frequency config register */ + struct { + uint32_t PCLK0S : 3; /*!< PCLK0 */ + uint32_t resvd0 : 1; /*!< reserved */ + uint32_t PCLK1S : 3; /*!< PCLK1 */ + uint32_t resvd1 : 1; /*!< reserved */ + uint32_t PCLK2S : 3; /*!< PCLK2 */ + uint32_t resvd2 : 1; /*!< reserved */ + uint32_t PCLK3S : 3; /*!< PCLK3 */ + uint32_t resvd3 : 1; /*!< reserved */ + uint32_t PCLK4S : 3; /*!< PCLK4 */ + uint32_t resvd4 : 1; /*!< reserved */ + uint32_t EXCKS : 3; /*!< EXCLK */ + uint32_t resvd5 : 1; /*!< reserved */ + uint32_t HCLKS : 3; /*!< HCLK */ + uint32_t resvd6 : 5; /*!< reserved */ + } SCFGR_f; + }; +} stc_clock_scale_t; + +/** + * @brief CLK PLL configuration structure definition + * @note PLL for MPLL + */ +typedef struct { + uint8_t u8PLLState; /*!< PLL new state, @ref CLK_PLL_Config for details */ + union { + uint32_t PLLCFGR; /*!< PLL config register */ + struct { + uint32_t PLLM : 5; /*!< PLL M divide */ + uint32_t resvd0 : 2; /*!< reserved */ + uint32_t PLLSRC : 1; /*!< PLL/PLLA source clock select */ + uint32_t PLLN : 9; /*!< PLL N multi */ + uint32_t resvd1 : 3; /*!< reserved */ + uint32_t PLLR : 4; /*!< PLL R divide */ + uint32_t PLLQ : 4; /*!< PLL Q divide */ + uint32_t PLLP : 4; /*!< PLL P divide */ + } PLLCFGR_f; + }; +} stc_clock_pll_init_t; + +/** + * @brief CLK PLLx configuration structure definition + * @note PLLx for UPLL while HC32F460,HC32F451,HC32F452 + * PLLx for PLLA while HC32F4A0 + */ +typedef struct { + uint8_t u8PLLState; /*!< PLLx new state, @ref CLK_PLLx_State for details */ + union { + uint32_t PLLCFGR; /*!< PLLx config register */ + struct { + uint32_t PLLM : 5; /*!< PLLx M divide */ + uint32_t resvd0 : 3; /*!< reserved */ + uint32_t PLLN : 9; /*!< PLLx N multi- */ + uint32_t resvd1 : 3; /*!< reserved */ + uint32_t PLLR : 4; /*!< PLLx R divide */ + uint32_t PLLQ : 4; /*!< PLLx Q divide */ + uint32_t PLLP : 4; /*!< PLLx P divide */ + } PLLCFGR_f; + }; +} stc_clock_pllx_init_t; + +/** + * @brief CLK bus frequency structure definition + */ +typedef struct { + uint32_t u32SysclkFreq; /*!< System clock frequency. */ + uint32_t u32HclkFreq; /*!< Hclk frequency. */ + uint32_t u32Pclk0Freq; /*!< Pclk0 frequency. */ + uint32_t u32Pclk1Freq; /*!< Pclk1 frequency. */ + uint32_t u32Pclk2Freq; /*!< Pclk2 frequency. */ + uint32_t u32Pclk3Freq; /*!< Pclk3 frequency. */ + uint32_t u32Pclk4Freq; /*!< Pclk4 frequency. */ + uint32_t u32ExclkFreq; /*!< Exclk frequency. */ +} stc_clock_freq_t; + +/** + * @brief CLK PLL clock frequency structure definition + */ +typedef struct { + uint32_t u32PllVcin; /*!< PLL vcin clock frequency. */ + uint32_t u32PllVco; /*!< PLL vco clock frequency. */ + uint32_t u32PllP; /*!< PLLp clock frequency. */ + uint32_t u32PllQ; /*!< PLLq clock frequency. */ + uint32_t u32PllR; /*!< PLLr clock frequency. */ + uint32_t u32PllxVcin; /*!< pllx vcin clock frequency. */ + uint32_t u32PllxVco; /*!< pllx vco clock frequency. */ + uint32_t u32PllxP; /*!< pllxp clock frequency. */ + uint32_t u32PllxQ; /*!< pllxq clock frequency. */ + uint32_t u32PllxR; /*!< pllxr clock frequency. */ +} stc_pll_clock_freq_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CLK_Global_Macros CLK Global Macros + * @{ + */ +/** + * @defgroup CLK_PLLx_State CLK PLLx State + * @note PLLx for UPLL while HC32F460,HC32F451,HC32F452 + * PLLx for PLLA while HC32F4A0 + * @{ + */ +#define CLK_PLLX_OFF (0x01U) +#define CLK_PLLX_ON (0x00U) +/** + * @} + */ + +/** + * @defgroup CLK_PLL_Config PLL Config + * @{ + */ +/** + * @brief PLL function config. + */ +#define CLK_PLL_OFF (0x01U) +#define CLK_PLL_ON (0x00U) + +/** + * @brief PLL source clock selection. + */ +#define CLK_PLL_SRC_XTAL (0x00UL) +#define CLK_PLL_SRC_HRC (0x01UL) +/** + * @} + */ + +/** + * @defgroup CLK_XTAL_Config XTAL Config + * @{ + */ +/** + * @brief XTAL function config. + */ +#define CLK_XTAL_OFF (CMU_XTALCR_XTALSTP) +#define CLK_XTAL_ON (0x00U) + +/** + * @brief XTAL driver ability + * @note + * @verbatim + * High | Mid | Low | ULow | + * [20~25] | [16~20) | (8~16) | [4~8] | + * @endverbatim + */ +#define CLK_XTAL_DRV_HIGH (0x00U << CMU_XTALCFGR_XTALDRV_POS) +#define CLK_XTAL_DRV_MID (0x01U << CMU_XTALCFGR_XTALDRV_POS) +#define CLK_XTAL_DRV_LOW (0x02U << CMU_XTALCFGR_XTALDRV_POS) +#define CLK_XTAL_DRV_ULOW (0x03U << CMU_XTALCFGR_XTALDRV_POS) + +/** + * @brief XTAL super drive on or off + */ +#define CLK_XTAL_SUPDRV_ON (CMU_XTALCFGR_SUPDRV) +#define CLK_XTAL_SUPDRV_OFF (0x00U) + +/** + * @brief XTAL mode selection osc or exclk + */ +#define CLK_XTAL_MD_OSC (0x00U) +#define CLK_XTAL_MD_EXCLK (CMU_XTALCFGR_XTALMS) + +/** + * @brief XTAL stable time selection. + * @note a cycle of stable counter = a cycle of LRC divide by 8 + */ +#define CLK_XTAL_STB_133US (0x01U) /*!< 35 stable count cycle, approx. 133us */ +#define CLK_XTAL_STB_255US (0x02U) /*!< 67 stable count cycle, approx. 255us */ +#define CLK_XTAL_STB_499US (0x03U) /*!< 131 stable count cycle, approx. 499us */ +#define CLK_XTAL_STB_988US (0x04U) /*!< 259 stable count cycle, approx. 988us */ +#define CLK_XTAL_STB_2MS (0x05U) /*!< 547 stable count cycle, approx. 2ms */ +#define CLK_XTAL_STB_4MS (0x06U) /*!< 1059 stable count cycle, approx. 4ms */ +#define CLK_XTAL_STB_8MS (0x07U) /*!< 2147 stable count cycle, approx. 8ms */ +#define CLK_XTAL_STB_16MS (0x08U) /*!< 4291 stable count cycle, approx. 16ms */ +#define CLK_XTAL_STB_31MS (0x09U) /*!< 8163 stable count cycle, approx. 32ms */ +/** + * @} + */ + +/** + * @defgroup CLK_XTALSTD_Config XTALSTD Config + * @{ + */ + +/** + * @brief XTAL error detection on or off + */ +#define CLK_XTALSTD_OFF (0x00U) +#define CLK_XTALSTD_ON (CMU_XTALSTDCR_XTALSTDE) + +/** + * @brief XTALSTD mode selection + */ +#define CLK_XTALSTD_MD_RST (CMU_XTALSTDCR_XTALSTDRIS) +#define CLK_XTALSTD_MD_INT (0x00U) + +/** + * @brief XTALSTD reset on or off + */ +#define CLK_XTALSTD_RST_OFF (0x00U) +#define CLK_XTALSTD_RST_ON (CMU_XTALSTDCR_XTALSTDRE) + +/** + * @brief XTALSTD interrupt on or off + */ +#define CLK_XTALSTD_INT_OFF (0x00U) +#define CLK_XTALSTD_INT_ON (CMU_XTALSTDCR_XTALSTDIE) +/** + * @} + */ + +/** + * @defgroup CLK_XTAL32_Config XTAL32 Config + * @{ + */ +/** + * @brief XTAL32 function config. + */ +#define CLK_XTAL32_OFF (CMU_XTAL32CR_XTAL32STP) +#define CLK_XTAL32_ON (0x00U) + +/** + * @brief XTAL32 driver ability. + */ +#define CLK_XTAL32_DRV_MID (0x00U) +#define CLK_XTAL32_DRV_HIGH (0x01U) + +/** + * @brief XTAL32 filtering selection. + */ +#define CLK_XTAL32_FILTER_ALL_MD (0x00U) /*!< Valid in run,stop,power down mode. */ +#define CLK_XTAL32_FILTER_RUN_MD (0x01U) /*!< Valid in run mode. */ +#define CLK_XTAL32_FILTER_OFF (0x03U) /*!< Invalid in run,stop,power down mode. */ +/** + * @} + */ + +/** + * @defgroup CLK_HRC_Config HRC Config + * @{ + */ +#define CLK_HRC_OFF (CMU_HRCCR_HRCSTP) +#define CLK_HRC_ON (0x00U) +/** + * @} + */ + +/** + * @defgroup CLK_STB_Flag CLK Stable Flags + * @{ + */ +#define CLK_STB_FLAG_HRC (CMU_OSCSTBSR_HRCSTBF) +#define CLK_STB_FLAG_XTAL (CMU_OSCSTBSR_XTALSTBF) +#define CLK_STB_FLAG_PLL (CMU_OSCSTBSR_MPLLSTBF) +#define CLK_STB_FLAG_PLLX (CMU_OSCSTBSR_UPLLSTBF) +#define CLK_STB_FLAG_MASK (CMU_OSCSTBSR_HRCSTBF | CMU_OSCSTBSR_XTALSTBF | \ + CMU_OSCSTBSR_MPLLSTBF | CMU_OSCSTBSR_UPLLSTBF) +/** + * @} + */ + +/** + * @defgroup CLK_System_Clock_Source System Clock Source + * @{ + */ +#define CLK_SYSCLK_SRC_HRC (0x00U) +#define CLK_SYSCLK_SRC_MRC (0x01U) +#define CLK_SYSCLK_SRC_LRC (0x02U) +#define CLK_SYSCLK_SRC_XTAL (0x03U) +#define CLK_SYSCLK_SRC_XTAL32 (0x04U) +#define CLK_SYSCLK_SRC_PLL (0x05U) +/** + * @} + */ + +/** + * @defgroup CLK_Bus_Clock_Sel Clock Bus Clock Category Selection + * @{ + */ +#define CLK_BUS_PCLK0 (CMU_SCFGR_PCLK0S) +#define CLK_BUS_PCLK1 (CMU_SCFGR_PCLK1S) +#define CLK_BUS_PCLK2 (CMU_SCFGR_PCLK2S) +#define CLK_BUS_PCLK3 (CMU_SCFGR_PCLK3S) +#define CLK_BUS_PCLK4 (CMU_SCFGR_PCLK4S) +#define CLK_BUS_EXCLK (CMU_SCFGR_EXCKS) +#define CLK_BUS_HCLK (CMU_SCFGR_HCLKS) +#define CLK_BUS_CLK_ALL (CLK_BUS_PCLK0 | CLK_BUS_PCLK1 | CLK_BUS_PCLK2 | CLK_BUS_PCLK3 | \ + CLK_BUS_PCLK4 | CLK_BUS_EXCLK | CLK_BUS_HCLK) +/** + * @} + */ + +/** + * @defgroup CLK_Clock_Divider Clock Divider + * @{ + */ + +/** + * @defgroup CLK_System_Clock_Divider System Clock Divider + * @{ + */ +#define CLK_SYSCLK_DIV1 (0x00U) +#define CLK_SYSCLK_DIV2 (0x01U) +#define CLK_SYSCLK_DIV4 (0x02U) +#define CLK_SYSCLK_DIV8 (0x03U) +#define CLK_SYSCLK_DIV16 (0x04U) +#define CLK_SYSCLK_DIV32 (0x05U) +#define CLK_SYSCLK_DIV64 (0x06U) +/** + * @} + */ + +/** + * @defgroup CLK_HCLK_Divider CLK HCLK Divider + * @{ + */ +#define CLK_HCLK_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_HCLKS_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK1_Divider CLK PCLK1 Divider + * @{ + */ +#define CLK_PCLK1_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK1S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK4_Divider CLK PCLK4 Divider + * @{ + */ +#define CLK_PCLK4_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK4S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK3_Divider CLK PCLK3 Divider + * @{ + */ +#define CLK_PCLK3_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK3S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_EXCLK_Divider CLK EXCLK Divider + * @{ + */ +#define CLK_EXCLK_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_EXCKS_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK2_Divider CLK PCLK2 Divider + * @{ + */ +#define CLK_PCLK2_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK2S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK0_Divider CLK PCLK0 Divider + * @{ + */ +#define CLK_PCLK0_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK0S_POS) +/** + * @} + */ +/** + * @} + */ + +/** + * @defgroup CLK_USBCLK_Sel CLK USB Clock Selection + * @{ + */ +#define CLK_USBCLK_SYSCLK_DIV2 (0x02U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_SYSCLK_DIV3 (0x03U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_SYSCLK_DIV4 (0x04U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_PLLP (0x08U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_PLLQ (0x09U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_PLLR (0x0AU << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_PLLXP (0x0BU << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_PLLXQ (0x0CU << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_PLLXR (0x0DU << CMU_USBCKCFGR_USBCKS_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PERIPH_Sel CLK Peripheral Clock Selection + * @note ADC,I2S,DAC,TRNG + * @{ + */ +/* PCLK2 is used for ADC clock, PCLK3 is used for I2S clock, PCLK4 is used for DAC/TRNG clock */ +#define CLK_PERIPHCLK_PCLK (0x0000U) +#define CLK_PERIPHCLK_PLLP (0x0008U) +#define CLK_PERIPHCLK_PLLQ (0x0009U) +#define CLK_PERIPHCLK_PLLR (0x000AU) +#define CLK_PERIPHCLK_PLLXP (0x000BU) +#define CLK_PERIPHCLK_PLLXQ (0x000CU) +#define CLK_PERIPHCLK_PLLXR (0x000DU) +/** + * @} + */ + +/** + * @defgroup CLK_I2S_Sel CLK I2S Channel Selection + * @{ + */ +#define CLK_I2S1 (0x00U) +#define CLK_I2S2 (0x01U) +#define CLK_I2S3 (0x02U) +#define CLK_I2S4 (0x03U) +/** + * @} + */ + +/** + * @defgroup CLK_TPIU_Divider TPIU clock divider + * @{ + */ +#define CLK_TPIUCLK_DIV1 (0x00U) +#define CLK_TPIUCLK_DIV2 (0x01U) +#define CLK_TPIUCLK_DIV4 (0x02U) +/** + * @} + */ + +/** + * @defgroup CLK_MCO_Channel_Sel CLK MCO Channel Select + * @{ + */ +#define CLK_MCO1 (0x00U) +#define CLK_MCO2 (0x01U) +/** + * @} + */ + +/** + * @defgroup CLK_MCO_Clock_Source CLK MCO Clock Source + * @{ + */ +#define CLK_MCO_SRC_HRC (0x00U) +#define CLK_MCO_SRC_MRC (0x01U) +#define CLK_MCO_SRC_LRC (0x02U) +#define CLK_MCO_SRC_XTAL (0x03U) +#define CLK_MCO_SRC_XTAL32 (0x04U) +#define CLK_MCO_SRC_PLLP (0x06U) +#define CLK_MCO_SRC_PLLXP (0x07U) +#define CLK_MCO_SRC_PLLQ (0x08U) +#define CLK_MCO_SRC_PLLXQ (0x09U) +#define CLK_MCO_SRC_HCLK (0x0BU) +/** + * @} + */ + +/** + * @defgroup CLK_MCO_Clock_Prescaler CLK MCO Clock Prescaler + * @{ + */ +#define CLK_MCO_DIV1 (0x00U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV2 (0x01U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV4 (0x02U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV8 (0x03U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV16 (0x04U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV32 (0x05U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV64 (0x06U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV128 (0x07U << CMU_MCOCFGR_MCODIV_POS) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CLK_Global_Functions + * @{ + */ +int32_t CLK_HrcCmd(en_functional_state_t enNewState); +int32_t CLK_MrcCmd(en_functional_state_t enNewState); +int32_t CLK_LrcCmd(en_functional_state_t enNewState); + +void CLK_HrcTrim(int8_t i8TrimVal); +void CLK_MrcTrim(int8_t i8TrimVal); +void CLK_LrcTrim(int8_t i8TrimVal); + +int32_t CLK_XtalStructInit(stc_clock_xtal_init_t *pstcXtalInit); +int32_t CLK_XtalInit(const stc_clock_xtal_init_t *pstcXtalInit); +int32_t CLK_XtalCmd(en_functional_state_t enNewState); + +int32_t CLK_XtalStdStructInit(stc_clock_xtalstd_init_t *pstcXtalStdInit); +int32_t CLK_XtalStdInit(const stc_clock_xtalstd_init_t *pstcXtalStdInit); +void CLK_ClearXtalStdStatus(void); +en_flag_status_t CLK_GetXtalStdStatus(void); + +int32_t CLK_Xtal32StructInit(stc_clock_xtal32_init_t *pstcXtal32Init); +int32_t CLK_Xtal32Init(const stc_clock_xtal32_init_t *pstcXtal32Init); +int32_t CLK_Xtal32Cmd(en_functional_state_t enNewState); + +void CLK_SetPLLSrc(uint32_t u32PllSrc); +int32_t CLK_PLLStructInit(stc_clock_pll_init_t *pstcPLLInit); +int32_t CLK_PLLInit(const stc_clock_pll_init_t *pstcPLLInit); +int32_t CLK_PLLCmd(en_functional_state_t enNewState); +int32_t CLK_GetPLLClockFreq(stc_pll_clock_freq_t *pstcPllClkFreq); +int32_t CLK_PLLxStructInit(stc_clock_pllx_init_t *pstcPLLxInit); +int32_t CLK_PLLxInit(const stc_clock_pllx_init_t *pstcPLLxInit); +int32_t CLK_PLLxCmd(en_functional_state_t enNewState); + +void CLK_MCOConfig(uint8_t u8Ch, uint8_t u8Src, uint8_t u8Div); +void CLK_MCOCmd(uint8_t u8Ch, en_functional_state_t enNewState); + +en_flag_status_t CLK_GetStableStatus(uint8_t u8Flag); +void CLK_SetSysClockSrc(uint8_t u8Src); +void CLK_SetClockDiv(uint32_t u32Clock, uint32_t u32Div); +int32_t CLK_GetClockFreq(stc_clock_freq_t *pstcClockFreq); +uint32_t CLK_GetBusClockFreq(uint32_t u32Clock); + +void CLK_SetPeriClockSrc(uint16_t u16Src); +void CLK_SetUSBClockSrc(uint8_t u8Src); +void CLK_SetI2SClockSrc(uint8_t u8Unit, uint8_t u8Src); + +void CLK_TpiuClockCmd(en_functional_state_t enNewState); +void CLK_SetTpiuClockDiv(uint8_t u8Div); +/** + * @} + */ + +#endif /* LL_CLK_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_CLK_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_cmp.h b/mcu/lib/inc/hc32_ll_cmp.h new file mode 100644 index 0000000..a1ca014 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_cmp.h @@ -0,0 +1,275 @@ +/** + ******************************************************************************* + * @file hc32_ll_cmp.h + * @brief This file contains all the functions prototypes of the CMP driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Modify macro define for API + 2023-01-15 CDT Code refine for scan function + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_CMP_H__ +#define __HC32_LL_CMP_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_CMP + * @{ + */ + +#if (LL_CMP_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CMP_Global_Types CMP Global Types + * @{ + */ + +/** + * @brief CMP normal mode configuration structure + */ +typedef struct { + uint16_t u16PositiveInput; /*!< Positive(compare voltage) input @ref CMP_Positive_Input_Select */ + uint16_t u16NegativeInput; /*!< Negative(Reference voltage) input @ref CMP_Negative_Input_Select */ + uint16_t u16OutPolarity; /*!< Output polarity select, @ref CMP_Out_Polarity_Select */ + uint16_t u16OutDetectEdge; /*!< Output detect edge, @ref CMP_Out_Detect_Edge_Select */ + uint16_t u16OutFilter; /*!< Output Filter, @ref CMP_Out_Filter */ +} stc_cmp_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup CMP_Global_Macros CMP Global Macros + * @{ + */ + +#define VISR_OFFSET (8U) + +/** + * @defgroup CMP_Positive_Input_Select CMP Positive(Compare) Voltage Input + * @{ + */ +#define CMP_POSITIVE_NONE (0x0U) +/* Note: + Normal mode: + 1) Select one positive input from the following values. + Scan mode: + 2) Select any combination of the following values, but the XXX_PGAO/ XXX_PGAO_BP/ XXX_CMP1_INP4/ XXX_CMP3_INP4 + should not be valid at the same time. +*/ +/* CMP1 */ +#define CMP1_POSITIVE_CMP1_INP1 (CMP_VLTSEL_CVSL_0) /*!< Pin CMP1_INP1 */ +#define CMP1_POSITIVE_CMP1_INP2 (CMP_VLTSEL_CVSL_1) /*!< Pin CMP1_INP2 */ +#define CMP1_POSITIVE_CMP1_INP3 (CMP_VLTSEL_CVSL_2) /*!< Pin CMP1_INP3 */ +#define CMP1_POSITIVE_PGAO (CMP_VLTSEL_CVSL_3 | CMP_VLTSEL_C4SL_0) /*!< Internal voltage PGAO */ +#define CMP1_POSITIVE_PGAO_BP (CMP_VLTSEL_CVSL_3 | CMP_VLTSEL_C4SL_1) /*!< Internal voltage PGAO_BP */ +#define CMP1_POSITIVE_CMP1_INP4 (CMP_VLTSEL_CVSL_3 | CMP_VLTSEL_C4SL_2) /*!< Pin CMP1_INP4 */ +/* CMP2 */ +#define CMP2_POSITIVE_CMP2_INP1 (CMP_VLTSEL_CVSL_0) /*!< Pin CMP2_INP1 */ +#define CMP2_POSITIVE_CMP2_INP2 (CMP_VLTSEL_CVSL_1) /*!< Pin CMP2_INP2 */ +#define CMP2_POSITIVE_CMP2_INP3 (CMP_VLTSEL_CVSL_2) /*!< Pin CMP2_INP3 */ +#define CMP2_POSITIVE_PGAO (CMP_VLTSEL_CVSL_3 | CMP_VLTSEL_C4SL_0) /*!< Internal voltage PGAO */ +#define CMP2_POSITIVE_PGAO_BP (CMP_VLTSEL_CVSL_3 | CMP_VLTSEL_C4SL_1) /*!< Internal voltage PGAO_BP */ +/* CMP3 */ +#define CMP3_POSITIVE_CMP3_INP1 (CMP_VLTSEL_CVSL_0) /*!< Pin CMP3_INP1 */ +#define CMP3_POSITIVE_CMP3_INP2 (CMP_VLTSEL_CVSL_1) /*!< Pin CMP3_INP2 */ +#define CMP3_POSITIVE_CMP3_INP3 (CMP_VLTSEL_CVSL_2) /*!< Pin CMP3_INP3 */ +#define CMP3_POSITIVE_CMP3_INP4 (CMP_VLTSEL_CVSL_3) /*!< Pin CMP3_INP4 */ +/** + * @} + */ + +/** + * @defgroup CMP_Scan_Inp_Status CMP Scan Function Positive In INP Source + * @{ + */ +#define CMP_SCAN_STAT_INP_NONE (0U) +#define CMP_SCAN_STAT_INP1 (1U << CMP_OUTMON_CVST_POS) +#define CMP_SCAN_STAT_INP2 (2U << CMP_OUTMON_CVST_POS) +#define CMP_SCAN_STAT_INP3 (4U << CMP_OUTMON_CVST_POS) +#define CMP_SCAN_STAT_INP4 (8U << CMP_OUTMON_CVST_POS) +/** + * @} + */ + +/** + * @defgroup CMP_Negative_Input_Select CMP Negative(Reference) Voltage Input + * @{ + */ +#define CMP_NEGATIVE_NONE (0x0U) +/* Negative input select table + CMP1 CMP2 CMP3 +---------------------------------------------------- +INM1 CMP1_INM1 CMP2_INM1 CMP3_INM1 +INM2 CMP1_INM2 CMP2_INM2 CMP3_INM2 +INM3 DAC1 DAC2 DAC1 +INM4 VREF VREF DAC2 +*/ +#define CMP_NEGATIVE_INM1 (1U << CMP_VLTSEL_RVSL_POS) +#define CMP_NEGATIVE_INM2 (2U << CMP_VLTSEL_RVSL_POS) +#define CMP_NEGATIVE_INM3 (4U << CMP_VLTSEL_RVSL_POS) +#define CMP_NEGATIVE_INM4 (8U << CMP_VLTSEL_RVSL_POS) +/** + * @} + */ + +/** + * @defgroup CMP_Out_Polarity_Select CMP Output Polarity + * @{ + */ +#define CMP_OUT_INVT_OFF (0x0U) /*!< CMP output don't reverse */ +#define CMP_OUT_INVT_ON (CMP_CTRL_INV) /*!< CMP output level reverse */ +/** + * @} + */ + +/** + * @defgroup CMP_Out_Detect_Edge_Select CMP Output Detect Edge + * @{ + */ +#define CMP_DETECT_EDGS_NONE (0U) /*!< Do not detect edge */ +#define CMP_DETECT_EDGS_RISING (1U << CMP_CTRL_EDGSL_POS) /*!< Detect rising edge */ +#define CMP_DETECT_EDGS_FALLING (2U << CMP_CTRL_EDGSL_POS) /*!< Detect falling edge */ +#define CMP_DETECT_EDGS_BOTH (3U << CMP_CTRL_EDGSL_POS) /*!< Detect rising and falling edges */ +/** + * @} + */ + +/** + * @defgroup CMP_Out_Filter CMP Output Filter Configuration + * @{ + */ +#define CMP_OUT_FILTER_NONE (0U) /*!< Do not filter */ +#define CMP_OUT_FILTER_CLK (1U << CMP_CTRL_FLTSL_POS) +#define CMP_OUT_FILTER_CLK_DIV2 (2U << CMP_CTRL_FLTSL_POS) +#define CMP_OUT_FILTER_CLK_DIV4 (3U << CMP_CTRL_FLTSL_POS) +#define CMP_OUT_FILTER_CLK_DIV8 (4U << CMP_CTRL_FLTSL_POS) +#define CMP_OUT_FILTER_CLK_DIV16 (5U << CMP_CTRL_FLTSL_POS) +#define CMP_OUT_FILTER_CLK_DIV32 (6U << CMP_CTRL_FLTSL_POS) +#define CMP_OUT_FILTER_CLK_DIV64 (7U << CMP_CTRL_FLTSL_POS) +/** + * @} + */ + +/** + * @defgroup CMP_8BitDAC_Adc_Ref_Switch CMP 8 bit DAC ADC Reference Voltage Switch + * @{ + */ +#define CMP_ADC_REF_VREF (CMPCR_RVADC_VREFSW) +#define CMP_ADC_REF_DA2 (CMPCR_RVADC_DA2SW) +#define CMP_ADC_REF_DA1 (CMPCR_RVADC_DA1SW) +/** + * @} + */ + +/** + * @defgroup CMP_8Bit_Dac_Ch CMP 8 bit DAC Channel + * @{ + */ +#define CMP_8BITDAC_CH1 (CMPCR_DACR_DA1EN) +#define CMP_8BITDAC_CH2 (CMPCR_DACR_DA2EN) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CMP_Global_Functions + * @{ + */ + +int32_t CMP_StructInit(stc_cmp_init_t *pstcCmpInit); +int32_t CMP_NormalModeInit(CM_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcCmpInit); +void CMP_DeInit(CM_CMP_TypeDef *CMPx); + +void CMP_FuncCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); +void CMP_IntCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); +void CMP_CompareOutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); +void CMP_PinVcoutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); +en_flag_status_t CMP_GetStatus(const CM_CMP_TypeDef *CMPx); +void CMP_SetOutDetectEdge(CM_CMP_TypeDef *CMPx, uint8_t u8CmpEdges); +void CMP_SetOutFilter(CM_CMP_TypeDef *CMPx, uint8_t u8CmpFilter); +void CMP_SetOutPolarity(CM_CMP_TypeDef *CMPx, uint16_t u16CmpPolarity); +void CMP_SetPositiveInput(CM_CMP_TypeDef *CMPx, uint16_t u16PositiveInput); +void CMP_SetNegativeInput(CM_CMP_TypeDef *CMPx, uint16_t u16NegativeInput); + +uint32_t CMP_GetScanInpSrc(CM_CMP_TypeDef *CMPx); +int32_t CMP_ScanTimeConfig(CM_CMP_TypeDef *CMPx, uint16_t u16Stable, uint16_t u16Period); +void CMP_ScanCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); + +void CMP_8BitDAC_Cmd(uint8_t u8Ch, en_functional_state_t enNewState); +void CMP_8BitDAC_AdcRefCmd(uint16_t u16AdcRefSw, en_functional_state_t enNewState); + +void CMP_8BitDAC_WriteData(uint8_t u8Ch, uint16_t u16DACData); + +/** + * @} + */ + +#endif /* LL_CMP_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_CMP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_crc.h b/mcu/lib/inc/hc32_ll_crc.h new file mode 100644 index 0000000..cb43d6d --- /dev/null +++ b/mcu/lib/inc/hc32_ll_crc.h @@ -0,0 +1,203 @@ +/** + ******************************************************************************* + * @file hc32_ll_crc.h + * @brief This file contains all the functions prototypes of the CRC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-06-30 CDT Reconstruct interface function relate to calculate CRC + Modify return type of function CRC_DeInit + 2023-09-30 CDT Modify comment + Delete and modify some of group/function relate to calculate CRC + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_CRC_H__ +#define __HC32_LL_CRC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_CRC + * @{ + */ + +#if (LL_CRC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CRC_Global_Types CRC Global Types + * @{ + */ + +/** + * @brief CRC initialization structure definition + */ +typedef struct { + uint32_t u32Protocol; /*!< Specifies CRC Protocol. + This parameter can be a value of @ref CRC_Protocol_Control_Bit */ + uint32_t u32InitValue; /*!< Specifies initial CRC value. + This parameter can be CRC_INIT_VALUE_DEFAULT @ref CRC_Init_Value_Default */ + uint32_t u32RefIn; /*!< Specifies CRC Retroflexion Input. + This parameter can be a value of @ref CRC_Retroflexion_Input */ + uint32_t u32RefOut; /*!< Specifies CRC Retroflexion Output. + This parameter can be a value of @ref CRC_Retroflexion_Output */ + uint32_t u32XorOut; /*!< Specifies CRC XOR Output. + This parameter can be a value of @ref CRC_XOR_Output */ +} stc_crc_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CRC_Global_Macros CRC Global Macros + * @{ + */ + +/** + * @defgroup CRC_Protocol_Control_Bit CRC Protocol Control Bit + * @{ + */ +#define CRC_CRC16 (0x0UL) +#define CRC_CRC32 (CRC_CR_CR) +/** + * @} + */ + +/** + * @defgroup CRC_DATA_Bit_Width CRC Data Bit Width + * @{ + */ +#define CRC_DATA_WIDTH_8BIT (1U) +#define CRC_DATA_WIDTH_16BIT (2U) +#define CRC_DATA_WIDTH_32BIT (4U) +/** + * @} + */ + +/** + * @defgroup CRC_Init_Value_Default CRC Default Computation Initialization Value + * @{ + */ +#define CRC_INIT_VALUE_DEFAULT (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup CRC_Retroflexion_Input CRC Retroflexion Input + * @{ + */ +#define CRC_REFIN_DISABLE (0x0UL) +#define CRC_REFIN_ENABLE (CRC_CR_REFIN) +/** + * @} + */ + +/** + * @defgroup CRC_Retroflexion_Output CRC Retroflexion Output + * @{ + */ +#define CRC_REFOUT_DISABLE (0x0UL) +#define CRC_REFOUT_ENABLE (CRC_CR_REFOUT) +/** + * @} + */ + +/** + * @defgroup CRC_XOR_Output CRC XOR Output + * @{ + */ +#define CRC_XOROUT_DISABLE (0x0UL) +#define CRC_XOROUT_ENABLE (CRC_CR_XOROUT) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CRC_Global_Functions + * @{ + */ +int32_t CRC_StructInit(stc_crc_init_t *pstcCrcInit); +int32_t CRC_Init(const stc_crc_init_t *pstcCrcInit); +int32_t CRC_DeInit(void); + +en_flag_status_t CRC_GetResultStatus(void); + +uint16_t CRC_CRC16_AccumulateData(uint8_t u8DataWidth, const void *pvData, uint32_t u32Len); +uint16_t CRC_CRC16_Calculate(uint16_t u16InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len); +en_flag_status_t CRC_CRC16_CheckData(uint16_t u16InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len, uint16_t u16ExpectValue); +en_flag_status_t CRC_CRC16_GetCheckResult(uint16_t u16ExpectValue); + +uint32_t CRC_CRC32_AccumulateData(uint8_t u8DataWidth, const void *pvData, uint32_t u32Len); +uint32_t CRC_CRC32_Calculate(uint32_t u32InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len); +en_flag_status_t CRC_CRC32_CheckData(uint32_t u32InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len, uint32_t u32ExpectValue); +en_flag_status_t CRC_CRC32_GetCheckResult(uint32_t u32ExpectValue); + +/** + * @} + */ + +#endif /* LL_CRC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_CRC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_dbgc.h b/mcu/lib/inc/hc32_ll_dbgc.h new file mode 100644 index 0000000..35a2b5c --- /dev/null +++ b/mcu/lib/inc/hc32_ll_dbgc.h @@ -0,0 +1,175 @@ +/** + ******************************************************************************* + * @file hc32_ll_dbgc.h + * @brief This file contains all the functions prototypes of the DBGC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-09-30 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_DBGC_H__ +#define __HC32_LL_DBGC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_DBGC + * @{ + */ + +#if (LL_DBGC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup DBGC_Global_Types DBGC Global Types + * @{ + */ +/** + * @brief DBGC authenticate ID definition + */ +typedef struct { + uint32_t u32AuthID0; /*!< auth ID 0. */ + uint32_t u32AuthID1; /*!< auth ID 1. */ + uint32_t u32AuthID2; /*!< auth ID 2. */ +} stc_dbgc_auth_id_t; +/** + * @} + */ +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DBGC_Global_Macros DBGC Global Macros + * @{ + */ + +/** + * @defgroup DBGC_MCU_Security_Flag DBGC MCU Security Status flag + * @{ + */ +#define DBGC_SECURITY_AUTH_SUCCESS (DBGC_MCUSTAT_AUTHFG) /*!< AUTHID register equal security password */ +#define DBGC_SECURITY_LOCK_LVL1 (DBGC_MCUSTAT_PRTLV1) /*!< Security lock level 1 */ +#define DBGC_SECURITY_LOCK_LVL2 (DBGC_MCUSTAT_PRTLV2) /*!< Security lock level 2 */ +#define DBGC_SECURITY_ALL (DBGC_MCUSTAT_AUTHFG | DBGC_MCUSTAT_PRTLV1 | DBGC_MCUSTAT_PRTLV2) +/** + * @} + */ + +/** + * @defgroup DBGC_Periph_Sel DBGC Periph Selection + * @{ + */ +#define DBGC_PERIPH_SWDT (DBGC_MCUSTPCTL_SWDTSTP) +#define DBGC_PERIPH_WDT (DBGC_MCUSTPCTL_WDTSTP) +#define DBGC_PERIPH_RTC (DBGC_MCUSTPCTL_RTCSTP) +#define DBGC_PERIPH_TMR0_1 (DBGC_MCUSTPCTL_TMR01STP) +#define DBGC_PERIPH_TMR0_2 (DBGC_MCUSTPCTL_TMR02STP) +#define DBGC_PERIPH_TMR4_1 (DBGC_MCUSTPCTL_TMR41STP) +#define DBGC_PERIPH_TMR4_2 (DBGC_MCUSTPCTL_TMR42STP) +#define DBGC_PERIPH_TMR4_3 (DBGC_MCUSTPCTL_TMR43STP) +#define DBGC_PERIPH_TMR6_1 (DBGC_MCUSTPCTL_TM61STP) +#define DBGC_PERIPH_TMR6_2 (DBGC_MCUSTPCTL_TM62STP) +#define DBGC_PERIPH_TMR6_3 (DBGC_MCUSTPCTL_TMR63STP) +#define DBGC_PERIPH_TMRA_1 (DBGC_MCUSTPCTL_TMRA1STP) +#define DBGC_PERIPH_TMRA_2 (DBGC_MCUSTPCTL_TMRA2STP) +#define DBGC_PERIPH_TMRA_3 (DBGC_MCUSTPCTL_TMRA3STP) +#define DBGC_PERIPH_TMRA_4 (DBGC_MCUSTPCTL_TMRA4STP) +#define DBGC_PERIPH_TMRA_5 (DBGC_MCUSTPCTL_TMRA5STP) +#define DBGC_PERIPH_TMRA_6 (DBGC_MCUSTPCTL_TMRA6STP) +/** + * @} + */ + +/** + * @defgroup DBGC_Periph2_Sel DBGC Periph2 Selection + * @{ + */ +/** + * @} + */ + +/** + * @defgroup DBGC_Trace_Mode DBGC trace mode + * @{ + */ +#define DBGC_TRACE_ASYNC (0UL) +#define DBGC_TRACE_SYNC_1BIT (DBGC_MCUTRACECTL_TRACEMODE_0) +#define DBGC_TRACE_SYNC_2BIT (DBGC_MCUTRACECTL_TRACEMODE_1) +#define DBGC_TRACE_SYNC_4BIT (DBGC_MCUTRACECTL_TRACEMODE) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup DBGC_Global_Functions + * @{ + */ +en_flag_status_t DBGC_GetSecurityStatus(uint32_t u32Flag); +int32_t DBGC_FlashErase(uint32_t u32Timeout); +void DBGC_GetAuthID(stc_dbgc_auth_id_t *pstcAuthID); +void DBGC_PeriphCmd(uint32_t u32Periph, en_functional_state_t enNewState); +void DBGC_TraceIoCmd(en_functional_state_t enNewState); +void DBGC_TraceModeConfig(uint32_t u32TraceMode); +/** + * @} + */ + +#endif /* LL_DBGC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_DBGC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_dcu.h b/mcu/lib/inc/hc32_ll_dcu.h new file mode 100644 index 0000000..8eb55aa --- /dev/null +++ b/mcu/lib/inc/hc32_ll_dcu.h @@ -0,0 +1,268 @@ +/** + ******************************************************************************* + * @file hc32_ll_dcu.h + * @brief This file contains all the functions prototypes of the DCU(Data + * Computing Unit) driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Modify macro group comments: DCU_Interrupt_Type + 2023-06-30 CDT Modify macro-definition according to RM:DCU_CTL_COMP_TRG->DCU_CTL_COMPTRG + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_DCU_H__ +#define __HC32_LL_DCU_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_DCU + * @{ + */ + +#if (LL_DCU_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup DCU_Global_Types DCU Global Types + * @{ + */ + +/** + * @brief DCU initialization structure definition + */ +typedef struct { + uint32_t u32Mode; /*!< Specifies DCU operation. + This parameter can be a value of @ref DCU_Mode */ + uint32_t u32DataWidth; /*!< Specifies DCU data width. + This parameter can be a value of @ref DCU_Data_Width */ +} stc_dcu_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DCU_Global_Macros DCU Global Macros + * @{ + */ + +/** + * @defgroup DCU_Data_Width DCU Data Width + * @{ + */ +#define DCU_DATA_WIDTH_8BIT (0UL) /*!< DCU data width: 8 bit */ +#define DCU_DATA_WIDTH_16BIT (DCU_CTL_DATASIZE_0) /*!< DCU data width: 16 bit */ +#define DCU_DATA_WIDTH_32BIT (DCU_CTL_DATASIZE_1) /*!< DCU data width: 32 bit */ +/** + * @} + */ + +/** + * @defgroup DCU_Compare_Trigger_Condition DCU Compare Trigger Condition + * @{ + */ +#define DCU_CMP_TRIG_DATA0 (0UL) /*!< DCU compare triggered by DATA0 */ +#define DCU_CMP_TRIG_DATA0_DATA1_DATA2 (DCU_CTL_COMPTRG) /*!< DCU compare triggered by DATA0 or DATA1 or DATA2 */ +/** + * @} + */ + +/** + * @defgroup DCU_Mode DCU Mode + * @{ + */ +#define DCU_MD_INVD (0UL) /*!< DCU invalid */ +#define DCU_MD_ADD (1UL) /*!< DCU add operation */ +#define DCU_MD_SUB (2UL) /*!< DCU sub operation */ +#define DCU_MD_HW_ADD (3UL) /*!< DCU hardware trigger add */ +#define DCU_MD_HW_SUB (4UL) /*!< DCU hardware trigger sub */ +#define DCU_MD_CMP (5UL) /*!< DCU compare */ +/** + * @} + */ + +/** + * @defgroup DCU_Flag DCU Flag + * @{ + */ +#define DCU_FLAG_CARRY (DCU_FLAG_FLAG_OP) /*!< DCU addition overflow or subtraction underflow flag */ +#define DCU_FLAG_DATA0_LT_DATA2 (DCU_FLAG_FLAG_LS2) /*!< DCU DATA0 < DATA2 flag */ +#define DCU_FLAG_DATA0_EQ_DATA2 (DCU_FLAG_FLAG_EQ2) /*!< DCU DATA0 = DATA2 flag */ +#define DCU_FLAG_DATA0_GT_DATA2 (DCU_FLAG_FLAG_GT2) /*!< DCU DATA0 > DATA2 flag */ +#define DCU_FLAG_DATA0_LT_DATA1 (DCU_FLAG_FLAG_LS1) /*!< DCU DATA0 < DATA1 flag */ +#define DCU_FLAG_DATA0_EQ_DATA1 (DCU_FLAG_FLAG_EQ1) /*!< DCU DATA0 = DATA1 flag */ +#define DCU_FLAG_DATA0_GT_DATA1 (DCU_FLAG_FLAG_GT1) /*!< DCU DATA0 > DATA1 flag */ + +#define DCU_FLAG_ALL (0x0000007FUL) +/** + * @} + */ + +/** + * @defgroup DCU_Category DCU Category + * @{ + */ +#define DCU_CATEGORY_OP (0UL) /*!< DCU operation result(overflow/underflow) */ +#define DCU_CATEGORY_CMP_WIN (1UL) /*!< DCU comparison(window) */ +#define DCU_CATEGORY_CMP_NON_WIN (2UL) /*!< DCU comparison(non-window) */ +/** + * @} + */ + +/** + * @defgroup DCU_Interrupt_Type DCU Interrupt Type + * @{ + */ +/** + * @defgroup DCU_Compare_Interrupt DCU Compare(Non-window) Interrupt + * @note Interrupt type DCU_Compare_Interrupt is valid when only select DCU_CATEGORY_CMP_NON_WIN + * @{ + */ +#define DCU_INT_CMP_DATA0_LT_DATA2 (DCU_INTEVTSEL_SEL_LS2) /*!< DCU DATA0 < DATA2 interrupt */ +#define DCU_INT_CMP_DATA0_EQ_DATA2 (DCU_INTEVTSEL_SEL_EQ2) /*!< DCU DATA0 = DATA2 interrupt */ +#define DCU_INT_CMP_DATA0_GT_DATA2 (DCU_INTEVTSEL_SEL_GT2) /*!< DCU DATA0 > DATA2 interrupt */ +#define DCU_INT_CMP_DATA0_LT_DATA1 (DCU_INTEVTSEL_SEL_LS1) /*!< DCU DATA0 < DATA1 interrupt */ +#define DCU_INT_CMP_DATA0_EQ_DATA1 (DCU_INTEVTSEL_SEL_EQ1) /*!< DCU DATA0 = DATA1 interrupt */ +#define DCU_INT_CMP_DATA0_GT_DATA1 (DCU_INTEVTSEL_SEL_GT1) /*!< DCU DATA0 > DATA1 interrupt */ +#define DCU_INT_CMP_NON_WIN_ALL (DCU_INT_CMP_DATA0_LT_DATA2 | \ + DCU_INT_CMP_DATA0_EQ_DATA2 | \ + DCU_INT_CMP_DATA0_GT_DATA2 | \ + DCU_INT_CMP_DATA0_LT_DATA1 | \ + DCU_INT_CMP_DATA0_EQ_DATA1 | \ + DCU_INT_CMP_DATA0_GT_DATA1) +/** + * @} + */ + +/** + * @defgroup DCU_Window_Compare_Interrupt DCU Window Compare Interrupt + * @note Interrupt type DCU_Window_Compare_Interrupt is valid when only select DCU_CATEGORY_CMP_WIN + * @{ + */ +#define DCU_INT_CMP_WIN_INSIDE (DCU_INTEVTSEL_SEL_WIN_0) /*!< DCU comparison(DATA2 <= DATA0 <= DATA1) interrupt */ +#define DCU_INT_CMP_WIN_OUTSIDE (DCU_INTEVTSEL_SEL_WIN_1) /*!< DCU comparison(DATA0 < DATA2 & DATA0 > DATA1 ) interrupt */ +#define DCU_INT_CMP_WIN_ALL (DCU_INT_CMP_WIN_INSIDE | DCU_INT_CMP_WIN_OUTSIDE) +/** + * @} + */ + +/** + * @defgroup DCU_Operation_Interrupt DCU Operation Interrupt + * @note DCU_Window_Compare_Interrupt selection is valid when only select DCU_CATEGORY_OP + * @{ + */ +#define DCU_INT_OP_CARRY (DCU_INTEVTSEL_SEL_OP) /*!< DCU addition overflow or subtraction underflow interrupt */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup DCU_Data_Register_Index DCU Data Register Index + * @{ + */ +#define DCU_DATA0_IDX (0UL) /*!< DCU DATA0 */ +#define DCU_DATA1_IDX (1UL) /*!< DCU DATA1 */ +#define DCU_DATA2_IDX (2UL) /*!< DCU DATA2 */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup DCU_Global_Functions + * @{ + */ + +/* Initialization and configuration functions */ +int32_t DCU_Init(CM_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcDcuInit); +int32_t DCU_StructInit(stc_dcu_init_t *pstcDcuInit); +int32_t DCU_DeInit(CM_DCU_TypeDef *DCUx); + +void DCU_SetMode(CM_DCU_TypeDef *DCUx, uint32_t u32Mode); +void DCU_SetDataWidth(CM_DCU_TypeDef *DCUx, uint32_t u32DataWidth); +void DCU_SetCompareCond(CM_DCU_TypeDef *DCUx, uint32_t u32Cond); + +/* Interrupt and flag management functions */ +en_flag_status_t DCU_GetStatus(const CM_DCU_TypeDef *DCUx, uint32_t u32Flag); +void DCU_ClearStatus(CM_DCU_TypeDef *DCUx, uint32_t u32Flag); +void DCU_GlobalIntCmd(CM_DCU_TypeDef *DCUx, en_functional_state_t enNewState); +void DCU_IntCmd(CM_DCU_TypeDef *DCUx, uint32_t u32IntCategory, uint32_t u32IntType, en_functional_state_t enNewState); + +/* Read and write functions */ +uint8_t DCU_ReadData8(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex); +void DCU_WriteData8(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint8_t u8Data); +uint16_t DCU_ReadData16(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex); +void DCU_WriteData16(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint16_t u16Data); +uint32_t DCU_ReadData32(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex); +void DCU_WriteData32(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint32_t u32Data); + +/** + * @} + */ + +#endif /* LL_DCU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_DCU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_def.h b/mcu/lib/inc/hc32_ll_def.h new file mode 100644 index 0000000..77220e6 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_def.h @@ -0,0 +1,395 @@ +/** + ******************************************************************************* + * @file hc32_ll_def.h + * @brief This file contains LL common definitions: enumeration, macros and + * structures definitions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-01-15 CDT Implemented the definition of __NO_INIT for AC6 and ARM Compiler + ARM Compiler suppress warning message: diag_1296 + 2023-06-30 CDT Modify typo + Add __NO_OPTIMIZE configuration item + 2023-09-30 CDT Add attribute for __RAM_FUNC definition + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_DEF_H__ +#define __HC32_LL_DEF_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include + +/** + * @addtogroup LL_Common + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup LL_Common_Global_Types LL Common Global Types + * @{ + */ + +/** + * @brief Single precision floating point number (4 byte) + */ +typedef float float32_t; + +/** + * @brief Double precision floating point number (8 byte) + */ +typedef double float64_t; + +/** + * @brief Function pointer type to void/void function + */ +typedef void (*func_ptr_t)(void); + +/** + * @brief Functional state + */ +typedef enum { + DISABLE = 0U, + ENABLE = 1U, +} en_functional_state_t; + +/** + * @brief Flag status + */ +typedef enum { + RESET = 0U, + SET = 1U, +} en_flag_status_t, en_int_status_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup LL_Common_Global_Macros LL Common Global Macros + * @{ + */ + +/** + * @defgroup Compiler_Macros Compiler Macros + * @{ + */ +#ifndef __UNUSED +#define __UNUSED __attribute__((unused)) +#endif /* __UNUSED */ + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#ifndef __WEAKDEF +#define __WEAKDEF __attribute__((weak)) +#endif /* __WEAKDEF */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN __attribute__((aligned(4))) +#endif /* __ALIGN_BEGIN */ +#ifndef __NOINLINE +#define __NOINLINE __attribute__((noinline)) +#endif /* __NOINLINE */ +/* RAM functions are defined using the toolchain options. +Functions that are executed in RAM should reside in a separate source module. +Using the 'Options for File' dialog you can simply change the 'Code / Const' +area of a module to a memory space in physical RAM. */ +#ifndef __RAM_FUNC +#define __RAM_FUNC __attribute__((section("RAMCODE"))) +#endif /* __RAM_FUNC */ +#ifndef __NO_INIT +#define __NO_INIT __attribute__((section(".bss.noinit"))) +#endif /* __NO_INIT */ +#ifndef __NO_OPTIMIZE +#define __NO_OPTIMIZE __attribute__((optnone)) +#endif /* __NO_OPTIMIZE */ +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /*!< GNU Compiler */ +#ifndef __WEAKDEF +#define __WEAKDEF __attribute__((weak)) +#endif /* __WEAKDEF */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN __attribute__((aligned (4))) +#endif /* __ALIGN_BEGIN */ +#ifndef __NOINLINE +#define __NOINLINE __attribute__((noinline)) +#endif /* __NOINLINE */ +#ifndef __RAM_FUNC +#define __RAM_FUNC __attribute__((long_call, section(".ramfunc"))) +/* Usage: __RAM_FUNC void foo(void) */ +#endif /* __RAM_FUNC */ +#ifndef __NO_INIT +#define __NO_INIT __attribute__((section(".noinit"))) +#endif /* __NO_INIT */ +#ifndef __NO_OPTIMIZE +#define __NO_OPTIMIZE __attribute__((optimize("O0"))) +#endif /* __NO_OPTIMIZE */ +#elif defined (__ICCARM__) /*!< IAR Compiler */ +#ifndef __WEAKDEF +#define __WEAKDEF __weak +#endif /* __WEAKDEF */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN _Pragma("data_alignment=4") +#endif /* __ALIGN_BEGIN */ +#ifndef __NOINLINE +#define __NOINLINE _Pragma("optimize = no_inline") +#endif /* __NOINLINE */ +#ifndef __RAM_FUNC +#define __RAM_FUNC __ramfunc +#endif /* __RAM_FUNC */ +#ifndef __NO_INIT +#define __NO_INIT __no_init +#endif /* __NO_INIT */ +#ifndef __NO_OPTIMIZE +#define __NO_OPTIMIZE _Pragma("optimize=none") +#endif /* __NO_OPTIMIZE */ +#elif defined (__CC_ARM) /*!< ARM Compiler */ +#ifndef __WEAKDEF +#define __WEAKDEF __attribute__((weak)) +#endif /* __WEAKDEF */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN __align(4) +#endif /* __ALIGN_BEGIN */ +#ifndef __NOINLINE +#define __NOINLINE __attribute__((noinline)) +#endif /* __NOINLINE */ +#ifndef __NO_INIT +#define __NO_INIT __attribute__((section(".bss.noinit"), zero_init)) +#endif /* __NO_INIT */ +#ifndef __NO_OPTIMIZE +#define __NO_OPTIMIZE +#endif /* __NO_OPTIMIZE */ +/* RAM functions are defined using the toolchain options. +Functions that are executed in RAM should reside in a separate source module. +Using the 'Options for File' dialog you can simply change the 'Code / Const' +area of a module to a memory space in physical RAM. */ +#ifndef __RAM_FUNC +#define __RAM_FUNC __attribute__((section("RAMCODE"))) +#endif /* __RAM_FUNC */ +/* Suppress warning message: extended constant initializer used */ +#pragma diag_suppress 1296 +#else +#error "unsupported compiler!!" +#endif +/** + * @} + */ + +/** + * @defgroup Extend_Macros Extend Macros + * @{ + */ +/* Decimal to BCD */ +#define DEC2BCD(x) ((((x) / 10U) << 4U) + ((x) % 10U)) + +/* BCD to decimal */ +#define BCD2DEC(x) ((((x) >> 4U) * 10U) + ((x) & 0x0FU)) + +/* Returns the dimension of an array */ +#define ARRAY_SZ(x) ((sizeof(x)) / (sizeof((x)[0]))) + +/* Returns the minimum value out of two values */ +#define LL_MIN(x, y) ((x) < (y) ? (x) : (y)) + +/* Returns the maximum value out of two values */ +#define LL_MAX(x, y) ((x) > (y) ? (x) : (y)) +/** + * @} + */ + +/** + * @defgroup Check_Parameters_Validity Check Parameters Validity + * @{ + */ + +/* Check Functional State */ +#define IS_FUNCTIONAL_STATE(state) (((state) == DISABLE) || ((state) == ENABLE)) + +/** + * @defgroup Check_Address_Align_Validity Check Address Align Validity + * @{ + */ +#define IS_ADDR_ALIGN(addr, align) (0UL == (((uint32_t)(addr)) & (((uint32_t)(align)) - 1UL))) +#define IS_ADDR_ALIGN_HALFWORD(addr) (0UL == (((uint32_t)(addr)) & 0x1UL)) +#define IS_ADDR_ALIGN_WORD(addr) (0UL == (((uint32_t)(addr)) & 0x3UL)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup Peripheral_Bit_Band Peripheral Bit Band + * @{ + */ +#define __PERIPH_BIT_BAND_BASE (0x42000000UL) +#define __PERIPH_BASE (0x40000000UL) +#define __REG_OFS(regAddr) ((regAddr) - __PERIPH_BASE) +#define __BIT_BAND_ADDR(regAddr, pos) ((__REG_OFS(regAddr) << 5U) + ((uint32_t)(pos) << 2U) + __PERIPH_BIT_BAND_BASE) +#define PERIPH_BIT_BAND(regAddr, pos) (*(__IO uint32_t *)__BIT_BAND_ADDR((regAddr), (pos))) +/** + * @} + */ + +/** + * @defgroup Generic_Error_Codes Generic Error Codes + * @{ + */ +#define LL_OK (0) /*!< No error */ +#define LL_ERR (-1) /*!< Non-specific error code */ +#define LL_ERR_UNINIT (-2) /*!< Module (or part of it) was not initialized properly */ +#define LL_ERR_INVD_PARAM (-3) /*!< Provided parameter is not valid */ +#define LL_ERR_INVD_MD (-4) /*!< Operation not allowed in current mode */ +#define LL_ERR_NOT_RDY (-5) /*!< A requested final state is not reached */ +#define LL_ERR_BUSY (-6) /*!< A conflicting or requested operation is still in progress */ +#define LL_ERR_ADDR_ALIGN (-7) /*!< Address alignment does not match */ +#define LL_ERR_TIMEOUT (-8) /*!< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) */ +#define LL_ERR_BUF_EMPTY (-9) /*!< Circular buffer can not be read because the buffer is empty */ +#define LL_ERR_BUF_FULL (-10) /*!< Circular buffer can not be written because the buffer is full */ +/** + * @} + */ + +/** + * @defgroup Chip_Module_Switch Chip Module Switch + * @{ + */ +#define DDL_ON (1U) +#define DDL_OFF (0U) +/** + * @} + */ + +/** + * @defgroup Bit_Mask_Macros Bit Mask Macros + * @{ + */ +#define BIT_MASK_00 (1UL << 0U) +#define BIT_MASK_01 (1UL << 1U) +#define BIT_MASK_02 (1UL << 2U) +#define BIT_MASK_03 (1UL << 3U) +#define BIT_MASK_04 (1UL << 4U) +#define BIT_MASK_05 (1UL << 5U) +#define BIT_MASK_06 (1UL << 6U) +#define BIT_MASK_07 (1UL << 7U) +#define BIT_MASK_08 (1UL << 8U) +#define BIT_MASK_09 (1UL << 9U) +#define BIT_MASK_10 (1UL << 10U) +#define BIT_MASK_11 (1UL << 11U) +#define BIT_MASK_12 (1UL << 12U) +#define BIT_MASK_13 (1UL << 13U) +#define BIT_MASK_14 (1UL << 14U) +#define BIT_MASK_15 (1UL << 15U) +#define BIT_MASK_16 (1UL << 16U) +#define BIT_MASK_17 (1UL << 17U) +#define BIT_MASK_18 (1UL << 18U) +#define BIT_MASK_19 (1UL << 19U) +#define BIT_MASK_20 (1UL << 20U) +#define BIT_MASK_21 (1UL << 21U) +#define BIT_MASK_22 (1UL << 22U) +#define BIT_MASK_23 (1UL << 23U) +#define BIT_MASK_24 (1UL << 24U) +#define BIT_MASK_25 (1UL << 25U) +#define BIT_MASK_26 (1UL << 26U) +#define BIT_MASK_27 (1UL << 27U) +#define BIT_MASK_28 (1UL << 28U) +#define BIT_MASK_29 (1UL << 29U) +#define BIT_MASK_30 (1UL << 30U) +#define BIT_MASK_31 (1UL << 31U) +/** + * @} + */ + +/** + * @defgroup Register_Macros Register Macros + * @{ + */ +#define RW_MEM8(addr) (*(volatile uint8_t *)(addr)) +#define RW_MEM16(addr) (*(volatile uint16_t *)(addr)) +#define RW_MEM32(addr) (*(volatile uint32_t *)(addr)) + +#define SET_REG_BIT(REG, BIT) ((REG) |= (BIT)) +#define SET_REG8_BIT(REG, BIT) ((REG) |= ((uint8_t)(BIT))) +#define SET_REG16_BIT(REG, BIT) ((REG) |= ((uint16_t)(BIT))) +#define SET_REG32_BIT(REG, BIT) ((REG) |= ((uint32_t)(BIT))) + +#define CLR_REG_BIT(REG, BIT) ((REG) &= (~(BIT))) +#define CLR_REG8_BIT(REG, BIT) ((REG) &= ((uint8_t)(~((uint8_t)(BIT))))) +#define CLR_REG16_BIT(REG, BIT) ((REG) &= ((uint16_t)(~((uint16_t)(BIT))))) +#define CLR_REG32_BIT(REG, BIT) ((REG) &= ((uint32_t)(~((uint32_t)(BIT))))) + +#define READ_REG_BIT(REG, BIT) ((REG) & (BIT)) +#define READ_REG8_BIT(REG, BIT) ((REG) & ((uint8_t)(BIT))) +#define READ_REG16_BIT(REG, BIT) ((REG) & ((uint16_t)(BIT))) +#define READ_REG32_BIT(REG, BIT) ((REG) & ((uint32_t)(BIT))) + +#define CLR_REG(REG) ((REG) = (0U)) +#define CLR_REG8(REG) ((REG) = ((uint8_t)(0U))) +#define CLR_REG16(REG) ((REG) = ((uint16_t)(0U))) +#define CLR_REG32(REG) ((REG) = ((uint32_t)(0UL))) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) +#define WRITE_REG8(REG, VAL) ((REG) = ((uint8_t)(VAL))) +#define WRITE_REG16(REG, VAL) ((REG) = ((uint16_t)(VAL))) +#define WRITE_REG32(REG, VAL) ((REG) = ((uint32_t)(VAL))) + +#define READ_REG(REG) (REG) +#define READ_REG8(REG) (REG) +#define READ_REG16(REG) (REG) +#define READ_REG32(REG) (REG) + +#define MODIFY_REG(REGS, CLRMASK, SETMASK) (WRITE_REG((REGS), (((READ_REG(REGS)) & (~(CLRMASK))) | ((SETMASK) & (CLRMASK))))) +#define MODIFY_REG8(REGS, CLRMASK, SETMASK) (WRITE_REG8((REGS), (((READ_REG8((REGS))) & ((uint8_t)(~((uint8_t)(CLRMASK))))) | ((uint8_t)(SETMASK) & (uint8_t)(CLRMASK))))) +#define MODIFY_REG16(REGS, CLRMASK, SETMASK) (WRITE_REG16((REGS), (((READ_REG16((REGS))) & ((uint16_t)(~((uint16_t)(CLRMASK))))) | ((uint16_t)(SETMASK) & (uint16_t)(CLRMASK))))) +#define MODIFY_REG32(REGS, CLRMASK, SETMASK) (WRITE_REG32((REGS), (((READ_REG32((REGS))) & ((uint32_t)(~((uint32_t)(CLRMASK))))) | ((uint32_t)(SETMASK) & (uint32_t)(CLRMASK))))) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_DEF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_dma.h b/mcu/lib/inc/hc32_ll_dma.h new file mode 100644 index 0000000..7207441 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_dma.h @@ -0,0 +1,541 @@ +/** + ******************************************************************************* + * @file hc32_ll_dma.h + * @brief This file contains all the functions prototypes of the DMA driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-06-30 CDT Add API DMA_SetDataWidth() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_DMA_H__ +#define __HC32_LL_DMA_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_DMA + * @{ + */ + +#if (LL_DMA_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup DMA_Global_Types DMA Global Types + * @{ + */ + +/** + * @brief DMA basic configuration + */ +typedef struct { + uint32_t u32IntEn; /*!< Specifies the DMA interrupt function. + This parameter can be a value of @ref DMA_Int_Config */ + uint32_t u32SrcAddr; /*!< Specifies the DMA source address. */ + uint32_t u32DestAddr; /*!< Specifies the DMA destination address. */ + uint32_t u32DataWidth; /*!< Specifies the DMA transfer data width. + This parameter can be a value of @ref DMA_DataWidth_Sel */ + uint32_t u32BlockSize; /*!< Specifies the DMA block size. */ + uint32_t u32TransCount; /*!< Specifies the DMA transfer count. */ + uint32_t u32SrcAddrInc; /*!< Specifies the source address increment mode. + This parameter can be a value of @ref DMA_SrcAddr_Incremented_Mode */ + uint32_t u32DestAddrInc; /*!< Specifies the destination address increment mode. + This parameter can be a value of @ref DMA_DesAddr_Incremented_Mode */ +} stc_dma_init_t; + +/** + * @brief DMA repeat mode configuration + */ +typedef struct { + uint32_t u32Mode; /*!< Specifies the DMA source repeat function. + This parameter can be a value of @ref DMA_Repeat_Config */ + uint32_t u32SrcCount; /*!< Specifies the DMA source repeat size. */ + uint32_t u32DestCount; /*!< Specifies the DMA destination repeat size. */ +} stc_dma_repeat_init_t; + +/** + * @brief DMA non-sequence mode configuration + */ +typedef struct { + uint32_t u32Mode; /*!< Specifies the DMA source non-sequence function. + This parameter can be a value of @ref DMA_NonSeq_Config */ + uint32_t u32SrcCount; /*!< Specifies the DMA source non-sequence function count. */ + uint32_t u32SrcOffset; /*!< Specifies the DMA source non-sequence function offset. */ + uint32_t u32DestCount; /*!< Specifies the DMA destination non-sequence function count. */ + uint32_t u32DestOffset; /*!< Specifies the DMA destination non-sequence function offset. */ +} stc_dma_nonseq_init_t; + +/** + * @brief DMA Link List Pointer (LLP) mode configuration + */ +typedef struct { + uint32_t u32State; /*!< Specifies the DMA LLP function. + This parameter can be a value of @ref DMA_Llp_En */ + uint32_t u32Mode; /*!< Specifies the DMA LLP auto or wait REQ. + This parameter can be a value of @ref DMA_Llp_Mode */ + uint32_t u32Addr; /*!< Specifies the DMA list pointer address for LLP function. */ +} stc_dma_llp_init_t; + +/** + * @brief DMA re-config function configuration + */ +typedef struct { + uint32_t u32CountMode; /*!< Specifies the DMA reconfig function count mode. + This parameter can be a value of @ref DMA_Reconfig_Count_Sel */ + uint32_t u32DestAddrMode; /*!< Specifies the DMA reconfig function destination address mode. + This parameter can be a value of @ref DMA_Reconfig_DestAddr_Sel */ + uint32_t u32SrcAddrMode; /*!< Specifies the DMA reconfig function source address mode. + This parameter can be a value of @ref DMA_Reconfig_SrcAddr_Sel */ +} stc_dma_reconfig_init_t; + +/** + * @brief Dma LLP(linked list pointer) descriptor structure definition + */ +typedef struct { + uint32_t SARx; /*!< LLP source address */ + uint32_t DARx; /*!< LLP destination address */ + uint32_t DTCTLx; /*!< LLP transfer count and block size */ + uint32_t RPTx; /*!< LLP source & destination repeat size */ + uint32_t SNSEQCTLx; /*!< LLP source non-seq count and offset */ + uint32_t DNSEQCTLx; /*!< LLP destination non-seq count and offset */ + uint32_t LLPx; /*!< LLP next list pointer */ + uint32_t CHCTLx; /*!< LLP channel control */ +} stc_dma_llp_descriptor_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DMA_Global_Macros DMA Global Macros + * @{ + */ + +/** + * @defgroup DMA_Channel_selection DMA Channel Position selection + * @{ + */ +#define DMA_CH0 (0x00U) /*!< DMA Channel 0 */ +#define DMA_CH1 (0x01U) /*!< DMA Channel 1 */ +#define DMA_CH2 (0x02U) /*!< DMA Channel 2 */ +#define DMA_CH3 (0x03U) /*!< DMA Channel 3 */ + +/** + * @} + */ + +/** + * @defgroup DMA_Mx_Channel_selection DMA Multiplex Channel selection + * @{ + */ +#define DMA_MX_CH0 (0x01UL) /*!< DMA Channel 0 position */ +#define DMA_MX_CH1 (0x02UL) /*!< DMA Channel 1 position */ +#define DMA_MX_CH_ALL (DMA_CHEN_CHEN) /*!< DMA Channel mask position */ +#define DMA_MX_CH2 (0x04UL) /*!< DMA Channel 2 position */ +#define DMA_MX_CH3 (0x08UL) /*!< DMA Channel 3 position */ +/** + * @} + */ + +/** + * @defgroup DMA_Flag_Request_Err_Sel DMA request error flag selection + * @{ + */ +#define DMA_FLAG_REQ_ERR_CH0 (DMA_INTSTAT0_REQERR_0) /*!< DMA request error flag CH.0 */ +#define DMA_FLAG_REQ_ERR_CH1 (DMA_INTSTAT0_REQERR_1) /*!< DMA request error flag CH.1 */ +#define DMA_FLAG_REQ_ERR_CH2 (DMA_INTSTAT0_REQERR_2) /*!< DMA request error flag CH.2 */ +#define DMA_FLAG_REQ_ERR_CH3 (DMA_INTSTAT0_REQERR_3) /*!< DMA request error flag CH.3 */ +/** + * @} + */ + +/** + * @defgroup DMA_Flag_Trans_Err_Sel DMA transfer error flag selection + * @{ + */ +#define DMA_FLAG_TRANS_ERR_CH0 (DMA_INTSTAT0_TRNERR_0) /*!< DMA transfer error flag CH.0 */ +#define DMA_FLAG_TRANS_ERR_CH1 (DMA_INTSTAT0_TRNERR_1) /*!< DMA transfer error flag CH.1 */ +#define DMA_FLAG_TRANS_ERR_CH2 (DMA_INTSTAT0_TRNERR_2) /*!< DMA transfer error flag CH.2 */ +#define DMA_FLAG_TRANS_ERR_CH3 (DMA_INTSTAT0_TRNERR_3) /*!< DMA transfer error flag CH.3 */ +/** + * @} + */ + +/** + * @defgroup DMA_Flag_Btc_Sel DMA block transfer completed flag selection + * @{ + */ +#define DMA_FLAG_BTC_CH0 (DMA_INTSTAT1_BTC_0) /*!< DMA block transfer completed flag CH.0 */ +#define DMA_FLAG_BTC_CH1 (DMA_INTSTAT1_BTC_1) /*!< DMA block transfer completed flag CH.1 */ +#define DMA_FLAG_BTC_CH2 (DMA_INTSTAT1_BTC_2) /*!< DMA block transfer completed flag CH.2 */ +#define DMA_FLAG_BTC_CH3 (DMA_INTSTAT1_BTC_3) /*!< DMA block transfer completed flag CH.3 */ +/** + * @} + */ + +/** + * @defgroup DMA_Flag_Tc_Sel DMA transfer completed flag selection + * @{ + */ +#define DMA_FLAG_TC_CH0 (DMA_INTSTAT1_TC_0) /*!< DMA transfer completed flag CH.0 */ +#define DMA_FLAG_TC_CH1 (DMA_INTSTAT1_TC_1) /*!< DMA transfer completed flag CH.1 */ +#define DMA_FLAG_TC_CH2 (DMA_INTSTAT1_TC_2) /*!< DMA transfer completed flag CH.2 */ +#define DMA_FLAG_TC_CH3 (DMA_INTSTAT1_TC_3) /*!< DMA transfer completed flag CH.3 */ +/** + * @} + */ + +/** + * @defgroup DMA_Int_Request_Err_Sel DMA request error interrupt selection + * @{ + */ +#define DMA_INT_REQ_ERR_CH0 (DMA_INTMASK0_MSKREQERR_0) /*!< DMA request error interrupt CH.0 */ +#define DMA_INT_REQ_ERR_CH1 (DMA_INTMASK0_MSKREQERR_1) /*!< DMA request error interrupt CH.1 */ +#define DMA_INT_REQ_ERR_CH2 (DMA_INTMASK0_MSKREQERR_2) /*!< DMA request error interrupt CH.2 */ +#define DMA_INT_REQ_ERR_CH3 (DMA_INTMASK0_MSKREQERR_3) /*!< DMA request error interrupt CH.3 */ +/** + * @} + */ + +/** + * @defgroup DMA_Int_Trans_Err_Sel DMA transfer error interrupt selection + * @{ + */ +#define DMA_INT_TRANS_ERR_CH0 (DMA_INTMASK0_MSKTRNERR_0) /*!< DMA transfer error interrupt CH.0 */ +#define DMA_INT_TRANS_ERR_CH1 (DMA_INTMASK0_MSKTRNERR_1) /*!< DMA transfer error interrupt CH.1 */ +#define DMA_INT_TRANS_ERR_CH2 (DMA_INTMASK0_MSKTRNERR_2) /*!< DMA transfer error interrupt CH.2 */ +#define DMA_INT_TRANS_ERR_CH3 (DMA_INTMASK0_MSKTRNERR_3) /*!< DMA transfer error interrupt CH.3 */ +/** + * @} + */ + +/** + * @defgroup DMA_Int_Btc_Sel DMA block transfer completed interrupt selection + * @{ + */ +#define DMA_INT_BTC_CH0 (DMA_INTMASK1_MSKBTC_0) /*!< DMA block transfer completed interrupt CH.0 */ +#define DMA_INT_BTC_CH1 (DMA_INTMASK1_MSKBTC_1) /*!< DMA block transfer completed interrupt CH.1 */ +#define DMA_INT_BTC_CH2 (DMA_INTMASK1_MSKBTC_2) /*!< DMA block transfer completed interrupt CH.2 */ +#define DMA_INT_BTC_CH3 (DMA_INTMASK1_MSKBTC_3) /*!< DMA block transfer completed interrupt CH.3 */ +/** + * @} + */ + +/** + * @defgroup DMA_Int_Tc_Sel DMA transfer completed interrupt selection + * @{ + */ +#define DMA_INT_TC_CH0 (DMA_INTMASK1_MSKTC_0) /*!< DMA transfer completed interrupt CH.0 */ +#define DMA_INT_TC_CH1 (DMA_INTMASK1_MSKTC_1) /*!< DMA transfer completed interrupt CH.1 */ +#define DMA_INT_TC_CH2 (DMA_INTMASK1_MSKTC_2) /*!< DMA transfer completed interrupt CH.2 */ +#define DMA_INT_TC_CH3 (DMA_INTMASK1_MSKTC_3) /*!< DMA transfer completed interrupt CH.3 */ +/** + * @} + */ + +/** + * @defgroup DMA_FlagMsk_Sel DMA flag mask selection + * @{ + */ +#define DMA_FLAG_ERR_MASK (DMA_INTSTAT0_TRNERR | DMA_INTSTAT0_REQERR) /*!< DMA error flag mask */ +#define DMA_FLAG_TRANS_MASK (DMA_INTSTAT1_TC | DMA_INTSTAT1_BTC) /*!< DMA transfer flag mask */ +/** + * @} + */ + +/** + * @defgroup DMA_IntMsk_Sel DMA interrupt mask selection + * @{ + */ +#define DMA_INT_ERR_MASK (DMA_INTMASK0_MSKREQERR | DMA_INTMASK0_MSKTRNERR) /*!< DMA error interrupt mask */ +#define DMA_INT_TRANS_MASK (DMA_INTMASK1_MSKTC | DMA_INTMASK1_MSKBTC) /*!< DMA transfer interrupt mask */ +/** + * @} + */ + +/** + * @defgroup DMA_Req_Status_Sel DMA request status + * @{ + */ +#define DMA_STAT_REQ_RECONFIG (DMA_REQSTAT_RCFGREQ) /*!< DMA request from reconfig */ +#define DMA_STAT_REQ_CH0 (DMA_REQSTAT_CHREQ_0) /*!< DMA request from CH.0 */ +#define DMA_STAT_REQ_CH1 (DMA_REQSTAT_CHREQ_1) /*!< DMA request from CH.1 */ +#define DMA_STAT_REQ_CH2 (DMA_REQSTAT_CHREQ_2) /*!< DMA request from CH.2 */ +#define DMA_STAT_REQ_CH3 (DMA_REQSTAT_CHREQ_3) /*!< DMA request from CH.3 */ + +#define DMA_STAT_REQ_MASK (DMA_REQSTAT_CHREQ | DMA_REQSTAT_RCFGREQ) /*!< DMA request mask */ +/** + * @} + */ + +/** + * @defgroup DMA_Trans_Status_Sel DMA transfer status + * @{ + */ +#define DMA_STAT_TRANS_CH0 (DMA_CHSTAT_CHACT_0) /*!< DMA transfer status of CH.0 */ +#define DMA_STAT_TRANS_CH1 (DMA_CHSTAT_CHACT_1) /*!< DMA transfer status of CH.1 */ +#define DMA_STAT_TRANS_CH2 (DMA_CHSTAT_CHACT_2) /*!< DMA transfer status of CH.2 */ +#define DMA_STAT_TRANS_CH3 (DMA_CHSTAT_CHACT_3) /*!< DMA transfer status of CH.3 */ +#define DMA_STAT_TRANS_DMA (DMA_CHSTAT_DMAACT) /*!< DMA transfer status of the DMA */ +#define DMA_STAT_TRANS_RECONFIG (DMA_CHSTAT_RCFGACT) /*!< DMA reconfig status */ + +#define DMA_STAT_TRANS_MASK (DMA_CHSTAT_DMAACT | DMA_CHSTAT_CHACT | DMA_CHSTAT_RCFGACT) +/** + * @} + */ + +/** + * @defgroup DMA_DataWidth_Sel DMA transfer data width + * @{ + */ +#define DMA_DATAWIDTH_8BIT (0x00000000UL) /*!< DMA transfer data width 8bit */ +#define DMA_DATAWIDTH_16BIT (DMA_CHCTL_HSIZE_0) /*!< DMA transfer data width 16bit */ +#define DMA_DATAWIDTH_32BIT (DMA_CHCTL_HSIZE_1) /*!< DMA transfer data width 32bit */ + +/** + * @} + */ + +/** + * @defgroup DMA_Llp_En DMA LLP(linked list pinter) enable or disable + * @{ + */ +#define DMA_LLP_DISABLE (0x00000000UL) /*!< DMA linked list pinter disable */ +#define DMA_LLP_ENABLE (DMA_CHCTL_LLPEN) /*!< DMA linked list pinter enable */ +/** + * @} + */ + +/** + * @defgroup DMA_Llp_Mode DMA linked list pinter mode while transferring complete + * @{ + */ +#define DMA_LLP_WAIT (0x00000000UL) /*!< DMA Llp wait next request while transferring complete */ +#define DMA_LLP_RUN (DMA_CHCTL_LLPRUN) /*!< DMA Llp run right now while transferring complete */ +/** + * @} + */ + +/** + * @defgroup DMA_SrcAddr_Incremented_Mode DMA source address increment mode + * @{ + */ +#define DMA_SRC_ADDR_FIX (0x00000000UL) /*!< DMA source address fix */ +#define DMA_SRC_ADDR_INC (DMA_CHCTL_SINC_0) /*!< DMA source address increment */ +#define DMA_SRC_ADDR_DEC (DMA_CHCTL_SINC_1) /*!< DMA source address decrement */ +/** + * @} + */ + +/** + * @defgroup DMA_DesAddr_Incremented_Mode DMA destination address increment mode + * @{ + */ +#define DMA_DEST_ADDR_FIX (0x00000000UL) /*!< DMA destination address fix */ +#define DMA_DEST_ADDR_INC (DMA_CHCTL_DINC_0) /*!< DMA destination address increment */ +#define DMA_DEST_ADDR_DEC (DMA_CHCTL_DINC_1) /*!< DMA destination address decrement */ +/** + * @} + */ + +/** + * @defgroup DMA_Int_Config DMA interrupt function config + * @{ + */ +#define DMA_INT_ENABLE (DMA_CHCTL_IE) /*!< DMA interrupt enable */ +#define DMA_INT_DISABLE (0x00000000UL) /*!< DMA interrupt disable */ +/** + * @} + */ + +/** + * @defgroup DMA_Repeat_Config DMA repeat mode function config + * @{ + */ +#define DMA_RPT_NONE (0x00000000UL) /*!< DMA repeat disable */ +#define DMA_RPT_SRC (DMA_CHCTL_SRPTEN) /*!< DMA source repeat enable */ +#define DMA_RPT_DEST (DMA_CHCTL_DRPTEN) /*!< DMA destination repeat enable */ +#define DMA_RPT_BOTH (DMA_CHCTL_SRPTEN | DMA_CHCTL_DRPTEN) /*!< DMA source & destination repeat enable */ + +/** + * @} + */ + +/** + * @defgroup DMA_NonSeq_Config DMA non-sequence mode function config + * @{ + */ +#define DMA_NON_SEQ_NONE (0x00000000UL) /*!< DMA non-sequence disable */ +#define DMA_NON_SEQ_SRC (DMA_CHCTL_SNSEQEN) /*!< DMA source non-sequence enable */ +#define DMA_NON_SEQ_DEST (DMA_CHCTL_DNSEQEN) /*!< DMA destination non-sequence enable */ +#define DMA_NON_SEQ_BOTH (DMA_CHCTL_SNSEQEN | DMA_CHCTL_DNSEQEN) /*!< DMA source & destination non-sequence enable */ + +/** + * @} + */ + +/** + * @defgroup DMA_Reconfig_Count_Sel DMA reconfig count mode selection + * @{ + */ +#define DMA_RC_CNT_KEEP (0x00000000UL) /*!< Keep the original counting method */ +#define DMA_RC_CNT_SRC (DMA_RCFGCTL_CNTMD_0) /*!< Use source address counting method */ +#define DMA_RC_CNT_DEST (DMA_RCFGCTL_CNTMD_1) /*!< Use destination address counting method */ +/** + * @} + */ + +/** + * @defgroup DMA_Reconfig_DestAddr_Sel DMA reconfig destination address mode selection + * @{ + */ +#define DMA_RC_DEST_ADDR_KEEP (0x00000000UL) /*!< Destination address Keep the original mode */ +#define DMA_RC_DEST_ADDR_NS (DMA_RCFGCTL_DARMD_0) /*!< Destination address non-sequence */ +#define DMA_RC_DEST_ADDR_RPT (DMA_RCFGCTL_DARMD_1) /*!< Destination address repeat */ +/** + * @} + */ + +/** + * @defgroup DMA_Reconfig_SrcAddr_Sel DMA reconfig source address mode selection + * @{ + */ +#define DMA_RC_SRC_ADDR_KEEP (0x00000000UL) /*!< Source address Keep the original mode */ +#define DMA_RC_SRC_ADDR_NS (DMA_RCFGCTL_SARMD_0) /*!< Source address non-sequence */ +#define DMA_RC_SRC_ADDR_RPT (DMA_RCFGCTL_SARMD_1) /*!< Source address repeat */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup DMA_Global_Functions + * @{ + */ +void DMA_Cmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState); + +void DMA_ErrIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32ErrInt, en_functional_state_t enNewState); +en_flag_status_t DMA_GetErrStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag); +void DMA_ClearErrStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag); + +void DMA_TransCompleteIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32TransCompleteInt, en_functional_state_t enNewState); +en_flag_status_t DMA_GetTransCompleteStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag); +void DMA_ClearTransCompleteStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag); + +int32_t DMA_ChCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState); + +en_flag_status_t DMA_GetRequestStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status); +en_flag_status_t DMA_GetTransStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status); + +int32_t DMA_SetSrcAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr); +int32_t DMA_SetDestAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr); +int32_t DMA_SetTransCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Count); +int32_t DMA_SetBlockSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size); +int32_t DMA_SetDataWidth(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32DataWidth); + +int32_t DMA_SetSrcRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size); +int32_t DMA_SetDestRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size); +int32_t DMA_SetNonSeqSrcCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count); +int32_t DMA_SetNonSeqDestCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count); +int32_t DMA_SetNonSeqSrcOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset); +int32_t DMA_SetNonSeqDestOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset); + +void DMA_SetLlpAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr); + +int32_t DMA_StructInit(stc_dma_init_t *pstcDmaInit); +int32_t DMA_Init(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_init_t *pstcDmaInit); +void DMA_DeInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch); + +int32_t DMA_RepeatStructInit(stc_dma_repeat_init_t *pstcDmaRepeatInit); +int32_t DMA_RepeatInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_repeat_init_t *pstcDmaRepeatInit); + +int32_t DMA_NonSeqStructInit(stc_dma_nonseq_init_t *pstcDmaNonSeqInit); +int32_t DMA_NonSeqInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_nonseq_init_t *pstcDmaNonSeqInit); + +int32_t DMA_LlpStructInit(stc_dma_llp_init_t *pstcDmaLlpInit); +int32_t DMA_LlpInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_llp_init_t *pstcDmaLlpInit); + +void DMA_LlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState); + +int32_t DMA_ReconfigStructInit(stc_dma_reconfig_init_t *pstcDmaRCInit); +int32_t DMA_ReconfigInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_reconfig_init_t *pstcDmaRCInit); +void DMA_ReconfigCmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState); +void DMA_ReconfigLlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState); + +uint32_t DMA_GetSrcAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetDestAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetTransCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetBlockSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetSrcRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetDestRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetNonSeqSrcCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetNonSeqDestCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetNonSeqSrcOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetNonSeqDestOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); + +/** + * @} + */ + +#endif /* LL_DMA_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_DMA_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_efm.h b/mcu/lib/inc/hc32_ll_efm.h new file mode 100644 index 0000000..1baf179 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_efm.h @@ -0,0 +1,487 @@ +/** + ******************************************************************************* + * @file hc32_ll_efm.h + * @brief This file contains all the functions prototypes of the EFM driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-10-31 CDT Add Flash protect level define + 2023-01-15 CDT Code refine + 2023-09-30 CDT Add FLASH security addr define + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_EFM_H__ +#define __HC32_LL_EFM_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_EFM + * @{ + */ + +#if (LL_EFM_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EFM_Global_Types EFM Global Types + * @{ + */ +/** + * @brief EFM unique ID definition + */ +typedef struct { + uint32_t u32UniqueID0; /*!< unique ID 0. */ + uint32_t u32UniqueID1; /*!< unique ID 1. */ + uint32_t u32UniqueID2; /*!< unique ID 2. */ +} stc_efm_unique_id_t; + +typedef struct { + uint32_t u32State; + uint32_t u32Addr; + uint32_t u32Size; +} stc_efm_remap_init_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EFM_Global_Macros EFM Global Macros + * @{ + */ +/** + * @defgroup EFM_Address EFM Address Area + * @{ + */ +#define EFM_START_ADDR (0x00000000UL) /*!< Flash start address */ + +#define EFM_END_ADDR (0x0007FFFFUL) /*!< Flash end address */ +#define EFM_OTP_START_ADDR (0x03000C00UL) /*!< OTP start address */ +#define EFM_OTP_END_ADDR (0x03000FFBUL) /*!< OTP end address */ +#define EFM_OTP_LOCK_ADDR_START (0x03000FC0UL) /*!< OTP lock start address */ +#define EFM_OTP_LOCK_ADDR_END (0x03000FFCUL) /*!< OTP lock end address */ +#define EFM_SECURITY_START_ADDR (0x0317FFE0UL) /*!< Flash security start address */ +#define EFM_SECURITY_END_ADDR (0x0317FFFFUL) /*!< Flash security end address */ + +/** + * @} + */ + +/** + * @defgroup EFM_Chip_Sel EFM Chip Selection + * @{ + */ +#define EFM_CHIP_ALL (EFM_FSTP_FSTP) +/** + * @} + */ + +/** + * @defgroup EFM_Bus_Status EFM Bus Status + * @{ + */ +#define EFM_BUS_HOLD (0x0UL) /*!< Bus busy while flash program or erase */ +#define EFM_BUS_RELEASE (0x1UL) /*!< Bus release while flash program or erase */ +/** + * @} + */ + +/** + * @defgroup EFM_Wait_Cycle EFM Wait Cycle + * @{ + */ + +#define EFM_WAIT_CYCLE0 (0U << EFM_FRMC_FLWT_POS) /*!< Don't insert read wait cycle */ +#define EFM_WAIT_CYCLE1 (1U << EFM_FRMC_FLWT_POS) /*!< Insert 1 read wait cycle */ + +#define EFM_WAIT_CYCLE2 (2U << EFM_FRMC_FLWT_POS) /*!< Insert 2 read wait cycles */ +#define EFM_WAIT_CYCLE3 (3U << EFM_FRMC_FLWT_POS) /*!< Insert 3 read wait cycles */ +#define EFM_WAIT_CYCLE4 (4U << EFM_FRMC_FLWT_POS) /*!< Insert 4 read wait cycles */ +#define EFM_WAIT_CYCLE5 (5U << EFM_FRMC_FLWT_POS) /*!< Insert 5 read wait cycles */ +#define EFM_WAIT_CYCLE6 (6U << EFM_FRMC_FLWT_POS) /*!< Insert 6 read wait cycles */ +#define EFM_WAIT_CYCLE7 (7U << EFM_FRMC_FLWT_POS) /*!< Insert 7 read wait cycles */ +#define EFM_WAIT_CYCLE8 (8U << EFM_FRMC_FLWT_POS) /*!< Insert 8 read wait cycles */ +#define EFM_WAIT_CYCLE9 (9U << EFM_FRMC_FLWT_POS) /*!< Insert 9 read wait cycles */ +#define EFM_WAIT_CYCLE10 (10U << EFM_FRMC_FLWT_POS) /*!< Insert 10 read wait cycles */ +#define EFM_WAIT_CYCLE11 (11U << EFM_FRMC_FLWT_POS) /*!< Insert 11 read wait cycles */ +#define EFM_WAIT_CYCLE12 (12U << EFM_FRMC_FLWT_POS) /*!< Insert 12 read wait cycles */ +#define EFM_WAIT_CYCLE13 (13U << EFM_FRMC_FLWT_POS) /*!< Insert 13 read wait cycles */ +#define EFM_WAIT_CYCLE14 (14U << EFM_FRMC_FLWT_POS) /*!< Insert 14 read wait cycles */ +#define EFM_WAIT_CYCLE15 (15U << EFM_FRMC_FLWT_POS) /*!< Insert 15 read wait cycles */ +/** + * @} + */ + +/** + * @defgroup EFM_Swap_Address EFM Swap Address + * @{ + */ +#define EFM_SWAP_ADDR (0x0007FFDCUL) +#define EFM_SWAP_DATA (0xFFFF4321UL) +/** + * @} + */ + +/** + * @defgroup EFM_OperateMode_Sel EFM Operate Mode Selection + * @{ + */ +#define EFM_MD_READONLY (0x0UL << EFM_FWMC_PEMOD_POS) /*!< Read only mode */ +#define EFM_MD_PGM_SINGLE (0x1UL << EFM_FWMC_PEMOD_POS) /*!< Program single mode */ +#define EFM_MD_PGM_READBACK (0x2UL << EFM_FWMC_PEMOD_POS) /*!< Program and read back mode */ +#define EFM_MD_PGM_SEQ (0x3UL << EFM_FWMC_PEMOD_POS) /*!< Program sequence mode */ +#define EFM_MD_ERASE_SECTOR (0x4UL << EFM_FWMC_PEMOD_POS) /*!< Sector erase mode */ + +#define EFM_MD_ERASE_ALL_CHIP (0x5UL << EFM_FWMC_PEMOD_POS) /*!< Chip erase mode */ +/** + * @} + */ + +/** + * @defgroup EFM_Flag_Sel EFM Flag Selection + * @{ + */ +#define EFM_FLAG_PEWERR (EFM_FSR_PEWERR) /*!< EFM Programming/erase error flag. */ +#define EFM_FLAG_PGMISMTCH (EFM_FSR_PGMISMTCH) /*!< EFM Programming missing match error flag */ +#define EFM_FLAG_OPTEND (EFM_FSR_OPTEND) /*!< EFM End of operation flag. */ +#define EFM_FLAG_COLERR (EFM_FSR_COLERR) /*!< EFM Read collide error flag. */ +#define EFM_FLAG_PEPRTERR (EFM_FSR_PEPRTERR) /*!< EFM write protect address error flag */ +#define EFM_FLAG_RDY (EFM_FSR_RDY) /*!< EFM ready flag. */ +#define EFM_FLAG_PGSZERR (EFM_FSR_PGSZERR) /*!< EFM Programming/erase protect area error flag. */ + +#define EFM_FLAG_ALL (EFM_FLAG_PEWERR | EFM_FLAG_PGMISMTCH | EFM_FLAG_OPTEND | EFM_FLAG_PEPRTERR | \ + EFM_FLAG_COLERR | EFM_FLAG_PGSZERR | EFM_FLAG_RDY) + +/** + * @} + */ + +/** + * @defgroup EFM_Interrupt_Sel EFM Interrupt Selection + * @{ + */ +#define EFM_INT_PEERR (EFM_FITE_PEERRITE) /*!< Program/erase error Interrupt source */ +#define EFM_INT_OPTEND (EFM_FITE_OPTENDITE) /*!< End of EFM operation Interrupt source */ +#define EFM_INT_COLERR (EFM_FITE_COLERRITE) /*!< Read collide error Interrupt source */ + +#define EFM_INT_ALL (EFM_FITE_PEERRITE | EFM_FITE_OPTENDITE | EFM_FITE_COLERRITE) +/** + * @} + */ + +/** + * @defgroup EFM_Keys EFM Keys + * @{ + */ +#define EFM_REG_UNLOCK_KEY1 (0x0123UL) +#define EFM_REG_UNLOCK_KEY2 (0x3210UL) +#define EFM_REG_LOCK_KEY (0x0000UL) +/** + * @} + */ + +/** + * @defgroup EFM_Sector_Size EFM Sector Size + * @{ + */ +#define SECTOR_SIZE (0x2000UL) +#define EFM_SECTOR_SIZE (0x2000UL) +/** + * @} + */ + +/** + * @defgroup EFM_Sector_Address EFM Sector Address + * @{ + */ +#define EFM_SECTOR_ADDR(x) (uint32_t)(SECTOR_SIZE * (x)) +/** + * @} + */ + +/** + * @defgroup EFM_OTP_Base_Address EFM Otp Base Address + * @{ + */ +#define EFM_OTP_BASE1_ADDR (0x03000C00UL) +#define EFM_OTP_BASE1_SIZE (0x40UL) +#define EFM_OTP_BASE1_OFFSET (0UL) +#define EFM_OTP_LOCK_ADDR (0x03000FC0UL) + +/** + * @} + */ + +/** + * @defgroup EFM_OTP_Address EFM Otp Address + * @{ + */ +#define EFM_OTP_BLOCK0 (EFM_OTP_BASE1_ADDR + ((0UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK1 (EFM_OTP_BASE1_ADDR + ((1UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK2 (EFM_OTP_BASE1_ADDR + ((2UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK3 (EFM_OTP_BASE1_ADDR + ((3UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK4 (EFM_OTP_BASE1_ADDR + ((4UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK5 (EFM_OTP_BASE1_ADDR + ((5UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK6 (EFM_OTP_BASE1_ADDR + ((6UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK7 (EFM_OTP_BASE1_ADDR + ((7UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK8 (EFM_OTP_BASE1_ADDR + ((8UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK9 (EFM_OTP_BASE1_ADDR + ((9UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK10 (EFM_OTP_BASE1_ADDR + ((10UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK11 (EFM_OTP_BASE1_ADDR + ((11UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK12 (EFM_OTP_BASE1_ADDR + ((12UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK13 (EFM_OTP_BASE1_ADDR + ((13UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK14 (EFM_OTP_BASE1_ADDR + ((14UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) + +/** + * @} + */ + +/** + * @defgroup EFM_OTP_Lock_Address EFM Otp Lock_address + * @note x at range of 0~14 + * @{ + */ +#define EFM_OTP_BLOCK_LOCKADDR(x) (EFM_OTP_LOCK_ADDR + 0x04UL * (x)) /*!< OTP block x lock address */ +/** + * @} + */ + +#define EFM_REMAP_REG_LOCK_KEY (0x0000UL) +#define EFM_REMAP_REG_UNLOCK_KEY1 (0x0123UL) +#define EFM_REMAP_REG_UNLOCK_KEY2 (0x3210UL) + +/** + * @defgroup EFM_Remap_State EFM remap function state + * @{ + */ +#define EFM_REMAP_OFF (0UL) +#define EFM_REMAP_ON (EFM_MMF_REMCR_EN) +/** + * @} + */ + +/** + * @defgroup EFM_Remap_Size EFM remap size definition + * @note refer to chip user manual for details size spec. + * @{ + */ +#define EFM_REMAP_4K (12UL) +#define EFM_REMAP_8K (13UL) +#define EFM_REMAP_16K (14UL) +#define EFM_REMAP_32K (15UL) +#define EFM_REMAP_64K (16UL) +#define EFM_REMAP_128K (17UL) +#define EFM_REMAP_256K (18UL) +#define EFM_REMAP_512K (19UL) +/** + * @} + */ + +/** + * @defgroup EFM_Remap_Index EFM remap index + * @{ + */ +#define EFM_REMAP_IDX0 (0U) +#define EFM_REMAP_IDX1 (1U) +/** + * @} + */ + +/** + * @defgroup EFM_Remap_BaseAddr EFM remap base address + * @{ + */ +#define EFM_REMAP_BASE_ADDR0 (0x2000000UL) +#define EFM_REMAP_BASE_ADDR1 (0x2080000UL) +/** + * @} + */ + +/** + * @defgroup EFM_Remap_Region EFM remap ROM/RAM region + * @{ + */ +#define EFM_REMAP_ROM_END_ADDR EFM_END_ADDR + +#define EFM_REMAP_RAM_START_ADDR (0x1FFF8000UL) +#define EFM_REMAP_RAM_END_ADDR (0x1FFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup EFM_Protect_Level EFM protect level + * @{ + */ +#define EFM_PROTECT_LEVEL1 (1U) +#define EFM_PROTECT_LEVEL2 (2U) +/** + * @} + */ + +/** + * @defgroup EFM_MCU_Status EFM protect level + * @{ + */ +#define EFM_MCU_PROTECT1_FREE (0U) +#define EFM_MCU_PROTECT1_LOCK (1U) +#define EFM_MCU_PROTECT1_UNLOCK (2U) +#define EFM_MCU_PROTECT2_LOCK (4U) +/** + * @} + */ + +/** + * @} + */ +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EFM_Global_Functions + * @{ + */ + +/** + * @brief EFM Protect Unlock. + * @param None + * @retval None + */ + +__STATIC_INLINE void EFM_REG_Unlock(void) +{ + WRITE_REG32(CM_EFM->FAPRT, EFM_REG_UNLOCK_KEY1); + WRITE_REG32(CM_EFM->FAPRT, EFM_REG_UNLOCK_KEY2); +} + +/** + * @brief EFM Protect Lock. + * @param None + * @retval None + */ +__STATIC_INLINE void EFM_REG_Lock(void) +{ + WRITE_REG32(CM_EFM->FAPRT, EFM_REG_LOCK_KEY); +} + +/** + * @brief EFM remap Unlock. + * @param None + * @retval None + */ +__STATIC_INLINE void EFM_REMAP_Unlock(void) +{ + WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_UNLOCK_KEY1); + WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_UNLOCK_KEY2); +} + +/** + * @brief EFM remap Lock. + * @param None + * @retval None + */ +__STATIC_INLINE void EFM_REMAP_Lock(void) +{ + WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_LOCK_KEY); +} + +void EFM_Cmd(uint32_t u32Flash, en_functional_state_t enNewState); +void EFM_FWMC_Cmd(en_functional_state_t enNewState); +void EFM_SetBusStatus(uint32_t u32Status); +void EFM_IntCmd(uint32_t u32EfmInt, en_functional_state_t enNewState); +void EFM_ClearStatus(uint32_t u32Flag); +int32_t EFM_SetWaitCycle(uint32_t u32WaitCycle); +int32_t EFM_SetOperateMode(uint32_t u32Mode); +int32_t EFM_ReadByte(uint32_t u32Addr, uint8_t *pu8ReadBuf, uint32_t u32ByteLen); +int32_t EFM_Program(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len); +int32_t EFM_ProgramWord(uint32_t u32Addr, uint32_t u32Data); +int32_t EFM_ProgramWordReadBack(uint32_t u32Addr, uint32_t u32Data); +int32_t EFM_SequenceProgram(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len); +int32_t EFM_SectorErase(uint32_t u32Addr); +int32_t EFM_ChipErase(uint8_t u8Chip); + +en_flag_status_t EFM_GetAnyStatus(uint32_t u32Flag); +en_flag_status_t EFM_GetStatus(uint32_t u32Flag); +void EFM_GetUID(stc_efm_unique_id_t *pstcUID); + +void EFM_DataCacheResetCmd(en_functional_state_t enNewState); +void EFM_CacheCmd(en_functional_state_t enNewState); + +void EFM_LowVoltageReadCmd(en_functional_state_t enNewState); +int32_t EFM_SwapCmd(en_functional_state_t enNewState); +en_flag_status_t EFM_GetSwapStatus(void); +int32_t EFM_OTP_Lock(uint32_t u32Addr); + +int32_t EFM_REMAP_StructInit(stc_efm_remap_init_t *pstcEfmRemapInit); +int32_t EFM_REMAP_Init(uint8_t u8RemapIdx, stc_efm_remap_init_t *pstcEfmRemapInit); +void EFM_REMAP_DeInit(void); +void EFM_REMAP_Cmd(uint8_t u8RemapIdx, en_functional_state_t enNewState); +void EFM_REMAP_SetAddr(uint8_t u8RemapIdx, uint32_t u32Addr); +void EFM_REMAP_SetSize(uint8_t u8RemapIdx, uint32_t u32Size); + +void EFM_LowVoltageCmd(en_functional_state_t enNewState); + +void EFM_SetWindowProtectAddr(uint32_t u32StartAddr, uint32_t u32EndAddr); + +void EFM_Protect_Enable(uint8_t u8Level); +int32_t EFM_WriteSecurityCode(uint8_t *pu8Buf, uint32_t u32Len); + +/** + * @} + */ + +#endif /* LL_EFM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_EFM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_emb.h b/mcu/lib/inc/hc32_ll_emb.h new file mode 100644 index 0000000..2049f11 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_emb.h @@ -0,0 +1,394 @@ +/** + ******************************************************************************* + * @file hc32_ll_emb.h + * @brief This file contains all the functions prototypes of the EMB + * (Emergency Brake) driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Modify structure comments:stc_emb_monitor_tmr_pwm_t + 2023-09-30 CDT Update EMB_CTL_CMPEN0~2 to EMB_CTL_CMPEN1~3 + Update EMB_INTEN_PORTINTEN to EMB_INTEN_PORTININTEN + Update EMB_INTEN_PWMINTEN to EMB_INTEN_PWMSINTEN + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_EMB_H__ +#define __HC32_LL_EMB_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_EMB + * @{ + */ + +#if (LL_EMB_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EMB_Global_Types EMB Global Types + * @{ + */ + +/** + * @brief EMB monitor OSC failure configuration + */ +typedef struct { + uint32_t u32OscState; /*!< Enable or disable EMB detect OSC failure function + This parameter can be a value of @ref EMB_OSC_Selection */ +} stc_emb_monitor_osc_t; + +/** + * @brief EMB monitor EMB port configuration + */ +typedef struct { + uint32_t u32PortState; /*!< Enable or disable EMB detect port in control function + This parameter can be a value of @ref EMB_Port_Selection */ + uint32_t u32PortLevel; /*!< EMB detect port level + This parameter can be a value of @ref EMB_Detect_Port_Level */ + uint32_t u32PortFilterDiv; /*!< EMB port filter division + This parameter can be a value of @ref EMB_Port_Filter_Clock_Division */ + uint32_t u32PortFilterState; /*!< EMB port filter division + This parameter can be a value of @ref EMB_Port_Filter_Selection */ +} stc_emb_monitor_port_config_t; + +/** + * @brief EMB monitor PWM configuration + */ +typedef struct { + uint32_t u32PwmState; /*!< Enable or disable EMB detect timer same phase function + This parameter can be a value of @ref EMB_Detect_PWM state. */ + uint32_t u32PwmLevel; /*!< Detect timer polarity level + This parameter can be a value of @ref EMB_Detect_PWM level */ +} stc_emb_monitor_tmr_pwm_t; + +/** + * @brief EMB monitor port in configuration + */ +typedef struct { + stc_emb_monitor_port_config_t stcPort1; /*!< EMB detect EMB port in function + This parameter details refer @ref stc_emb_monitor_port_config_t structure */ +} stc_emb_monitor_port_t; + +/** + * @brief EMB monitor CMP configuration + */ +typedef struct { + uint32_t u32Cmp1State; /*!< Enable or disable EMB detect CMP1 result function + This parameter can be a value of @ref EMB_CMP_Selection */ + uint32_t u32Cmp2State; /*!< Enable or disable EMB detect CMP2 result function + This parameter can be a value of @ref EMB_CMP_Selection */ + uint32_t u32Cmp3State; /*!< Enable or disable EMB detect CMP3 result function + This parameter can be a value of @ref EMB_CMP_Selection */ +} stc_emb_monitor_cmp_t; + +/** + * @brief EMB monitor TMR4 configuration + */ +typedef struct { + stc_emb_monitor_tmr_pwm_t stcTmr4PwmU; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr4PwmV; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr4PwmW; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ +} stc_emb_monitor_tmr4_t; + +/** + * @brief EMB monitor TMR6 configuration + */ +typedef struct { + stc_emb_monitor_tmr_pwm_t stcTmr6_1; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr6_2; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr6_3; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ +} stc_emb_monitor_tmr6_t; + +/** + * @brief EMB control TMR4 initialization configuration + */ +typedef struct { + stc_emb_monitor_cmp_t stcCmp; /*!< EMB detect CMP function + This parameter details refer @ref stc_emb_monitor_cmp_t structure */ + stc_emb_monitor_osc_t stcOsc; /*!< EMB detect OSC function + This parameter details refer @ref stc_emb_monitor_osc_t structure */ + stc_emb_monitor_port_t stcPort; /*!< EMB detect EMB port function + This parameter details refer @ref stc_emb_monitor_port_t structure */ + stc_emb_monitor_tmr4_t stcTmr4; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr4_t structure */ +} stc_emb_tmr4_init_t; + +/** + * @brief EMB control TMR6 initialization configuration + */ +typedef struct { + stc_emb_monitor_cmp_t stcCmp; /*!< EMB detect CMP function + This parameter details refer @ref stc_emb_monitor_cmp_t structure */ + stc_emb_monitor_osc_t stcOsc; /*!< EMB detect OSC function + This parameter details refer @ref stc_emb_monitor_osc_t structure */ + stc_emb_monitor_port_t stcPort; /*!< EMB detect EMB port function + This parameter details refer @ref stc_emb_monitor_port_t structure */ + stc_emb_monitor_tmr6_t stcTmr6; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr6_t structure */ +} stc_emb_tmr6_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EMB_Global_Macros EMB Global Macros + * @{ + */ + +/** + * @defgroup EMB_CMP_Selection EMB CMP Selection + * @{ + */ +#define EMB_CMP1_DISABLE (0UL) +#define EMB_CMP2_DISABLE (0UL) +#define EMB_CMP3_DISABLE (0UL) + +#define EMB_CMP1_ENABLE (EMB_CTL_CMPEN1) +#define EMB_CMP2_ENABLE (EMB_CTL_CMPEN2) +#define EMB_CMP3_ENABLE (EMB_CTL_CMPEN3) +/** + * @} + */ + +/** + * @defgroup EMB_OSC_Selection EMB OSC Selection + * @{ + */ +#define EMB_OSC_DISABLE (0UL) +#define EMB_OSC_ENABLE (EMB_CTL_OSCSTPEN) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_PWM EMB Detect PWM + * @{ + */ +/** + * @defgroup EMB_TMR4_PWM_Selection EMB TMR4 PWM Selection + * @{ + */ +#define EMB_TMR4_PWM_W_DISABLE (0UL) +#define EMB_TMR4_PWM_V_DISABLE (0UL) +#define EMB_TMR4_PWM_U_DISABLE (0UL) + +#define EMB_TMR4_PWM_W_ENABLE (EMB_CTL_PWMSEN0) +#define EMB_TMR4_PWM_V_ENABLE (EMB_CTL_PWMSEN1) +#define EMB_TMR4_PWM_U_ENABLE (EMB_CTL_PWMSEN2) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_TMR4_PWM_Level EMB Detect TMR4 PWM Level + * @{ + */ +#define EMB_DETECT_TMR4_PWM_W_BOTH_LOW (0UL) +#define EMB_DETECT_TMR4_PWM_V_BOTH_LOW (0UL) +#define EMB_DETECT_TMR4_PWM_U_BOTH_LOW (0UL) + +#define EMB_DETECT_TMR4_PWM_W_BOTH_HIGH (EMB_PWMLV_PWMLV0) +#define EMB_DETECT_TMR4_PWM_V_BOTH_HIGH (EMB_PWMLV_PWMLV1) +#define EMB_DETECT_TMR4_PWM_U_BOTH_HIGH (EMB_PWMLV_PWMLV2) +/** + * @} + */ + +/** + * @defgroup EMB_TMR6_PWM_Selection EMB TMR6 PWM Selection + * @{ + */ +#define EMB_TMR6_1_PWM_DISABLE (0UL) +#define EMB_TMR6_2_PWM_DISABLE (0UL) +#define EMB_TMR6_3_PWM_DISABLE (0UL) + +#define EMB_TMR6_1_PWM_ENABLE (EMB_CTL_PWMSEN0) +#define EMB_TMR6_2_PWM_ENABLE (EMB_CTL_PWMSEN1) +#define EMB_TMR6_3_PWM_ENABLE (EMB_CTL_PWMSEN2) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_TMR6_PWM_Level EMB Detect TMR6 PWM Level + * @{ + */ +#define EMB_DETECT_TMR6_1_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_2_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_3_PWM_BOTH_LOW (0UL) + +#define EMB_DETECT_TMR6_1_PWM_BOTH_HIGH (EMB_PWMLV_PWMLV0) +#define EMB_DETECT_TMR6_2_PWM_BOTH_HIGH (EMB_PWMLV_PWMLV1) +#define EMB_DETECT_TMR6_3_PWM_BOTH_HIGH (EMB_PWMLV_PWMLV2) +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup EMB_Port_Selection EMB Port Selection + * @{ + */ +#define EMB_PORT1_DISABLE (0UL) + +#define EMB_PORT1_ENABLE (EMB_CTL_PORTINEN) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_Port_Level EMB Detect Port Level + * @{ + */ +#define EMB_PORT1_DETECT_LVL_HIGH (0UL) + +#define EMB_PORT1_DETECT_LVL_LOW (EMB_CTL_INVSEL) +/** + * @} + */ + +/** + * @defgroup EMB_Port_Filter_Selection EMB Port Filter Selection + * @{ + */ +#define EMB_PORT1_FILTER_DISABLE (0UL) + +#define EMB_PORT1_FILTER_ENABLE (EMB_CTL_NFEN) +/** + * @} + */ + +/** + * @defgroup EMB_Port_Filter_Clock_Division EMB Port Filter Clock Division + * @{ + */ +#define EMB_PORT1_FILTER_CLK_DIV1 (0UL << EMB_CTL_NFSEL_POS) +#define EMB_PORT1_FILTER_CLK_DIV8 (1UL << EMB_CTL_NFSEL_POS) +#define EMB_PORT1_FILTER_CLK_DIV32 (2UL << EMB_CTL_NFSEL_POS) +#define EMB_PORT1_FILTER_CLK_DIV128 (3UL << EMB_CTL_NFSEL_POS) +/** + * @} + */ + +/** + * @defgroup EMB_Flag_State EMB Flag State + * @{ + */ +#define EMB_FLAG_PWMS (EMB_STAT_PWMSF) +#define EMB_FLAG_CMP (EMB_STAT_CMPF) +#define EMB_FLAG_OSC (EMB_STAT_OSF) +#define EMB_FLAG_PORT1 (EMB_STAT_PORTINF) +#define EMB_STAT_PWMS (EMB_STAT_PWMST) +#define EMB_STAT_PORT1 (EMB_STAT_PORTINST) +#define EMB_FLAG_ALL (EMB_FLAG_PWMS | EMB_FLAG_CMP | EMB_FLAG_OSC | EMB_FLAG_PORT1 | \ + EMB_STAT_PWMS | EMB_STAT_PORT1) +/** + * @} + */ + +/** + * @defgroup EMB_Interrupt EMB Interrupt + * @{ + */ +#define EMB_INT_PWMS (EMB_INTEN_PWMSINTEN) +#define EMB_INT_CMP (EMB_INTEN_CMPINTEN) +#define EMB_INT_OSC (EMB_INTEN_OSINTEN) +#define EMB_INT_PORT1 (EMB_INTEN_PORTININTEN) +#define EMB_INT_ALL (EMB_INT_PWMS | EMB_INT_CMP | EMB_INT_OSC | EMB_INT_PORT1) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EMB_Global_Functions + * @{ + */ +int32_t EMB_TMR4_StructInit(stc_emb_tmr4_init_t *pstcEmbInit); +int32_t EMB_TMR4_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr4_init_t *pstcEmbInit); + +int32_t EMB_TMR6_StructInit(stc_emb_tmr6_init_t *pstcEmbInit); +int32_t EMB_TMR6_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr6_init_t *pstcEmbInit); + +void EMB_DeInit(CM_EMB_TypeDef *EMBx); +void EMB_IntCmd(CM_EMB_TypeDef *EMBx, uint32_t u32IntType, en_functional_state_t enNewState); +void EMB_ClearStatus(CM_EMB_TypeDef *EMBx, uint32_t u32Flag); +en_flag_status_t EMB_GetStatus(const CM_EMB_TypeDef *EMBx, uint32_t u32Flag); +void EMB_SWBrake(CM_EMB_TypeDef *EMBx, en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_EMB_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_EMB_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_event_port.h b/mcu/lib/inc/hc32_ll_event_port.h new file mode 100644 index 0000000..eb59e8a --- /dev/null +++ b/mcu/lib/inc/hc32_ll_event_port.h @@ -0,0 +1,233 @@ +/** + ******************************************************************************* + * @file hc32_ll_event_port.h + * @brief This file contains all the functions prototypes of the Event Port + * driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_EVENT_PORT_H__ +#define __HC32_LL_EVENT_PORT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_EVENT_PORT + * @{ + */ + +#if (LL_EVENT_PORT_ENABLE == DDL_ON) +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EP_Global_Types Event Port Global Types + * @{ + */ + +/** + * @brief Event Pin Set and Reset enumeration + */ +typedef enum { + EVT_PIN_RESET = 0U, /*!< Pin reset */ + EVT_PIN_SET = 1U /*!< Pin set */ +} en_ep_state_t; + +typedef struct { + uint32_t u32PinDir; /*!< Input/Output setting, @ref EP_PinDirection_Sel for details */ + en_ep_state_t enPinState; /*!< Corresponding pin initial state, @ref en_ep_state_t for details */ + uint32_t u32PinTriggerOps; /*!< Corresponding pin state after triggered, @ref EP_TriggerOps_Sel for details */ + uint32_t u32Edge; /*!< Event port trigger edge, @ref EP_Trigger_Sel for details */ + uint32_t u32Filter; /*!< Filter clock function setting, @ref EP_FilterClock_Sel for details */ + uint32_t u32FilterClock; /*!< Filter clock, ref@ EP_FilterClock_Div for details */ +} stc_ep_init_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EP_Global_Macros Event Port Global Macros + * @{ + */ + +/** + * @defgroup EP_Port_source EP Port Source + * @{ + */ +#define EVT_PORT_1 (0U) /*!< Event port 1 */ +#define EVT_PORT_2 (1U) /*!< Event port 2 */ +#define EVT_PORT_3 (2U) /*!< Event port 3 */ +#define EVT_PORT_4 (3U) /*!< Event port 4 */ +/** + * @} + */ + +/** + * @defgroup EP_pins_define EP Pin Source + * @{ + */ +#define EVT_PIN_00 (0x0001U) /*!< Event port Pin 00 */ +#define EVT_PIN_01 (0x0002U) /*!< Event port Pin 01 */ +#define EVT_PIN_02 (0x0004U) /*!< Event port Pin 02 */ +#define EVT_PIN_03 (0x0008U) /*!< Event port Pin 03 */ +#define EVT_PIN_04 (0x0010U) /*!< Event port Pin 04 */ +#define EVT_PIN_05 (0x0020U) /*!< Event port Pin 05 */ +#define EVT_PIN_06 (0x0040U) /*!< Event port Pin 06 */ +#define EVT_PIN_07 (0x0080U) /*!< Event port Pin 07 */ +#define EVT_PIN_08 (0x0100U) /*!< Event port Pin 08 */ +#define EVT_PIN_09 (0x0200U) /*!< Event port Pin 09 */ +#define EVT_PIN_10 (0x0400U) /*!< Event port Pin 10 */ +#define EVT_PIN_11 (0x0800U) /*!< Event port Pin 11 */ +#define EVT_PIN_12 (0x1000U) /*!< Event port Pin 12 */ +#define EVT_PIN_13 (0x2000U) /*!< Event port Pin 13 */ +#define EVT_PIN_14 (0x4000U) /*!< Event port Pin 14 */ +#define EVT_PIN_15 (0x8000U) /*!< Event port Pin 15 */ +#define EVT_PIN_All (0xFFFFU) /*!< All event pins are selected */ +#define EVT_PIN_MASK (0xFFFFU) /*!< Event pin mask for assert test */ +/** + * @} + */ + +/** + * @defgroup EP_PinDirection_Sel EP Pin Input/Output Direction Selection + * @{ + */ +#define EP_DIR_IN (0UL) /*!< EP input */ +#define EP_DIR_OUT (1UL) /*!< EP output */ +/** + * @} + */ + +/** + * @defgroup EP_FilterClock_Sel Event Port Filter Function Selection + * @{ + */ +#define EP_FILTER_OFF (0UL) /*!< EP filter function OFF */ + +#define EP_FILTER_ON (1UL) /*!< EP filter function ON */ + +/** + * @} + */ + +/** + * @defgroup EP_FilterClock_Div Event Port Filter Sampling Clock Division Selection + * @{ + */ +#define EP_FCLK_DIV1 (0UL) /*!< PCLK as EP filter clock source */ +#define EP_FCLK_DIV8 (1UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div8 as EP filter clock source */ +#define EP_FCLK_DIV32 (2UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div32 as EP filter clock source */ +#define EP_FCLK_DIV64 (3UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div64 as EP filter clock source */ + +/** + * @} + */ + +/** + * @defgroup EP_Trigger_Sel Event Port Trigger Edge Selection + * @{ + */ +#define EP_TRIG_NONE (0UL) /*!< No Trigger by edge */ +#define EP_TRIG_FALLING (1UL) /*!< Trigger by falling edge */ +#define EP_TRIG_RISING (2UL) /*!< Trigger by rising edge */ +#define EP_TRIG_BOTH (3UL) /*!< Trigger by falling and rising edge */ + +/** + * @} + */ + +/** + * @defgroup EP_TriggerOps_Sel Event Port Operation + * @{ + */ +#define EP_OPS_NONE (0UL) /*!< Pin no action after triggered */ +#define EP_OPS_LOW (1UL) /*!< Pin ouput low after triggered */ +#define EP_OPS_HIGH (2UL) /*!< Pin ouput high after triggered */ +#define EP_OPS_TOGGLE (3UL) /*!< Pin toggle after triggered */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EP_Global_Functions + * @{ + */ +void EP_DeInit(void); +int32_t EP_StructInit(stc_ep_init_t *pstcEventPortInit); + +int32_t EP_Init(uint8_t u8EventPort, uint16_t u16EventPin, const stc_ep_init_t *pstcEventPortInit); +int32_t EP_SetTriggerEdge(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Edge); +int32_t EP_SetTriggerOps(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Ops); +en_ep_state_t EP_ReadInputPins(uint8_t u8EventPort, uint16_t u16EventPin); +uint16_t EP_ReadInputPort(uint8_t u8EventPort); +en_ep_state_t EP_ReadOutputPins(uint8_t u8EventPort, uint16_t u16EventPin); +uint16_t EP_ReadOutputPort(uint8_t u8EventPort); +void EP_SetPins(uint8_t u8EventPort, uint16_t u16EventPin); +void EP_ResetPins(uint8_t u8EventPort, uint16_t u16EventPin); +void EP_SetDir(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Dir); + +/** + * @} + */ + +#endif /* LL_EVENT_PORT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_EVENT_PORT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_fcg.h b/mcu/lib/inc/hc32_ll_fcg.h new file mode 100644 index 0000000..e6d9d33 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_fcg.h @@ -0,0 +1,203 @@ +/** + ******************************************************************************* + * @file hc32_ll_fcg.h + * @brief This file contains all the functions prototypes of the FCG driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_FCG_H__ +#define __HC32_LL_FCG_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_FCG + * @{ + */ + +#if (LL_FCG_ENABLE == DDL_ON) +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup FCG_Global_Macros FCG Global Macros + * @{ + */ +/** + * @defgroup FCG_FCG0_Peripheral FCG FCG0 peripheral + * @{ + */ +#define FCG0_PERIPH_SRAMH (PWC_FCG0_SRAMH) +#define FCG0_PERIPH_SRAM12 (PWC_FCG0_SRAM12) +#define FCG0_PERIPH_SRAM3 (PWC_FCG0_SRAM3) +#define FCG0_PERIPH_SRAMRET (PWC_FCG0_SRAMRET) +#define FCG0_PERIPH_DMA1 (PWC_FCG0_DMA1) +#define FCG0_PERIPH_DMA2 (PWC_FCG0_DMA2) +#define FCG0_PERIPH_FCM (PWC_FCG0_FCM) +#define FCG0_PERIPH_AOS (PWC_FCG0_AOS) +#define FCG0_PERIPH_AES (PWC_FCG0_AES) +#define FCG0_PERIPH_HASH (PWC_FCG0_HASH) +#define FCG0_PERIPH_TRNG (PWC_FCG0_TRNG) +#define FCG0_PERIPH_CRC (PWC_FCG0_CRC) +#define FCG0_PERIPH_DCU1 (PWC_FCG0_DCU1) +#define FCG0_PERIPH_DCU2 (PWC_FCG0_DCU2) +#define FCG0_PERIPH_DCU3 (PWC_FCG0_DCU3) +#define FCG0_PERIPH_DCU4 (PWC_FCG0_DCU4) +#define FCG0_PERIPH_KEY (PWC_FCG0_KEY) +/** + * @} + */ + +/** + * @defgroup FCG_FCG1_Peripheral FCG FCG1 peripheral + * @{ + */ +#define FCG1_PERIPH_CAN (PWC_FCG1_CAN) +#define FCG1_PERIPH_QSPI (PWC_FCG1_QSPI) +#define FCG1_PERIPH_I2C1 (PWC_FCG1_I2C1) +#define FCG1_PERIPH_I2C2 (PWC_FCG1_I2C2) +#define FCG1_PERIPH_I2C3 (PWC_FCG1_I2C3) +#define FCG1_PERIPH_USBFS (PWC_FCG1_USBFS) +#define FCG1_PERIPH_SDIOC1 (PWC_FCG1_SDIOC1) +#define FCG1_PERIPH_SDIOC2 (PWC_FCG1_SDIOC2) +#define FCG1_PERIPH_I2S1 (PWC_FCG1_I2S1) +#define FCG1_PERIPH_I2S2 (PWC_FCG1_I2S2) +#define FCG1_PERIPH_I2S3 (PWC_FCG1_I2S3) +#define FCG1_PERIPH_I2S4 (PWC_FCG1_I2S4) +#define FCG1_PERIPH_SPI1 (PWC_FCG1_SPI1) +#define FCG1_PERIPH_SPI2 (PWC_FCG1_SPI2) +#define FCG1_PERIPH_SPI3 (PWC_FCG1_SPI3) +#define FCG1_PERIPH_SPI4 (PWC_FCG1_SPI4) +#define FCG1_PERIPH_USART1 (PWC_FCG1_USART1) +#define FCG1_PERIPH_USART2 (PWC_FCG1_USART2) +#define FCG1_PERIPH_USART3 (PWC_FCG1_USART3) +#define FCG1_PERIPH_USART4 (PWC_FCG1_USART4) +/** + * @} + */ + +/** + * @defgroup FCG_FCG2_Peripheral FCG FCG2 peripheral + * @{ + */ +#define FCG2_PERIPH_TMR0_1 (PWC_FCG2_TIMER0_1) +#define FCG2_PERIPH_TMR0_2 (PWC_FCG2_TIMER0_2) +#define FCG2_PERIPH_TMRA_1 (PWC_FCG2_TIMERA_1) +#define FCG2_PERIPH_TMRA_2 (PWC_FCG2_TIMERA_2) +#define FCG2_PERIPH_TMRA_3 (PWC_FCG2_TIMERA_3) +#define FCG2_PERIPH_TMRA_4 (PWC_FCG2_TIMERA_4) +#define FCG2_PERIPH_TMRA_5 (PWC_FCG2_TIMERA_5) +#define FCG2_PERIPH_TMRA_6 (PWC_FCG2_TIMERA_6) +#define FCG2_PERIPH_TMR4_1 (PWC_FCG2_TIMER4_1) +#define FCG2_PERIPH_TMR4_2 (PWC_FCG2_TIMER4_2) +#define FCG2_PERIPH_TMR4_3 (PWC_FCG2_TIMER4_3) +#define FCG2_PERIPH_EMB (PWC_FCG2_EMB) +#define FCG2_PERIPH_TMR6_1 (PWC_FCG2_TIMER6_1) +#define FCG2_PERIPH_TMR6_2 (PWC_FCG2_TIMER6_2) +#define FCG2_PERIPH_TMR6_3 (PWC_FCG2_TIMER6_3) +/** + * @} + */ + +/** + * @defgroup FCG_FCG3_Peripheral FCG FCG3 peripheral + * @{ + */ +#define FCG3_PERIPH_ADC1 (PWC_FCG3_ADC1) +#define FCG3_PERIPH_ADC2 (PWC_FCG3_ADC2) +#define FCG3_PERIPH_CMP (PWC_FCG3_CMP) +#define FCG3_PERIPH_OTS (PWC_FCG3_OTS) +/** + * @} + */ + +/** + * @defgroup FCG_FCGx_Peripheral_Mask FCG FCGx Peripheral Mask + * @{ + */ +#define FCG_FCG0_PERIPH_MASK (0x8FF3C511UL) +#define FCG_FCG1_PERIPH_MASK (0x0F0FFD79UL) +#define FCG_FCG2_PERIPH_MASK (0x000787FFUL) +#define FCG_FCG3_PERIPH_MASK (0x00001103UL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup FCG_Global_Functions + * @{ + */ + +void FCG_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState); + +void FCG_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState); +void FCG_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState); +void FCG_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_FCG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_FCG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_fcm.h b/mcu/lib/inc/hc32_ll_fcm.h new file mode 100644 index 0000000..46d8691 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_fcm.h @@ -0,0 +1,293 @@ +/** + ******************************************************************************* + * @file hc32_ll_fcm.h + * @brief This file contains all the functions prototypes of the FCM driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-06-30 CDT Modify API FCM_DeInit() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_FCM_H__ +#define __HC32_LL_FCM_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_FCM + * @{ + */ + +#if (LL_FCM_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup FCM_Global_Types FCM Global Types + * @{ + */ +/** + * @brief FCM Init structure definition + */ +typedef struct { + uint16_t u16LowerLimit; /*!< FCM lower limit value */ + uint16_t u16UpperLimit; /*!< FCM upper limit value */ + uint32_t u32TargetClock; /*!< FCM target clock source selection, @ref FCM_Target_Clock_Src */ + uint32_t u32TargetClockDiv; /*!< FCM target clock source division selection, @ref FCM_Target_Clock_Div */ + uint32_t u32ExtRefClockEnable; /*!< FCM external reference clock function config, @ref FCM_Ext_Ref_Clock_Config */ + uint32_t u32RefClockEdge; /*!< FCM reference clock trigger edge selection, @ref FCM_Ref_Clock_Edge */ + uint32_t u32DigitalFilter; /*!< FCM digital filter function config, @ref FCM_Digital_Filter_Config */ + uint32_t u32RefClock; /*!< FCM reference clock source selection, @ref FCM_Ref_Clock_Src */ + uint32_t u32RefClockDiv; /*!< FCM reference clock source division selection, @ref FCM_Ref_Clock_Div */ + uint32_t u32ExceptionType; /*!< FCM exception type select, @ref FCM_Exception_Type */ +} stc_fcm_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup FCM_Global_Macros FCM Global Macros + * @{ + */ + +/** + * @defgroup FCM_Target_Clock_Src FCM Target Clock Source + * @{ + */ +#define FCM_TARGET_CLK_XTAL (0x00UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_XTAL32 (0x01UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_HRC (0x02UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_LRC (0x03UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_SWDTLRC (0x04UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_PCLK1 (0x05UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_UPLLP (0x06UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_MRC (0x07UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_MPLLP (0x08UL << FCM_MCCR_MCKS_POS) + +/** + * @} + */ + +/** + * @defgroup FCM_Target_Clock_Div FCM Target Clock Division + * @{ + */ +#define FCM_TARGET_CLK_DIV1 (0x00UL << FCM_MCCR_MDIVS_POS) +#define FCM_TARGET_CLK_DIV4 (0x01UL << FCM_MCCR_MDIVS_POS) +#define FCM_TARGET_CLK_DIV8 (0x02UL << FCM_MCCR_MDIVS_POS) +#define FCM_TARGET_CLK_DIV32 (0x03UL << FCM_MCCR_MDIVS_POS) +/** + * @} + */ + +/** + * @defgroup FCM_Ext_Ref_Clock_Config FCM External Reference Clock Config + * @{ + */ +#define FCM_EXT_REF_OFF (0x00UL) +#define FCM_EXT_REF_ON (FCM_RCCR_EXREFE) +/** + * @} + */ + +/** + * @defgroup FCM_Ref_Clock_Edge FCM Reference Clock Edge + * @{ + */ +#define FCM_REF_CLK_RISING (0x00UL) +#define FCM_REF_CLK_FALLING (FCM_RCCR_EDGES_0) +#define FCM_REF_CLK_BOTH (FCM_RCCR_EDGES_1) +/** + * @} + */ + +/** + * @defgroup FCM_Digital_Filter_Config FCM Digital Filter Config + * @{ + */ +#define FCM_DIG_FILTER_OFF (0x00UL) +#define FCM_DIG_FILTER_DIV1 (FCM_RCCR_DNFS_0) +#define FCM_DIG_FILTER_DIV4 (FCM_RCCR_DNFS_1) +#define FCM_DIG_FILTER_DIV16 (FCM_RCCR_DNFS) +/** + * @} + */ + +/** + * @defgroup FCM_Ref_Clock_Src FCM Reference Clock Source + * @{ + */ +#define FCM_REF_CLK_EXTCLK (0x00UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_XTAL (0x10UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_XTAL32 (0x11UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_HRC (0x12UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_LRC (0x13UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_SWDTLRC (0x14UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_PCLK1 (0x15UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_UPLLP (0x16UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_MRC (0x17UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_MPLLP (0x18UL << FCM_RCCR_RCKS_POS) + +/** + * @} + */ + +/** + * @defgroup FCM_Ref_Clock_Div FCM Reference Clock Division + * @{ + */ +#define FCM_REF_CLK_DIV32 (0x00UL << FCM_RCCR_RDIVS_POS) +#define FCM_REF_CLK_DIV128 (0x01UL << FCM_RCCR_RDIVS_POS) +#define FCM_REF_CLK_DIV1024 (0x02UL << FCM_RCCR_RDIVS_POS) +#define FCM_REF_CLK_DIV8192 (0x03UL << FCM_RCCR_RDIVS_POS) +/** + * @} + */ + +/** + * @defgroup FCM_Abnormal_Reset_Func FCM Abnormal Reset Function Config + * @{ + */ +#define FCM_ERR_RST_OFF (0x00UL) +#define FCM_ERR_RST_ON (FCM_RIER_ERRE) +/** + * @} + */ + +/** + * @defgroup FCM_Exception_Type FCM Exception Type + * @{ + */ +#define FCM_EXP_TYPE_INT (0x00UL) +#define FCM_EXP_TYPE_RST (FCM_RIER_ERRINTRS) +/** + * @} + */ + +/** + * @defgroup FCM_Int_Type FCM Interrupt Type + * @{ + */ +#define FCM_INT_OVF (FCM_RIER_OVFIE) +#define FCM_INT_END (FCM_RIER_MENDIE) +#define FCM_INT_ERR (FCM_RIER_ERRIE) +/** + * @} + */ + +/** + * @defgroup FCM_Flag_Sel FCM Status Flag Selection + * @{ + */ +#define FCM_FLAG_ERR (FCM_SR_ERRF) +#define FCM_FLAG_END (FCM_SR_MENDF) +#define FCM_FLAG_OVF (FCM_SR_OVF) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup FCM_Global_Functions + * @{ + */ + +/** + * @brief Set FCM upper limit value. + * @param u16Limit + * @retval None. + */ +__STATIC_INLINE void FCM_SetUpperLimit(uint16_t u16Limit) +{ + WRITE_REG32(CM_FCM->UVR, u16Limit); +} + +/** + * @brief Set FCM lower limit value. + * @param u16Limit + * @retval None + */ +__STATIC_INLINE void FCM_SetLowerLimit(uint16_t u16Limit) +{ + WRITE_REG32(CM_FCM->LVR, u16Limit); +} + +int32_t FCM_Init(const stc_fcm_init_t *pstcFcmInit); +int32_t FCM_StructInit(stc_fcm_init_t *pstcFcmInit); +int32_t FCM_DeInit(void); +uint16_t FCM_GetCountValue(void); +void FCM_SetUpperLimit(uint16_t u16Limit); +void FCM_SetLowerLimit(uint16_t u16Limit); +void FCM_SetTargetClock(uint32_t u32ClockSrc, uint32_t u32Div); +void FCM_SetRefClock(uint32_t u32ClockSrc, uint32_t u32Div); +en_flag_status_t FCM_GetStatus(uint32_t u32Flag); +void FCM_ClearStatus(uint32_t u32Flag); +void FCM_ResetCmd(en_functional_state_t enNewState); +void FCM_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState); +void FCM_Cmd(en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_FCM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_FCM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_gpio.h b/mcu/lib/inc/hc32_ll_gpio.h new file mode 100644 index 0000000..3b60137 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_gpio.h @@ -0,0 +1,418 @@ +/** + ******************************************************************************* + * @file hc32_ll_gpio.h + * @brief This file contains all the functions prototypes of the GPIO driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Add API GPIO_AnalogCmd() and GPIO_ExIntCmd() + 2023-06-30 CDT Rename GPIO_ExIntCmd() as GPIO_ExtIntCmd + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_GPIO_H__ +#define __HC32_LL_GPIO_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_GPIO + * @{ + */ + +#if (LL_GPIO_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup GPIO_Global_Types GPIO Global Types + * @{ + */ + +/** + * @brief GPIO Pin Set and Reset enumeration + */ +typedef enum { + PIN_RESET = 0U, /*!< Pin reset */ + PIN_SET = 1U /*!< Pin set */ +} en_pin_state_t; + +/** + * @brief GPIO Init structure definition + */ +typedef struct { + uint16_t u16PinState; /*!< Set pin state to High or Low, @ref GPIO_PinState_Sel for details */ + uint16_t u16PinDir; /*!< Pin mode setting, @ref GPIO_PinDirection_Sel for details */ + uint16_t u16PinOutputType; /*!< Output type setting, @ref GPIO_PinOutType_Sel for details */ + uint16_t u16PinDrv; /*!< Pin drive capacity setting, @ref GPIO_PinDrv_Sel for details */ + uint16_t u16Latch; /*!< Pin latch setting, @ref GPIO_PinLatch_Sel for details */ + uint16_t u16PullUp; /*!< Internal pull-up resistor setting, @ref GPIO_PinPU_Sel for details */ + uint16_t u16Invert; /*!< Pin input/output invert setting, @ref GPIO_PinInvert_Sel for details */ + uint16_t u16ExtInt; /*!< External interrupt pin setting, @ref GPIO_PinExtInt_Sel for details */ + uint16_t u16PinAttr; /*!< Digital or analog attribute setting, @ref GPIO_PinMode_Sel for details */ +} stc_gpio_init_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup GPIO_Global_Macros GPIO Global Macros + * @{ + */ + +/** + * @defgroup GPIO_Pins_Define GPIO Pin Source + * @{ + */ +#define GPIO_PIN_00 (0x0001U) /*!< Pin 00 selected */ +#define GPIO_PIN_01 (0x0002U) /*!< Pin 01 selected */ +#define GPIO_PIN_02 (0x0004U) /*!< Pin 02 selected */ +#define GPIO_PIN_03 (0x0008U) /*!< Pin 03 selected */ +#define GPIO_PIN_04 (0x0010U) /*!< Pin 04 selected */ +#define GPIO_PIN_05 (0x0020U) /*!< Pin 05 selected */ +#define GPIO_PIN_06 (0x0040U) /*!< Pin 06 selected */ +#define GPIO_PIN_07 (0x0080U) /*!< Pin 07 selected */ +#define GPIO_PIN_08 (0x0100U) /*!< Pin 08 selected */ +#define GPIO_PIN_09 (0x0200U) /*!< Pin 09 selected */ +#define GPIO_PIN_10 (0x0400U) /*!< Pin 10 selected */ +#define GPIO_PIN_11 (0x0800U) /*!< Pin 11 selected */ +#define GPIO_PIN_12 (0x1000U) /*!< Pin 12 selected */ +#define GPIO_PIN_13 (0x2000U) /*!< Pin 13 selected */ +#define GPIO_PIN_14 (0x4000U) /*!< Pin 14 selected */ +#define GPIO_PIN_15 (0x8000U) /*!< Pin 15 selected */ +#define GPIO_PIN_ALL (0xFFFFU) /*!< All pins selected */ +/** + * @} + */ + +/** + * @defgroup GPIO_All_Pins_Define GPIO All Pin Definition for Each Product + * @{ + */ +#define GPIO_PIN_A_ALL (0xFFFFU) /*!< Pin A all*/ +#define GPIO_PIN_B_ALL (0xFFFFU) /*!< Pin B all*/ +#define GPIO_PIN_C_ALL (0xFFFFU) /*!< Pin C all*/ +#define GPIO_PIN_D_ALL (0xFFFFU) /*!< Pin D all*/ +#define GPIO_PIN_E_ALL (0xFFFFU) /*!< Pin E all*/ +#define GPIO_PIN_H_ALL (0x0007U) /*!< Pin H all*/ +/** + * @} + */ + +/** + * @defgroup GPIO_Port_Source GPIO Port Source + * @{ + */ +#define GPIO_PORT_A (0x00U) /*!< Port A selected */ +#define GPIO_PORT_B (0x01U) /*!< Port B selected */ +#define GPIO_PORT_C (0x02U) /*!< Port C selected */ +#define GPIO_PORT_D (0x03U) /*!< Port D selected */ +#define GPIO_PORT_E (0x04U) /*!< Port E selected */ +#define GPIO_PORT_H (0x05U) /*!< Port H selected */ +/** + * @} + */ + +/** + * @defgroup GPIO_Function_Sel GPIO Function Selection + * @{ + */ +#define GPIO_FUNC_0 (0U) +#define GPIO_FUNC_1 (1U) +#define GPIO_FUNC_2 (2U) +#define GPIO_FUNC_3 (3U) +#define GPIO_FUNC_4 (4U) +#define GPIO_FUNC_5 (5U) +#define GPIO_FUNC_6 (6U) +#define GPIO_FUNC_7 (7U) +#define GPIO_FUNC_8 (8U) +#define GPIO_FUNC_9 (9U) +#define GPIO_FUNC_10 (10U) +#define GPIO_FUNC_11 (11U) +#define GPIO_FUNC_12 (12U) +#define GPIO_FUNC_13 (13U) +#define GPIO_FUNC_14 (14U) +#define GPIO_FUNC_15 (15U) +#define GPIO_FUNC_32 (32U) +#define GPIO_FUNC_33 (33U) +#define GPIO_FUNC_34 (34U) +#define GPIO_FUNC_35 (35U) +#define GPIO_FUNC_36 (36U) +#define GPIO_FUNC_37 (37U) +#define GPIO_FUNC_38 (38U) +#define GPIO_FUNC_39 (39U) +#define GPIO_FUNC_40 (40U) +#define GPIO_FUNC_41 (41U) +#define GPIO_FUNC_42 (42U) +#define GPIO_FUNC_43 (43U) +#define GPIO_FUNC_44 (44U) +#define GPIO_FUNC_45 (45U) +#define GPIO_FUNC_46 (46U) +#define GPIO_FUNC_47 (47U) +#define GPIO_FUNC_48 (48U) +#define GPIO_FUNC_49 (49U) +#define GPIO_FUNC_50 (50U) +#define GPIO_FUNC_51 (51U) +#define GPIO_FUNC_52 (52U) +#define GPIO_FUNC_53 (53U) +#define GPIO_FUNC_54 (54U) +#define GPIO_FUNC_55 (55U) +#define GPIO_FUNC_56 (56U) +#define GPIO_FUNC_57 (57U) +#define GPIO_FUNC_58 (58U) +#define GPIO_FUNC_59 (59U) +/** + * @} + */ + +/** + * @defgroup GPIO_DebugPin_Sel GPIO Debug Pin Selection + * @{ + */ +#define GPIO_PIN_TCK (0x01U) +#define GPIO_PIN_TMS (0x02U) +#define GPIO_PIN_TDO (0x04U) +#define GPIO_PIN_TDI (0x08U) +#define GPIO_PIN_TRST (0x10U) +#define GPIO_PIN_DEBUG_JTAG (0x1FU) +#define GPIO_PIN_SWCLK (0x01U) +#define GPIO_PIN_SWDIO (0x02U) +#define GPIO_PIN_SWO (0x04U) +#define GPIO_PIN_DEBUG_SWD (0x07U) +#define GPIO_PIN_DEBUG (0x1FU) +/** + * @} + */ + +/** + * @defgroup GPIO_ReadCycle_Sel GPIO Pin Read Wait Cycle Selection + * @{ + */ +#define GPIO_RD_WAIT0 (0x00U << GPIO_PCCR_RDWT_POS) +#define GPIO_RD_WAIT1 (0x01U << GPIO_PCCR_RDWT_POS) +#define GPIO_RD_WAIT2 (0x02U << GPIO_PCCR_RDWT_POS) +#define GPIO_RD_WAIT3 (0x03U << GPIO_PCCR_RDWT_POS) +/** + * @} + */ + +/** + * @defgroup GPIO_PinState_Sel GPIO Pin Output State Selection + * @{ + */ +#define PIN_STAT_RST (0U) +#define PIN_STAT_SET (GPIO_PCR_POUT) +/** + * @} + */ + +/** + * @defgroup GPIO_PinDirection_Sel GPIO Pin Input/Output Direction Selection + * @{ + */ +#define PIN_DIR_IN (0U) +#define PIN_DIR_OUT (GPIO_PCR_POUTE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinOutType_Sel GPIO Pin Output Type Selection + * @{ + */ +#define PIN_OUT_TYPE_CMOS (0U) +#define PIN_OUT_TYPE_NMOS (GPIO_PCR_NOD) +/** + * @} + */ + +/** + * @defgroup GPIO_PinDrv_Sel GPIO Pin Drive Capacity Selection + * @{ + */ +#define PIN_LOW_DRV (0U) +#define PIN_MID_DRV (GPIO_PCR_DRV_0) +#define PIN_HIGH_DRV (GPIO_PCR_DRV_1) +/** + * @} + */ + +/** + * @defgroup GPIO_PinLatch_Sel GPIO Pin Output Latch Selection + * @{ + */ +#define PIN_LATCH_OFF (0U) +#define PIN_LATCH_ON (GPIO_PCR_LTE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinPU_Sel GPIO Pin Internal Pull-Up Resistor Selection + * @{ + */ +#define PIN_PU_OFF (0U) +#define PIN_PU_ON (GPIO_PCR_PUU) +/** + * @} + */ + +/** + * @defgroup GPIO_PinInvert_Sel GPIO Pin I/O Invert Selection + * @{ + */ +#define PIN_INVT_OFF (0U) +#define PIN_INVT_ON (GPIO_PCR_INVE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinExtInt_Sel GPIO Pin External Interrupt Selection + * @{ + */ +#define PIN_EXTINT_OFF (0U) +#define PIN_EXTINT_ON (GPIO_PCR_INTE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinMode_Sel GPIO Pin Mode Selection + * @{ + */ +#define PIN_ATTR_DIGITAL (0U) +#define PIN_ATTR_ANALOG (GPIO_PCR_DDIS) +/** + * @} + */ + +/** + * @defgroup GPIO_PinSubFuncSet_Sel GPIO Pin Sub-function Enable or Disable + * @{ + */ +#define PIN_SUBFUNC_DISABLE (0U) +#define PIN_SUBFUNC_ENABLE (GPIO_PFSR_BFE) +/** + * @} + */ + +/** + * @defgroup GPIO_Register_Protect_Key GPIO Registers Protect Key + * @{ + */ +#define GPIO_REG_LOCK_KEY (0xA500U) +#define GPIO_REG_UNLOCK_KEY (0xA501U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup GPIO_Global_Functions + * @{ + */ +/** + * @brief GPIO lock. PSPCR, PCCR, PINAER, PCRxy, PFSRxy write disable + * @param None + * @retval None + */ +__STATIC_INLINE void GPIO_REG_Lock(void) +{ + WRITE_REG16(CM_GPIO->PWPR, GPIO_REG_LOCK_KEY); +} + +/** + * @brief GPIO unlock. PSPCR, PCCR, PINAER, PCRxy, PFSRxy write enable + * @param None + * @retval None + */ +__STATIC_INLINE void GPIO_REG_Unlock(void) +{ + WRITE_REG16(CM_GPIO->PWPR, GPIO_REG_UNLOCK_KEY); +} + +int32_t GPIO_Init(uint8_t u8Port, uint16_t u16Pin, const stc_gpio_init_t *pstcGpioInit); +void GPIO_DeInit(void); +int32_t GPIO_StructInit(stc_gpio_init_t *pstcGpioInit); +void GPIO_SetDebugPort(uint8_t u8DebugPort, en_functional_state_t enNewState); +void GPIO_SetFunc(uint8_t u8Port, uint16_t u16Pin, uint16_t u16Func); +void GPIO_SubFuncCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState); +void GPIO_SetSubFunc(uint8_t u8Func); +void GPIO_SetReadWaitCycle(uint16_t u16ReadWait); +void GPIO_InputMOSCmd(uint8_t u8Port, en_functional_state_t enNewState); +void GPIO_OutputCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState); +en_pin_state_t GPIO_ReadInputPins(uint8_t u8Port, uint16_t u16Pin); +uint16_t GPIO_ReadInputPort(uint8_t u8Port); +en_pin_state_t GPIO_ReadOutputPins(uint8_t u8Port, uint16_t u16Pin); +uint16_t GPIO_ReadOutputPort(uint8_t u8Port); +void GPIO_SetPins(uint8_t u8Port, uint16_t u16Pin); +void GPIO_ResetPins(uint8_t u8Port, uint16_t u16Pin); +void GPIO_WritePort(uint8_t u8Port, uint16_t u16PortVal); +void GPIO_TogglePins(uint8_t u8Port, uint16_t u16Pin); +void GPIO_ExtIntCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState); +void GPIO_AnalogCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState); +/** + * @} + */ + +#endif /* LL_GPIO_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_GPIO_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_hash.h b/mcu/lib/inc/hc32_ll_hash.h new file mode 100644 index 0000000..18509c2 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_hash.h @@ -0,0 +1,95 @@ +/** + ******************************************************************************* + * @file hc32_ll_hash.h + * @brief This file contains all the functions prototypes of the HASH driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-06-30 CDT Add HASH_DeInit function + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_HASH_H__ +#define __HC32_LL_HASH_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_HASH + * @{ + */ + +#if (LL_HASH_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup HASH_Global_Functions + * @{ + */ + +int32_t HASH_DeInit(void); +int32_t HASH_Calculate(const uint8_t *pu8SrcData, uint32_t u32SrcDataSize, uint8_t *pu8MsgDigest); + +/** + * @} + */ + +#endif /* LL_HASH_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_HASH_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_i2c.h b/mcu/lib/inc/hc32_ll_i2c.h new file mode 100644 index 0000000..f1ff0c4 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_i2c.h @@ -0,0 +1,327 @@ +/** + ******************************************************************************* + * @file hc32_ll_i2c.h + * @brief This file contains all the functions prototypes of the Inter-Integrated + * Circuit(I2C) driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Add API I2C_SlaveAddrCmd() + 2023-09-30 CDT Modify typo + Move macro define I2C_SRC_CLK to head file + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_I2C_H__ +#define __HC32_LL_I2C_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_I2C + * @{ + */ + +#if (LL_I2C_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup I2C_Global_Types I2C Global Types + * @{ + */ + +/** + * @brief I2c configuration structure + */ +typedef struct { + uint32_t u32ClockDiv; /*!< I2C clock division for i2c source clock */ + uint32_t u32Baudrate; /*!< I2C baudrate config */ + uint32_t u32SclTime; /*!< The SCL rising and falling time, count of T(i2c source clock after frequency divider) */ +} stc_i2c_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup I2C_Global_Macros I2C Global Macros + * @{ + */ + +#define I2C_SRC_CLK (SystemCoreClock >> ((CM_CMU->SCFGR & CMU_SCFGR_PCLK3S) >> CMU_SCFGR_PCLK3S_POS)) + +#define I2C_WIDTH_MAX_IMME (68UL) + +/** + * @defgroup I2C_Trans_Dir I2C Transfer Direction + * @{ + */ +#define I2C_DIR_TX (0x0U) +#define I2C_DIR_RX (0x1U) +/** + * @} + */ + +/** + * @defgroup I2C_Addr_Config I2C Address Configure + * @{ + */ +#define I2C_ADDR_DISABLE (0U) +#define I2C_ADDR_7BIT (I2C_SLR0_SLADDR0EN) +#define I2C_ADDR_10BIT (I2C_SLR0_ADDRMOD0 | I2C_SLR0_SLADDR0EN) +/** + * @} + */ + +/** + * @defgroup I2C_Clock_Division I2C Clock Division + * @{ + */ +#define I2C_CLK_DIV1 (0UL) /*!< I2c source clock/1 */ +#define I2C_CLK_DIV2 (1UL) /*!< I2c source clock/2 */ +#define I2C_CLK_DIV4 (2UL) /*!< I2c source clock/4 */ +#define I2C_CLK_DIV8 (3UL) /*!< I2c source clock/8 */ +#define I2C_CLK_DIV16 (4UL) /*!< I2c source clock/16 */ +#define I2C_CLK_DIV32 (5UL) /*!< I2c source clock/32 */ +#define I2C_CLK_DIV64 (6UL) /*!< I2c source clock/64 */ +#define I2C_CLK_DIV128 (7UL) /*!< I2c source clock/128 */ +/** + * @} + */ + +/** + * @defgroup I2C_Address_Num I2C Address Number + * @{ + */ +#define I2C_ADDR0 (0UL) +#define I2C_ADDR1 (1UL) +/** + * @} + */ + +/** + * @defgroup I2C_Ack_Config I2C ACK Configure + * @{ + */ +#define I2C_ACK (0UL) /*!< Send ACK after date receive */ +#define I2C_NACK (I2C_CR1_ACK) /*!< Send NACK after date received */ +/** + * @} + */ + +/** + * @defgroup I2C_Smbus_Match_Config I2C SMBUS Address Match Configure + * @{ + */ +#define I2C_SMBUS_MATCH_ALARM (I2C_CR1_SMBALRTEN) +#define I2C_SMBUS_MATCH_DEFAULT (I2C_CR1_SMBDEFAULTEN) +#define I2C_SMBUS_MATCH_HOST (I2C_CR1_SMBHOSTEN) +#define I2C_SMBUS_MATCH_ALL (I2C_CR1_SMBALRTEN | I2C_CR1_SMBDEFAULTEN | I2C_CR1_SMBHOSTEN) +/** + * @} + */ + +/** + * @defgroup I2C_Digital_Filter_Clock I2C Digital Filter Clock + * @{ + */ +#define I2C_DIG_FILTER_CLK_DIV1 (0UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/1 */ +#define I2C_DIG_FILTER_CLK_DIV2 (1UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/2 */ +#define I2C_DIG_FILTER_CLK_DIV3 (2UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/3 */ +#define I2C_DIG_FILTER_CLK_DIV4 (3UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/4 */ +/** + * @} + */ + +/** + * @defgroup I2C_Flag I2C Flag + * @{ + */ +#define I2C_FLAG_START (I2C_SR_STARTF) /*!< Start condition detected */ +#define I2C_FLAG_MATCH_ADDR0 (I2C_SR_SLADDR0F) /*!< Address 0 detected */ +#define I2C_FLAG_MATCH_ADDR1 (I2C_SR_SLADDR1F) /*!< Address 1 detected */ +#define I2C_FLAG_TX_CPLT (I2C_SR_TENDF) /*!< Transfer end */ +#define I2C_FLAG_STOP (I2C_SR_STOPF) /*!< Stop condition detected */ +#define I2C_FLAG_RX_FULL (I2C_SR_RFULLF) /*!< Receive buffer full */ +#define I2C_FLAG_TX_EMPTY (I2C_SR_TEMPTYF) /*!< Transfer buffer empty */ +#define I2C_FLAG_ARBITRATE_FAIL (I2C_SR_ARLOF) /*!< Arbitration fails */ +#define I2C_FLAG_ACKR (I2C_SR_ACKRF) /*!< ACK status */ +#define I2C_FLAG_NACKF (I2C_SR_NACKF) /*!< NACK detected */ +#define I2C_FLAG_TMOUTF (I2C_SR_TMOUTF) /*!< Time out detected */ +#define I2C_FLAG_MASTER (I2C_SR_MSL) /*!< Master mode flag */ +#define I2C_FLAG_BUSY (I2C_SR_BUSY) /*!< Bus busy status */ +#define I2C_FLAG_TRA (I2C_SR_TRA) /*!< Transfer mode flag */ +#define I2C_FLAG_GENERAL_CALL (I2C_SR_GENCALLF) /*!< General call detected */ +#define I2C_FLAG_SMBUS_DEFAULT_MATCH (I2C_SR_SMBDEFAULTF) /*!< SMBUS default address detected */ +#define I2C_FLAG_SMBUS_HOST_MATCH (I2C_SR_SMBHOSTF) /*!< SMBUS host address detected */ +#define I2C_FLAG_SMBUS_ALARM_MATCH (I2C_SR_SMBALRTF) /*!< SMBUS alarm address detected */ + +#define I2C_FLAG_CLR_ALL (I2C_FLAG_START | I2C_FLAG_MATCH_ADDR0 | I2C_FLAG_MATCH_ADDR1 \ + | I2C_FLAG_TX_CPLT | I2C_FLAG_STOP | I2C_FLAG_RX_FULL | I2C_FLAG_TX_EMPTY \ + | I2C_FLAG_ARBITRATE_FAIL | I2C_FLAG_NACKF | I2C_FLAG_TMOUTF \ + | I2C_FLAG_GENERAL_CALL | I2C_FLAG_SMBUS_DEFAULT_MATCH \ + | I2C_FLAG_SMBUS_HOST_MATCH | I2C_FLAG_SMBUS_ALARM_MATCH) +#define I2C_FLAG_ALL (I2C_FLAG_START | I2C_FLAG_MATCH_ADDR0 | I2C_FLAG_MATCH_ADDR1 | I2C_FLAG_TX_CPLT \ + | I2C_FLAG_STOP | I2C_FLAG_RX_FULL | I2C_FLAG_TX_EMPTY | I2C_FLAG_ARBITRATE_FAIL\ + | I2C_FLAG_ACKR | I2C_FLAG_NACKF | I2C_FLAG_TMOUTF | I2C_FLAG_MASTER \ + | I2C_FLAG_BUSY | I2C_FLAG_TRA | I2C_FLAG_GENERAL_CALL \ + | I2C_FLAG_SMBUS_DEFAULT_MATCH | I2C_FLAG_SMBUS_HOST_MATCH \ + | I2C_FLAG_SMBUS_ALARM_MATCH) +/** + * @} + */ + +/** + * @defgroup I2C_Int_Flag I2C Interrupt Flag Bits + * @{ + */ +#define I2C_INT_START (I2C_CR2_STARTIE) +#define I2C_INT_MATCH_ADDR0 (I2C_CR2_SLADDR0IE) +#define I2C_INT_MATCH_ADDR1 (I2C_CR2_SLADDR1IE) +#define I2C_INT_TX_CPLT (I2C_CR2_TENDIE) +#define I2C_INT_STOP (I2C_CR2_STOPIE) +#define I2C_INT_RX_FULL (I2C_CR2_RFULLIE) +#define I2C_INT_TX_EMPTY (I2C_CR2_TEMPTYIE) +#define I2C_INT_ARBITRATE_FAIL (I2C_CR2_ARLOIE) +#define I2C_INT_NACK (I2C_CR2_NACKIE) +#define I2C_INT_TMOUTIE (I2C_CR2_TMOUTIE) +#define I2C_INT_GENERAL_CALL (I2C_CR2_GENCALLIE) +#define I2C_INT_SMBUS_DEFAULT_MATCH (I2C_CR2_SMBDEFAULTIE) +#define I2C_INT_SMBUS_HOST_MATCH (I2C_CR2_SMBHOSTIE) +#define I2C_INT_SMBUS_ALARM_MATCH (I2C_CR2_SMBALRTIE) + +#define I2C_INT_ALL (I2C_INT_START | I2C_INT_MATCH_ADDR0 | I2C_INT_MATCH_ADDR1 | I2C_INT_TX_CPLT \ + | I2C_INT_STOP | I2C_INT_RX_FULL | I2C_INT_TX_EMPTY | I2C_INT_ARBITRATE_FAIL \ + | I2C_INT_NACK | I2C_INT_TMOUTIE | I2C_INT_GENERAL_CALL \ + | I2C_INT_SMBUS_DEFAULT_MATCH | I2C_INT_SMBUS_HOST_MATCH \ + | I2C_INT_SMBUS_ALARM_MATCH) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup I2C_Global_Functions + * @{ + */ + +/* Initialization and Configuration **********************************/ +int32_t I2C_StructInit(stc_i2c_init_t *pstcI2cInit); +int32_t I2C_BaudrateConfig(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error); +void I2C_DeInit(CM_I2C_TypeDef *I2Cx); +int32_t I2C_Init(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error); +void I2C_SlaveAddrConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32Addr); +void I2C_SlaveAddrCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, en_functional_state_t enNewState); +void I2C_Cmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_FastAckCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_BusWaitCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +void I2C_SmbusConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32SmbusConfig, en_functional_state_t enNewState); +void I2C_SmbusCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +void I2C_DigitalFilterConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32FilterClock); +void I2C_DigitalFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +void I2C_AnalogFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +void I2C_GeneralCallCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_SWResetCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_IntCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32IntType, en_functional_state_t enNewState); + +/* Start/Restart/Stop ************************************************/ +void I2C_GenerateStart(CM_I2C_TypeDef *I2Cx); +void I2C_GenerateRestart(CM_I2C_TypeDef *I2Cx); +void I2C_GenerateStop(CM_I2C_TypeDef *I2Cx); + +/* Status management *************************************************/ +en_flag_status_t I2C_GetStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag); +void I2C_ClearStatus(CM_I2C_TypeDef *I2Cx, uint32_t u32Flag); + +/* Data transfer *****************************************************/ +void I2C_WriteData(CM_I2C_TypeDef *I2Cx, uint8_t u8Data); +uint8_t I2C_ReadData(const CM_I2C_TypeDef *I2Cx); +void I2C_AckConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AckConfig); + +/* Time out function *************************************************/ +void I2C_SCLHighTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutH); +void I2C_SCLLowTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutL); +void I2C_SCLHighTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_SCLLowTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_SCLTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +/* High level functions for reference ********************************/ +int32_t I2C_Start(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout); +int32_t I2C_Restart(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout); +int32_t I2C_TransAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout); +int32_t I2C_Trans10BitAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout); +int32_t I2C_TransData(CM_I2C_TypeDef *I2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout); +int32_t I2C_ReceiveData(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout); +int32_t I2C_MasterReceiveDataAndStop(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout); +int32_t I2C_Stop(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout); +int32_t I2C_WaitStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout); + +/** + * @} + */ + +#endif /* LL_I2C_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_I2C_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_i2s.h b/mcu/lib/inc/hc32_ll_i2s.h new file mode 100644 index 0000000..388142b --- /dev/null +++ b/mcu/lib/inc/hc32_ll_i2s.h @@ -0,0 +1,342 @@ +/** + ******************************************************************************* + * @file hc32_ll_i2s.h + * @brief This file contains all the functions prototypes of the I2S driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_I2S_H__ +#define __HC32_LL_I2S_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_I2S + * @{ + */ + +#if (LL_I2S_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup I2S_Global_Types I2S Global Types + * @{ + */ + +/** + * @brief I2S Init structure definition + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Specifies the clock source of I2S. + This parameter can be a value of @ref I2S_Clock_Source */ + uint32_t u32Mode; /*!< Specifies the master/slave mode of I2S. + This parameter can be a value of @ref I2S_Mode */ + uint32_t u32Protocol; /*!< Specifies the communication protocol of I2S. + This parameter can be a value of @ref I2S_Protocol */ + uint32_t u32TransMode; /*!< Specifies the transmission mode for the I2S communication. + This parameter can be a value of @ref I2S_Trans_Mode */ + uint32_t u32AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + uint32_t u32ChWidth; /*!< Specifies the channel length for the I2S communication. + This parameter can be a value of @ref I2S_Channel_Length */ + uint32_t u32DataWidth; /*!< Specifies the data length for the I2S communication. + This parameter can be a value of @ref I2S_Data_Length */ + uint32_t u32MCKOutput; /*!< Specifies the validity of the MCK output for I2S. + This parameter can be a value of @ref I2S_MCK_Output */ + uint32_t u32TransFIFOLevel; /*!< Specifies the level of transfer FIFO. + This parameter can be a value of @ref I2S_Trans_Level */ + uint32_t u32ReceiveFIFOLevel; /*!< Specifies the level of receive FIFO. + This parameter can be a value of @ref I2S_Receive_Level */ +} stc_i2s_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup I2S_Global_Macros I2S Global Macros + * @{ + */ + +/** + * @defgroup I2S_External_Clock_Frequency I2S External Clock Frequency + * @{ + */ +#ifndef I2S_EXT_CLK_FREQ +#define I2S_EXT_CLK_FREQ (12288000UL) /*!< Value of the external oscillator */ +#endif /* I2S_EXT_CLK_FREQ */ +/** + * @} + */ + +/** + * @defgroup I2S_Clock_Source I2S Clock Source + * @{ + */ +#define I2S_CLK_SRC_PLL (I2S_CTRL_I2SPLLSEL) /*!< Internal PLL Clock */ +#define I2S_CLK_SRC_EXT (I2S_CTRL_CLKSEL) /*!< External Clock */ +/** + * @} + */ + +/** + * @defgroup I2S_Mode I2S Mode + * @{ + */ +#define I2S_MD_MASTER (0UL) /*!< Master mode */ +#define I2S_MD_SLAVE (I2S_CTRL_WMS) /*!< Slave mode */ +/** + * @} + */ + +/** + * @defgroup I2S_Protocol I2S Communication Protocol + * @{ + */ +#define I2S_PROTOCOL_PHILLIPS (0UL) /*!< Phillips protocol */ +#define I2S_PROTOCOL_MSB (I2S_CFGR_I2SSTD_0) /*!< MSB justified protocol */ +#define I2S_PROTOCOL_LSB (I2S_CFGR_I2SSTD_1) /*!< LSB justified protocol */ +#define I2S_PROTOCOL_PCM_SHORT (I2S_CFGR_I2SSTD) /*!< PCM short-frame protocol */ +#define I2S_PROTOCOL_PCM_LONG (I2S_CFGR_I2SSTD | I2S_CFGR_PCMSYNC) /*!< PCM long-frame protocol */ +/** + * @} + */ + +/** + * @defgroup I2S_Trans_Mode I2S Transfer Mode + * @{ + */ +#define I2S_TRANS_MD_HALF_DUPLEX_RX (0UL) /*!< Receive only and half duplex mode */ +#define I2S_TRANS_MD_HALF_DUPLEX_TX (I2S_CTRL_SDOE) /*!< Send only and half duplex mode */ +#define I2S_TRANS_MD_FULL_DUPLEX (I2S_CTRL_DUPLEX | I2S_CTRL_SDOE) /*!< Full duplex mode */ +/** + * @} + */ + +/** + * @defgroup I2S_Audio_Frequency I2S Audio Frequency + * @{ + */ +#define I2S_AUDIO_FREQ_192K (192000UL) /*!< FS = 192000Hz */ +#define I2S_AUDIO_FREQ_96K (96000UL) /*!< FS = 96000Hz */ +#define I2S_AUDIO_FREQ_48K (48000UL) /*!< FS = 48000Hz */ +#define I2S_AUDIO_FREQ_44K (44100UL) /*!< FS = 44100Hz */ +#define I2S_AUDIO_FREQ_32K (32000UL) /*!< FS = 32000Hz */ +#define I2S_AUDIO_FREQ_22K (22050UL) /*!< FS = 22050Hz */ +#define I2S_AUDIO_FREQ_16K (16000UL) /*!< FS = 16000Hz */ +#define I2S_AUDIO_FREQ_8K (8000UL) /*!< FS = 8000Hz */ +#define I2S_AUDIO_FREQ_DEFAULT (2UL) +/** + * @} + */ + +/** + * @defgroup I2S_Channel_Length I2S Channel Length + * @{ + */ +#define I2S_CH_LEN_16BIT (0UL) /*!< Channel length is 16bits */ +#define I2S_CH_LEN_32BIT (I2S_CFGR_CHLEN) /*!< Channel length is 32bits */ +/** + * @} + */ + +/** + * @defgroup I2S_Data_Length I2S Data Length + * @{ + */ +#define I2S_DATA_LEN_16BIT (0UL) /*!< Transfer data length is 16bits */ +#define I2S_DATA_LEN_24BIT (I2S_CFGR_DATLEN_0) /*!< Transfer data length is 24bits */ +#define I2S_DATA_LEN_32BIT (I2S_CFGR_DATLEN_1) /*!< Transfer data length is 32bits */ +/** + * @} + */ + +/** + * @defgroup I2S_MCK_Output I2S MCK Output + * @{ + */ +#define I2S_MCK_OUTPUT_DISABLE (0UL) /*!< Disable the drive clock(MCK) output */ +#define I2S_MCK_OUTPUT_ENABLE (I2S_CTRL_MCKOE) /*!< Enable the drive clock(MCK) output */ +/** + * @} + */ + +/** + * @defgroup I2S_Trans_Level I2S Transfer Level + * @{ + */ +#define I2S_TRANS_LVL0 (0x00UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 0 */ +#define I2S_TRANS_LVL1 (0x01UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 1 */ +#define I2S_TRANS_LVL2 (0x02UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 2 */ + +/** + * @} + */ + +/** + * @defgroup I2S_Receive_Level I2S Receive Level + * @{ + */ +#define I2S_RECEIVE_LVL0 (0x00UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 0 */ +#define I2S_RECEIVE_LVL1 (0x01UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 1 */ +#define I2S_RECEIVE_LVL2 (0x02UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 2 */ + +/** + * @} + */ + +/** + * @defgroup I2S_Com_Func I2S Communication Function + * @{ + */ +#define I2S_FUNC_TX (I2S_CTRL_TXE) /*!< Transfer function */ +#define I2S_FUNC_RX (I2S_CTRL_RXE) /*!< Receive function */ +#define I2S_FUNC_ALL (I2S_FUNC_TX | I2S_FUNC_RX) +/** + * @} + */ + +/** + * @defgroup I2S_Reset_Type I2S Reset Type + * @{ + */ +#define I2S_RST_TYPE_CODEC (I2S_CTRL_CODECRC) /*!< Reset codec of I2S */ +#define I2S_RST_TYPE_FIFO (I2S_CTRL_FIFOR) /*!< Reset FIFO of I2S */ + +#define I2S_RST_TYPE_ALL (I2S_RST_TYPE_CODEC | I2S_RST_TYPE_FIFO) +/** + * @} + */ + +/** + * @defgroup I2S_Interrupt I2S Interrupt + * @{ + */ +#define I2S_INT_TX (I2S_CTRL_TXIE) /*!< Transfer interrupt */ +#define I2S_INT_RX (I2S_CTRL_RXIE) /*!< Receive interrupt */ +#define I2S_INT_ERR (I2S_CTRL_EIE) /*!< Communication error interrupt */ +#define I2S_INT_ALL (I2S_INT_TX | I2S_INT_RX | I2S_INT_ERR) +/** + * @} + */ + +/** + * @defgroup I2S_Flag I2S Flag + * @{ + */ +#define I2S_FLAG_TX_ALARM (I2S_SR_TXBA) /*!< Transfer buffer alarm flag */ +#define I2S_FLAG_RX_ALARM (I2S_SR_RXBA) /*!< Receive buffer alarm flag */ +#define I2S_FLAG_TX_EMPTY (I2S_SR_TXBE) /*!< Transfer buffer empty flag */ +#define I2S_FLAG_TX_FULL (I2S_SR_TXBF) /*!< Transfer buffer full flag */ +#define I2S_FLAG_RX_EMPTY (I2S_SR_RXBE) /*!< Receive buffer empty flag */ +#define I2S_FLAG_RX_FULL (I2S_SR_RXBF) /*!< Receive buffer full flag */ +#define I2S_FLAG_TX_ERR (I2S_ER_TXERR << 16U) /*!< Transfer overflow or underflow flag */ +#define I2S_FLAG_RX_ERR (I2S_ER_RXERR << 16U) /*!< Receive overflow flag */ +#define I2S_FLAG_ALL (I2S_FLAG_TX_ALARM | I2S_FLAG_RX_ALARM | I2S_FLAG_TX_EMPTY | \ + I2S_FLAG_TX_FULL | I2S_FLAG_RX_EMPTY | I2S_FLAG_RX_FULL | \ + I2S_FLAG_TX_ERR | I2S_FLAG_RX_ERR) +#define I2S_FLAG_CLR_ALL (I2S_FLAG_TX_ERR | I2S_FLAG_RX_ERR) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup I2S_Global_Functions + * @{ + */ + +/* Initialization and configuration functions */ +void I2S_DeInit(CM_I2S_TypeDef *I2Sx); +int32_t I2S_Init(CM_I2S_TypeDef *I2Sx, const stc_i2s_init_t *pstcI2sInit); +int32_t I2S_StructInit(stc_i2s_init_t *pstcI2sInit); +void I2S_SWReset(CM_I2S_TypeDef *I2Sx, uint32_t u32Type); +void I2S_SetTransMode(CM_I2S_TypeDef *I2Sx, uint32_t u32Mode); +void I2S_SetTransFIFOLevel(CM_I2S_TypeDef *I2Sx, uint32_t u32Level); +void I2S_SetReceiveFIFOLevel(CM_I2S_TypeDef *I2Sx, uint32_t u32Level); +void I2S_SetProtocol(CM_I2S_TypeDef *I2Sx, uint32_t u32Protocol); +int32_t I2S_SetAudioFreq(CM_I2S_TypeDef *I2Sx, uint32_t u32Freq); +void I2S_MCKOutputCmd(CM_I2S_TypeDef *I2Sx, en_functional_state_t enNewState); +void I2S_FuncCmd(CM_I2S_TypeDef *I2Sx, uint32_t u32Func, en_functional_state_t enNewState); + +/* Transfer and receive data functions */ +void I2S_WriteData(CM_I2S_TypeDef *I2Sx, uint32_t u32Data); +uint32_t I2S_ReadData(const CM_I2S_TypeDef *I2Sx); +int32_t I2S_Trans(CM_I2S_TypeDef *I2Sx, const void *pvTxBuf, uint32_t u32Len, uint32_t u32Timeout); +int32_t I2S_Receive(const CM_I2S_TypeDef *I2Sx, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout); +int32_t I2S_TransReceive(CM_I2S_TypeDef *I2Sx, const void *pvTxBuf, + void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout); + +/* Interrupt and flag management functions */ +void I2S_IntCmd(CM_I2S_TypeDef *I2Sx, uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t I2S_GetStatus(const CM_I2S_TypeDef *I2Sx, uint32_t u32Flag); +void I2S_ClearStatus(CM_I2S_TypeDef *I2Sx, uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_I2S_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_I2S_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_icg.h b/mcu/lib/inc/hc32_ll_icg.h new file mode 100644 index 0000000..ebb3834 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_icg.h @@ -0,0 +1,469 @@ +/** + ******************************************************************************* + * @file hc32_ll_icg.h + * @brief This file contains all the Macro Definitions of the ICG driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_ICG_H__ +#define __HC32_LL_ICG_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_ICG + * @{ + */ + +#if (LL_ICG_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ICG_Global_Macros ICG Global Macros + * @{ + */ + +/** + * @defgroup ICG_SWDT_Reset_State ICG SWDT Reset State + * @{ + */ +#define ICG_SWDT_RST_START (0UL) /*!< SWDT auto start after reset */ +#define ICG_SWDT_RST_STOP (ICG_ICG0_SWDTAUTS) /*!< SWDT stop after reset */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_Exception_Type ICG SWDT Exception Type + * @{ + */ +#define ICG_SWDT_EXP_TYPE_INT (0UL) /*!< SWDT trigger interrupt */ +#define ICG_SWDT_EXP_TYPE_RST (ICG_ICG0_SWDTITS) /*!< SWDT trigger reset */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_Count_Period ICG SWDT Count Period + * @{ + */ +#define ICG_SWDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */ +#define ICG_SWDT_CNT_PERIOD4096 (ICG_ICG0_SWDTPERI_0) /*!< 4096 clock cycle */ +#define ICG_SWDT_CNT_PERIOD16384 (ICG_ICG0_SWDTPERI_1) /*!< 16384 clock cycle */ +#define ICG_SWDT_CNT_PERIOD65536 (ICG_ICG0_SWDTPERI) /*!< 65536 clock cycle */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_Clock_Division ICG SWDT Clock Division + * @{ + */ +#define ICG_SWDT_CLK_DIV1 (0UL) /*!< CLK */ +#define ICG_SWDT_CLK_DIV16 (0x04UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/16 */ +#define ICG_SWDT_CLK_DIV32 (0x05UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/32 */ +#define ICG_SWDT_CLK_DIV64 (0x06UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/64 */ +#define ICG_SWDT_CLK_DIV128 (0x07UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/128 */ +#define ICG_SWDT_CLK_DIV256 (0x08UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/256 */ +#define ICG_SWDT_CLK_DIV2048 (0x0BUL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/2048 */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_Refresh_Range ICG SWDT Refresh Range + * @{ + */ +#define ICG_SWDT_RANGE_0TO25PCT (0x01UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% */ +#define ICG_SWDT_RANGE_25TO50PCT (0x02UL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~50% */ +#define ICG_SWDT_RANGE_0TO50PCT (0x03UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~50% */ +#define ICG_SWDT_RANGE_50TO75PCT (0x04UL << ICG_ICG0_SWDTWDPT_POS) /*!< 50%~75% */ +#define ICG_SWDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 50%~75% */ +#define ICG_SWDT_RANGE_25TO75PCT (0x06UL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~75% */ +#define ICG_SWDT_RANGE_0TO75PCT (0x07UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~75% */ +#define ICG_SWDT_RANGE_75TO100PCT (0x08UL << ICG_ICG0_SWDTWDPT_POS) /*!< 75%~100% */ +#define ICG_SWDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 75%~100% */ +#define ICG_SWDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~50% & 75%~100% */ +#define ICG_SWDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~50% & 75%~100% */ +#define ICG_SWDT_RANGE_50TO100PCT (0x0CUL << ICG_ICG0_SWDTWDPT_POS) /*!< 50%~100% */ +#define ICG_SWDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 50%~100% */ +#define ICG_SWDT_RANGE_25TO100PCT (0x0EUL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~100% */ +#define ICG_SWDT_RANGE_0TO100PCT (0x0FUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~100% */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_LPM_Count ICG SWDT Low Power Mode Count + * @brief Counting control of SWDT in sleep/stop mode + * @{ + */ +#define ICG_SWDT_LPM_CNT_CONTINUE (0UL) /*!< Continue counting in sleep/stop mode */ +#define ICG_SWDT_LPM_CNT_STOP (ICG_ICG0_SWDTSLPOFF) /*!< Stop counting in sleep/stop mode */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Reset_State ICG WDT Reset State + * @{ + */ +#define ICG_WDT_RST_START (0UL) /*!< WDT auto start after reset */ +#define ICG_WDT_RST_STOP (ICG_ICG0_WDTAUTS) /*!< WDT stop after reset */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Exception_Type ICG WDT Exception Type + * @{ + */ +#define ICG_WDT_EXP_TYPE_INT (0UL) /*!< WDT trigger interrupt */ +#define ICG_WDT_EXP_TYPE_RST (ICG_ICG0_WDTITS) /*!< WDT trigger reset */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Count_Period ICG WDT Count Period + * @{ + */ +#define REDEF_ICG_WDTPERI_POS ICG_ICG0_WDTPERI_POS + +#define ICG_WDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */ +#define ICG_WDT_CNT_PERIOD4096 (0x01UL << REDEF_ICG_WDTPERI_POS) /*!< 4096 clock cycle */ +#define ICG_WDT_CNT_PERIOD16384 (0x02UL << REDEF_ICG_WDTPERI_POS) /*!< 16384 clock cycle */ +#define ICG_WDT_CNT_PERIOD65536 (0x03UL << REDEF_ICG_WDTPERI_POS) /*!< 65536 clock cycle */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Clock_Division ICG WDT Clock Division + * @{ + */ +#define REDEF_ICG_WDTCKS_POS ICG_ICG0_WDTCKS_POS + +#define ICG_WDT_CLK_DIV4 (0x02UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/4 */ +#define ICG_WDT_CLK_DIV64 (0x06UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/64 */ +#define ICG_WDT_CLK_DIV128 (0x07UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/128 */ +#define ICG_WDT_CLK_DIV256 (0x08UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/256 */ +#define ICG_WDT_CLK_DIV512 (0x09UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/512 */ +#define ICG_WDT_CLK_DIV1024 (0x0AUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/1024 */ +#define ICG_WDT_CLK_DIV2048 (0x0BUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/2048 */ +#define ICG_WDT_CLK_DIV8192 (0x0DUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/8192 */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Refresh_Range ICG WDT Refresh Range + * @{ + */ +#define REDEF_ICG_WDTWDPT_POS ICG_ICG0_WDTWDPT_POS + +#define ICG_WDT_RANGE_0TO25PCT (0x01UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% */ +#define ICG_WDT_RANGE_25TO50PCT (0x02UL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~50% */ +#define ICG_WDT_RANGE_0TO50PCT (0x03UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~50% */ +#define ICG_WDT_RANGE_50TO75PCT (0x04UL << REDEF_ICG_WDTWDPT_POS) /*!< 50%~75% */ +#define ICG_WDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 50%~75% */ +#define ICG_WDT_RANGE_25TO75PCT (0x06UL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~75% */ +#define ICG_WDT_RANGE_0TO75PCT (0x07UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~75% */ +#define ICG_WDT_RANGE_75TO100PCT (0x08UL << REDEF_ICG_WDTWDPT_POS) /*!< 75%~100% */ +#define ICG_WDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 75%~100% */ +#define ICG_WDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~50% & 75%~100% */ +#define ICG_WDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~50% & 75%~100% */ +#define ICG_WDT_RANGE_50TO100PCT (0x0CUL << REDEF_ICG_WDTWDPT_POS) /*!< 50%~100% */ +#define ICG_WDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 50%~100% */ +#define ICG_WDT_RANGE_25TO100PCT (0x0EUL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~100% */ +#define ICG_WDT_RANGE_0TO100PCT (0x0FUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~100% */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_LPM_Count ICG WDT Low Power Mode Count + * @brief Counting control of WDT in sleep mode + * @{ + */ +#define ICG_WDT_LPM_CNT_CONTINUE (0UL) /*!< Continue counting in sleep mode */ +#define ICG_WDT_LPM_CNT_STOP (ICG_ICG0_WDTSLPOFF) /*!< Stop counting in sleep mode */ +/** + * @} + */ + +/** + * @defgroup ICG_NMI_Pin_Filter_Clock_Division ICG NMI Pin Filter Clock Division + * @{ + */ +#define REDEF_ICG_NMIFCLK_POS ICG_ICG1_SMPCLK_POS + +#define ICG_NMI_PIN_FILTER_CLK_DIV1 (0UL) /*!< CLK */ +#define ICG_NMI_PIN_FILTER_CLK_DIV8 (0x01UL << REDEF_ICG_NMIFCLK_POS) /*!< CLK/8 */ +#define ICG_NMI_PIN_FILTER_CLK_DIV32 (0x02UL << REDEF_ICG_NMIFCLK_POS) /*!< CLK/32 */ +#define ICG_NMI_PIN_FILTER_CLK_DIV64 (0x03UL << REDEF_ICG_NMIFCLK_POS) /*!< CLK/64 */ +/** + * @} + */ + +/** + * @defgroup ICG_NMI_Pin_Filter ICG NMI Pin Filter + * @{ + */ +#define ICG_NMI_PIN_FILTER_DISABLE (0UL) /*!< Disable NMI Pin filter */ +#define ICG_NMI_PIN_FILTER_ENABLE (ICG_ICG1_NFEN) /*!< Enable NMI Pin filter */ +/** + * @} + */ + +/** + * @defgroup ICG_NMI_Pin_Trigger_Edge ICG NMI Pin Trigger Edge + * @{ + */ +#define ICG_NMI_PIN_TRIG_EDGE_FALLING (0UL) /*!< Falling edge trigger */ +#define ICG_NMI_PIN_TRIG_EDGE_RISING (ICG_ICG1_NMITRG) /*!< Rising edge trigger */ +/** + * @} + */ + +/** + * @defgroup ICG_NMI_Pin_Interrupt ICG NMI Pin Interrupt + * @{ + */ +#define ICG_NMI_PIN_INT_DISABLE (0UL) /*!< Disable NMI pin interrupt */ +#define ICG_NMI_PIN_INT_ENABLE (ICG_ICG1_NMIEN) /*!< Enable NMI pin interrupt */ +/** + * @} + */ + +/** + * @defgroup ICG_NMI_Pin_Reset_State ICG NMI Pin Reset State + * @{ + */ +#define ICG_NMI_PIN_RST_ENABLE (0UL) /*!< Enable NMI pin after reset */ +#define ICG_NMI_PIN_RST_DISABLE (ICG_ICG1_NMIICGEN) /*!< Disable NMI pin after reset */ +/** + * @} + */ + +/** + * @defgroup ICG_BOR_Voltage_Threshold ICG BOR Voltage Threshold + * @{ + */ +#define ICG_BOR_VOL_THRESHOLD_LVL0 (0UL) /*!< BOR voltage threshold 1.9V */ +#define ICG_BOR_VOL_THRESHOLD_LVL1 (ICG_ICG1_BOR_LEV_0) /*!< BOR voltage threshold 2.0V */ +#define ICG_BOR_VOL_THRESHOLD_LVL2 (ICG_ICG1_BOR_LEV_1) /*!< BOR voltage threshold 2.1V */ +#define ICG_BOR_VOL_THRESHOLD_LVL3 (ICG_ICG1_BOR_LEV) /*!< BOR voltage threshold 2.3V */ +/** + * @} + */ + +/** + * @defgroup ICG_BOR_Reset_State ICG BOR Reset State + * @{ + */ +#define ICG_BOR_RST_ENABLE (0UL) /*!< Enable BOR voltage detection after reset */ +#define ICG_BOR_RST_DISABLE (ICG_ICG1_BORDIS) /*!< Disable BOR voltage detection after reset */ +/** + * @} + */ + +/** + * @defgroup ICG_HRC_Frequency_Select ICG HRC Frequency Select + * @{ + */ + +#define ICG_HRC_20M (0UL) /*!< HRC = 20MHZ */ +#define ICG_HRC_16M (ICG_ICG1_HRCFREQSEL) /*!< HRC = 16MHZ */ +/** + * @} + */ + +/** + * @defgroup ICG_HRC_Reset_State ICG HRC Reset State + * @{ + */ +#define ICG_HRC_RST_OSCILLATION (0UL) /*!< HRC Oscillation after reset */ +#define ICG_HRC_RST_STOP (ICG_ICG1_HRCSTOP) /*!< HRC stop after reset */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup ICG_Register_Configuration ICG Register Configuration + * @{ + */ + +/** + * @defgroup ICG_SWDT_Preload_Configuration ICG SWDT Preload Configuration + * @{ + */ +/* SWDT register config */ +#define ICG_RB_SWDT_AUTS (ICG_SWDT_RST_START) +#define ICG_RB_SWDT_ITS (ICG_SWDT_EXP_TYPE_RST) +#define ICG_RB_SWDT_PERI (ICG_SWDT_CNT_PERIOD16384) +#define ICG_RB_SWDT_CKS (ICG_SWDT_CLK_DIV1) +#define ICG_RB_SWDT_WDPT (ICG_SWDT_RANGE_0TO100PCT) +#define ICG_RB_SWDT_SLTPOFF (ICG_SWDT_LPM_CNT_STOP) + +/* SWDT register value */ +#define ICG_REG_SWDT_CONFIG (ICG_RB_SWDT_AUTS | ICG_RB_SWDT_ITS | ICG_RB_SWDT_PERI | \ + ICG_RB_SWDT_CKS | ICG_RB_SWDT_WDPT | ICG_RB_SWDT_SLTPOFF) +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Preload_Configuration ICG WDT Preload Configuration + * @{ + */ +/* WDT register config */ +#define ICG_RB_WDT_AUTS (ICG_WDT_RST_STOP) +#define ICG_RB_WDT_ITS (ICG_WDT_EXP_TYPE_RST) +#define ICG_RB_WDT_PERI (ICG_WDT_CNT_PERIOD65536) +#define ICG_RB_WDT_CKS (ICG_WDT_CLK_DIV8192) +#define ICG_RB_WDT_WDPT (ICG_WDT_RANGE_0TO100PCT) +#define ICG_RB_WDT_SLTPOFF (ICG_WDT_LPM_CNT_STOP) + +/* WDT register value */ +#define ICG_REG_WDT_CONFIG (ICG_RB_WDT_AUTS | ICG_RB_WDT_ITS | ICG_RB_WDT_PERI | \ + ICG_RB_WDT_CKS | ICG_RB_WDT_WDPT | ICG_RB_WDT_SLTPOFF) +/** + * @} + */ + +/** + * @defgroup ICG_NMI_Pin_Preload_Configuration ICG NMI Pin Preload Configuration + * @{ + */ +/* NMI register config */ +#define ICG_RB_NMI_FCLK (ICG_NMI_PIN_FILTER_CLK_DIV64) +#define ICG_RB_NMI_FEN (ICG_NMI_PIN_FILTER_ENABLE) +#define ICG_RB_NMI_TRG (ICG_NMI_PIN_TRIG_EDGE_RISING) +#define ICG_RB_NMI_EN (ICG_NMI_PIN_INT_ENABLE) +#define ICG_RB_NMI_ICGEN (ICG_NMI_PIN_RST_DISABLE) + +/* NMI register value */ +#define ICG_REG_NMI_CONFIG (ICG_RB_NMI_FCLK | ICG_RB_NMI_FEN | ICG_RB_NMI_TRG | \ + ICG_RB_NMI_EN | ICG_RB_NMI_ICGEN) +/** + * @} + */ + +/** + * @defgroup ICG_BOR_Preload_Configuration ICG BOR Preload Configuration + * @{ + */ +/* BOR register config */ +#define ICG_RB_BOR_LEV (ICG_BOR_VOL_THRESHOLD_LVL3) +#define ICG_RB_BOR_DIS (ICG_BOR_RST_DISABLE) + +/* BOR register value */ +#define ICG_REG_BOR_CONFIG (ICG_RB_BOR_LEV | ICG_RB_BOR_DIS) +/** + * @} + */ + +/** + * @defgroup ICG_HRC_Preload_Configuration ICG HRC Preload Configuration + * @{ + */ +/* HRC register config */ +#define ICG_RB_HRC_FREQSEL (ICG_HRC_16M) +#define ICG_RB_HRC_STOP (ICG_HRC_RST_OSCILLATION) + +/* HRC register value */ +#define ICG_REG_HRC_CONFIG (ICG_RB_HRC_FREQSEL | ICG_RB_HRC_STOP) +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup ICG_Register_Value ICG Register Value + * @{ + */ +/* ICG register value */ +#ifndef ICG_REG_CFG0_CONST +#define ICG_REG_CFG0_CONST (ICG_REG_WDT_CONFIG | ICG_REG_SWDT_CONFIG | 0xE000E000UL) +#endif +#ifndef ICG_REG_CFG1_CONST +#define ICG_REG_CFG1_CONST (ICG_REG_NMI_CONFIG | ICG_REG_BOR_CONFIG | ICG_REG_HRC_CONFIG | 0x03F8FEFEUL) +#endif +/* ICG reserved value */ +#define ICG_REG_RESV_CONST (0xFFFFFFFFUL) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +#endif /* LL_ICG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_ICG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_interrupts.h b/mcu/lib/inc/hc32_ll_interrupts.h new file mode 100644 index 0000000..14cc0f5 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_interrupts.h @@ -0,0 +1,592 @@ +/** + ******************************************************************************* + * @file hc32_ll_interrupts.h + * @brief This file contains all the functions prototypes of the interrupt driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_INTERRUPTS_H__ +#define __HC32_LL_INTERRUPTS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_INTERRUPTS + * @{ + */ + +#if (LL_INTERRUPTS_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup INTC_Global_Types INTC Global Types + * @{ + */ + +/** + * @brief Interrupt registration structure definition + */ +typedef struct { + en_int_src_t enIntSrc; /*!< Peripheral interrupt number, can be any value @ref en_int_src_t */ + IRQn_Type enIRQn; /*!< Peripheral IRQ type, can be INT000_IRQn~INT127_IRQn @ref IRQn_Type */ + func_ptr_t pfnCallback; /*!< Callback function for corresponding peripheral IRQ */ +} stc_irq_signin_config_t; + +/** + * @brief NMI initialize configuration structure definition + */ +typedef struct { + uint32_t u32Src; /*!< NMI trigger source, @ref NMI_TriggerSrc_Sel for details */ + uint32_t u32Edge; /*!< NMI pin trigger edge, @ref NMI_Trigger_level_Sel for details */ + uint32_t u32Filter; /*!< NMI filter function setting, @ref NMI_FilterClock_Sel for details */ + uint32_t u32FilterClock; /*!< NMI filter clock division, @ref NMI_FilterClock_Div for details */ +} stc_nmi_init_t; + +/** + * @brief EXTINT initialize configuration structure definition + */ +typedef struct { + uint32_t u32Filter; /*!< ExtInt filter (A) function setting, @ref EXTINT_FilterClock_Sel for details */ + uint32_t u32FilterClock; /*!< ExtInt filter (A) clock division, @ref EXTINT_FilterClock_Div for details */ + uint32_t u32Edge; /*!< ExtInt trigger edge, @ref EXTINT_Trigger_Sel for details */ +} stc_extint_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup INTC_Global_Macros INTC Global Macros + * @{ + */ +/** + * @defgroup INTC_Priority_Sel Interrupt Priority Level 00 ~ 15 + * @{ + */ +#define DDL_IRQ_PRIO_00 (0U) +#define DDL_IRQ_PRIO_01 (1U) +#define DDL_IRQ_PRIO_02 (2U) +#define DDL_IRQ_PRIO_03 (3U) +#define DDL_IRQ_PRIO_04 (4U) +#define DDL_IRQ_PRIO_05 (5U) +#define DDL_IRQ_PRIO_06 (6U) +#define DDL_IRQ_PRIO_07 (7U) +#define DDL_IRQ_PRIO_08 (8U) +#define DDL_IRQ_PRIO_09 (9U) +#define DDL_IRQ_PRIO_10 (10U) +#define DDL_IRQ_PRIO_11 (11U) +#define DDL_IRQ_PRIO_12 (12U) +#define DDL_IRQ_PRIO_13 (13U) +#define DDL_IRQ_PRIO_14 (14U) +#define DDL_IRQ_PRIO_15 (15U) + +#define DDL_IRQ_PRIO_DEFAULT (DDL_IRQ_PRIO_15) + +/** + * @} + */ + +/** + * @defgroup NMI_TriggerSrc_Sel NMI Trigger Source Selection + * @{ + */ +#define NMI_SRC_PIN (INTC_NMIFR_NMIFR) +#define NMI_SRC_SWDT (INTC_NMIFR_SWDTFR) +#define NMI_SRC_LVD1 (INTC_NMIFR_PVD1FR) +#define NMI_SRC_LVD2 (INTC_NMIFR_PVD2FR) +#define NMI_SRC_XTAL (INTC_NMIFR_XTALSTPFR) +#define NMI_SRC_SRAM_PARITY (INTC_NMIFR_REPFR) +#define NMI_SRC_SRAM_ECC (INTC_NMIFR_RECCFR) +#define NMI_SRC_BUS_ERR (INTC_NMIFR_BUSMFR) +#define NMI_SRC_WDT (INTC_NMIFR_WDTFR) +#define NMI_SRC_ALL (NMI_SRC_PIN | NMI_SRC_SWDT | NMI_SRC_LVD1 | \ + NMI_SRC_LVD2 | NMI_SRC_XTAL | NMI_SRC_BUS_ERR | \ + NMI_SRC_SRAM_PARITY | NMI_SRC_WDT | NMI_SRC_SRAM_ECC) + +/** + * @} + */ + +/** + * @defgroup NMI_Trigger_level_Sel NMI Pin Trigger Edge Selection + * @{ + */ +#define NMI_TRIG_FALLING (0UL) +#define NMI_TRIG_RISING (INTC_NMICR_NMITRG) +/** + * @} + */ + +/** + * @defgroup NMI_FilterClock_Sel NMI Pin Filter Selection + * @{ + */ +#define NMI_FILTER_OFF (0UL) +#define NMI_FILTER_ON (INTC_NMICR_NFEN) +/** + * @} + */ + +/** + * @defgroup NMI_FilterClock_Div NMI Pin Filter Sampling Clock Division Selection + * @{ + */ +#define NMI_FCLK_DIV1 (0UL << INTC_NMICR_NSMPCLK_POS) +#define NMI_FCLK_DIV8 (1UL << INTC_NMICR_NSMPCLK_POS) +#define NMI_FCLK_DIV32 (2UL << INTC_NMICR_NSMPCLK_POS) +#define NMI_FCLK_DIV64 (3UL << INTC_NMICR_NSMPCLK_POS) +/** + * @} + */ + +/** + * @defgroup EXTINT_Channel_Sel External Interrupt Channel Selection + * @{ + */ +#define EXTINT_CH00 (1UL << 0U) +#define EXTINT_CH01 (1UL << 1U) +#define EXTINT_CH02 (1UL << 2U) +#define EXTINT_CH03 (1UL << 3U) +#define EXTINT_CH04 (1UL << 4U) +#define EXTINT_CH05 (1UL << 5U) +#define EXTINT_CH06 (1UL << 6U) +#define EXTINT_CH07 (1UL << 7U) +#define EXTINT_CH08 (1UL << 8U) +#define EXTINT_CH09 (1UL << 9U) +#define EXTINT_CH10 (1UL <<10U) +#define EXTINT_CH11 (1UL <<11U) +#define EXTINT_CH12 (1UL <<12U) +#define EXTINT_CH13 (1UL <<13U) +#define EXTINT_CH14 (1UL <<14U) +#define EXTINT_CH15 (1UL <<15U) +#define EXTINT_CH_ALL (EXTINT_CH00 | EXTINT_CH01 | EXTINT_CH02 | EXTINT_CH03 | \ + EXTINT_CH04 | EXTINT_CH05 | EXTINT_CH06 | EXTINT_CH07 | \ + EXTINT_CH08 | EXTINT_CH09 | EXTINT_CH10 | EXTINT_CH11 | \ + EXTINT_CH12 | EXTINT_CH13 | EXTINT_CH14 | EXTINT_CH15) +/** + * @} + */ + +/** + * @defgroup INT_Channel_Sel Interrupt Channel Selection + * @{ + */ +#define INTC_INT0 INTC_IER_IER0 +#define INTC_INT1 INTC_IER_IER1 +#define INTC_INT2 INTC_IER_IER2 +#define INTC_INT3 INTC_IER_IER3 +#define INTC_INT4 INTC_IER_IER4 +#define INTC_INT5 INTC_IER_IER5 +#define INTC_INT6 INTC_IER_IER6 +#define INTC_INT7 INTC_IER_IER7 +#define INTC_INT8 INTC_IER_IER8 +#define INTC_INT9 INTC_IER_IER9 +#define INTC_INT10 INTC_IER_IER10 +#define INTC_INT11 INTC_IER_IER11 +#define INTC_INT12 INTC_IER_IER12 +#define INTC_INT13 INTC_IER_IER13 +#define INTC_INT14 INTC_IER_IER14 +#define INTC_INT15 INTC_IER_IER15 +#define INTC_INT16 INTC_IER_IER16 +#define INTC_INT17 INTC_IER_IER17 +#define INTC_INT18 INTC_IER_IER18 +#define INTC_INT19 INTC_IER_IER19 +#define INTC_INT20 INTC_IER_IER20 +#define INTC_INT21 INTC_IER_IER21 +#define INTC_INT22 INTC_IER_IER22 +#define INTC_INT23 INTC_IER_IER23 +#define INTC_INT24 INTC_IER_IER24 +#define INTC_INT25 INTC_IER_IER25 +#define INTC_INT26 INTC_IER_IER26 +#define INTC_INT27 INTC_IER_IER27 +#define INTC_INT28 INTC_IER_IER28 +#define INTC_INT29 INTC_IER_IER29 +#define INTC_INT30 INTC_IER_IER30 +#define INTC_INT31 INTC_IER_IER31 +#define INTC_INT_ALL (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup INTC_Event_Channel_Sel Event Channel Selection + * @{ + */ +#define INTC_EVT0 INTC_EVTER_EVTE0 +#define INTC_EVT1 INTC_EVTER_EVTE1 +#define INTC_EVT2 INTC_EVTER_EVTE2 +#define INTC_EVT3 INTC_EVTER_EVTE3 +#define INTC_EVT4 INTC_EVTER_EVTE4 +#define INTC_EVT5 INTC_EVTER_EVTE5 +#define INTC_EVT6 INTC_EVTER_EVTE6 +#define INTC_EVT7 INTC_EVTER_EVTE7 +#define INTC_EVT8 INTC_EVTER_EVTE8 +#define INTC_EVT9 INTC_EVTER_EVTE9 +#define INTC_EVT10 INTC_EVTER_EVTE10 +#define INTC_EVT11 INTC_EVTER_EVTE11 +#define INTC_EVT12 INTC_EVTER_EVTE12 +#define INTC_EVT13 INTC_EVTER_EVTE13 +#define INTC_EVT14 INTC_EVTER_EVTE14 +#define INTC_EVT15 INTC_EVTER_EVTE15 +#define INTC_EVT16 INTC_EVTER_EVTE16 +#define INTC_EVT17 INTC_EVTER_EVTE17 +#define INTC_EVT18 INTC_EVTER_EVTE18 +#define INTC_EVT19 INTC_EVTER_EVTE19 +#define INTC_EVT20 INTC_EVTER_EVTE20 +#define INTC_EVT21 INTC_EVTER_EVTE21 +#define INTC_EVT22 INTC_EVTER_EVTE22 +#define INTC_EVT23 INTC_EVTER_EVTE23 +#define INTC_EVT24 INTC_EVTER_EVTE24 +#define INTC_EVT25 INTC_EVTER_EVTE25 +#define INTC_EVT26 INTC_EVTER_EVTE26 +#define INTC_EVT27 INTC_EVTER_EVTE27 +#define INTC_EVT28 INTC_EVTER_EVTE28 +#define INTC_EVT29 INTC_EVTER_EVTE29 +#define INTC_EVT30 INTC_EVTER_EVTE30 +#define INTC_EVT31 INTC_EVTER_EVTE31 +#define INTC_EVT_ALL (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup SWINT_Channel_Sel Software Interrupt Channel Selection + * @{ + */ +#define SWINT_CH00 INTC_SWIER_SWIE0 +#define SWINT_CH01 INTC_SWIER_SWIE1 +#define SWINT_CH02 INTC_SWIER_SWIE2 +#define SWINT_CH03 INTC_SWIER_SWIE3 +#define SWINT_CH04 INTC_SWIER_SWIE4 +#define SWINT_CH05 INTC_SWIER_SWIE5 +#define SWINT_CH06 INTC_SWIER_SWIE6 +#define SWINT_CH07 INTC_SWIER_SWIE7 +#define SWINT_CH08 INTC_SWIER_SWIE8 +#define SWINT_CH09 INTC_SWIER_SWIE9 +#define SWINT_CH10 INTC_SWIER_SWIE10 +#define SWINT_CH11 INTC_SWIER_SWIE11 +#define SWINT_CH12 INTC_SWIER_SWIE12 +#define SWINT_CH13 INTC_SWIER_SWIE13 +#define SWINT_CH14 INTC_SWIER_SWIE14 +#define SWINT_CH15 INTC_SWIER_SWIE15 +#define SWINT_CH16 INTC_SWIER_SWIE16 +#define SWINT_CH17 INTC_SWIER_SWIE17 +#define SWINT_CH18 INTC_SWIER_SWIE18 +#define SWINT_CH19 INTC_SWIER_SWIE19 +#define SWINT_CH20 INTC_SWIER_SWIE20 +#define SWINT_CH21 INTC_SWIER_SWIE21 +#define SWINT_CH22 INTC_SWIER_SWIE22 +#define SWINT_CH23 INTC_SWIER_SWIE23 +#define SWINT_CH24 INTC_SWIER_SWIE24 +#define SWINT_CH25 INTC_SWIER_SWIE25 +#define SWINT_CH26 INTC_SWIER_SWIE26 +#define SWINT_CH27 INTC_SWIER_SWIE27 +#define SWINT_CH28 INTC_SWIER_SWIE28 +#define SWINT_CH29 INTC_SWIER_SWIE29 +#define SWINT_CH30 INTC_SWIER_SWIE30 +#define SWINT_CH31 INTC_SWIER_SWIE31 +#define SWINT_ALL (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup EXTINT_FilterClock_Sel External Interrupt Filter A Function Selection + * @{ + */ +#define EXTINT_FILTER_OFF (0UL) +#define EXTINT_FILTER_ON INTC_EIRQCR_EFEN + +/** + * @} + */ + +/** + * @defgroup EXTINT_FilterClock_Div External Interrupt Filter A Sampling Clock Division Selection + * @{ + */ +#define EXTINT_FCLK_DIV1 (0UL) +#define EXTINT_FCLK_DIV8 (INTC_EIRQCR_EISMPCLK_0) +#define EXTINT_FCLK_DIV32 (INTC_EIRQCR_EISMPCLK_1) +#define EXTINT_FCLK_DIV64 (INTC_EIRQCR_EISMPCLK) + +/** + * @} + */ + +/** + * @defgroup EXTINT_Trigger_Sel External Interrupt Trigger Edge Selection + * @{ + */ +#define EXTINT_TRIG_FALLING (0UL) +#define EXTINT_TRIG_RISING INTC_EIRQCR_EIRQTRG_0 +#define EXTINT_TRIG_BOTH INTC_EIRQCR_EIRQTRG_1 +#define EXTINT_TRIG_LOW INTC_EIRQCR_EIRQTRG + +/** + * @} + */ + +/** + * @defgroup INTC_Stop_Wakeup_Source_Sel Stop Mode Wakeup Source Selection + * @{ + */ +#define INTC_STOP_WKUP_EXTINT_CH0 INTC_WUPEN_EIRQWUEN_0 +#define INTC_STOP_WKUP_EXTINT_CH1 INTC_WUPEN_EIRQWUEN_1 +#define INTC_STOP_WKUP_EXTINT_CH2 INTC_WUPEN_EIRQWUEN_2 +#define INTC_STOP_WKUP_EXTINT_CH3 INTC_WUPEN_EIRQWUEN_3 +#define INTC_STOP_WKUP_EXTINT_CH4 INTC_WUPEN_EIRQWUEN_4 +#define INTC_STOP_WKUP_EXTINT_CH5 INTC_WUPEN_EIRQWUEN_5 +#define INTC_STOP_WKUP_EXTINT_CH6 INTC_WUPEN_EIRQWUEN_6 +#define INTC_STOP_WKUP_EXTINT_CH7 INTC_WUPEN_EIRQWUEN_7 +#define INTC_STOP_WKUP_EXTINT_CH8 INTC_WUPEN_EIRQWUEN_8 +#define INTC_STOP_WKUP_EXTINT_CH9 INTC_WUPEN_EIRQWUEN_9 +#define INTC_STOP_WKUP_EXTINT_CH10 INTC_WUPEN_EIRQWUEN_10 +#define INTC_STOP_WKUP_EXTINT_CH11 INTC_WUPEN_EIRQWUEN_11 +#define INTC_STOP_WKUP_EXTINT_CH12 INTC_WUPEN_EIRQWUEN_12 +#define INTC_STOP_WKUP_EXTINT_CH13 INTC_WUPEN_EIRQWUEN_13 +#define INTC_STOP_WKUP_EXTINT_CH14 INTC_WUPEN_EIRQWUEN_14 +#define INTC_STOP_WKUP_EXTINT_CH15 INTC_WUPEN_EIRQWUEN_15 +#define INTC_STOP_WKUP_SWDT INTC_WUPEN_SWDTWUEN +#define INTC_STOP_WKUP_LVD1 INTC_WUPEN_PVD1WUEN +#define INTC_STOP_WKUP_LVD2 INTC_WUPEN_PVD2WUEN +#define INTC_STOP_WKUP_CMP INTC_WUPEN_CMPI0WUEN +#define INTC_STOP_WKUP_WKTM INTC_WUPEN_WKTMWUEN +#define INTC_STOP_WKUP_RTC_ALM INTC_WUPEN_RTCALMWUEN +#define INTC_STOP_WKUP_RTC_PRD INTC_WUPEN_RTCPRDWUEN +#define INTC_STOP_WKUP_TMR0_CMP INTC_WUPEN_TMR0WUEN +#define INTC_STOP_WKUP_USART1_RX INTC_WUPEN_RXWUEN +#define INTC_WUPEN_ALL (INTC_WUPEN_EIRQWUEN | INTC_WUPEN_SWDTWUEN | \ + INTC_WUPEN_PVD1WUEN | INTC_WUPEN_PVD2WUEN | \ + INTC_WUPEN_CMPI0WUEN | INTC_WUPEN_WKTMWUEN | \ + INTC_WUPEN_RTCALMWUEN | INTC_WUPEN_RTCPRDWUEN | \ + INTC_WUPEN_TMR0WUEN | INTC_WUPEN_RXWUEN) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup INTC_Global_Functions + * @{ + */ + +int32_t INTC_IrqSignIn(const stc_irq_signin_config_t *pstcIrqSignConfig); +int32_t INTC_IrqSignOut(IRQn_Type enIRQn); +void INTC_WakeupSrcCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewState); +void INTC_EventCmd(uint32_t u32Event, en_functional_state_t enNewState); +void INTC_IntCmd(uint32_t u32Int, en_functional_state_t enNewState); +void INTC_SWIntInit(uint32_t u32Ch, const func_ptr_t pfnCallback, uint32_t u32Priority); +void INTC_SWIntCmd(uint32_t u32SWInt, en_functional_state_t enNewState); + +int32_t NMI_Init(const stc_nmi_init_t *pstcNmiInit); +int32_t NMI_StructInit(stc_nmi_init_t *pstcNmiInit); +en_flag_status_t NMI_GetNmiStatus(uint32_t u32Src); +void NMI_NmiSrcCmd(uint32_t u32Src, en_functional_state_t enNewState); +void NMI_ClearNmiStatus(uint32_t u32Src); + +int32_t EXTINT_Init(uint32_t u32Ch, const stc_extint_init_t *pstcExtIntInit); +int32_t EXTINT_StructInit(stc_extint_init_t *pstcExtIntInit); +en_flag_status_t EXTINT_GetExtIntStatus(uint32_t u32ExtIntCh); +void EXTINT_ClearExtIntStatus(uint32_t u32ExtIntCh); + +void IRQ000_Handler(void); +void IRQ001_Handler(void); +void IRQ002_Handler(void); +void IRQ003_Handler(void); +void IRQ004_Handler(void); +void IRQ005_Handler(void); +void IRQ006_Handler(void); +void IRQ007_Handler(void); + +void IRQ008_Handler(void); +void IRQ009_Handler(void); +void IRQ010_Handler(void); +void IRQ011_Handler(void); +void IRQ012_Handler(void); +void IRQ013_Handler(void); +void IRQ014_Handler(void); +void IRQ015_Handler(void); + +void IRQ016_Handler(void); +void IRQ017_Handler(void); +void IRQ018_Handler(void); +void IRQ019_Handler(void); +void IRQ020_Handler(void); +void IRQ021_Handler(void); +void IRQ022_Handler(void); +void IRQ023_Handler(void); + +void IRQ024_Handler(void); +void IRQ025_Handler(void); +void IRQ026_Handler(void); +void IRQ027_Handler(void); +void IRQ028_Handler(void); +void IRQ029_Handler(void); +void IRQ030_Handler(void); +void IRQ031_Handler(void); +void IRQ032_Handler(void); +void IRQ033_Handler(void); +void IRQ034_Handler(void); +void IRQ035_Handler(void); +void IRQ036_Handler(void); +void IRQ037_Handler(void); +void IRQ038_Handler(void); +void IRQ039_Handler(void); +void IRQ040_Handler(void); +void IRQ041_Handler(void); +void IRQ042_Handler(void); +void IRQ043_Handler(void); +void IRQ044_Handler(void); +void IRQ045_Handler(void); +void IRQ046_Handler(void); +void IRQ047_Handler(void); +void IRQ048_Handler(void); +void IRQ049_Handler(void); +void IRQ050_Handler(void); +void IRQ051_Handler(void); +void IRQ052_Handler(void); +void IRQ053_Handler(void); +void IRQ054_Handler(void); +void IRQ055_Handler(void); +void IRQ056_Handler(void); +void IRQ057_Handler(void); +void IRQ058_Handler(void); +void IRQ059_Handler(void); +void IRQ060_Handler(void); +void IRQ061_Handler(void); +void IRQ062_Handler(void); +void IRQ063_Handler(void); +void IRQ064_Handler(void); +void IRQ065_Handler(void); +void IRQ066_Handler(void); +void IRQ067_Handler(void); +void IRQ068_Handler(void); +void IRQ069_Handler(void); +void IRQ070_Handler(void); +void IRQ071_Handler(void); +void IRQ072_Handler(void); +void IRQ073_Handler(void); +void IRQ074_Handler(void); +void IRQ075_Handler(void); +void IRQ076_Handler(void); +void IRQ077_Handler(void); +void IRQ078_Handler(void); +void IRQ079_Handler(void); +void IRQ080_Handler(void); +void IRQ081_Handler(void); +void IRQ082_Handler(void); +void IRQ083_Handler(void); +void IRQ084_Handler(void); +void IRQ085_Handler(void); +void IRQ086_Handler(void); +void IRQ087_Handler(void); +void IRQ088_Handler(void); +void IRQ089_Handler(void); +void IRQ090_Handler(void); +void IRQ091_Handler(void); +void IRQ092_Handler(void); +void IRQ093_Handler(void); +void IRQ094_Handler(void); +void IRQ095_Handler(void); +void IRQ096_Handler(void); +void IRQ097_Handler(void); +void IRQ098_Handler(void); +void IRQ099_Handler(void); +void IRQ100_Handler(void); +void IRQ101_Handler(void); +void IRQ102_Handler(void); +void IRQ103_Handler(void); +void IRQ104_Handler(void); +void IRQ105_Handler(void); +void IRQ106_Handler(void); +void IRQ107_Handler(void); +void IRQ108_Handler(void); +void IRQ109_Handler(void); +void IRQ110_Handler(void); +void IRQ111_Handler(void); +void IRQ112_Handler(void); +void IRQ113_Handler(void); +void IRQ114_Handler(void); +void IRQ115_Handler(void); +void IRQ116_Handler(void); +void IRQ117_Handler(void); +void IRQ118_Handler(void); +void IRQ119_Handler(void); +void IRQ120_Handler(void); +void IRQ121_Handler(void); +void IRQ122_Handler(void); +void IRQ123_Handler(void); +void IRQ124_Handler(void); +void IRQ125_Handler(void); +void IRQ126_Handler(void); +void IRQ127_Handler(void); + +/** + * @} + */ + +#endif /* LL_INTERRUPTS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_INTERRUPTS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_keyscan.h b/mcu/lib/inc/hc32_ll_keyscan.h new file mode 100644 index 0000000..e855e9b --- /dev/null +++ b/mcu/lib/inc/hc32_ll_keyscan.h @@ -0,0 +1,241 @@ +/** + ******************************************************************************* + * @file hc32_ll_keyscan.h + * @brief This file contains all the functions prototypes of the KEYSCAN driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-06-30 CDT Add function KEYSCAN_DeInit + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_KEYSCAN_H__ +#define __HC32_LL_KEYSCAN_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_KEYSCAN + * @{ + */ + +#if (LL_KEYSCAN_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup KEYSCAN_Global_Types KEYSCAN Global Types + * @{ + */ + +/** + * @brief KEYSCAN configuration + */ +typedef struct { + uint32_t u32HizCycle; /*!< Specifies the KEYSCAN Hiz cycles. + This parameter can be a value of @ref KEYSCAN_Hiz_Cycle_Sel */ + + uint32_t u32LowCycle; /*!< Specifies the KEYSCAN low cycles. + This parameter can be a value of @ref KEYSCAN_Low_Cycle_Sel */ + + uint32_t u32KeyClock; /*!< Specifies the KEYSCAN low cycles. + This parameter can be a value of @ref KEYSCAN_Clock_Sel */ + + uint32_t u32KeyOut; /*!< Specifies the KEYSCAN low cycles. + This parameter can be a value of @ref KEYSCAN_Keyout_Sel */ + + uint32_t u32KeyIn; /*!< Specifies the KEYSCAN low cycles. + This parameter can be a value of @ref KEYSCAN_Keyin_Sel */ +} stc_keyscan_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup KEYSCAN_Global_Macros KEYSCAN Global Macros + * @{ + */ + +/** + * @defgroup KEYSCAN_Hiz_Cycle_Sel KEYSCAN Hiz cycles during low ouput selection + * @{ + */ +#define KEYSCAN_HIZ_CYCLE_4 (0x00UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 4 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_8 (0x01UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 8 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_16 (0x02UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 16 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_32 (0x03UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 32 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_64 (0x04UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 64 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_256 (0x05UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 256 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_512 (0x06UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 512 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_1024 (0x07UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 1024 cycles during low ouput */ +/** + * @} + */ + +/** + * @defgroup KEYSCAN_Low_Cycle_Sel KEYSCAN low level output cycles selection + * @{ + */ +#define KEYSCAN_LOW_CYCLE_4 (0x02UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^2=4 cycles */ +#define KEYSCAN_LOW_CYCLE_8 (0x03UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^3=8 cycles */ +#define KEYSCAN_LOW_CYCLE_16 (0x04UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^4=16 cycles */ +#define KEYSCAN_LOW_CYCLE_32 (0x05UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^5=32 cycles */ +#define KEYSCAN_LOW_CYCLE_64 (0x06UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^6=64 cycles */ +#define KEYSCAN_LOW_CYCLE_128 (0x07UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^7=128 cycles */ +#define KEYSCAN_LOW_CYCLE_256 (0x08UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^8=256 cycles */ +#define KEYSCAN_LOW_CYCLE_512 (0x09UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^9=512 cycles */ +#define KEYSCAN_LOW_CYCLE_1K (0x0AUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^10=1K cycles */ +#define KEYSCAN_LOW_CYCLE_2K (0x0BUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^11=2K cycles */ +#define KEYSCAN_LOW_CYCLE_4K (0x0CUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^12=4K cycles */ +#define KEYSCAN_LOW_CYCLE_8K (0x0DUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^13=8K cycles */ +#define KEYSCAN_LOW_CYCLE_16K (0x0EUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^14=16K cycles */ +#define KEYSCAN_LOW_CYCLE_32K (0x0FUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^15=32K cycles */ +#define KEYSCAN_LOW_CYCLE_64K (0x10UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^16=64K cycles */ +#define KEYSCAN_LOW_CYCLE_128K (0x11UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^17=128K cycles */ +#define KEYSCAN_LOW_CYCLE_256K (0x12UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^18=256K cycles */ +#define KEYSCAN_LOW_CYCLE_512K (0x13UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^19=512K cycles */ +#define KEYSCAN_LOW_CYCLE_1M (0x14UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^20=1M cycles */ +#define KEYSCAN_LOW_CYCLE_2M (0x15UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^21=2M cycles */ +#define KEYSCAN_LOW_CYCLE_4M (0x16UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^22=4M cycles */ +#define KEYSCAN_LOW_CYCLE_8M (0x17UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^23=8M cycles */ +#define KEYSCAN_LOW_CYCLE_16M (0x18UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^24=16M cycles */ +/** + * @} + */ + +/** + * @defgroup KEYSCAN_Clock_Sel KEYSCAN scan clock selection + * @{ + */ +#define KEYSCAN_CLK_HCLK (0x00UL) /*!< Use as HCLK KEYSCAN clock */ +#define KEYSCAN_CLK_LRC (KEYSCAN_SCR_CKSEL_0) /*!< Use as LRC KEYSCAN clock */ +#define KEYSCAN_CLK_XTAL32 (KEYSCAN_SCR_CKSEL_1) /*!< Use as XTAL32 KEYSCAN clock */ +/** + * @} + */ + +/** + * @defgroup KEYSCAN_Keyout_Sel KEYSCAN keyout pins selection + * @{ + */ +#define KEYSCAN_OUT_0T1 (0x01UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 1 are selected */ +#define KEYSCAN_OUT_0T2 (0x02UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 2 are selected */ +#define KEYSCAN_OUT_0T3 (0x03UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 3 are selected */ +#define KEYSCAN_OUT_0T4 (0x04UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 4 are selected */ +#define KEYSCAN_OUT_0T5 (0x05UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 5 are selected */ +#define KEYSCAN_OUT_0T6 (0x06UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 6 are selected */ +#define KEYSCAN_OUT_0T7 (0x07UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 7 are selected */ +/** + * @} + */ + +/** + * @defgroup KEYSCAN_Keyin_Sel KEYSCAN keyin pins selection + * @{ + */ +#define KEYSCAN_IN_0 (1UL << 0U) /*!< KEYIN(EIRQ) 0 is selected */ +#define KEYSCAN_IN_1 (1UL << 1U) /*!< KEYIN(EIRQ) 1 is selected */ +#define KEYSCAN_IN_2 (1UL << 2U) /*!< KEYIN(EIRQ) 2 is selected */ +#define KEYSCAN_IN_3 (1UL << 3U) /*!< KEYIN(EIRQ) 3 is selected */ +#define KEYSCAN_IN_4 (1UL << 4U) /*!< KEYIN(EIRQ) 4 is selected */ +#define KEYSCAN_IN_5 (1UL << 5U) /*!< KEYIN(EIRQ) 5 is selected */ +#define KEYSCAN_IN_6 (1UL << 6U) /*!< KEYIN(EIRQ) 6 is selected */ +#define KEYSCAN_IN_7 (1UL << 7U) /*!< KEYIN(EIRQ) 7 is selected */ +#define KEYSCAN_IN_8 (1UL << 8U) /*!< KEYIN(EIRQ) 8 is selected */ +#define KEYSCAN_IN_9 (1UL << 9U) /*!< KEYIN(EIRQ) 9 is selected */ +#define KEYSCAN_IN_10 (1UL << 10U) /*!< KEYIN(EIRQ) 10 is selected */ +#define KEYSCAN_IN_11 (1UL << 11U) /*!< KEYIN(EIRQ) 11 is selected */ +#define KEYSCAN_IN_12 (1UL << 12U) /*!< KEYIN(EIRQ) 12 is selected */ +#define KEYSCAN_IN_13 (1UL << 13U) /*!< KEYIN(EIRQ) 13 is selected */ +#define KEYSCAN_IN_14 (1UL << 14U) /*!< KEYIN(EIRQ) 14 is selected */ +#define KEYSCAN_IN_15 (1UL << 15U) /*!< KEYIN(EIRQ) 15 is selected */ +#define KEYSCAN_IN_ALL (KEYSCAN_SCR_KEYINSEL) /*!< KEYIN(EIRQ) mask */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup KEYSCAN_Global_Functions + * @{ + */ +/** + * @brief Get KEYOUT index. + * @param None + * @retval uint32_t: KEYOUT index 0~7. + */ +__STATIC_INLINE uint32_t KEYSCAN_GetKeyoutIdx(void) +{ + return READ_REG32_BIT(CM_KEYSCAN->SSR, KEYSCAN_SSR_INDEX); +} + +int32_t KEYSCAN_StructInit(stc_keyscan_init_t *pstcKeyscanInit); +int32_t KEYSCAN_Init(const stc_keyscan_init_t *pstcKeyscanInit); +void KEYSCAN_Cmd(en_functional_state_t enNewState); +int32_t KEYSCAN_DeInit(void); + +/** + * @} + */ + +#endif /* LL_KEYSCAN_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_KEYSCAN_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_mpu.h b/mcu/lib/inc/hc32_ll_mpu.h new file mode 100644 index 0000000..780a2a8 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_mpu.h @@ -0,0 +1,384 @@ +/** + ******************************************************************************* + * @file hc32_ll_mpu.h + * @brief This file contains all the functions prototypes of the MPU driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_MPU_H__ +#define __HC32_LL_MPU_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_MPU + * @{ + */ + +#if (LL_MPU_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup MPU_Global_Types MPU Global Types + * @{ + */ + +/** + * @brief MPU Unit configure structure definition + */ +typedef struct { + uint32_t u32ExceptionType; /*!< Specifies the type of exception that occurs when the unit accesses a protected region. + This parameter can be a value of @ref MPU_Exception_Type */ + uint32_t u32BackgroundWrite; /*!< Specifies the unit's write permission for the background space. + This parameter can be a value of @ref MPU_Background_Write_Permission */ + uint32_t u32BackgroundRead; /*!< Specifies the unit's read permission for the background space + This parameter can be a value of @ref MPU_Background_Read_Permission */ +} stc_mpu_unit_config_t; + +/** + * @brief MPU Init structure definition + */ +typedef struct { + stc_mpu_unit_config_t stcDma1; /*!< Configure storage protection unit of DMA1 */ + stc_mpu_unit_config_t stcDma2; /*!< Configure storage protection unit of DMA2 */ + stc_mpu_unit_config_t stcUsbFSDma; /*!< Configure storage protection unit of USBFS_DMA */ +} stc_mpu_init_t; + +/** + * @brief MPU Region Permission structure definition + */ +typedef struct { + uint32_t u32RegionWrite; /*!< Specifies the unit's write permission for the region. + This parameter can be a value of @ref MPU_Region_Write_Permission */ + uint32_t u32RegionRead; /*!< Specifies the unit's read permission for the region. + This parameter can be a value of @ref MPU_Region_Read_Permission */ +} stc_mpu_region_permission_t; + +/** + * @brief MPU region initialization structure definition + * @note The effective bits of the 'u32BaseAddr' are related to the 'u32Size' of the region, + * and the low 'u32Size+1' bits are fixed at 0. + */ +typedef struct { + uint32_t u32BaseAddr; /*!< Specifies the base address of the region. + This parameter can be a number between 0UL and 0xFFFFFFE0UL */ + uint32_t u32Size; /*!< Specifies the size of the region. + This parameter can be a value of @ref MPU_Region_Size */ + stc_mpu_region_permission_t stcDma1; /*!< Specifies the DMA1 access permission for the region */ + stc_mpu_region_permission_t stcDma2; /*!< Specifies the DMA2 access permission for the region */ + stc_mpu_region_permission_t stcUsbFSDma; /*!< Specifies the USBFS_DMA access permission for the region */ +} stc_mpu_region_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup MPU_Global_Macros MPU Global Macros + * @{ + */ + +/** + * @defgroup MPU_Unit_Type MPU Unit Type + * @{ + */ +#define MPU_UNIT_DMA2 (0x01UL) /*!< System DMA_2 MPU */ +#define MPU_UNIT_DMA1 (0x02UL) /*!< System DMA_1 MPU */ +#define MPU_UNIT_USBFS_DMA (0x04UL) /*!< USBFS_DMA MPU */ +#define MPU_UNIT_ALL (MPU_UNIT_DMA2 | MPU_UNIT_DMA1 | MPU_UNIT_USBFS_DMA) +/** + * @} + */ + +/** + * @defgroup MPU_Region_Number MPU Region Number + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @{ + */ +#define MPU_REGION_NUM0 (0x00UL) /*!< MPU region number 0 */ +#define MPU_REGION_NUM1 (0x01UL) /*!< MPU region number 1 */ +#define MPU_REGION_NUM2 (0x02UL) /*!< MPU region number 2 */ +#define MPU_REGION_NUM3 (0x03UL) /*!< MPU region number 3 */ +#define MPU_REGION_NUM4 (0x04UL) /*!< MPU region number 4 */ +#define MPU_REGION_NUM5 (0x05UL) /*!< MPU region number 5 */ +#define MPU_REGION_NUM6 (0x06UL) /*!< MPU region number 6 */ +#define MPU_REGION_NUM7 (0x07UL) /*!< MPU region number 7 */ +#define MPU_REGION_NUM8 (0x08UL) /*!< MPU region number 8 */ +#define MPU_REGION_NUM9 (0x09UL) /*!< MPU region number 9 */ +#define MPU_REGION_NUM10 (0x0AUL) /*!< MPU region number 10 */ +#define MPU_REGION_NUM11 (0x0BUL) /*!< MPU region number 11 */ +#define MPU_REGION_NUM12 (0x0CUL) /*!< MPU region number 12 */ +#define MPU_REGION_NUM13 (0x0DUL) /*!< MPU region number 13 */ +#define MPU_REGION_NUM14 (0x0EUL) /*!< MPU region number 14 */ +#define MPU_REGION_NUM15 (0x0FUL) /*!< MPU region number 15 */ +/** + * @} + */ + +/** + * @defgroup MPU_Background_Write_Permission MPU Background Write Permission + * @{ + */ +#define MPU_BACKGROUND_WR_DISABLE (MPU_CR_SMPU2BWP) /*!< Disable write the background space */ +#define MPU_BACKGROUND_WR_ENABLE (0UL) /*!< Enable write the background space */ +/** + * @} + */ + +/** + * @defgroup MPU_Background_Read_Permission MPU Background Read Permission + * @{ + */ +#define MPU_BACKGROUND_RD_DISABLE (MPU_CR_SMPU2BRP) /*!< Disable read the background space */ +#define MPU_BACKGROUND_RD_ENABLE (0UL) /*!< Enable read the background space */ +/** + * @} + */ + +/** + * @defgroup MPU_Exception_Type MPU Exception Type + * @{ + */ +#define MPU_EXP_TYPE_NONE (0UL) /*!< The host unit access protection regions will be ignored */ +#define MPU_EXP_TYPE_BUS_ERR (MPU_CR_SMPU2ACT_0) /*!< The host unit access protection regions will be ignored and a bus error will be triggered */ +#define MPU_EXP_TYPE_NMI (MPU_CR_SMPU2ACT_1) /*!< The host unit access protection regions will be ignored and a NMI interrupt will be triggered */ +#define MPU_EXP_TYPE_RST (MPU_CR_SMPU2ACT) /*!< The host unit access protection regions will trigger the reset */ +/** + * @} + */ + +/** + * @defgroup MPU_Region_Write_Permission MPU Region Write Permission + * @{ + */ +#define MPU_REGION_WR_DISABLE (MPU_RGCR_S2RGWP) /*!< Disable write the region */ +#define MPU_REGION_WR_ENABLE (0UL) /*!< Enable write the region */ +/** + * @} + */ + +/** + * @defgroup MPU_Region_Read_Permission MPU Region Read Permission + * @{ + */ +#define MPU_REGION_RD_DISABLE (MPU_RGCR_S2RGRP) /*!< Disable read the region */ +#define MPU_REGION_RD_ENABLE (0UL) /*!< Enable read the region */ +/** + * @} + */ + +/** + * @defgroup MPU_Region_Size MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32BYTE (0x04UL) /*!< 32 Byte */ +#define MPU_REGION_SIZE_64BYTE (0x05UL) /*!< 64 Byte */ +#define MPU_REGION_SIZE_128BYTE (0x06UL) /*!< 126 Byte */ +#define MPU_REGION_SIZE_256BYTE (0x07UL) /*!< 256 Byte */ +#define MPU_REGION_SIZE_512BYTE (0x08UL) /*!< 512 Byte */ +#define MPU_REGION_SIZE_1KBYTE (0x09UL) /*!< 1K Byte */ +#define MPU_REGION_SIZE_2KBYTE (0x0AUL) /*!< 2K Byte */ +#define MPU_REGION_SIZE_4KBYTE (0x0BUL) /*!< 4K Byte */ +#define MPU_REGION_SIZE_8KBYTE (0x0CUL) /*!< 8K Byte */ +#define MPU_REGION_SIZE_16KBYTE (0x0DUL) /*!< 16K Byte */ +#define MPU_REGION_SIZE_32KBYTE (0x0EUL) /*!< 32K Byte */ +#define MPU_REGION_SIZE_64KBYTE (0x0FUL) /*!< 64K Byte */ +#define MPU_REGION_SIZE_128KBYTE (0x10UL) /*!< 128K Byte */ +#define MPU_REGION_SIZE_256KBYTE (0x11UL) /*!< 256K Byte */ +#define MPU_REGION_SIZE_512KBYTE (0x12UL) /*!< 512K Byte */ +#define MPU_REGION_SIZE_1MBYTE (0x13UL) /*!< 1M Byte */ +#define MPU_REGION_SIZE_2MBYTE (0x14UL) /*!< 2M Byte */ +#define MPU_REGION_SIZE_4MBYTE (0x15UL) /*!< 4M Byte */ +#define MPU_REGION_SIZE_8MBYTE (0x16UL) /*!< 8M Byte */ +#define MPU_REGION_SIZE_16MBYTE (0x17UL) /*!< 16M Byte */ +#define MPU_REGION_SIZE_32MBYTE (0x18UL) /*!< 32M Byte */ +#define MPU_REGION_SIZE_64MBYTE (0x19UL) /*!< 64M Byte */ +#define MPU_REGION_SIZE_128MBYTE (0x1AUL) /*!< 128M Byte */ +#define MPU_REGION_SIZE_256MBYTE (0x1BUL) /*!< 256M Byte */ +#define MPU_REGION_SIZE_512MBYTE (0x1CUL) /*!< 512M Byte */ +#define MPU_REGION_SIZE_1GBYTE (0x1DUL) /*!< 1G Byte */ +#define MPU_REGION_SIZE_2GBYTE (0x1EUL) /*!< 2G Byte */ +#define MPU_REGION_SIZE_4GBYTE (0x1FUL) /*!< 4G Byte */ +/** + * @} + */ + +/** + * @defgroup MPU_Flag MPU Flag + * @{ + */ +#define MPU_FLAG_SMPU1EAF (MPU_SR_SMPU1EAF) /*!< System DMA_1 error flag */ +#define MPU_FLAG_SMPU2EAF (MPU_SR_SMPU2EAF) /*!< System DMA_2 error flag */ +#define MPU_FLAG_FMPUEAF (MPU_SR_FMPUEAF) /*!< USBFS_DMA error flag */ + +#define MPU_FLAG_ALL (MPU_FLAG_SMPU1EAF | MPU_FLAG_SMPU2EAF | MPU_FLAG_FMPUEAF) +/** + * @} + */ + +/** + * @defgroup MPU_IP_Type MPU IP Type + * @note IP access protection is not available in privileged mode. + * @{ + */ +#define MPU_IP_AES (MPU_IPPR_AESRDP) /*!< AES module */ +#define MPU_IP_HASH (MPU_IPPR_HASHRDP) /*!< HASH module */ +#define MPU_IP_TRNG (MPU_IPPR_TRNGRDP) /*!< TRNG module */ +#define MPU_IP_CRC (MPU_IPPR_CRCRDP) /*!< CRC module */ +#define MPU_IP_EFM (MPU_IPPR_EFMRDP) /*!< EFM module */ +#define MPU_IP_WDT (MPU_IPPR_WDTRDP) /*!< WDT module */ +#define MPU_IP_SWDT (MPU_IPPR_SWDTRDP) /*!< SWDT module */ +#define MPU_IP_BKSRAM (MPU_IPPR_BKSRAMRDP) /*!< BKSRAM module */ +#define MPU_IP_RTC (MPU_IPPR_RTCRDP) /*!< RTC module */ +#define MPU_IP_MPU (MPU_IPPR_DMPURDP) /*!< MPU module */ +#define MPU_IP_SRAMC (MPU_IPPR_SRAMCRDP) /*!< SRAMC module */ +#define MPU_IP_INTC (MPU_IPPR_INTCRDP) /*!< INTC module */ +#define MPU_IP_RMU_CMU_PWC (MPU_IPPR_SYSCRDP) /*!< RMU, CMU and PWC modules */ +#define MPU_IP_FCG (MPU_IPPR_MSTPRDP) /*!< PWR_FCG0/1/2/3 and PWR_FCG0PC registers */ +#define MPU_IP_ALL (MPU_IP_AES | MPU_IP_HASH | MPU_IP_TRNG | MPU_IP_CRC | \ + MPU_IP_EFM | MPU_IP_WDT | MPU_IP_SWDT | MPU_IP_BKSRAM | \ + MPU_IP_RTC | MPU_IP_MPU | MPU_IP_SRAMC | MPU_IP_INTC | \ + MPU_IP_FCG | MPU_IP_RMU_CMU_PWC) +/** + * @} + */ + +/** + * @defgroup MPU_IP_Exception_Type MPU IP Exception Type + * @{ + */ +#define MPU_IP_EXP_TYPE_NONE (0UL) /*!< Access to the protected IP will be ignored */ +#define MPU_IP_EXP_TYPE_BUS_ERR (MPU_IPPR_BUSERRE) /*!< Access to the protected IP will trigger a bus error */ +/** + * @} + */ + +/** + * @defgroup MPU_Register_Protect_Key INTC Registers Protect Key + * @{ + */ +#define MPU_REG_LOCK_KEY (0x96A4UL) +#define MPU_REG_UNLOCK_KEY (0x96A5UL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup MPU_Global_Functions + * @{ + */ + +/** + * @brief MPU write protect unlock. + * @param None + * @retval None + */ +__STATIC_INLINE void MPU_REG_Unlock(void) +{ + WRITE_REG32(CM_MPU->WP, MPU_REG_UNLOCK_KEY); +} + +/** + * @brief MPU write protect lock. + * @param None + * @retval None + */ +__STATIC_INLINE void MPU_REG_Lock(void) +{ + WRITE_REG32(CM_MPU->WP, MPU_REG_LOCK_KEY); +} + +void MPU_REG_Unlock(void); +void MPU_REG_Lock(void); + +void MPU_DeInit(void); +int32_t MPU_Init(const stc_mpu_init_t *pstcMpuInit); +int32_t MPU_StructInit(stc_mpu_init_t *pstcMpuInit); +void MPU_SetExceptionType(uint32_t u32Unit, uint32_t u32Type); +void MPU_BackgroundWriteCmd(uint32_t u32Unit, en_functional_state_t enNewState); +void MPU_BackgroundReadCmd(uint32_t u32Unit, en_functional_state_t enNewState); +void MPU_UnitCmd(uint32_t u32Unit, en_functional_state_t enNewState); +en_flag_status_t MPU_GetStatus(uint32_t u32Flag); +void MPU_ClearStatus(uint32_t u32Flag); + +int32_t MPU_RegionInit(uint32_t u32Num, const stc_mpu_region_init_t *pstcRegionInit); +int32_t MPU_RegionStructInit(stc_mpu_region_init_t *pstcRegionInit); +void MPU_SetRegionBaseAddr(uint32_t u32Num, uint32_t u32Addr); +void MPU_SetRegionSize(uint32_t u32Num, uint32_t u32Size); +void MPU_RegionWriteCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState); +void MPU_RegionReadCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState); +void MPU_RegionCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState); + +void MPU_IP_SetExceptionType(uint32_t u32Type); +void MPU_IP_WriteCmd(uint32_t u32Periph, en_functional_state_t enNewState); +void MPU_IP_ReadCmd(uint32_t u32Periph, en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_MPU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_MPU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_ots.h b/mcu/lib/inc/hc32_ll_ots.h new file mode 100644 index 0000000..67cb047 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_ots.h @@ -0,0 +1,189 @@ +/** + ******************************************************************************* + * @file hc32_ll_ots.h + * @brief This file contains all the functions prototypes of the OTS driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-06-30 CDT Modify API OTS_DeInit() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_OTS_H__ +#define __HC32_LL_OTS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_OTS + * @{ + */ + +#if (LL_OTS_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup OTS_Global_Types OTS Global Types + * @{ + */ + +/** + * @brief OTS initialization structure. + */ +typedef struct { + uint16_t u16ClockSrc; /*!< Specifies clock source for OTS. + This parameter can be a value of @ref OTS_Clock_Source */ + uint16_t u16AutoOffEn; /*!< Enable or disable OTS automatic-off(after sampled temperature). + This parameter can be a value of @ref OTS_Auto_Off_En */ + float32_t f32SlopeK; /*!< K: Temperature slope (calculated by calibration experiment). + If you want to use the default parameters(slope K and offset M), + specify both 'f32SlopeK' and 'f32OffsetM' as ZERO. */ + float32_t f32OffsetM; /*!< M: Temperature offset (calculated by calibration experiment). + If you want to use the default parameters(slope K and offset M), + specify both 'f32SlopeK' and 'f32OffsetM' as ZERO. */ +} stc_ots_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup OTS_Global_Macros OTS Global Macros + * @{ + */ + +/** + * @defgroup OTS_Clock_Source OTS Clock Source + * @{ + */ +#define OTS_CLK_XTAL (0x0U) /*!< Select XTAL as OTS clock. */ +#define OTS_CLK_HRC (OTS_CTL_OTSCK) /*!< Select HRC as OTS clock */ +/** + * @} + */ + +/** + * @defgroup OTS_Auto_Off_En OTS Automatic Off Function Control + * @{ + */ +#define OTS_AUTO_OFF_DISABLE (0x0U) /*!< OTS automatically turned off when sampled done. */ +#define OTS_AUTO_OFF_ENABLE (OTS_CTL_TSSTP) /*!< OTS is still on when sampled done. */ +/** + * @} + */ + +/** + * @defgroup OTS_Param_Temp_Cond OTS Parameter Temperature Condition + * @{ + */ +#define OTS_PARAM_TEMP_COND_TN40 (0U) /*!< -40 degrees Celsius. */ +#define OTS_PARAM_TEMP_COND_T25 (1U) /*!< 25 degrees Celsius. */ +#define OTS_PARAM_TEMP_COND_T125 (2U) /*!< 125 degrees Celsius. */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup OTS_Global_Functions + * @{ + */ + +/** + * @brief Start OTS. + * @param None + * @retval None + */ +__STATIC_INLINE void OTS_Start(void) +{ + WRITE_REG32(bCM_OTS->CTL_b.OTSST, 1U); +} + +/** + * @brief Stop OTS. + * @param None + * @retval None + */ +__STATIC_INLINE void OTS_Stop(void) +{ + WRITE_REG32(bCM_OTS->CTL_b.OTSST, 0U); +} + +int32_t OTS_Init(const stc_ots_init_t *pstcOTSInit); +int32_t OTS_StructInit(stc_ots_init_t *pstcOTSInit); +int32_t OTS_DeInit(void); + +int32_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout); + +void OTS_IntCmd(en_functional_state_t enNewState); + +int32_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2, + uint16_t *pu16Ecr, float32_t *pf32A, + uint32_t u32Timeout); + +float32_t OTS_CalculateTemp(void); + +/** + * @} + */ + +#endif /* LL_OTS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_OTS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_pwc.h b/mcu/lib/inc/hc32_ll_pwc.h new file mode 100644 index 0000000..f77b9c1 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_pwc.h @@ -0,0 +1,634 @@ +/** + ******************************************************************************* + * @file hc32_ll_pwc.h + * @brief This file contains all the functions prototypes of the PWC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Refine API PWC_STOP_Enter() + 2023-06-30 CDT Modify group PWC_Stop_Type + 2023-09-30 CDT Add function PWC_LVD_DeInit + Modify the PWC_LVD_Detection_Voltage_Sel comment + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_PWC_H__ +#define __HC32_LL_PWC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_PWC + * @{ + */ + +#if (LL_PWC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup PWC_Global_Types PWC Global Types + * @{ + */ +/** + * @brief PWC LVD Init + */ +typedef struct { + uint32_t u32State; /*!< LVD function setting, @ref PWC_LVD_Config for details */ + uint32_t u32CompareOutputState; /*!< LVD compare output function setting, @ref PWC_LVD_CMP_Config for details */ + uint32_t u32ExceptionType; /*!< LVD interrupt or reset selection, @ref PWC_LVD_Exception_Type_Sel for details */ + uint32_t u32Filter; /*!< LVD digital filter function setting, @ref PWC_LVD_DF_Config for details */ + uint32_t u32FilterClock; /*!< LVD digital filter clock setting, @ref PWC_LVD_DFS_Clk_Sel for details */ + uint32_t u32ThresholdVoltage; /*!< LVD detect voltage setting, @ref PWC_LVD_Detection_Voltage_Sel for details */ +} stc_pwc_lvd_init_t; + +/** + * @brief PWC power down mode innit + */ +typedef struct { + uint8_t u8Mode; /*!< Power down mode, @ref PWC_PDMode_Sel for details. */ + uint8_t u8IOState; /*!< IO state in power down mode, @ref PWC_PDMode_IO_Sel for details. */ + uint8_t u8VcapCtrl; /*!< Power down Wakeup time control, @ref PWC_PD_VCAP_Sel for details. */ +} stc_pwc_pd_mode_config_t; + +/** + * @brief PWC Stop mode Init + */ +typedef struct { + uint16_t u16Clock; /*!< System clock setting after wake-up from stop mode, + @ref PWC_STOP_CLK_Sel for details. */ + uint8_t u8StopDrv; /*!< Stop mode drive capacity, + @ref PWC_STOP_DRV_Sel for details. */ + uint16_t u16FlashWait; /*!< Waiting flash stable after wake-up from stop mode, + @ref PWC_STOP_Flash_Wait_Sel for details. */ +} stc_pwc_stop_mode_config_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup PWC_Global_Macros PWC Global Macros + * @{ + */ + +/** + * @defgroup PWC_PDMode_Sel Power down mode selection + * @{ + */ +#define PWC_PD_MD1 (0x00U) /*!< Power down mode 1 */ +#define PWC_PD_MD2 (0x01U) /*!< Power down mode 2 */ +#define PWC_PD_MD3 (0x02U) /*!< Power down mode 3 */ +#define PWC_PD_MD4 (0x03U) /*!< Power down mode 4 */ +/** + * @} + */ + +/** + * @defgroup PWC_PDMode_IO_Sel IO state config in Power down mode + * @{ + */ +#define PWC_PD_IO_KEEP1 (0x00U) /*!< IO state retain in PD mode and configurable after wakeup */ +#define PWC_PD_IO_KEEP2 (PWC_PWRC0_IORTN_0) /*!< IO state retain in PD mode and configurable after wakeup & set IORTN[1:0]=00b */ +#define PWC_PD_IO_HIZ (PWC_PWRC0_IORTN_1) /*!< IO state switch to HiZ */ +/** + * @} + */ + +/** + * @defgroup PWC_PD_VCAP_Sel Wakeup speed config in Power down mode + * @{ + */ +#define PWC_PD_VCAP_0P1UF (0x00U) /*!< VCAP1/VCAP2 = 0.1uF x2 or 0.22uF x1 */ +#define PWC_PD_VCAP_0P047UF (0x01U) /*!< VCAP1/VCAP2 = 0.047uF x2 or 0.1uF x1 */ +/** + * @} + */ + +/** + * @defgroup PWC_STOP_DRV_Sel Drive capacity while enter stop mode + * @{ + */ +#define PWC_STOP_DRV_HIGH (0x00U) /*!< Enter stop mode from high speed mode */ +#define PWC_STOP_DRV_LOW (PWC_PWRC1_STPDAS) /*!< Enter stop mode from ultra low speed mode */ +/** + * @} + */ + +/** + * @defgroup PWC_STOP_CLK_Sel System clock setting after wake-up from stop mode + * @{ + */ +#define PWC_STOP_CLK_KEEP (0x00U) /*!< Keep System clock setting after wake-up from stop mode */ +#define PWC_STOP_CLK_MRC (PWC_STPMCR_CKSMRC) /*!< System clock switch to MRC after wake-up from stop mode */ + +/** + * @} + */ + +/** + * @defgroup PWC_STOP_Flash_Wait_Sel Whether wait flash stable or not after wake-up from stop mode + * @{ + */ +#define PWC_STOP_FLASH_WAIT_ON (0x00U) /*!< Wait flash stable after wake-up from stop mode */ +#define PWC_STOP_FLASH_WAIT_OFF (PWC_STPMCR_FLNWT) /*!< Don't wait flash stable after wake-up from stop mode */ +/** + * @} + */ + +/** + * @defgroup PWC_Stop_Type PWC stop mode type. + * @{ + */ +#define PWC_STOP_WFI (0x00U) /*!< Enter stop mode by WFI, and wake-up by interrupt handle. */ +#define PWC_STOP_WFE_INT (0x01U) /*!< Enter stop mode by WFE, and wake-up by interrupt request. */ +#define PWC_STOP_WFE_EVT (0x02U) /*!< Enter stop mode by WFE, and wake-up by event. */ +/** + * @} + */ + +/** + * @defgroup PWC_RAM_Config Operating mode for RAM Config + * @{ + */ +#define PWC_RAM_HIGH_SPEED (0x8043U) /*!< MCU operating under high frequency (lower than 240MHz) */ +#define PWC_RAM_ULOW_SPEED (0x9062U) /*!< MCU operating under ultra low frequency (lower than 8MHz) */ +/** + * @} + */ + +/** + * @defgroup PWC_PD_Periph_Ram Peripheral ram to power down + * @{ + */ +#define PWC_RAM_PD_SRAM1 (PWC_RAMPC0_RAMPDC0) +#define PWC_RAM_PD_SRAM2 (PWC_RAMPC0_RAMPDC1) +#define PWC_RAM_PD_SRAM3 (PWC_RAMPC0_RAMPDC2) +#define PWC_RAM_PD_SRAMH (PWC_RAMPC0_RAMPDC3) +#define PWC_RAM_PD_USBFS (PWC_RAMPC0_RAMPDC4) +#define PWC_RAM_PD_SDIO0 (PWC_RAMPC0_RAMPDC5) +#define PWC_RAM_PD_SDIO1 (PWC_RAMPC0_RAMPDC6) +#define PWC_RAM_PD_CACHE (PWC_RAMPC0_RAMPDC8) +#define PWC_RAM_PD_CAN (PWC_RAMPC0_RAMPDC7) +#define PWC_RAM_PD_ALL (0x1FFU) + +/** + * @} + */ + +/** + * @defgroup PWC_LVD_Channel PWC LVD channel + * @{ + */ +#define PWC_LVD_CH1 (0x00U) +#define PWC_LVD_CH2 (0x01U) + +/** + * @} + */ + +/** + * @defgroup PWC_LVD_Config PWC LVD Config + * @{ + */ +#define PWC_LVD_ON (PWC_PVDCR0_PVD1EN) +#define PWC_LVD_OFF (0x00U) +/** + * @} + */ + +/** + * @defgroup PWC_LVD_Exception_Type_Sel PWC LVD Exception Type Select + * @{ + */ +#define PWC_LVD_EXP_TYPE_NONE (0x00U) +#define PWC_LVD_EXP_TYPE_INT (0x0101U) +#define PWC_LVD_EXP_TYPE_NMI (0x0001U) +#define PWC_LVD_EXP_TYPE_RST (PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS) + +/** + * @} + */ + +/** + * @defgroup PWC_LVD_CMP_Config PWC LVD Compare Config + * @{ + */ +#define PWC_LVD_CMP_OFF (0x00U) +#define PWC_LVD_CMP_ON (PWC_PVDCR1_PVD1CMPOE) +/** + * @} + */ + +/** + * @defgroup PWC_LVD_DF_Config LVD digital filter ON or OFF + * @{ + */ +#define PWC_LVD_FILTER_ON (0x00U) +#define PWC_LVD_FILTER_OFF (0x01U) +/** + * @} + */ + +/** + * @defgroup PWC_LVD_DFS_Clk_Sel LVD digital filter sample ability + * @note modified this value must when PWC_LVD_FILTER_OFF + * @{ + */ +#define PWC_LVD_FILTER_LRC_DIV4 (0x00UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 0.25 LRC cycle */ +#define PWC_LVD_FILTER_LRC_DIV2 (0x01UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 0.5 LRC cycle */ +#define PWC_LVD_FILTER_LRC_DIV1 (0x02UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 1 LRC cycle */ +#define PWC_LVD_FILTER_LRC_MUL2 (0x03UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 2 LRC cycles */ + +/** + * @} + */ + +/** + * @defgroup PWC_LVD_Detection_Voltage_Sel PWC LVD Detection voltage + * @{ + * @note + * @verbatim + * | LVL0 | LVL1 | LVL2 | LVL3 | LVL4 | LVL5 | LVL6 | LVL7 | EXVCC | + * LVD1 | 2.00V | 2.10V | 2.30V | 2.55V | 2.65V | 2.75V | 2.85V | 2.95V | -- | + * LVD2 | 2.10V | 2.30V | 2.55V | 2.65V | 2.75V | 2.85V | 2.95V | 1.10V | EXVCC | + * @endverbatim + */ +#define PWC_LVD_THRESHOLD_LVL0 (0x00U) +#define PWC_LVD_THRESHOLD_LVL1 (0x01U) +#define PWC_LVD_THRESHOLD_LVL2 (0x02U) +#define PWC_LVD_THRESHOLD_LVL3 (0x03U) +#define PWC_LVD_THRESHOLD_LVL4 (0x04U) +#define PWC_LVD_THRESHOLD_LVL5 (0x05U) +#define PWC_LVD_THRESHOLD_LVL6 (0x06U) +#define PWC_LVD_THRESHOLD_LVL7 (0x07U) +#define PWC_LVD_EXTVCC (0x07U) + +/** + * @} + */ + +/** + * @defgroup PWC_LVD_Flag LVD flag + * @{ + */ +#define PWC_LVD1_FLAG_DETECT (PWC_PVDDSR_PVD1DETFLG) /*!< VCC across VLVD1 */ +#define PWC_LVD2_FLAG_DETECT (PWC_PVDDSR_PVD2DETFLG) /*!< VCC across VLVD2 */ +#define PWC_LVD1_FLAG_MON (PWC_PVDDSR_PVD1MON) /*!< VCC > VLVD1 */ +#define PWC_LVD2_FLAG_MON (PWC_PVDDSR_PVD2MON) /*!< VCC > VLVD2 */ + +/** + * @} + */ + +/** + * @defgroup PWC_WKUP_Event_Sel Power down mode wakeup event selection + * @{ + */ +#define PWC_PD_WKUP0_POS (0U) +#define PWC_PD_WKUP1_POS (8U) +#define PWC_PD_WKUP2_POS (16U) +#define PWC_PD_WKUP_WKUP00 (PWC_PDWKE0_WKE00 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP01 (PWC_PDWKE0_WKE01 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP02 (PWC_PDWKE0_WKE02 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP03 (PWC_PDWKE0_WKE03 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP10 (PWC_PDWKE0_WKE10 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP11 (PWC_PDWKE0_WKE11 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP12 (PWC_PDWKE0_WKE12 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP13 (PWC_PDWKE0_WKE13 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP20 (PWC_PDWKE1_WKE20 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP21 (PWC_PDWKE1_WKE21 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP22 (PWC_PDWKE1_WKE22 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP23 (PWC_PDWKE1_WKE23 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP30 (PWC_PDWKE1_WKE30 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP31 (PWC_PDWKE1_WKE31 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP32 (PWC_PDWKE1_WKE32 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP33 (PWC_PDWKE1_WKE33 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_LVD1 (PWC_PDWKE2_VD1WKE << PWC_PD_WKUP2_POS) +#define PWC_PD_WKUP_LVD2 (PWC_PDWKE2_VD2WKE << PWC_PD_WKUP2_POS) +#define PWC_PD_WKUP_NMI (PWC_PDWKE2_NMIWKE << PWC_PD_WKUP2_POS) +#define PWC_PD_WKUP_RTCPRD (PWC_PDWKE2_RTCPRDWKE << PWC_PD_WKUP2_POS) +#define PWC_PD_WKUP_RTCALM (PWC_PDWKE2_RTCALMWKE << PWC_PD_WKUP2_POS) +#define PWC_PD_WKUP_WKTM (PWC_PDWKE2_WKTMWKE << PWC_PD_WKUP2_POS) +/** + * @} + */ + +/** + * @defgroup PWC_WKUP_Trigger_Event_Sel Power down mode wakeup event selection to set trigger edge. + * @{ + */ +#define PWC_PD_WKUP_TRIG_LVD1 (PWC_PDWKES_VD1EGS) +#define PWC_PD_WKUP_TRIG_LVD2 (PWC_PDWKES_VD2EGS) +#define PWC_PD_WKUP_TRIG_WKUP0 (PWC_PDWKES_WK0EGS) +#define PWC_PD_WKUP_TRIG_WKUP1 (PWC_PDWKES_WK1EGS) +#define PWC_PD_WKUP_TRIG_WKUP2 (PWC_PDWKES_WK2EGS) +#define PWC_PD_WKUP_TRIG_WKUP3 (PWC_PDWKES_WK3EGS) + +#define PWC_PD_WKUP_TRIG_NMI (PWC_PDWKES_NMIEGS) +#define PWC_PD_WKUP_TRIG_ALL (PWC_PD_WKUP_TRIG_LVD1 | PWC_PD_WKUP_TRIG_LVD2 | PWC_PD_WKUP_TRIG_WKUP0 | \ + PWC_PD_WKUP_TRIG_WKUP1 | PWC_PD_WKUP_TRIG_WKUP2 | PWC_PD_WKUP_TRIG_WKUP3 | \ + PWC_PD_WKUP_TRIG_NMI) +/** + * @} + */ + +/** + * @defgroup PWC_WKUP_Trigger_Edge_Sel Power down mode wakeup trigger edge selection + * @{ + */ +#define PWC_PD_WKUP_TRIG_FALLING (0x00U) +#define PWC_PD_WKUP_TRIG_RISING (0x01U) +/** + * @} + */ + +/** + * @defgroup PWC_WKUP_Event_Flag_Sel Power down mode wakeup Event status selection + * @{ + */ +#define PWC_PD_WKUP_FLAG0_POS (0U) +#define PWC_PD_WKUP_FLAG1_POS (8U) +#define PWC_PD_WKUP_FLAG_WKUP0 (PWC_PDWKF0_PTWK0F << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_WKUP1 (PWC_PDWKF0_PTWK1F << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_WKUP2 (PWC_PDWKF0_PTWK2F << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_WKUP3 (PWC_PDWKF0_PTWK3F << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_LVD1 (PWC_PDWKF0_VD1WKF << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_LVD2 (PWC_PDWKF0_VD2WKF << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_NMI (PWC_PDWKF0_NMIWKF << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_RTCPRD (PWC_PDWKF1_RTCPRDWKF << PWC_PD_WKUP_FLAG1_POS) +#define PWC_PD_WKUP_FLAG_RTCALM (PWC_PDWKF1_RTCALMWKF << PWC_PD_WKUP_FLAG1_POS) +#define PWC_PD_WKUP_FLAG_WKTM (PWC_PDWKF1_WKTMWKF << PWC_PD_WKUP_FLAG1_POS) + +#define PWC_PD_WKUP_FLAG_ALL (PWC_PD_WKUP_FLAG_WKUP0 | PWC_PD_WKUP_FLAG_WKUP1 | PWC_PD_WKUP_FLAG_WKUP2 | \ + PWC_PD_WKUP_FLAG_WKUP3 | PWC_PD_WKUP_FLAG_LVD1 | PWC_PD_WKUP_FLAG_LVD2 | \ + PWC_PD_WKUP_FLAG_NMI | PWC_PD_WKUP_FLAG_RTCPRD | PWC_PD_WKUP_FLAG_RTCALM | \ + PWC_PD_WKUP_FLAG_WKTM) +/** + * @} + */ + +/** + * @defgroup PWC_Monitor_Power PWC Power Monitor voltage definition + * @{ + */ +#define PWC_PWR_MON_IREF (0x00U) /*!< Internal reference voltage */ +/** + * @} + */ + +/** + * @defgroup PWC_WKT_State PWC WKT State + * @{ + */ +#define PWC_WKT_OFF (0x00U) +#define PWC_WKT_ON (PWC_WKTCR_WKTCE) +/** + * @} + */ + +/** + * @defgroup PWC_WKT_Clock_Source PWC WKT Clock Source + * @{ + */ +#define PWC_WKT_CLK_SRC_64HZ ((0x00U << PWC_WKTCR_WKCKS_POS)) /*!< 64Hz Clock */ +#define PWC_WKT_CLK_SRC_XTAL32 ((0x01U << PWC_WKTCR_WKCKS_POS)) /*!< XTAL32 Clock */ +#define PWC_WKT_CLK_SRC_LRC ((0x02U << PWC_WKTCR_WKCKS_POS)) /*!< LRC Clock */ + +/** + * @} + */ + +/** + * @defgroup PWC_Ldo_Sel PWC LDO Selection + * @{ + */ +#define PWC_LDO_HRC (PWC_PWRC1_VHRCSD) +#define PWC_LDO_PLL (PWC_PWRC1_VPLLSD) +#define PWC_LDO_MASK (PWC_LDO_HRC | PWC_LDO_PLL) +/** + * @} + */ + +/** + * @defgroup PWC_REG_Write_Unlock_Code PWC register unlock code. + * @brief Lock/unlock Code for each module + * PWC_UNLOCK_CODE0: + * Below registers are locked in CLK module. + * XTALCFGR, XTALSTBCR, XTALCR, XTALSTDCR, XTALSTDSR, HRCTRM, HRCCR, + * MRCTRM, MRCCR, PLLCFGR, PLLCR, UPLLCFGR, UPLLCR, OSCSTBSR, CKSWR, + * SCFGR, USBCKCFGR, TPIUCKCFGR, MCO1CFGR, MCO2CFGR, XTAL32CR, + * XTALC32CFGR, XTAL32NFR, LRCCR, LRCTRM. + * PWC_UNLOCK_CODE1: + * Below registers are locked in PWC module. + * PWRC0, PWRC1, PWRC2, PWRC3, PDWKE0, PDWKE1, PDWKE2, PDWKES, PDWKF0, + * PDWKF1, PWCMR, PWR_STPMCR, RAMPC0, RAMOPM. + * Below registers are locked in CLK module. + * PERICKSEL, I2SCKSEL, + * Below register is locked in RMU module. + * RSTF0 + * PWC_UNLOCK_CODE2: + * Below registers are locked in PWC module. + * PVDCR0, PVDCR1, PVDFCR, PVDLCR, PVDICR, PVDDSR + * @{ + */ +#define PWC_WRITE_ENABLE (0xA500U) +#define PWC_UNLOCK_CODE0 (0xA501U) +#define PWC_UNLOCK_CODE1 (0xA502U) +#define PWC_UNLOCK_CODE2 (0xA508U) + +/** + * @brief PWC FCG0 Unlock/Lock code + */ +#define PWC_FCG0_REG_UNLOCK_KEY (0xA5A50001UL) +#define PWC_FCG0_REG_LOCK_KEY (0xA5A50000UL) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup PWC_Global_Functions + * @{ + */ +/** + * @brief Lock PWC, CLK, RMU register. + * @param [in] u16Module Lock code for each module. + * @arg PWC_UNLOCK_CODE0 + * @arg PWC_UNLOCK_CODE1 + * @arg PWC_UNLOCK_CODE2 + * @retval None + */ +__STATIC_INLINE void PWC_REG_Lock(uint16_t u16Module) +{ + CM_PWC->FPRC = (PWC_WRITE_ENABLE | (uint16_t)((uint16_t)(~u16Module) & (CM_PWC->FPRC))); +} + +/** + * @brief Unlock PWC, CLK, RMU register. + * @param [in] u16Module Unlock code for each module. + * @arg PWC_UNLOCK_CODE0 + * @arg PWC_UNLOCK_CODE1 + * @arg PWC_UNLOCK_CODE2 + * @retval None + */ +__STATIC_INLINE void PWC_REG_Unlock(uint16_t u16Module) +{ + SET_REG16_BIT(CM_PWC->FPRC, u16Module); +} + +/** + * @brief Lock PWC_FCG0 register . + * @param None + * @retval None + */ +__STATIC_INLINE void PWC_FCG0_REG_Lock(void) +{ + WRITE_REG32(CM_PWC->FCG0PC, PWC_FCG0_REG_LOCK_KEY); +} + +/** + * @brief Unlock PWR_FCG0 register. + * @param None + * @retval None + * @note Call this function before FCG_Fcg0PeriphClockCmd() + */ +__STATIC_INLINE void PWC_FCG0_REG_Unlock(void) +{ + WRITE_REG32(CM_PWC->FCG0PC, PWC_FCG0_REG_UNLOCK_KEY); +} + +/* PWC PD Function */ +void PWC_PD_Enter(void); +int32_t PWC_PD_StructInit(stc_pwc_pd_mode_config_t *pstcPDModeConfig); +int32_t PWC_PD_Config(const stc_pwc_pd_mode_config_t *pstcPDModeConfig); +void PWC_PD_WakeupCmd(uint32_t u32Event, en_functional_state_t enNewState); +void PWC_PD_SetWakeupTriggerEdge(uint8_t u8Event, uint8_t u8TrigEdge); +en_flag_status_t PWC_PD_GetWakeupStatus(uint16_t u16Flag); +void PWC_PD_ClearWakeupStatus(uint16_t u16Flag); +void PWC_PD_PeriphRamCmd(uint32_t u32PeriphRam, en_functional_state_t enNewState); +void PWC_PD_VdrCmd(en_functional_state_t enNewState); + +/* PWC WKTM Function */ +void PWC_WKT_Config(uint16_t u16ClkSrc, uint16_t u16CmpVal); +void PWC_WKT_SetCompareValue(uint16_t u16CmpVal); +uint16_t PWC_WKT_GetCompareValue(void); +void PWC_WKT_Cmd(en_functional_state_t enNewState); +en_flag_status_t PWC_WKT_GetStatus(void); +void PWC_WKT_ClearStatus(void); + +void PWC_RamModeConfig(uint16_t u16Mode); + +/* PWC Sleep Function */ +void PWC_SLEEP_Enter(void); + +/* PWC Stop Function */ +void PWC_STOP_Enter(uint8_t u8StopType); +int32_t PWC_STOP_StructInit(stc_pwc_stop_mode_config_t *pstcStopConfig); +int32_t PWC_STOP_Config(const stc_pwc_stop_mode_config_t *pstcStopConfig); +void PWC_STOP_ClockSelect(uint8_t u8Clock); +void PWC_STOP_NvicBackup(void); +void PWC_STOP_NvicRecover(void); +void PWC_STOP_ClockBackup(void); +void PWC_STOP_ClockRecover(void); +void PWC_STOP_IrqClockBackup(void); +void PWC_STOP_IrqClockRecover(void); +void PWC_STOP_SetDrv(uint8_t u8StopDrv); +void PWC_STOP_FlashWaitCmd(en_functional_state_t enNewState); + +/* PWC Speed Switch Function */ +int32_t PWC_HighSpeedToLowSpeed(void); +int32_t PWC_LowSpeedToHighSpeed(void); +int32_t PWC_HighSpeedToHighPerformance(void); +int32_t PWC_HighPerformanceToHighSpeed(void); +int32_t PWC_LowSpeedToHighPerformance(void); +int32_t PWC_HighPerformanceToLowSpeed(void); + +/* PWC LDO Function */ +void PWC_LDO_Cmd(uint16_t u16Ldo, en_functional_state_t enNewState); + +/* PWC LVD/PVD Function */ +int32_t PWC_LVD_Init(uint8_t u8Ch, const stc_pwc_lvd_init_t *pstcLvdInit); +void PWC_LVD_DeInit(uint8_t u8Ch); +int32_t PWC_LVD_StructInit(stc_pwc_lvd_init_t *pstcLvdInit); +void PWC_LVD_Cmd(uint8_t u8Ch, en_functional_state_t enNewState); +void PWC_LVD_ExtInputCmd(en_functional_state_t enNewState); +void PWC_LVD_CompareOutputCmd(uint8_t u8Ch, en_functional_state_t enNewState); +void PWC_LVD_DigitalFilterCmd(uint8_t u8Ch, en_functional_state_t enNewState); +void PWC_LVD_SetFilterClock(uint8_t u8Ch, uint32_t u32Clock); +void PWC_LVD_SetThresholdVoltage(uint8_t u8Ch, uint32_t u32Voltage); +void PWC_LVD_ClearStatus(uint8_t u8Flag); +en_flag_status_t PWC_LVD_GetStatus(uint8_t u8Flag); + +/* PWC Power Monitor Function */ +void PWC_PowerMonitorCmd(en_functional_state_t enNewState); + +/* PWC RAM Function */ + +void PWC_XTAL32_PowerCmd(en_functional_state_t enNewState); +void PWC_RetSram_PowerCmd(en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_PWC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_PWC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_qspi.h b/mcu/lib/inc/hc32_ll_qspi.h new file mode 100644 index 0000000..035cdb1 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_qspi.h @@ -0,0 +1,446 @@ +/** + ******************************************************************************* + * @file hc32_ll_qspi.h + * @brief This file contains all the functions prototypes of the QSPI driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-09-30 CDT Modify return value type of QSPI_DeInit function + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_QSPI_H__ +#define __HC32_LL_QSPI_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_QSPI + * @{ + */ + +#if (LL_QSPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup QSPI_Global_Types QSPI Global Types + * @{ + */ + +/** + * @brief QSPI initialization structure definition + */ +typedef struct { + uint32_t u32ClockDiv; /*!< Specifies the clock division. + This parameter can be a value of @ref QSPI_Clock_Division */ + uint32_t u32SpiMode; /*!< Specifies the SPI mode. + This parameter can be a value of @ref QSPI_SPI_Mode */ + uint32_t u32PrefetchMode; /*!< Specifies the prefetch mode. + This parameter can be a value of @ref QSPI_Prefetch_Mode */ + uint32_t u32ReadMode; /*!< Specifies the read mode. + This parameter can be a value of @ref QSPI_Read_Mode */ + uint32_t u32DummyCycle; /*!< Specifies the number of dummy cycles. + This parameter can be a value of @ref QSPI_Dummy_Cycle */ + uint32_t u32AddrWidth; /*!< Specifies the address width. + This parameter can be a value of @ref QSPI_Addr_Width */ + uint32_t u32SetupTime; /*!< Specifies the advance time of QSSN setup. + This parameter can be a value of @ref QSPI_QSSN_Setup_Time */ + uint32_t u32ReleaseTime; /*!< Specifies the delay time of QSSN release. + This parameter can be a value of @ref QSPI_QSSN_Release_Time */ + uint32_t u32IntervalTime; /*!< Specifies the minimum interval time of QSSN. + This parameter can be a value of @ref QSPI_QSSN_Interval_Time */ +} stc_qspi_init_t; + +/** + * @brief QSPI Custom read mode structure definition + */ +typedef struct { + uint32_t u32InstrProtocol; /*!< Specifies the instruction stage protocol. + This parameter can be a value of @ref QSPI_Instruction_Protocol */ + uint32_t u32AddrProtocol; /*!< Specifies the address stage protocol. + This parameter can be a value of @ref QSPI_Addr_Protocol */ + uint32_t u32DataProtocol; /*!< Specifies the data stage protocol. + This parameter can be a value of @ref QSPI_Data_Protocol */ + uint8_t u8InstrCode; /*!< Specifies the instruction code in custom read mode. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF */ +} stc_qspi_custom_mode_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup QSPI_Global_Macros QSPI Global Macros + * @{ + */ + +/* QSPI memory mapping base and end address */ +#define QSPI_ROM_BASE (0x98000000UL) +#define QSPI_ROM_END (0x9BFFFFFFUL) + +/** + * @defgroup QSPI_Clock_Division QSPI Clock Division + * @{ + */ +#define QSPI_CLK_DIV2 (0x01UL << QSPI_CR_DIV_POS) /*!< Clock division by 2 */ +#define QSPI_CLK_DIV3 (0x02UL << QSPI_CR_DIV_POS) /*!< Clock division by 3 */ +#define QSPI_CLK_DIV4 (0x03UL << QSPI_CR_DIV_POS) /*!< Clock division by 4 */ +#define QSPI_CLK_DIV5 (0x04UL << QSPI_CR_DIV_POS) /*!< Clock division by 5 */ +#define QSPI_CLK_DIV6 (0x05UL << QSPI_CR_DIV_POS) /*!< Clock division by 6 */ +#define QSPI_CLK_DIV7 (0x06UL << QSPI_CR_DIV_POS) /*!< Clock division by 7 */ +#define QSPI_CLK_DIV8 (0x07UL << QSPI_CR_DIV_POS) /*!< Clock division by 8 */ +#define QSPI_CLK_DIV9 (0x08UL << QSPI_CR_DIV_POS) /*!< Clock division by 9 */ +#define QSPI_CLK_DIV10 (0x09UL << QSPI_CR_DIV_POS) /*!< Clock division by 10 */ +#define QSPI_CLK_DIV11 (0x0AUL << QSPI_CR_DIV_POS) /*!< Clock division by 11 */ +#define QSPI_CLK_DIV12 (0x0BUL << QSPI_CR_DIV_POS) /*!< Clock division by 12 */ +#define QSPI_CLK_DIV13 (0x0CUL << QSPI_CR_DIV_POS) /*!< Clock division by 13 */ +#define QSPI_CLK_DIV14 (0x0DUL << QSPI_CR_DIV_POS) /*!< Clock division by 14 */ +#define QSPI_CLK_DIV15 (0x0EUL << QSPI_CR_DIV_POS) /*!< Clock division by 15 */ +#define QSPI_CLK_DIV16 (0x0FUL << QSPI_CR_DIV_POS) /*!< Clock division by 16 */ +#define QSPI_CLK_DIV17 (0x10UL << QSPI_CR_DIV_POS) /*!< Clock division by 17 */ +#define QSPI_CLK_DIV18 (0x11UL << QSPI_CR_DIV_POS) /*!< Clock division by 18 */ +#define QSPI_CLK_DIV19 (0x12UL << QSPI_CR_DIV_POS) /*!< Clock division by 19 */ +#define QSPI_CLK_DIV20 (0x13UL << QSPI_CR_DIV_POS) /*!< Clock division by 20 */ +#define QSPI_CLK_DIV21 (0x14UL << QSPI_CR_DIV_POS) /*!< Clock division by 21 */ +#define QSPI_CLK_DIV22 (0x15UL << QSPI_CR_DIV_POS) /*!< Clock division by 22 */ +#define QSPI_CLK_DIV23 (0x16UL << QSPI_CR_DIV_POS) /*!< Clock division by 23 */ +#define QSPI_CLK_DIV24 (0x17UL << QSPI_CR_DIV_POS) /*!< Clock division by 24 */ +#define QSPI_CLK_DIV25 (0x18UL << QSPI_CR_DIV_POS) /*!< Clock division by 25 */ +#define QSPI_CLK_DIV26 (0x19UL << QSPI_CR_DIV_POS) /*!< Clock division by 26 */ +#define QSPI_CLK_DIV27 (0x1AUL << QSPI_CR_DIV_POS) /*!< Clock division by 27 */ +#define QSPI_CLK_DIV28 (0x1BUL << QSPI_CR_DIV_POS) /*!< Clock division by 28 */ +#define QSPI_CLK_DIV29 (0x1CUL << QSPI_CR_DIV_POS) /*!< Clock division by 29 */ +#define QSPI_CLK_DIV30 (0x1DUL << QSPI_CR_DIV_POS) /*!< Clock division by 30 */ +#define QSPI_CLK_DIV31 (0x1EUL << QSPI_CR_DIV_POS) /*!< Clock division by 31 */ +#define QSPI_CLK_DIV32 (0x1FUL << QSPI_CR_DIV_POS) /*!< Clock division by 32 */ +#define QSPI_CLK_DIV33 (0x20UL << QSPI_CR_DIV_POS) /*!< Clock division by 33 */ +#define QSPI_CLK_DIV34 (0x21UL << QSPI_CR_DIV_POS) /*!< Clock division by 34 */ +#define QSPI_CLK_DIV35 (0x22UL << QSPI_CR_DIV_POS) /*!< Clock division by 35 */ +#define QSPI_CLK_DIV36 (0x23UL << QSPI_CR_DIV_POS) /*!< Clock division by 36 */ +#define QSPI_CLK_DIV37 (0x24UL << QSPI_CR_DIV_POS) /*!< Clock division by 37 */ +#define QSPI_CLK_DIV38 (0x25UL << QSPI_CR_DIV_POS) /*!< Clock division by 38 */ +#define QSPI_CLK_DIV39 (0x26UL << QSPI_CR_DIV_POS) /*!< Clock division by 39 */ +#define QSPI_CLK_DIV40 (0x27UL << QSPI_CR_DIV_POS) /*!< Clock division by 40 */ +#define QSPI_CLK_DIV41 (0x28UL << QSPI_CR_DIV_POS) /*!< Clock division by 41 */ +#define QSPI_CLK_DIV42 (0x29UL << QSPI_CR_DIV_POS) /*!< Clock division by 42 */ +#define QSPI_CLK_DIV43 (0x2AUL << QSPI_CR_DIV_POS) /*!< Clock division by 43 */ +#define QSPI_CLK_DIV44 (0x2BUL << QSPI_CR_DIV_POS) /*!< Clock division by 44 */ +#define QSPI_CLK_DIV45 (0x2CUL << QSPI_CR_DIV_POS) /*!< Clock division by 45 */ +#define QSPI_CLK_DIV46 (0x2DUL << QSPI_CR_DIV_POS) /*!< Clock division by 46 */ +#define QSPI_CLK_DIV47 (0x2EUL << QSPI_CR_DIV_POS) /*!< Clock division by 47 */ +#define QSPI_CLK_DIV48 (0x2FUL << QSPI_CR_DIV_POS) /*!< Clock division by 48 */ +#define QSPI_CLK_DIV49 (0x30UL << QSPI_CR_DIV_POS) /*!< Clock division by 49 */ +#define QSPI_CLK_DIV50 (0x31UL << QSPI_CR_DIV_POS) /*!< Clock division by 50 */ +#define QSPI_CLK_DIV51 (0x32UL << QSPI_CR_DIV_POS) /*!< Clock division by 51 */ +#define QSPI_CLK_DIV52 (0x33UL << QSPI_CR_DIV_POS) /*!< Clock division by 52 */ +#define QSPI_CLK_DIV53 (0x34UL << QSPI_CR_DIV_POS) /*!< Clock division by 53 */ +#define QSPI_CLK_DIV54 (0x35UL << QSPI_CR_DIV_POS) /*!< Clock division by 54 */ +#define QSPI_CLK_DIV55 (0x36UL << QSPI_CR_DIV_POS) /*!< Clock division by 55 */ +#define QSPI_CLK_DIV56 (0x37UL << QSPI_CR_DIV_POS) /*!< Clock division by 56 */ +#define QSPI_CLK_DIV57 (0x38UL << QSPI_CR_DIV_POS) /*!< Clock division by 57 */ +#define QSPI_CLK_DIV58 (0x39UL << QSPI_CR_DIV_POS) /*!< Clock division by 58 */ +#define QSPI_CLK_DIV59 (0x3AUL << QSPI_CR_DIV_POS) /*!< Clock division by 59 */ +#define QSPI_CLK_DIV60 (0x3BUL << QSPI_CR_DIV_POS) /*!< Clock division by 60 */ +#define QSPI_CLK_DIV61 (0x3CUL << QSPI_CR_DIV_POS) /*!< Clock division by 61 */ +#define QSPI_CLK_DIV62 (0x3DUL << QSPI_CR_DIV_POS) /*!< Clock division by 62 */ +#define QSPI_CLK_DIV63 (0x3EUL << QSPI_CR_DIV_POS) /*!< Clock division by 63 */ +#define QSPI_CLK_DIV64 (0x3FUL << QSPI_CR_DIV_POS) /*!< Clock division by 64 */ +/** + * @} + */ + +/** + * @defgroup QSPI_SPI_Mode QSPI SPI Mode + * @{ + */ +#define QSPI_SPI_MD0 (0UL) /*!< Selects SPI mode 0 */ +#define QSPI_SPI_MD3 (QSPI_CR_SPIMD3) /*!< Selects SPI mode 3 */ +/** + * @} + */ + +/** + * @defgroup QSPI_Prefetch_Mode QSPI Prefetch Mode + * @{ + */ +#define QSPI_PREFETCH_MD_INVD (0UL) /*!< Disable prefetch */ +#define QSPI_PREFETCH_MD_EDGE_STOP (QSPI_CR_PFE) /*!< Stop prefetch at the edge of byte */ +#define QSPI_PREFETCH_MD_IMMED_STOP (QSPI_CR_PFE | QSPI_CR_PFSAE) /*!< Stop prefetch at current position immediately */ +/** + * @} + */ + +/** + * @defgroup QSPI_Read_Mode QSPI Read Mode + * @{ + */ +#define QSPI_RD_MD_STD_RD (0UL) /*!< Standard read mode (no dummy cycles) */ +#define QSPI_RD_MD_FAST_RD (0x01UL << QSPI_CR_MDSEL_POS) /*!< Fast read mode (dummy cycles between address and data) */ +#define QSPI_RD_MD_DUAL_OUTPUT_FAST_RD (0x02UL << QSPI_CR_MDSEL_POS) /*!< Fast read dual output mode (data on 2 lines) */ +#define QSPI_RD_MD_DUAL_IO_FAST_RD (0x03UL << QSPI_CR_MDSEL_POS) /*!< Fast read dual I/O mode (address and data on 2 lines) */ +#define QSPI_RD_MD_QUAD_OUTPUT_FAST_RD (0x04UL << QSPI_CR_MDSEL_POS) /*!< Fast read quad output mode (data on 4 lines) */ +#define QSPI_RD_MD_QUAD_IO_FAST_RD (0x05UL << QSPI_CR_MDSEL_POS) /*!< Fast read quad I/O mode (address and data on 4 lines) */ +#define QSPI_RD_MD_CUSTOM_STANDARD_RD (0x06UL << QSPI_CR_MDSEL_POS) /*!< Custom standard read mode */ +#define QSPI_RD_MD_CUSTOM_FAST_RD (0x07UL << QSPI_CR_MDSEL_POS) /*!< Custom fast read mode */ +/** + * @} + */ + +/** + * @defgroup QSPI_Dummy_Cycle QSPI Dummy Cycle + * @{ + */ +#define QSPI_DUMMY_CYCLE3 (0UL) /*!< Dummy cycle is 3 */ +#define QSPI_DUMMY_CYCLE4 (0x01UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 4 */ +#define QSPI_DUMMY_CYCLE5 (0x02UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 5 */ +#define QSPI_DUMMY_CYCLE6 (0x03UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 6 */ +#define QSPI_DUMMY_CYCLE7 (0x04UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 7 */ +#define QSPI_DUMMY_CYCLE8 (0x05UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 8 */ +#define QSPI_DUMMY_CYCLE9 (0x06UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 9 */ +#define QSPI_DUMMY_CYCLE10 (0x07UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 10 */ +#define QSPI_DUMMY_CYCLE11 (0x08UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 11 */ +#define QSPI_DUMMY_CYCLE12 (0x09UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 12 */ +#define QSPI_DUMMY_CYCLE13 (0x0AUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 13 */ +#define QSPI_DUMMY_CYCLE14 (0x0BUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 14 */ +#define QSPI_DUMMY_CYCLE15 (0x0CUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 15 */ +#define QSPI_DUMMY_CYCLE16 (0x0DUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 16 */ +#define QSPI_DUMMY_CYCLE17 (0x0EUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 15 */ +#define QSPI_DUMMY_CYCLE18 (0x0FUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 16 */ +/** + * @} + */ + +/** + * @defgroup QSPI_Addr_Width QSPI Address Width + * @{ + */ +#define QSPI_ADDR_WIDTH_8BIT (0x0U) /*!< QSPI address width is 8 bits */ +#define QSPI_ADDR_WIDTH_16BIT (QSPI_FCR_AWSL_0) /*!< QSPI address width is 16 bits */ +#define QSPI_ADDR_WIDTH_24BIT (QSPI_FCR_AWSL_1) /*!< QSPI address width is 24 bits */ +#define QSPI_ADDR_WIDTH_32BIT_INSTR_24BIT (QSPI_FCR_AWSL) /*!< QSPI address width is 32 bits and don't use 4-byte address read instruction code */ +#define QSPI_ADDR_WIDTH_32BIT_INSTR_32BIT (QSPI_FCR_AWSL | QSPI_FCR_FOUR_BIC) /*!< QSPI address width is 32 bits and use 4-byte address read instruction code */ +/** + * @} + */ + +/** + * @defgroup QSPI_QSSN_Setup_Time QSPI QSSN Setup Time + * @{ + */ +#define QSPI_QSSN_SETUP_ADVANCE_QSCK0P5 (0UL) /*!< Output QSSN signal 0.5 QSCK before the first rising edge of QSCK */ +#define QSPI_QSSN_SETUP_ADVANCE_QSCK1P5 (QSPI_FCR_SSNLD) /*!< Output QSSN signal 1.5 QSCK before the first rising edge of QSCK */ +/** + * @} + */ + +/** + * @defgroup QSPI_QSSN_Release_Time QSPI QSSN Release Time + * @{ + */ +#define QSPI_QSSN_RELEASE_DELAY_QSCK0P5 (0UL) /*!< Release QSSN signal 0.5 QSCK after the last rising edge of QSCK */ +#define QSPI_QSSN_RELEASE_DELAY_QSCK1P5 (QSPI_FCR_SSNHD) /*!< Release QSSN signal 1.5 QSCK after the last rising edge of QSCK */ +#define QSPI_QSSN_RELEASE_DELAY_QSCK32 (QSPI_CSCR_SSNW_0 << 8U) /*!< Release QSSN signal 32 QSCK after the last rising edge of QSCK */ +#define QSPI_QSSN_RELEASE_DELAY_QSCK128 (QSPI_CSCR_SSNW_1 << 8U) /*!< Release QSSN signal 128 QSCK after the last rising edge of QSCK */ +#define QSPI_QSSN_RELEASE_DELAY_INFINITE (QSPI_CSCR_SSNW << 8U) /*!< Never release QSSN signal after the last rising edge of QSCK */ +/** + * @} + */ + +/** + * @defgroup QSPI_QSSN_Interval_Time QSPI QSSN Interval Time + * @{ + */ +#define QSPI_QSSN_INTERVAL_QSCK1 (0UL) /*!< Minimum interval time is 1 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK2 (0x01UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 2 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK3 (0x02UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 3 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK4 (0x03UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 4 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK5 (0x04UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 5 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK6 (0x05UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 6 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK7 (0x06UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 7 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK8 (0x07UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 8 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK9 (0x08UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 9 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK10 (0x09UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 10 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK11 (0x0AUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 11 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK12 (0x0BUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 12 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK13 (0x0CUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 13 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK14 (0x0DUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 14 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK15 (0x0EUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 15 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK16 (0x0FUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 16 QSCK */ +/** + * @} + */ + +/** + * @defgroup QSPI_Instruction_Protocol QSPI Instruction Protocol + * @{ + */ +#define QSPI_INSTR_PROTOCOL_1LINE (0x0U) /*!< Instruction on 1 line */ +#define QSPI_INSTR_PROTOCOL_2LINE (QSPI_CR_IPRSL_0) /*!< Instruction on 2 lines */ +#define QSPI_INSTR_PROTOCOL_4LINE (QSPI_CR_IPRSL_1) /*!< Instruction on 4 lines */ +/** + * @} + */ + +/** + * @defgroup QSPI_Addr_Protocol QSPI Address Protocol + * @{ + */ +#define QSPI_ADDR_PROTOCOL_1LINE (0x0U) /*!< Address on 1 line */ +#define QSPI_ADDR_PROTOCOL_2LINE (QSPI_CR_APRSL_0) /*!< Address on 2 lines */ +#define QSPI_ADDR_PROTOCOL_4LINE (QSPI_CR_APRSL_1) /*!< Address on 4 lines */ +/** + * @} + */ + +/** + * @defgroup QSPI_Data_Protocol QSPI Data Protocol + * @{ + */ +#define QSPI_DATA_PROTOCOL_1LINE (0x0U) /*!< Data on 1 line */ +#define QSPI_DATA_PROTOCOL_2LINE (QSPI_CR_DPRSL_0) /*!< Data on 2 lines */ +#define QSPI_DATA_PROTOCOL_4LINE (QSPI_CR_DPRSL_1) /*!< Data on 4 lines */ +/** + * @} + */ + +/** + * @defgroup QSPI_WP_Pin_Level QSPI WP Pin Level + * @{ + */ +#define QSPI_WP_PIN_LOW (0x0U) /*!< WP(QSIO2) pin output low */ +#define QSPI_WP_PIN_HIGH (QSPI_FCR_WPOL) /*!< WP(QSIO2) pin output high */ +/** + * @} + */ + +/** + * @defgroup QSPI_Status_Flag QSPI Status Flag + * @{ + */ +#define QSPI_FLAG_DIRECT_COMM_BUSY (QSPI_SR_BUSY) /*!< Serial transfer being processed */ +#define QSPI_FLAG_XIP_MD (QSPI_SR_XIPF) /*!< XIP mode */ +#define QSPI_FLAG_ROM_ACCESS_ERR (QSPI_SR_RAER) /*!< ROM access detection status in direct communication mode */ +#define QSPI_FLAG_PREFETCH_BUF_FULL (QSPI_SR_PFFUL) /*!< Prefetch buffer is full */ +#define QSPI_FLAG_PREFETCH_STOP (QSPI_SR_PFAN) /*!< Prefetch function operating */ + +#define QSPI_FLAG_ALL (QSPI_FLAG_DIRECT_COMM_BUSY | QSPI_FLAG_XIP_MD | \ + QSPI_FLAG_ROM_ACCESS_ERR | QSPI_FLAG_PREFETCH_BUF_FULL | \ + QSPI_FLAG_PREFETCH_STOP) +#define QSPI_FLAG_CLR_ALL (QSPI_FLAG_ROM_ACCESS_ERR) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup QSPI_Global_Functions + * @{ + */ + +/** + * @brief Write data in direct communication mode. + * @param [in] u8Value Byte data. + * @retval None + */ +__STATIC_INLINE void QSPI_WriteDirectCommValue(uint8_t u8Value) +{ + WRITE_REG32(CM_QSPI->DCOM, u8Value); +} + +/** + * @brief Read data in direct communication mode. + * @param None + * @retval uint8_t Byte data. + */ +__STATIC_INLINE uint8_t QSPI_ReadDirectCommValue(void) +{ + return (uint8_t)CM_QSPI->DCOM; +} + +/* Initialization and configuration functions */ +int32_t QSPI_DeInit(void); +int32_t QSPI_Init(const stc_qspi_init_t *pstcQspiInit); +int32_t QSPI_StructInit(stc_qspi_init_t *pstcQspiInit); +void QSPI_SetWpPinLevel(uint32_t u32Level); +void QSPI_SetPrefetchMode(uint32_t u32Mode); +void QSPI_SelectMemoryBlock(uint8_t u8Block); +void QSPI_SetReadMode(uint32_t u32Mode); +int32_t QSPI_CustomReadConfig(const stc_qspi_custom_mode_t *pstcCustomMode); +void QSPI_XipModeCmd(uint8_t u8ModeCode, en_functional_state_t enNewState); + +/* Transfer and receive data functions */ +void QSPI_EnterDirectCommMode(void); +void QSPI_ExitDirectCommMode(void); +void QSPI_WriteDirectCommValue(uint8_t u8Value); +uint8_t QSPI_ReadDirectCommValue(void); + +/* Interrupt and flag management functions */ +uint8_t QSPI_GetPrefetchBufSize(void); +en_flag_status_t QSPI_GetStatus(uint32_t u32Flag); +void QSPI_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_QSPI_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_QSPI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_rmu.h b/mcu/lib/inc/hc32_ll_rmu.h new file mode 100644 index 0000000..b4d2ba8 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_rmu.h @@ -0,0 +1,128 @@ +/** + ******************************************************************************* + * @file hc32_ll_rmu.h + * @brief This file contains all the functions prototypes of the RMU driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_RMU_H__ +#define __HC32_LL_RMU_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_RMU + * @{ + */ +#if (LL_RMU_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup RMU_Global_Macros RMU Global Macros + * @{ + */ + +/** + * @defgroup RMU_ResetCause Rmu reset cause + * @{ + */ +#define RMU_FLAG_PWR_ON (RMU_RSTF0_PORF) /*!< Power on reset */ +#define RMU_FLAG_PIN (RMU_RSTF0_PINRF) /*!< Reset pin reset */ +#define RMU_FLAG_BROWN_OUT (RMU_RSTF0_BORF) /*!< Brown-out reset */ +#define RMU_FLAG_PVD1 (RMU_RSTF0_PVD1RF) /*!< Program voltage Detection 1 reset */ +#define RMU_FLAG_PVD2 (RMU_RSTF0_PVD2RF) /*!< Program voltage Detection 2 reset */ +#define RMU_FLAG_WDT (RMU_RSTF0_WDRF) /*!< Watchdog timer reset */ +#define RMU_FLAG_SWDT (RMU_RSTF0_SWDRF) /*!< Special watchdog timer reset */ +#define RMU_FLAG_PWR_DOWN (RMU_RSTF0_PDRF) /*!< Power down reset */ +#define RMU_FLAG_SW (RMU_RSTF0_SWRF) /*!< Software reset */ +#define RMU_FLAG_MPU_ERR (RMU_RSTF0_MPUERF) /*!< Mpu error reset */ +#define RMU_FLAG_RAM_PARITY_ERR (RMU_RSTF0_RAPERF) /*!< Ram parity error reset */ +#define RMU_FLAG_RAM_ECC (RMU_RSTF0_RAECRF) /*!< Ram ECC reset */ +#define RMU_FLAG_CLK_ERR (RMU_RSTF0_CKFERF) /*!< Clk frequency error reset */ +#define RMU_FLAG_XTAL_ERR (RMU_RSTF0_XTALERF) /*!< Xtal error reset */ +#define RMU_FLAG_MX (RMU_RSTF0_MULTIRF) /*!< Multiply reset cause */ +#define RMU_FLAG_ALL (RMU_FLAG_PWR_ON | RMU_FLAG_PIN | RMU_FLAG_BROWN_OUT | RMU_FLAG_PVD1 | \ + RMU_FLAG_PVD2 | RMU_FLAG_WDT | RMU_FLAG_SWDT | RMU_FLAG_PWR_DOWN | \ + RMU_FLAG_SW | RMU_FLAG_MPU_ERR | RMU_FLAG_RAM_PARITY_ERR | RMU_FLAG_RAM_ECC | \ + RMU_FLAG_CLK_ERR | RMU_FLAG_XTAL_ERR | RMU_FLAG_MX) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup RMU_Global_Functions + * @{ + */ + +en_flag_status_t RMU_GetStatus(uint32_t u32RmuResetCause); +void RMU_ClearStatus(void); + +/** + * @} + */ + +#endif /* LL_RMU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_RMU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/mcu/lib/inc/hc32_ll_rtc.h b/mcu/lib/inc/hc32_ll_rtc.h new file mode 100644 index 0000000..978debf --- /dev/null +++ b/mcu/lib/inc/hc32_ll_rtc.h @@ -0,0 +1,364 @@ +/** + ******************************************************************************* + * @file hc32_ll_rtc.h + * @brief This file contains all the functions prototypes of the RTC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_RTC_H__ +#define __HC32_LL_RTC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_RTC + * @{ + */ + +#if (LL_RTC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup RTC_Global_Types RTC Global Types + * @{ + */ + +/** + * @brief RTC Init structure definition + */ +typedef struct { + uint8_t u8ClockSrc; /*!< Specifies the RTC clock source. + This parameter can be a value of @ref RTC_Clock_Source */ + uint8_t u8HourFormat; /*!< Specifies the RTC hour format. + This parameter can be a value of @ref RTC_Hour_Format */ + uint8_t u8IntPeriod; /*!< Specifies the RTC interrupt period. + This parameter can be a value of @ref RTC_Interrupt_Period */ + uint8_t u8ClockCompen; /*!< Specifies the validity of RTC clock compensation. + This parameter can be a value of @ref RTC_Clock_Compensation */ + uint8_t u8CompenMode; /*!< Specifies the mode of RTC clock compensation. + This parameter can be a value of @ref RTC_Clock_Compensation_Mode */ + uint16_t u16CompenValue; /*!< Specifies the value of RTC clock compensation. + This parameter can be a number between Min_Data = 0 and Max_Data = 0x1FF */ +} stc_rtc_init_t; + +/** + * @brief RTC Date structure definition + */ +typedef struct { + uint8_t u8Year; /*!< Specifies the RTC Year. + This parameter can be a number between Min_Data = 0 and Max_Data = 99 */ + uint8_t u8Month; /*!< Specifies the RTC Month (in Decimal format). + This parameter can be a value of @ref RTC_Month */ + uint8_t u8Day; /*!< Specifies the RTC Day. + This parameter can be a number between Min_Data = 1 and Max_Data = 31 */ + uint8_t u8Weekday; /*!< Specifies the RTC Weekday. + This parameter can be a value of @ref RTC_Weekday */ +} stc_rtc_date_t; + +/** + * @brief RTC Time structure definition + */ +typedef struct { + uint8_t u8Hour; /*!< Specifies the RTC Hour. + This parameter can be a number between Min_Data = 1 and Max_Data = 12 if the RTC_HOUR_FMT_12H is selected. + This parameter can be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HOUR_FMT_24H is selected */ + uint8_t u8Minute; /*!< Specifies the RTC Minute. + This parameter can be a number between Min_Data = 0 and Max_Data = 59 */ + uint8_t u8Second; /*!< Specifies the RTC Second. + This parameter can be a number between Min_Data = 0 and Max_Data = 59 */ + uint8_t u8AmPm; /*!< Specifies the RTC Am/Pm Time (in RTC_HOUR_FMT_12H mode). + This parameter can be a value of @ref RTC_Hour12_AM_PM */ +} stc_rtc_time_t; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct { + uint8_t u8AlarmHour; /*!< Specifies the RTC Alarm Hour. + This parameter can be a number between Min_Data = 1 and Max_Data = 12 if the RTC_HOUR_FMT_12H is selected. + This parameter can be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HOUR_FMT_24H is selected */ + uint8_t u8AlarmMinute; /*!< Specifies the RTC Alarm Minute. + This parameter can be a number between Min_Data = 0 and Max_Data = 59 */ + uint8_t u8AlarmWeekday; /*!< Specifies the RTC Alarm Weekday. + This parameter can be a value of @ref RTC_Alarm_Weekday */ + uint8_t u8AlarmAmPm; /*!< Specifies the RTC Alarm Am/Pm Time (in RTC_HOUR_FMT_12H mode). + This parameter can be a value of @ref RTC_Hour12_AM_PM */ +} stc_rtc_alarm_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup RTC_Global_Macros RTC Global Macros + * @{ + */ + +/** + * @defgroup RTC_Data_Format RTC Data Format + * @{ + */ +#define RTC_DATA_FMT_DEC (0x00U) /*!< Decimal data format */ +#define RTC_DATA_FMT_BCD (0x01U) /*!< BCD data format */ +/** + * @} + */ + +/** + * @defgroup RTC_Decimal_BCD_Conversion RTC Decimal BCD Conversion + * @{ + */ +#define RTC_DEC2BCD(__DATA__) ((((__DATA__) / 10U) << 4U) + ((__DATA__) % 10U)) +#define RTC_BCD2DEC(__DATA__) ((((__DATA__) >> 4U) * 10U) + ((__DATA__) & 0x0FU)) +/** + * @} + */ + +/** + * @defgroup RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RTC_CLK_SRC_XTAL32 (0U) /*!< XTAL32 Clock */ +#define RTC_CLK_SRC_LRC (RTC_CR3_RCKSEL | RTC_CR3_LRCEN) /*!< RTC LRC Clock */ +/** + * @} + */ + +/** + * @defgroup RTC_Hour_Format RTC Hour Format + * @{ + */ +#define RTC_HOUR_FMT_12H (0U) /*!< 12 hour time system */ +#define RTC_HOUR_FMT_24H (RTC_CR1_AMPM) /*!< 24 hour time system */ +/** + * @} + */ + +/** + * @defgroup RTC_Interrupt_Period RTC Interrupt Period + * @{ + */ +#define RTC_INT_PERIOD_INVD (0U) /*!< Interrupt period invalid */ +#define RTC_INT_PERIOD_PER_HALF_SEC (0x01U << RTC_CR1_PRDS_POS) /*!< Interrupt period per half second */ +#define RTC_INT_PERIOD_PER_SEC (0x02U << RTC_CR1_PRDS_POS) /*!< Interrupt period per second */ +#define RTC_INT_PERIOD_PER_MINUTE (0x03U << RTC_CR1_PRDS_POS) /*!< Interrupt period per minute */ +#define RTC_INT_PERIOD_PER_HOUR (0x04U << RTC_CR1_PRDS_POS) /*!< Interrupt period per hour */ +#define RTC_INT_PERIOD_PER_DAY (0x05U << RTC_CR1_PRDS_POS) /*!< Interrupt period per day */ +#define RTC_INT_PERIOD_PER_MONTH (0x06U << RTC_CR1_PRDS_POS) /*!< Interrupt period per month */ +/** + * @} + */ + +/** + * @defgroup RTC_Clock_Compensation RTC Clock Compensation + * @{ + */ +#define RTC_CLK_COMPEN_DISABLE (0U) +#define RTC_CLK_COMPEN_ENABLE (RTC_ERRCRH_COMPEN) +/** + * @} + */ + +/** + * @defgroup RTC_Clock_Compensation_Mode RTC Clock Compensation Mode + * @{ + */ +#define RTC_CLK_COMPEN_MD_DISTRIBUTED (0U) /*!< Distributed compensation 1Hz output */ +#define RTC_CLK_COMPEN_MD_UNIFORM (RTC_CR1_ONEHZSEL) /*!< Uniform compensation 1Hz output */ +/** + * @} + */ + +/** + * @defgroup RTC_Hour12_AM_PM RTC Hour12 AM/PM + * @{ + */ +#define RTC_HOUR_24H (0U) /*!< 24-hour format */ +#define RTC_HOUR_12H_AM (0U) /*!< AM in 12-hour */ +#define RTC_HOUR_12H_PM (RTC_HOUR_HOURD_1) /*!< PM in 12-hour */ +/** + * @} + */ + +/** + * @defgroup RTC_Month RTC Month + * @{ + */ +#define RTC_MONTH_JANUARY (0x01U) +#define RTC_MONTH_FEBRUARY (0x02U) +#define RTC_MONTH_MARCH (0x03U) +#define RTC_MONTH_APRIL (0x04U) +#define RTC_MONTH_MAY (0x05U) +#define RTC_MONTH_JUNE (0x06U) +#define RTC_MONTH_JULY (0x07U) +#define RTC_MONTH_AUGUST (0x08U) +#define RTC_MONTH_SEPTEMBER (0x09U) +#define RTC_MONTH_OCTOBER (0x0AU) +#define RTC_MONTH_NOVEMBER (0x0BU) +#define RTC_MONTH_DECEMBER (0x0CU) +/** + * @} + */ + +/** + * @defgroup RTC_Weekday RTC Weekday + * @{ + */ +#define RTC_WEEKDAY_SUNDAY (0x00U) +#define RTC_WEEKDAY_MONDAY (0x01U) +#define RTC_WEEKDAY_TUESDAY (0x02U) +#define RTC_WEEKDAY_WEDNESDAY (0x03U) +#define RTC_WEEKDAY_THURSDAY (0x04U) +#define RTC_WEEKDAY_FRIDAY (0x05U) +#define RTC_WEEKDAY_SATURDAY (0x06U) +/** + * @} + */ + +/** + * @defgroup RTC_Alarm_Weekday RTC Alarm Weekday + * @{ + */ +#define RTC_ALARM_WEEKDAY_SUNDAY (0x01U) +#define RTC_ALARM_WEEKDAY_MONDAY (0x02U) +#define RTC_ALARM_WEEKDAY_TUESDAY (0x04U) +#define RTC_ALARM_WEEKDAY_WEDNESDAY (0x08U) +#define RTC_ALARM_WEEKDAY_THURSDAY (0x10U) +#define RTC_ALARM_WEEKDAY_FRIDAY (0x20U) +#define RTC_ALARM_WEEKDAY_SATURDAY (0x40U) +#define RTC_ALARM_WEEKDAY_EVERYDAY (0x7FU) +/** + * @} + */ + +/** + * @defgroup RTC_Flag RTC Flag + * @{ + */ +#define RTC_FLAG_RD_WR (RTC_CR2_RWEN) /*!< Read and write permission flag */ +#define RTC_FLAG_ALARM (RTC_CR2_ALMF) /*!< Alarm flag */ +#define RTC_FLAG_ALL (RTC_FLAG_RD_WR | RTC_FLAG_ALARM) +#define RTC_FLAG_CLR_ALL (RTC_FLAG_ALARM) +/** + * @} + */ + +/** + * @defgroup RTC_Interrupt RTC Interrupt + * @{ + */ +#define RTC_INT_PERIOD (RTC_CR2_PRDIE) /*!< Period interrupt */ +#define RTC_INT_ALARM (RTC_CR2_ALMIE) /*!< Alarm interrupt */ +#define RTC_INT_ALL (RTC_INT_PERIOD | RTC_INT_ALARM) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup RTC_Global_Functions + * @{ + */ + +/* Initialization and configuration functions */ +int32_t RTC_DeInit(void); +int32_t RTC_Init(const stc_rtc_init_t *pstcRtcInit); +int32_t RTC_StructInit(stc_rtc_init_t *pstcRtcInit); +int32_t RTC_EnterRwMode(void); +int32_t RTC_ExitRwMode(void); + +/* Control configuration */ +int32_t RTC_ConfirmLPMCond(void); +void RTC_SetIntPeriod(uint8_t u8Period); +void RTC_SetClockSrc(uint8_t u8Src); +void RTC_SetClockCompenValue(uint16_t u16Value); +en_functional_state_t RTC_GetCounterState(void); +void RTC_Cmd(en_functional_state_t enNewState); +void RTC_LrcCmd(en_functional_state_t enNewState); +void RTC_OneHzOutputCmd(en_functional_state_t enNewState); +void RTC_ClockCompenCmd(en_functional_state_t enNewState); + +/* Date and time functions */ +int32_t RTC_SetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate); +int32_t RTC_GetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate); +int32_t RTC_SetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime); +int32_t RTC_GetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime); + +/* Alarm configuration functions */ +int32_t RTC_SetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm); +int32_t RTC_GetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm); +void RTC_AlarmCmd(en_functional_state_t enNewState); + +/* Interrupt and flag management functions */ +void RTC_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t RTC_GetStatus(uint32_t u32Flag); +void RTC_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_RTC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_RTC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_sdioc.h b/mcu/lib/inc/hc32_ll_sdioc.h new file mode 100644 index 0000000..16b6a77 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_sdioc.h @@ -0,0 +1,892 @@ +/** + ******************************************************************************* + * @file hc32_ll_sdioc.h + * @brief This file contains all the functions prototypes of the SDIOC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-09-30 CDT Modify typo + Rename function SDMMC_ACMD41_SendOperatCond to SDMMC_ACMD41_SendOperateCond + Rename function SDMMC_CMD1_SendOperatCond to SDMMC_CMD1_SendOperateCond + Support CMD5/CMD52/CMD53 + Rename macro definition SDIOC_ACMD52_RW_DIRECT to SDIOC_CMD52_IO_RW_DIRECT + Rename macro definition SDIOC_ACMD53_RW_EXTENDED to SDIOC_CMD53_IO_RW_EXTENDED + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_SDIOC_H__ +#define __HC32_LL_SDIOC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_SDIOC + * @{ + */ + +#if (LL_SDIOC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup SDIOC_Global_Types SDIOC Global Types + * @{ + */ + +/** + * @brief SDIOC Init structure definition + */ +typedef struct { + uint32_t u32Mode; /*!< Specifies the SDIOC work mode. + This parameter can be a value of @ref SDIOC_Mode */ + uint8_t u8CardDetect; /*!< Specifies the SDIOC card detect way. + This parameter can be a value of @ref SDIOC_Card_Detect_Way */ + uint8_t u8SpeedMode; /*!< Specifies the SDIOC speed mode. + This parameter can be a value of @ref SDIOC_Speed_Mode */ + uint8_t u8BusWidth; /*!< Specifies the SDIOC bus width. + This parameter can be a value of @ref SDIOC_Bus_Width */ + uint16_t u16ClockDiv; /*!< Specifies the SDIOC clock division. + This parameter can be a value of @ref SDIOC_Clock_Division */ +} stc_sdioc_init_t; + +/** + * @brief SDIOC Command Configuration structure definition + */ +typedef struct { + uint32_t u32Argument; /*!< Specifies the SDIOC command argument. */ + uint16_t u16CmdIndex; /*!< Specifies the SDIOC command index. + This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ + uint16_t u16CmdType; /*!< Specifies the SDIOC command type. + This parameter can be a value of @ref SDIOC_Command_Type */ + uint16_t u16DataLine; /*!< Specifies whether SDIOC uses data lines in current command. + This parameter can be a value of @ref SDIOC_Data_Line_Valid */ + uint16_t u16ResponseType; /*!< Specifies the SDIOC response type. + This parameter can be a value of @ref SDIOC_Response_Type */ +} stc_sdioc_cmd_config_t; + +/** + * @brief SDIOC Data Configuration structure definition + */ +typedef struct { + uint16_t u16BlockSize; /*!< Specifies the SDIOC data block size. + This parameter must be a number between Min_Data = 1 and Max_Data = 512 */ + uint16_t u16BlockCount; /*!< Specifies the SDIOC data block count. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF */ + uint16_t u16TransDir; /*!< Specifies the SDIOC data transfer direction. + This parameter can be a value of @ref SDIOC_Transfer_Direction */ + uint16_t u16AutoCmd12; /*!< Specifies the validity of the SDIOC Auto Send CMD12. + This parameter can be a value of @ref SDIOC_Auto_Send_CMD12 */ + uint16_t u16TransMode; /*!< Specifies the SDIOC data transfer mode. + This parameter can be a value of @ref SDIOC_Transfer_Mode */ + uint8_t u16DataTimeout; /*!< Specifies the SDIOC data timeout time. + This parameter can be a value of @ref SDIOC_Data_Timeout_Time */ +} stc_sdioc_data_config_t; + +/** + * @brief SDIO CMD52 arguments structure definition + */ +typedef struct { + uint8_t u8FuncNum; /*!< Specifies the number of the function within the I/O card. + This parameter must be a number between Min_Data = 0 and Max_Data = 7 */ + uint32_t u32RwFlag; /*!< Specifies the direction of the I/O operation. + This parameter can be a value of @ref SDIO_CMD52_Arguments_RW_Flag */ + uint32_t u32RegAddr; /*!< Specifies the address of the byte of data inside of the selected function. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFF */ + uint32_t u32RawFlag; /*!< Specifies the direction of the I/O operation. + This parameter can be a value of @ref SDIO_CMD52_Arguments_RAW_Flag */ +} stc_sdio_cmd52_arg_t; + +/** + * @brief SDIO CMD53 arguments structure definition + */ +typedef struct { + uint8_t u8FuncNum; /*!< Specifies the number of the function within the I/O card. + This parameter must be a number between Min_Data = 0 and Max_Data = 7 */ + uint32_t u32RwFlag; /*!< Specifies the direction of the I/O operation. + This parameter can be a value of @ref SDIO_CMD53_Arguments_RW_Flag */ + uint32_t u32RegAddr; /*!< Specifies the address of the byte of data inside of the selected function. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFF */ + uint32_t u32OperateCode; /*!< Specifies the operation code. + This parameter can be a value of @ref SDIO_CMD53_Arguments_Operate_Code */ + uint32_t u32BlockMode; /*!< Specifies the operation code. + This parameter can be a value of @ref SDIO_CMD53_Arguments_Block_Mode */ + uint32_t u32Count; /*!< Specifies the byte/block count. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FF */ +} stc_sdio_cmd53_arg_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SDIOC_Global_Macros SDIOC Global Macros + * @{ + */ + +/** + * @defgroup SDIOC_Mode SDIOC Mode + * @{ + */ +#define SDIOC_MD_SD (0x00UL) /*!< SDIOCx selects SD mode */ +#define SDIOC_MD_MMC (0x01UL) /*!< SDIOCx selects MMC mode */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Card_Detect_Way SDIOC Card Detect Way + * @{ + */ +#define SDIOC_CARD_DETECT_CD_PIN_LVL (0x00U) /*!< SDIOCx_CD(x=1~2) line is selected (for normal use) */ +#define SDIOC_CARD_DETECT_TEST_SIGNAL (SDIOC_HOSTCON_CDSS) /*!< The Card Detect Test Level is selected(for test purpose) */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Card_Detect_Test_Level SDIOC Card Detect Test Level + * @{ + */ +#define SDIOC_CARD_DETECT_TEST_LVL_LOW (0x00U) /*!< Card identification test signal is low level (with device insertion) */ +#define SDIOC_CARD_DETECT_TEST_LVL_HIGH (SDIOC_HOSTCON_CDTL) /*!< Card identification test signal is high level (no device insertion) */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Speed_Mode SDIOC Speed Mode + * @{ + */ +#define SDIOC_SPEED_MD_NORMAL (0x00U) /*!< Normal speed mode */ +#define SDIOC_SPEED_MD_HIGH (SDIOC_HOSTCON_HSEN) /*!< High speed mode */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Bus_Width SDIOC Bus Width + * @{ + */ +#define SDIOC_BUS_WIDTH_1BIT (0x00U) /*!< The Bus width is 1 bit */ +#define SDIOC_BUS_WIDTH_4BIT (SDIOC_HOSTCON_DW) /*!< The Bus width is 4 bit */ +#define SDIOC_BUS_WIDTH_8BIT (SDIOC_HOSTCON_EXDW) /*!< The Bus width is 8 bit */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Clock_Division SDIOC Clock Division + * @{ + */ +#define SDIOC_CLK_DIV1 (0x00U) /*!< CLK1/1 */ +#define SDIOC_CLK_DIV2 (SDIOC_CLKCON_FS_0) /*!< CLK1/2 */ +#define SDIOC_CLK_DIV4 (SDIOC_CLKCON_FS_1) /*!< CLK1/4 */ +#define SDIOC_CLK_DIV8 (SDIOC_CLKCON_FS_2) /*!< CLK1/8 */ +#define SDIOC_CLK_DIV16 (SDIOC_CLKCON_FS_3) /*!< CLK1/16 */ +#define SDIOC_CLK_DIV32 (SDIOC_CLKCON_FS_4) /*!< CLK1/32 */ +#define SDIOC_CLK_DIV64 (SDIOC_CLKCON_FS_5) /*!< CLK1/64 */ +#define SDIOC_CLK_DIV128 (SDIOC_CLKCON_FS_6) /*!< CLK1/128 */ +#define SDIOC_CLK_DIV256 (SDIOC_CLKCON_FS_7) /*!< CLK1/256 */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Command_Type SDIOC Command Type + * @{ + */ +#define SDIOC_CMD_TYPE_NORMAL (0x00U) /*!< Other commands */ +#define SDIOC_CMD_TYPE_SUSPEND (SDIOC_CMD_TYP_0) /*!< CMD52 for writing "Bus Suspend" in CCCR */ +#define SDIOC_CMD_TYPE_RESUME (SDIOC_CMD_TYP_1) /*!< CMD52 for writing "Function Select" in CCCR */ +#define SDIOC_CMD_TYPE_ABORT (SDIOC_CMD_TYP) /*!< CMD12, CMD52 for writing "I/O Abort" in CCCR */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Data_Line_Valid SDIOC Data Line Valid + * @{ + */ +#define SDIOC_DATA_LINE_DISABLE (0x00U) /*!< The current command uses only SDIOCx_CMD(x=1~2) command line */ +#define SDIOC_DATA_LINE_ENABLE (SDIOC_CMD_DAT) /*!< The current command requires the use of SDIOCx_Dy(x=1~2) data line */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Transfer_Direction SDIOC Transfer Direction + * @{ + */ +#define SDIOC_TRANS_DIR_TO_CARD (0x00U) /*!< Write (Host to Card) */ +#define SDIOC_TRANS_DIR_TO_HOST (SDIOC_TRANSMODE_DDIR) /*!< Read (Card to Host) */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Auto_Send_CMD12 SDIOC Auto Send CMD12 + * @{ + */ +#define SDIOC_AUTO_SEND_CMD12_DISABLE (0x00U) /*!< Do not send autocommands */ +#define SDIOC_AUTO_SEND_CMD12_ENABLE (SDIOC_TRANSMODE_ATCEN_0) /*!< CMD12 is automatically sent after multiple block transfers */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Transfer_Mode SDIOC Transfer Mode + * @{ + */ +#define SDIOC_TRANS_MD_SINGLE (0x00U) /*!< Single Block transfer */ +#define SDIOC_TRANS_MD_INFINITE (SDIOC_TRANSMODE_MULB) /*!< Infinite Block transfer */ +#define SDIOC_TRANS_MD_MULTI (SDIOC_TRANSMODE_MULB | SDIOC_TRANSMODE_BCE) /*!< Multiple Block transfer */ +#define SDIOC_TRANS_MD_STOP_MULTI (0x8000U | SDIOC_TRANS_MD_MULTI) /*!< Stop Multiple Block transfer */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Data_Timeout_Time SDIOC Data Timeout Time + * @{ + */ +#define SDIOC_DATA_TIMEOUT_CLK_2E13 (0x00U) /*!< Timeout time: CLK1*2^13 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E14 (0x01U) /*!< Timeout time: CLK1*2^14 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E15 (0x02U) /*!< Timeout time: CLK1*2^15 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E16 (0x03U) /*!< Timeout time: CLK1*2^16 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E17 (0x04U) /*!< Timeout time: CLK1*2^17 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E18 (0x05U) /*!< Timeout time: CLK1*2^18 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E19 (0x06U) /*!< Timeout time: CLK1*2^19 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E20 (0x07U) /*!< Timeout time: CLK1*2^20 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E21 (0x08U) /*!< Timeout time: CLK1*2^21 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E22 (0x09U) /*!< Timeout time: CLK1*2^22 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E23 (0x0AU) /*!< Timeout time: CLK1*2^23 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E24 (0x0BU) /*!< Timeout time: CLK1*2^24 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E25 (0x0CU) /*!< Timeout time: CLK1*2^25 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E26 (0x0DU) /*!< Timeout time: CLK1*2^26 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E27 (0x0EU) /*!< Timeout time: CLK1*2^27 */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Response_Register SDIOC Response Register + * @{ + */ +#define SDIOC_RESP_REG_BIT0_31 (0x00U) /*!< Command Response Register 0-31bit */ +#define SDIOC_RESP_REG_BIT32_63 (0x04U) /*!< Command Response Register 32-63bit */ +#define SDIOC_RESP_REG_BIT64_95 (0x08U) /*!< Command Response Register 64-95bit */ +#define SDIOC_RESP_REG_BIT96_127 (0x0CU) /*!< Command Response Register 96-127bit */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Software_Reset_Type SDIOC Software Reset Type + * @{ + */ +#define SDIOC_SW_RST_DATA_LINE (SDIOC_SFTRST_RSTD) /*!< Only part of data circuit is reset */ +#define SDIOC_SW_RST_CMD_LINE (SDIOC_SFTRST_RSTC) /*!< Only part of command circuit is reset */ +#define SDIOC_SW_RST_ALL (SDIOC_SFTRST_RSTA) /*!< Reset the entire Host Controller except for the card detection circuit */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Output_Clock_Frequency SDIOC Output Clock Frequency + * @{ + */ +#define SDIOC_OUTPUT_CLK_FREQ_400K (400000UL) /*!< SDIOC clock: 400KHz */ +#define SDIOC_OUTPUT_CLK_FREQ_25M (25000000UL) /*!< SDIOC clock: 25MHz */ +#define SDIOC_OUTPUT_CLK_FREQ_26M (26000000UL) /*!< SDIOC clock: 26MHz */ +#define SDIOC_OUTPUT_CLK_FREQ_50M (50000000UL) /*!< SDIOC clock: 50MHz */ +#define SDIOC_OUTPUT_CLK_FREQ_52M (52000000UL) /*!< SDIOC clock: 52MHz */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Host_Flag SDIOC Host Flag + * @{ + */ +#define SDIOC_HOST_FLAG_CMDL (SDIOC_PSTAT_CMDL) /*!< CMD Line Level status */ +#define SDIOC_HOST_FLAG_DATL (SDIOC_PSTAT_DATL) /*!< DAT[3:0] Line Level status */ +#define SDIOC_HOST_FLAG_DATL_D0 (SDIOC_PSTAT_DATL_0) /*!< DAT[0] Line Level status */ +#define SDIOC_HOST_FLAG_DATL_D1 (SDIOC_PSTAT_DATL_1) /*!< DAT[1] Line Level status */ +#define SDIOC_HOST_FLAG_DATL_D2 (SDIOC_PSTAT_DATL_2) /*!< DAT[2] Line Level status */ +#define SDIOC_HOST_FLAG_DATL_D3 (SDIOC_PSTAT_DATL_3) /*!< DAT[3] Line Level status */ +#define SDIOC_HOST_FLAG_WPL (SDIOC_PSTAT_WPL) /*!< Write Protect Line Level status */ +#define SDIOC_HOST_FLAG_CDL (SDIOC_PSTAT_CDL) /*!< Card Detect Line Level status */ +#define SDIOC_HOST_FLAG_CSS (SDIOC_PSTAT_CSS) /*!< Device Stable Status */ +#define SDIOC_HOST_FLAG_CIN (SDIOC_PSTAT_CIN) /*!< Device Inserted status */ +#define SDIOC_HOST_FLAG_BRE (SDIOC_PSTAT_BRE) /*!< Data buffer full status */ +#define SDIOC_HOST_FLAG_BWE (SDIOC_PSTAT_BWE) /*!< Data buffer empty status */ +#define SDIOC_HOST_FLAG_RTA (SDIOC_PSTAT_RTA) /*!< Read operation status */ +#define SDIOC_HOST_FLAG_WTA (SDIOC_PSTAT_WTA) /*!< Write operation status */ +#define SDIOC_HOST_FLAG_DA (SDIOC_PSTAT_DA) /*!< DAT Line transfer status */ +#define SDIOC_HOST_FLAG_CID (SDIOC_PSTAT_CID) /*!< Command Inhibit with data status */ +#define SDIOC_HOST_FLAG_CIC (SDIOC_PSTAT_CIC) /*!< Command Inhibit status */ +#define SDIOC_HOST_FLAG_ALL (SDIOC_HOST_FLAG_CMDL | SDIOC_HOST_FLAG_DATL | SDIOC_HOST_FLAG_WPL | \ + SDIOC_HOST_FLAG_CDL | SDIOC_HOST_FLAG_CSS | SDIOC_HOST_FLAG_CIN | \ + SDIOC_HOST_FLAG_BRE | SDIOC_HOST_FLAG_BWE | SDIOC_HOST_FLAG_RTA | \ + SDIOC_HOST_FLAG_WTA | SDIOC_HOST_FLAG_DA | SDIOC_HOST_FLAG_CID | \ + SDIOC_HOST_FLAG_CIC) +/** + * @} + */ + +/** + * @defgroup SDIOC_Interrupt_Flag SDIOC Interrupt Flag + * @{ + */ +#define SDIOC_INT_FLAG_EI (SDIOC_NORINTST_EI) /*!< Error Interrupt Status */ +#define SDIOC_INT_FLAG_CINT (SDIOC_NORINTST_CINT) /*!< Card Interrupt status */ +#define SDIOC_INT_FLAG_CRM (SDIOC_NORINTST_CRM) /*!< Card Removal status */ +#define SDIOC_INT_FLAG_CIST (SDIOC_NORINTST_CIST) /*!< Card Insertion status */ +#define SDIOC_INT_FLAG_BRR (SDIOC_NORINTST_BRR) /*!< Buffer Read Ready status */ +#define SDIOC_INT_FLAG_BWR (SDIOC_NORINTST_BWR) /*!< Buffer Write Ready status */ +#define SDIOC_INT_FLAG_BGE (SDIOC_NORINTST_BGE) /*!< Block Gap Event status */ +#define SDIOC_INT_FLAG_TC (SDIOC_NORINTST_TC) /*!< Transfer Complete status */ +#define SDIOC_INT_FLAG_CC (SDIOC_NORINTST_CC) /*!< Command Complete status */ +#define SDIOC_INT_FLAG_ACE ((uint32_t)SDIOC_ERRINTST_ACE << 16U) /*!< Auto CMD12 Error Status */ +#define SDIOC_INT_FLAG_DEBE ((uint32_t)SDIOC_ERRINTST_DEBE << 16U) /*!< Data End Bit Error status */ +#define SDIOC_INT_FLAG_DCE ((uint32_t)SDIOC_ERRINTST_DCE << 16U) /*!< Data CRC Error status */ +#define SDIOC_INT_FLAG_DTOE ((uint32_t)SDIOC_ERRINTST_DTOE << 16U) /*!< Data Timeout Error status */ +#define SDIOC_INT_FLAG_CIE ((uint32_t)SDIOC_ERRINTST_CIE << 16U) /*!< Command Index Error status */ +#define SDIOC_INT_FLAG_CEBE ((uint32_t)SDIOC_ERRINTST_CEBE << 16U) /*!< Command End Bit Error status */ +#define SDIOC_INT_FLAG_CCE ((uint32_t)SDIOC_ERRINTST_CCE << 16U) /*!< Command CRC Error status */ +#define SDIOC_INT_FLAG_CTOE ((uint32_t)SDIOC_ERRINTST_CTOE << 16U) /*!< Command Timeout Error status */ +#define SDIOC_INT_STATIC_FLAGS (SDIOC_INT_FLAG_ACE | SDIOC_INT_FLAG_DEBE | SDIOC_INT_FLAG_DCE | \ + SDIOC_INT_FLAG_DTOE | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | \ + SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE | SDIOC_INT_FLAG_TC | \ + SDIOC_INT_FLAG_CC) +#define SDIOC_NORMAL_INT_FLAG_ALL (SDIOC_INT_FLAG_EI | SDIOC_INT_FLAG_CINT | SDIOC_INT_FLAG_CRM | \ + SDIOC_INT_FLAG_CIST | SDIOC_INT_FLAG_BRR | SDIOC_INT_FLAG_BWR | \ + SDIOC_INT_FLAG_BGE | SDIOC_INT_FLAG_TC | SDIOC_INT_FLAG_CC) +#define SDIOC_ERR_INT_FLAG_ALL (SDIOC_INT_FLAG_ACE | SDIOC_INT_FLAG_DEBE | SDIOC_INT_FLAG_DCE | \ + SDIOC_INT_FLAG_DTOE | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | \ + SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE) +#define SDIOC_INT_FLAG_ALL (SDIOC_NORMAL_INT_FLAG_ALL | SDIOC_ERR_INT_FLAG_ALL) +#define SDIOC_INT_FLAG_CLR_ALL (SDIOC_INT_FLAG_CRM | SDIOC_INT_FLAG_CIST | SDIOC_INT_FLAG_BRR | \ + SDIOC_INT_FLAG_BWR | SDIOC_INT_FLAG_BGE | SDIOC_INT_FLAG_TC | \ + SDIOC_INT_FLAG_CC | SDIOC_ERR_INT_FLAG_ALL) +/** + * @} + */ + +/** + * @defgroup SDIOC_Interrupt SDIOC Interrupt + * @{ + */ +#define SDIOC_INT_CINTSEN (SDIOC_NORINTSGEN_CINTSEN) /*!< Card Interrupt */ +#define SDIOC_INT_CRMSEN (SDIOC_NORINTSGEN_CRMSEN) /*!< Card Removal Interrupt */ +#define SDIOC_INT_CISTSEN (SDIOC_NORINTSGEN_CISTSEN) /*!< Card Insertion Interrupt */ +#define SDIOC_INT_BRRSEN (SDIOC_NORINTSGEN_BRRSEN) /*!< Buffer Read Ready Interrupt */ +#define SDIOC_INT_BWRSEN (SDIOC_NORINTSGEN_BWRSEN) /*!< Buffer Write Ready Interrupt */ +#define SDIOC_INT_BGESEN (SDIOC_NORINTSGEN_BGESEN) /*!< Block Gap Event Interrupt */ +#define SDIOC_INT_TCSEN (SDIOC_NORINTSGEN_TCSEN) /*!< Transfer Complete Interrupt */ +#define SDIOC_INT_CCSEN (SDIOC_NORINTSGEN_CCSEN) /*!< Command Complete Interrupt */ +#define SDIOC_INT_ACESEN ((uint32_t)SDIOC_ERRINTSGEN_ACESEN << 16U) /*!< Auto CMD12 Error Interrupt */ +#define SDIOC_INT_DEBESEN ((uint32_t)SDIOC_ERRINTSGEN_DEBESEN << 16U) /*!< Data End Bit Error Interrupt */ +#define SDIOC_INT_DCESEN ((uint32_t)SDIOC_ERRINTSGEN_DCESEN << 16U) /*!< Data CRC Error Interrupt */ +#define SDIOC_INT_DTOESEN ((uint32_t)SDIOC_ERRINTSGEN_DTOESEN << 16U) /*!< Data Timeout Error Interrupt */ +#define SDIOC_INT_CIESEN ((uint32_t)SDIOC_ERRINTSGEN_CIESEN << 16U) /*!< Command Index Error Interrupt */ +#define SDIOC_INT_CEBESEN ((uint32_t)SDIOC_ERRINTSGEN_CEBESEN << 16U) /*!< Command End Bit Error Interrupt */ +#define SDIOC_INT_CCESEN ((uint32_t)SDIOC_ERRINTSGEN_CCESEN << 16U) /*!< Command CRC Error Interrupt */ +#define SDIOC_INT_CTOESEN ((uint32_t)SDIOC_ERRINTSGEN_CTOESEN << 16U) /*!< Command Timeout Error Interrupt */ +#define SDIOC_NORMAL_INT_ALL (SDIOC_INT_CINTSEN | SDIOC_INT_CRMSEN | SDIOC_INT_CISTSEN | \ + SDIOC_INT_BRRSEN | SDIOC_INT_BWRSEN | SDIOC_INT_BGESEN | \ + SDIOC_INT_TCSEN | SDIOC_INT_CCSEN) +#define SDIOC_ERR_INT_ALL (SDIOC_INT_ACESEN | SDIOC_INT_DEBESEN | SDIOC_INT_DCESEN | \ + SDIOC_INT_DTOESEN | SDIOC_INT_CIESEN | SDIOC_INT_CEBESEN | \ + SDIOC_INT_CCESEN | SDIOC_INT_CTOESEN) +#define SDIOC_INT_ALL (SDIOC_NORMAL_INT_ALL | SDIOC_ERR_INT_ALL) +/** + * @} + */ + +/** + * @defgroup SDIOC_Auto_CMD_Error_Flag SDIOC Auto CMD Error Flag + * @{ + */ +#define SDIOC_AUTO_CMD_ERR_FLAG_CMDE (SDIOC_ATCERRST_CMDE) /*!< Command Not Issued By Auto CMD12 Error Status */ +#define SDIOC_AUTO_CMD_ERR_FLAG_IE (SDIOC_ATCERRST_IE) /*!< Auto CMD12 Index Error status */ +#define SDIOC_AUTO_CMD_ERR_FLAG_EBE (SDIOC_ATCERRST_EBE) /*!< Auto CMD12 End Bit Error status */ +#define SDIOC_AUTO_CMD_ERR_FLAG_CE (SDIOC_ATCERRST_CE) /*!< Auto CMD12 CRC Error status */ +#define SDIOC_AUTO_CMD_ERR_FLAG_TOE (SDIOC_ATCERRST_TOE) /*!< Auto CMD12 Timeout Error status */ +#define SDIOC_AUTO_CMD_ERR_FLAG_NE (SDIOC_ATCERRST_NE) /*!< Auto CMD12 Not Executed status */ +#define SDIOC_AUTO_CMD_ERR_FLAG_ALL (SDIOC_AUTO_CMD_ERR_FLAG_CMDE | SDIOC_AUTO_CMD_ERR_FLAG_IE | \ + SDIOC_AUTO_CMD_ERR_FLAG_EBE | SDIOC_AUTO_CMD_ERR_FLAG_CE | \ + SDIOC_AUTO_CMD_ERR_FLAG_TOE | SDIOC_AUTO_CMD_ERR_FLAG_NE) +/** + * @} + */ + +/** + * @defgroup SDIOC_Force_Auto_CMD_Error SDIOC Force Auto CMD Error + * @{ + */ +#define SDIOC_FORCE_AUTO_CMD_ERR_FCMDE (SDIOC_FEA_FCMDE) /*!< Force Event for Command Not Issued By Auto CMD12 Error */ +#define SDIOC_FORCE_AUTO_CMD_ERR_FIE (SDIOC_FEA_FIE) /*!< Force Event for Auto CMD12 Index Error */ +#define SDIOC_FORCE_AUTO_CMD_ERR_FEBE (SDIOC_FEA_FEBE) /*!< Force Event for Auto CMD12 End Bit Error */ +#define SDIOC_FORCE_AUTO_CMD_ERR_FCE (SDIOC_FEA_FCE) /*!< Force Event for Auto CMD12 CRC Error */ +#define SDIOC_FORCE_AUTO_CMD_ERR_FTOE (SDIOC_FEA_FTOE) /*!< Force Event for Auto CMD12 Timeout Error */ +#define SDIOC_FORCE_AUTO_CMD_ERR_FNE (SDIOC_FEA_FNE) /*!< Force Event for Auto CMD12 Not Executed */ +#define SDIOC_FORCE_AUTO_CMD_ERR_ALL (SDIOC_FORCE_AUTO_CMD_ERR_FCMDE | SDIOC_FORCE_AUTO_CMD_ERR_FIE | \ + SDIOC_FORCE_AUTO_CMD_ERR_FEBE | SDIOC_FORCE_AUTO_CMD_ERR_FCE | \ + SDIOC_FORCE_AUTO_CMD_ERR_FTOE | SDIOC_FORCE_AUTO_CMD_ERR_FNE) +/** + * @} + */ + +/** + * @defgroup SDIOC_Force_Error_Interrupt SDIOC Force Error Interrupt + * @{ + */ +#define SDIOC_FORCE_ERR_INT_FACE (SDIOC_FEE_FACE) /*!< Force Event for Auto CMD12 Error */ +#define SDIOC_FORCE_ERR_INT_FDEBE (SDIOC_FEE_FDEBE) /*!< Force Event for Data End Bit Error */ +#define SDIOC_FORCE_ERR_INT_FDCE (SDIOC_FEE_FDCE) /*!< Force Event for Data CRC Error */ +#define SDIOC_FORCE_ERR_INT_FDTOE (SDIOC_FEE_FDTOE) /*!< Force Event for Data Timeout Error */ +#define SDIOC_FORCE_ERR_INT_FCIE (SDIOC_FEE_FCIE) /*!< Force Event for Command Index Error */ +#define SDIOC_FORCE_ERR_INT_FCEBE (SDIOC_FEE_FCEBE) /*!< Force Event for Command End Bit Error */ +#define SDIOC_FORCE_ERR_INT_FCCE (SDIOC_FEE_FCCE) /*!< Force Event for Command CRC Error */ +#define SDIOC_FORCE_ERR_INT_FCTOE (SDIOC_FEE_FCTOE) /*!< Force Event for Command Timeout Error */ +#define SDIOC_FORCE_ERR_INT_ALL (SDIOC_FORCE_ERR_INT_FACE | SDIOC_FORCE_ERR_INT_FDEBE | \ + SDIOC_FORCE_ERR_INT_FDCE | SDIOC_FORCE_ERR_INT_FDTOE | \ + SDIOC_FORCE_ERR_INT_FCIE | SDIOC_FORCE_ERR_INT_FCEBE | \ + SDIOC_FORCE_ERR_INT_FCCE | SDIOC_FORCE_ERR_INT_FCTOE) +/** + * @} + */ + +/** + * @defgroup SDIOC_Response_Type SDIOC Response Type + * @{ + */ +#define SDIOC_RESP_TYPE_NO (0x00U) /*!< No Response */ +#define SDIOC_RESP_TYPE_R2 (SDIOC_CMD_RESTYP_0) /*!< Command Response 2 */ +#define SDIOC_RESP_TYPE_R3_R4 (SDIOC_CMD_RESTYP_1) /*!< Command Response 3, 4 */ +#define SDIOC_RESP_TYPE_R1_R5_R6_R7 (SDIOC_CMD_RESTYP_1 | SDIOC_CMD_ICE | SDIOC_CMD_CCE) /*!< Command Response 1, 5, 6, 7 */ +#define SDIOC_RESP_TYPE_R1B_R5B (SDIOC_CMD_RESTYP | SDIOC_CMD_ICE | SDIOC_CMD_CCE) /*!< Command Response 1 and 5 with busy */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Command SDIOC Command + * @{ + */ +/** + * @defgroup SDIOC_SDMMC_CMD SDIOC SDMMC CMD + * @{ + */ +#define SDIOC_CMD0_GO_IDLE_STATE (0U) /*!< Resets the SD memory card. */ +#define SDIOC_CMD1_SEND_OP_COND (1U) /*!< Sends host capacity support information and activates the card's initialization process. */ +#define SDIOC_CMD2_ALL_SEND_CID (2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define SDIOC_CMD3_SEND_RELATIVE_ADDR (3U) /*!< Asks the card to publish a new relative address (RCA). */ +#define SDIOC_CMD4_SET_DSR (4U) /*!< Programs the DSR of all cards. */ +#define SDIOC_CMD5_IO_SEND_OP_COND (5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its \ + operating condition register (OCR) content in the response on the CMD line. */ +#define SDIOC_CMD6_SWITCH_FUNC (6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define SDIOC_CMD7_SELECT_DESELECT_CARD (7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define SDIOC_CMD8_SEND_IF_COND (8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information \ + and asks the card whether card supports voltage. */ +#define SDIOC_CMD9_SEND_CSD (9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define SDIOC_CMD10_SEND_CID (10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define SDIOC_CMD11_READ_DAT_UNTIL_STOP (11U) /*!< SD card doesn't support it. */ +#define SDIOC_CMD12_STOP_TRANSMISSION (12U) /*!< Forces the card to stop transmission. */ +#define SDIOC_CMD13_SEND_STATUS (13U) /*!< Addressed card sends its status register. */ +#define SDIOC_CMD14_HS_BUSTEST_READ (14U) /*!< Reserved */ +#define SDIOC_CMD15_GO_INACTIVE_STATE (15U) /*!< Sends an addressed card into the inactive state. */ +#define SDIOC_CMD16_SET_BLOCKLEN (16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands(read, write). \ + Default block length is fixed to 512 Bytes. Not effective for SDHS and SDXC. */ +#define SDIOC_CMD17_READ_SINGLE_BLOCK (17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed \ + 512 bytes in case of SDHC and SDXC. */ +#define SDIOC_CMD18_READ_MULTI_BLOCK (18U) /*!< Continuously transfers data blocks from card to host until interrupted by \ + STOP_TRANSMISSION command. */ +#define SDIOC_CMD19_HS_BUSTEST_WRITE (19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define SDIOC_CMD20_WRITE_DAT_UNTIL_STOP (20U) /*!< Speed class control command. */ +#define SDIOC_CMD23_SET_BLOCK_COUNT (23U) /*!< Specify block count for CMD18 and CMD25. */ +#define SDIOC_CMD24_WRITE_SINGLE_BLOCK (24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed\ + 512 bytes in case of SDHC and SDXC. */ +#define SDIOC_CMD25_WRITE_MULTI_BLOCK (25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define SDIOC_CMD26_PROGRAM_CID (26U) /*!< Reserved for manufacturers. */ +#define SDIOC_CMD27_PROGRAM_CSD (27U) /*!< Programming of the programmable bits of the CSD. */ +#define SDIOC_CMD28_SET_WRITE_PROT (28U) /*!< Sets the write protection bit of the addressed group. */ +#define SDIOC_CMD29_CLR_WRITE_PROT (29U) /*!< Clears the write protection bit of the addressed group. */ +#define SDIOC_CMD30_SEND_WRITE_PROT (30U) /*!< Asks the card to send the status of the write protection bits. */ +#define SDIOC_CMD32_ERASE_WR_BLK_START (32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define SDIOC_CMD33_ERASE_WR_BLK_END (33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define SDIOC_CMD35_ERASE_GROUP_START (35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system \ + set by switch function command (CMD6). */ +#define SDIOC_CMD36_ERASE_GROUP_END (36U) /*!< Sets the address of the last write block of the continuous range to be erased. \ + Reserved for each command system set by switch function command (CMD6). */ +#define SDIOC_CMD38_ERASE (38U) /*!< Reserved for SD security applications. */ +#define SDIOC_CMD39_FAST_IO (39U) /*!< SD card doesn't support it (Reserved). */ +#define SDIOC_CMD40_GO_IRQ_STATE (40U) /*!< SD card doesn't support it (Reserved). */ +#define SDIOC_CMD42_LOCK_UNLOCK (42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by \ + the SET_BLOCK_LEN command. */ +#define SDIOC_CMD52_IO_RW_DIRECT (52U) /*!< For SD I/O card only, access a single I/O register. */ +#define SDIOC_CMD53_IO_RW_EXTENDED (53U) /*!< For SD I/O card only, access multiple I/O registers with a single command. */ +#define SDIOC_CMD55_APP_CMD (55U) /*!< Indicates to the card that the next command is an application specific command rather \ + than a standard command. */ +#define SDIOC_CMD56_GEN_CMD (56U) /*!< Used either to transfer a data block to the card or to get a data block from the card \ + for general purpose/application specific commands. */ +#define SDIOC_CMD64_NO_CMD (64U) /*!< No command */ +/** + * @} + */ + +/** + * @defgroup SDIOC_SDMMC_ACMD SDIOC SDMMC ACMD + * @{ + */ +/* Following commands are SD Card Specific commands. SDIOC_CMD55_APP_CMD should be sent before sending these commands. */ +#define SDIOC_ACMD6_SET_BUS_WIDTH (6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus \ + widths are given in SCR register. */ +#define SDIOC_ACMD13_SD_STATUS (13U) /*!< (ACMD13) Sends the SD status. */ +#define SDIOC_ACMD22_SEND_NUM_WR_BLOCKS (22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with \ + 32bit+CRC data block. */ +#define SDIOC_ACMD23_SET_WR_BLK_ERASE_COUNT (23U) /*!< Set the number of write blocks to be pre-erased before writing (to be used for faster \ + Multiple Block WR command). */ +#define SDIOC_ACMD41_SD_APP_OP_COND (41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to \ + send its operating condition register (OCR) content in the response on the CMD line. */ +#define SDIOC_ACMD42_SET_CLR_CARD_DETECT (42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ +#define SDIOC_ACMD51_SEND_SCR (51U) /*!< Reads the SD Configuration Register (SCR). */ + +#define SDIOC_ACMD43_GET_MKB (43U) +#define SDIOC_ACMD44_GET_MID (44U) +#define SDIOC_ACMD45_SET_CER_RN1 (45U) +#define SDIOC_ACMD46_GET_CER_RN2 (46U) +#define SDIOC_ACMD47_SET_CER_RES2 (47U) +#define SDIOC_ACMD48_GET_CER_RES1 (48U) +#define SDIOC_ACMD18_SECURE_READ_MULTI_BLOCK (18U) +#define SDIOC_ACMD25_SECURE_WRITE_MULTI_BLOCK (25U) +#define SDIOC_ACMD38_SECURE_ERASE (38U) +#define SDIOC_ACMD49_CHANGE_SECURE_AREA (49U) +#define SDIOC_ACMD48_SECURE_WRITE_MKB (48U) +/** + * @} + */ +/** + * @} + */ + +/** + * @defgroup SDMMC_Error_Code SDMMC Error Code + * @{ + */ +#define SDMMC_ERR_NONE (0x00000000UL) /*!< No error */ +#define SDMMC_ERR_ADDR_OUT_OF_RANGE (0x80000000UL) /*!< Error when addressed block is out of range */ +#define SDMMC_ERR_ADDR_MISALIGNED (0x40000000UL) /*!< Misaligned address */ +#define SDMMC_ERR_BLOCK_LEN_ERR (0x20000000UL) /*!< Transferred block length is not allowed for the card or the \ + number of transferred bytes does not match the block length */ +#define SDMMC_ERR_ERASE_SEQ_ERR (0x10000000UL) /*!< An error in the sequence of erase command occurs */ +#define SDMMC_ERR_BAD_ERASE_PARAM (0x08000000UL) /*!< An invalid selection for erase groups */ +#define SDMMC_ERR_WR_PROT_VIOLATION (0x04000000UL) /*!< Attempt to program a write protect block */ +#define SDMMC_ERR_LOCK_UNLOCK_FAILED (0x01000000UL) /*!< Sequence or password error has been detected in unlock command \ + or if there was an attempt to access a locked card */ +#define SDMMC_ERR_COM_CRC_FAILED (0x00800000UL) /*!< CRC check of the previous command failed */ +#define SDMMC_ERR_ILLEGAL_CMD (0x00400000UL) /*!< Command is not legal for the card state */ +#define SDMMC_ERR_CARD_ECC_FAILED (0x00200000UL) /*!< Card internal ECC was applied but failed to correct the data */ +#define SDMMC_ERR_CC_ERR (0x00100000UL) /*!< Internal card controller error */ +#define SDMMC_ERR_GENERAL_UNKNOWN_ERR (0x00080000UL) /*!< General or unknown error */ +#define SDMMC_ERR_STREAM_RD_UNDERRUN (0x00040000UL) /*!< The card could not sustain data reading in stream mode */ +#define SDMMC_ERR_STREAM_WR_OVERRUN (0x00020000UL) /*!< The card could not sustain data programming in stream mode */ +#define SDMMC_ERR_CID_CSD_OVERWRITE (0x00010000UL) /*!< CID/CSD overwrite error */ +#define SDMMC_ERR_WP_ERASE_SKIP (0x00008000UL) /*!< Only partial address space was erased */ +#define SDMMC_ERR_CARD_ECC_DISABLED (0x00004000UL) /*!< Command has been executed without using internal ECC */ +#define SDMMC_ERR_ERASE_RST (0x00002000UL) /*!< Erase sequence was cleared before executing because an out of \ + erase sequence command was received */ +#define SDMMC_ERR_CMD_AUTO_SEND (0x00001000UL) /*!< An error occurred in sending the command automatically */ +#define SDMMC_ERR_CMD_INDEX (0x00000800UL) /*!< The received response contains a command number error */ +#define SDMMC_ERR_CMD_STOP_BIT (0x00000400UL) /*!< Command line detects low level at stop bit */ +#define SDMMC_ERR_CMD_CRC_FAIL (0x00000200UL) /*!< Command response received (but CRC check failed) */ +#define SDMMC_ERR_CMD_TIMEOUT (0x00000100UL) /*!< Command response timeout */ +#define SDMMC_ERR_SWITCH_ERR (0x00000080UL) /*!< The card did not switch to the expected mode as requested by \ + the SWITCH command */ +#define SDMMC_ERR_DATA_STOP_BIT (0x00000040UL) /*!< Data line detects low level at stop bit */ +#define SDMMC_ERR_DATA_CRC_FAIL (0x00000020UL) /*!< Data block sent/received (CRC check failed) */ +#define SDMMC_ERR_DATA_TIMEOUT (0x00000010UL) /*!< Data timeout */ +#define SDMMC_ERR_AKE_SEQ_ERR (0x00000008UL) /*!< Error in sequence of authentication */ +#define SDMMC_ERR_INVD_VOLT (0x00000004UL) /*!< Error in case of invalid voltage range */ +#define SDMMC_ERR_REQ_NOT_APPLICABLE (0x00000002UL) /*!< Error when command request is not applicable */ +#define SDMMC_ERR_UNSUPPORT_FEATURE (0x00000001UL) /*!< Error when feature is unsupported */ + +#define SDMMC_ERR_BITS_MASK (0xFDFFE048UL) /*!< SD/MMC Error status bits mask */ +/** + * @} + */ + +/** + * @defgroup SDMMC_Card_Status_Bit SDMMC Card Status Bit + * @{ + */ +#define SDMMC_STATUS_CARD_IS_LOCKED_POS (24U) +#define SDMMC_STATUS_CARD_IS_LOCKED (0x02000000UL) /*!< When set, signals that the card is locked by the host */ +#define SDMMC_STATUS_CURR_STATE_POS (9U) +#define SDMMC_STATUS_CURR_STATE (0x00001E00UL) /*!< The state of the card when receiving the command */ +#define SDMMC_STATUS_RDY_FOR_DATA_POS (8U) +#define SDMMC_STATUS_RDY_FOR_DATA (0x00000100UL) /*!< Corresponds to buffer empty signaling on the bus */ +#define SDMMC_STATUS_APP_CMD_POS (5U) +#define SDMMC_STATUS_APP_CMD (0x00000020UL) /*!< The card will expect ACMD, or an indication that the command has been interpreted as ACMD */ +/** + * @} + */ + +/** + * @defgroup SDMMC_SCR_Register SDMMC SCR Register + * @{ + */ +#define SDMMC_SCR_PHY_SPEC_VER_1P0 (0x00000000UL) +#define SDMMC_SCR_PHY_SPEC_VER_1P1 (0x01000000UL) +#define SDMMC_SCR_PHY_SPEC_VER_2P0 (0x02000000UL) +#define SDMMC_SCR_BUS_WIDTH_4BIT (0x00040000UL) +#define SDMMC_SCR_BUS_WIDTH_1BIT (0x00010000UL) +/** + * @} + */ + +/** + * @defgroup SDMMC_OCR_Register SDMMC OCR Register + * @{ + */ +#define SDMMC_OCR_HIGH_CAPACITY (0x40000000UL) +#define SDMMC_OCR_STD_CAPACITY (0x00000000UL) +/** + * @} + */ + +/** + * @defgroup SDMMC_CSD_Register SDMMC CSD Register + * @{ + */ +/* Command Class supported */ +#define SDMMC_CSD_SUPPORT_CLASS5_ERASE (0x00000020UL) +/** + * @} + */ + +/** + * @defgroup SDMMC_Common_Parameter SDMMC Common Parameter + * @{ + */ +#define SDMMC_DATA_TIMEOUT (0x0000FFFFUL) +#define SDMMC_MAX_VOLT_TRIAL (0x0000FFFFUL) +/** + * @} + */ + +/** + * @defgroup SDMMC_IO_Command_Arguments SDMMC IO Command Arguments + * @{ + */ +/** + * @defgroup SDIO_CMD52_Arguments SDIO CMD52 Arguments + * @{ + */ +/** + * @defgroup SDIO_CMD52_Arguments_RW_Flag SDIO CMD52 Arguments RW_Flag + * @{ + */ +#define SDIO_CMD52_ARG_RD (0UL << 31) +#define SDIO_CMD52_ARG_WR (1UL << 31) +/** + * @} + */ + +/** + * @defgroup SDIO_CMD52_Arguments_RAW_Flag SDIO CMD52 Arguments RAW Flag + * @{ + */ +#define SDIO_CMD52_ARG_RAW_FLAG_0 (0UL << 27) +#define SDIO_CMD52_ARG_RAW_FLAG_1 (1UL << 27) +/** + * @} + */ +/** + * @} + */ + +/** + * @defgroup SDIO_CMD53_Arguments SDIO CMD53 Arguments + * @{ + */ +/** + * @defgroup SDIO_CMD53_Arguments_RW_Flag SDIO CMD53 Arguments RW_Flag + * @{ + */ +#define SDIO_CMD53_ARG_RD (0UL << 31) +#define SDIO_CMD53_ARG_WR (1UL << 31) +/** + * @} + */ + +/** + * @defgroup SDIO_CMD53_Arguments_Block_Mode SDIO CMD53 Arguments Block Mode + * @{ + */ +#define SDIO_CMD53_ARG_TRANS_MD_BYTE (0UL << 27) +#define SDIO_CMD53_ARG_TRANS_MD_BLOCK (1UL << 27) +/** + * @} + */ + +/** + * @defgroup SDIO_CMD53_Arguments_Operate_Code SDIO CMD53 Arguments Operate Code + * @{ + */ +#define SDIO_CMD53_ARG_OP_CODE_ADDR_FIX (0UL << 26) +#define SDIO_CMD53_ARG_OP_CODE_ADDR_INC (1UL << 26) +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup SDIOC_Global_Functions + * @{ + */ +int32_t SDIOC_DeInit(CM_SDIOC_TypeDef *SDIOCx); +int32_t SDIOC_Init(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_init_t *pstcSdiocInit); +int32_t SDIOC_StructInit(stc_sdioc_init_t *pstcSdiocInit); +int32_t SDIOC_SWReset(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Type); +void SDIOC_PowerCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState); +en_functional_state_t SDIOC_GetPowerState(const CM_SDIOC_TypeDef *SDIOCx); +uint32_t SDIOC_GetMode(const CM_SDIOC_TypeDef *SDIOCx); +void SDIOC_ClockCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState); +void SDIOC_SetClockDiv(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Div); +int32_t SDIOC_GetOptimumClockDiv(uint32_t u32ClockFreq, uint16_t *pu16Div); +int32_t SDIOC_VerifyClockDiv(uint32_t u32Mode, uint8_t u8SpeedMode, uint16_t u16ClockDiv); +en_flag_status_t SDIOC_GetInsertStatus(const CM_SDIOC_TypeDef *SDIOCx); +void SDIOC_SetSpeedMode(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8SpeedMode); +void SDIOC_SetBusWidth(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8BusWidth); +void SDIOC_SetCardDetectSrc(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Src); +void SDIOC_SetCardDetectTestLevel(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Level); + +int32_t SDIOC_SendCommand(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_cmd_config_t *pstcCmdConfig); +int32_t SDIOC_CommandStructInit(stc_sdioc_cmd_config_t *pstcCmdConfig); +int32_t SDIOC_GetResponse(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Reg, uint32_t *pu32Value); +int32_t SDIOC_ConfigData(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_data_config_t *pstcDataConfig); +int32_t SDIOC_DataStructInit(stc_sdioc_data_config_t *pstcDataConfig); +int32_t SDIOC_ReadBuffer(CM_SDIOC_TypeDef *SDIOCx, uint8_t au8Data[], uint32_t u32Len); +int32_t SDIOC_WriteBuffer(CM_SDIOC_TypeDef *SDIOCx, const uint8_t au8Data[], uint32_t u32Len); + +void SDIOC_BlockGapStopCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState); +void SDIOC_RestartTrans(CM_SDIOC_TypeDef *SDIOCx); +void SDIOC_ReadWaitCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState); +void SDIOC_BlockGapIntCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState); + +void SDIOC_IntCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType, en_functional_state_t enNewState); +en_functional_state_t SDIOC_GetIntEnableState(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType); +void SDIOC_IntStatusCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t SDIOC_GetIntStatus(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag); +void SDIOC_ClearIntStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag); +en_flag_status_t SDIOC_GetHostStatus(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag); +en_flag_status_t SDIOC_GetAutoCmdErrorStatus(const CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Flag); +void SDIOC_ForceAutoCmdErrorEvent(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Event); +void SDIOC_ForceErrorIntEvent(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Event); + +/* SDMMC Commands management functions */ +int32_t SDMMC_CMD0_GoIdleState(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD2_AllSendCID(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD3_SendRelativeAddr(CM_SDIOC_TypeDef *SDIOCx, uint16_t *pu16RCA, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD6_SwitchFunc(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD7_SelectDeselectCard(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD8_SendInterfaceCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD9_SendCSD(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD12_StopTrans(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD13_SendStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD16_SetBlockLength(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32BlockLen, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD17_ReadSingleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD18_ReadMultipleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD24_WriteSingleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD25_WriteMultipleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD32_EraseBlockStartAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD33_EraseBlockEndAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD38_Erase(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD55_AppCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus); + +int32_t SDMMC_ACMD6_SetBusWidth(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32BusWidth, uint32_t *pu32ErrStatus); +int32_t SDMMC_ACMD13_SendStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); +int32_t SDMMC_ACMD41_SendOperateCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus); +int32_t SDMMC_ACMD51_SendSCR(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); + +int32_t SDMMC_CMD1_SendOperateCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD35_EraseGroupStartAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD36_EraseGroupEndAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrStatus); + +int32_t SDMMC_CMD5_IOSendOperateCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD52_IORwDirect(CM_SDIOC_TypeDef *SDIOCx, const stc_sdio_cmd52_arg_t *pstcCmdArg, + uint8_t u8In, uint8_t *pu8Out, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD53_IORwExtended(CM_SDIOC_TypeDef *SDIOCx, const stc_sdio_cmd53_arg_t *pstcCmdArg, + uint32_t *pu32ErrStatus); + +/** + * @} + */ + +#endif /* LL_SDIOC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_SDIOC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_spi.h b/mcu/lib/inc/hc32_ll_spi.h new file mode 100644 index 0000000..5de00ee --- /dev/null +++ b/mcu/lib/inc/hc32_ll_spi.h @@ -0,0 +1,457 @@ +/** + ******************************************************************************* + * @file hc32_ll_spi.h + * @brief This file contains all the functions prototypes of the SPI driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-06-30 CDT Add SPI_SetSckPolarity,SPI_SetSckPhase functions + Add group SPI_SCK_Polarity_Define, SPI_SCK_Phase_Define + Modify return type of fuction SPI_DeInit + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_SPI_H__ +#define __HC32_LL_SPI_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_SPI + * @{ + */ + +#if (LL_SPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup SPI_Global_Types SPI Global Types + * @{ + */ + +/** + * @brief Structure definition of SPI initialization. + */ +typedef struct { + uint32_t u32WireMode; /*!< SPI wire mode, 3 wire mode or 4 wire mode. + This parameter can be a value of @ref SPI_Wire_Mode_Define */ + uint32_t u32TransMode; /*!< SPI transfer mode, send only or full duplex. + This parameter can be a value of @ref SPI_Trans_Mode_Define */ + uint32_t u32MasterSlave; /*!< SPI master/slave mode. + This parameter can be a value of @ref SPI_Master_Slave_Mode_Define */ + uint32_t u32ModeFaultDetect; /*!< SPI mode fault detect command. + This parameter can be a value of @ref SPI_Mode_Fault_Detect_Command_Define */ + uint32_t u32Parity; /*!< SPI parity check selection. + This parameter can be a value of @ref SPI_Parity_Check_Define */ + uint32_t u32SpiMode; /*!< SPI mode. + This parameter can be a value of @ref SPI_Mode_Define */ + uint32_t u32BaudRatePrescaler; /*!< SPI baud rate prescaler. + This parameter can be a value of @ref SPI_Baud_Rate_Prescaler_Define */ + uint32_t u32DataBits; /*!< SPI data bits, 4 bits ~ 32 bits. + This parameter can be a value of @ref SPI_Data_Size_Define */ + uint32_t u32FirstBit; /*!< MSB first or LSB first. + This parameter can be a value of @ref SPI_First_Bit_Define */ + uint32_t u32SuspendMode; /*!< SPI communication suspend function. + This parameter can be a value of @ref SPI_Com_Suspend_Func_Define */ + uint32_t u32FrameLevel; /*!< SPI frame level, SPI_1_FRAME ~ SPI_4_FRAME. + This parameter can be a value of @ref SPI_Frame_Level_Define */ +} stc_spi_init_t; + +/** + * @brief Structure definition of SPI delay time configuration. + */ +typedef struct { + uint32_t u32IntervalDelay; /*!< SPI interval time delay (Next access delay time) + This parameter can be a value of @ref SPI_Interval_Delay_Time_define */ + uint32_t u32ReleaseDelay; /*!< SPI release time delay (SCK invalid delay time) + This parameter can be a value of @ref SPI_Release_Delay_Time_define */ + uint32_t u32SetupDelay; /*!< SPI Setup time delay (SCK valid delay time) define + This parameter can be a value of @ref SPI_Setup_Delay_Time_define */ +} stc_spi_delay_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SPI_Global_Macros SPI Global Macros + * @{ + */ + +/** + * @defgroup SPI_Wire_Mode_Define SPI Wire Mode Define + * @{ + */ +#define SPI_4_WIRE (0UL) +#define SPI_3_WIRE (SPI_CR1_SPIMDS) +/** + * @} + */ + +/** + * @defgroup SPI_Trans_Mode_Define SPI Transfer Mode Define + * @{ + */ +#define SPI_FULL_DUPLEX (0UL) /*!< Full duplex. */ +#define SPI_SEND_ONLY (SPI_CR1_TXMDS) /*!< Send only. */ +/** + * @} + */ + +/** + * @defgroup SPI_Master_Slave_Mode_Define SPI Master Slave Mode Define + * @{ + */ +#define SPI_SLAVE (0UL) +#define SPI_MASTER (SPI_CR1_MSTR) +/** + * @} + */ + +/** + * @defgroup SPI_Loopback_Selection_Define SPI Loopback Selection Define + * @note Loopback mode is mainly used for parity self-diagnosis in 4-wire full-duplex mode. + * @{ + */ +#define SPI_LOOPBACK_INVD (0UL) +#define SPI_LOOPBACK_MOSI_INVT (SPI_CR1_SPLPBK) /*!< MISO data is the inverse of the data output by MOSI. */ +#define SPI_LOOPBACK_MOSI (SPI_CR1_SPLPBK2) /*!< MISO data is the data output by MOSI. */ +/** + * @} + */ + +/** + * @defgroup SPI_Int_Type_Define SPI Interrupt Type Define + * @{ + */ +#define SPI_INT_ERR (SPI_CR1_EIE) /*!< Including overload, underload and parity error. */ +#define SPI_INT_TX_BUF_EMPTY (SPI_CR1_TXIE) +#define SPI_INT_RX_BUF_FULL (SPI_CR1_RXIE) +#define SPI_INT_IDLE (SPI_CR1_IDIE) +#define SPI_IRQ_ALL (SPI_INT_ERR | SPI_INT_TX_BUF_EMPTY | SPI_INT_RX_BUF_FULL | SPI_INT_IDLE ) +/** + * @} + */ + +/** + * @defgroup SPI_Mode_Fault_Detect_Command_Define SPI Mode Fault Detect Command Define + * @{ + */ +#define SPI_MD_FAULT_DETECT_DISABLE (0UL) /*!< Disable mode fault detection. */ +#define SPI_MD_FAULT_DETECT_ENABLE (SPI_CR1_MODFE) /*!< Enable mode fault detection. */ +/** + * @} + */ + +/** + * @defgroup SPI_Parity_Check_Define SPI Parity Check Mode Define + * @{ + */ +#define SPI_PARITY_INVD (0UL) /*!< Parity check invalid. */ +#define SPI_PARITY_EVEN (SPI_CR1_PAE) /*!< Parity check selection even parity. */ +#define SPI_PARITY_ODD (SPI_CR1_PAE | SPI_CR1_PAOE) /*!< Parity check selection odd parity. */ +/** + * @} + */ + +/** + * @defgroup SPI_SS_Pin_Define SPI SSx Define + * @{ + */ +#define SPI_PIN_SS0 (SPI_CFG1_SS0PV) +#define SPI_PIN_SS1 (SPI_CFG1_SS1PV) +#define SPI_PIN_SS2 (SPI_CFG1_SS2PV) +#define SPI_PIN_SS3 (SPI_CFG1_SS3PV) +/** + * @} + */ + +/** + * @defgroup SPI_Read_Target_Buf_Define SPI Read Data Register Target Buffer Define + * @{ + */ +#define SPI_RD_TARGET_RD_BUF (0UL) /*!< Read RX buffer. */ +#define SPI_RD_TARGET_WR_BUF (SPI_CFG1_SPRDTD) /*!< Read TX buffer. */ +/** + * @} + */ + +/** + * @defgroup SPI_Frame_Level_Define SPI data frame level define, The Data in the SPI_DR register will be send to TX_BUFF + * after enough data frame write to the SPI_DR + * @{ + */ +#define SPI_1_FRAME (0UL) /*!< Data 1 frame */ +#define SPI_2_FRAME (SPI_CFG1_FTHLV_0) /*!< Data 2 frame.*/ +#define SPI_3_FRAME (SPI_CFG1_FTHLV_1) /*!< Data 3 frame.*/ +#define SPI_4_FRAME (SPI_CFG1_FTHLV) /*!< Data 4 frame.*/ +/** + * @} + */ + +/** + * @defgroup SPI_Interval_Delay_Time_define SPI Interval Time Delay (Next Access Delay Time) define + * @{ + */ +#define SPI_INTERVAL_TIME_1SCK (0UL << SPI_CFG1_MIDI_POS) /*!< 1 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_2SCK (1UL << SPI_CFG1_MIDI_POS) /*!< 2 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_3SCK (2UL << SPI_CFG1_MIDI_POS) /*!< 3 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_4SCK (3UL << SPI_CFG1_MIDI_POS) /*!< 4 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_5SCK (4UL << SPI_CFG1_MIDI_POS) /*!< 5 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_6SCK (5UL << SPI_CFG1_MIDI_POS) /*!< 6 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_7SCK (6UL << SPI_CFG1_MIDI_POS) /*!< 7 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_8SCK (7UL << SPI_CFG1_MIDI_POS) /*!< 8 SCK + 2 PCLK1 */ +/** + * @} + */ + +/** + * @defgroup SPI_Release_Delay_Time_define SPI Release Time Delay (SCK Invalid Delay Time) Define + * @{ + */ +#define SPI_RELEASE_TIME_1SCK (0UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_2SCK (1UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_3SCK (2UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_4SCK (3UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_5SCK (4UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_6SCK (5UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_7SCK (6UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_8SCK (7UL << SPI_CFG1_MSSDL_POS) +/** + * @} + */ + +/** + * @defgroup SPI_Setup_Delay_Time_define SPI Setup Time Delay (SCK Valid Delay Time) Define + * @{ + */ +#define SPI_SETUP_TIME_1SCK (0UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_2SCK (1UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_3SCK (2UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_4SCK (3UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_5SCK (4UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_6SCK (5UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_7SCK (6UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_8SCK (7UL << SPI_CFG1_MSSI_POS) +/** + * @} + */ + +/** + * @defgroup SPI_Com_Suspend_Func_Define SPI Communication Suspend Function Define + * @{ + */ +#define SPI_COM_SUSP_FUNC_OFF (0UL) +#define SPI_COM_SUSP_FUNC_ON (SPI_CR1_CSUSPE) +/** + * @} + */ + +/** + * @defgroup SPI_Mode_Define SPI Mode Define + * @{ + */ +#define SPI_MD_0 (0UL) /*!< SCK pin output low in idle state; \ + MOSI/MISO pin data valid in odd edge, \ + MOSI/MISO pin data change in even edge */ +#define SPI_MD_1 (SPI_CFG2_CPHA) /*!< SCK pin output low in idle state; \ + MOSI/MISO pin data valid in even edge, \ + MOSI/MISO pin data change in odd edge */ +#define SPI_MD_2 (SPI_CFG2_CPOL) /*!< SCK pin output high in idle state; \ + MOSI/MISO pin data valid in odd edge, \ + MOSI/MISO pin data change in even edge */ +#define SPI_MD_3 (SPI_CFG2_CPOL | SPI_CFG2_CPHA) /*!< SCK pin output high in idle state; \ + MOSI/MISO pin data valid in even edge, \ + MOSI/MISO pin data change in odd edge */ + +/** + * @} + */ + +/** + * @defgroup SPI_SCK_Polarity_Define SPI SCK Polarity Define + * @{ + */ +#define SPI_SCK_POLARITY_LOW (0UL) /*!< SCK pin output low in idle state */ +#define SPI_SCK_POLARITY_HIGH (SPI_CFG2_CPOL) /*!< SCK pin output high in idle state */ +/** + * @} + */ + +/** + * @defgroup SPI_SCK_Phase_Define SPI SCK Phase Define + * @{ + */ +#define SPI_SCK_PHASE_ODD_EDGE_SAMPLE (0UL) /*!< MOSI/MISO pin data sample in odd edge, MOSI/MISO pin data change in even edge */ +#define SPI_SCK_PHASE_EVEN_EDGE_SAMPLE (SPI_CFG2_CPHA) /*!< MOSI/MISO pin data sample in even edge, MOSI/MISO pin data change in odd edge */ +/** + * @} + */ + +/** + * @defgroup SPI_Baud_Rate_Prescaler_Define SPI Baudrate Prescaler Define + * @{ + */ +#define SPI_BR_CLK_DIV2 (0UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 2. */ +#define SPI_BR_CLK_DIV4 (1UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 4. */ +#define SPI_BR_CLK_DIV8 (2UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 8. */ +#define SPI_BR_CLK_DIV16 (3UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 16. */ +#define SPI_BR_CLK_DIV32 (4UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 32. */ +#define SPI_BR_CLK_DIV64 (5UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 64. */ +#define SPI_BR_CLK_DIV128 (6UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 128. */ +#define SPI_BR_CLK_DIV256 (7UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 256. */ +/** + * @} + */ + +/** + * @defgroup SPI_Data_Size_Define SPI Data Size Define + * @{ + */ +#define SPI_DATA_SIZE_4BIT (0UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_5BIT (1UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_6BIT (2UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_7BIT (3UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_8BIT (4UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_9BIT (5UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_10BIT (6UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_11BIT (7UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_12BIT (8UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_13BIT (9UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_14BIT (10UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_15BIT (11UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_16BIT (12UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_20BIT (13UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_24BIT (14UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_32BIT (15UL << SPI_CFG2_DSIZE_POS) + +/** + * @} + */ + +/** + * @defgroup SPI_First_Bit_Define SPI First Bit Define + * @{ + */ +#define SPI_FIRST_MSB (0UL) +#define SPI_FIRST_LSB (SPI_CFG2_LSBF) +/** + * @} + */ + +/** + * @defgroup SPI_State_Flag_Define SPI State Flag Define + * @{ + */ +#define SPI_FLAG_OVERLOAD (SPI_SR_OVRERF) +#define SPI_FLAG_IDLE (SPI_SR_IDLNF) +#define SPI_FLAG_MD_FAULT (SPI_SR_MODFERF) +#define SPI_FLAG_PARITY_ERR (SPI_SR_PERF) +#define SPI_FLAG_UNDERLOAD (SPI_SR_UDRERF) +#define SPI_FLAG_TX_BUF_EMPTY (SPI_SR_TDEF) /*!< This flag is set when the data in the data register \ + is copied into the shift register, but the transmission \ + of the data bit may not have been completed. */ +#define SPI_FLAG_RX_BUF_FULL (SPI_SR_RDFF) /*!< Indicates that a data was received. */ +#define SPI_FLAG_CLR_ALL (SPI_FLAG_OVERLOAD | SPI_FLAG_MD_FAULT | SPI_FLAG_PARITY_ERR | SPI_FLAG_UNDERLOAD) +#define SPI_FLAG_ALL (SPI_FLAG_OVERLOAD | SPI_FLAG_IDLE | SPI_FLAG_MD_FAULT | SPI_FLAG_PARITY_ERR | \ + SPI_FLAG_UNDERLOAD | SPI_FLAG_TX_BUF_EMPTY | SPI_FLAG_RX_BUF_FULL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup SPI_Global_Functions + * @{ + */ +int32_t SPI_StructInit(stc_spi_init_t *pstcSpiInit); +int32_t SPI_Init(CM_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInit); +int32_t SPI_DeInit(CM_SPI_TypeDef *SPIx); + +void SPI_IntCmd(CM_SPI_TypeDef *SPIx, uint32_t u32IntType, en_functional_state_t enNewState); +void SPI_Cmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState); +void SPI_WriteData(CM_SPI_TypeDef *SPIx, uint32_t u32Data); +uint32_t SPI_ReadData(const CM_SPI_TypeDef *SPIx); + +en_flag_status_t SPI_GetStatus(const CM_SPI_TypeDef *SPIx, uint32_t u32Flag); +void SPI_ClearStatus(CM_SPI_TypeDef *SPIx, uint32_t u32Flag); +void SPI_LoopbackModeConfig(CM_SPI_TypeDef *SPIx, uint32_t u32Mode); +void SPI_ParityCheckCmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState); +void SPI_SSValidLevelConfig(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin, en_functional_state_t enNewState); +void SPI_SetSckPolarity(CM_SPI_TypeDef *SPIx, uint32_t u32Polarity); +void SPI_SetSckPhase(CM_SPI_TypeDef *SPIx, uint32_t u32Phase); + +int32_t SPI_DelayTimeConfig(CM_SPI_TypeDef *SPIx, const stc_spi_delay_t *pstcDelayConfig); +void SPI_SSPinSelect(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin); +void SPI_ReadBufConfig(CM_SPI_TypeDef *SPIx, uint32_t u32ReadBuf); +int32_t SPI_DelayStructInit(stc_spi_delay_t *pstcDelayConfig); + +int32_t SPI_Trans(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32TxLen, uint32_t u32Timeout); +int32_t SPI_Receive(CM_SPI_TypeDef *SPIx, void *pvRxBuf, uint32_t u32RxLen, uint32_t u32Timeout); +int32_t SPI_TransReceive(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout); + +/** + * @} + */ + +#endif /* LL_SPI_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_SPI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_sram.h b/mcu/lib/inc/hc32_ll_sram.h new file mode 100644 index 0000000..16ba38b --- /dev/null +++ b/mcu/lib/inc/hc32_ll_sram.h @@ -0,0 +1,231 @@ +/** + ******************************************************************************* + * @file hc32_ll_sram.h + * @brief This file contains all the functions prototypes of the SRAM driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-10-31 CDT Deleted redundant comments + 2023-06-30 CDT Modify typo + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_SRAM_H__ +#define __HC32_LL_SRAM_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_SRAM + * @{ + */ + +#if (LL_SRAM_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SRAM_Global_Macros SRAM Global Macros + * @{ + */ + +/** + * @defgroup SRAM_Sel SRAM Selection + * @{ + */ +#define SRAM_SRAMH (1UL << 2U) /*!< SRAMH: 0x1FFF8000~0x1FFFFFFF, 32KB */ +#define SRAM_SRAM12 (1UL << 0U) /*!< SRAM1: 0x20000000~0x2000FFFF, 64KB + SRAM2: 0x20010000~0x2001FFFF, 64KB */ +#define SRAM_SRAM3 (1UL << 1U) /*!< SRAM3: 0x20020000~0x20026FFF, 28KB */ +#define SRAM_SRAMR (1UL << 3U) /*!< Ret_SRAM: 0x200F0000~0x200F0FFF, 4KB */ +#define SRAM_SRAM_ALL (SRAM_SRAMH | SRAM_SRAM12 | SRAM_SRAM3 | SRAM_SRAMR) +#define SRAM_ECC_SRAM3 (SRAM_SRAM3) + +/** + * @} + */ + +/** + * @defgroup SRAM_Access_Wait_Cycle SRAM Access Wait Cycle + * @{ + */ +#define SRAM_WAIT_CYCLE0 (0U) /*!< Wait 0 CPU cycle. */ +#define SRAM_WAIT_CYCLE1 (1U) /*!< Wait 1 CPU cycle. */ +#define SRAM_WAIT_CYCLE2 (2U) /*!< Wait 2 CPU cycles. */ +#define SRAM_WAIT_CYCLE3 (3U) /*!< Wait 3 CPU cycles. */ +#define SRAM_WAIT_CYCLE4 (4U) /*!< Wait 4 CPU cycles. */ +#define SRAM_WAIT_CYCLE5 (5U) /*!< Wait 5 CPU cycles. */ +#define SRAM_WAIT_CYCLE6 (6U) /*!< Wait 6 CPU cycles. */ +#define SRAM_WAIT_CYCLE7 (7U) /*!< Wait 7 CPU cycles. */ +/** + * @} + */ + +/** + * @defgroup SRAM_Err_Mode SRAM Error Mode + * @note Even-parity check error, ECC check error. + * @{ + */ +#define SRAM_ERR_MD_NMI (0UL) /*!< Non-maskable interrupt occurrence while check error occurs. */ +#define SRAM_ERR_MD_RST (1UL) /*!< System reset occurrence while check error occurs. */ +/** + * @} + */ + +/** + * @defgroup SRAM_ECC_Mode SRAM ECC Mode + * @{ + */ +#define SRAM_ECC_MD_INVD (0U) /*!< The ECC mode is invalid. */ +#define SRAM_ECC_MD1 (SRAMC_CKCR_ECCMOD_0) /*!< When 1-bit error occurs: + ECC error corrects. + No 1-bit-error status flag setting, no interrupt or reset. + When 2-bit error occurs: + ECC error detects. + 2-bit-error status flag sets and interrupt or reset occurs. */ +#define SRAM_ECC_MD2 (SRAMC_CKCR_ECCMOD_1) /*!< When 1-bit error occurs: + ECC error corrects. + 1-bit-error status flag sets, no interrupt or reset. + When 2-bit error occurs: + ECC error detects. + 2-bit-error status flag sets and interrupt or reset occurs. */ +#define SRAM_ECC_MD3 (SRAMC_CKCR_ECCMOD) /*!< When 1-bit error occurs: + ECC error corrects. + 1-bit-error status flag sets and interrupt or reset occurs. + When 2-bit error occurs: + ECC error detects. + 2-bit-error status flag sets and interrupt or reset occurs. */ +/** + * @} + */ + +/** + * @defgroup SRAM_Err_Status_Flag SRAM Error Status Flag + * @{ + */ +#define SRAM_FLAG_SRAM3_1ERR (SRAMC_CKSR_SRAM3_1ERR) /*!< SRAM3 ECC 1-bit error. */ +#define SRAM_FLAG_SRAM3_2ERR (SRAMC_CKSR_SRAM3_2ERR) /*!< SRAM3 ECC 2-bit error. */ +#define SRAM_FLAG_SRAM12_PYERR (SRAMC_CKSR_SRAM12_PYERR) /*!< SRAM12 parity error. */ +#define SRAM_FLAG_SRAMH_PYERR (SRAMC_CKSR_SRAMH_PYERR) /*!< SRAMH parity error. */ +#define SRAM_FLAG_SRAMR_PYERR (SRAMC_CKSR_SRAMR_PYERR) /*!< SRAMR parity error. */ +#define SRAM_FLAG_ALL (0x1FUL) + +/** + * @} + */ + +/** + * @defgroup SRAM_Reg_Protect_Key SRAM Register Protect Key + * @{ + */ +#define SRAM_REG_LOCK_KEY (0x76U) +#define SRAM_REG_UNLOCK_KEY (0x77U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup SRAM_Global_Functions + * @{ + */ + +/** + * @brief Lock SRAM registers, write protect. + * @param None + * @retval None + */ +__STATIC_INLINE void SRAM_REG_Lock(void) +{ + WRITE_REG32(CM_SRAMC->WTPR, SRAM_REG_LOCK_KEY); + WRITE_REG32(CM_SRAMC->CKPR, SRAM_REG_LOCK_KEY); +} + +/** + * @brief Unlock SRAM registers, write enable. + * @param None + * @retval None + */ +__STATIC_INLINE void SRAM_REG_Unlock(void) +{ + WRITE_REG32(CM_SRAMC->WTPR, SRAM_REG_UNLOCK_KEY); + WRITE_REG32(CM_SRAMC->CKPR, SRAM_REG_UNLOCK_KEY); +} + +void SRAM_Init(void); +void SRAM_DeInit(void); + +void SRAM_REG_Lock(void); +void SRAM_REG_Unlock(void); + +void SRAM_SetWaitCycle(uint32_t u32SramSel, uint32_t u32WriteCycle, uint32_t u32ReadCycle); +void SRAM_SetEccMode(uint32_t u32SramSel, uint32_t u32EccMode); +void SRAM_SetErrorMode(uint32_t u32SramSel, uint32_t u32ErrMode); + +en_flag_status_t SRAM_GetStatus(uint32_t u32Flag); +void SRAM_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_SRAM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_SRAM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_swdt.h b/mcu/lib/inc/hc32_ll_swdt.h new file mode 100644 index 0000000..9ce09b4 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_swdt.h @@ -0,0 +1,129 @@ +/** + ******************************************************************************* + * @file hc32_ll_swdt.h + * @brief This file contains all the functions prototypes of the SWDT driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_SWDT_H__ +#define __HC32_LL_SWDT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_SWDT + * @{ + */ + +#if (LL_SWDT_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SWDT_Global_Macros SWDT Global Macros + * @{ + */ + +/** + * @defgroup SWDT_Flag SWDT Flag + * @{ + */ +#define SWDT_FLAG_UDF (SWDT_SR_UDF) /*!< Count underflow flag */ +#define SWDT_FLAG_REFRESH (SWDT_SR_REF) /*!< Refresh error flag */ +#define SWDT_FLAG_ALL (SWDT_SR_UDF | SWDT_SR_REF) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup SWDT_Global_Functions + * @{ + */ + +/** + * @brief Get SWDT count value. + * @param None + * @retval uint16_t Count value + */ +__STATIC_INLINE uint16_t SWDT_GetCountValue(void) +{ + return (uint16_t)(READ_REG32(CM_SWDT->SR) & SWDT_SR_CNT); +} + +/* Initialization and configuration functions */ +void SWDT_FeedDog(void); +uint16_t SWDT_GetCountValue(void); + +/* Flags management functions */ +en_flag_status_t SWDT_GetStatus(uint32_t u32Flag); +int32_t SWDT_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_SWDT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_SWDT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_tmr0.h b/mcu/lib/inc/hc32_ll_tmr0.h new file mode 100644 index 0000000..6138d3f --- /dev/null +++ b/mcu/lib/inc/hc32_ll_tmr0.h @@ -0,0 +1,225 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr0.h + * @brief This file contains all the functions prototypes of the TMR0 driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-06-30 CDT Modify typo + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TMR0_H__ +#define __HC32_LL_TMR0_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TMR0 + * @{ + */ + +#if (LL_TMR0_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TMR0_Global_Types TMR0 Global Types + * @{ + */ + +/** + * @brief TMR0 initialization structure definition + * @note The 'u32ClockDiv' is invalid when the value of 'u32ClockSrc' is "TMR0_CLK_SRC_SPEC_EVT". + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Specifies the clock source of TMR0 channel. + This parameter can be a value of @ref TMR0_Clock_Source */ + uint32_t u32ClockDiv; /*!< Specifies the clock division of TMR0 channel. + This parameter can be a value of @ref TMR0_Clock_Division */ + uint32_t u32Func; /*!< Specifies the function of TMR0 channel. + This parameter can be a value of @ref TMR0_Function */ + uint16_t u16CompareValue; /*!< Specifies the compare value of TMR0 channel. + This parameter can be a value of half-word */ +} stc_tmr0_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR0_Global_Macros TMR0 Global Macros + * @{ + */ + +/** + * @defgroup TMR0_Channel TMR0 Channel + * @{ + */ +#define TMR0_CH_A (0UL) +#define TMR0_CH_B (1UL) +/** + * @} + */ + +/** + * @defgroup TMR0_Clock_Source TMR0 Clock Source + * @note In asynchronous clock, continuous operation of the BCONR register requires waiting for 3 asynchronous clocks. + * @{ + */ +#define TMR0_CLK_SRC_INTERN_CLK (0UL) /*!< Internal clock (Synchronous clock) */ +#define TMR0_CLK_SRC_SPEC_EVT (TMR0_BCONR_SYNCLKA) /*!< Specified event (Synchronous clock) */ +#define TMR0_CLK_SRC_LRC (TMR0_BCONR_SYNSA) /*!< LRC (Asynchronous clock) */ +#define TMR0_CLK_SRC_XTAL32 (TMR0_BCONR_ASYNCLKA | TMR0_BCONR_SYNSA) /*!< XTAL32 (Asynchronous clock) */ +/** + * @} + */ + +/** + * @defgroup TMR0_Clock_Division TMR0 Clock Division + * @{ + */ +#define TMR0_CLK_DIV1 (0UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK */ +#define TMR0_CLK_DIV2 (1UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/2 */ +#define TMR0_CLK_DIV4 (2UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/4 */ +#define TMR0_CLK_DIV8 (3UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/8 */ +#define TMR0_CLK_DIV16 (4UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/16 */ +#define TMR0_CLK_DIV32 (5UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/32 */ +#define TMR0_CLK_DIV64 (6UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/64 */ +#define TMR0_CLK_DIV128 (7UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/128 */ +#define TMR0_CLK_DIV256 (8UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/256 */ +#define TMR0_CLK_DIV512 (9UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/512 */ +#define TMR0_CLK_DIV1024 (10UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/1024 */ +/** + * @} + */ + +/** + * @defgroup TMR0_Function TMR0 Function + * @{ + */ +#define TMR0_FUNC_CMP (0UL) /*!< Output compare function */ +#define TMR0_FUNC_CAPT (TMR0_BCONR_CAPMDA | TMR0_BCONR_HICPA) /*!< Input capture function */ +/** + * @} + */ + +/** + * @defgroup TMR0_Interrupt TMR0 Interrupt + * @{ + */ +#define TMR0_INT_CMP_A (TMR0_BCONR_INTENA) +#define TMR0_INT_CMP_B (TMR0_BCONR_INTENB) +#define TMR0_INT_ALL (TMR0_INT_CMP_A | TMR0_INT_CMP_B) +/** + * @} + */ + +/** + * @defgroup TMR0_FLAG TMR0 Flag + * @{ + */ +#define TMR0_FLAG_CMP_A (TMR0_STFLR_CMFA) +#define TMR0_FLAG_CMP_B (TMR0_STFLR_CMFB) +#define TMR0_FLAG_ALL (TMR0_FLAG_CMP_A | TMR0_FLAG_CMP_B) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TMR0_Global_Functions + * @{ + */ + +/* Initialization functions */ +void TMR0_DeInit(CM_TMR0_TypeDef *TMR0x); +int32_t TMR0_Init(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, const stc_tmr0_init_t *pstcTmr0Init); +int32_t TMR0_StructInit(stc_tmr0_init_t *pstcTmr0Init); +void TMR0_Start(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch); +void TMR0_Stop(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch); + +/* Control configuration functions */ +void TMR0_SetCountValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value); +uint16_t TMR0_GetCountValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch); +void TMR0_SetCompareValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value); +uint16_t TMR0_GetCompareValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch); +void TMR0_SetClockSrc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Src); +void TMR0_SetClockDiv(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Div); +void TMR0_SetFunc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Func); + +/* Hardware trigger Functions */ +void TMR0_HWCaptureCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR0_HWStartCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR0_HWStopCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR0_HWClearCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState); + +/* Interrupt and flag management functions */ +void TMR0_IntCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t TMR0_GetStatus(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag); +void TMR0_ClearStatus(CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_TMR0_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TMR0_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_tmr4.h b/mcu/lib/inc/hc32_ll_tmr4.h new file mode 100644 index 0000000..cf8a5f3 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_tmr4.h @@ -0,0 +1,787 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr4.h + * @brief This file contains all the functions prototypes of the TMR4 + * driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-10-31 CDT Update API parameter u16IntType to u32IntType + 2023-06-30 CDT Add the macros group @ref TMR4_OC_Output_Polarity + Modify typo + TMR4_OC_Buffer_Object group add macro-definition: TMR4_OC_BUF_NONE + 2023-09-30 CDT Modify API TMR4_DeInit + Fix spell error about "response" that in function name + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TMR4_H__ +#define __HC32_LL_TMR4_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TMR4 + * @{ + */ + +#if (LL_TMR4_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TMR4_Global_Types TMR4 Global Types + * @{ + */ + +/** + * @brief TMR4 Counter function initialization configuration + * @note The TMR4 division(u16ClockDiv) is valid when clock source is the internal clock. + */ +typedef struct { + uint16_t u16ClockSrc; /*!< TMR4 counter clock source. + This parameter can be a value of @ref TMR4_Count_Clock_Source */ + uint16_t u16ClockDiv; /*!< TMR4 counter internal clock division. + This parameter can be a value of @ref TMR4_Count_Clock_Division. */ + uint16_t u16CountMode; /*!< TMR4 counter mode. + This parameter can be a value of @ref TMR4_Count_Mode */ + uint16_t u16PeriodValue; /*!< TMR4 counter period value. + This parameter can be a value of half-word */ +} stc_tmr4_init_t; + +/** + * @brief The configuration of Output-Compare high channel(OUH/OVH/OWH) + */ +typedef union { + uint16_t OCMRx; /*!< OCMRxH(x=U/V/W) register */ + + struct { /*!< OCMRxH(x=U/V/W) register struct field bit */ + uint16_t OCFDCH : 1; /*!< OCMRxh b0 High channel's OCF status when high channel match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint16_t OCFPKH : 1; /*!< OCMRxh b1 High channel's OCF status when high channel match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint16_t OCFUCH : 1; /*!< OCMRxh b2 High channel's OCF status when high channel match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint16_t OCFZRH : 1; /*!< OCMRxh b3 High channel's OCF status when high channel match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint16_t OPDCH : 2; /*!< OCMRxh b5~b4 High channel's OP output status when high channel match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint16_t OPPKH : 2; /*!< OCMRxh b7~b6 High channel's OP output status when high channel match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint16_t OPUCH : 2; /*!< OCMRxh b9~b8 High channel's OP output status when high channel match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint16_t OPZRH : 2; /*!< OCMRxh b11~b10 High channel's OP output status when high channel match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint16_t OPNPKH : 2; /*!< OCMRxh b13~b12 High channel's OP output status when high channel match doesn't occur at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint16_t OPNZRH : 2; /*!< OCMRxh b15~b14 High channel's OP output status when high channel match doesn't occur at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + } OCMRx_f; +} un_tmr4_oc_ocmrh_t; + +/** + * @brief The configuration of Output-Compare low channel(OUL/OVL/OWL) + */ +typedef union { + uint32_t OCMRx; /*!< OCMRxL(x=U/V/W) register */ + + struct { /*!< OCMRxL(x=U/V/W) register struct field bit*/ + uint32_t OCFDCL : 1; /*!< OCMRxl b0 Low channel's OCF status when low channel match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint32_t OCFPKL : 1; /*!< OCMRxl b1 Low channel's OCF status when low channel match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint32_t OCFUCL : 1; /*!< OCMRxl b2 Low channel's OCF status when low channel match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint32_t OCFZRL : 1; /*!< OCMRxl b3 Low channel's OCF status when low channel match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint32_t OPDCL : 2; /*!< OCMRxl b5~b4 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t OPPKL : 2; /*!< OCMRxl b7~b6 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t OPUCL : 2; /*!< OCMRxl b9~b8 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t OPZRL : 2; /*!< OCMRxl b11~b10 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t OPNPKL : 2; /*!< OCMRxl b13~b12 Low channel's OP output status when high channel not match and low channel not match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t OPNZRL : 2; /*!< OCMRxl b15~b14 Low channel's OP output status when high channel not match and low channel not match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPNDCL : 2; /*!< OCMRxl b17~b16 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPNUCL : 2; /*!< OCMRxl b19~b18 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPDCL : 2; /*!< OCMRxl b21~b20 Low channel's OP output status when high channel and low channel match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPPKL : 2; /*!< OCMRxl b23~b22 Low channel's OP output status when high channel and low channel match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPUCL : 2; /*!< OCMRxl b25~b24 Low channel's OP output status when high channel and low channel match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPZRL : 2; /*!< OCMRxl b27~b26 Low channel's OP output status when high channel and low channel match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPNPKL : 2; /*!< OCMRxl b29~b28 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPNZRL : 2; /*!< OCMRxl b31~b30 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + } OCMRx_f; +} un_tmr4_oc_ocmrl_t; + +/** + * @brief TMR4 Output-Compare(OC) initialization configuration + */ +typedef struct { + uint16_t u16CompareValue; /*!< TMR4 OC compare match value. + This parameter can be a value of half-word. */ + uint16_t u16OcInvalidPolarity; /*!< Port output polarity when OC is disabled. + This parameter can be a value of @ref TMR4_OC_Invalid_Output_Polarity. */ + uint16_t u16CompareModeBufCond; /*!< Register OCMR buffer transfer condition. + This parameter can be a value of @ref TMR4_OC_Buffer_Transfer_Condition. */ + uint16_t u16CompareValueBufCond; /*!< Register OCCR buffer transfer condition. + This parameter can be a value of @ref TMR4_OC_Buffer_Transfer_Condition. */ + uint16_t u16BufLinkTransObject; /*!< Enable the specified object(OCMR/OCCR) register buffer linked transfer with the counter interrupt mask. + This parameter can be a value of @ref TMR4_OC_Buffer_Object. */ +} stc_tmr4_oc_init_t; + +/** + * @brief TMR4 PWM initialization configuration + * @note The clock division(u16ClockDiv) is valid when TMR4 clock source is the internal clock. + */ +typedef struct { + uint16_t u16Mode; /*!< Select PWM mode + This parameter can be a value of @ref TMR4_PWM_Mode */ + uint16_t u16ClockDiv; /*!< The internal clock division of PWM timer. + This parameter can be a value of @ref TMR4_PWM_Clock_Division. */ + uint16_t u16Polarity; /*!< TMR4 PWM polarity + This parameter can be a value of @ref TMR4_PWM_Polarity */ +} stc_tmr4_pwm_init_t; + +/** + * @brief TMR4 Special-Event(EVT) initialization configuration + */ +typedef struct { + uint16_t u16Mode; /*!< TMR4 event mode + This parameter can be a value of @ref TMR4_Event_Mode */ + uint16_t u16CompareValue; /*!< TMR4 event compare match value. + This parameter can be a value of half-word */ + uint16_t u16OutputEvent; /*!< TMR4 event output event when match count compare condition. + This parameter can be a value of @ref TMR4_Event_Output_Event */ + uint16_t u16MatchCond; /*!< Enable the specified count compare type with counter count to generate event. + This parameter can be a value of @ref TMR4_Event_Match_Condition */ +} stc_tmr4_evt_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR4_Global_Macros TMR4 Global Macros + * @{ + */ + +/** + * @defgroup TMR4_Counter_Macros TMR4 Counter Macros + * @{ + */ + +/** + * @defgroup TMR4_Count_Clock_Source TMR4 Count Clock Source + * @{ + */ +#define TMR4_CLK_SRC_INTERNCLK (0U) +#define TMR4_CLK_SRC_EXTCLK (TMR4_CCSR_ECKEN) +/** + * @} + */ + +/** + * @defgroup TMR4_Count_Clock_Division TMR4 Count Clock Division + * @{ + */ +#define TMR4_CLK_DIV1 (0U << TMR4_CCSR_CKDIV_POS) /*!< CLK */ +#define TMR4_CLK_DIV2 (1U << TMR4_CCSR_CKDIV_POS) /*!< CLK/2 */ +#define TMR4_CLK_DIV4 (2U << TMR4_CCSR_CKDIV_POS) /*!< CLK/4 */ +#define TMR4_CLK_DIV8 (3U << TMR4_CCSR_CKDIV_POS) /*!< CLK/8 */ +#define TMR4_CLK_DIV16 (4U << TMR4_CCSR_CKDIV_POS) /*!< CLK/16 */ +#define TMR4_CLK_DIV32 (5U << TMR4_CCSR_CKDIV_POS) /*!< CLK/32 */ +#define TMR4_CLK_DIV64 (6U << TMR4_CCSR_CKDIV_POS) /*!< CLK/64 */ +#define TMR4_CLK_DIV128 (7U << TMR4_CCSR_CKDIV_POS) /*!< CLK/128 */ +#define TMR4_CLK_DIV256 (8U << TMR4_CCSR_CKDIV_POS) /*!< CLK/256 */ +#define TMR4_CLK_DIV512 (9U << TMR4_CCSR_CKDIV_POS) /*!< CLK/512 */ +#define TMR4_CLK_DIV1024 (10U << TMR4_CCSR_CKDIV_POS) /*!< CLK/1024 */ +/** + * @} + */ + +/** + * @defgroup TMR4_Count_Mode TMR4 Count Mode + * @{ + */ +#define TMR4_MD_SAWTOOTH (0U) +#define TMR4_MD_TRIANGLE (TMR4_CCSR_MODE) +/** + * @} + */ + +/** + * @defgroup TMR4_Flag TMR4 Flag + * @{ + */ +#define TMR4_FLAG_CNT_PEAK ((uint32_t)TMR4_CCSR_IRQPF) /*!< Count peak flag */ +#define TMR4_FLAG_CNT_VALLEY ((uint32_t)TMR4_CCSR_IRQZF) /*!< Count valley flag */ +#define TMR4_FLAG_RELOAD_TMR_U (1UL << 0U) /*!< TMR4 PWM reload-timer flag - channel U */ +#define TMR4_FLAG_RELOAD_TMR_V (1UL << 4U) /*!< TMR4 PWM reload-timer flag - channel V */ +#define TMR4_FLAG_RELOAD_TMR_W (1UL << 8U) /*!< TMR4 PWM reload-timer flag - channel W */ +#define TMR4_FLAG_OC_CMP_UH (1UL << 16U) /*!< TMR4 output-compare compare flag - channel UH */ +#define TMR4_FLAG_OC_CMP_UL (1UL << 17U) /*!< TMR4 output-compare compare flag - channel UL */ +#define TMR4_FLAG_OC_CMP_VH (1UL << 18U) /*!< TMR4 output-compare compare flag - channel VH */ +#define TMR4_FLAG_OC_CMP_VL (1UL << 19U) /*!< TMR4 output-compare compare flag - channel VL */ +#define TMR4_FLAG_OC_CMP_WH (1UL << 20U) /*!< TMR4 output-compare compare flag - channel WH */ +#define TMR4_FLAG_OC_CMP_WL (1UL << 21U) /*!< TMR4 output-compare compare flag - channel WL */ + +#define TMR4_FLAG_ALL (TMR4_FLAG_CNT_PEAK | TMR4_FLAG_CNT_VALLEY | TMR4_FLAG_RELOAD_TMR_U | \ + TMR4_FLAG_RELOAD_TMR_V | TMR4_FLAG_RELOAD_TMR_W | TMR4_FLAG_OC_CMP_UH | \ + TMR4_FLAG_OC_CMP_UL | TMR4_FLAG_OC_CMP_VH | TMR4_FLAG_OC_CMP_VL | \ + TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL) +/** + * @} + */ + +/** + * @defgroup TMR4_Interrupt TMR4 Interrupt + * @{ + */ +#define TMR4_INT_CNT_PEAK ((uint32_t)TMR4_CCSR_IRQPEN) /*!< Count peak interrupt */ +#define TMR4_INT_CNT_VALLEY ((uint32_t)TMR4_CCSR_IRQZEN) /*!< Count valley interrupt */ +#define TMR4_INT_RELOAD_TMR_U (1UL << 0U) /*!< TMR4 PWM reload-timer interrupt - channel U */ +#define TMR4_INT_RELOAD_TMR_V (1UL << 1U) /*!< TMR4 PWM reload-timer interrupt - channel W */ +#define TMR4_INT_RELOAD_TMR_W (1UL << 2U) /*!< TMR4 PWM reload-timer interrupt - channel V */ +#define TMR4_INT_OC_CMP_UH (1UL << 16U) /*!< TMR4 output-compare compare interrupt - channel UH */ +#define TMR4_INT_OC_CMP_UL (1UL << 17U) /*!< TMR4 output-compare compare interrupt - channel UL */ +#define TMR4_INT_OC_CMP_VH (1UL << 18U) /*!< TMR4 output-compare compare interrupt - channel VH */ +#define TMR4_INT_OC_CMP_VL (1UL << 19U) /*!< TMR4 output-compare compare interrupt - channel VL */ +#define TMR4_INT_OC_CMP_WH (1UL << 20U) /*!< TMR4 output-compare compare interrupt - channel WH */ +#define TMR4_INT_OC_CMP_WL (1UL << 21U) /*!< TMR4 output-compare compare interrupt - channel WL */ + +#define TMR4_INT_ALL (TMR4_INT_CNT_PEAK | TMR4_INT_CNT_VALLEY | TMR4_INT_RELOAD_TMR_U | \ + TMR4_INT_RELOAD_TMR_V | TMR4_INT_RELOAD_TMR_W | TMR4_INT_OC_CMP_UH | \ + TMR4_INT_OC_CMP_UL | TMR4_INT_OC_CMP_VH | TMR4_INT_OC_CMP_VL | \ + TMR4_INT_OC_CMP_WH | TMR4_INT_OC_CMP_WL) +/** + * @} + */ + +/** + * @defgroup TMR4_Count_Interrupt_Mask_Time TMR4 Count Interrupt Mask Time + * @{ + */ +#define TMR4_INT_CNT_MASK0 (0U) /*!< Counter interrupt flag is always set(not masked) for counter count every time at "0x0000" or peak */ +#define TMR4_INT_CNT_MASK1 (1U) /*!< Counter interrupt flag is set once when counter counts 2 times at "0x0000" or peak (skipping 1 count) */ +#define TMR4_INT_CNT_MASK2 (2U) /*!< Counter interrupt flag is set once when counter counts 3 times at "0x0000" or peak (skipping 2 count) */ +#define TMR4_INT_CNT_MASK3 (3U) /*!< Counter interrupt flag is set once when counter counts 4 times at "0x0000" or peak (skipping 3 count) */ +#define TMR4_INT_CNT_MASK4 (4U) /*!< Counter interrupt flag is set once when counter counts 5 times at "0x0000" or peak (skipping 4 count) */ +#define TMR4_INT_CNT_MASK5 (5U) /*!< Counter interrupt flag is set once when counter counts 6 times at "0x0000" or peak (skipping 5 count) */ +#define TMR4_INT_CNT_MASK6 (6U) /*!< Counter interrupt flag is set once when counter counts 7 times at "0x0000" or peak (skipping 6 count) */ +#define TMR4_INT_CNT_MASK7 (7U) /*!< Counter interrupt flag is set once when counter counts 8 times at "0x0000" or peak (skipping 7 count) */ +#define TMR4_INT_CNT_MASK8 (8U) /*!< Counter interrupt flag is set once when counter counts 9 times at "0x0000" or peak (skipping 8 count) */ +#define TMR4_INT_CNT_MASK9 (9U) /*!< Counter interrupt flag is set once when counter counts 10 times at "0x0000" or peak (skipping 9 count) */ +#define TMR4_INT_CNT_MASK10 (10U) /*!< Counter interrupt flag is set once when counter counts 11 times at "0x0000" or peak (skipping 10 count) */ +#define TMR4_INT_CNT_MASK11 (11U) /*!< Counter interrupt flag is set once when counter counts 12 times at "0x0000" or peak (skipping 11 count) */ +#define TMR4_INT_CNT_MASK12 (12U) /*!< Counter interrupt flag is set once when counter counts 13 times at "0x0000" or peak (skipping 12 count) */ +#define TMR4_INT_CNT_MASK13 (13U) /*!< Counter interrupt flag is set once when counter counts 14 times at "0x0000" or peak (skipping 13 count) */ +#define TMR4_INT_CNT_MASK14 (14U) /*!< Counter interrupt flag is set once when counter counts 15 times at "0x0000" or peak (skipping 14 count) */ +#define TMR4_INT_CNT_MASK15 (15U) /*!< Counter interrupt flag is set once when counter counts 16 times at "0x0000" or peak (skipping 15 count) */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup TMR4_Output_Compare_Macros TMR4 Output-Compare Macros + * @{ + */ + +/** + * @defgroup TMR4_OC_Channel TMR4 OC Channel + * @{ + */ +#define TMR4_OC_CH_UH (0UL) /*!< TMR4 OC channel:UH */ +#define TMR4_OC_CH_UL (1UL) /*!< TMR4 OC channel:UL */ +#define TMR4_OC_CH_VH (2UL) /*!< TMR4 OC channel:VH */ +#define TMR4_OC_CH_VL (3UL) /*!< TMR4 OC channel:VL */ +#define TMR4_OC_CH_WH (4UL) /*!< TMR4 OC channel:WH */ +#define TMR4_OC_CH_WL (5UL) /*!< TMR4 OC channel:WL */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Invalid_Output_Polarity TMR4 OC Invalid Output Polarity + * @{ + */ +#define TMR4_OC_INVD_LOW (0U) /*!< TMR4 OC Output low level when OC is invalid */ +#define TMR4_OC_INVD_HIGH (TMR4_OCSR_OCPH) /*!< TMR4 OC Output high level when OC is invalid */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Output_Polarity TMR4 OC Output Polarity + * @{ + */ +#define TMR4_OC_PORT_LOW (0U) /*!< TMR4 OC Output low level */ +#define TMR4_OC_PORT_HIGH (TMR4_OCSR_OCPH) /*!< TMR4 OC Output high level */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Buffer_Object TMR4 OC Buffer Object + * @{ + */ +#define TMR4_OC_BUF_NONE (0x00U) /*!< Disable the buffer function of OCCR/OCMR */ +#define TMR4_OC_BUF_CMP_VALUE (0x01U) /*!< The register OCCR buffer function */ +#define TMR4_OC_BUF_CMP_MD (0x02U) /*!< The register OCMR buffer function */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Buffer_Transfer_Condition TMR4 OC OCCR Buffer Transfer Condition + * @{ + */ +#define TMR4_OC_BUF_COND_IMMED (0U) /*!< Buffer transfer is made when writing to the OCCR/OCMR register. */ +#define TMR4_OC_BUF_COND_VALLEY (1U) /*!< Buffer transfer is made when counter count valley */ +#define TMR4_OC_BUF_COND_PEAK (2U) /*!< Buffer transfer is made when counter count peak */ +#define TMR4_OC_BUF_COND_PEAK_VALLEY (3U) /*!< Buffer transfer is made when counter count peak or valley */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Count_Match_OCF_State TMR4 OC Count Match OCF State + * @{ + */ +#define TMR4_OC_OCF_HOLD (0U) /*!< Hold OCF when the TMR4 OC count match */ +#define TMR4_OC_OCF_SET (TMR4_OCMRH_OCFDCH) /*!< Set OCF when the TMR4 OC count match */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Count_Match_Output_Polarity TMR4 OC Count Match Output Polarity + * @{ + */ +#define TMR4_OC_HOLD (0U) /*!< Hold output when the TMR4 OC count match */ +#define TMR4_OC_HIGH (1U) /*!< Output high when the TMR4 OC count match */ +#define TMR4_OC_LOW (2U) /*!< Output low when the TMR4 OC count match */ +#define TMR4_OC_INVT (3U) /*!< Invert output when the TMR4 OC count match */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Macros TMR4 PWM Macros + * @{ + */ + +/** + * @defgroup TMR4_PWM_Channel TMR4 PWM Channel + * @{ + */ +#define TMR4_PWM_CH_U (0UL) /*!< TMR4 PWM couple channel: U */ +#define TMR4_PWM_CH_V (1UL) /*!< TMR4 PWM couple channel: V */ +#define TMR4_PWM_CH_W (2UL) /*!< TMR4 PWM couple channel: W */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Pin TMR4 PWM Pin + * @{ + */ +#define TMR4_PWM_PIN_OUH (0UL) /*!< TMR4 PWM port: TIM4__OUH */ +#define TMR4_PWM_PIN_OUL (1UL) /*!< TMR4 PWM port: TIM4__OUL */ +#define TMR4_PWM_PIN_OVH (2UL) /*!< TMR4 PWM port: TIM4__OVH */ +#define TMR4_PWM_PIN_OVL (3UL) /*!< TMR4 PWM port: TIM4__OVL */ +#define TMR4_PWM_PIN_OWH (4UL) /*!< TMR4 PWM port: TIM4__OWH */ +#define TMR4_PWM_PIN_OWL (5UL) /*!< TMR4 PWM port: TIM4__OWL */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Clock_Division TMR4 PWM Clock Division + * @{ + */ +#define TMR4_PWM_CLK_DIV1 (0U) /*!< CLK */ +#define TMR4_PWM_CLK_DIV2 (1U << TMR4_POCR_DIVCK_POS) /*!< CLK/2 */ +#define TMR4_PWM_CLK_DIV4 (2U << TMR4_POCR_DIVCK_POS) /*!< CLK/8 */ +#define TMR4_PWM_CLK_DIV8 (3U << TMR4_POCR_DIVCK_POS) /*!< CLK/8 */ +#define TMR4_PWM_CLK_DIV16 (4U << TMR4_POCR_DIVCK_POS) /*!< CLK/16 */ +#define TMR4_PWM_CLK_DIV32 (5U << TMR4_POCR_DIVCK_POS) /*!< CLK/32 */ +#define TMR4_PWM_CLK_DIV64 (6U << TMR4_POCR_DIVCK_POS) /*!< CLK/64 */ +#define TMR4_PWM_CLK_DIV128 (7U << TMR4_POCR_DIVCK_POS) /*!< CLK/128 */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Mode TMR4 PWM Mode + * @{ + */ +#define TMR4_PWM_MD_THROUGH (0U) /*!< Through mode */ +#define TMR4_PWM_MD_DEAD_TMR (TMR4_POCR_PWMMD_0) /*!< Dead timer mode */ +#define TMR4_PWM_MD_DEAD_TMR_FILTER (TMR4_POCR_PWMMD_1) /*!< Dead timer filter mode */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Polarity TMR4 PWM Polarity + * @{ + */ +#define TMR4_PWM_OXH_HOLD_OXL_HOLD (0U) /*!< Output PWML and PWMH signals without changing the level */ +#define TMR4_PWM_OXH_INVT_OXL_INVT (TMR4_POCR_LVLS_0) /*!< Output both PWML and PWMH signals reversed */ +#define TMR4_PWM_OXH_INVT_OXL_HOLD (TMR4_POCR_LVLS_1) /*!< Output the PWMH signal reversed, outputs the PWML signal without changing the level. */ +#define TMR4_PWM_OXH_HOLD_OXL_INVT (TMR4_POCR_LVLS) /*!< Output the PWMH signal without changing the level, Outputs the PWML signal reversed. */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Dead_Time_Register_Index TMR4 PWM Dead Time Register Index + * @{ + */ +#define TMR4_PWM_PDAR_IDX (0UL) /*!< TMR4_PDARn(n=U/V/W) */ +#define TMR4_PWM_PDBR_IDX (1UL) /*!< TMR4_PDBRn(n=U/V/W) */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Abnormal_Pin_Status TMR4 PWM Abnormal Pin Status + * @{ + */ +#define TMR4_PWM_ABNORMAL_PIN_NORMAL (0UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output normal */ +#define TMR4_PWM_ABNORMAL_PIN_HIZ (1UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) to Hi-z */ +#define TMR4_PWM_ABNORMAL_PIN_LOW (2UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output low level */ +#define TMR4_PWM_ABNORMAL_PIN_HIGH (3UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output high level */ +#define TMR4_PWM_ABNORMAL_PIN_HOLD (4UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output hold */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Macros TMR4 Event Macros + * @{ + */ + +/** + * @defgroup TMR4_Event_Channel TMR4 Event Channel + * @{ + */ +#define TMR4_EVT_CH_UH (0UL) /*!< TMR4 EVT channel:UH */ +#define TMR4_EVT_CH_UL (1UL) /*!< TMR4 EVT channel:UL */ +#define TMR4_EVT_CH_VH (2UL) /*!< TMR4 EVT channel:VH */ +#define TMR4_EVT_CH_VL (3UL) /*!< TMR4 EVT channel:VL */ +#define TMR4_EVT_CH_WH (4UL) /*!< TMR4 EVT channel:WH */ +#define TMR4_EVT_CH_WL (5UL) /*!< TMR4 EVT channel:WL */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Match_Condition TMR4 Event Match Condition + * @{ + */ +#define TMR4_EVT_MATCH_CNT_UP (TMR4_SCSR_UEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count up */ +#define TMR4_EVT_MATCH_CNT_DOWN (TMR4_SCSR_DEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count down */ +#define TMR4_EVT_MATCH_CNT_PEAK (TMR4_SCSR_PEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count peak */ +#define TMR4_EVT_MATCH_CNT_VALLEY (TMR4_SCSR_ZEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count valley */ +#define TMR4_EVT_MATCH_CNT_ALL (TMR4_EVT_MATCH_CNT_DOWN | TMR4_EVT_MATCH_CNT_UP | \ + TMR4_EVT_MATCH_CNT_PEAK | TMR4_EVT_MATCH_CNT_VALLEY) +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Mask TMR4 Event Mask + * @{ + */ +#define TMR4_EVT_MASK_PEAK (TMR4_SCMR_MPCE) /*!< Match with the count peak interrupt mask of the counter */ +#define TMR4_EVT_MASK_VALLEY (TMR4_SCMR_MZCE) /*!< Match with the count valley interrupt mask of the counter */ +#define TMR4_EVT_MASK_TYPE_ALL (TMR4_EVT_MASK_PEAK | TMR4_EVT_MASK_VALLEY) +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Buffer_Transfer_Condition TMR4 Event Buffer Transfer Condition + * @{ + */ +#define TMR4_EVT_BUF_COND_IMMED (0U) /*!< Register SCCR&SCMR buffer transfer when writing to the SCCR&SCMR register */ +#define TMR4_EVT_BUF_COND_VALLEY (TMR4_SCSR_BUFEN_0) /*!< Register SCCR&SCMR buffer transfer when counter count valley */ +#define TMR4_EVT_BUF_COND_PEAK (TMR4_SCSR_BUFEN_1) /*!< Register SCCR&SCMR buffer transfer when counter count peak */ +#define TMR4_EVT_BUF_COND_PEAK_VALLEY (TMR4_SCSR_BUFEN) /*!< Register SCCR&SCMR buffer transfer when counter count peak or valley */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Mode TMR4 Event Mode + * @{ + */ +#define TMR4_EVT_MD_CMP (0U) /*!< TMR4 EVT compare mode */ +#define TMR4_EVT_MD_DELAY (TMR4_SCSR_EVTMS) /*!< TMR4 EVT delay mode */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Delay_Object TMR4 Event Delay Object + * @{ + */ +#define TMR4_EVT_DELAY_OCCRXH (0U) /*!< TMR4 EVT delay object: OCCRxh(x=u/v/w) */ +#define TMR4_EVT_DELAY_OCCRXL (TMR4_SCSR_EVTDS) /*!< TMR4 EVT delay object: OCCRxl(x=u/v/w) */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Mask_Times TMR4 Event Mask Times + * @{ + */ +#define TMR4_EVT_MASK0 (0U << TMR4_SCMR_AMC_POS) /*!< Mask 0 time */ +#define TMR4_EVT_MASK1 (1U << TMR4_SCMR_AMC_POS) /*!< Mask 1 times */ +#define TMR4_EVT_MASK2 (2U << TMR4_SCMR_AMC_POS) /*!< Mask 2 times */ +#define TMR4_EVT_MASK3 (3U << TMR4_SCMR_AMC_POS) /*!< Mask 3 times */ +#define TMR4_EVT_MASK4 (4U << TMR4_SCMR_AMC_POS) /*!< Mask 4 times */ +#define TMR4_EVT_MASK5 (5U << TMR4_SCMR_AMC_POS) /*!< Mask 5 times */ +#define TMR4_EVT_MASK6 (6U << TMR4_SCMR_AMC_POS) /*!< Mask 6 times */ +#define TMR4_EVT_MASK7 (7U << TMR4_SCMR_AMC_POS) /*!< Mask 7 times */ +#define TMR4_EVT_MASK8 (8U << TMR4_SCMR_AMC_POS) /*!< Mask 8 times */ +#define TMR4_EVT_MASK9 (9U << TMR4_SCMR_AMC_POS) /*!< Mask 9 times */ +#define TMR4_EVT_MASK10 (10U << TMR4_SCMR_AMC_POS) /*!< Mask 10 times */ +#define TMR4_EVT_MASK11 (11U << TMR4_SCMR_AMC_POS) /*!< Mask 11 times */ +#define TMR4_EVT_MASK12 (12U << TMR4_SCMR_AMC_POS) /*!< Mask 12 times */ +#define TMR4_EVT_MASK13 (13U << TMR4_SCMR_AMC_POS) /*!< Mask 13 times */ +#define TMR4_EVT_MASK14 (14U << TMR4_SCMR_AMC_POS) /*!< Mask 14 times */ +#define TMR4_EVT_MASK15 (15U << TMR4_SCMR_AMC_POS) /*!< Mask 15 times */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Output_Event TMR4 Event Output Event + * @{ + */ +#define TMR4_EVT_OUTPUT_EVT0 (0U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 0 */ +#define TMR4_EVT_OUTPUT_EVT1 (1U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 1 */ +#define TMR4_EVT_OUTPUT_EVT2 (2U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 2 */ +#define TMR4_EVT_OUTPUT_EVT3 (3U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 3 */ +#define TMR4_EVT_OUTPUT_EVT4 (4U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 4 */ +#define TMR4_EVT_OUTPUT_EVT5 (5U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 5 */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Output_Signal TMR4 Event Output Signal + * @{ + */ +#define TMR4_EVT_OUTPUT_NONE (0U) /*!< Disable output event signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT0_SIGNAL (1U) /*!< Output the specified event 0 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT1_SIGNAL (2U) /*!< Output the specified event 1 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT2_SIGNAL (3U) /*!< Output the specified event 2 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT3_SIGNAL (4U) /*!< Output the specified event 3 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT4_SIGNAL (5U) /*!< Output the specified event 4 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT5_SIGNAL (6U) /*!< Output the specified event 5 signal of TMR4 Special-EVT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TMR4_Global_Functions + * @{ + */ + +/** + * @addtogroup TMR4_Counter_Global_Functions + * @{ + */ + +/* Initialization and configuration TMR4 counter functions */ +int32_t TMR4_StructInit(stc_tmr4_init_t *pstcTmr4Init); +int32_t TMR4_Init(CM_TMR4_TypeDef *TMR4x, const stc_tmr4_init_t *pstcTmr4Init); +int32_t TMR4_DeInit(CM_TMR4_TypeDef *TMR4x); +void TMR4_SetClockSrc(CM_TMR4_TypeDef *TMR4x, uint16_t u16Src); +void TMR4_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint16_t u16Div); +void TMR4_SetCountMode(CM_TMR4_TypeDef *TMR4x, uint16_t u16Mode); +uint16_t TMR4_GetPeriodValue(const CM_TMR4_TypeDef *TMR4x); +void TMR4_SetPeriodValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value); +uint16_t TMR4_GetCountValue(const CM_TMR4_TypeDef *TMR4x); +void TMR4_SetCountValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value); +void TMR4_ClearCountValue(CM_TMR4_TypeDef *TMR4x); +void TMR4_Start(CM_TMR4_TypeDef *TMR4x); +void TMR4_Stop(CM_TMR4_TypeDef *TMR4x); +void TMR4_ClearStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag); +en_flag_status_t TMR4_GetStatus(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag); +void TMR4_IntCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, en_functional_state_t enNewState); +void TMR4_PeriodBufCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState); +uint16_t TMR4_GetCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType); +void TMR4_SetCountIntMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, uint16_t u16MaskTime); +uint16_t TMR4_GetCurrentCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType); +/** + * @} + */ + +/** + * @addtogroup TMR4_Output_Compare_Global_Functions + * @{ + */ + +/* Initialization and configuration TMR4 Output-Compare functions */ +int32_t TMR4_OC_StructInit(stc_tmr4_oc_init_t *pstcTmr4OcInit); +int32_t TMR4_OC_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_oc_init_t *pstcTmr4OcInit); +void TMR4_OC_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +uint16_t TMR4_OC_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_OC_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value); +void TMR4_OC_Cmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR4_OC_ExtendControlCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR4_OC_BufIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, + uint16_t u16Object, en_functional_state_t enNewState); +uint16_t TMR4_OC_GetPolarity(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_OC_SetOcInvalidPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity); +void TMR4_OC_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object, uint16_t u16BufCond); +uint16_t TMR4_OC_GetHighChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_OC_SetHighChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrh_t unTmr4Ocmrh); +uint32_t TMR4_OC_GetLowChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_OC_SetLowChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrl_t unTmr4Ocmrl); +/** + * @} + */ + +/** + * @addtogroup TMR4_PWM_Global_Functions + * @{ + */ + +/* Initialization and configuration TMR4 PWM functions */ +int32_t TMR4_PWM_StructInit(stc_tmr4_pwm_init_t *pstcTmr4PwmInit); +int32_t TMR4_PWM_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_pwm_init_t *pstcTmr4PwmInit); +void TMR4_PWM_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_PWM_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Div); +void TMR4_PWM_SetPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity); +void TMR4_PWM_StartReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_PWM_StopReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_PWM_SetFilterCountValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value); +void TMR4_PWM_SetDeadTimeValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex, uint16_t u16Value); +uint16_t TMR4_PWM_GetDeadTimeValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex); +void TMR4_PWM_SetAbnormalPinStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32PwmPin, uint32_t u32PinStatus); + +/** + * @} + */ + +/** + * @addtogroup TMR4_Event_Global_Functions + * @{ + */ + +/* Initialization and configuration TMR4 event functions */ +int32_t TMR4_EVT_StructInit(stc_tmr4_evt_init_t *pstcTmr4EventInit); +int32_t TMR4_EVT_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_evt_init_t *pstcTmr4EventInit); +void TMR4_EVT_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_EVT_SetDelayObject(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object); +void TMR4_EVT_SetMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16MaskTime); +uint16_t TMR4_EVT_GetMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_EVT_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value); +uint16_t TMR4_EVT_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_EVT_SetOutputEvent(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Event); +void TMR4_EVT_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16BufCond); +void TMR4_EVT_BufIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR4_EVT_EventIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, + uint16_t u16MaskType, en_functional_state_t enNewState); +void TMR4_EVT_MatchCondCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState); +/** + * @} + */ + +/** + * @} + */ + +#endif /* LL_TMR4_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TMR4_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_tmr6.h b/mcu/lib/inc/hc32_ll_tmr6.h new file mode 100644 index 0000000..e909053 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_tmr6.h @@ -0,0 +1,795 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr6.h + * @brief This file contains all the functions prototypes of the TMR6 driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-01-15 CDT Modify structure stc_timer6_init_t to stc_tmr6_init_t + Modify macro define for group TMR6_hardware_xxx_condition_Define + Modify macro define for group TMR6_HW_Count_xx_Cond_Define + Modify macro define for group TMR6_Valid_Period_Count_Cond_Define + Modify API TMR6_SetFilterClockDiv() + 2023-06-30 CDT Modify for TMR6_Count_Mode_Define + Delete union in stc_tmr6_init_t structure + 2023-09-30 CDT Add macro define for TMR6_Count_Dir_Status_Define + Modify typo + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TMR6_H__ +#define __HC32_LL_TMR6_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TMR6 + * @{ + */ + +#if (LL_TMR6_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TMR6_Global_Types TMR6 Global Types + * @{ + */ + +/** + * @brief Timer6 count function structure definition + */ +typedef struct { + uint8_t u8CountSrc; /*!< Specifies the count source @ref TMR6_Count_Src_Define */ + struct { + uint32_t u32ClockDiv; /*!< Count clock division select, @ref TMR6_Count_Clock_Define */ + uint32_t u32CountMode; /*!< Count mode, @ref TMR6_Count_Mode_Define */ + uint32_t u32CountDir; /*!< Count direction, @ref TMR6_Count_Dir_Define */ + } sw_count; + struct { + uint32_t u32CountUpCond; /*!< Hardware count up condition. @ref TMR6_HW_Count_Up_Cond_Define */ + uint32_t u32CountDownCond; /*!< Hardware count down condition. @ref TMR6_HW_Count_Down_Cond_Define */ + } hw_count; + uint32_t u32PeriodValue; /*!< The period reference value. (0x00 ~ 0xFFFF) or (0x00 ~ 0xFFFFFFFF) */ +} stc_tmr6_init_t; + +/** + * @brief Timer6 pwm output function structure definition + */ +typedef struct { + uint32_t u32CompareValue; /*!< Range (0 ~ 0xFFFF) or (0 ~ 0xFFFFFFFF) */ + uint32_t u32StartPolarity; /*!< Pin polarity when count start @ref TMR6_Pin_Polarity_Define */ + uint32_t u32StopPolarity; /*!< Pin polarity when count stop @ref TMR6_Pin_Polarity_Define */ + uint32_t u32CompareMatchPolarity; /*! Pin polarity when compare register @ref TMR6_Pin_Polarity_Define */ + uint32_t u32PeriodMatchPolarity; /*! Pin polarity when period register @ref TMR6_Pin_Polarity_Define */ + uint32_t u32StartStopHold; /*! Pin polarity hold when count re-start or re-stop \ + @ref TMR6_Output_StaStp_Hold_Define */ +} stc_tmr6_pwm_init_t; + +/** + * @brief Timer6 buffer function configuration structure definition + */ +typedef struct { + uint32_t u32BufNum; /*!< The buffer number, and this parameter can be a value of \ + @ref TMR6_Buf_Num_Define */ + uint32_t u32BufTransCond; /*!< The buffer send time, and this parameter can be a value of \ + @ref TMR6_Buf_Trans_Cond_Define */ +} stc_tmr6_buf_config_t; + +/** + * @brief Timer6 Valid period function configuration structure definition + */ +typedef struct { + uint32_t u32CountCond; /*!< The count condition, and this parameter can be a value of \ + @ref TMR6_Valid_Period_Count_Cond_Define */ + uint32_t u32PeriodInterval; /*!< The interval of the valid period @ref TMR6_Valid_Period_Count_Define */ +} stc_tmr6_valid_period_config_t; + +/** + * @brief Timer6 EMB configuration structure definition + */ +typedef struct { + uint32_t u32PinStatus; /*!< Pin output status when EMB event valid @ref TMR6_Emb_Pin_Status_Define */ +} stc_tmr6_emb_config_t; + +/** + * @brief Timer6 Dead time function configuration structure definition + */ +typedef struct { + uint32_t u32EqualUpDown; /*!< Enable down count dead time register equal to up count DT register \ + @ref TMR6_Deadtime_Reg_Equal_Func_Define */ + uint32_t u32BufUp; /*!< Enable buffer transfer for up count dead time register (DTUBR-->DTUAR) \ + @ref TMR6_Deadtime_CountUp_Buf_Func_Define*/ + uint32_t u32BufDown; /*!< Enable buffer transfer for down count dead time register (DTDBR-->DTDAR) \ + @ref TMR6_Deadtime_CountDown_Buf_Func_Define*/ +} stc_tmr6_deadtime_config_t; + +/** + * @brief Timer6 Dead time function configuration structure definition + */ +typedef struct { + uint32_t u32ZMaskCycle; /*!< Z phase input mask periods selection @ref TMR6_Zmask_Cycle_Define */ + uint32_t u32PosCountMaskFunc; /*!< As position count timer, clear function enable(TRUE) or disable(FALSE) during \ + the time of Z phase input mask @ref TMR6_Zmask_Pos_Unit_Clear_Func_Define */ + uint32_t u32RevoCountMaskFunc; /*!< As revolution count timer, the counter function enable(TRUE) or disable(FALSE) \ + during the time of Z phase input mask \ + @ref TMR6_Zmask_Revo_Unit_Count_Func_Define*/ +} stc_tmr6_zmask_config_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR6_Global_Macros TMR6 Global Macros + * @{ + */ + +/** + * @defgroup TMR6_Count_Src_Define TMR6 Count Source Define + * @{ + */ +#define TMR6_CNT_SRC_SW (0U) /*!< Timer6 normal count function */ +#define TMR6_CNT_SRC_HW (1U) /*!< Timer6 hardware count function */ +/** + * @} + */ + +/** + * @defgroup TMR6_Stat_Flag_Define TMR6 Status Flag Define + * @{ + */ +#define TMR6_FLAG_MATCH_A (TMR6_STFLR_CMAF) /*!< GCMAR match counter */ +#define TMR6_FLAG_MATCH_B (TMR6_STFLR_CMBF) /*!< GCMBR match counter */ +#define TMR6_FLAG_MATCH_C (TMR6_STFLR_CMCF) /*!< GCMCR match counter */ +#define TMR6_FLAG_MATCH_D (TMR6_STFLR_CMDF) /*!< GCMDR match counter */ +#define TMR6_FLAG_MATCH_E (TMR6_STFLR_CMEF) /*!< GCMER match counter */ +#define TMR6_FLAG_MATCH_F (TMR6_STFLR_CMFF) /*!< GCMFR match counter */ +#define TMR6_FLAG_OVF (TMR6_STFLR_OVFF) /*!< Sawtooth wave counter overflow, \ + Triangular wave peak point */ +#define TMR6_FLAG_UDF (TMR6_STFLR_UDFF) /*!< Sawtooth wave counter underflow, \ + Triangular wave valley point */ +#define TMR6_FLAG_DEAD_TIME_ERR (TMR6_STFLR_DTEF) /*!< Dead time error */ +#define TMR6_FLAG_UP_CNT_SPECIAL_MATCH_A (TMR6_STFLR_CMSAUF) /*!< SCMAR match counter when count-up */ +#define TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_A (TMR6_STFLR_CMSADF) /*!< SCMAR match counter when count-down */ +#define TMR6_FLAG_UP_CNT_SPECIAL_MATCH_B (TMR6_STFLR_CMSBUF) /*!< SCMBR match counter when count-up */ +#define TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_B (TMR6_STFLR_CMSBDF) /*!< SCMBR match counter when count-down */ +#define TMR6_FLAG_CNT_DIR (TMR6_STFLR_DIRF) /*!< Count direction flag */ + +#define TMR6_FLAG_CLR_ALL (0x00001EFFUL) /*!< Clear all flag */ +#define TMR6_FLAG_ALL (TMR6_FLAG_MATCH_A | TMR6_FLAG_MATCH_B | TMR6_FLAG_MATCH_C | \ + TMR6_FLAG_MATCH_D | TMR6_FLAG_MATCH_E | TMR6_FLAG_MATCH_F | \ + TMR6_FLAG_OVF | TMR6_FLAG_UDF | TMR6_FLAG_DEAD_TIME_ERR | \ + TMR6_FLAG_UP_CNT_SPECIAL_MATCH_A | TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_A | \ + TMR6_FLAG_UP_CNT_SPECIAL_MATCH_B | TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_B | \ + TMR6_FLAG_CNT_DIR) + +/** + * @} + */ + +/** + * @defgroup TMR6_Int_Flag_Define TMR6 Interrupt Flag Define + * @{ + */ +#define TMR6_INT_MATCH_A (TMR6_ICONR_INTENA) /*!< GCMAR register matched */ +#define TMR6_INT_MATCH_B (TMR6_ICONR_INTENB) /*!< GCMBR register matched */ +#define TMR6_INT_MATCH_C (TMR6_ICONR_INTENC) /*!< GCMCR register matched */ +#define TMR6_INT_MATCH_D (TMR6_ICONR_INTEND) /*!< GCMDR register matched */ +#define TMR6_INT_MATCH_E (TMR6_ICONR_INTENE) /*!< GCMER register matched */ +#define TMR6_INT_MATCH_F (TMR6_ICONR_INTENF) /*!< GCMFR register matched */ +#define TMR6_INT_OVF (TMR6_ICONR_INTENOVF) /*!< Counter register overflow */ +#define TMR6_INT_UDF (TMR6_ICONR_INTENUDF) /*!< Counter register underflow */ +#define TMR6_INT_DEAD_TIME_ERR (TMR6_ICONR_INTENDTE) /*!< Dead time error */ +#define TMR6_INT_UP_CNT_SPECIAL_MATCH_A (TMR6_ICONR_INTENSAU) /*!< SCMAR register matched when count-up */ +#define TMR6_INT_DOWN_CNT_SPECIAL_MATCH_A (TMR6_ICONR_INTENSAD) /*!< SCMAR register matched when count-down */ +#define TMR6_INT_UP_CNT_SPECIAL_MATCH_B (TMR6_ICONR_INTENSBU) /*!< SCMBR register matched when count-up */ +#define TMR6_INT_DOWN_CNT_SPECIAL_MATCH_B (TMR6_ICONR_INTENSBD) /*!< SCMBR register matched when count-down */ +#define TMR6_INT_ALL (TMR6_INT_MATCH_A | TMR6_INT_MATCH_B | TMR6_INT_MATCH_C | TMR6_INT_MATCH_D |\ + TMR6_INT_MATCH_E | TMR6_INT_MATCH_F | TMR6_INT_OVF | TMR6_INT_UDF | \ + TMR6_INT_DEAD_TIME_ERR | TMR6_INT_UP_CNT_SPECIAL_MATCH_A | \ + TMR6_INT_DOWN_CNT_SPECIAL_MATCH_A | TMR6_INT_UP_CNT_SPECIAL_MATCH_B | \ + TMR6_INT_DOWN_CNT_SPECIAL_MATCH_B) +/** + * @} + */ + +/** + * @defgroup TMR6_Period_Reg_Index_Define TMR6 Period Register Index Define + * @{ + */ +#define TMR6_PERIOD_REG_A (0x00UL) +#define TMR6_PERIOD_REG_B (0x01UL) +#define TMR6_PERIOD_REG_C (0x02UL) +/** + * @} + */ + +/** + * @defgroup TMR6_Compare_Reg_Index_Define TMR6 Compare Register Index Define + * @{ + */ +#define TMR6_CMP_REG_A (0x00UL) +#define TMR6_CMP_REG_B (0x01UL) +#define TMR6_CMP_REG_C (0x02UL) +#define TMR6_CMP_REG_D (0x03UL) +#define TMR6_CMP_REG_E (0x04UL) +#define TMR6_CMP_REG_F (0x05UL) +/** + * @} + */ + +/** + * @defgroup TMR6_Count_Ch_Define TMR6 General/Special Compare Channel Define + * @{ + */ +#define TMR6_CH_A (0x00UL) +#define TMR6_CH_B (0x01UL) +/** + * @} + */ + +/** + * @defgroup TMR6_Buf_Num_Define TMR6 Buffer Number Define + * @{ + */ +#define TMR6_BUF_SINGLE (0x00UL) +#define TMR6_BUF_DUAL (TMR6_BCONR_BSEA) +/** + * @} + */ + +/** + * @defgroup TMR6_Buf_Trans_Cond_Define TMR6 Buffer Transfer Time Configuration Define + * @{ + */ +#define TMR6_BUF_TRANS_INVD (0x00UL) +#define TMR6_BUF_TRANS_OVF (0x00000004UL) +#define TMR6_BUF_TRANS_UDF (0x00000008UL) +#define TMR6_BUF_TRANS_OVF_UDF (0x0000000CUL) + +/** + * @} + */ + +/** + * @defgroup TMR6_Valid_Period_Count_Cond_Define TMR6 Valid Period Function Count Condition Define + * @{ + */ +#define TMR6_VALID_PERIOD_INVD (0x00UL) /*!< Valid period function off */ +#define TMR6_VALID_PERIOD_CNT_COND_VALLEY (TMR6_VPERR_PCNTE_0) /*!< Count when Sawtooth waveform overflow and underflow, \ + triangular wave valley */ +#define TMR6_VALID_PERIOD_CNT_COND_PEAK (TMR6_VPERR_PCNTE_1) /*!< Count when Sawtooth waveform overflow and underflow, \ + triangular wave peak */ +#define TMR6_VALID_PERIOD_CNT_COND_VALLEY_PEAK (TMR6_VPERR_PCNTE) /*!< Count when Sawtooth waveform overflow and underflow, \ + triangular wave valley and peak */ +/** + * @} + */ + +/** + * @defgroup TMR6_Valid_Period_Count_Define TMR6 Valid Period Function Count Define + * @{ + */ +#define TMR6_VALID_PERIOD_CNT_INVD (0x00UL) +#define TMR6_VALID_PERIOD_CNT1 (1UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT2 (2UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT3 (3UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT4 (4UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT5 (5UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT6 (6UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT7 (7UL << TMR6_VPERR_PCNTS_POS) +/** + * @} + */ + +/** + * @defgroup TMR6_DeadTime_Reg_Define TMR6 Dead Time Register Define + * @{ + */ +#define TMR6_DEADTIME_REG_UP_A (0x00U) /*!< Register DTUAR */ +#define TMR6_DEADTIME_REG_DOWN_A (0x01U) /*!< Register DTDAR */ +#define TMR6_DEADTIME_REG_UP_B (0x02U) /*!< Register DTUBR */ +#define TMR6_DEADTIME_REG_DOWN_B (0x03U) /*!< Register DTDBR */ +/** + * @} + */ + +/** + * @defgroup TMR6_Pin_Define TMR6 Input And Output Pin Define + * @{ + */ +#define TMR6_IO_PWMA (0x00U) /*!< Pin TIM6__PWMA */ +#define TMR6_IO_PWMB (0x01U) /*!< Pin TIM6__PWMB */ +#define TMR6_INPUT_TRIGA (0x02U) /*!< Input pin TIM6_TRIGA */ +#define TMR6_INPUT_TRIGB (0x03U) /*!< Input pin TIM6_TRIGB */ +/** + * @} + */ + +/** + * @defgroup TMR6_Input_Filter_Clock TMR6 Input Pin Filter Clock Divider Define + * @{ + */ +#define TMR6_FILTER_CLK_DIV1 (0x00U) +#define TMR6_FILTER_CLK_DIV4 (0x01U) +#define TMR6_FILTER_CLK_DIV16 (0x02U) +#define TMR6_FILTER_CLK_DIV64 (0x03U) +/** + * @} + */ + +/** + * @defgroup TMR6_Pin_Mode_Define TMR6 Pin Function Mode Selection + * @{ + */ +#define TMR6_PIN_CMP_OUTPUT (0x00UL) +#define TMR6_PIN_CAPT_INPUT (TMR6_PCONR_CAPMDA) +/** + * @} + */ + +/** + * @defgroup TMR6_Count_State_Define TMR6 Count State + * @{ + */ +#define TMR6_STAT_START (0U) /*!< Count start */ +#define TMR6_STAT_STOP (1U) /*!< Count stop */ +#define TMR6_STAT_MATCH_CMP (2U) /*!< Count match compare register */ +#define TMR6_STAT_MATCH_PERIOD (3U) /*!< Count match period register */ + +/** + * @} + */ + +/** + * @defgroup TMR6_Pin_Polarity_Define TMR6 Pin Output Polarity + * @{ + */ + +#define TMR6_PWM_LOW (0x00U) +#define TMR6_PWM_HIGH (0x01U) +#define TMR6_PWM_HOLD (0x02U) +#define TMR6_PWM_INVT (0x03U) +/** + * @} + */ + +/** + * @defgroup TMR6_Output_StaStp_Hold_Define TMR6 Output Polarity Hold When Count Start And Stop + * @{ + */ +#define TMR6_PWM_START_STOP_HOLD (TMR6_PCONR_STASTPSA) +#define TMR6_PWM_START_STOP_CHANGE (0x00UL) +/** + * @} + */ + +/** + * @defgroup TMR6_Emb_Pin_Status_Define TMR6 Pin Output Status When EMB Event Valid + * @{ + */ +#define TMR6_EMB_PIN_NORMAL (0x00UL) +#define TMR6_EMB_PIN_HIZ (TMR6_PCONR_EMBVALA_0) +#define TMR6_EMB_PIN_LOW (TMR6_PCONR_EMBVALA_1) +#define TMR6_EMB_PIN_HIGH (TMR6_PCONR_EMBVALA) +/** + * @} + */ + +/** + * @defgroup TMR6_Deadtime_CountUp_Buf_Func_Define TMR6 Dead Time Buffer Function For Count Up Stage + * @{ + */ +#define TMR6_DEADTIME_CNT_UP_BUF_OFF (0x00UL) +#define TMR6_DEADTIME_CNT_UP_BUF_ON (TMR6_DCONR_DTBENU) +/** + * @} + */ + +/** + * @defgroup TMR6_Deadtime_CountDown_Buf_Func_Define TMR6 Dead Time Buffer Function For Count Down Stage + * @{ + */ +#define TMR6_DEADTIME_CNT_DOWN_BUF_OFF (0x00UL) +#define TMR6_DEADTIME_CNT_DOWN_BUF_ON (TMR6_DCONR_DTBEND) +/** + * @} + */ + +/** + * @defgroup TMR6_Deadtime_Reg_Equal_Func_Define TMR6 Dead Time Function DTDAR Equal DTUAR + * @{ + */ +#define TMR6_DEADTIME_EQUAL_OFF (0x00UL) +#define TMR6_DEADTIME_EQUAL_ON (TMR6_DCONR_SEPA) +/** + * @} + */ + +/** + * @defgroup TMR6_SW_Sync_Unit_define TMR6 Software Synchronization Start/Stop/Clear/Update Unit Number Define + * @{ + */ +#define TMR6_SW_SYNC_U1 (TMR6CR_SSTAR_SSTA1) +#define TMR6_SW_SYNC_U2 (TMR6CR_SSTAR_SSTA2) +#define TMR6_SW_SYNC_U3 (TMR6CR_SSTAR_SSTA3) +#define TMR6_SW_SYNC_ALL (0x07UL) + +/** + * @} + */ + +/** + * @defgroup TMR6_hardware_start_condition_Define TMR6 Hardware Start Condition Define + * @{ + */ +#define TMR6_START_COND_EVT0 (TMR6_HSTAR_HSTA0) +#define TMR6_START_COND_EVT1 (TMR6_HSTAR_HSTA1) +#define TMR6_START_COND_PWMA_RISING (TMR6_HSTAR_HSTA4) +#define TMR6_START_COND_PWMA_FALLING (TMR6_HSTAR_HSTA5) +#define TMR6_START_COND_PWMB_RISING (TMR6_HSTAR_HSTA6) +#define TMR6_START_COND_PWMB_FALLING (TMR6_HSTAR_HSTA7) +#define TMR6_START_COND_TRIGA_RISING (TMR6_HSTAR_HSTA8) +#define TMR6_START_COND_TRIGA_FALLING (TMR6_HSTAR_HSTA9) +#define TMR6_START_COND_TRIGB_RISING (TMR6_HSTAR_HSTA10) +#define TMR6_START_COND_TRIGB_FALLING (TMR6_HSTAR_HSTA11) +#define TMR6_START_COND_ALL (0x00000FF3UL) + +/** + * @} + */ + +/** + * @defgroup TMR6_hardware_stop_condition_Define TMR6 Hardware Stop Condition Define + * @{ + */ +#define TMR6_STOP_COND_EVT0 (TMR6_HSTPR_HSTP0) +#define TMR6_STOP_COND_EVT1 (TMR6_HSTPR_HSTP1) +#define TMR6_STOP_COND_PWMA_RISING (TMR6_HSTPR_HSTP4) +#define TMR6_STOP_COND_PWMA_FALLING (TMR6_HSTPR_HSTP5) +#define TMR6_STOP_COND_PWMB_RISING (TMR6_HSTPR_HSTP6) +#define TMR6_STOP_COND_PWMB_FALLING (TMR6_HSTPR_HSTP7) +#define TMR6_STOP_COND_TRIGA_RISING (TMR6_HSTPR_HSTP8) +#define TMR6_STOP_COND_TRIGA_FALLING (TMR6_HSTPR_HSTP9) +#define TMR6_STOP_COND_TRIGB_RISING (TMR6_HSTPR_HSTP10) +#define TMR6_STOP_COND_TRIGB_FALLING (TMR6_HSTPR_HSTP11) +#define TMR6_STOP_COND_ALL (0x00000FF3UL) + +/** + * @} + */ + +/** + * @defgroup TMR6_hardware_clear_condition_Define TMR6 Hardware Clear Condition Define + * @{ + */ +#define TMR6_CLR_COND_EVT0 (TMR6_HCLRR_HCLE0) +#define TMR6_CLR_COND_EVT1 (TMR6_HCLRR_HCLE1) +#define TMR6_CLR_COND_PWMA_RISING (TMR6_HCLRR_HCLE4) +#define TMR6_CLR_COND_PWMA_FALLING (TMR6_HCLRR_HCLE5) +#define TMR6_CLR_COND_PWMB_RISING (TMR6_HCLRR_HCLE6) +#define TMR6_CLR_COND_PWMB_FALLING (TMR6_HCLRR_HCLE7) +#define TMR6_CLR_COND_TRIGA_RISING (TMR6_HCLRR_HCLE8) +#define TMR6_CLR_COND_TRIGA_FALLING (TMR6_HCLRR_HCLE9) +#define TMR6_CLR_COND_TRIGB_RISING (TMR6_HCLRR_HCLE10) +#define TMR6_CLR_COND_TRIGB_FALLING (TMR6_HCLRR_HCLE11) +#define TMR6_CLR_COND_ALL (0x00000FF3UL) + +/** + * @} + */ + +/** + * @defgroup TMR6_hardware_capture_condition_Define TMR6 Hardware Capture Condition Define + * @{ + */ +#define TMR6_CAPT_COND_EVT0 (TMR6_HCPAR_HCPA0) +#define TMR6_CAPT_COND_EVT1 (TMR6_HCPAR_HCPA1) +#define TMR6_CAPT_COND_PWMA_RISING (TMR6_HCPAR_HCPA4) +#define TMR6_CAPT_COND_PWMA_FALLING (TMR6_HCPAR_HCPA5) +#define TMR6_CAPT_COND_PWMB_RISING (TMR6_HCPAR_HCPA6) +#define TMR6_CAPT_COND_PWMB_FALLING (TMR6_HCPAR_HCPA7) +#define TMR6_CAPT_COND_TRIGA_RISING (TMR6_HCPAR_HCPA8) +#define TMR6_CAPT_COND_TRIGA_FALLING (TMR6_HCPAR_HCPA9) +#define TMR6_CAPT_COND_TRIGB_RISING (TMR6_HCPAR_HCPA10) +#define TMR6_CAPT_COND_TRIGB_FALLING (TMR6_HCPAR_HCPA11) +#define TMR6_CAPT_COND_ALL (0x00000FF3UL) +/** + * @} + */ + +/** + * @defgroup TMR6_HW_Count_Up_Cond_Define TMR6 Hardware Count Up Condition Define + * @{ + */ +#define TMR6_CNT_UP_COND_INVD (0U) +#define TMR6_CNT_UP_COND_PWMA_LOW_PWMB_RISING (TMR6_HCUPR_HCUP0) +#define TMR6_CNT_UP_COND_PWMA_LOW_PWMB_FALLING (TMR6_HCUPR_HCUP1) +#define TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING (TMR6_HCUPR_HCUP2) +#define TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_FALLING (TMR6_HCUPR_HCUP3) +#define TMR6_CNT_UP_COND_PWMB_LOW_PWMA_RISING (TMR6_HCUPR_HCUP4) +#define TMR6_CNT_UP_COND_PWMB_LOW_PWMA_FALLING (TMR6_HCUPR_HCUP5) +#define TMR6_CNT_UP_COND_PWMB_HIGH_PWMA_RISING (TMR6_HCUPR_HCUP6) +#define TMR6_CNT_UP_COND_PWMB_HIGH_PWMA_FALLING (TMR6_HCUPR_HCUP7) +#define TMR6_CNT_UP_COND_TRIGA_RISING (TMR6_HCUPR_HCUP8) +#define TMR6_CNT_UP_COND_TRIGA_FALLING (TMR6_HCUPR_HCUP9) +#define TMR6_CNT_UP_COND_TRIGB_RISING (TMR6_HCUPR_HCUP10) +#define TMR6_CNT_UP_COND_TRIGB_FALLING (TMR6_HCUPR_HCUP11) +#define TMR6_CNT_UP_COND_EVT0 (TMR6_HCUPR_HCUP16) +#define TMR6_CNT_UP_COND_EVT1 (TMR6_HCUPR_HCUP17) +#define TMR6_CNT_UP_COND_ALL (0x00030FFFUL) + +/** + * @} + */ + +/** + * @defgroup TMR6_HW_Count_Down_Cond_Define TMR6 Hardware Count Down Condition Define + * @{ + */ +#define TMR6_CNT_DOWN_COND_INVD (0U) +#define TMR6_CNT_DOWN_COND_PWMA_LOW_PWMB_RISING (TMR6_HCDOR_HCDO0) +#define TMR6_CNT_DOWN_COND_PWMA_LOW_PWMB_FALLING (TMR6_HCDOR_HCDO1) +#define TMR6_CNT_DOWN_COND_PWMA_HIGH_PWMB_RISING (TMR6_HCDOR_HCDO2) +#define TMR6_CNT_DOWN_COND_PWMA_HIGH_PWMB_FALLING (TMR6_HCDOR_HCDO3) +#define TMR6_CNT_DOWN_COND_PWMB_LOW_PWMA_RISING (TMR6_HCDOR_HCDO4) +#define TMR6_CNT_DOWN_COND_PWMB_LOW_PWMA_FALLING (TMR6_HCDOR_HCDO5) +#define TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING (TMR6_HCDOR_HCDO6) +#define TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_FALLING (TMR6_HCDOR_HCDO7) +#define TMR6_CNT_DOWN_COND_TRIGA_RISING (TMR6_HCDOR_HCDO8) +#define TMR6_CNT_DOWN_COND_TRIGA_FALLING (TMR6_HCDOR_HCDO9) +#define TMR6_CNT_DOWN_COND_TRIGB_RISING (TMR6_HCDOR_HCDO10) +#define TMR6_CNT_DOWN_COND_TRIGB_FALLING (TMR6_HCDOR_HCDO11) +#define TMR6_CNT_DOWN_COND_EVT0 (TMR6_HCDOR_HCDO16) +#define TMR6_CNT_DOWN_COND_EVT1 (TMR6_HCDOR_HCDO17) +#define TMR6_CNT_DOWN_COND_ALL (0x00030FFFUL) + +/** + * @} + */ + +/** + * @defgroup TMR6_Count_Dir_Define TMR6 Base Counter Function Direction Define + * @{ + */ +#define TMR6_CNT_UP (TMR6_GCONR_DIR) +#define TMR6_CNT_DOWN (0x00UL) +/** + * @} + */ + +/** + * @defgroup TMR6_Count_Dir_Status_Define TMR6 Count Direction Status Define + * @{ + */ +#define TMR6_STAT_CNT_UP (TMR6_STFLR_DIRF) +#define TMR6_STAT_CNT_DOWN (0x00UL) +/** + * @} + */ + +/** + * @defgroup TMR6_Count_Mode_Define TMR6 Base Counter Function Mode Define + * @{ + */ +#define TMR6_MD_SAWTOOTH (0x00UL) +#define TMR6_MD_TRIANGLE_A (0x04UL << TMR6_GCONR_MODE_POS) +#define TMR6_MD_TRIANGLE_B (0x05UL << TMR6_GCONR_MODE_POS) +/** + * @} + */ + +/** + * @defgroup TMR6_Count_Clock_Define TMR6 Base Counter Clock Source Define + * @{ + */ +#define TMR6_CLK_DIV1 (0x00UL) +#define TMR6_CLK_DIV2 (0x01UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV4 (0x02UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV8 (0x03UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV16 (0x04UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV64 (0x05UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV256 (0x06UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV1024 (0x07UL << TMR6_GCONR_CKDIV_POS) +/** + * @} + */ + +/** + * @defgroup TMR6_Zmask_Cycle_Define TMR6 Z Mask Input Function Mask Cycles Number Define + * @{ + */ +#define TMR6_ZMASK_FUNC_INVD (0x00UL) +#define TMR6_ZMASK_CYCLE_4 (TMR6_GCONR_ZMSKVAL_0) +#define TMR6_ZMASK_CYCLE_8 (TMR6_GCONR_ZMSKVAL_1) +#define TMR6_ZMASK_CYCLE_16 (TMR6_GCONR_ZMSKVAL) +/** + * @} + */ + +/** + * @defgroup TMR6_Zmask_Pos_Unit_Clear_Func_Define TMR6 Unit As Position Timer, Z Phase Input Mask Function Define For Clear Action + * @{ + */ +#define TMR6_POS_CLR_ZMASK_FUNC_OFF (0x00UL) +#define TMR6_POS_CLR_ZMASK_FUNC_ON (TMR6_GCONR_ZMSKPOS) +/** + * @} + */ + +/** + * @defgroup TMR6_Zmask_Revo_Unit_Count_Func_Define TMR6 Unit As Revolution Timer, Z Phase Input Mask Function Define For Count Action + * @{ + */ +#define TMR6_REVO_CNT_ZMASK_FUNC_OFF (0x00UL) +#define TMR6_REVO_CNT_ZMASK_FUNC_ON (TMR6_GCONR_ZMSKREV) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TMR6_Global_Functions + * @{ + */ +/** + * @brief Get Software Sync start status + * @param None + * @retval uint32_t Data indicate the read status. + */ +__STATIC_INLINE uint32_t TMR6_GetSWSyncStartStatus(void) +{ + return READ_REG32(CM_TMR6CR->SSTAR); +} + +/* Base count */ +int32_t TMR6_StructInit(stc_tmr6_init_t *pstcTmr6Init); +int32_t TMR6_Init(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_init_t *pstcTmr6Init); + +void TMR6_SetCountMode(CM_TMR6_TypeDef *TMR6x, uint32_t u32Mode); +void TMR6_SetCountDir(CM_TMR6_TypeDef *TMR6x, uint32_t u32Dir); +uint32_t TMR6_GetCountDir(CM_TMR6_TypeDef *TMR6x); +void TMR6_SetClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Div); + +/* Hardware count */ +void TMR6_HWCountUpCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); +void TMR6_HWCountDownCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); + +/* PWM output */ +int32_t TMR6_PWM_StructInit(stc_tmr6_pwm_init_t *pstcPwmInit); +int32_t TMR6_PWM_Init(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_pwm_init_t *pstcPwmInit); +void TMR6_PWM_OutputCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR6_PWM_SetPolarity(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32CountState, uint32_t u32Polarity); +void TMR6_PWM_SetStartStopHold(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32HoldStatus); + +/* Input capture */ +void TMR6_HWCaptureCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState); + +/* Pin config */ +/* note: Please make sure that peripheral clock of CM_TMR6_1 is valid if The TRIGX pin is used.*/ +void TMR6_SetFilterClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, uint32_t u32Div); +void TMR6_FilterCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, en_functional_state_t enNewState); +void TMR6_SetFunc(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Func); + +/* Universal */ +void TMR6_IntCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t TMR6_GetStatus(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag); +void TMR6_ClearStatus(CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag); +uint32_t TMR6_GetPeriodNum(const CM_TMR6_TypeDef *TMR6x); +void TMR6_DeInit(CM_TMR6_TypeDef *TMR6x); +void TMR6_Start(CM_TMR6_TypeDef *TMR6x); +void TMR6_Stop(CM_TMR6_TypeDef *TMR6x); + +/* Register write */ +void TMR6_SetCountValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Value); +void TMR6_SetPeriodValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value); +void TMR6_SetCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value); +void TMR6_SetSpecialCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value); +void TMR6_SetDeadTimeValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value); + +/* Register read */ +uint32_t TMR6_GetCountValue(const CM_TMR6_TypeDef *TMR6x); +uint32_t TMR6_GetPeriodValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index); +uint32_t TMR6_GetCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index); +uint32_t TMR6_GetSpecialCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index); +uint32_t TMR6_GetDeadTimeValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index); + +/* Buffer function */ +void TMR6_SetGeneralBufNum(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32BufNum); +void TMR6_SetPeriodBufNum(CM_TMR6_TypeDef *TMR6x, uint32_t u32BufNum); + +int32_t TMR6_SpecialBufConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_buf_config_t *pstcBufConfig); +void TMR6_GeneralBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR6_SpecialBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR6_PeriodBufCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); + +/* Extend function */ +int32_t TMR6_ValidPeriodConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_valid_period_config_t *pstcValidperiodConfig); +void TMR6_ValidPeriodCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR6_DeadTimeFuncCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +int32_t TMR6_DeadTimeConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_deadtime_config_t *pstcDeadTimeConfig); +int32_t TMR6_ZMaskConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_zmask_config_t *pstcZMaskConfig); +int32_t TMR6_EMBConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_emb_config_t *pstcEmbConfig); +int32_t TMR6_BufFuncStructInit(stc_tmr6_buf_config_t *pstcBufConfig); +int32_t TMR6_ValidPeriodStructInit(stc_tmr6_valid_period_config_t *pstcValidperiodConfig); +int32_t TMR6_EMBConfigStructInit(stc_tmr6_emb_config_t *pstcEmbConfig); +int32_t TMR6_DeadTimeStructInit(stc_tmr6_deadtime_config_t *pstcDeadTimeConfig); +int32_t TMR6_ZMaskConfigStructInit(stc_tmr6_zmask_config_t *pstcZMaskConfig); + +/* Software synchronous control */ +void TMR6_SWSyncStart(uint32_t u32Unit); +void TMR6_SWSyncStop(uint32_t u32Unit); +void TMR6_SWSyncClear(uint32_t u32Unit); + +/* Hardware control */ +void TMR6_HWStartCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); +void TMR6_HWStartCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +void TMR6_HWStopCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); +void TMR6_HWStopCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +void TMR6_HWClearCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); +void TMR6_HWClearCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +/** + * @} + */ + +#endif /* LL_TMR6_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TMR6_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_tmra.h b/mcu/lib/inc/hc32_ll_tmra.h new file mode 100644 index 0000000..973b069 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_tmra.h @@ -0,0 +1,552 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmra.h + * @brief This file contains all the functions prototypes of the TMRA(TimerA) + * driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-10-31 CDT Comments optimization + 2023-06-30 CDT Modify typo + Update about split 16bit register TMRA_BCSTR into two 8bit registers TMRA_BCSTRH and TMRA_BCSTRL + Delete union in stc_tmra_init_t structure + 2023-09-30 CDT Modify some of member type of struct stc_tmra_init_t and relate fuction about these member + Modify macro-definition value for group TMRA_Interrupt_Type/TMRA_Status_Flag + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TMRA_H__ +#define __HC32_LL_TMRA_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TMRA + * @{ + */ + +#if (LL_TMRA_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TMRA_Global_Types TMRA Global Types + * @{ + */ +/** + * @brief TMRA initialization structure. + */ +typedef struct { + uint8_t u8CountSrc; /*!< Specifies the count source of TMRA. + This parameter can be a value of @ref TMRA_Count_Src */ + struct { + uint8_t u8ClockDiv; /*!< Specifies the divider of software clock source. + This parameter can be a value of @ref TMRA_Clock_Divider */ + uint8_t u8CountMode; /*!< Specifies count mode. + This parameter can be a value of @ref TMRA_Count_Mode */ + uint8_t u8CountDir; /*!< Specifies count direction. + This parameter can be a value of @ref TMRA_Count_Dir */ + } sw_count; + struct { + uint16_t u16CountUpCond; /*!< Hardware count up condition. + This parameter can be a value of @ref TMRA_Hard_Count_Up_Condition */ + uint16_t u16CountDownCond; /*!< Hardware count down condition. + This parameter can be a value of @ref TMRA_Hard_Count_Down_Condition */ + } hw_count; + uint32_t u32PeriodValue; /*!< Specifies the period reference value. + This parameter can be a number between 0U and 0xFFFFU, inclusive. */ +} stc_tmra_init_t; + +/** + * @brief TMRA PWM configuration structure. + */ +typedef struct { + uint32_t u32CompareValue; /*!< Specifies compare value of the TMRA channel. + This parameter can be a number between: + 0UL and 0xFFFFFFFFUL for 32-bit TimerA units. + 0UL and 0xFFFFUL for 16-bit TimerA units. */ + uint16_t u16StartPolarity; /*!< Specifies the polarity when the counter start counting. + This parameter can be a value of @ref TMRA_PWM_Polarity + NOTE: CAN NOT be specified as TMRA_PWM_LOW or TMRA_PWM_HIGH when + sw_count.u16ClockDiv of @ref stc_tmra_init_t is NOT specified + as @ref TMRA_CLK_DIV1 */ + uint16_t u16StopPolarity; /*!< Specifies the polarity when the counter stop counting. + This parameter can be a value of @ref TMRA_PWM_Polarity */ + uint16_t u16CompareMatchPolarity; /*!< Specifies the polarity when the counter matches the compare register. + This parameter can be a value of @ref TMRA_PWM_Polarity */ + uint16_t u16PeriodMatchPolarity; /*!< Specifies the polarity when the counter matches the period register. + This parameter can be a value of @ref TMRA_PWM_Polarity */ +} stc_tmra_pwm_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMRA_Global_Macros TMRA Global Macros + * @{ + */ + +/** + * @defgroup TMRA_Count_Src TMRA Count Source + * @{ + */ +#define TMRA_CNT_SRC_SW (0U) /*!< Clock source is PCLK. */ +#define TMRA_CNT_SRC_HW (1U) /*!< Clock source is from external pin or peripheral event. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Channel TMRA Channel + * @{ + */ +#define TMRA_CH1 (0U) /*!< Channel 1 of TMRA. */ +#define TMRA_CH2 (1U) /*!< Channel 2 of TMRA. */ +#define TMRA_CH3 (2U) /*!< Channel 3 of TMRA. */ +#define TMRA_CH4 (3U) /*!< Channel 4 of TMRA. */ +#define TMRA_CH5 (4U) /*!< Channel 5 of TMRA. */ +#define TMRA_CH6 (5U) /*!< Channel 6 of TMRA. */ +#define TMRA_CH7 (6U) /*!< Channel 7 of TMRA. */ +#define TMRA_CH8 (7U) /*!< Channel 8 of TMRA. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Count_Dir TMRA Count Direction + * @{ + */ +#define TMRA_DIR_DOWN (0x0U) /*!< TMRA count down. */ +#define TMRA_DIR_UP (TMRA_BCSTRL_DIR) /*!< TMRA count up. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Count_Mode TMRA Count Mode + * @{ + */ +#define TMRA_MD_SAWTOOTH (0x0U) /*!< Count mode is sawtooth wave. */ +#define TMRA_MD_TRIANGLE (TMRA_BCSTRL_MODE) /*!< Count mode is triangle wave. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Function_Mode TMRA TMRA Function Mode + * @{ + */ +#define TMRA_FUNC_CMP (0x0U) /*!< Function mode of TMRA channel is ouput compare. */ +#define TMRA_FUNC_CAPT (TMRA_CCONR_CAPMD) /*!< Function mode of TMRA channel is input capture. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Clock_Divider TMRA Clock Divider + * @{ + */ +#define TMRA_CLK_DIV1 (0x0U) /*!< The clock source of TMRA is PCLK. */ +#define TMRA_CLK_DIV2 (0x1U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 2. */ +#define TMRA_CLK_DIV4 (0x2U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 4. */ +#define TMRA_CLK_DIV8 (0x3U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 8. */ +#define TMRA_CLK_DIV16 (0x4U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 16. */ +#define TMRA_CLK_DIV32 (0x5U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 32. */ +#define TMRA_CLK_DIV64 (0x6U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 64. */ +#define TMRA_CLK_DIV128 (0x7U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 128. */ +#define TMRA_CLK_DIV256 (0x8U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 256. */ +#define TMRA_CLK_DIV512 (0x9U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 512. */ +#define TMRA_CLK_DIV1024 (0xAU << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 1024. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Filter_Pin TMRA Pin With Filter + * @{ + */ +#define TMRA_PIN_TRIG (0U) /*!< Pin TIMA__TRIG. */ +#define TMRA_PIN_CLKA (1U) /*!< Pin TIMA__CLKA. */ +#define TMRA_PIN_CLKB (2U) /*!< Pin TIMA__CLKB. */ +#define TMRA_PIN_PWM1 (3U) /*!< Pin TIMA__PWM1. */ +#define TMRA_PIN_PWM2 (4U) /*!< Pin TIMA__PWM2. */ +#define TMRA_PIN_PWM3 (5U) /*!< Pin TIMA__PWM3. */ +#define TMRA_PIN_PWM4 (6U) /*!< Pin TIMA__PWM4. */ +#define TMRA_PIN_PWM5 (7U) /*!< Pin TIMA__PWM5. */ +#define TMRA_PIN_PWM6 (8U) /*!< Pin TIMA__PWM6. */ +#define TMRA_PIN_PWM7 (9U) /*!< Pin TIMA__PWM7. */ +#define TMRA_PIN_PWM8 (10U) /*!< Pin TIMA__PWM8. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Hard_Count_Up_Condition TMRA Hardware Count Up Condition + * @note Symmetric units: unit 1 and 2; unit 3 and 4; ...; unit 11 and 12. + * @{ + */ +#define TMRA_CNT_UP_COND_INVD (0U) /*!< TMRA hardware count up condition is INVALID. */ +#define TMRA_CNT_UP_COND_CLKA_LOW_CLKB_RISING (TMRA_HCUPR_HCUP0) /*!< When CLKA is low, a rising edge is sampled on CLKB, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKA_LOW_CLKB_FALLING (TMRA_HCUPR_HCUP1) /*!< When CLKA is low, a falling edge is sampled on CLKB, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING (TMRA_HCUPR_HCUP2) /*!< When CLKA is high, a rising edge is sampled on CLKB, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_FALLING (TMRA_HCUPR_HCUP3) /*!< When CLKA is high, a falling edge is sampled on CLKB, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKB_LOW_CLKA_RISING (TMRA_HCUPR_HCUP4) /*!< When CLKB is low, a rising edge is sampled on CLKA, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKB_LOW_CLKA_FALLING (TMRA_HCUPR_HCUP5) /*!< When CLKB is low, a falling edge is sampled on CLKA, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKB_HIGH_CLKA_RISING (TMRA_HCUPR_HCUP6) /*!< When CLKB is high, a rising edge is sampled on CLKA, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKB_HIGH_CLKA_FALLING (TMRA_HCUPR_HCUP7) /*!< When CLKB is high, a falling edge is sampled on CLKA, the counter register counts up. */ +#define TMRA_CNT_UP_COND_TRIG_RISING (TMRA_HCUPR_HCUP8) /*!< When a rising edge occurred on TRIG, the counter register counts up. */ +#define TMRA_CNT_UP_COND_TRIG_FALLING (TMRA_HCUPR_HCUP9) /*!< When a falling edge occurred on TRIG, the counter register counts up. */ +#define TMRA_CNT_UP_COND_EVT (TMRA_HCUPR_HCUP10) /*!< When the TMRA common trigger event occurred, the counter register counts up. */ +#define TMRA_CNT_UP_COND_SYM_OVF (TMRA_HCUPR_HCUP11) /*!< When the symmetric unit overflow, the counter register counts up. */ +#define TMRA_CNT_UP_COND_SYM_UDF (TMRA_HCUPR_HCUP12) /*!< When the symmetric unit underflow, the counter register counts up. */ +#define TMRA_CNT_UP_COND_ALL (0x1FFFU) +/** + * @} + */ + +/** + * @defgroup TMRA_Hard_Count_Down_Condition TMRA Hardware Count Down Condition + * @note Symmetric units: unit 1 and 2; unit 3 and 4; ...; unit 11 and 12. + * @{ + */ +#define TMRA_CNT_DOWN_COND_INVD (0U) /*!< TMRA hardware count down condition is INVALID. */ +#define TMRA_CNT_DOWN_COND_CLKA_LOW_CLKB_RISING (TMRA_HCDOR_HCDO0) /*!< When CLKA is low, a rising edge is sampled on CLKB, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKA_LOW_CLKB_FALLING (TMRA_HCDOR_HCDO1) /*!< When CLKA is low, a falling edge is sampled on CLKB, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKA_HIGH_CLKB_RISING (TMRA_HCDOR_HCDO2) /*!< When CLKA is high, a rising edge is sampled on CLKB, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKA_HIGH_CLKB_FALLING (TMRA_HCDOR_HCDO3) /*!< When CLKA is high, a falling edge is sampled on CLKB, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKB_LOW_CLKA_RISING (TMRA_HCDOR_HCDO4) /*!< When CLKB is low, a rising edge is sampled on CLKA, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKB_LOW_CLKA_FALLING (TMRA_HCDOR_HCDO5) /*!< When CLKB is low, a falling edge is sampled on CLKA, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING (TMRA_HCDOR_HCDO6) /*!< When CLKB is high, a rising edge is sampled on CLKA, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_FALLING (TMRA_HCDOR_HCDO7) /*!< When CLKB is high, a falling edge is sampled on CLKA, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_TRIG_RISING (TMRA_HCDOR_HCDO8) /*!< When a rising edge occurred on TRIG, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_TRIG_FALLING (TMRA_HCDOR_HCDO9) /*!< When a falling edge occurred on TRIG, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_EVT (TMRA_HCDOR_HCDO10) /*!< When the TMRA common trigger event occurred, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_SYM_OVF (TMRA_HCDOR_HCDO11) /*!< When the symmetric unit overflow, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_SYM_UDF (TMRA_HCDOR_HCDO12) /*!< When the symmetric unit underflow, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_ALL (0x1FFFU) +/** + * @} + */ + +/** + * @defgroup TMRA_Interrupt_Type TMRA Interrupt Type + * @{ + */ +#define TMRA_INT_OVF (1UL << 4U) /*!< The interrupt of counting overflow. */ +#define TMRA_INT_UDF (1UL << 5U) /*!< The interrupt of counting underflow. */ +#define TMRA_INT_CMP_CH1 (1UL << 16U) /*!< The interrupt of compare-match of channel 1. */ +#define TMRA_INT_CMP_CH2 (1UL << 17U) /*!< The interrupt of compare-match of channel 2. */ +#define TMRA_INT_CMP_CH3 (1UL << 18U) /*!< The interrupt of compare-match of channel 3. */ +#define TMRA_INT_CMP_CH4 (1UL << 19U) /*!< The interrupt of compare-match of channel 4. */ +#define TMRA_INT_CMP_CH5 (1UL << 20U) /*!< The interrupt of compare-match of channel 5. */ +#define TMRA_INT_CMP_CH6 (1UL << 21U) /*!< The interrupt of compare-match of channel 6. */ +#define TMRA_INT_CMP_CH7 (1UL << 22U) /*!< The interrupt of compare-match of channel 7. */ +#define TMRA_INT_CMP_CH8 (1UL << 23U) /*!< The interrupt of compare-match of channel 8. */ +#define TMRA_INT_ALL (0xFF0030UL) +/** + * @} + */ + +/** + * @defgroup TMRA_Event_Type TMRA Event Type + * @{ + */ +#define TMRA_EVT_CMP_CH1 (TMRA_ECONR_ETEN1) /*!< The event of compare-match of channel 1. */ +#define TMRA_EVT_CMP_CH2 (TMRA_ECONR_ETEN2) /*!< The event of compare-match of channel 2. */ +#define TMRA_EVT_CMP_CH3 (TMRA_ECONR_ETEN3) /*!< The event of compare-match of channel 3. */ +#define TMRA_EVT_CMP_CH4 (TMRA_ECONR_ETEN4) /*!< The event of compare-match of channel 4. */ +#define TMRA_EVT_CMP_CH5 (TMRA_ECONR_ETEN5) /*!< The event of compare-match of channel 5. */ +#define TMRA_EVT_CMP_CH6 (TMRA_ECONR_ETEN6) /*!< The event of compare-match of channel 6. */ +#define TMRA_EVT_CMP_CH7 (TMRA_ECONR_ETEN7) /*!< The event of compare-match of channel 7. */ +#define TMRA_EVT_CMP_CH8 (TMRA_ECONR_ETEN8) /*!< The event of compare-match of channel 8. */ +#define TMRA_EVT_ALL (TMRA_EVT_CMP_CH1 | TMRA_EVT_CMP_CH2 | TMRA_EVT_CMP_CH3 | \ + TMRA_EVT_CMP_CH4 | TMRA_EVT_CMP_CH5 | TMRA_EVT_CMP_CH6 | \ + TMRA_EVT_CMP_CH7 | TMRA_EVT_CMP_CH8) +/** + * @} + */ + +/** + * @defgroup TMRA_Status_Flag TMRA Status Flag + * @{ + */ +#define TMRA_FLAG_OVF (1UL << 6U) /*!< The flag of counting overflow. */ +#define TMRA_FLAG_UDF (1UL << 7U) /*!< The flag of counting underflow. */ +#define TMRA_FLAG_CMP_CH1 (1UL << 16U) /*!< The flag of compare-match of channel 1. */ +#define TMRA_FLAG_CMP_CH2 (1UL << 17U) /*!< The flag of compare-match of channel 2. */ +#define TMRA_FLAG_CMP_CH3 (1UL << 18U) /*!< The flag of compare-match of channel 3. */ +#define TMRA_FLAG_CMP_CH4 (1UL << 19U) /*!< The flag of compare-match of channel 4. */ +#define TMRA_FLAG_CMP_CH5 (1UL << 20U) /*!< The flag of compare-match of channel 5. */ +#define TMRA_FLAG_CMP_CH6 (1UL << 21U) /*!< The flag of compare-match of channel 6. */ +#define TMRA_FLAG_CMP_CH7 (1UL << 22U) /*!< The flag of compare-match of channel 7. */ +#define TMRA_FLAG_CMP_CH8 (1UL << 23U) /*!< The flag of compare-match of channel 8. */ +#define TMRA_FLAG_ALL (0xFF00C0UL) +/** + * @} + */ + +/** + * @defgroup TMRA_Capture_Cond TMRA Capture Condition + * @note 'TMRA_CAPT_COND_TRIG_RISING' and 'TMRA_CAPT_COND_TRIG_FALLING' are only valid for channel 4. + * @{ + */ +#define TMRA_CAPT_COND_INVD (0x0U) /*!< The condition of capture is INVALID. */ +#define TMRA_CAPT_COND_PWM_RISING (TMRA_CCONR_HICP0) /*!< The condition of capture is a rising edge is sampled on pin TIMA__PWMn. */ +#define TMRA_CAPT_COND_PWM_FALLING (TMRA_CCONR_HICP1) /*!< The condition of capture is a falling edge is sampled on pin TIMA__PWMn. */ +#define TMRA_CAPT_COND_EVT (TMRA_CCONR_HICP2) /*!< The condition of capture is the specified event occurred. */ +#define TMRA_CAPT_COND_TRIG_RISING (TMRA_CCONR_HICP3) /*!< The condition of capture is a rising edge is sampled on pin TIMA__TRIG. + This condition is only valid for channel 4. */ +#define TMRA_CAPT_COND_TRIG_FALLING (TMRA_CCONR_HICP4) /*!< The condition of capture is a falling edge is sampled on pin TIMA__TRIG. + This condition is only valid for channel 4. */ +#define TMRA_CAPT_COND_ALL (TMRA_CAPT_COND_PWM_RISING | TMRA_CAPT_COND_PWM_FALLING | \ + TMRA_CAPT_COND_EVT | TMRA_CAPT_COND_TRIG_RISING | \ + TMRA_CAPT_COND_TRIG_FALLING) + +/** + * @} + */ + +/** + * @defgroup TMRA_Cmp_Value_Buf_Trans_Cond TMRA Compare Value Buffer Transmission Condition + * @{ + */ +#define TMRA_BUF_TRANS_COND_OVF_UDF_CLR (0x0U) /*!< This configuration value applies to non-triangular wave counting mode. + When counting overflow or underflow or counting register was cleared, + transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */ +#define TMRA_BUF_TRANS_COND_PEAK (TMRA_BCONR_BSE0) /*!< In triangle wave count mode, when count reached peak, + transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */ +#define TMRA_BUF_TRANS_COND_VALLEY (TMRA_BCONR_BSE1) /*!< In triangle wave count mode, when count reached valley, + transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,.... */ +#define TMRA_BUF_TRANS_COND_PEAK_VALLEY (TMRA_BCONR_BSE1 | \ + TMRA_BCONR_BSE0) /*!< In triangle wave count mode, when count reached peak or valley, + transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */ +/** + * @} + */ + +/** + * @defgroup TMRA_Filter_Clock_Divider TMRA Filter Clock Divider + * @{ + */ +#define TMRA_FILTER_CLK_DIV1 (0x0U) /*!< The filter clock is the clock of TimerA / 1 */ +#define TMRA_FILTER_CLK_DIV4 (0x1U) /*!< The filter clock is the clock of TimerA / 4 */ +#define TMRA_FILTER_CLK_DIV16 (0x2U) /*!< The filter clock is the clock of TimerA / 16 */ +#define TMRA_FILTER_CLK_DIV64 (0x3U) /*!< The filter clock is the clock of TimerA / 64 */ +/** + * @} + */ + +/** + * @defgroup TMRA_Counter_State TMRA Counter State + * @{ + */ +#define TMRA_CNT_STAT_START (0U) /*!< Counter start counting. */ +#define TMRA_CNT_STAT_STOP (1U) /*!< Counter stop counting. */ +#define TMRA_CNT_STAT_MATCH_CMP (2U) /*!< Counter value matches the compare value. */ +#define TMRA_CNT_STAT_MATCH_PERIOD (3U) /*!< Counter value matches the period value. */ +/** + * @} + */ + +/** + * @defgroup TMRA_PWM_Polarity TMRA PWM Polarity + * @{ + */ +#define TMRA_PWM_LOW (0x0U) /*!< PWM output low. */ +#define TMRA_PWM_HIGH (0x1U) /*!< PWM output high. */ +#define TMRA_PWM_HOLD (0x2U) /*!< PWM output holds the current polarity. */ +#define TMRA_PWM_INVT (0x3U) /*!< PWM output reverses the current polarity. */ +/** + * @} + */ + +/** + * @defgroup TMRA_PWM_Force_Polarity TMRA PWM Force Polarity + * @{ + */ +#define TMRA_PWM_FORCE_INVD (0x0U) /*!< Force polarity is invalid. */ +#define TMRA_PWM_FORCE_LOW (TMRA_PCONR_FORC_1) /*!< Force the PWM output low at the beginning of the next cycle. + The beginning of the next cycle: overflow position or underflow position + of sawtooth wave; valley position of triangle wave. */ +#define TMRA_PWM_FORCE_HIGH (TMRA_PCONR_FORC) /*!< Force the PWM output high at the beginning of the next cycle. + The beginning of the next cycle: overflow position or underflow position + of sawtooth wave; valley position of triangle wave. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Hardware_Start_Condition TMRA Hardware Start Condition + * @{ + */ +#define TMRA_START_COND_INVD (0x0U) /*!< The condition of start is INVALID. */ +#define TMRA_START_COND_TRIG_RISING (TMRA_HCONR_HSTA0) /*!< 1. Sync start is invalid: The condition is that a rising edge is sampled on TRIG of the current TMRA unit. + 2. Sync start is valid: The condition is that a rising edge is sampled on TRIG of the symmetric TMRA unit. */ +#define TMRA_START_COND_TRIG_FALLING (TMRA_HCONR_HSTA1) /*!< 1. Sync start is invalid: The condition is that a falling edge is sampled on TRIG of the current TMRA unit. + 2. Sync start is valid: The condition is that a falling edge is sampled on TRIG of the symmetric TMRA unit. */ +#define TMRA_START_COND_EVT (TMRA_HCONR_HSTA2) /*!< The condition is that the TMRA common trigger event has occurred. */ +#define TMRA_START_COND_ALL (TMRA_START_COND_TRIG_RISING | TMRA_START_COND_TRIG_FALLING | \ + TMRA_START_COND_EVT) +/** + * @} + */ + +/** + * @defgroup TMRA_Hardware_Stop_Condition TMRA Hardware Stop Condition + * @{ + */ +#define TMRA_STOP_COND_INVD (0x0U) /*!< The condition of stop is INVALID. */ +#define TMRA_STOP_COND_TRIG_RISING (TMRA_HCONR_HSTP0) /*!< The condition is that a rising edge is sampled on pin TRIG of the current TMRA unit. */ +#define TMRA_STOP_COND_TRIG_FALLING (TMRA_HCONR_HSTP1) /*!< The condition is that a falling edge is sampled on pin TRIG of the current TMRA unit. */ +#define TMRA_STOP_COND_EVT (TMRA_HCONR_HSTP2) /*!< The condition is that the TMRA common trigger event has occurred. */ +#define TMRA_STOP_COND_ALL (TMRA_STOP_COND_TRIG_RISING | TMRA_STOP_COND_TRIG_FALLING | \ + TMRA_STOP_COND_EVT) +/** + * @} + */ + +/** + * @defgroup TMRA_Hardware_Clear_Condition TMRA Hardware Clear Condition + * @note Symmetric units: unit 1 and 2; unit 3 and 4; ... ; unit 11 and 12. + * @{ + */ +#define TMRA_CLR_COND_INVD (0x0U) /*!< The condition of clear is INVALID. */ +#define TMRA_CLR_COND_TRIG_RISING (TMRA_HCONR_HCLE0) /*!< The condition is that a rising edge is sampled on TRIG of the current TMRA unit. */ +#define TMRA_CLR_COND_TRIG_FALLING (TMRA_HCONR_HCLE1) /*!< The condition is that a falling edge is sampled on TRIG of the current TMRA unit. */ +#define TMRA_CLR_COND_EVT (TMRA_HCONR_HCLE2) /*!< The condition is that the TMRA common trigger event has occurred. */ +#define TMRA_CLR_COND_SYM_TRIG_RISING (TMRA_HCONR_HCLE3) /*!< The condition is that a rising edge is sampled on TRIG of the symmetric unit. */ +#define TMRA_CLR_COND_SYM_TRIG_FALLING (TMRA_HCONR_HCLE4) /*!< The condition is that a falling edge is sampled on TRIG of the symmetric unit. */ +#define TMRA_CLR_COND_PWM3_RISING (TMRA_HCONR_HCLE5) /*!< The condition is that a rising edge is sampled on PWM3 of the current TMRA unit. */ +#define TMRA_CLR_COND_PWM3_FALLING (TMRA_HCONR_HCLE6) /*!< The condition is that a falling edge is sampled on PWM3 of the current TMRA unit. */ +#define TMRA_CLR_COND_ALL (TMRA_CLR_COND_TRIG_RISING | TMRA_CLR_COND_TRIG_FALLING | \ + TMRA_CLR_COND_EVT| TMRA_CLR_COND_SYM_TRIG_RISING | \ + TMRA_CLR_COND_SYM_TRIG_FALLING | TMRA_CLR_COND_PWM3_RISING| \ + TMRA_CLR_COND_PWM3_FALLING) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TMRA_Global_Functions + * @{ + */ +/* Base count(use software clock PCLK/HCLK) */ +int32_t TMRA_Init(CM_TMRA_TypeDef *TMRAx, const stc_tmra_init_t *pstcTmraInit); +int32_t TMRA_StructInit(stc_tmra_init_t *pstcTmraInit); +void TMRA_SetCountMode(CM_TMRA_TypeDef *TMRAx, uint8_t u8Mode); +void TMRA_SetCountDir(CM_TMRA_TypeDef *TMRAx, uint8_t u8Dir); +void TMRA_SetClockDiv(CM_TMRA_TypeDef *TMRAx, uint8_t u8Div); + +/* Hardware count */ +void TMRA_HWCountUpCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState); +void TMRA_HWCountDownCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState); +/* Set function mode */ +void TMRA_SetFunc(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Func); + +/* Ouput compare */ +int32_t TMRA_PWM_Init(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, const stc_tmra_pwm_init_t *pstcPwmInit); +int32_t TMRA_PWM_StructInit(stc_tmra_pwm_init_t *pstcPwmInit); +void TMRA_PWM_OutputCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState); +void TMRA_PWM_SetPolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint8_t u8CountState, uint16_t u16Polarity); +void TMRA_PWM_SetForcePolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Polarity); +/* Input capture */ +void TMRA_HWCaptureCondCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState); + +/* Trigger: hardware trigger to start/stop/clear the counter */ +void TMRA_HWStartCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState); +void TMRA_HWStopCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState); +void TMRA_HWClearCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState); + +/* Filter */ +void TMRA_SetFilterClockDiv(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, uint16_t u16Div); +void TMRA_FilterCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, en_functional_state_t enNewState); + +/* Global */ +void TMRA_DeInit(CM_TMRA_TypeDef *TMRAx); +/* Counting direction, period value, counter value, compare value */ +uint8_t TMRA_GetCountDir(const CM_TMRA_TypeDef *TMRAx); + +void TMRA_SetPeriodValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value); +uint32_t TMRA_GetPeriodValue(const CM_TMRA_TypeDef *TMRAx); +void TMRA_SetCountValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value); +uint32_t TMRA_GetCountValue(const CM_TMRA_TypeDef *TMRAx); +void TMRA_SetCompareValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint32_t u32Value); +uint32_t TMRA_GetCompareValue(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch); + +/* Sync start */ +void TMRA_SyncStartCmd(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState); + +void TMRA_SetCompareBufCond(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond); +void TMRA_CompareBufCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState); + +en_flag_status_t TMRA_GetStatus(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag); +void TMRA_ClearStatus(CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag); +void TMRA_IntCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32IntType, en_functional_state_t enNewState); +void TMRA_EventCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32EventType, en_functional_state_t enNewState); +void TMRA_Start(CM_TMRA_TypeDef *TMRAx); +void TMRA_Stop(CM_TMRA_TypeDef *TMRAx); + +/** + * @} + */ + +#endif /* LL_TMRA_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TMRA_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_trng.h b/mcu/lib/inc/hc32_ll_trng.h new file mode 100644 index 0000000..0dfca20 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_trng.h @@ -0,0 +1,130 @@ +/** + ******************************************************************************* + * @file hc32_ll_trng.h + * @brief This file contains all the functions prototypes of the TRNG driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-06-30 CDT Add TRNG_Cmd,TRNG_DeInit functions + API optimized for better random numbers: TRNG_GenerateRandom() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TRNG_H__ +#define __HC32_LL_TRNG_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TRNG + * @{ + */ + +#if (LL_TRNG_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup TRNG_Global_Macros TRNG Global Macros + * @{ + */ + +/** + * @defgroup TRNG_Reload_Init_Value TRNG Reload Initial Value + * @{ + */ +#define TRNG_RELOAD_INIT_VAL_ENABLE (TRNG_MR_LOAD) /* Enable reload new initial value. */ +#define TRNG_RELOAD_INIT_VAL_DISABLE (0x0U) /* Disable reload new initial value. */ +/** + * @} + */ + +/** + * @defgroup TRNG_Shift_Ctrl TRNG Shift Control + * @{ + */ +#define TRNG_SHIFT_CNT32 (0x3UL << TRNG_MR_CNT_POS) /* Shift 32 times when capturing random noise. */ +#define TRNG_SHIFT_CNT64 (0x4UL << TRNG_MR_CNT_POS) /* Shift 64 times when capturing random noise. */ +#define TRNG_SHIFT_CNT128 (0x5UL << TRNG_MR_CNT_POS) /* Shift 128 times when capturing random noise. */ +#define TRNG_SHIFT_CNT256 (0x6UL << TRNG_MR_CNT_POS) /* Shift 256 times when capturing random noise. */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TRNG_Global_Functions + * @{ + */ +int32_t TRNG_DeInit(void); +void TRNG_Init(uint32_t u32ShiftCount, uint32_t u32ReloadInitValueEn); +int32_t TRNG_GenerateRandom(uint32_t *pu32Random, uint32_t u32RandomLen); + +void TRNG_Start(void); +void TRNG_Cmd(en_functional_state_t enNewState); +int32_t TRNG_GetRandom(uint32_t *pu32Random, uint8_t u8RandomLen); +/** + * @} + */ + +#endif /* LL_TRNG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TRNG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_usart.h b/mcu/lib/inc/hc32_ll_usart.h new file mode 100644 index 0000000..8a9df29 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_usart.h @@ -0,0 +1,422 @@ +/** + ******************************************************************************* + * @file hc32_ll_usart.h + * @brief This file contains all the functions prototypes of the USART(Universal + * Synchronous/Asynchronous Receiver Transmitter) driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-06-30 CDT Modify typo + Change macro-definition: USART_DR_MPID -> USART_TDR_MPID + Modify USART_SetTransType parameter: u32Type -> u16Type + Modify USART_SC_ETU_CLK128/256 value + Modify return type of function USART_DeInit + 2023-09-30 CDT Remove u32StopBit param from stc_usart_smartcard_init_t structure + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_USART_H__ +#define __HC32_LL_USART_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_USART + * @{ + */ + +#if (LL_USART_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup USART_Global_Types USART Global Types + * @{ + */ + +/** + * @brief clock synchronization mode initialization structure definition + * @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock. + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Clock Source. + This parameter can be a value of @ref USART_Clock_Source */ + uint32_t u32ClockDiv; /*!< Clock division. + This parameter can be a value of @ref USART_Clock_Division. */ + uint32_t u32Baudrate; /*!< USART baudrate. + This parameter is valid when clock source is the internal clock. */ + uint32_t u32FirstBit; /*!< Significant bit. + This parameter can be a value of @ref USART_First_Bit */ + uint32_t u32HWFlowControl; /*!< Hardware flow control. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} stc_usart_clocksync_init_t; + +/** + * @brief UART multiple-processor initialization structure definition + * @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock. + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Clock Source. + This parameter can be a value of @ref USART_Clock_Source */ + uint32_t u32ClockDiv; /*!< Clock division. + This parameter can be a value of @ref USART_Clock_Division. */ + uint32_t u32CKOutput; /*!< USART_CK output selection. + This parameter can be a value of @ref USART_CK_Output_Selection. */ + uint32_t u32Baudrate; /*!< USART baudrate. + This parameter is valid when clock source is the internal clock. */ + uint32_t u32DataWidth; /*!< Data width. + This parameter can be a value of @ref USART_Data_Width_Bit */ + uint32_t u32StopBit; /*!< Stop Bits. + This parameter can be a value of @ref USART_Stop_Bit */ + uint32_t u32OverSampleBit; /*!< Oversampling Bits. + This parameter can be a value of @ref USART_Over_Sample_Bit */ + uint32_t u32FirstBit; /*!< Significant bit. + This parameter can be a value of @ref USART_First_Bit */ + uint32_t u32StartBitPolarity; /*!< Start Bit Detect Polarity. + This parameter can be a value of @ref USART_Start_Bit_Polarity */ + uint32_t u32HWFlowControl; /*!< Hardware flow control. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} stc_usart_multiprocessor_init_t; + +/** + * @brief UART mode initialization structure definition + * @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock. + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Clock Source. + This parameter can be a value of @ref USART_Clock_Source */ + uint32_t u32ClockDiv; /*!< Clock division. + This parameter can be a value of @ref USART_Clock_Division. */ + uint32_t u32CKOutput; /*!< USART_CK output selection. + This parameter can be a value of @ref USART_CK_Output_Selection. */ + uint32_t u32Baudrate; /*!< USART baudrate. + This parameter is valid when clock source is the internal clock. */ + uint32_t u32DataWidth; /*!< Data width. + This parameter can be a value of @ref USART_Data_Width_Bit */ + uint32_t u32StopBit; /*!< Stop Bits. + This parameter can be a value of @ref USART_Stop_Bit */ + uint32_t u32Parity; /*!< Parity format. + This parameter can be a value of @ref USART_Parity_Control */ + uint32_t u32OverSampleBit; /*!< Oversampling Bits. + This parameter can be a value of @ref USART_Over_Sample_Bit */ + uint32_t u32FirstBit; /*!< Significant bit. + This parameter can be a value of @ref USART_First_Bit */ + uint32_t u32StartBitPolarity; /*!< Start Bit Detect Polarity. + This parameter can be a value of @ref USART_Start_Bit_Polarity */ + uint32_t u32HWFlowControl; /*!< Hardware flow control. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} stc_usart_uart_init_t; + +/** + * @brief Smartcard mode initialization structure definition + */ +typedef struct { + uint32_t u32ClockDiv; /*!< Clock division. This parameter can be a value of @ref USART_Clock_Division. + @note This parameter is valid when clock source is the internal clock. */ + uint32_t u32CKOutput; /*!< USART_CK output selection. This parameter can be a value of @ref USART_CK_Output_Selection. + @note This parameter is valid when clock source is the internal clock. */ + uint32_t u32Baudrate; /*!< USART baudrate. + This parameter is calculated according with smartcard default ETU and clock. */ + uint32_t u32FirstBit; /*!< Significant bit. + This parameter can be a value of @ref USART_First_Bit */ +} stc_usart_smartcard_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup USART_Global_Macros USART Global Macros + * @{ + */ + +/** + * @defgroup USART_Flag USART Flag + * @{ + */ +#define USART_FLAG_RX_FULL (USART_SR_RXNE) /*!< Receive data register not empty flag */ +#define USART_FLAG_OVERRUN (USART_SR_ORE) /*!< Overrun error flag */ +#define USART_FLAG_TX_CPLT (USART_SR_TC) /*!< Transmission complete flag */ +#define USART_FLAG_TX_EMPTY (USART_SR_TXE) /*!< Transmit data register empty flag */ +#define USART_FLAG_FRAME_ERR (USART_SR_FE) /*!< Framing error flag */ +#define USART_FLAG_PARITY_ERR (USART_SR_PE) /*!< Parity error flag */ +#define USART_FLAG_MX_PROCESSOR (USART_SR_MPB) /*!< Receive processor ID flag */ +#define USART_FLAG_RX_TIMEOUT (USART_SR_RTOF) /*!< Receive timeout flag */ + +#define USART_FLAG_ALL (USART_FLAG_RX_FULL | USART_FLAG_FRAME_ERR | USART_FLAG_TX_EMPTY | \ + USART_FLAG_OVERRUN | USART_FLAG_PARITY_ERR | USART_FLAG_RX_TIMEOUT | \ + USART_FLAG_TX_CPLT | USART_FLAG_MX_PROCESSOR ) + +/** + * @} + */ + +/** + * @defgroup USART_Transmission_Type USART Transmission Type + * @{ + */ +#define USART_TRANS_DATA (0UL) +#define USART_TRANS_ID (USART_TDR_MPID) +/** + * @} + */ + +/** + * @defgroup USART_Function USART Function + * @{ + */ +#define USART_TX (USART_CR1_TE) /*!< USART TX function */ +#define USART_RX (USART_CR1_RE) /*!< USART RX function */ +#define USART_INT_RX (USART_CR1_RIE) /*!< USART receive data register not empty && receive error interrupt */ +#define USART_INT_TX_CPLT (USART_CR1_TCIE) /*!< USART transmission complete interrupt */ +#define USART_INT_TX_EMPTY (USART_CR1_TXEIE) /*!< USART transmit data register empty interrupt */ +#define USART_RX_TIMEOUT (USART_CR1_RTOE) /*!< USART RX timeout function */ +#define USART_INT_RX_TIMEOUT (USART_CR1_RTOIE) /*!< USART RX timeout interrupt */ + +#define USART_FUNC_ALL (USART_TX | USART_RX | USART_INT_RX | USART_INT_TX_CPLT | USART_RX_TIMEOUT | \ + USART_INT_RX_TIMEOUT | USART_INT_TX_EMPTY) + +/** + * @} + */ + +/** + * @defgroup USART_Parity_Control USART Parity Control + * @{ + */ +#define USART_PARITY_NONE (0UL) /*!< Parity control disabled */ +#define USART_PARITY_EVEN (USART_CR1_PCE) /*!< Parity control enabled and Even Parity is selected */ +#define USART_PARITY_ODD (USART_CR1_PCE | \ + USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** + * @defgroup USART_Data_Width_Bit USART Data Width Bit + * @{ + */ +#define USART_DATA_WIDTH_8BIT (0UL) /*!< 8 bits */ +#define USART_DATA_WIDTH_9BIT (USART_CR1_M) /*!< 9 bits */ +/** + * @} + */ + +/** + * @defgroup USART_Over_Sample_Bit USART Over Sample Bit + * @{ + */ +#define USART_OVER_SAMPLE_16BIT (0UL) /*!< Oversampling by 16 bits */ +#define USART_OVER_SAMPLE_8BIT (USART_CR1_OVER8) /*!< Oversampling by 8 bits */ +/** + * @} + */ + +/** + * @defgroup USART_First_Bit USART First Bit + * @{ + */ +#define USART_FIRST_BIT_LSB (0UL) /*!< LSB(Least Significant Bit) */ +#define USART_FIRST_BIT_MSB (USART_CR1_ML) /*!< MSB(Most Significant Bit) */ +/** + * @} + */ + +/** + * @defgroup USART_Start_Bit_Polarity USART Start Bit Polarity + * @{ + */ +#define USART_START_BIT_LOW (0UL) /*!< Detect RX pin low level */ +#define USART_START_BIT_FALLING (USART_CR1_SBS) /*!< Detect RX pin falling edge */ +/** + * @} + */ + +/** + * @defgroup USART_Clock_Source USART Clock Source + * @{ + */ +#define USART_CLK_SRC_INTERNCLK (0UL) /*!< Select internal clock source and don't output clock */ +#define USART_CLK_SRC_EXTCLK (USART_CR2_CLKC_1) /*!< Select external clock source. */ +/** + * @} + */ + +/** + * @defgroup USART_CK_Output_Selection USART_CK Output Selection + * @{ + */ +#define USART_CK_OUTPUT_DISABLE (0UL) /*!< Disable USART_CK output */ +#define USART_CK_OUTPUT_ENABLE (USART_CR2_CLKC_0) /*!< Enable USART_CK output. */ +/** + * @} + */ + +/** + * @defgroup USART_Stop_Bit USART Stop Bit + * @{ + */ +#define USART_STOPBIT_1BIT (0UL) /*!< 1 stop bit */ +#define USART_STOPBIT_2BIT (USART_CR2_STOP) /*!< 2 stop bit */ +/** + * @} + */ + +/** + * @defgroup USART_Hardware_Flow_Control USART Hardware Flow Control + * @{ + */ +#define USART_HW_FLOWCTRL_CTS (USART_CR3_CTSE) /*!< USART hardware flow control CTS mode */ +#define USART_HW_FLOWCTRL_RTS (USART_CR3_CTSE >> 1U) /*!< USART hardware flow control RTS mode */ +/** + * @} + */ + +/** + * @defgroup USART_Clock_Division USART Clock Division + * @{ + */ +#define USART_CLK_DIV1 (0UL) /*!< CLK */ +#define USART_CLK_DIV4 (1UL) /*!< CLK/4 */ +#define USART_CLK_DIV16 (2UL) /*!< CLK/16 */ +#define USART_CLK_DIV64 (3UL) /*!< CLK/64 */ +/** + * @} + */ + +/** + * @defgroup USART_Max_Timeout USART Max Timeout + * @{ + */ +#define USART_MAX_TIMEOUT (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup USART_Smartcard_ETU_Clock USART Smartcard ETU Clock + * @{ + */ +#define USART_SC_ETU_CLK32 (0UL << USART_CR3_BCN_POS) /*!< 1 etu = 32/f */ +#define USART_SC_ETU_CLK64 (1UL << USART_CR3_BCN_POS) /*!< 1 etu = 64/f */ +#define USART_SC_ETU_CLK128 (3UL << USART_CR3_BCN_POS) /*!< 1 etu = 128/f */ +#define USART_SC_ETU_CLK256 (5UL << USART_CR3_BCN_POS) /*!< 1 etu = 256/f */ +#define USART_SC_ETU_CLK372 (6UL << USART_CR3_BCN_POS) /*!< 1 etu = 372/f */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup USART_Global_Functions + * @{ + */ +int32_t USART_ClockSync_StructInit(stc_usart_clocksync_init_t *pstcClockSyncInit); +int32_t USART_ClockSync_Init(CM_USART_TypeDef *USARTx, + const stc_usart_clocksync_init_t *pstcClockSyncInit, float32_t *pf32Error); +int32_t USART_MultiProcessor_StructInit(stc_usart_multiprocessor_init_t *pstcMultiProcessorInit); +int32_t USART_MultiProcessor_Init(CM_USART_TypeDef *USARTx, + const stc_usart_multiprocessor_init_t *pstcMultiProcessorInit, float32_t *pf32Error); +int32_t USART_UART_StructInit(stc_usart_uart_init_t *pstcUartInit); +int32_t USART_UART_Init(CM_USART_TypeDef *USARTx, const stc_usart_uart_init_t *pstcUartInit, float32_t *pf32Error); + +int32_t USART_SmartCard_StructInit(stc_usart_smartcard_init_t *pstcSmartCardInit); +int32_t USART_SmartCard_Init(CM_USART_TypeDef *USARTx, + const stc_usart_smartcard_init_t *pstcSmartCardInit, float32_t *pf32Error); + +int32_t USART_DeInit(CM_USART_TypeDef *USARTx); +void USART_FuncCmd(CM_USART_TypeDef *USARTx, uint32_t u32Func, en_functional_state_t enNewState); +en_flag_status_t USART_GetStatus(const CM_USART_TypeDef *USARTx, uint32_t u32Flag); +void USART_ClearStatus(CM_USART_TypeDef *USARTx, uint32_t u32Flag); +void USART_SetParity(CM_USART_TypeDef *USARTx, uint32_t u32Parity); +void USART_SetFirstBit(CM_USART_TypeDef *USARTx, uint32_t u32FirstBit); +void USART_SetStopBit(CM_USART_TypeDef *USARTx, uint32_t u32StopBit); +void USART_SetDataWidth(CM_USART_TypeDef *USARTx, uint32_t u32DataWidth); +void USART_SetOverSampleBit(CM_USART_TypeDef *USARTx, uint32_t u32OverSampleBit); +void USART_SetStartBitPolarity(CM_USART_TypeDef *USARTx, uint32_t u32Polarity); +void USART_SetTransType(CM_USART_TypeDef *USARTx, uint16_t u16Type); +void USART_SetClockDiv(CM_USART_TypeDef *USARTx, uint32_t u32ClockDiv); +uint32_t USART_GetClockDiv(const CM_USART_TypeDef *USARTx); +void USART_SetClockSrc(CM_USART_TypeDef *USARTx, uint32_t u32ClockSrc); +uint32_t USART_GetClockSrc(const CM_USART_TypeDef *USARTx); +void USART_FilterCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState); +void USART_SilenceCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState); +void USART_SetHWFlowControl(CM_USART_TypeDef *USARTx, uint32_t u32HWFlowControl); +uint16_t USART_ReadData(const CM_USART_TypeDef *USARTx); +void USART_WriteData(CM_USART_TypeDef *USARTx, uint16_t u16Data); +void USART_WriteID(CM_USART_TypeDef *USARTx, uint16_t u16ID); + +int32_t USART_SetBaudrate(CM_USART_TypeDef *USARTx, uint32_t u32Baudrate, float32_t *pf32Error); + +void USART_SmartCard_SetEtuClock(CM_USART_TypeDef *USARTx, uint32_t u32EtuClock); + +int32_t USART_UART_Trans(CM_USART_TypeDef *USARTx, const void *pvBuf, uint32_t u32Len, uint32_t u32Timeout); +int32_t USART_UART_Receive(const CM_USART_TypeDef *USARTx, void *pvBuf, uint32_t u32Len, uint32_t u32Timeout); +int32_t USART_ClockSync_Trans(CM_USART_TypeDef *USARTx, const uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout); +int32_t USART_ClockSync_Receive(CM_USART_TypeDef *USARTx, uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout); +int32_t USART_ClockSync_TransReceive(CM_USART_TypeDef *USARTx, const uint8_t au8TxBuf[], uint8_t au8RxBuf[], + uint32_t u32Len, uint32_t u32Timeout); + +/** + * @} + */ + +#endif /* LL_USART_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_USART_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_usb.h b/mcu/lib/inc/hc32_ll_usb.h new file mode 100644 index 0000000..6306242 --- /dev/null +++ b/mcu/lib/inc/hc32_ll_usb.h @@ -0,0 +1,687 @@ +/** + ******************************************************************************* + * @file hc32_ll_usb.h + * @brief A detailed description is available at hardware registers. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Add USB core ID select function + Delete comment + 2023-06-30 CDT Modify typo + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_USB_H__ +#define __HC32_LL_USB_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_USB + * @{ + */ + +#if (LL_USB_ENABLE == DDL_ON) + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define USB_MAX_TX_FIFOS (12U) +#define USB_MAX_CH_NUM (USB_MAX_TX_FIFOS) +#define USB_MAX_EP_NUM (6U) + +/* USB Core ID define */ +#define USBFS_CORE_ID (0U) +#define USBHS_CORE_ID (1U) + +/* USB PHY type define for USBHS core */ +#define USBHS_PHY_EMBED (0U) +#define USBHS_PHY_EXT (1U) + +#define USB_MAX_EP0_SIZE (64U) +/* working mode of the USB core */ +#define DEVICE_MODE (0U) +#define HOST_MODE (1U) + +/* Macro definations for device mode*/ +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << USBFS_DSTS_ENUMSPD_POS) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << USBFS_DSTS_ENUMSPD_POS) +#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << USBFS_DSTS_ENUMSPD_POS) +#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << USBFS_DSTS_ENUMSPD_POS) + +/* EP type */ +#define EP_TYPE_CTRL (0U) +#define EP_TYPE_ISOC (1U) +#define EP_TYPE_BULK (2U) +#define EP_TYPE_INTR (3U) +#define EP_TYPE_MSK (3U) + +/* USB port speed */ +#define PRTSPD_FULL_SPEED (1U) +#define PRTSPD_LOW_SPEED (2U) + +/* PHY clock */ +#define HCFG_30_60_MHZ (0U) +#define HCFG_48_MHZ (1U) +#define HCFG_6_MHZ (2U) + +#define USB_EP_TX_DIS (0x0000U) +#define USB_EP_TX_STALL (0x0010U) +#define USB_EP_TX_NAK (0x0020U) +#define USB_EP_TX_VALID (0x0030U) + +#define USB_EP_RX_DIS (0x0000U) +#define USB_EP_RX_STALL (0x1000U) +#define USB_EP_RX_NAK (0x2000U) +#define USB_EP_RX_VALID (0x3000U) + +#define USB_OK (0U) +#define USB_ERROR (1U) + +#define USB_FRAME_INTERVAL_80 (0UL << USBFS_DCFG_PFIVL_POS) +#define USB_FRAME_INTERVAL_85 (1UL << USBFS_DCFG_PFIVL_POS) +#define USB_FRAME_INTERVAL_90 (2UL << USBFS_DCFG_PFIVL_POS) +#define USB_FRAME_INTERVAL_95 (3UL << USBFS_DCFG_PFIVL_POS) + +#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ + (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) +#define LOBYTE(x) ((uint8_t)((uint16_t)(x) & 0x00FFU)) +#define HIBYTE(x) ((uint8_t)(((uint16_t)(x) & 0xFF00U) >>8U)) + +#ifdef USB_INTERNAL_DMA_ENABLED +#define __USB_ALIGN_END +#if defined (__GNUC__) /* GNU Compiler */ +#define __USB_ALIGN_BEGIN __attribute__ ((aligned (4))) +#elif defined (__CC_ARM) /* ARM Compiler */ +#define __USB_ALIGN_BEGIN __align(4) +#elif defined (__ICCARM__) /* IAR Compiler */ +#define __USB_ALIGN_BEGIN +#elif defined (__TASKING__) /* TASKING Compiler */ +#define __USB_ALIGN_BEGIN __align(4) +#endif +#else +#define __USB_ALIGN_BEGIN +#define __USB_ALIGN_END +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +typedef struct { + __IO uint32_t GVBUSCFG; /* VBUS Configuration Register 000h */ + uint32_t Reserved04; /* Reserved 004h */ + __IO uint32_t GAHBCFG; /* AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /* USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /* Reset Register 010h */ + __IO uint32_t GINTSTS; /* Interrupt Register 014h */ + __IO uint32_t GINTMSK; /* Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */ + __IO uint32_t HNPTXFSIZ; /* HNPTXFSIZ: Host Non-Periodic Transmit FIFO Size Register 028h + DIEPTXF0: Device IN EP0 Transmit FIFO size register 028h */ + __IO uint32_t HNPTXSTS; /* Host Non Periodic Transmit FIFO/Queue Status Register 02Ch */ + uint32_t Reserved30[3]; /* Reserved 030h-038h */ + __IO uint32_t CID; /* User ID Register 03Ch */ + uint32_t Reserved40[5]; /* Reserved 040h-050h */ + __IO uint32_t GLPMCFG; /* Low Power Mode Configuration Register 054h */ + uint32_t Reserved58[42]; /* Reserved 058h-0FCh */ + __IO uint32_t HPTXFSIZ; /* Host Periodic Transmit FIFO Size Register 100h */ + __IO uint32_t DIEPTXF[USB_MAX_TX_FIFOS]; /* Device Periodic Transmit FIFO Size Register */ +} USB_CORE_GREGS; + +typedef struct { + __IO uint32_t DCFG; /* Device Configuration Register 800h */ + __IO uint32_t DCTL; /* Device Control Register 804h */ + __IO uint32_t DSTS; /* Device Status Register (RO) 808h */ + uint32_t Reserved0C; /* Reserved 80Ch */ + __IO uint32_t DIEPMSK; /* Device IN EP Common Interrupt Mask Register 810h */ + __IO uint32_t DOEPMSK; /* Device OUT EP Common Interrupt Mask Register 814h */ + __IO uint32_t DAINT; /* Device All EP Interrupt Register 818h */ + __IO uint32_t DAINTMSK; /* Device All EP Interrupt Mask Register 81Ch */ + uint32_t Reserved20[4]; /* Reserved 820h-82Ch */ + __IO uint32_t DTHRCTL; /* Device Threshold Control Register 830h */ + __IO uint32_t DIEPEMPMSK; /* Device IN EP FIFO Empty Interrupt Mask Register 834h */ + __IO uint32_t DEACHINT; /* Device Each EP Interrupt Register 838h */ + __IO uint32_t DEACHINTMSK; /* Device Each EP Interrupt Mask Register 83Ch */ + uint32_t Reserved40; /* Reserved 840h */ + __IO uint32_t DIEPEACHMSK1; /* Device IN EP1 Interrupt Mask Register 844h */ + uint32_t Reserved48[15]; /* Reserved 848-880h */ + __IO uint32_t DOEPEACHMSK1; /* Device OUT EP1 Interrupt Mask Register 884h */ +} USB_CORE_DREGS; + +typedef struct { + __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /* IN Endpoint Tx FIFO Status 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ +} USB_CORE_INEPREGS; + +typedef struct { + __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_CORE_OUTEPREGS; + +typedef struct { + __IO uint32_t HCFG; /* Host Configuration Register 400h*/ + __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ + __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ + uint32_t Reserved40C; /* Reserved 40Ch*/ + __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ + __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ + __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ +} USB_CORE_HREGS; + +typedef struct { + __IO uint32_t HCCHAR; + __IO uint32_t HCSPLT; + __IO uint32_t HCINT; + __IO uint32_t HCINTMSK; + __IO uint32_t HCTSIZ; + __IO uint32_t HCDMA; + uint32_t Reserved[2]; +} USB_CORE_HC_REGS; + +typedef struct { /* 000h */ + USB_CORE_GREGS *GREGS; + USB_CORE_DREGS *DREGS; + USB_CORE_HREGS *HREGS; + USB_CORE_INEPREGS *INEP_REGS[USB_MAX_TX_FIFOS]; + USB_CORE_OUTEPREGS *OUTEP_REGS[USB_MAX_TX_FIFOS]; + USB_CORE_HC_REGS *HC_REGS[USB_MAX_TX_FIFOS]; + __IO uint32_t *HPRT; + __IO uint32_t *DFIFO[USB_MAX_TX_FIFOS]; + __IO uint32_t *GCCTL; +} LL_USB_TypeDef; + +typedef struct { + uint8_t host_chnum; + uint8_t dev_epnum; + uint8_t dmaen; + uint8_t low_power; + uint8_t phy_type; + uint8_t core_type; +} USB_CORE_BASIC_CFGS; + +typedef struct { + uint8_t dev_addr; + uint8_t ep_idx; + uint8_t is_epin; + uint8_t ch_speed; + uint8_t do_ping; + uint8_t ep_type; + uint16_t max_packet; + uint8_t pid_type; + uint8_t in_toggle; + uint8_t out_toggle; + /* transaction level variables*/ + uint32_t dma_addr; + uint32_t xfer_len; + uint32_t xfer_count; + uint8_t *xfer_buff; +} USB_HOST_CH; + +typedef struct { + uint8_t epidx; + uint8_t ep_dir; + uint8_t trans_type; + uint8_t ep_stall; + uint8_t data_pid_start; + uint8_t datax_pid; + uint16_t tx_fifo_num; + uint32_t maxpacket; + /* Transfer level variables */ + uint32_t rem_data_len; + uint32_t total_data_len; + uint32_t ctl_data_len; + /* transaction level variables*/ + uint32_t dma_addr; + uint32_t xfer_len; + uint32_t xfer_count; + uint8_t *xfer_buff; +} USB_DEV_EP; + +typedef struct { + uint8_t u8CoreID; /* USBFS_CORE_ID or USBHS_CORE_ID */ +} stc_usb_port_identify; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @addtogroup USB_Global_Functions + * @{ + */ + +/** + * @brief get the current mode of the usb core from the corresponding register + * @param [in] USBx usb instance + * @retval current mode 1: host mode 0: device mode + */ +__STATIC_INLINE uint8_t usb_getcurmod(LL_USB_TypeDef *USBx) +{ + if (0UL != READ_REG32_BIT(USBx->GREGS->GINTSTS, USBFS_GINTSTS_CMOD)) { + return 1U; + } else { + return 0U; + } +} + +/** + * @brief Initializes the normal interrupts + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_normalinten(LL_USB_TypeDef *USBx) +{ + WRITE_REG32(USBx->GREGS->GINTSTS, 0xBFFFFFFFUL); + WRITE_REG32(USBx->GREGS->GINTMSK, USBFS_GINTMSK_WKUIM | USBFS_GINTMSK_USBSUSPM); +} + +/** + * @brief clear all the pending device interrupt bits and mask the IN and OUT + * endpoint interrupts. + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_clrandmskepint(LL_USB_TypeDef *USBx) +{ + WRITE_REG32(USBx->DREGS->DIEPMSK, 0UL); + WRITE_REG32(USBx->DREGS->DOEPMSK, 0UL); + WRITE_REG32(USBx->DREGS->DAINT, 0xFFFFFFFFUL); + WRITE_REG32(USBx->DREGS->DAINTMSK, 0UL); +} + +/** + * @brief generate a device connect signal to the USB host + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_coreconn(LL_USB_TypeDef *USBx) +{ + CLR_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_SDIS); +} + +/** + * @brief test of mode processing + * @param [in] USBx usb instance + * @param [in] reg Register write + * @retval None + */ +__STATIC_INLINE void usb_runtestmode(LL_USB_TypeDef *USBx, uint32_t reg) +{ + WRITE_REG32(USBx->DREGS->DCTL, reg); +} + +/** + * @brief Enables the controller's Global interrupts in the AHB Configuration + * registers. + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_ginten(LL_USB_TypeDef *USBx) +{ + SET_REG32_BIT(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_GINTMSK); +} + +/** + * @brief Disable the controller's Global interrupt in the AHB Configuration + * register. + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_gintdis(LL_USB_TypeDef *USBx) +{ + CLR_REG32_BIT(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_GINTMSK); +} + +/** + * @brief Get the Core Interrupt bits from the interrupt register not including + * the bits that are masked. + * @param [in] USBx usb instance + * @retval status[32bits] + */ +__STATIC_INLINE uint32_t usb_getcoreintr(LL_USB_TypeDef *USBx) +{ + uint32_t v; + v = READ_REG32(USBx->GREGS->GINTSTS); + v &= READ_REG32(USBx->GREGS->GINTMSK); + return v; +} + +/** + * @brief Get the out endpoint interrupt bits from the all endpoint interrupt + * register not including the bits masked. + * @param [in] USBx usb instance + * @retval The status that shows which OUT EP have interrupted. + */ +__STATIC_INLINE uint32_t usb_getalloepintr(LL_USB_TypeDef *USBx) +{ + uint32_t v; + v = READ_REG32(USBx->DREGS->DAINT); + v &= READ_REG32(USBx->DREGS->DAINTMSK); + return ((v & 0xFFFF0000UL) >> 16U); +} + +/** + * @brief Get the Device OUT EP Interrupt register(DOEPINT) not including the + * interrupt bits that are masked. + * @param [in] USBx usb instance + * @param [in] epnum end point index + * @retval all the interrupt bits on DOEPINTn while n = epnum + */ +__STATIC_INLINE uint32_t usb_getoepintbit(LL_USB_TypeDef *USBx, uint8_t epnum) +{ + uint32_t v; + v = READ_REG32(USBx->OUTEP_REGS[epnum]->DOEPINT); + v &= READ_REG32(USBx->DREGS->DOEPMSK); + return v; +} + +/** + * @brief Get the IN endpoint interrupt bits from the all endpoint interrupt + * register not including the bits masked. + * @param [in] USBx usb instance + * @retval The status that shows which IN EP have interrupted. + */ +__STATIC_INLINE uint32_t usb_getalliepintr(LL_USB_TypeDef *USBx) +{ + uint32_t v; + v = READ_REG32(USBx->DREGS->DAINT); + v &= READ_REG32(USBx->DREGS->DAINTMSK); + return (v & 0xFFFFUL); +} + +/** + * @brief Set the device a new address. + * @param [in] USBx usb instance + * @param [in] address device address which will be set to the corresponding register. + * @retval None + */ +__STATIC_INLINE void usb_devaddrset(LL_USB_TypeDef *USBx, uint8_t address) +{ + MODIFY_REG32(USBx->DREGS->DCFG, USBFS_DCFG_DAD, (uint32_t)address << USBFS_DCFG_DAD_POS); +} + +/** + * @brief Select the USB PHY. + * @param [in] USBx usb instance + * @param [in] PhyType USB phy, 1 select external ULPI PHY, 0 select internal FS PHY + * @retval None + */ +__STATIC_INLINE void usb_PhySelect(LL_USB_TypeDef *USBx, uint8_t PhyType) +{ + if (USBHS_PHY_EXT == PhyType) { + CLR_REG32_BIT(USBx->GREGS->GUSBCFG, USBFS_GUSBCFG_PHYSEL); + //SET_REG32_BIT(USBx->GREGS->GUSBCFG, 1UL<<4); + } else { + SET_REG32_BIT(USBx->GREGS->GUSBCFG, USBFS_GUSBCFG_PHYSEL); + } +} + +/** + * @brief Select the USB device PHY. + * @param [in] USBx usb instance + * @param [in] PhyType USB phy, 1 select external ULPI PHY, 0 select internal FS PHY + * @retval None + */ +__STATIC_INLINE void usb_DevPhySelect(LL_USB_TypeDef *USBx, uint8_t PhyType) +{ + if (1U == PhyType) { + CLR_REG32_BIT(USBx->DREGS->DCFG, USBFS_DCFG_DSPD); + } else { + SET_REG32_BIT(USBx->DREGS->DCFG, USBFS_DCFG_DSPD); + } + +} + +/** + * @brief USB DMA function command. + * @param [in] USBx usb instance + * @param [in] DmaCmd USB DMA command status, 0 disable, 1 enable + * @retval None + */ +__STATIC_INLINE void usb_DmaCmd(LL_USB_TypeDef *USBx, uint8_t DmaCmd) +{ + MODIFY_REG32(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_DMAEN, (uint32_t)DmaCmd << USBFS_GAHBCFG_DMAEN_POS); +} + +/** + * @brief USB burst length config. + * @param [in] USBx usb instance + * @param [in] len Burst length + * @retval None + */ +__STATIC_INLINE void usb_BurstLenConfig(LL_USB_TypeDef *USBx, uint8_t len) +{ + MODIFY_REG32(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_HBSTLEN, (uint32_t)len << USBFS_GAHBCFG_HBSTLEN_POS); +} + +/** + * @brief USB frame interval config + * @param [in] USBx usb instance + * @param [in] interval Frame interval + * @retval None + */ +__STATIC_INLINE void usb_FrameIntervalConfig(LL_USB_TypeDef *USBx, uint8_t interval) +{ + MODIFY_REG32(USBx->DREGS->DCFG, USBFS_DCFG_PFIVL, interval); +} + +#ifdef USE_HOST_MODE +/** + * @brief Read the register HPRT and reset the following bits. + * @param [in] USBx usb instance + * @retval value of HPRT + */ +//#define USBFS_HPRT_PRTOVRCURRCHNG (0x00000020UL) +__STATIC_INLINE uint32_t usb_rdhprt(LL_USB_TypeDef *USBx) +{ + return (READ_REG32(*USBx->HPRT) & ~(USBFS_HPRT_PENA | USBFS_HPRT_PCDET | USBFS_HPRT_PENCHNG)); +} + +/** + * @brief Issues a ping token + * @param [in] USBx usb instance + * @param [in] hc_num the host channel index + * @retval None + */ +//#define USBFS_HCTSIZ_DOPNG (0x80000000UL) +__STATIC_INLINE void usb_pingtokenissue(LL_USB_TypeDef *USBx, uint8_t hc_num) +{ + WRITE_REG32(USBx->HC_REGS[hc_num]->HCTSIZ, 1UL << USBFS_HCTSIZ_PKTCNT_POS); + MODIFY_REG32(USBx->HC_REGS[hc_num]->HCCHAR, USBFS_HCCHAR_CHENA | USBFS_HCCHAR_CHDIS, USBFS_HCCHAR_CHENA); +} + +/** + * @brief This function returns the frame number for sof packet + * @param [in] USBx usb instance + * @retval Frame number + */ +__STATIC_INLINE uint32_t usb_ifevenframe(LL_USB_TypeDef *USBx) +{ + return ((READ_REG32(USBx->HREGS->HFNUM) + 1UL) & 0x1UL); +} + +/** + * @brief Initializes the FSLSPClkSel field of the HCFG register on the PHY type + * @param [in] USBx usb instance + * @param [in] freq clock frequency + * @retval None + */ +__STATIC_INLINE void usb_fslspclkselset(LL_USB_TypeDef *USBx, uint8_t freq) +{ + MODIFY_REG32(USBx->HREGS->HCFG, USBFS_HCFG_FSLSPCS, (uint32_t)freq << USBFS_HCFG_FSLSPCS_POS); +} + +/** + * @brief suspend the port + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_prtsusp(LL_USB_TypeDef *USBx) +{ + uint32_t u32hprt; + u32hprt = usb_rdhprt(USBx); + u32hprt |= USBFS_HPRT_PSUSP; + u32hprt &= ~USBFS_HPRT_PRES; + WRITE_REG32(*USBx->HPRT, u32hprt); +} + +/** + * @brief control the enumeration speed of the core, this function make sure that + * the maximum speed supperted by the connected device. + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_enumspeed(LL_USB_TypeDef *USBx) +{ + CLR_REG32_BIT(USBx->HREGS->HCFG, USBFS_HCFG_FSLSS); +} + +/** + * @brief set the TXFIFO and depth for non-periodic and periodic and RXFIFO size + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_sethostfifo(LL_USB_TypeDef *USBx, uint8_t u8CoreID) +{ + if (USBFS_CORE_ID == u8CoreID) { +#ifdef USB_FS_MODE + /* USBFS Core*/ + WRITE_REG32(USBx->GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); /* set the RxFIFO Depth */ + /* non-periodic transmit RAM start address, set the non-periodic TxFIFO depth */ + WRITE_REG32(USBx->GREGS->HNPTXFSIZ, + (RX_FIFO_FS_SIZE << USBFS_HNPTXFSIZ_NPTXFSA_POS) + | (TXH_NP_FS_FIFOSIZ << USBFS_HNPTXFSIZ_NPTXFD_POS)); + /* set the host periodic TxFIFO start address, set the host periodic TxFIFO depth */ + WRITE_REG32(USBx->GREGS->HPTXFSIZ, + ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ) << USBFS_HPTXFSIZ_PTXSA_POS) + | (TXH_P_FS_FIFOSIZ << USBFS_HPTXFSIZ_PTXFD_POS)); +#endif + } else { +#ifdef USB_HS_MODE + /* USBHS Core */ + WRITE_REG32(USBx->GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); + WRITE_REG32(USBx->GREGS->HNPTXFSIZ, + (RX_FIFO_HS_SIZE << USBFS_HNPTXFSIZ_NPTXFSA_POS) + | (TXH_NP_HS_FIFOSIZ << USBFS_HNPTXFSIZ_NPTXFD_POS)); + WRITE_REG32(USBx->GREGS->HPTXFSIZ, + ((RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ) << USBFS_HPTXFSIZ_PTXSA_POS) + | (TXH_P_HS_FIFOSIZ << USBFS_HPTXFSIZ_PTXFD_POS)); +#endif + } +} + +/** + * @brief reset the channel whose channel number is ch_idx + * @param [in] USBx usb instance + * @param [in] ch_idx channel number + * @retval None + */ +__STATIC_INLINE void usb_chrst(LL_USB_TypeDef *USBx, uint8_t ch_idx) +{ + MODIFY_REG32(USBx->HC_REGS[ch_idx]->HCCHAR, + USBFS_HCCHAR_CHENA | USBFS_HCCHAR_CHDIS | USBFS_HCCHAR_EPDIR, + USBFS_HCCHAR_CHDIS); +} +#endif /* end of USE_HOST_MODE */ + +extern void usb_initusbcore(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs); +extern void usb_setregaddr(LL_USB_TypeDef *USBx, stc_usb_port_identify *pstcPortIdentify, USB_CORE_BASIC_CFGS *basic_cfgs); +extern void usb_rdpkt(LL_USB_TypeDef *USBx, uint8_t *dest, uint16_t len); +extern void usb_wrpkt(LL_USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t u8DmaEn); +extern void usb_txfifoflush(LL_USB_TypeDef *USBx, uint32_t num); +extern void usb_rxfifoflush(LL_USB_TypeDef *USBx); +extern void usb_modeset(LL_USB_TypeDef *USBx, uint8_t mode); +extern void usb_coresoftrst(LL_USB_TypeDef *USBx); + +#ifdef USE_HOST_MODE +extern void usb_hostmodeinit(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs); +extern void usb_hostinten(LL_USB_TypeDef *USBx, uint8_t u8DmaEn); +extern uint8_t usb_inithch(LL_USB_TypeDef *USBx, uint8_t hc_num, USB_HOST_CH *pCh, uint8_t u8DmaEn); +extern void usb_hoststop(LL_USB_TypeDef *USBx, uint8_t u8ChNum); +extern void usb_hchstop(LL_USB_TypeDef *USBx, uint8_t hc_num); +extern uint8_t usb_hchtransbegin(LL_USB_TypeDef *USBx, uint8_t hc_num, USB_HOST_CH *pCh, uint8_t u8DmaEn); +extern void usb_hprtrst(LL_USB_TypeDef *USBx); +extern void usb_vbusctrl(LL_USB_TypeDef *USBx, uint8_t u8State); +#endif + +#ifdef USE_DEVICE_MODE +extern void usb_devmodeinit(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs); +extern void usb_devinten(LL_USB_TypeDef *USBx, uint8_t u8DmaEn); +extern void usb_ep0activate(LL_USB_TypeDef *USBx); +extern void usb_epactive(LL_USB_TypeDef *USBx, USB_DEV_EP *ep); +extern void usb_epdeactive(LL_USB_TypeDef *USBx, USB_DEV_EP *ep); +extern void usb_epntransbegin(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint8_t u8DmaEn); +extern void usb_ep0transbegin(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint8_t u8DmaEn); +extern void usb_setepstall(LL_USB_TypeDef *USBx, USB_DEV_EP *ep); +extern void usb_clearepstall(LL_USB_TypeDef *USBx, USB_DEV_EP *ep); +extern void usb_ep0revcfg(LL_USB_TypeDef *USBx, uint8_t u8DmaEn, uint8_t *u8RevBuf); +extern void usb_remotewakeupen(LL_USB_TypeDef *USBx); +extern void usb_epstatusset(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint32_t Status); +extern uint32_t usb_epstatusget(LL_USB_TypeDef *USBx, USB_DEV_EP *ep); +extern void usb_devepdis(LL_USB_TypeDef *USBx, uint8_t u8EpNum); +extern void usb_ctrldevconnect(LL_USB_TypeDef *USBx, uint8_t link); +#endif + +/** + * @} + */ + +#endif /* LL_USB_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_USB_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_utility.h b/mcu/lib/inc/hc32_ll_utility.h new file mode 100644 index 0000000..efc9cfe --- /dev/null +++ b/mcu/lib/inc/hc32_ll_utility.h @@ -0,0 +1,131 @@ +/** + ******************************************************************************* + * @file hc32_ll_utility.h + * @brief This file contains all the functions prototypes of the DDL utility. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_UTILITY_H__ +#define __HC32_LL_UTILITY_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_UTILITY + * @{ + */ + +#if (LL_UTILITY_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup UTILITY_Global_Functions + * @{ + */ + +/* Imprecise delay */ +void DDL_DelayMS(uint32_t u32Count); +void DDL_DelayUS(uint32_t u32Count); + +/* Systick functions */ +int32_t SysTick_Init(uint32_t u32Freq); +void SysTick_Delay(uint32_t u32Delay); +void SysTick_IncTick(void); +uint32_t SysTick_GetTick(void); +void SysTick_Suspend(void); +void SysTick_Resume(void); + +#if (LL_PRINT_ENABLE == DDL_ON) +int32_t LL_PrintfInit(void *vpDevice, uint32_t u32Param, int32_t (*pfnPreinit)(void *vpDevice, uint32_t u32Param)); +#endif + +/* You can add your own assert functions by implement the function DDL_AssertHandler + definition follow the function DDL_AssertHandler declaration */ +#ifdef __DEBUG +#define DDL_ASSERT(x) \ +do { \ + ((x) ? (void)0 : DDL_AssertHandler(__FILE__, __LINE__)); \ +} while (0) +/* Exported function */ +void DDL_AssertHandler(const char *file, int line); +#else +#define DDL_ASSERT(x) ((void)0U) +#endif /* __DEBUG */ + +#if (LL_PRINT_ENABLE == DDL_ON) +#include +__WEAKDEF int32_t DDL_ConsoleOutputChar(char cData); + +#define DDL_PrintfInit (void)LL_PrintfInit +#define DDL_Printf (void)printf +#else +#define DDL_PrintfInit(vpDevice, u32Param, pfnPreinit) +#define DDL_Printf(...) +#endif + +/** + * @} + */ + +#endif /* LL_UTILITY_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_UTILITY_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32_ll_wdt.h b/mcu/lib/inc/hc32_ll_wdt.h new file mode 100644 index 0000000..0bb130d --- /dev/null +++ b/mcu/lib/inc/hc32_ll_wdt.h @@ -0,0 +1,227 @@ +/** + ******************************************************************************* + * @file hc32_ll_wdt.h + * @brief This file contains all the functions prototypes of the WDT driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_WDT_H__ +#define __HC32_LL_WDT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_WDT + * @{ + */ + +#if (LL_WDT_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup WDT_Global_Types WDT Global Types + * @{ + */ + +/** + * @brief WDT Init structure definition + */ +typedef struct { + uint32_t u32CountPeriod; /*!< Specifies the counting period of WDT. + This parameter can be a value of @ref WDT_Count_Period */ + uint32_t u32ClockDiv; /*!< Specifies the clock division factor of WDT. + This parameter can be a value of @ref WDT_Clock_Division */ + uint32_t u32RefreshRange; /*!< Specifies the allow refresh range of WDT. + This parameter can be a value of @ref WDT_Refresh_Range */ + uint32_t u32LPMCount; /*!< Specifies the count state in Low Power Mode (Sleep Mode). + This parameter can be a value of @ref WDT_LPM_Count */ + uint32_t u32ExceptionType; /*!< Specifies the type of exception response for WDT. + This parameter can be a value of @ref WDT_Exception_Type */ +} stc_wdt_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup WDT_Global_Macros WDT Global Macros + * @{ + */ + +/** + * @defgroup WDT_Count_Period WDT Count Period + * @{ + */ +#define WDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */ +#define WDT_CNT_PERIOD4096 (WDT_CR_PERI_0) /*!< 4096 clock cycle */ +#define WDT_CNT_PERIOD16384 (WDT_CR_PERI_1) /*!< 16384 clock cycle */ +#define WDT_CNT_PERIOD65536 (WDT_CR_PERI) /*!< 65536 clock cycle */ +/** + * @} + */ + +/** + * @defgroup WDT_Clock_Division WDT Clock Division + * @{ + */ +#define WDT_CLK_DIV4 (0x02UL << WDT_CR_CKS_POS) /*!< PLCKx/4 */ +#define WDT_CLK_DIV64 (0x06UL << WDT_CR_CKS_POS) /*!< PLCKx/64 */ +#define WDT_CLK_DIV128 (0x07UL << WDT_CR_CKS_POS) /*!< PLCKx/128 */ +#define WDT_CLK_DIV256 (0x08UL << WDT_CR_CKS_POS) /*!< PLCKx/256 */ +#define WDT_CLK_DIV512 (0x09UL << WDT_CR_CKS_POS) /*!< PLCKx/512 */ +#define WDT_CLK_DIV1024 (0x0AUL << WDT_CR_CKS_POS) /*!< PLCKx/1024 */ +#define WDT_CLK_DIV2048 (0x0BUL << WDT_CR_CKS_POS) /*!< PLCKx/2048 */ +#define WDT_CLK_DIV8192 (0x0DUL << WDT_CR_CKS_POS) /*!< PLCKx/8192 */ +/** + * @} + */ + +/** + * @defgroup WDT_Refresh_Range WDT Refresh Range + * @{ + */ +#define WDT_RANGE_0TO25PCT (0x01UL << WDT_CR_WDPT_POS) /*!< 0%~25% */ +#define WDT_RANGE_25TO50PCT (0x02UL << WDT_CR_WDPT_POS) /*!< 25%~50% */ +#define WDT_RANGE_0TO50PCT (0x03UL << WDT_CR_WDPT_POS) /*!< 0%~50% */ +#define WDT_RANGE_50TO75PCT (0x04UL << WDT_CR_WDPT_POS) /*!< 50%~75% */ +#define WDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << WDT_CR_WDPT_POS) /*!< 0%~25% & 50%~75% */ +#define WDT_RANGE_25TO75PCT (0x06UL << WDT_CR_WDPT_POS) /*!< 25%~75% */ +#define WDT_RANGE_0TO75PCT (0x07UL << WDT_CR_WDPT_POS) /*!< 0%~75% */ +#define WDT_RANGE_75TO100PCT (0x08UL << WDT_CR_WDPT_POS) /*!< 75%~100% */ +#define WDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << WDT_CR_WDPT_POS) /*!< 0%~25% & 75%~100% */ +#define WDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << WDT_CR_WDPT_POS) /*!< 25%~50% & 75%~100% */ +#define WDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << WDT_CR_WDPT_POS) /*!< 0%~50% & 75%~100% */ +#define WDT_RANGE_50TO100PCT (0x0CUL << WDT_CR_WDPT_POS) /*!< 50%~100% */ +#define WDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << WDT_CR_WDPT_POS) /*!< 0%~25% & 50%~100% */ +#define WDT_RANGE_25TO100PCT (0x0EUL << WDT_CR_WDPT_POS) /*!< 25%~100% */ +#define WDT_RANGE_0TO100PCT (0x0FUL << WDT_CR_WDPT_POS) /*!< 0%~100% */ +/** + * @} + */ + +/** + * @defgroup WDT_LPM_Count WDT Low Power Mode Count + * @brief Counting control of WDT in sleep mode. + * @{ + */ +#define WDT_LPM_CNT_CONTINUE (0UL) /*!< Continue counting in sleep mode */ +#define WDT_LPM_CNT_STOP (WDT_CR_SLPOFF) /*!< Stop counting in sleep mode */ +/** + * @} + */ + +/** + * @defgroup WDT_Exception_Type WDT Exception Type + * @brief Specifies the exception response when a refresh error or count overflow occurs. + * @{ + */ +#define WDT_EXP_TYPE_INT (0UL) /*!< WDT trigger interrupt */ +#define WDT_EXP_TYPE_RST (WDT_CR_ITS) /*!< WDT trigger reset */ +/** + * @} + */ + +/** + * @defgroup WDT_Flag WDT Flag + * @{ + */ +#define WDT_FLAG_UDF (WDT_SR_UDF) /*!< Count underflow flag */ +#define WDT_FLAG_REFRESH (WDT_SR_REF) /*!< Refresh error flag */ +#define WDT_FLAG_ALL (WDT_SR_UDF | WDT_SR_REF) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup WDT_Global_Functions + * @{ + */ + +/** + * @brief Get WDT count value. + * @param None + * @retval uint16_t Count value + */ +__STATIC_INLINE uint16_t WDT_GetCountValue(void) +{ + return (uint16_t)(READ_REG32(CM_WDT->SR) & WDT_SR_CNT); +} + +/* Initialization and configuration functions */ +int32_t WDT_Init(const stc_wdt_init_t *pstcWdtInit); +void WDT_FeedDog(void); +uint16_t WDT_GetCountValue(void); + +/* Flags management functions */ +en_flag_status_t WDT_GetStatus(uint32_t u32Flag); +int32_t WDT_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_WDT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_WDT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32f460_ll_interrupts_share.h b/mcu/lib/inc/hc32f460_ll_interrupts_share.h new file mode 100644 index 0000000..a616605 --- /dev/null +++ b/mcu/lib/inc/hc32f460_ll_interrupts_share.h @@ -0,0 +1,351 @@ +/** + ******************************************************************************* + * @file hc32f460_ll_interrupts_share.h + * @brief This file contains all the functions prototypes of the interrupt driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-10-31 CDT Rename I2Cx_Error_IrqHandler as I2Cx_EE_IrqHandler + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F460_LL_INTERRUPTS_SHARE_H__ +#define __HC32F460_LL_INTERRUPTS_SHARE_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_HC32F460_SHARE_INTERRUPTS + * @{ + */ + +#if (LL_INTERRUPTS_SHARE_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup Share_Interrupts_Global_Functions + * @{ + */ + +int32_t INTC_ShareIrqCmd(en_int_src_t enIntSrc, en_functional_state_t enNewState); + +void IRQ128_Handler(void); +void IRQ129_Handler(void); +void IRQ130_Handler(void); +void IRQ131_Handler(void); +void IRQ132_Handler(void); +void IRQ136_Handler(void); +void IRQ137_Handler(void); +void IRQ138_Handler(void); +void IRQ139_Handler(void); +void IRQ140_Handler(void); +void IRQ141_Handler(void); +void IRQ142_Handler(void); +void IRQ143_Handler(void); + +void EXTINT00_IrqHandler(void); +void EXTINT01_IrqHandler(void); +void EXTINT02_IrqHandler(void); +void EXTINT03_IrqHandler(void); +void EXTINT04_IrqHandler(void); +void EXTINT05_IrqHandler(void); +void EXTINT06_IrqHandler(void); +void EXTINT07_IrqHandler(void); +void EXTINT08_IrqHandler(void); +void EXTINT09_IrqHandler(void); +void EXTINT10_IrqHandler(void); +void EXTINT11_IrqHandler(void); +void EXTINT12_IrqHandler(void); +void EXTINT13_IrqHandler(void); +void EXTINT14_IrqHandler(void); +void EXTINT15_IrqHandler(void); + +void DMA1_TC0_IrqHandler(void); +void DMA1_TC1_IrqHandler(void); +void DMA1_TC2_IrqHandler(void); +void DMA1_TC3_IrqHandler(void); +void DMA2_TC0_IrqHandler(void); +void DMA2_TC1_IrqHandler(void); +void DMA2_TC2_IrqHandler(void); +void DMA2_TC3_IrqHandler(void); +void DMA1_BTC0_IrqHandler(void); +void DMA1_BTC1_IrqHandler(void); +void DMA1_BTC2_IrqHandler(void); +void DMA1_BTC3_IrqHandler(void); +void DMA2_BTC0_IrqHandler(void); +void DMA2_BTC1_IrqHandler(void); +void DMA2_BTC2_IrqHandler(void); +void DMA2_BTC3_IrqHandler(void); +void DMA1_Error0_IrqHandler(void); +void DMA1_Error1_IrqHandler(void); +void DMA1_Error2_IrqHandler(void); +void DMA1_Error3_IrqHandler(void); +void DMA2_Error0_IrqHandler(void); +void DMA2_Error1_IrqHandler(void); +void DMA2_Error2_IrqHandler(void); +void DMA2_Error3_IrqHandler(void); + +void EFM_ProgramEraseError_IrqHandler(void); +void EFM_ColError_IrqHandler(void); +void EFM_OpEnd_IrqHandler(void); +void QSPI_Error_IrqHandler(void); +void DCU1_IrqHandler(void); +void DCU2_IrqHandler(void); +void DCU3_IrqHandler(void); +void DCU4_IrqHandler(void); + +void TMR0_1_CmpA_IrqHandler(void); +void TMR0_1_CmpB_IrqHandler(void); +void TMR0_2_CmpA_IrqHandler(void); +void TMR0_2_CmpB_IrqHandler(void); + +void CLK_XtalStop_IrqHandler(void); +void PWC_WakeupTimer_IrqHandler(void); +void SWDT_IrqHandler(void); +void WDT_IrqHandler(void); + +void TMR6_1_GCmpA_IrqHandler(void); +void TMR6_1_GCmpB_IrqHandler(void); +void TMR6_1_GCmpC_IrqHandler(void); +void TMR6_1_GCmpD_IrqHandler(void); +void TMR6_1_GCmpE_IrqHandler(void); +void TMR6_1_GCmpF_IrqHandler(void); +void TMR6_1_GOvf_IrqHandler(void); +void TMR6_1_GUdf_IrqHandler(void); +void TMR6_1_GDte_IrqHandler(void); +void TMR6_1_SCmpA_IrqHandler(void); +void TMR6_1_SCmpB_IrqHandler(void); + +void TMR6_2_GCmpA_IrqHandler(void); +void TMR6_2_GCmpB_IrqHandler(void); +void TMR6_2_GCmpC_IrqHandler(void); +void TMR6_2_GCmpD_IrqHandler(void); +void TMR6_2_GCmpE_IrqHandler(void); +void TMR6_2_GCmpF_IrqHandler(void); +void TMR6_2_GOvf_IrqHandler(void); +void TMR6_2_GUdf_IrqHandler(void); +void TMR6_2_GDte_IrqHandler(void); +void TMR6_2_SCmpA_IrqHandler(void); +void TMR6_2_SCmpB_IrqHandler(void); + +void TMR6_3_GCmpA_IrqHandler(void); +void TMR6_3_GCmpB_IrqHandler(void); +void TMR6_3_GCmpC_IrqHandler(void); +void TMR6_3_GCmpD_IrqHandler(void); +void TMR6_3_GCmpE_IrqHandler(void); +void TMR6_3_GCmpF_IrqHandler(void); +void TMR6_3_GOvf_IrqHandler(void); +void TMR6_3_GUdf_IrqHandler(void); +void TMR6_3_GDte_IrqHandler(void); +void TMR6_3_SCmpA_IrqHandler(void); +void TMR6_3_SCmpB_IrqHandler(void); + +void TMRA_1_Ovf_IrqHandler(void); +void TMRA_1_Udf_IrqHandler(void); +void TMRA_1_Cmp_IrqHandler(void); +void TMRA_2_Ovf_IrqHandler(void); +void TMRA_2_Udf_IrqHandler(void); +void TMRA_2_Cmp_IrqHandler(void); +void TMRA_3_Ovf_IrqHandler(void); +void TMRA_3_Udf_IrqHandler(void); +void TMRA_3_Cmp_IrqHandler(void); +void TMRA_4_Ovf_IrqHandler(void); +void TMRA_4_Udf_IrqHandler(void); +void TMRA_4_Cmp_IrqHandler(void); +void TMRA_5_Ovf_IrqHandler(void); +void TMRA_5_Udf_IrqHandler(void); +void TMRA_5_Cmp_IrqHandler(void); +void TMRA_6_Ovf_IrqHandler(void); +void TMRA_6_Udf_IrqHandler(void); +void TMRA_6_Cmp_IrqHandler(void); + +void USBFS_Global_IrqHandler(void); + +void USART1_RxError_IrqHandler(void); +void USART1_RxFull_IrqHandler(void); +void USART1_TxEmpty_IrqHandler(void); +void USART1_TxComplete_IrqHandler(void); +void USART1_RxTO_IrqHandler(void); +void USART2_RxError_IrqHandler(void); +void USART2_RxFull_IrqHandler(void); +void USART2_TxEmpty_IrqHandler(void); +void USART2_TxComplete_IrqHandler(void); +void USART2_RxTO_IrqHandler(void); +void USART3_RxError_IrqHandler(void); +void USART3_RxFull_IrqHandler(void); +void USART3_TxEmpty_IrqHandler(void); +void USART3_TxComplete_IrqHandler(void); +void USART3_RxTO_IrqHandler(void); +void USART4_RxError_IrqHandler(void); +void USART4_RxFull_IrqHandler(void); +void USART4_TxEmpty_IrqHandler(void); +void USART4_TxComplete_IrqHandler(void); +void USART4_RxTO_IrqHandler(void); + +void SPI1_RxFull_IrqHandler(void); +void SPI1_TxEmpty_IrqHandler(void); +void SPI1_Error_IrqHandler(void); +void SPI1_Idle_IrqHandler(void); +void SPI2_RxFull_IrqHandler(void); +void SPI2_TxEmpty_IrqHandler(void); +void SPI2_Error_IrqHandler(void); +void SPI2_Idle_IrqHandler(void); +void SPI3_RxFull_IrqHandler(void); +void SPI3_TxEmpty_IrqHandler(void); +void SPI3_Error_IrqHandler(void); +void SPI3_Idle_IrqHandler(void); +void SPI4_RxFull_IrqHandler(void); +void SPI4_TxEmpty_IrqHandler(void); +void SPI4_Error_IrqHandler(void); +void SPI4_Idle_IrqHandler(void); + +void TMR4_1_GCmpUH_IrqHandler(void); +void TMR4_1_GCmpUL_IrqHandler(void); +void TMR4_1_GCmpVH_IrqHandler(void); +void TMR4_1_GCmpVL_IrqHandler(void); +void TMR4_1_GCmpWH_IrqHandler(void); +void TMR4_1_GCmpWL_IrqHandler(void); +void TMR4_1_GOvf_IrqHandler(void); +void TMR4_1_GUdf_IrqHandler(void); +void TMR4_1_ReloadU_IrqHandler(void); +void TMR4_1_ReloadV_IrqHandler(void); +void TMR4_1_ReloadW_IrqHandler(void); +void TMR4_2_GCmpUH_IrqHandler(void); +void TMR4_2_GCmpUL_IrqHandler(void); +void TMR4_2_GCmpVH_IrqHandler(void); +void TMR4_2_GCmpVL_IrqHandler(void); +void TMR4_2_GCmpWH_IrqHandler(void); +void TMR4_2_GCmpWL_IrqHandler(void); +void TMR4_2_GOvf_IrqHandler(void); +void TMR4_2_GUdf_IrqHandler(void); +void TMR4_2_ReloadU_IrqHandler(void); +void TMR4_2_ReloadV_IrqHandler(void); +void TMR4_2_ReloadW_IrqHandler(void); +void TMR4_3_GCmpUH_IrqHandler(void); +void TMR4_3_GCmpUL_IrqHandler(void); +void TMR4_3_GCmpVH_IrqHandler(void); +void TMR4_3_GCmpVL_IrqHandler(void); +void TMR4_3_GCmpWH_IrqHandler(void); +void TMR4_3_GCmpWL_IrqHandler(void); +void TMR4_3_GOvf_IrqHandler(void); +void TMR4_3_GUdf_IrqHandler(void); +void TMR4_3_ReloadU_IrqHandler(void); +void TMR4_3_ReloadV_IrqHandler(void); +void TMR4_3_ReloadW_IrqHandler(void); + +void EMB_GR0_IrqHandler(void); +void EMB_GR1_IrqHandler(void); +void EMB_GR2_IrqHandler(void); +void EMB_GR3_IrqHandler(void); + +void I2S1_Tx_IrqHandler(void); +void I2S1_Rx_IrqHandler(void); +void I2S1_Error_IrqHandler(void); +void I2S2_Tx_IrqHandler(void); +void I2S2_Rx_IrqHandler(void); +void I2S2_Error_IrqHandler(void); +void I2S3_Tx_IrqHandler(void); +void I2S3_Rx_IrqHandler(void); +void I2S3_Error_IrqHandler(void); +void I2S4_Tx_IrqHandler(void); +void I2S4_Rx_IrqHandler(void); +void I2S4_Error_IrqHandler(void); + +void I2C1_RxFull_IrqHandler(void); +void I2C1_TxComplete_IrqHandler(void); +void I2C1_TxEmpty_IrqHandler(void); +void I2C1_EE_IrqHandler(void); +void I2C2_RxFull_IrqHandler(void); +void I2C2_TxComplete_IrqHandler(void); +void I2C2_TxEmpty_IrqHandler(void); +void I2C2_EE_IrqHandler(void); +void I2C3_RxFull_IrqHandler(void); +void I2C3_TxComplete_IrqHandler(void); +void I2C3_TxEmpty_IrqHandler(void); +void I2C3_EE_IrqHandler(void); + +void PWC_LVD1_IrqHandler(void); +void PWC_LVD2_IrqHandler(void); + +void FCM_Error_IrqHandler(void); +void FCM_End_IrqHandler(void); +void FCM_Ovf_IrqHandler(void); + +void ADC1_SeqA_IrqHandler(void); +void ADC1_SeqB_IrqHandler(void); +void ADC1_ChCmp_IrqHandler(void); +void ADC1_SeqCmp_IrqHandler(void); +void ADC2_SeqA_IrqHandler(void); +void ADC2_SeqB_IrqHandler(void); +void ADC2_ChCmp_IrqHandler(void); +void ADC2_SeqCmp_IrqHandler(void); + +void SDIOC1_IrqHandler(void); +void SDIOC2_IrqHandler(void); + +void CAN_IrqHandler(void); + +/** + * @} + */ + +#endif /* LL_INTERRUPTS_SHARE_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_LL_INTERRUPTS_SHARE_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/inc/hc32f4xx_conf.h b/mcu/lib/inc/hc32f4xx_conf.h new file mode 100644 index 0000000..f53d489 --- /dev/null +++ b/mcu/lib/inc/hc32f4xx_conf.h @@ -0,0 +1,137 @@ +/** + ******************************************************************************* + * @file gpio/gpio_output/source/hc32f4xx_conf.h + * @brief This file contains HC32 Series Device Driver Library usage management. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4XX_CONF_H__ +#define __HC32F4XX_CONF_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +#define HC32_DEBUG +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @brief This is the list of modules to be used in the Device Driver Library. + * Select the modules you need to use to DDL_ON. + * @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works + * properly. + * @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver + * Library. + * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. + */ + +#ifndef BOOT_ENABLE +#define LL_ICG_ENABLE (DDL_ON) +#endif + +#define LL_UTILITY_ENABLE (DDL_ON) +#define LL_PRINT_ENABLE (DDL_OFF) + +#define LL_ADC_ENABLE (DDL_OFF) +#define LL_AES_ENABLE (DDL_OFF) +#define LL_AOS_ENABLE (DDL_ON) +#define LL_CAN_ENABLE (DDL_OFF) +#define LL_CLK_ENABLE (DDL_ON) +#define LL_CMP_ENABLE (DDL_OFF) +#define LL_CRC_ENABLE (DDL_OFF) +#define LL_DBGC_ENABLE (DDL_OFF) +#define LL_DCU_ENABLE (DDL_OFF) +#define LL_DMA_ENABLE (DDL_ON) +#define LL_EFM_ENABLE (DDL_ON) +#define LL_EMB_ENABLE (DDL_OFF) +#define LL_EVENT_PORT_ENABLE (DDL_OFF) +#define LL_FCG_ENABLE (DDL_ON) +#define LL_FCM_ENABLE (DDL_ON) +#define LL_GPIO_ENABLE (DDL_ON) +#define LL_HASH_ENABLE (DDL_OFF) +#define LL_I2C_ENABLE (DDL_OFF) +#define LL_I2S_ENABLE (DDL_OFF) +#define LL_INTERRUPTS_ENABLE (DDL_ON) +#define LL_INTERRUPTS_SHARE_ENABLE (DDL_OFF) +#define LL_KEYSCAN_ENABLE (DDL_ON) +#define LL_MPU_ENABLE (DDL_OFF) +#define LL_OTS_ENABLE (DDL_OFF) +#define LL_PWC_ENABLE (DDL_ON) +#define LL_QSPI_ENABLE (DDL_OFF) +#define LL_RMU_ENABLE (DDL_OFF) +#define LL_RTC_ENABLE (DDL_OFF) +#define LL_SDIOC_ENABLE (DDL_OFF) +#define LL_SPI_ENABLE (DDL_ON) +#define LL_SRAM_ENABLE (DDL_ON) +#define LL_SWDT_ENABLE (DDL_ON) +#define LL_TMR0_ENABLE (DDL_ON) +#define LL_TMR4_ENABLE (DDL_OFF) +#define LL_TMR6_ENABLE (DDL_OFF) +#define LL_TMRA_ENABLE (DDL_ON) +#define LL_TRNG_ENABLE (DDL_OFF) +#define LL_USART_ENABLE (DDL_ON) +#define LL_USB_ENABLE (DDL_OFF) +#define LL_WDT_ENABLE (DDL_ON) + +/** + * @brief The following is a list of currently supported BSP boards. + */ +#define BSP_EV_HC32F460_LQFP100_V2 (4U) + +/** + * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently + * in use. + * The value should be set to one of the list of currently supported BSP boards. + * @note If there is no supported BSP board or the BSP function is not used, + * the value needs to be set to 0U. + */ +#define BSP_EV_HC32F4XX (0U) + +/** + * @brief This is the list of BSP components to be used. + * Select the components you need to use to DDL_ON. + */ +#define BSP_24CXX_ENABLE (DDL_OFF) +#define BSP_W25QXX_ENABLE (DDL_OFF) +#define BSP_WM8731_ENABLE (DDL_OFF) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4XX_CONF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/src/hc32_ll.c b/mcu/lib/src/hc32_ll.c new file mode 100644 index 0000000..e0a31a2 --- /dev/null +++ b/mcu/lib/src/hc32_ll.c @@ -0,0 +1,170 @@ +/** + ******************************************************************************* + * @file hc32_ll.c + * @brief This file provides firmware functions to low-level drivers (LL). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_Global Global + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup LL_Global_Functions LL Global Functions + * @{ + */ +void LL_PERIPH_WE(uint32_t u32Peripheral) +{ +#if (LL_EFM_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_EFM) != 0UL) { + /* Unlock all EFM registers */ + EFM_REG_Unlock(); + } +#endif +#if (LL_FCG_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_FCG) != 0UL) { + /* Unlock FCG register */ + PWC_FCG0_REG_Unlock(); + } +#endif +#if (LL_GPIO_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_GPIO) != 0UL) { + /* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */ + GPIO_REG_Unlock(); + } +#endif +#if (LL_MPU_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_MPU) != 0UL) { + /* Unlock all MPU registers */ + MPU_REG_Unlock(); + } +#endif +#if (LL_PWC_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_LVD) != 0UL) { + /* Unlock LVD registers, @ref PWC_REG_Write_Unlock_Code for details */ + PWC_REG_Unlock(PWC_UNLOCK_CODE2); + } +#endif +#if (LL_PWC_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_PWC_CLK_RMU) != 0UL) { + /* Unlock PWC, CLK, RMU registers, @ref PWC_REG_Write_Unlock_Code for details */ + PWC_REG_Unlock(PWC_UNLOCK_CODE0 | PWC_UNLOCK_CODE1); + } +#endif +#if (LL_SRAM_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_SRAM) != 0UL) { + /* Unlock SRAM register: WTCR, CKCR */ + SRAM_REG_Unlock(); + } +#endif +} + +void LL_PERIPH_WP(uint32_t u32Peripheral) +{ +#if (LL_EFM_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_EFM) != 0UL) { + /* Lock all EFM registers */ + EFM_REG_Lock(); + } +#endif +#if (LL_FCG_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_FCG) != 0UL) { + /* Lock FCG register */ + PWC_FCG0_REG_Lock(); + } +#endif +#if (LL_GPIO_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_GPIO) != 0UL) { + /* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */ + GPIO_REG_Lock(); + } +#endif +#if (LL_MPU_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_MPU) != 0UL) { + /* Lock all MPU registers */ + MPU_REG_Lock(); + } +#endif +#if (LL_PWC_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_LVD) != 0UL) { + /* Lock LVD registers, @ref PWC_REG_Write_Unlock_Code for details */ + PWC_REG_Lock(PWC_UNLOCK_CODE2); + } +#endif +#if (LL_PWC_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_PWC_CLK_RMU) != 0UL) { + /* Lock PWC, CLK, RMU registers, @ref PWC_REG_Write_Unlock_Code for details */ + PWC_REG_Lock(PWC_UNLOCK_CODE0 | PWC_UNLOCK_CODE1); + } +#endif +#if (LL_SRAM_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_SRAM) != 0UL) { + /* Lock SRAM register: WTCR, CKCR */ + SRAM_REG_Lock(); + } +#endif +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_adc.c b/mcu/lib/src/hc32_ll_adc.c new file mode 100644 index 0000000..79d074b --- /dev/null +++ b/mcu/lib/src/hc32_ll_adc.c @@ -0,0 +1,1084 @@ +/** + ******************************************************************************* + * @file hc32_ll_adc.c + * @brief This file provides firmware functions to manage the Analog-to-Digital + * Converter(ADC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-01-15 CDT API fixed: ADC_DeInit() + 2023-06-30 CDT Modify typo + API fixed: ADC_DeInit() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_adc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_ADC ADC + * @brief Analog-to-Digital Converter Driver Library + * @{ + */ + +#if (LL_ADC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ADC_Local_Macros ADC Local Macros + * @{ + */ + +/** + * @defgroup ADC_PGA_En ADC PGA Function Control + * @{ + */ +#define ADC_PGA_DISABLE (0x0U) +#define ADC_PGA_ENABLE (0xEU) +/** + * @} + */ + +/** + * @defgroup ADC_Channel_Max ADC Channel Max + * @{ + */ +#define ADC1_CH_MAX (ADC_CH16) +#define ADC2_CH_MAX (ADC_CH8) +#define ADC1_REMAP_CH_MAX (ADC_CH15) +#define ADC2_REMAP_CH_MAX (ADC_CH7) +#define ADC1_REMAP_PIN_MAX (ADC1_PIN_PC5) +#define ADC2_REMAP_PIN_MAX (ADC2_PIN_PC1) +#define ADC_SSTR_NUM (16U) +#define ADC1_SSTR_NUM (ADC_SSTR_NUM) +#define ADC2_SSTR_NUM (9U) +/** + * @} + */ + +/** + * @defgroup ADC_Check_Parameters_Validity ADC check parameters validity + * @{ + */ +#define IS_ADC_1BIT_MASK(x) (((x) != 0U) && (((x) & ((x) - 1U)) == 0U)) +#define IS_ADC_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask))) + +/* ADC unit check */ +#define IS_ADC_UNIT(x) (((x) == CM_ADC1) || ((x) == CM_ADC2)) + +/* ADC sequence check */ +#define IS_ADC_SEQ(x) (((x) == ADC_SEQ_A) || ((x) == ADC_SEQ_B)) + +/* ADC channel check */ +#define IS_ADC_CH(adc, ch) \ +( (((adc) == CM_ADC1) && ((ch) <= ADC1_CH_MAX)) || \ + (((adc) == CM_ADC2) && ((ch) <= ADC2_CH_MAX))) + +#define IS_ADC_SCAN_MD(x) \ +( ((x) == ADC_MD_SEQA_SINGLESHOT) || \ + ((x) == ADC_MD_SEQA_CONT) || \ + ((x) == ADC_MD_SEQA_SEQB_SINGLESHOT) || \ + ((x) == ADC_MD_SEQA_CONT_SEQB_SINGLESHOT)) + +#define IS_ADC_RESOLUTION(x) \ +( ((x) == ADC_RESOLUTION_8BIT) || \ + ((x) == ADC_RESOLUTION_10BIT) || \ + ((x) == ADC_RESOLUTION_12BIT)) + +#define IS_ADC_HARDTRIG(x) \ +( ((x) == ADC_HARDTRIG_ADTRG_PIN) || \ + ((x) == ADC_HARDTRIG_EVT0) || \ + ((x) == ADC_HARDTRIG_EVT1) || \ + ((x) == ADC_HARDTRIG_EVT0_EVT1)) + +#define IS_ADC_DATAALIGN(x) \ +( ((x) == ADC_DATAALIGN_RIGHT) || \ + ((x) == ADC_DATAALIGN_LEFT)) + +#define IS_ADC_SEQA_RESUME_MD(x) \ +( ((x) == ADC_SEQA_RESUME_SCAN_CONT) || \ + ((x) == ADC_SEQA_RESUME_SCAN_RESTART)) + +#define IS_ADC_SAMPLE_TIME(x) ((x) >= 5U) + +#define IS_ADC_INT(x) IS_ADC_BIT_MASK(x, ADC_INT_ALL) +#define IS_ADC_FLAG(x) IS_ADC_BIT_MASK(x, ADC_FLAG_ALL) + +/* Scan-average. */ +#define IS_ADC_AVG_CNT(x) (((x) | ADC_AVG_CNT256) == ADC_AVG_CNT256) + +/* Channel remapping. */ +#define IS_ADC_REMAP_PIN(adc, pin) \ +( (((adc) == CM_ADC1) && ((pin) <= ADC1_REMAP_PIN_MAX)) || \ + (((adc) == CM_ADC2) && ((pin) <= ADC2_REMAP_PIN_MAX))) +#define IS_ADC_REMAP_CH(adc, ch) \ +( (((adc) == CM_ADC1) && ((ch) <= ADC1_REMAP_CH_MAX)) || \ + (((adc) == CM_ADC2) && ((ch) <= ADC2_REMAP_CH_MAX))) + +/* Sync mode. */ +#define IS_ADC_SYNC_MD(x) \ +( ((x) == ADC_SYNC_SINGLE_DELAY_TRIG) || \ + ((x) == ADC_SYNC_SINGLE_PARALLEL_TRIG) || \ + ((x) == ADC_SYNC_CYCLIC_DELAY_TRIG) || \ + ((x) == ADC_SYNC_CYCLIC_PARALLEL_TRIG)) + +#define IS_ADC_SYNC(x) ((x) == ADC_SYNC_ADC1_ADC2) + +/* Analog watchdog. */ +#define IS_ADC_AWD_MD(x) \ +( ((x) == ADC_AWD_MD_CMP_OUT) || \ + ((x) == ADC_AWD_MD_CMP_IN)) + +#define IS_ADC_AWD(x) ((x) == ADC_AWD0) + +/* AWD flag check */ +#define IS_ADC_AWD_FLAG(adc, flag) \ +( (((adc) == CM_ADC1) && IS_ADC_BIT_MASK(flag, ADC1_AWD_FLAG_ALL)) || \ + (((adc) == CM_ADC2) && IS_ADC_BIT_MASK(flag, ADC2_AWD_FLAG_ALL))) + +#define IS_ADC_AWD_INT(x) IS_ADC_BIT_MASK(x, ADC_AWD_INT_ALL) + +/* PGA */ +#define IS_ADC_PGA_GAIN(x) ((x) <= ADC_PGA_GAIN_32) + +#define IS_ADC_PGA_VSS(x) (((x) == ADC_PGA_VSS_PGAVSS) || ((x) == ADC_PGA_VSS_AVSS)) + +/* PGA unit */ +#define IS_ADC_PGA(adc, pga) (((adc) == CM_ADC1) && ((pga) == ADC_PGA1)) +#define IS_PGA_ADC(x) ((x) == CM_ADC1) +#define IS_ADC_PGA_INPUT_SRC(x) \ +( IS_ADC_BIT_MASK(x, ADC_PGAINSR0_PGAINSEL) && IS_ADC_1BIT_MASK(x)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup ADC_Global_Functions ADC Global Functions + * @{ + */ + +/** + * @brief Initializes the specified ADC peripheral according to the specified parameters + * in the structure pstcAdcInit. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] pstcAdcInit Pointer to a @ref stc_adc_init_t structure that contains the + * configuration information for the specified ADC. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcAdcInit == NULL. + */ +int32_t ADC_Init(CM_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcAdcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + + if (pstcAdcInit != NULL) { + DDL_ASSERT(IS_ADC_SCAN_MD(pstcAdcInit->u16ScanMode)); + DDL_ASSERT(IS_ADC_RESOLUTION(pstcAdcInit->u16Resolution)); + DDL_ASSERT(IS_ADC_DATAALIGN(pstcAdcInit->u16DataAlign)); + /* Configures scan mode, resolution, data align. */ + WRITE_REG16(ADCx->CR0, pstcAdcInit->u16ScanMode | pstcAdcInit->u16Resolution | pstcAdcInit->u16DataAlign); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Deinitialize the specified ADC peripheral registers to their default reset values. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @retval int32_t: + * - LL_OK: De-Initialize success. + */ +int32_t ADC_DeInit(CM_ADC_TypeDef *ADCx) +{ + uint8_t i; + __IO uint8_t *reg8SSTR; + uint8_t u8SSTRNum; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + + /* Stop the ADC. */ + WRITE_REG8(ADCx->STR, 0U); + /* Set the registers to reset value. */ + WRITE_REG16(ADCx->CR0, 0x0U); + WRITE_REG16(ADCx->CR1, 0x0U); + WRITE_REG16(ADCx->TRGSR, 0x0U); + WRITE_REG32(ADCx->CHSELRA, 0x0U); + WRITE_REG32(ADCx->CHSELRB, 0x0U); + WRITE_REG8(ADCx->ICR, 0x03U); + WRITE_REG32(ADCx->AVCHSELR, 0x0U); + + /* SSTRx */ + u8SSTRNum = (ADCx == CM_ADC1) ? ADC1_SSTR_NUM : ADC2_SSTR_NUM; + reg8SSTR = (__IO uint8_t *)((uint32_t)&ADCx->SSTR0); + for (i = 0U; i < u8SSTRNum; i++) { + reg8SSTR[i] = 0x0BU; + } + + /* SSTRL */ + if (ADCx == CM_ADC1) { + WRITE_REG8(ADCx->SSTRL, 0x0BU); + } + + /* CHMUXRx */ + WRITE_REG16(ADCx->CHMUXR0, 0x3210U); + WRITE_REG16(ADCx->CHMUXR1, 0x7654U); + if (ADCx == CM_ADC1) { + WRITE_REG16(ADCx->CHMUXR2, 0xBA98U); + WRITE_REG16(ADCx->CHMUXR3, 0xFEDCU); + } + + /* ISR clearing */ + WRITE_REG8(ADCx->ISR, 0x03U); + + /* Sync mode */ + WRITE_REG16(ADCx->SYNCCR, 0x0C00U); + + /* Analog watchdog */ + WRITE_REG16(ADCx->AWDCR, 0x0U); + WRITE_REG16(ADCx->AWDDR0, 0x0U); + WRITE_REG16(ADCx->AWDDR1, 0x0U); + WRITE_REG16(ADCx->AWDCHSR, 0x0U); + WRITE_REG16(ADCx->AWDSR, 0x0U); + + /* PGA and OPA */ + if (ADCx == CM_ADC1) { + WRITE_REG16(ADCx->PGACR, 0x0U); + WRITE_REG16(ADCx->PGAGSR, 0x0U); + WRITE_REG16(ADCx->PGAINSR0, 0x0U); + WRITE_REG16(ADCx->PGAINSR1, 0x0U); + } + return LL_OK; +} + +/** + * @brief Set each @ref stc_adc_init_t field to default value. + * @param [in] pstcAdcInit Pointer to a @ref stc_adc_init_t structure + * whose fields will be set to default values. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcAdcInit == NULL. + */ +int32_t ADC_StructInit(stc_adc_init_t *pstcAdcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcAdcInit != NULL) { + pstcAdcInit->u16ScanMode = ADC_MD_SEQA_SINGLESHOT; + pstcAdcInit->u16Resolution = ADC_RESOLUTION_12BIT; + pstcAdcInit->u16DataAlign = ADC_DATAALIGN_RIGHT; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Enable or disable the specified ADC channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Seq The sequence whose channel specified by 'u8Ch' will be enabled or disabled. + * This parameter can be a value of @ref ADC_Sequence + * @arg ADC_SEQ_A: ADC sequence A. + * @arg ADC_SEQ_B: ADC sequence B. + * @param [in] u8Ch The ADC channel. + * This parameter can be values of @ref ADC_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @note Sequence A and Sequence B CAN NOT include the same channel! + * @note Sequence A can always started by software(by calling @ref ADC_Start()), + * regardless of whether the hardware trigger source is valid or not. + * @note Sequence B must be specified a valid hard trigger by calling functions @ref ADC_TriggerConfig() + * and @ref ADC_TriggerCmd(). + */ +void ADC_ChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint8_t u8Ch, en_functional_state_t enNewState) +{ + uint32_t u32CHSELAddr; + + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + DDL_ASSERT(IS_ADC_SEQ(u8Seq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32CHSELAddr = (uint32_t)&ADCx->CHSELRA + (u8Seq * 4UL); + if (enNewState == ENABLE) { + /* Enable the specified channel. */ + SET_REG32_BIT(RW_MEM32(u32CHSELAddr), 1UL << u8Ch); + } else { + /* Disable the specified channel. */ + CLR_REG32_BIT(RW_MEM32(u32CHSELAddr), 1UL << u8Ch); + } +} + +/** + * @brief Set sampling time for the specified channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch The channel to be set sampling time. + * This parameter can be values of @ref ADC_Channel + * @param [in] u8SampleTime Sampling time for the channel that specified by 'u8Ch'. + * @retval None + */ +void ADC_SetSampleTime(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8SampleTime) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_ADC_SAMPLE_TIME(u8SampleTime)); + + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + if (u8Ch < ADC_SSTR_NUM) { + u32Addr = (uint32_t)&ADCx->SSTR0 + u8Ch; + WRITE_REG8(RW_MEM8(u32Addr), u8SampleTime); + } else { + WRITE_REG8(ADCx->SSTRL, u8SampleTime); + } +} + +/** + * @brief Set scan-average count. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u16AverageCount Scan-average count. + * This parameter can be a value of @ref ADC_Average_Count + * @arg ADC_AVG_CNT2: 2 consecutive average conversions. + * @arg ADC_AVG_CNT4: 4 consecutive average conversions. + * @arg ADC_AVG_CNT8: 8 consecutive average conversions. + * @arg ADC_AVG_CNT16: 16 consecutive average conversions. + * @arg ADC_AVG_CNT32: 32 consecutive average conversions. + * @arg ADC_AVG_CNT64: 64 consecutive average conversions. + * @arg ADC_AVG_CNT128: 128 consecutive average conversions. + * @arg ADC_AVG_CNT256: 256 consecutive average conversions. + * @retval None + */ +void ADC_ConvDataAverageConfig(CM_ADC_TypeDef *ADCx, uint16_t u16AverageCount) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AVG_CNT(u16AverageCount)); + MODIFY_REG16(ADCx->CR0, ADC_CR0_AVCNT, u16AverageCount); +} + +/** + * @brief Enable or disable conversion data average calculation channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch The ADC channel. + * This parameter can be values of @ref ADC_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_ConvDataAverageChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG32_BIT(ADCx->AVCHSELR, 1UL << u8Ch); + } else { + CLR_REG32_BIT(ADCx->AVCHSELR, 1UL << u8Ch); + } +} + +/** + * @brief Specifies the hard trigger for the specified ADC sequence. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADCx or CM_ADC + * @param [in] u8Seq The sequence to be configured. + * This parameter can be a value of @ref ADC_Sequence + * @arg ADC_SEQ_A: Sequence A. + * @arg ADC_SEQ_B: Sequence B. + * @param [in] u16TriggerSel Hard trigger selection. This parameter can be a value of @ref ADC_Hard_Trigger_Sel + * @arg ADC_HARDTRIG_ADTRG_PIN: Selects the following edge of pin ADTRG as the trigger of ADC sequence. + * @arg ADC_HARDTRIG_EVT0: Selects an internal event as the trigger of ADC sequence. + This event is specified by register ADCx_TRGSEL0(x=(null), 1, 2, 3). + * @arg ADC_HARDTRIG_EVT1: Selects an internal event as the trigger of ADC sequence. + This event is specified by register ADCx_TRGSEL1(x=(null), 1, 2, 3). + * @arg ADC_HARDTRIG_EVT0_EVT1: Selects two internal events as the trigger of ADC sequence. + The two events are specified by register ADCx_TRGSEL0 and register ADCx_TRGSEL1. + * @retval None + * @note ADC must be stopped while calling this function. + * @note The trigger source CANNOT be an event that generated by the sequence itself. + */ +void ADC_TriggerConfig(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint16_t u16TriggerSel) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SEQ(u8Seq)); + DDL_ASSERT(IS_ADC_HARDTRIG(u16TriggerSel)); + + u8Seq *= ADC_TRGSR_TRGSELB_POS; + MODIFY_REG16(ADCx->TRGSR, (uint32_t)ADC_TRGSR_TRGSELA << u8Seq, (uint32_t)u16TriggerSel << u8Seq); +} + +/** + * @brief Enable or disable the hard trigger of the specified ADC sequence. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADCx or CM_ADC + * @param [in] u8Seq The sequence to be configured. + * This parameter can be a value of @ref ADC_Sequence + * @arg ADC_SEQ_A: Sequence A. + * @arg ADC_SEQ_B: Sequence B. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note ADC must be stopped while calling this function. + */ +void ADC_TriggerCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SEQ(u8Seq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Addr = (uint32_t)&ADCx->TRGSR; + /* Enable bit position: u8Seq * sequence_offset + enable_bit_base. */ + WRITE_REG32(PERIPH_BIT_BAND(u32Addr, (uint32_t)u8Seq * ADC_TRGSR_TRGSELB_POS + ADC_TRGSR_TRGENA_POS), enNewState); +} + +/** + * @brief Enable or disable ADC interrupts. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8IntType ADC interrupt. + * This parameter can be values of @ref ADC_Int_Type + * @arg ADC_INT_EOCA: Interrupt of the end of conversion of sequence A. + * @arg ADC_INT_EOCB: Interrupt of the end of conversion of sequence B. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_IntCmd(CM_ADC_TypeDef *ADCx, uint8_t u8IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_INT(u8IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG8_BIT(ADCx->ICR, u8IntType); + } else { + CLR_REG8_BIT(ADCx->ICR, u8IntType); + } +} + +/** + * @brief Start sequence A conversion. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @retval None + */ +void ADC_Start(CM_ADC_TypeDef *ADCx) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + WRITE_REG8(ADCx->STR, ADC_STR_STRT); +} + +/** + * @brief Stop ADC conversion, both sequence A and sequence B. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @retval None + */ +void ADC_Stop(CM_ADC_TypeDef *ADCx) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + WRITE_REG8(ADCx->STR, 0U); +} + +/** + * @brief Get the ADC value of the specified channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch The ADC channel. + * This parameter can be values of @ref ADC_Channel + * @retval An uint16_t type value of ADC value. + */ +uint16_t ADC_GetValue(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + + return RW_MEM16((uint32_t)&ADCx->DR0 + u8Ch * 2UL); +} + +/** + * @brief Get the status of the specified ADC flag. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Flag ADC status flag. + * This parameter can be a value of @ref ADC_Status_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t ADC_GetStatus(const CM_ADC_TypeDef *ADCx, uint8_t u8Flag) +{ + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_FLAG(u8Flag)); + + if (READ_REG8_BIT(ADCx->ISR, u8Flag) != 0U) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of the specified ADC flag. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Flag ADC status flag. + * This parameter can be valueS of @ref ADC_Status_Flag + * @retval None + */ +void ADC_ClearStatus(CM_ADC_TypeDef *ADCx, uint8_t u8Flag) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_FLAG(u8Flag)); + + CLR_REG8_BIT(ADCx->ISR, u8Flag); +} + +/** + * @brief Remap the correspondence between ADC channel and analog input pins. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch This parameter can be values of @ref ADC_Channel + * @param [in] u8AdcPin This parameter can be a value of @ref ADC_Remap_Pin + * @retval None + */ +void ADC_ChRemap(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8AdcPin) +{ + uint8_t u8FieldOfs; + uint8_t u8RegIdx; + __IO uint16_t *regCHMUXR; + + DDL_ASSERT(IS_ADC_REMAP_CH(ADCx, u8Ch)); + DDL_ASSERT(IS_ADC_REMAP_PIN(ADCx, u8AdcPin)); + + regCHMUXR = (__IO uint16_t *)((uint32_t)&ADCx->CHMUXR0); + u8RegIdx = u8Ch / 4U; + u8FieldOfs = (u8Ch % 4U) * 4U; + MODIFY_REG16(regCHMUXR[u8RegIdx], ((uint32_t)ADC_CHMUXR0_CH00MUX << u8FieldOfs), ((uint32_t)u8AdcPin << u8FieldOfs)); +} + +/** + * @brief Get the ADC pin corresponding to the specified ADC channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch ADC channel. + * This parameter can be one of the following values of @ref ADC_Channel + * @retval An uint8_t type value of ADC pin. @ref ADC_Remap_Pin + */ +uint8_t ADC_GetChPin(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch) +{ + uint8_t u8RetPin; + uint8_t u8FieldOfs; + uint8_t u8RegIdx; + __IO uint16_t *regCHMUXR; + + DDL_ASSERT(IS_ADC_REMAP_CH(ADCx, u8Ch)); + + regCHMUXR = (__IO uint16_t *)((uint32_t)&ADCx->CHMUXR0); + u8RegIdx = u8Ch / 4U; + u8FieldOfs = (u8Ch % 4U) * 4U; + u8RetPin = ((uint8_t)(regCHMUXR[u8RegIdx] >> u8FieldOfs)) & 0xFU; + + return u8RetPin; +} + +/** + * @brief Reset channel-pin mapping. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @retval None + */ +void ADC_ResetChMapping(CM_ADC_TypeDef *ADCx) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + + WRITE_REG16(ADCx->CHMUXR0, 0x3210U); + WRITE_REG16(ADCx->CHMUXR1, 0x7654U); + if (ADCx == CM_ADC1) { + WRITE_REG16(ADCx->CHMUXR2, 0xBA98U); + WRITE_REG16(ADCx->CHMUXR3, 0xFEDCU); + } +} + +/** + * @brief Configures synchronous mode. + * @param [in] u16SyncUnit Specify the ADC units which work synchronously. + * This parameter can be a value of @ref ADC_Sync_Unit + * @param [in] u16SyncMode Synchronous mode. + * This parameter can be a value of @ref ADC_Sync_Mode + * @arg ADC_SYNC_SINGLE_DELAY_TRIG: Single shot delayed trigger mode. + * When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has). + * All ADCs scan once. + * @arg ADC_SYNC_SINGLE_PARALLEL_TRIG: Single shot parallel trigger mode. + * When the trigger condition occurs, all ADCs start at the same time. + * All ADCs scan once. + * @arg ADC_SYNC_CYCLIC_DELAY_TRIG: Cyclic delayed trigger mode. + * When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has). + * All ADCs scan cyclicly(keep scanning till you stop them). + * @arg ADC_SYNC_CYCLIC_PARALLEL_TRIG: Single shot parallel trigger mode. + * When the trigger condition occurs, all ADCs start at the same time. + * All ADCs scan cyclicly(keep scanning till you stop them). + * @param [in] u8TriggerDelay Trigger delay time(ADCLK cycle), range is [1, 255]. + * @retval None + */ +void ADC_SyncModeConfig(uint16_t u16SyncUnit, uint16_t u16SyncMode, uint8_t u8TriggerDelay) +{ + DDL_ASSERT(IS_ADC_SYNC(u16SyncUnit)); + DDL_ASSERT(IS_ADC_SYNC_MD(u16SyncMode)); + + u16SyncMode |= ((uint16_t)((uint32_t)u8TriggerDelay << ADC_SYNCCR_SYNCDLY_POS)) | u16SyncUnit; + MODIFY_REG16(CM_ADC1->SYNCCR, ADC_SYNCCR_SYNCMD | ADC_SYNCCR_SYNCDLY, u16SyncMode); +} + +/** + * @brief Enable or disable synchronous mode. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_SyncModeCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(bCM_ADC1->SYNCCR_b.SYNCEN, enNewState); +} + +/** + * @brief Configures analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] u8Ch The channel that to be used as an analog watchdog channel. + * This parameter can be a value of @ref ADC_Channel + * @param [in] pstcAwd Pointer to a @ref stc_adc_awd_config_t structure value that + * contains the configuration information of the AWD. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcAwd == NULL. + */ +int32_t ADC_AWD_Config(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch, const stc_adc_awd_config_t *pstcAwd) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + + if (pstcAwd != NULL) { + DDL_ASSERT(IS_ADC_AWD_MD(pstcAwd->u16WatchdogMode)); + + (void)(u8AwdUnit); + MODIFY_REG16(ADCx->AWDCR, ADC_AWDCR_AWDMD, pstcAwd->u16WatchdogMode << ADC_AWDCR_AWDMD_POS); + WRITE_REG16(ADCx->AWDDR0, pstcAwd->u16LowThreshold); + WRITE_REG16(ADCx->AWDDR1, pstcAwd->u16HighThreshold); + SET_REG32_BIT(ADCx->AWDCHSR, 1UL << u8Ch); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Specifies the compare mode of analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] u16WatchdogMode Analog watchdog compare mode. + * This parameter can be a value of @ref ADC_AWD_Mode + * @arg ADC_AWD_MD_CMP_OUT: ADCValue > HighThreshold or ADCValue < LowThreshold + * @arg ADC_AWD_MD_CMP_IN: LowThreshold < ADCValue < HighThreshold + * @retval None + */ +void ADC_AWD_SetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16WatchdogMode) +{ + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + DDL_ASSERT(IS_ADC_AWD_MD(u16WatchdogMode)); + + (void)(u8AwdUnit); + MODIFY_REG16(ADCx->AWDCR, ADC_AWDCR_AWDMD, u16WatchdogMode << ADC_AWDCR_AWDMD_POS); +} + +/** + * @brief Get the compare mode of analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @retval Analog watchdog compare mode. A value of @ref ADC_AWD_Mode + * - ADC_AWD_MD_CMP_OUT: ADCValue > HighThreshold or ADCValue < LowThreshold + * - ADC_AWD_MD_CMP_IN: LowThreshold < ADCValue < HighThreshold + */ +uint16_t ADC_AWD_GetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit) +{ + uint16_t u16RetMode; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + + (void)(u8AwdUnit); + u16RetMode = READ_REG16_BIT(ADCx->AWDCR, ADC_AWDCR_AWDMD) >> ADC_AWDCR_AWDMD_POS; + + return u16RetMode; +} + +/** + * @brief Specifies the low threshold and high threshold of analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] u16LowThreshold Low threshold of analog watchdog. + * @param [in] u16HighThreshold High threshold of analog watchdog. + * @retval None + */ +void ADC_AWD_SetThreshold(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16LowThreshold, uint16_t u16HighThreshold) +{ + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + + (void)(u8AwdUnit); + WRITE_REG16(ADCx->AWDDR0, u16LowThreshold); + WRITE_REG16(ADCx->AWDDR1, u16HighThreshold); +} + +/** + * @brief Select the specified ADC channel as an analog watchdog channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] u8Ch The channel that to be used as an analog watchdog channel. + * This parameter can be a value of @ref ADC_Channel + * @retval None + */ +void ADC_AWD_SelectCh(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch) +{ + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + (void)(u8AwdUnit); + SET_REG32_BIT(ADCx->AWDCHSR, 1UL << u8Ch); +} + +/** + * @brief Deselects the specified ADC channel as an AWD channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] u8Ch ADC channel. + * This parameter can be a value of @ref ADC_Channel + * @retval None + */ +void ADC_AWD_DeselectCh(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch) +{ + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + (void)(u8AwdUnit); + CLR_REG32_BIT(ADCx->AWDCHSR, 1UL << u8Ch); +} + +/** + * @brief Enable or disable the specified analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be enabled or disabled. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_AWD_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Addr = (uint32_t)&ADCx->AWDCR; + (void)(u8AwdUnit); + /* Enable bit position: ADC_AWDCR_AWDEN_POS */ + WRITE_REG32(PERIPH_BIT_BAND(u32Addr, ADC_AWDCR_AWDEN_POS), enNewState); +} + +/** + * @brief Enable or disable the specified analog watchdog interrupts. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u16IntType Interrupt of AWD. + * This parameter can be a value of @ref ADC_AWD_Int_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_AWD_IntCmd(CM_ADC_TypeDef *ADCx, uint16_t u16IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD_INT(u16IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + static uint16_t u16AWDIntSeq = 0U; + if (enNewState == ENABLE) { + SET_REG16_BIT(ADCx->AWDCR, u16IntType | ADC_AWDCR_AWDIEN); + u16AWDIntSeq |= u16IntType; + } else { + u16AWDIntSeq &= ~u16IntType; + CLR_REG16_BIT(ADCx->AWDCR, u16IntType); + if (u16AWDIntSeq == 0U) { + CLR_REG16_BIT(ADCx->AWDCR, ADC_AWDCR_AWDIEN); + } + } +} + +/** + * @brief Get the status of the specified analog watchdog flag. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u32Flag AWD status flag. + * This parameter can be values of @ref ADC_AWD_Status_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t ADC_AWD_GetStatus(const CM_ADC_TypeDef *ADCx, uint32_t u32Flag) +{ + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_ADC_AWD_FLAG(ADCx, u32Flag)); + if (READ_REG32_BIT(ADCx->AWDSR, u32Flag) != 0U) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of the specified analog watchdog flag. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u32Flag AWD status flag. + * This parameter can be values of @ref ADC_AWD_Status_Flag + * @retval None + */ +void ADC_AWD_ClearStatus(CM_ADC_TypeDef *ADCx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_ADC_AWD_FLAG(ADCx, u32Flag)); + CLR_REG32_BIT(ADCx->AWDSR, u32Flag); +} + +/** + * @brief Configures the specified programmable gain amplifier. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8PgaUnit The PGA unit. + * This parameter can be a value of @ref ADC_PGA_Unit + * @param [in] u8Gain Gain of the specified PGA. + * This parameter can be a value of @ref ADC_PGA_Gain + * @arg ADC_PGA_GAIN_2: PGA gain factor is 2. + * @arg ADC_PGA_GAIN_2P133: PGA gain factor is 2.133. + * @arg ADC_PGA_GAIN_2P286: PGA gain factor is 2.286. + * @arg ADC_PGA_GAIN_2P667: PGA gain factor is 2.667. + * @arg ADC_PGA_GAIN_2P909: PGA gain factor is 2.909. + * @arg ADC_PGA_GAIN_3P2: PGA gain factor is 3.2. + * @arg ADC_PGA_GAIN_3P556: PGA gain factor is 2.556. + * @arg ADC_PGA_GAIN_4: PGA gain factor is 4. + * @arg ADC_PGA_GAIN_4P571: PGA gain factor is 4.571. + * @arg ADC_PGA_GAIN_5P333: PGA gain factor is 5.333. + * @arg ADC_PGA_GAIN_6P4: PGA gain factor is 6.4. + * @arg ADC_PGA_GAIN_8: PGA gain factor is 8. + * @arg ADC_PGA_GAIN_10P667: PGA gain factor is 10.667. + * @arg ADC_PGA_GAIN_16: PGA gain factor is 16. + * @arg ADC_PGA_GAIN_32: PGA gain factor is 32. + * @param [in] u8PgaVss VSS for the specified PGA. + * This parameter can be a value of @ref ADC_PGA_VSS + * @arg ADC_PGA_VSS_PGAVSS: Use pin PGAx_VSS as the reference GND of PGAx + * @arg ADC_PGA_VSS_AVSS: Use AVSS as the reference GND of PGAx. + * @retval None + */ +void ADC_PGA_Config(CM_ADC_TypeDef *ADCx, uint8_t u8PgaUnit, uint8_t u8Gain, uint8_t u8PgaVss) +{ + DDL_ASSERT(IS_ADC_PGA(ADCx, u8PgaUnit)); + DDL_ASSERT(IS_ADC_PGA_GAIN(u8Gain)); + DDL_ASSERT(IS_ADC_PGA_VSS(u8PgaVss)); + + (void)(u8PgaUnit); + WRITE_REG16(ADCx->PGAGSR, u8Gain); + WRITE_REG16(ADCx->PGAINSR1, u8PgaVss); +} + +/** + * @brief Enable the specified programmable gain amplifier. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8PgaUnit The PGA unit. + * This parameter can be a value of @ref ADC_PGA_Unit + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_PGA_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8PgaUnit, en_functional_state_t enNewState) +{ + const uint8_t au8Cmd[] = {ADC_PGA_DISABLE, ADC_PGA_ENABLE}; + + DDL_ASSERT(IS_ADC_PGA(ADCx, u8PgaUnit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + (void)(u8PgaUnit); + WRITE_REG16(ADCx->PGACR, au8Cmd[(uint8_t)enNewState]); +} + +/** + * @brief Selects PGA input source. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC1 + * @param [in] u16PgaInputSrc PGA input source. + * This parameter can be a value of @ref ADC_PGA_Input_Src + * @retval None + */ +void ADC_PGA_SelectInputSrc(CM_ADC_TypeDef *ADCx, uint16_t u16PgaInputSrc) +{ + DDL_ASSERT(IS_PGA_ADC(ADCx)); + DDL_ASSERT(IS_ADC_PGA_INPUT_SRC(u16PgaInputSrc)); + WRITE_REG16(ADCx->PGAINSR0, u16PgaInputSrc); +} + +/** + * @brief Deselects PGA input source. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC1 + * @retval None + */ +void ADC_PGA_DeselectInputSrc(CM_ADC_TypeDef *ADCx) +{ + DDL_ASSERT(IS_PGA_ADC(ADCx)); + WRITE_REG16(ADCx->PGAINSR0, 0U); +} + +/** + * @brief Enable or disable automatically clear data register. + * The automatic clearing function is mainly used to detect whether the data register is updated. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_DataRegAutoClearCmd(CM_ADC_TypeDef *ADCx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(ADCx->CR0, ADC_CR0_CLREN); + } else { + CLR_REG16_BIT(ADCx->CR0, ADC_CR0_CLREN); + } +} + +/** + * @brief Sequence A restart channel selection. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u16SeqAResumeMode Sequence A resume mode. + * This parameter can be a value of @ref ADC_SeqA_Resume_Mode + * @arg ADC_SEQA_RESUME_SCAN_CONT: Scanning will continue from the interrupted channel. + * @arg ADC_SEQA_RESUME_SCAN_RESTART: Scanning will start from the first channel. + * @retval None + */ +void ADC_SetSeqAResumeMode(CM_ADC_TypeDef *ADCx, uint16_t u16SeqAResumeMode) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SEQA_RESUME_MD(u16SeqAResumeMode)); + WRITE_REG16(ADCx->CR1, u16SeqAResumeMode); +} + +/** + * @} + */ + +#endif /* LL_ADC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_aes.c b/mcu/lib/src/hc32_ll_aes.c new file mode 100644 index 0000000..ea062aa --- /dev/null +++ b/mcu/lib/src/hc32_ll_aes.c @@ -0,0 +1,307 @@ +/** + ******************************************************************************* + * @file hc32_ll_aes.c + * @brief This file provides firmware functions to manage the Advanced Encryption + * Standard(AES). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-06-30 CDT Add API AES_DeInit() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_aes.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_AES AES + * @brief AES Driver Library + * @{ + */ + +#if (LL_AES_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup AES_Local_Macros AES Local Macros + * @{ + */ +/* Delay count for timeout */ +#define AES_TIMEOUT (30000UL) + +/* AES block size */ +#define AES_BLOCK_SIZE (16U) + +/** + * @defgroup AES_Check_Parameters_Validity AES Check Parameters Validity + * @{ + */ +#define IS_AES_KEY_SIZE(x) ((x) == AES_KEY_SIZE_16BYTE) + +/** + * @} + */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup AES_Local_Functions AES Local Functions + * @{ + */ +/** + * @brief Write the input buffer in data register. + * @param [in] pu8SrcData Point to the source data buffer. + * @retval None + */ +static void AES_WriteData(const uint8_t *pu8SrcData) +{ + uint8_t i; + __IO uint32_t *regDR = &CM_AES->DR0; + const uint32_t *pu32Data = (const uint32_t *)((uint32_t)pu8SrcData); + + for (i = 0U; i < 4U; i++) { + regDR[i] = pu32Data[i]; + } +} + +/** + * @brief Read the from data register. + * @param [out] pu8Result Point to the result buffer. + * @retval None + */ +static void AES_ReadData(uint8_t *pu8Result) +{ + uint8_t i; + __IO uint32_t *regDR = &CM_AES->DR0; + uint32_t *pu32Result = (uint32_t *)((uint32_t)pu8Result); + + for (i = 0U; i < 4U; i++) { + pu32Result[i] = regDR[i]; + } +} + +/** + * @brief Write the input buffer in key register. + * @param [in] pu8Key Pointer to the key buffer. + * @param [in] u8KeySize AES key size. This parameter can be a value of @ref AES_Key_Size + * @retval None + */ +static void AES_WriteKey(const uint8_t *pu8Key, uint8_t u8KeySize) +{ + uint8_t i; + uint8_t u8KeyWordSize = u8KeySize / 4U; + __IO uint32_t *regKR = &CM_AES->KR0; + const uint32_t *pu32Key = (const uint32_t *)((uint32_t)pu8Key); + + for (i = 0U; i < u8KeyWordSize; i++) { + regKR[i] = pu32Key[i]; + } +} + +/** + * @brief Wait AES operation done. + * @param None + * @retval None + */ +static int32_t AES_WaitDone(void) +{ + __IO uint32_t u32TimeCount = 0UL; + int32_t i32Ret = LL_OK; + + while (bCM_AES->CR_b.START != 0UL) { + if (u32TimeCount++ >= AES_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} +/** + * @} + */ + +/** + * @defgroup AES_Global_Functions AES Global Functions + * @{ + */ + +/** + * @brief AES encryption. + * @param [in] pu8Plaintext Buffer of the plaintext(the source data which will be encrypted). + * @param [in] u32PlaintextSize Length of plaintext in bytes. + * @param [in] pu8Key Pointer to the AES key. + * @param [in] u8KeySize AES key size. This parameter can be a value of @ref AES_Key_Size + * @param [out] pu8Ciphertext Buffer of the ciphertext. + * @retval int32_t: + * - LL_OK: Encrypt successfully. + * - LL_ERR_INVD_PARAM: Invalid parameter. + * - LL_TIMEOUT: Encrypt timeout. + */ +int32_t AES_Encrypt(const uint8_t *pu8Plaintext, uint32_t u32PlaintextSize, + const uint8_t *pu8Key, uint8_t u8KeySize, + uint8_t *pu8Ciphertext) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32Index = 0UL; + + DDL_ASSERT(IS_AES_KEY_SIZE(u8KeySize)); + DDL_ASSERT((u32PlaintextSize % AES_BLOCK_SIZE) == 0U); + + if ((pu8Plaintext != NULL) && (u32PlaintextSize > 0UL) && \ + (pu8Key != NULL) && (pu8Ciphertext != NULL)) { + AES_WriteKey(pu8Key, u8KeySize); + /* Set AES encrypt. */ + WRITE_REG32(bCM_AES->CR_b.MODE, 0UL); + while (u32Index < u32PlaintextSize) { + AES_WriteData(&pu8Plaintext[u32Index]); + /* Start AES calculating. */ + WRITE_REG32(bCM_AES->CR_b.START, 1UL); + /* Wait for AES to stop */ + i32Ret = AES_WaitDone(); + if (i32Ret != LL_OK) { + break; + } + AES_ReadData(&pu8Ciphertext[u32Index]); + u32Index += AES_BLOCK_SIZE; + } + } + + return i32Ret; +} + +/** + * @brief AES decryption. + * @param [in] pu8Ciphertext Buffer of the Ciphertext(the source data which will be decrypted). + * @param [in] u32CiphertextSize Length of ciphertext in bytes. + * @param [in] pu8Key Pointer to the AES key. + * @param [in] u8KeySize AES key size. This parameter can be a value of @ref AES_Key_Size + * @param [out] pu8Plaintext Buffer of the plaintext. + * @retval int32_t: + * - LL_OK: Decrypt successfully. + * - LL_ERR_INVD_PARAM: Invalid parameter. + * - LL_TIMEOUT: Decrypt timeout. + */ +int32_t AES_Decrypt(const uint8_t *pu8Ciphertext, uint32_t u32CiphertextSize, + const uint8_t *pu8Key, uint8_t u8KeySize, + uint8_t *pu8Plaintext) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32Index = 0UL; + + DDL_ASSERT(IS_AES_KEY_SIZE(u8KeySize)); + DDL_ASSERT((u32CiphertextSize % AES_BLOCK_SIZE) == 0U); + + if ((pu8Plaintext != NULL) && (u32CiphertextSize > 0UL) && \ + (pu8Key != NULL) && (pu8Ciphertext != NULL)) { + AES_WriteKey(pu8Key, u8KeySize); + /* Set AES decrypt. */ + WRITE_REG32(bCM_AES->CR_b.MODE, 1UL); + while (u32Index < u32CiphertextSize) { + AES_WriteData(&pu8Ciphertext[u32Index]); + /* Start AES calculating. */ + WRITE_REG32(bCM_AES->CR_b.START, 1UL); + /* Wait for AES to stop */ + i32Ret = AES_WaitDone(); + if (i32Ret != LL_OK) { + break; + } + AES_ReadData(&pu8Plaintext[u32Index]); + u32Index += AES_BLOCK_SIZE; + } + } + + return i32Ret; +} + +/** + * @brief De-Initialize AES function. + * @param None + * @retval int32_t: + * - LL_OK: De-Initialize success. + * - LL_ERR_TIMEOUT: Timeout. + */ +int32_t AES_DeInit(void) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32TimeOut = 0U; + uint8_t i; + __IO uint32_t *regDR = &CM_AES->DR0; + __IO uint32_t *regKR = &CM_AES->KR0; + /* Wait generating done */ + while (0UL != READ_REG32(bCM_AES->CR_b.START)) { + u32TimeOut++; + if (u32TimeOut > AES_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + if (LL_OK == i32Ret) { + /* Configures the registers to reset value. */ + WRITE_REG32(CM_AES->CR, 0x00000000UL); + for (i = 0U; i < 4U; i++) { + regDR[i] = 0x00000000UL; + } + for (i = 0U; i < 8U; i++) { + regKR[i] = 0x00000000UL; + } + } + return i32Ret; +} +/** + * @} + */ + +#endif /* LL_AES_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/mcu/lib/src/hc32_ll_aos.c b/mcu/lib/src/hc32_ll_aos.c new file mode 100644 index 0000000..3794de9 --- /dev/null +++ b/mcu/lib/src/hc32_ll_aos.c @@ -0,0 +1,179 @@ +/** + ******************************************************************************* + * @file hc32_ll_aos.c + * @brief This file provides firmware functions to manage the AOS. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-01-15 CDT Macro name modified: from IS_AOS_TRIG_SEL to IS_AOS_TARGET + Modified parameters name and comments of AOS_CommonTriggerCmd() and AOS_SetTriggerEventSrc() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_aos.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_AOS AOS + * @brief AOS Driver Library + * @{ + */ + +#if (LL_AOS_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup AOS_Local_Macros AOS Local Macros + * @{ + */ + +/** + * @defgroup AOS_Common_Trigger_ID_Validity AOS Common Trigger ID Validity + * @{ + */ +#define IS_AOS_COMM_TRIG(x) \ +( ((x) != 0UL) && \ + ((x) | AOS_COMM_TRIG_MASK) == AOS_COMM_TRIG_MASK) + +/** + * @} + */ + +/** + * @defgroup AOS_Target_Select_Validity AOS Target Select Validity + * @{ + */ +#define IS_AOS_TARGET(x) \ +( ((x) == AOS_DCU1) || \ + ((x) == AOS_DCU2) || \ + ((x) == AOS_DCU3) || \ + ((x) == AOS_DCU4) || \ + ((x) == AOS_DMA1_0) || \ + ((x) == AOS_DMA1_1) || \ + ((x) == AOS_DMA1_2) || \ + ((x) == AOS_DMA1_3) || \ + ((x) == AOS_DMA2_0) || \ + ((x) == AOS_DMA2_1) || \ + ((x) == AOS_DMA2_2) || \ + ((x) == AOS_DMA2_3) || \ + ((x) == AOS_DMA_RC) || \ + ((x) == AOS_TMR6_0) || \ + ((x) == AOS_TMR6_1) || \ + ((x) == AOS_TMR0) || \ + ((x) == AOS_EVTPORT12) || \ + ((x) == AOS_EVTPORT34) || \ + ((x) == AOS_TMRA_0) || \ + ((x) == AOS_TMRA_1) || \ + ((x) == AOS_OTS) || \ + ((x) == AOS_ADC1_0) || \ + ((x) == AOS_ADC1_1) || \ + ((x) == AOS_ADC2_0) || \ + ((x) == AOS_ADC2_1) || \ + ((x) == AOS_COMM_1) || \ + ((x) == AOS_COMM_2)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup AOS_Global_Functions AOS Global Functions + * @{ + */ + +/** + * @brief Common trigger function command + * @param [in] u32Target AOS target that need to be triggered by common trigger @ref AOS_Target_Select in details + * @param [in] u32CommonTrigger Common trigger ID + * This parameter can be one of the following values: + * @arg AOS_COMM_TRIG1: Common trigger 1. + * @arg AOS_COMM_TRIG2: Common trigger 2. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void AOS_CommonTriggerCmd(uint32_t u32Target, uint32_t u32CommonTrigger, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_AOS_TARGET(u32Target)); + DDL_ASSERT(IS_AOS_COMM_TRIG(u32CommonTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(*(__IO uint32_t *)u32Target, u32CommonTrigger); + } else { + CLR_REG32_BIT(*(__IO uint32_t *)u32Target, u32CommonTrigger); + } +} + +/** + * @brief Set trigger event source + * @param [in] u32Target AOS target that need to be triggered by AOS source @ref AOS_Target_Select in details + * @param [in] enSource AOS source that trigger the AOS target @ref en_event_src_t in details + * @retval None + */ +void AOS_SetTriggerEventSrc(uint32_t u32Target, en_event_src_t enSource) +{ + DDL_ASSERT(IS_AOS_TARGET(u32Target)); + + MODIFY_REG32(*(__IO uint32_t *)u32Target, AOS_TRIG_SEL_MASK, enSource); +} + +/** + * @} + */ + +#endif /* LL_AOS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_can.c b/mcu/lib/src/hc32_ll_can.c new file mode 100644 index 0000000..2315663 --- /dev/null +++ b/mcu/lib/src/hc32_ll_can.c @@ -0,0 +1,1410 @@ +/** + ******************************************************************************* + * @file hc32_ll_can.c + * @brief This file provides firmware functions to manage the CAN. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-10-31 CDT Deleted redundant comments + API fixed: CAN_FillTxFrame(), CAN_GetStatus(), CAN_ClearStatus() + 2023-06-30 CDT Added 3 APIs for local-reset.Refine local function CAN_ReadRxBuf(), CAN_WriteTxBuf() + Modify typo + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_can.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_CAN CAN + * @brief CAN Driver Library + * @{ + */ + +#if (LL_CAN_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CAN_Local_Macros CAN Local Macros + * @{ + */ + +/** + * @defgroup CAN_Check_Parameters_Validity CAN Check Parameters Validity + * @{ + */ +#define IS_CAN_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask))) + +#define IS_CAN_FUNC_EN(x, en) (((x) == 0U) || ((x) == (en))) + +#define IS_CAN_UNIT(x) ((x) == CM_CAN) + +#define IS_CAN_BIT_TIME_PRESC(x) (((x) >= 1U) && ((x) <= 256U)) + +#define IS_CAN_WORK_MD(x) ((x) <= CAN_WORK_MD_ELB_SILENT) + +#define IS_CAN_TX_BUF_TYPE(x) (((x) == CAN_TX_BUF_PTB) || ((x) == CAN_TX_BUF_STB)) + +#define IS_CAN_PTB_SINGLESHOT_TX(x) IS_CAN_FUNC_EN(x, CAN_PTB_SINGLESHOT_TX_ENABLE) + +#define IS_CAN_STB_SINGLESHOT_TX(x) IS_CAN_FUNC_EN(x, CAN_STB_SINGLESHOT_TX_ENABLE) + +#define IS_CAN_STB_PRIO_MD(x) IS_CAN_FUNC_EN(x, CAN_STB_PRIO_MD_ENABLE) + +#define IS_CAN_TX_REQ(x) IS_CAN_BIT_MASK(x, CAN_TX_REQ_STB_ONE|CAN_TX_REQ_STB_ALL|CAN_TX_REQ_PTB) + +#define IS_CAN_RX_ALL_FRAME(x) IS_CAN_FUNC_EN(x, CAN_RX_ALL_FRAME_ENABLE) + +#define IS_CAN_RX_OVF_MD(x) (((x) == CAN_RX_OVF_SAVE_NEW) || ((x) == CAN_RX_OVF_DISCARD_NEW)) + +#define IS_CAN_SELF_ACK(x) IS_CAN_FUNC_EN(x, CAN_SELF_ACK_ENABLE) + +#define IS_CAN_INT(x) IS_CAN_BIT_MASK(x, CAN_INT_ALL) + +#define IS_CAN_FLAG(x) IS_CAN_BIT_MASK(x, CAN_FLAG_ALL) + +#define IS_CAN_ID(ide, x) \ +( (((ide) == 1U) && (((x) | 0x1FFFFFFFUL) == 0x1FFFFFFFUL)) || \ + (((ide) == 0U) && (((x) | 0x7FFUL) == 0x7FFUL))) + +#define IS_CAN_ID_MASK(x) (((x) | 0x1FFFFFFFUL) == 0x1FFFFFFFUL) + +#define IS_CAN_IDE(x) (((x) == 0U) || ((x) == 1U)) + +#define IS_CAN_FILTER(x) IS_CAN_BIT_MASK(x, CAN_FILTER_ALL) + +#define IS_CAN_RX_WARN(x) (((x) >= CAN_RX_WARN_MIN) && ((x) <= CAN_RX_WARN_MAX)) + +#define IS_CAN_ERR_WARN(x) ((x) < 16U) + +#define IS_TTCAN_TX_BUF_MD(x) (((x) == CAN_TTC_TX_BUF_MD_CAN) || ((x) == CAN_TTC_TX_BUF_MD_TTCAN)) + +#define IS_TTCAN_TX_BUF_SEL(x) ((x) <= CAN_TTC_TX_BUF_STB4) + +#define IS_TTCAN_INT(x) IS_CAN_BIT_MASK(x, CAN_TTC_INT_ALL) + +#define IS_TTCAN_FLAG(x) IS_CAN_BIT_MASK(x, CAN_TTC_FLAG_ALL) + +#define IS_TTCAN_TX_EN_WINDOW(x) (((x) > 0U) && ((x) <= 16U)) + +#define IS_TTCAN_NTU_PRESCALER(x) \ +( ((x) == CAN_TTC_NTU_PRESCALER1) || \ + ((x) == CAN_TTC_NTU_PRESCALER2) || \ + ((x) == CAN_TTC_NTU_PRESCALER4) || \ + ((x) == CAN_TTC_NTU_PRESCALER8)) + +#define IS_TTCAN_TRIG_TYPE(x) \ +( ((x) == CAN_TTC_TRIG_IMMED_TRIG) || \ + ((x) == CAN_TTC_TRIG_TIME_TRIG) || \ + ((x) == CAN_TTC_TRIG_SINGLESHOT_TX_TRIG) || \ + ((x) == CAN_TTC_TRIG_TX_START_TRIG) || \ + ((x) == CAN_TTC_TRIG_TX_STOP_TRIG)) + +#define IS_CAN_ID_TYPE(x) \ +( ((x) == CAN_ID_STD_EXT) || \ + ((x) == CAN_ID_STD) || \ + ((x) == CAN_ID_EXT)) + +#define IS_CAN_SBT(seg1, seg2, sjw) \ +( (((seg1) >= 2U) && ((seg1) <= 65U)) && \ + (((seg2) >= 1U) && ((seg2) <= 8U)) && \ + (((sjw) >= 1U) && ((sjw) <= 8U)) && \ + ((seg1) >= ((seg2) + 1U)) && \ + ((seg2) >= (sjw))) + +/* FDF bit check */ +#define IS_CAN20_FDF(x) ((x) == 0U) + +/** + * @} + */ + +/** + * @defgroup CAN_Miscellaneous_Macros CAN Miscellaneous Macros + * @{ + */ +#define CAN_RX_BUF_NUM (10U) + +#define CAN_RX_WARN_MIN (1U) +#define CAN_RX_WARN_MAX (CAN_RX_BUF_NUM) + +#define CAN_ERRINT_FLAG_MASK (CAN_ERRINT_BEIF | CAN_ERRINT_ALIF | CAN_ERRINT_EPIF) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/** + * @defgroup CAN_Local_Variables CAN Local Variables + * @{ + */ +const static uint8_t m_au8DLC2WordSize[9U] = { + 0U, 1U, 1U, 1U, 1U, 2U, 2U, 2U, 2U +}; + +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup CAN_Local_Functions CAN Local Functions + * @{ + */ + +#if defined __DEBUG +/** + * @brief Initialization parameter check. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] pstcCanInit Pointer to a stc_can_init_t structure value that + * contains the configuration information for the CAN. + * @retval None + */ +static void CAN_InitParameterCheck(CM_CAN_TypeDef *CANx, const stc_can_init_t *pstcCanInit) +{ + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_WORK_MD(pstcCanInit->u8WorkMode)); + DDL_ASSERT(IS_CAN_PTB_SINGLESHOT_TX(pstcCanInit->u8PTBSingleShotTx)); + DDL_ASSERT(IS_CAN_STB_SINGLESHOT_TX(pstcCanInit->u8STBSingleShotTx)); + DDL_ASSERT(IS_CAN_STB_PRIO_MD(pstcCanInit->u8STBPrioMode)); + DDL_ASSERT(IS_CAN_RX_WARN(pstcCanInit->u8RxWarnLimit)); + DDL_ASSERT(IS_CAN_ERR_WARN(pstcCanInit->u8ErrorWarnLimit)); + DDL_ASSERT(IS_CAN_FILTER(pstcCanInit->u16FilterSelect)); + DDL_ASSERT(IS_CAN_RX_ALL_FRAME(pstcCanInit->u8RxAllFrame)); + DDL_ASSERT(IS_CAN_RX_OVF_MD(pstcCanInit->u8RxOvfMode)); + DDL_ASSERT(IS_CAN_SELF_ACK(pstcCanInit->u8SelfAck)); + + DDL_ASSERT(IS_CAN_BIT_TIME_PRESC(pstcCanInit->stcBitCfg.u32Prescaler)); + DDL_ASSERT(IS_CAN_SBT(pstcCanInit->stcBitCfg.u32TimeSeg1, + pstcCanInit->stcBitCfg.u32TimeSeg2, + pstcCanInit->stcBitCfg.u32SJW)); +} +#endif + +/** + * @brief Specifies work mode for the specified CAN unit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8WorkMode Work mode of CAN. + * This parameter can be a value of @ref CAN_Work_Mode + * @arg CAN_WORK_MD_NORMAL: Normal work mode. + * @arg CAN_WORK_MD_SILENT: Silent work mode. Prohibit data transmission. + * @arg CAN_WORK_MD_ILB: Internal loop back mode, just for self-test while developing. + * @arg CAN_WORK_MD_ELB: External loop back mode, just for self-test while developing. + * @arg CAN_WORK_MD_ELB_SILENT: External loop back silent mode, just for self-test while developing. + * It is forbidden to respond to received frames and error frames, + * but data can be transmitted. + * @retval None + * @note Call this function when CFG_STAT.RESET is 0. + */ +static void CAN_SetWorkMode(CM_CAN_TypeDef *CANx, uint8_t u8WorkMode) +{ + uint8_t u8CFGSTAT = 0U; + uint8_t u8TCMD = 0U; + + switch (u8WorkMode) { + case CAN_WORK_MD_SILENT: + u8TCMD = CAN_TCMD_LOM; + break; + case CAN_WORK_MD_ILB: + u8CFGSTAT = CAN_CFG_STAT_LBMI; + break; + case CAN_WORK_MD_ELB: + u8CFGSTAT = CAN_CFG_STAT_LBME; + break; + case CAN_WORK_MD_ELB_SILENT: + u8TCMD = CAN_TCMD_LOM; + u8CFGSTAT = CAN_CFG_STAT_LBME; + break; + case CAN_WORK_MD_NORMAL: + default: + break; + } + + MODIFY_REG8(CANx->CFG_STAT, CAN_CFG_STAT_LBMI | CAN_CFG_STAT_LBME, u8CFGSTAT); + MODIFY_REG8(CANx->TCMD, CAN_TCMD_LOM, u8TCMD); +} + +/** + * @brief Configures acceptance filter. Set ID and ID mask for the specified acceptance filters. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u16FilterSelect Acceptance filters selection. + * This parameter can be values of @ref CAN_Acceptance_Filter + * @param [in] pstcFilter Pointer to a stc_can_filter_config_t structure type array which contains ID and ID mask + * values for the acceptance filters specified by parameter u16FilterSelect. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: If one the following cases matches: + * - u16FilterSelect == 0U. + * - pstcFilter == NULL. + * @note Call this function when CFG_STAT.RESET is 1. + */ +static int32_t CAN_FilterConfig(CM_CAN_TypeDef *CANx, uint16_t u16FilterSelect, + const stc_can_filter_config_t *pstcFilter) +{ + uint8_t u8FilterAddr = 0U; + uint8_t i = 0U; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + if ((u16FilterSelect != 0U) && (pstcFilter != NULL)) { + while (u16FilterSelect != 0U) { + if ((u16FilterSelect & 0x1U) != 0U) { + DDL_ASSERT(IS_CAN_ID_TYPE(pstcFilter[i].u32IDType)); + DDL_ASSERT(IS_CAN_ID_MASK(pstcFilter[i].u32IDMask)); + WRITE_REG8(CANx->ACFCTRL, u8FilterAddr); + WRITE_REG32(CANx->ACF, pstcFilter[i].u32ID); + SET_REG8_BIT(CANx->ACFCTRL, CAN_ACFCTRL_SELMASK); + WRITE_REG32(CANx->ACF, pstcFilter[i].u32IDMask | pstcFilter[i].u32IDType); + i++; + } + u16FilterSelect >>= 1U; + u8FilterAddr++; + } + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Write TX buffer register in bytes. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] pstcTx Pointer to a @ref stc_can_tx_frame_t structure. + * @retval None + */ +static void CAN_WriteTxBuf(CM_CAN_TypeDef *CANx, const stc_can_tx_frame_t *pstcTx) +{ + uint8_t i; + uint8_t u8WordLen; + __IO uint32_t *reg32TBUF; + uint32_t *pu32TxData = (uint32_t *)((uint32_t)(&pstcTx->au8Data[0U])); + + reg32TBUF = (__IO uint32_t *)((uint32_t)&CANx->TBUF); + reg32TBUF[0U] = pstcTx->u32ID; + reg32TBUF[1U] = pstcTx->u32Ctrl; + + u8WordLen = m_au8DLC2WordSize[pstcTx->DLC]; + if ((pstcTx->FDF == 0U) && (u8WordLen > 2U)) { + /* Maximum size of data payload is 8 bytes(2words) for classical CAN frame. */ + u8WordLen = 2U; + } + + for (i = 0U; i < u8WordLen; i++) { + reg32TBUF[2U + i] = pu32TxData[i]; + } +} + +/** + * @brief Read RX buffer register in bytes. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] pstcRx Pointer to a @ref stc_can_rx_frame_t structure. + * @retval None + */ +static void CAN_ReadRxBuf(const CM_CAN_TypeDef *CANx, stc_can_rx_frame_t *pstcRx) +{ + __I uint32_t *reg32RBUF; + uint8_t i; + uint8_t u8WordLen; + uint32_t *pu32RxData = (uint32_t *)((uint32_t)(&pstcRx->au8Data[0U])); + + reg32RBUF = (__I uint32_t *)((uint32_t)&CANx->RBUF); + pstcRx->u32ID = reg32RBUF[0U]; + pstcRx->u32Ctrl = reg32RBUF[1U]; + + if (pstcRx->IDE == 0U) { + pstcRx->u32ID &= 0x7FFUL; + } else { + pstcRx->u32ID &= 0x1FFFFFFFUL; + } + + u8WordLen = m_au8DLC2WordSize[pstcRx->DLC]; + if ((pstcRx->FDF == 0U) && (u8WordLen > 2U)) { + /* Maximum size of data payload is 8 bytes(2words) for classical CAN frame. */ + u8WordLen = 2U; + } + + for (i = 0U; i < u8WordLen; i++) { + pu32RxData[i] = reg32RBUF[2U + i]; + } +} + +/** + * @} + */ + +/** + * @defgroup CAN_Global_Functions CAN Global Functions + * @{ + */ + +/** + * @brief Initializes the specified CAN peripheral according to the specified parameters + * in the structure pstcCanInit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] pstcCanInit Pointer to a @ref stc_can_init_t structure value that + * contains the configuration information for the CAN. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcCanInit == NULL + */ +int32_t CAN_Init(CM_CAN_TypeDef *CANx, const stc_can_init_t *pstcCanInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcCanInit != NULL) { +#if defined __DEBUG + CAN_InitParameterCheck(CANx, pstcCanInit); +#endif + /* Local reset. */ + SET_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET); + /* Configures nominal bit time. */ + WRITE_REG32(CANx->SBT, ((pstcCanInit->stcBitCfg.u32TimeSeg1 - 2U) | \ + ((pstcCanInit->stcBitCfg.u32TimeSeg2 - 1U) << CAN_SBT_S_SEG_2_POS) | \ + ((pstcCanInit->stcBitCfg.u32SJW - 1U) << CAN_SBT_S_SJW_POS) | \ + ((pstcCanInit->stcBitCfg.u32Prescaler - 1U) << CAN_SBT_S_PRESC_POS))); + /* Enable or disable STB priority mode. */ + MODIFY_REG8(CANx->TCTRL, CAN_TCTRL_TSMODE, pstcCanInit->u8STBPrioMode); + /* Configures acceptance filters. */ + (void)CAN_FilterConfig(CANx, pstcCanInit->u16FilterSelect, pstcCanInit->pstcFilter); + + /* CAN enters normal communication mode. */ + CLR_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET); + /* Specifies CAN work mode. */ + CAN_SetWorkMode(CANx, pstcCanInit->u8WorkMode); + /* Enable or disable single shot transmission mode of PTB and STB. */ + MODIFY_REG8(CANx->CFG_STAT, \ + (CAN_CFG_STAT_TPSS | CAN_CFG_STAT_TSSS), \ + (pstcCanInit->u8PTBSingleShotTx | pstcCanInit->u8STBSingleShotTx)); + /* Specifies receive buffer almost full warning limit. Specifies error warning limit. */ + WRITE_REG8(CANx->LIMIT, ((pstcCanInit->u8RxWarnLimit << CAN_LIMIT_AFWL_POS) | pstcCanInit->u8ErrorWarnLimit)); + + /* Enable or disable RX all frames(include frames with error). + Specifies receive overflow mode. In case of a full rx buffer when a new message is received. + Enable or disable self-acknowledge. */ + WRITE_REG8(CANx->RCTRL, pstcCanInit->u8RxAllFrame | \ + pstcCanInit->u8RxOvfMode | \ + pstcCanInit->u8SelfAck); + /* Enable acceptance filters that configured before. */ + WRITE_REG8(CANx->ACFEN, pstcCanInit->u16FilterSelect); + /* Configures TTCAN if needed. */ + if (pstcCanInit->pstcCanTtc != NULL) { + (void)CAN_TTC_Config(CANx, pstcCanInit->pstcCanTtc); + } + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set each @ref stc_can_init_t field to a default value. + * Classical CAN bit time configuration: + * Based on 40MHz CAN clock, TQ clock is CAN clock divided by 4. + * Bit rate 500Kbps, 1 bit time is 20TQs, sample point is 80%. + * CAN-FD bit time configuration: + * Based on 40MHz CAN clock, TQ clock is CAN clock divided by 1. + * Bit rate 2Mbps, 1 bit time is 20TQs, primary sample point is 80%, + * secondary sample point is 80%. + * @param [in] pstcCanInit Pointer to a @ref stc_can_init_t structure + * whose fields will be set to default values. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcCanInit == NULL. + */ +int32_t CAN_StructInit(stc_can_init_t *pstcCanInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcCanInit != NULL) { + /** + * Synchronization Segment(SS): Fixed as 1TQ + * Propagation Time Segment(PTS) and Phase Buffer Segment 1(PBS1): 15TQs + * Phase Buffer Segment 2(PBS2): 4TQs + * + * Field 'S_SEG_1' in register CAN_SBT contains SS, PTS and PBS1. + * Field 'S_SEG_2' in register CAN_SBT only contains PBS2. + * Sample point = (SS + PTS + PBS1) / (SS + PTS + PBS1 + PBS2) + * = (1 + 15) / (1 + 15 + 4) + * = 80%. + */ + pstcCanInit->stcBitCfg.u32Prescaler = 4U; + pstcCanInit->stcBitCfg.u32TimeSeg1 = 16U; + pstcCanInit->stcBitCfg.u32TimeSeg2 = 4U; + pstcCanInit->stcBitCfg.u32SJW = 2U; + pstcCanInit->pstcFilter = NULL; + pstcCanInit->u16FilterSelect = 0U; + pstcCanInit->u8WorkMode = CAN_WORK_MD_NORMAL; + pstcCanInit->u8PTBSingleShotTx = CAN_PTB_SINGLESHOT_TX_DISABLE; + pstcCanInit->u8STBSingleShotTx = CAN_STB_SINGLESHOT_TX_DISABLE; + pstcCanInit->u8STBPrioMode = CAN_STB_PRIO_MD_DISABLE; + pstcCanInit->u8RxWarnLimit = CAN_RX_WARN_MAX; + pstcCanInit->u8ErrorWarnLimit = 7U; + pstcCanInit->u8RxAllFrame = CAN_RX_ALL_FRAME_DISABLE; + pstcCanInit->u8RxOvfMode = CAN_RX_OVF_DISCARD_NEW; + pstcCanInit->u8SelfAck = CAN_SELF_ACK_DISABLE; + pstcCanInit->pstcCanTtc = NULL; + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Deinitialize the specified CAN peripheral registers to their default reset values. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @retval None + */ +void CAN_DeInit(CM_CAN_TypeDef *CANx) +{ + uint8_t i; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + CLR_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET); + for (i = 0U; i < 2U; i++) { + WRITE_REG8(CANx->CFG_STAT, 0x80U); + WRITE_REG8(CANx->TCMD, 0x00U); + WRITE_REG8(CANx->TCTRL, 0x90U); + WRITE_REG8(CANx->RCTRL, 0x10U); + WRITE_REG8(CANx->RTIE, 0xFEU); + WRITE_REG8(CANx->RTIF, 0xFFU); + WRITE_REG8(CANx->ERRINT, 0xD5U); + WRITE_REG8(CANx->LIMIT, 0x1BU); + WRITE_REG32(CANx->SBT, 0x01020203UL); + WRITE_REG8(CANx->RECNT, 0x00U); + WRITE_REG8(CANx->TECNT, 0x00U); + WRITE_REG8(CANx->ACFCTRL, 0x00U); + WRITE_REG8(CANx->TBSLOT, 0x00U); + WRITE_REG8(CANx->TTCFG, 0xD8U); + WRITE_REG16(CANx->TRG_CFG, 0x00U); + WRITE_REG16(CANx->TT_TRIG, 0x00U); + WRITE_REG16(CANx->TT_WTRIG, 0x00U); + WRITE_REG8(CANx->ACFEN, 0x01U); + + SET_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET); + } +} + +/** + * @brief Enable or disable specified interrupts. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u32IntType Interrupt of CAN. + * This parameter can be values of @ref CAN_Interrupt_Type + * @arg CAN_INT_ERR_INT: Register bit RTIE.EIE. Error interrupt. + * @arg CAN_INT_STB_TX: Register bit RTIE.TSIE. STB was transmitted successfully. + * @arg CAN_INT_PTB_TX: Register bit RTIE.TPIE. PTB was transmitted successfully. + * @arg CAN_INT_RX_BUF_WARN: Register bit RTIE.RAFIE. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. + * @arg CAN_INT_RX_BUF_FULL: Register bit RTIE.RFIE. The FIFO of receive buffer is full. + * @arg CAN_INT_RX_OVERRUN: Register bit RTIE.ROIE. Receive buffers are full and there is a further message to be stored. + * @arg CAN_INT_RX: Register bit RTIE.RIE. Received a valid data frame or remote frame. + * @arg CAN_INT_BUS_ERR: Register bit ERRINT.BEIE. Arbitration lost caused bus error + * @arg CAN_INT_ARBITR_LOST: Register bit ERRINT.ALIE. Arbitration lost. + * @arg CAN_INT_ERR_PASSIVE: Register bit ERRINT.EPIE. A change from error-passive to error-active or error-active to error-passive has occurred. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CAN_IntCmd(CM_CAN_TypeDef *CANx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint8_t u8RTIE; + uint8_t u8ERRINT; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u8RTIE = (uint8_t)u32IntType; + u8ERRINT = (uint8_t)(u32IntType >> 8U); + + if (enNewState == ENABLE) { + SET_REG8_BIT(CANx->RTIE, u8RTIE); + SET_REG8_BIT(CANx->ERRINT, u8ERRINT); + } else { + CLR_REG8_BIT(CANx->RTIE, u8RTIE); + CLR_REG8_BIT(CANx->ERRINT, u8ERRINT); + } +} + +/** + * @brief Fills transmit frame. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8TxBufType CAN transmit buffer type. + * This parameter can be a value of @ref CAN_Tx_Buf_Type + * @param [in] pstcTx Pointer to a @ref stc_can_tx_frame_t structure. + * @arg CAN_TX_BUF_PTB: Primary transmit buffer. + * @arg CAN_TX_BUF_STB: Secondary transmit buffer. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcTx == NULL. + * - LL_ERR_BUF_FULL: The specified transmit buffer is full. + * - LL_ERR_BUSY: The specified transmit buffer is being transmitted. + */ +int32_t CAN_FillTxFrame(CM_CAN_TypeDef *CANx, uint8_t u8TxBufType, const stc_can_tx_frame_t *pstcTx) +{ + uint8_t u8RTIE; + uint8_t u8TCTRL; + uint32_t u32RegAddr; + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_TX_BUF_TYPE(u8TxBufType)); + + if (pstcTx != NULL) { + DDL_ASSERT(IS_CAN20_FDF(pstcTx->FDF)); + if (u8TxBufType == CAN_TX_BUF_PTB) { + if (READ_REG8_BIT(CANx->TCMD, CAN_TCMD_TPE) != 0U) { + /* PTB is being transmitted. */ + i32Ret = LL_ERR_BUSY; + } + } else { + if (READ_REG8_BIT(CANx->TCMD, (CAN_TCMD_TSONE | CAN_TCMD_TSALL)) != 0U) { + /* STB is being transmitted. */ + i32Ret = LL_ERR_BUSY; + } else { + u8RTIE = READ_REG8(CANx->RTIE); + u8TCTRL = READ_REG8(CANx->TCTRL); + if (((u8RTIE & CAN_RTIE_TSFF) == CAN_RTIE_TSFF) || \ + ((u8TCTRL & CAN_TCTRL_TSSTAT) == CAN_TCTRL_TSSTAT)) { + /* All STBs are filled. */ + i32Ret = LL_ERR_BUF_FULL; + } + } + } + + if (i32Ret == LL_OK) { + /* Assert ID */ + DDL_ASSERT(IS_CAN_ID(pstcTx->IDE, pstcTx->u32ID)); + + /* Specifies the transmit buffer, PTB or STB. */ + u32RegAddr = (uint32_t)&CANx->TCMD; + WRITE_REG32(PERIPH_BIT_BAND(u32RegAddr, CAN_TCMD_TBSEL_POS), u8TxBufType); + + CAN_WriteTxBuf(CANx, pstcTx); + + if (u8TxBufType == CAN_TX_BUF_STB) { + /* After writes the data in transmit buffer(TB), sets the TSNEXT bit to indicate that the current + STB slot has been filled, so that the hardware will point TB to the next STB slot. */ + SET_REG8_BIT(CANx->TCTRL, CAN_TCTRL_TSNEXT); + } + } + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + + return i32Ret; +} + +/** + * @brief Starts transmission. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8TxRequest The transmit buffer to be transmitted. + * This parameter can be values of @ref CAN_Tx_Request + * @arg CAN_TX_REQ_STB_ONE: Transmit one STB frame. + * @arg CAN_TX_REQ_STB_ALL: Transmit all STB frames. + * @arg CAN_TX_REQ_PTB: Transmit PTB frame. + * @retval None + * @note Call this function when CFG_STAT.RESET is 0. + */ +void CAN_StartTx(CM_CAN_TypeDef *CANx, uint8_t u8TxRequest) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_TX_REQ(u8TxRequest)); + SET_REG8_BIT(CANx->TCMD, u8TxRequest); +} + +/** + * @brief Abort the transmission of the specified transmit buffer. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8TxBufType The transmit buffer to be aborted. + * This parameter can be a value of @ref CAN_Tx_Buf_Type + * @arg CAN_TX_BUF_PTB: Abort PTB transmission. + * @arg CAN_TX_BUF_STB: Abort STB transmission. + * @retval None + * @note Call this function when CFG_STAT.RESET is 0. + */ +void CAN_AbortTx(CM_CAN_TypeDef *CANx, uint8_t u8TxBufType) +{ + uint8_t au8Abort[] = {CAN_TCMD_TPA, CAN_TCMD_TSA}; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_TX_BUF_TYPE(u8TxBufType)); + SET_REG8_BIT(CANx->TCMD, au8Abort[u8TxBufType]); +} + +/** + * @brief Get one received frame. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [out] pstcRx Pointer to a @ref stc_can_rx_frame_t structure. + * @retval int32_t: + * - LL_OK: Get one received frame successfully. + * - LL_ERR_BUF_EMPTY: Receive buffer is empty, and no frame has been read. + * - LL_ERR_INVD_PARAM: pstcRx == NULL. + */ +int32_t CAN_GetRxFrame(CM_CAN_TypeDef *CANx, stc_can_rx_frame_t *pstcRx) +{ + int32_t i32Ret = LL_ERR_BUF_EMPTY; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + if (pstcRx == NULL) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + if (READ_REG8_BIT(CANx->RCTRL, CAN_RCTRL_RSTAT) != CAN_RX_BUF_EMPTY) { + CAN_ReadRxBuf(CANx, pstcRx); + /* Set RB to point to the next RB slot. */ + SET_REG8_BIT(CANx->RCTRL, CAN_RCTRL_RREL); + + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** Request a local-reset. The some register (e.g for node configuration) can only be modified if RESET=1. + * Bit RESET forces several components to a reset state, see the reference manual for details. + * @brief + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @retval None + */ +void CAN_EnterLocalReset(CM_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + SET_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET); +} + +/** Exit the local-reset state. A CAN node will participate in CAN communication after RESET is switched to 0 after 11 CAN bit times. + * @brief + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @retval None + */ +void CAN_ExitLocalReset(CM_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + CLR_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET); +} + +/** Check whether CAN is in the local-reset state. + * @brief + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CAN_GetLocalResetStatus(CM_CAN_TypeDef *CANx) +{ + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + if (READ_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET) != 0U) { + /* The CAN is in local-reset state */ + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Get the status of specified flag. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u32Flag CAN status flag. + * This parameter can be a value of @ref CAN_Status_Flag + * @arg CAN_FLAG_BUS_OFF: Register bit CFG_STAT.BUSOFF. CAN bus off. + * @arg CAN_FLAG_TX_GOING: Register bit CFG_STAT.TACTIVE. CAN bus is transmitting. + * @arg CAN_FLAG_RX_GOING: Register bit CFG_STAT.RACTIVE. CAN bus is receiving. + * @arg CAN_FLAG_RX_BUF_OVF: Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one data is lost. + * @arg CAN_FLAG_TX_BUF_FULL: Register bit RTIE.TSFF. Transmit buffers are all full: + * TTCFG.TTEN == 0 or TCTRL.TTTEM == 0: ALL STB slots are filled. + * TTCFG.TTEN == 1 and TCTRL.TTTEM == 1: Transmit buffer that pointed by TBSLOT.TBPTR is filled. + * @arg CAN_FLAG_TX_ABORTED: Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled. + * @arg CAN_FLAG_ERR_INT: Register bit RTIF.EIF. The CFG_STAT.BUSOFF bit changes, or the relative relationship between the value of the error counter and the + * set value of the ERROR warning limit changes. For example, the value of the error counter changes from less than + * the set value to greater than the set value, or from greater than the set value to less than the set value. + * @arg CAN_FLAG_STB_TX: Register bit RTIF.TSIF. STB was transmitted successfully. + * @arg CAN_FLAG_PTB_TX: Register bit RTIF.TPIF. PTB was transmitted successfully. + * @arg CAN_FLAG_RX_BUF_WARN: Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. + * @arg CAN_FLAG_RX_BUF_FULL: Register bit RTIF.RFIF. The FIFO of receive buffer is full. + * @arg CAN_FLAG_RX_OVERRUN: Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored. + * @arg CAN_FLAG_RX: Register bit RTIF.RIF. Received a valid data frame or remote frame. + * @arg CAN_FLAG_BUS_ERR: Register bit ERRINT.BEIF. In case of an error, KOER and the error counters get updated. BEIF gets set if BEIE is enabled + * and the other error interrupt flags will act accordingly. + * @arg CAN_FLAG_ARBITR_LOST: Register bit ERRINT.ALIF. Arbitration lost. + * @arg CAN_FLAG_ERR_PASSIVE: Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred. + * @arg CAN_FLAG_ERR_PASSIVE_NODE: Register bit ERRINT.EPASS. The node is an error-passive node. + * @arg CAN_FLAG_TEC_REC_WARN: Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CAN_GetStatus(const CM_CAN_TypeDef *CANx, uint32_t u32Flag) +{ + uint8_t u8CFGSTAT; + uint8_t u8RCTRL; + uint8_t u8RTIE; + uint8_t u8RTIF; + uint8_t u8ERRINT; + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_FLAG(u32Flag)); + + u8CFGSTAT = (uint8_t)(u32Flag & 0x7UL); + u8RCTRL = (uint8_t)(u32Flag & CAN_FLAG_RX_BUF_OVF); + u8RTIE = (uint8_t)(u32Flag >> 8U); + u8RTIF = (uint8_t)(u32Flag >> 16U); + u8ERRINT = (uint8_t)(u32Flag >> 24U); + + u8CFGSTAT = READ_REG8_BIT(CANx->CFG_STAT, u8CFGSTAT); + u8RCTRL = READ_REG8_BIT(CANx->RCTRL, u8RCTRL); + u8RTIE = READ_REG8_BIT(CANx->RTIE, u8RTIE); + u8RTIF = READ_REG8_BIT(CANx->RTIF, u8RTIF); + u8ERRINT = READ_REG8_BIT(CANx->ERRINT, u8ERRINT); + + if ((u8CFGSTAT != 0U) || (u8RCTRL != 0U) || \ + (u8RTIE != 0U) || (u8RTIF != 0U) || (u8ERRINT != 0U)) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of specified flags. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u32Flag CAN status flag. + * This parameter can be values of @ref CAN_Status_Flag + * @arg CAN_FLAG_TX_ABORTED: Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled. + * @arg CAN_FLAG_ERR_INT: Register bit RTIF.EIF. The CFG_STAT.BUSOFF bit changes, or the relative relationship between the value of the error counter + * and the set value of the ERROR warning limit changes. For example, the value of the error counter changes from less than + * the set value to greater than the set value, or from greater than the set value to less than the set value. + * @arg CAN_FLAG_STB_TX: Register bit RTIF.TSIF. STB was transmitted successfully. + * @arg CAN_FLAG_PTB_TX: Register bit RTIF.TPIF. PTB was transmitted successfully. + * @arg CAN_FLAG_RX_BUF_WARN: Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. + * @arg CAN_FLAG_RX_BUF_FULL: Register bit RTIF.RFIF. The FIFO of receive buffer is full. + * @arg CAN_FLAG_RX_OVERRUN: Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored. + * @arg CAN_FLAG_RX: Register bit RTIF.RIF. Received a valid data frame or remote frame. + * @arg CAN_FLAG_BUS_ERR: Register bit ERRINT.BEIF. In case of an error, KOER and the error counters get updated. BEIF gets set if BEIE is enabled + * and the other error interrupt flags will act accordingly. + * @arg CAN_FLAG_ARBITR_LOST: Register bit ERRINT.ALIF. Arbitration lost. + * @arg CAN_FLAG_ERR_PASSIVE: Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred. + * @arg CAN_FLAG_ERR_PASSIVE_NODE: Register bit ERRINT.EPASS. The node is an error-passive node. + * @arg CAN_FLAG_TEC_REC_WARN: Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value. + * @retval None + */ +void CAN_ClearStatus(CM_CAN_TypeDef *CANx, uint32_t u32Flag) +{ + uint8_t u8RTIF; + uint8_t u8ERRINT; + uint8_t u8Reg; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_FLAG(u32Flag)); + + u32Flag &= CAN_FLAG_CLR_ALL; + u8RTIF = (uint8_t)(u32Flag >> 16U); + u8ERRINT = (uint8_t)(u32Flag >> 24U); + + WRITE_REG8(CANx->RTIF, u8RTIF); + + u8Reg = READ_REG8(CANx->ERRINT); + u8Reg &= (uint8_t)(~CAN_ERRINT_FLAG_MASK); + u8Reg |= u8ERRINT; + WRITE_REG8(CANx->ERRINT, u8Reg); +} + +/** + * @brief Get the value of CAN status. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @retval An uint32_t type value that includes the flowing status flags. + * - CAN_FLAG_BUS_OFF: Register bit CFG_STAT.BUSOFF. CAN bus off. + * - CAN_FLAG_TX_GOING: Register bit CFG_STAT.TACTIVE. CAN bus is transmitting. + * - CAN_FLAG_RX_GOING: Register bit CFG_STAT.RACTIVE. CAN bus is receiving. + * - CAN_FLAG_RX_BUF_OVF: Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one data is lost. + * - CAN_FLAG_TX_BUF_FULL: Register bit RTIE.TSFF. Transmit buffers are all full: + * TTCFG.TTEN == 0 or TCTRL.TTTEM == 0: ALL STB slots are filled. + * TTCFG.TTEN == 1 and TCTRL.TTTEM == 1: Transmit buffer that pointed by TBSLOT.TBPTR is filled. + * - CAN_FLAG_TX_ABORTED: Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled. + * - CAN_FLAG_ERR_INT: Register bit RTIF.EIF. The CFG_STAT.BUSOFF bit changes, or the relative relationship between the value of the error counter and the + * set value of the ERROR warning limit changes. For example, the value of the error counter changes from less than + * the set value to greater than the set value, or from greater than the set value to less than the set value. + * - CAN_FLAG_STB_TX: Register bit RTIF.TSIF. STB was transmitted successfully. + * - CAN_FLAG_PTB_TX: Register bit RTIF.TPIF. PTB was transmitted successfully. + * - CAN_FLAG_RX_BUF_WARN: Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. + * - CAN_FLAG_RX_BUF_FULL: Register bit RTIF.RFIF. The FIFO of receive buffer is full. + * - CAN_FLAG_RX_OVERRUN: Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored. + * - CAN_FLAG_RX: Register bit RTIF.RIF. Received a valid data frame or remote frame. + * - CAN_FLAG_BUS_ERR: Register bit ERRINT.BEIF. In case of an error, KOER and the error counters get updated. BEIF gets set if BEIE is enabled + * and the other error interrupt flags will act accordingly. + * - CAN_FLAG_ARBITR_LOST: Register bit ERRINT.ALIF. Arbitration lost. + * - CAN_FLAG_ERR_PASSIVE: Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred. + * - CAN_FLAG_ERR_PASSIVE_NODE: Register bit ERRINT.EPASS. The node is an error-passive node. + * - CAN_FLAG_TEC_REC_WARN: Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value. + */ +uint32_t CAN_GetStatusValue(const CM_CAN_TypeDef *CANx) +{ + uint32_t u32RCTRL; + uint32_t u32RTIE; + uint32_t u32RTIF; + uint32_t u32ERRINT; + uint32_t u32RetVal; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + u32RetVal = CANx->CFG_STAT; + u32RCTRL = CANx->RCTRL; + u32RCTRL &= CAN_FLAG_RX_BUF_OVF; + u32RTIE = CANx->RTIE; + u32RTIF = CANx->RTIF; + u32ERRINT = CANx->ERRINT; + + u32RetVal |= (u32RCTRL | (u32RTIE << 8U) | (u32RTIF << 16U) | (u32ERRINT << 24U)); + u32RetVal &= CAN_FLAG_ALL; + + return u32RetVal; +} + +/** + * @brief Get the information of CAN errors. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [out] pstcErr Pointer to a @ref stc_can_error_info_t structure. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcErr == NULL. + */ +int32_t CAN_GetErrorInfo(const CM_CAN_TypeDef *CANx, stc_can_error_info_t *pstcErr) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + if (pstcErr != NULL) { + pstcErr->u8ArbitrLostPos = READ_REG8_BIT(CANx->EALCAP, CAN_EALCAP_ALC); + pstcErr->u8ErrorType = READ_REG8_BIT(CANx->EALCAP, CAN_EALCAP_KOER) >> CAN_EALCAP_KOER_POS; + pstcErr->u8RxErrorCount = READ_REG8(CANx->RECNT); + pstcErr->u8TxErrorCount = READ_REG8(CANx->TECNT); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Get status(full or empty) of transmit buffer. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @retval An uint8_t type value of status of transmit buffer. It can be a value of @ref CAN_Tx_Buf_Status + * - CAN_TX_BUF_EMPTY: TTCAN is disabled(TTEN == 0): STB is empty. + * TTCAN is disabled(TTEN == 1) and transmit buffer is specified by TBPTR and TTPTR(TTTBM == 1): + * PTB and STB are both empty. + * - CAN_TX_BUF_NOT_MORE_THAN_HALF: TTEN == 0: STB is not less than half full; + * TTEN == 1 && TTTBM == 1: PTB and STB are neither empty. + * - CAN_TX_BUF_MORE_THAN_HALF: TTEN == 0: STB is more than half full; + * TTEN == 1 && TTTBM == 1: reserved value. + * - CAN_TX_BUF_FULL: TTEN == 0: STB is full; + * TTEN == 1 && TTTBM == 1: PTB and STB are both full. + */ +uint8_t CAN_GetTxBufStatus(const CM_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return (READ_REG8_BIT(CANx->TCTRL, CAN_TCTRL_TSSTAT)); +} + +/** + * @brief Get status(full or empty) of receive buffer. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @retval An uint8_t type value of status of receive buffer. It can be a value of @ref CAN_Rx_Buf_Status + * - CAN_RX_BUF_EMPTY: Receive buffer is empty. + * - CAN_RX_BUF_NOT_WARN: Receive buffer is not empty, but is less than almost full warning limit. + * - CAN_RX_BUF_WARN: Receive buffer is not full, but is more than or equal to almost full warning limit. + * - CAN_RX_BUF_FULL: Receive buffer is full. + */ +uint8_t CAN_GetRxBufStatus(const CM_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return (READ_REG8_BIT(CANx->RCTRL, CAN_RCTRL_RSTAT)); +} + +/** + * @brief Enable or disable the specified acceptance filters. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u16FilterSelect Acceptance filters selection. + * This parameter can be values of @ref CAN_Acceptance_Filter + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CAN_FilterCmd(CM_CAN_TypeDef *CANx, uint16_t u16FilterSelect, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_FILTER(u16FilterSelect)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG8_BIT(CANx->ACFEN, u16FilterSelect); + } else { + CLR_REG8_BIT(CANx->ACFEN, u16FilterSelect); + } +} + +/** + * @brief Set receive buffer full warning limit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8RxWarnLimit: Receive buffer full warning limit. + * When the number of received frames reaches the value specified by + * parameter 'u8RxWarnLimit', register bit RTIF.RAFIF set and the + * interrupt occurred if it was enabled. + * @retval None + */ +void CAN_SetRxWarnLimit(CM_CAN_TypeDef *CANx, uint8_t u8RxWarnLimit) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_RX_WARN(u8RxWarnLimit)); + MODIFY_REG8(CANx->LIMIT, CAN_LIMIT_AFWL, u8RxWarnLimit << CAN_LIMIT_AFWL_POS); +} + +/** + * @brief Set error warning limit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8ErrorWarnLimit Programmable error warning limit. Range is [0, 15]. + * Error warning limit = (u8ErrorWarnLimit + 1) * 8. + * @retval None + */ +void CAN_SetErrorWarnLimit(CM_CAN_TypeDef *CANx, uint8_t u8ErrorWarnLimit) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_ERR_WARN(u8ErrorWarnLimit)); + MODIFY_REG8(CANx->LIMIT, CAN_LIMIT_EWL, u8ErrorWarnLimit); +} + +/** + * @brief Set each @ref stc_can_ttc_config_t field to a default value. + * @param [in] pstcCanTtc Pointer to a @ref stc_can_ttc_config_t structure value that + * contains the configuration information for TTCAN. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcCanTtc == NULL. + */ +int32_t CAN_TTC_StructInit(stc_can_ttc_config_t *pstcCanTtc) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcCanTtc != NULL) { + pstcCanTtc->u8NTUPrescaler = CAN_TTC_NTU_PRESCALER1; + pstcCanTtc->u32RefMsgID = 0x0UL; + pstcCanTtc->u32RefMsgIDE = 0U; + pstcCanTtc->u8TxBufMode = CAN_TTC_TX_BUF_MD_TTCAN; + pstcCanTtc->u16TriggerType = CAN_TTC_TRIG_SINGLESHOT_TX_TRIG; + pstcCanTtc->u16TxEnableWindow = 16U; + pstcCanTtc->u16TxTriggerTime = 0xFFFFU; + pstcCanTtc->u16WatchTriggerTime = 0xFFFFU; + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Configures the specified TTCAN according to the specified parameters + * in @ref stc_can_ttc_config_t type structure. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] pstcCanTtc Pointer to a @ref stc_can_ttc_config_t structure value that + * contains the configuration information for TTCAN. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcCanTtc == NULL. + */ +int32_t CAN_TTC_Config(CM_CAN_TypeDef *CANx, const stc_can_ttc_config_t *pstcCanTtc) +{ + uint32_t u32RefMsgID; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + if (pstcCanTtc != NULL) { + DDL_ASSERT(IS_TTCAN_TX_BUF_MD(pstcCanTtc->u8TxBufMode)); + DDL_ASSERT(IS_TTCAN_NTU_PRESCALER(pstcCanTtc->u8NTUPrescaler)); + DDL_ASSERT(IS_CAN_ID(pstcCanTtc->u32RefMsgIDE, pstcCanTtc->u32RefMsgID)); + DDL_ASSERT(IS_TTCAN_TRIG_TYPE(pstcCanTtc->u16TriggerType)); + DDL_ASSERT(IS_TTCAN_TX_EN_WINDOW(pstcCanTtc->u16TxEnableWindow)); + + u32RefMsgID = pstcCanTtc->u32RefMsgID & ((uint32_t)(~CAN_REF_MSG_REF_IDE)); + /* Specifies transmission buffer mode. */ + MODIFY_REG8(CANx->TCTRL, CAN_TCTRL_TTTBM, pstcCanTtc->u8TxBufMode); + /* Specifies Tx_Enable window and trigger type. */ + WRITE_REG16(CANx->TRG_CFG, pstcCanTtc->u16TriggerType | + ((pstcCanTtc->u16TxEnableWindow - 1U) << CAN_TRG_CFG_TEW_POS)); + /* Specifies ID of reference message and its extension bit. */ + WRITE_REG32(CANx->REF_MSG, (((pstcCanTtc->u32RefMsgIDE << CAN_REF_MSG_REF_IDE_POS) | u32RefMsgID))); + /* Specifies transmission trigger time. */ + WRITE_REG16(CANx->TT_TRIG, pstcCanTtc->u16TxTriggerTime); + /* Specifies watch trigger time. */ + WRITE_REG16(CANx->TT_WTRIG, pstcCanTtc->u16WatchTriggerTime); + /* Specifies NTU prescaler. */ + MODIFY_REG8(CANx->TTCFG, CAN_TTCFG_T_PRESC, pstcCanTtc->u8NTUPrescaler); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Enable or disable the specified interrupts of TTCAN. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8IntType Interrupt of TTCAN. + * This parameter can be values of @ref TTCAN_Interrupt_Type + * @arg CAN_TTC_INT_TIME_TRIG: Time trigger interrupt. + * @arg CAN_TTC_INT_WATCH_TRIG: Watch trigger interrupt. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CAN_TTC_IntCmd(CM_CAN_TypeDef *CANx, uint8_t u8IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_TTCAN_INT(u8IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG8_BIT(CANx->TTCFG, u8IntType); + } else { + CLR_REG8_BIT(CANx->TTCFG, u8IntType); + } +} + +/** + * @brief Enable or disable TTCAN of the specified CAN unit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call this function when CFG_STAT.RESET is 0. + */ +void CAN_TTC_Cmd(CM_CAN_TypeDef *CANx, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Addr = (uint32_t)&CANx->TTCFG; + WRITE_REG32(PERIPH_BIT_BAND(u32Addr, CAN_TTCFG_TTEN_POS), enNewState); +} + +/** + * @brief Get status of the specified TTCAN flag. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8Flag Status flag of TTCAN. + * This parameter can be values of @ref TTCAN_Status_Flag + * @arg CAN_TTC_FLAG_TIME_TRIG: Time trigger interrupt flag. + * @arg CAN_TTC_FLAG_TRIG_ERR: Trigger error interrupt flag. + * @arg CAN_TTC_FLAG_WATCH_TRIG: Watch trigger interrupt flag. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CAN_TTC_GetStatus(const CM_CAN_TypeDef *CANx, uint8_t u8Flag) +{ + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_TTCAN_FLAG(u8Flag)); + + if (READ_REG8_BIT(CANx->TTCFG, (u8Flag & CAN_TTC_FLAG_ALL)) != 0U) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of TTCAN flags. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8Flag Status flag of TTCAN. + * This parameter can be a value of @ref TTCAN_Status_Flag except CAN_TTC_FLAG_TRIG_ERR. + * @arg CAN_TTC_FLAG_TIME_TRIG: Time trigger interrupt flag. + * @arg CAN_TTC_FLAG_WATCH_TRIG: Watch trigger interrupt flag. + * @retval None + */ +void CAN_TTC_ClearStatus(CM_CAN_TypeDef *CANx, uint8_t u8Flag) +{ + uint8_t u8Reg; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_TTCAN_FLAG(u8Flag)); + + u8Reg = READ_REG8(CANx->TTCFG); + u8Reg &= (uint8_t)(~CAN_TTC_FLAG_ALL); + u8Reg |= u8Flag; + WRITE_REG8(CANx->TTCFG, u8Reg); +} + +/** + * @brief Get the status value of TTCAN. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @retval An uint8_t type value that includes the flowing status flags. + * - CAN_TTC_FLAG_TIME_TRIG: Time trigger interrupt flag. + * - CAN_TTC_FLAG_TRIG_ERR: Trigger error interrupt flag. + * - CAN_TTC_FLAG_WATCH_TRIG: Watch trigger interrupt flag. + */ +uint8_t CAN_TTC_GetStatusValue(const CM_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return READ_REG8_BIT(CANx->TTCFG, CAN_TTC_FLAG_ALL); +} + +/** + * @brief Specifies trigger type of TTCAN. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u16TriggerType TTCAN trigger type. + * This parameter can be a value of @ref TTCAN_Trigger_Type + * @arg CAN_TTC_TRIG_IMMED_TRIG: Immediate trigger for immediate transmission. + * @arg CAN_TTC_TRIG_TIME_TRIG: Time trigger for receive triggers. + * @arg CAN_TTC_TRIG_SINGLESHOT_TX_TRIG: Single shot transmit trigger for exclusive time windows. + * @arg CAN_TTC_TRIG_TX_START_TRIG: Transmit start trigger for merged arbitrating time windows. + * @arg CAN_TTC_TRIG_TX_STOP_TRIG: Transmit stop trigger for merged arbitrating time windows. + * @retval None + */ +void CAN_TTC_SetTriggerType(CM_CAN_TypeDef *CANx, uint16_t u16TriggerType) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_TTCAN_TRIG_TYPE(u16TriggerType)); + MODIFY_REG16(CANx->TRG_CFG, CAN_TRG_CFG_TTYPE, u16TriggerType); +} + +/** + * @brief Specifies transmit enable window time of TTCAN. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u16TxEnableWindow Number of NTU. Time period within which the transmit of a message may be started. + * @retval None + */ +void CAN_TTC_SetTxEnableWindow(CM_CAN_TypeDef *CANx, uint16_t u16TxEnableWindow) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_TTCAN_TX_EN_WINDOW(u16TxEnableWindow)); + MODIFY_REG16(CANx->TRG_CFG, CAN_TRG_CFG_TEW, (u16TxEnableWindow - 1U) << CAN_TRG_CFG_TEW_POS); +} + +/** + * @brief Specifies transmit trigger time of TTCAN. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u16TxTriggerTime Transmit trigger time(number of NTU). + * @retval None + */ +void CAN_TTC_SetTxTriggerTime(CM_CAN_TypeDef *CANx, uint16_t u16TxTriggerTime) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + WRITE_REG16(CANx->TT_TRIG, u16TxTriggerTime); +} + +/** + * @brief TTCAN specifies watch-trigger time. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u16WatchTriggerTime Watch trigger time(number of NTU). + * @retval None + */ +void CAN_TTC_SetWatchTriggerTime(CM_CAN_TypeDef *CANx, uint16_t u16WatchTriggerTime) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + WRITE_REG16(CANx->TT_WTRIG, u16WatchTriggerTime); +} + +/** + * @brief TTCAN fill transmit frame. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8CANTTCTxBuf TTCAN transmit buffer selection. + * This parameter can be a value of @ref TTCAN_Tx_Buf_Sel + * @param [in] pstcTx Pointer to a @ref stc_can_tx_frame_t structure. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcTx == NULL. + * - LL_ERR_BUF_FULL: The target transmit buffer is full. + */ +int32_t CAN_TTC_FillTxFrame(CM_CAN_TypeDef *CANx, uint8_t u8CANTTCTxBuf, const stc_can_tx_frame_t *pstcTx) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_TTCAN_TX_BUF_SEL(u8CANTTCTxBuf)); + + if (pstcTx != NULL) { + DDL_ASSERT(IS_CAN20_FDF(pstcTx->FDF)); + + if (READ_REG8_BIT(CANx->TCTRL, CAN_TX_BUF_FULL) == CAN_TX_BUF_FULL) { + i32Ret = LL_ERR_BUF_FULL; + } else { + WRITE_REG8(CANx->TBSLOT, u8CANTTCTxBuf); + MODIFY_REG16(CANx->TRG_CFG, CAN_TRG_CFG_TTPTR, u8CANTTCTxBuf); + CAN_WriteTxBuf(CANx, pstcTx); + + /* Set buffer as filled. */ + SET_REG8_BIT(CANx->TBSLOT, CAN_TBSLOT_TBF); + + /* Write MSB of TT_TRIG to transmit. */ + WRITE_REG16(CANx->TT_TRIG, CANx->TT_TRIG); + + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Get the configuration of TTCAN. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [out] pstcCanTtc Pointer to a @ref stc_can_ttc_config_t structure. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcCanTtc == NULL. + */ +int32_t CAN_TTC_GetConfig(const CM_CAN_TypeDef *CANx, stc_can_ttc_config_t *pstcCanTtc) +{ + uint32_t u32Tmp; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcCanTtc != NULL) { + u32Tmp = READ_REG32(CANx->REF_MSG); + pstcCanTtc->u8TxBufMode = READ_REG8_BIT(CANx->TCTRL, CAN_TCTRL_TTTBM); + pstcCanTtc->u8NTUPrescaler = READ_REG8_BIT(CANx->TTCFG, CAN_TTCFG_T_PRESC); + pstcCanTtc->u32RefMsgIDE = (u32Tmp >> CAN_REF_MSG_REF_IDE_POS) & 0x1UL; + pstcCanTtc->u32RefMsgID = u32Tmp & 0x7FFFFFFFUL; + pstcCanTtc->u16TriggerType = READ_REG16_BIT(CANx->TRG_CFG, CAN_TRG_CFG_TTYPE); + pstcCanTtc->u16TxEnableWindow = (READ_REG16_BIT(CANx->TRG_CFG, CAN_TRG_CFG_TEW) >> CAN_TRG_CFG_TEW_POS) + 1U; + pstcCanTtc->u16TxTriggerTime = READ_REG16(CANx->TT_TRIG); + pstcCanTtc->u16WatchTriggerTime = READ_REG16(CANx->TT_WTRIG); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_CAN_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_clk.c b/mcu/lib/src/hc32_ll_clk.c new file mode 100644 index 0000000..1d7fd99 --- /dev/null +++ b/mcu/lib/src/hc32_ll_clk.c @@ -0,0 +1,1671 @@ +/** + ******************************************************************************* + * @file hc32_ll_clk.c + * @brief This file provides firmware functions to manage the Clock(CLK). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-10-31 CDT Fixed bug# GetClockFreq() API xtal32 value + 2023-01-15 CDT Optimize API CLK_SetCANClockSrc(), add assert IS_PWC_UNLOCKED() + Modify CLK_PLL_FREQ_MAX value, remove redundant code + 2023-06-30 CDT Modify FCG0 default value + Modify typo + Modify CLK_SetUSBClockSrc(), add delay after configure USB clock + 2023-09-30 CDT Modify API CLK_Xtal32Cmd(), CLK_MrcCmd() and CLK_LrcCmd(), use DDL_DelayUS() to replace CLK_Delay() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_clk.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_CLK CLK + * @brief Clock Driver Library + * @{ + */ + +#if (LL_CLK_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CLK_Local_Macros CLK Local Macros + * @{ + */ + +/** + * @brief CLK_FREQ Clock frequency definition + */ +#define CLK_FREQ_48M (48UL*1000UL*1000UL) +#define CLK_FREQ_64M (64UL*1000UL*1000UL) +#define CLK_FREQ_32M (32UL*1000UL*1000UL) + +/** + * @brief Be able to modify TIMEOUT according to board condition. + */ +#define CLK_TIMEOUT ((uint32_t)0x1000UL) +#define CLK_LRC_TIMEOUT (160U) +#define CLK_MRC_TIMEOUT (1U) +#define CLK_XTAL32_TIMEOUT (160U) + +/** + * @brief LRC State ON or OFF + */ +#define CLK_LRC_OFF (CMU_LRCCR_LRCSTP) +#define CLK_LRC_ON (0x00U) + +/** + * @brief MRC State ON or OFF + */ +#define CLK_MRC_OFF (CMU_MRCCR_MRCSTP) +#define CLK_MRC_ON (0x80U) + +/** + * @brief Clk PLL Relevant Parameter Range Definition + */ +#define CLK_PLLP_DEFAULT (0x01UL) +#define CLK_PLLQ_DEFAULT (0x01UL) +#define CLK_PLLR_DEFAULT (0x01UL) +#define CLK_PLLN_DEFAULT (0x13UL) +#define CLK_PLLM_DEFAULT (0x00UL) + +#define CLK_PLLR_DIV_MIN (2UL) +#define CLK_PLLR_DIV_MAX (16UL) +#define CLK_PLLQ_DIV_MIN (2UL) +#define CLK_PLLQ_DIV_MAX (16UL) +#define CLK_PLLP_DIV_MIN (2UL) +#define CLK_PLLP_DIV_MAX (16UL) + +#define CLK_PLLX_FREQ_MIN (15UL*1000UL*1000UL) +#define CLK_PLLX_VCO_IN_MIN (1UL*1000UL*1000UL) +#define CLK_PLLX_VCO_IN_MAX (25UL*1000UL*1000UL) +#define CLK_PLLX_VCO_OUT_MIN (240UL*1000UL*1000UL) +#define CLK_PLLX_VCO_OUT_MAX (480UL*1000UL*1000UL) +#define CLK_PLLXM_DIV_MIN (2UL) +#define CLK_PLLXM_DIV_MAX (24UL) +#define CLK_PLLXN_MULTI_MIN (20UL) +#define CLK_PLLXN_MULTI_MAX (480UL) +#define CLK_PLLXR_DIV_MIN (2UL) +#define CLK_PLLXR_DIV_MAX (16UL) +#define CLK_PLLXQ_DIV_MIN (2UL) +#define CLK_PLLXQ_DIV_MAX (16UL) +#define CLK_PLLXP_DIV_MIN (2UL) +#define CLK_PLLXP_DIV_MAX (16UL) +#define CLK_PLLXP_DEFAULT (0x01UL) +#define CLK_PLLXQ_DEFAULT (0x01UL) +#define CLK_PLLXR_DEFAULT (0x01UL) +#define CLK_PLLXN_DEFAULT (0x13UL) +#define CLK_PLLXM_DEFAULT (0x00UL) + +#define CLK_PLL_FREQ_MIN (15UL*1000UL*1000UL) +#define CLK_PLL_VCO_IN_MIN (1UL*1000UL*1000UL) +#define CLK_PLL_VCO_IN_MAX (25UL*1000UL*1000UL) +#define CLK_PLL_VCO_OUT_MIN (240UL*1000UL*1000UL) +#define CLK_PLL_VCO_OUT_MAX (480UL*1000UL*1000UL) +#define CLK_PLLM_DIV_MIN (1UL) +#define CLK_PLLM_DIV_MAX (24UL) +#define CLK_PLLN_MULTI_MIN (20UL) +#define CLK_PLLN_MULTI_MAX (480UL) +#define CLK_PLLX_FREQ_MAX (200UL*1000UL*1000UL) +#define CLK_PLL_FREQ_MAX (200UL*1000UL*1000UL) + +/** + * @brief Clk PLL Register Redefinition + */ +#define PLL_SRC_REG (CM_CMU->PLLCFGR) +#define PLL_SRC_BIT (CMU_PLLCFGR_PLLSRC) +#define PLL_SRC_POS (CMU_PLLCFGR_PLLSRC_POS) +#define PLL_SRC ((CM_CMU->PLLCFGR & CMU_PLLCFGR_PLLSRC) >> CMU_PLLCFGR_PLLSRC_POS) +#define PLL_EN_REG (CM_CMU->PLLCR) +#define PLLX_EN_REG (CM_CMU->UPLLCR) + +/** + * @brief Switch clock stable time + * @note Approx. 30us + */ +#define CLK_SYSCLK_SW_STB (30U) + +/** + * @brief Clk FCG Default Value + */ +#define CLK_FCG0_DEFAULT (0xFFFFFAEEUL) +#define CLK_FCG1_DEFAULT (0xFFFFFFFFUL) +#define CLK_FCG2_DEFAULT (0xFFFFFFFFUL) +#define CLK_FCG3_DEFAULT (0xFFFFFFFFUL) + +/** + * @defgroup CLK_Check_Parameters_Validity CLK Check Parameters Validity + * @{ + */ +/* Check CLK register lock status. */ +#define IS_CLK_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB0) == PWC_FPRC_FPRCB0) +#define IS_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1) + +/* Parameter valid check for XTAL state */ +#define IS_CLK_XTAL_STATE(x) \ +( ((x) == CLK_XTAL_OFF) || \ + ((x) == CLK_XTAL_ON)) + +/* Parameter valid check for XTAL mode */ +#define IS_CLK_XTAL_MD(x) \ +( ((x) == CLK_XTAL_MD_OSC) || \ + ((x) == CLK_XTAL_MD_EXCLK)) + +/* Parameter valid check for XTAL super drive state */ +#define IS_CLK_XTAL_SUPDRV_STATE(x) \ +( ((x) == CLK_XTAL_SUPDRV_ON) || \ + ((x) == CLK_XTAL_SUPDRV_OFF)) + +/* Parameter valid check for XTAL driver ability mode */ +#define IS_CLK_XTAL_DRV_MD(x) \ +( ((x) == CLK_XTAL_DRV_HIGH) || \ + ((x) == CLK_XTAL_DRV_MID) || \ + ((x) == CLK_XTAL_DRV_LOW) || \ + ((x) == CLK_XTAL_DRV_ULOW)) + +/* Parameter valid check for XTAL stable time selection */ +#define IS_CLK_XTAL_STB_SEL(x) \ +( ((x) == CLK_XTAL_STB_133US) || \ + ((x) == CLK_XTAL_STB_255US) || \ + ((x) == CLK_XTAL_STB_499US) || \ + ((x) == CLK_XTAL_STB_988US) || \ + ((x) == CLK_XTAL_STB_2MS) || \ + ((x) == CLK_XTAL_STB_4MS) || \ + ((x) == CLK_XTAL_STB_8MS) || \ + ((x) == CLK_XTAL_STB_16MS) || \ + ((x) == CLK_XTAL_STB_31MS)) + +/* Parameter valid check for XTALSTD state */ +#define IS_CLK_XTALSTD_STATE(x) \ +( ((x) == CLK_XTALSTD_OFF) || \ + ((x) == CLK_XTALSTD_ON)) + +/* Parameter valid check for XTALSTD mode */ +#define IS_CLK_XTALSTD_MD(x) \ +( ((x) == CLK_XTALSTD_MD_RST) || \ + ((x) == CLK_XTALSTD_MD_INT)) + +/* Parameter valid check for XTALSTD interrupt state */ +#define IS_CLK_XTALSTD_INT_STATE(x) \ +( ((x) == CLK_XTALSTD_INT_OFF) || \ + ((x) == CLK_XTALSTD_INT_ON)) + +/* Parameter valid check for XTALSTD reset state */ +#define IS_CLK_XTALSTD_RST_STATE(x) \ +( ((x) == CLK_XTALSTD_RST_OFF) || \ + ((x) == CLK_XTALSTD_RST_ON)) + +/* Parameter valid check for PLL state */ +#define IS_CLK_PLL_STATE(x) \ +( ((x) == CLK_PLL_OFF) || \ + ((x) == CLK_PLL_ON)) + +/* Parameter validity check for PLL input source */ +#define IS_CLK_PLL_SRC(x) \ +( ((x) == CLK_PLL_SRC_XTAL) || \ + ((x) == CLK_PLL_SRC_HRC)) + +/* Parameter validity check for PLL frequency range */ +#define IS_CLK_PLL_FREQ(x) \ +( ((x) <= CLK_PLL_FREQ_MAX) && \ + ((x) >= CLK_PLL_FREQ_MIN)) + +/* Parameter validity check for PLL M divide */ +#define IS_CLK_PLLM_DIV(x) \ +( ((x) <= CLK_PLLM_DIV_MAX) && \ + ((x) >= CLK_PLLM_DIV_MIN)) + +/* Parameter validity check for PLL N multi- */ +#define IS_CLK_PLLN_MULTI(x) \ +( ((x) <= CLK_PLLN_MULTI_MAX) && \ + ((x) >= CLK_PLLN_MULTI_MIN)) + +/* Parameter validity check for PLL P divide */ +#define IS_CLK_PLLP_DIV(x) \ +( ((x) <= CLK_PLLP_DIV_MAX) && \ + ((x) >= CLK_PLLP_DIV_MIN)) + +/* Parameter validity check for PLL_input freq./PLLM(vco_in) */ +#define IS_CLK_PLL_VCO_IN(x) \ +( ((x) <= CLK_PLL_VCO_IN_MAX) && \ + ((x) >= CLK_PLL_VCO_IN_MIN)) + +/* Parameter validity check for PLL vco_in*PLLN(vco_out) */ +#define IS_CLK_PLL_VCO_OUT(x) \ +( ((x) <= CLK_PLL_VCO_OUT_MAX) && \ + ((x) >= CLK_PLL_VCO_OUT_MIN)) + +/* Parameter validity check for PLL R divide */ +#define IS_CLK_PLLR_DIV(x) \ +( ((x) <= CLK_PLLR_DIV_MAX) && \ + ((x) >= CLK_PLLR_DIV_MIN)) + +/* Parameter validity check for PLL Q divide */ +#define IS_CLK_PLLQ_DIV(x) \ +( ((x) <= CLK_PLLQ_DIV_MAX) && \ + ((x) >= CLK_PLLQ_DIV_MIN)) + +/* Parameter valid check for PLLX state */ +#define IS_CLK_PLLX_STATE(x) \ +( ((x) == CLK_PLLX_OFF) || \ + ((x) == CLK_PLLX_ON)) + +/* Parameter validity check for PLLX frequency range */ +#define IS_CLK_PLLX_FREQ(x) \ +( (CLK_PLLX_FREQ_MIN <= (x)) && \ + (CLK_PLLX_FREQ_MAX >= (x))) + +/* Parameter validity check for PLLX M divide */ +#define IS_CLK_PLLXM_DIV(x) \ +( (CLK_PLLXM_DIV_MIN <= (x)) && \ + (CLK_PLLXM_DIV_MAX >= (x))) + +/* Parameter validity check for PLLX N multi- */ +#define IS_CLK_PLLXN_MULTI(x) \ +( (CLK_PLLXN_MULTI_MIN <= (x)) && \ + (CLK_PLLXN_MULTI_MAX >= (x))) + +/* Parameter validity check for PLLX R divide */ +#define IS_CLK_PLLXR_DIV(x) \ +( (CLK_PLLXR_DIV_MIN <= (x)) && \ + (CLK_PLLXR_DIV_MAX >= (x))) + +/* Parameter validity check for PLLX Q divide */ +#define IS_CLK_PLLXQ_DIV(x) \ +( (CLK_PLLXQ_DIV_MIN <= (x)) && \ + (CLK_PLLXQ_DIV_MAX >= (x))) + +/* Parameter validity check for PLLX P divide */ +#define IS_CLK_PLLXP_DIV(x) \ +( (CLK_PLLXP_DIV_MIN <= (x)) && \ + (CLK_PLLXP_DIV_MAX >= (x))) + +/* Parameter validity check for PLLX_input freq./PLLM(vco_in) */ +#define IS_CLK_PLLX_VCO_IN(x) \ +( (CLK_PLLX_VCO_IN_MIN <= (x)) && \ + (CLK_PLLX_VCO_IN_MAX >= (x))) + +/* Parameter validity check for PLLX vco_in*PLLN(vco_out) */ +#define IS_CLK_PLLX_VCO_OUT(x) \ +( (CLK_PLLX_VCO_OUT_MIN <= (x)) && \ + (CLK_PLLX_VCO_OUT_MAX >= (x))) + +/* Parameter valid check for XTAL32 state */ +#define IS_CLK_XTAL32_STATE(x) \ +( ((x) == CLK_XTAL32_OFF) || \ + ((x) == CLK_XTAL32_ON)) + +/* Parameter valid check for XTAL32 driver ability mode */ +#define IS_CLK_XTAL32_DRV_MD(x) \ +( ((x) == CLK_XTAL32_DRV_MID) || \ + ((x) == CLK_XTAL32_DRV_HIGH)) + +/* Parameter valid check for XTAL32 filtering selection */ +#define IS_CLK_XTAL32_FILT_SEL(x) \ +( ((x) == CLK_XTAL32_FILTER_ALL_MD) || \ + ((x) == CLK_XTAL32_FILTER_RUN_MD) || \ + ((x) == CLK_XTAL32_FILTER_OFF)) + +/* Parameter valid check for system clock source */ +#define IS_CLK_SYSCLK_SRC(x) \ +( ((x) == CLK_SYSCLK_SRC_HRC) || \ + ((x) == CLK_SYSCLK_SRC_MRC) || \ + ((x) == CLK_SYSCLK_SRC_LRC) || \ + ((x) == CLK_SYSCLK_SRC_XTAL) || \ + ((x) == CLK_SYSCLK_SRC_XTAL32) || \ + ((x) == CLK_SYSCLK_SRC_PLL)) + +/* Parameter valid check for CLK stable flag. */ +#define IS_CLK_STB_FLAG(x) \ +( ((x) != 0x00U) && \ + (((x) | CLK_STB_FLAG_MASK) == CLK_STB_FLAG_MASK)) + +/* Parameter valid check for bus clock category */ +#define IS_CLK_BUS_CLK_CATE(x) (((x) & CLK_BUS_CLK_ALL) != (0x00U)) + +/* Parameter valid check for HCLK divider */ +#define IS_CLK_HCLK_DIV(x) \ +( ((x) == CLK_HCLK_DIV1) || \ + ((x) == CLK_HCLK_DIV2) || \ + ((x) == CLK_HCLK_DIV4) || \ + ((x) == CLK_HCLK_DIV8) || \ + ((x) == CLK_HCLK_DIV16) || \ + ((x) == CLK_HCLK_DIV32) || \ + ((x) == CLK_HCLK_DIV64)) + +/* Parameter valid check for PCLK1 divider */ +#define IS_CLK_PCLK1_DIV(x) \ +( ((x) == CLK_PCLK1_DIV1) || \ + ((x) == CLK_PCLK1_DIV2) || \ + ((x) == CLK_PCLK1_DIV4) || \ + ((x) == CLK_PCLK1_DIV8) || \ + ((x) == CLK_PCLK1_DIV16) || \ + ((x) == CLK_PCLK1_DIV32) || \ + ((x) == CLK_PCLK1_DIV64)) + +/* Parameter valid check for PCLK4 divider */ +#define IS_CLK_PCLK4_DIV(x) \ +( ((x) == CLK_PCLK4_DIV1) || \ + ((x) == CLK_PCLK4_DIV2) || \ + ((x) == CLK_PCLK4_DIV4) || \ + ((x) == CLK_PCLK4_DIV8) || \ + ((x) == CLK_PCLK4_DIV16) || \ + ((x) == CLK_PCLK4_DIV32) || \ + ((x) == CLK_PCLK4_DIV64)) + +/* Parameter valid check for PCLK3 divider */ +#define IS_CLK_PCLK3_DIV(x) \ +( ((x) == CLK_PCLK3_DIV1) || \ + ((x) == CLK_PCLK3_DIV2) || \ + ((x) == CLK_PCLK3_DIV4) || \ + ((x) == CLK_PCLK3_DIV8) || \ + ((x) == CLK_PCLK3_DIV16) || \ + ((x) == CLK_PCLK3_DIV32) || \ + ((x) == CLK_PCLK3_DIV64)) + +/* Parameter valid check for EXCLK divider */ +#define IS_CLK_EXCLK_DIV(x) \ +( ((x) == CLK_EXCLK_DIV1) || \ + ((x) == CLK_EXCLK_DIV2) || \ + ((x) == CLK_EXCLK_DIV4) || \ + ((x) == CLK_EXCLK_DIV8) || \ + ((x) == CLK_EXCLK_DIV16) || \ + ((x) == CLK_EXCLK_DIV32) || \ + ((x) == CLK_EXCLK_DIV64)) + +/* Parameter valid check for PCLK0 divider */ +#define IS_CLK_PCLK0_DIV(x) \ +( ((x) == CLK_PCLK0_DIV1) || \ + ((x) == CLK_PCLK0_DIV2) || \ + ((x) == CLK_PCLK0_DIV4) || \ + ((x) == CLK_PCLK0_DIV8) || \ + ((x) == CLK_PCLK0_DIV16) || \ + ((x) == CLK_PCLK0_DIV32) || \ + ((x) == CLK_PCLK0_DIV64)) + +/* Parameter valid check for PCLK2 divider */ +#define IS_CLK_PCLK2_DIV(x) \ +( ((x) == CLK_PCLK2_DIV1) || \ + ((x) == CLK_PCLK2_DIV2) || \ + ((x) == CLK_PCLK2_DIV4) || \ + ((x) == CLK_PCLK2_DIV8) || \ + ((x) == CLK_PCLK2_DIV16) || \ + ((x) == CLK_PCLK2_DIV32) || \ + ((x) == CLK_PCLK2_DIV64)) + +/* Parameter valid check for bus clock */ +#define IS_CLK_BUS_CLK(x) \ +( ((x) == CLK_BUS_HCLK) || \ + ((x) == CLK_BUS_EXCLK) || \ + ((x) == CLK_BUS_PCLK0) || \ + ((x) == CLK_BUS_PCLK1) || \ + ((x) == CLK_BUS_PCLK2) || \ + ((x) == CLK_BUS_PCLK3) || \ + ((x) == CLK_BUS_PCLK4)) + +/* Parameter valid check for USB clock source */ +#define IS_CLK_USBCLK_SRC(x) \ +( ((x) == CLK_USBCLK_SYSCLK_DIV2) || \ + ((x) == CLK_USBCLK_SYSCLK_DIV3) || \ + ((x) == CLK_USBCLK_SYSCLK_DIV4) || \ + ((x) == CLK_USBCLK_PLLP) || \ + ((x) == CLK_USBCLK_PLLQ) || \ + ((x) == CLK_USBCLK_PLLR) || \ + ((x) == CLK_USBCLK_PLLXP) || \ + ((x) == CLK_USBCLK_PLLXQ) || \ + ((x) == CLK_USBCLK_PLLXR)) + +/* Parameter valid check for I2S channel for clock source config */ +#define IS_CLK_I2S_UNIT(x) \ +( ((x) == CLK_I2S1) || \ + ((x) == CLK_I2S2) || \ + ((x) == CLK_I2S3) || \ + ((x) == CLK_I2S4)) + +/* Parameter valid check for peripheral source */ +#define IS_CLK_PERIPHCLK_SRC(x) \ +( ((x) == CLK_PERIPHCLK_PCLK) || \ + ((x) == CLK_PERIPHCLK_PLLP) || \ + ((x) == CLK_PERIPHCLK_PLLQ) || \ + ((x) == CLK_PERIPHCLK_PLLR) || \ + ((x) == CLK_PERIPHCLK_PLLXP) || \ + ((x) == CLK_PERIPHCLK_PLLXQ) || \ + ((x) == CLK_PERIPHCLK_PLLXR)) + +/* Parameter valid check for TPIU clock divider */ +#define IS_CLK_TPIUCLK_DIV(x) \ +( ((x) == CLK_TPIUCLK_DIV1) || \ + ((x) == CLK_TPIUCLK_DIV2) || \ + ((x) == CLK_TPIUCLK_DIV4)) + +/* Parameter valid check for CLK MCO clock source . */ +#define IS_CLK_MCO_SRC(x) \ +( ((x) == CLK_MCO_SRC_HRC) || \ + ((x) == CLK_MCO_SRC_MRC) || \ + ((x) == CLK_MCO_SRC_LRC) || \ + ((x) == CLK_MCO_SRC_XTAL) || \ + ((x) == CLK_MCO_SRC_XTAL32) || \ + ((x) == CLK_MCO_SRC_PLLP) || \ + ((x) == CLK_MCO_SRC_PLLXP) || \ + ((x) == CLK_MCO_SRC_PLLQ) || \ + ((x) == CLK_MCO_SRC_PLLXQ) || \ + ((x) == CLK_MCO_SRC_HCLK)) + +/* Parameter valid check for CLK MCO clock divide. */ +#define IS_CLK_MCO_DIV(x) \ +( ((x) == CLK_MCO_DIV1) || \ + ((x) == CLK_MCO_DIV2) || \ + ((x) == CLK_MCO_DIV4) || \ + ((x) == CLK_MCO_DIV8) || \ + ((x) == CLK_MCO_DIV16) || \ + ((x) == CLK_MCO_DIV32) || \ + ((x) == CLK_MCO_DIV64) || \ + ((x) == CLK_MCO_DIV128)) + +/* Parameter valid check for CLK MCO channel. */ +#define IS_CLK_MCO_CH(x) \ +( ((x) == CLK_MCO1) || \ + ((x) == CLK_MCO2)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup CLK_Local_Functions CLK Local Functions + * @{ + */ +/** + * @brief Wait clock stable flag. + * @param [in] u8Flag Specifies the stable flag to be wait. @ref CLK_STB_Flag + * @param [in] u32Time Specifies the time to wait while the flag not be set. + * @retval int32_t + */ +static int32_t CLK_WaitStable(uint8_t u8Flag, uint32_t u32Time) +{ + __IO uint32_t u32Timeout = 0UL; + int32_t i32Ret = LL_ERR_TIMEOUT; + + while (u32Timeout <= u32Time) { + if (SET == CLK_GetStableStatus(u8Flag)) { + i32Ret = LL_OK; + break; + } + u32Timeout++; + } + return i32Ret; +} + +#ifdef __DEBUG +/** + * @note The pll_input/PLLM (VCOIN) must between 1 ~ 24MHz. + * The VCOIN*PLLN (VCOOUT) is between 240 ~ 480MHz. + * The PLLx frequency (VCOOUT/PLLxP_Q_R) is between 15 ~ 240MHz. +*/ +static void PLLxParamCheck(const stc_clock_pllx_init_t *pstcPLLxInit) +{ + uint32_t vcoIn; + uint32_t vcoOut; + + DDL_ASSERT(IS_CLK_PLLXM_DIV(pstcPLLxInit->PLLCFGR_f.PLLM + 1UL)); + DDL_ASSERT(IS_CLK_PLLXN_MULTI(pstcPLLxInit->PLLCFGR_f.PLLN + 1UL)); + DDL_ASSERT(IS_CLK_PLLXR_DIV(pstcPLLxInit->PLLCFGR_f.PLLR + 1UL)); + DDL_ASSERT(IS_CLK_PLLXQ_DIV(pstcPLLxInit->PLLCFGR_f.PLLQ + 1UL)); + DDL_ASSERT(IS_CLK_PLLXP_DIV(pstcPLLxInit->PLLCFGR_f.PLLP + 1UL)); + + vcoIn = ((CLK_PLL_SRC_XTAL == PLL_SRC ? + XTAL_VALUE : HRC_VALUE) / (pstcPLLxInit->PLLCFGR_f.PLLM + 1UL)); + vcoOut = vcoIn * (pstcPLLxInit->PLLCFGR_f.PLLN + 1UL); + + DDL_ASSERT(IS_CLK_PLLX_VCO_IN(vcoIn)); + DDL_ASSERT(IS_CLK_PLLX_VCO_OUT(vcoOut)); + DDL_ASSERT(IS_CLK_PLLX_FREQ(vcoOut / (pstcPLLxInit->PLLCFGR_f.PLLR + 1UL))); + DDL_ASSERT(IS_CLK_PLLX_FREQ(vcoOut / (pstcPLLxInit->PLLCFGR_f.PLLQ + 1UL))); + DDL_ASSERT(IS_CLK_PLLX_FREQ(vcoOut / (pstcPLLxInit->PLLCFGR_f.PLLP + 1UL))); + DDL_ASSERT(IS_CLK_PLLX_STATE(pstcPLLxInit->u8PLLState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); +} +#endif /* __DEBUG */ + +static void SetSysClockSrc(uint8_t u8Src) +{ + uint8_t u8TmpFlag = 0U; + /* backup FCGx setting */ + __IO uint32_t fcg0 = CM_PWC->FCG0; + __IO uint32_t fcg1 = CM_PWC->FCG1; + __IO uint32_t fcg2 = CM_PWC->FCG2; + __IO uint32_t fcg3 = CM_PWC->FCG3; + + DDL_ASSERT(IS_CLK_SYSCLK_SRC(u8Src)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + /* Only current system clock source or target system clock source is PLLH + need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source. + We need to backup fcg0~fcg3 before close them. */ + if (CLK_SYSCLK_SRC_PLL == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW) || (CLK_SYSCLK_SRC_PLL == u8Src)) { + u8TmpFlag = 1U; + /* FCG0 protect judgment */ + DDL_ASSERT((CM_PWC->FCG0PC & PWC_FCG0PC_PRT0) == PWC_FCG0PC_PRT0); + /* Close FCGx. */ + WRITE_REG32(CM_PWC->FCG0, CLK_FCG0_DEFAULT); + WRITE_REG32(CM_PWC->FCG1, CLK_FCG1_DEFAULT); + WRITE_REG32(CM_PWC->FCG2, CLK_FCG2_DEFAULT); + WRITE_REG32(CM_PWC->FCG3, CLK_FCG3_DEFAULT); + /* Wait stable after close FCGx. */ + DDL_DelayUS(CLK_SYSCLK_SW_STB); + } + /* Set system clock source */ + WRITE_REG8(CM_CMU->CKSWR, u8Src); + /* Wait stable after setting system clock source */ + DDL_DelayUS(CLK_SYSCLK_SW_STB); + if (1U == u8TmpFlag) { + WRITE_REG32(CM_PWC->FCG0, fcg0); + WRITE_REG32(CM_PWC->FCG1, fcg1); + WRITE_REG32(CM_PWC->FCG2, fcg2); + WRITE_REG32(CM_PWC->FCG3, fcg3); + /* Wait stable after open fcg. */ + DDL_DelayUS(CLK_SYSCLK_SW_STB); + } +} + +static void GetClockFreq(stc_clock_freq_t *pstcClockFreq) +{ + stc_clock_scale_t *pstcClockScale; + uint32_t u32HrcValue; + uint8_t plln; + uint8_t pllp; + uint8_t pllm; + + switch (READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + case CLK_SYSCLK_SRC_HRC: + /* HRC is used to system clock */ + pstcClockFreq->u32SysclkFreq = HRC_VALUE; + break; + case CLK_SYSCLK_SRC_MRC: + /* MRC is used to system clock */ + pstcClockFreq->u32SysclkFreq = MRC_VALUE; + break; + case CLK_SYSCLK_SRC_LRC: + /* LRC is used to system clock */ + pstcClockFreq->u32SysclkFreq = LRC_VALUE; + break; + case CLK_SYSCLK_SRC_XTAL: + /* XTAL is used to system clock */ + pstcClockFreq->u32SysclkFreq = XTAL_VALUE; + break; + case CLK_SYSCLK_SRC_XTAL32: + /* XTAL32 is used to system clock */ + pstcClockFreq->u32SysclkFreq = XTAL32_VALUE; + break; + case CLK_SYSCLK_SRC_PLL: + /* PLLHP is used as system clock. */ + pllp = (uint8_t)((CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLP) >> CMU_PLLCFGR_MPLLP_POS); + plln = (uint8_t)((CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLN) >> CMU_PLLCFGR_MPLLN_POS); + pllm = (uint8_t)((CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLM) >> CMU_PLLCFGR_MPLLM_POS); + /* pll = ((pllin / pllm) * plln) / pllp */ + if (CLK_PLL_SRC_XTAL == PLL_SRC) { + pstcClockFreq->u32SysclkFreq = ((XTAL_VALUE / (pllm + 1UL)) * (plln + 1UL)) / (pllp + 1UL); + } else { + u32HrcValue = HRC_VALUE; + pstcClockFreq->u32SysclkFreq = ((u32HrcValue / (pllm + 1UL)) * (plln + 1UL)) / (pllp + 1UL); + } + break; + default: + break; + } + + pstcClockScale = (stc_clock_scale_t *)((uint32_t)&CM_CMU->SCFGR); + pstcClockScale->SCFGR = READ_REG32(CM_CMU->SCFGR); + /* Get hclk. */ + pstcClockFreq->u32HclkFreq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.HCLKS; + /* Get pclk1. */ + pstcClockFreq->u32Pclk1Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK1S; + /* Get pclk4. */ + pstcClockFreq->u32Pclk4Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK4S; + /* Get pclk3. */ + pstcClockFreq->u32Pclk3Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK3S; + /* Get exclk. */ + pstcClockFreq->u32ExclkFreq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.EXCKS; + /* Get pclk0. */ + pstcClockFreq->u32Pclk0Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK0S; + /* Get pclk2. */ + pstcClockFreq->u32Pclk2Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK2S; +} + +static void SetSysClockDiv(uint32_t u32Clock, uint32_t u32Div) +{ + uint8_t u8TmpFlag = 0U; + + /* backup FCGx setting */ + __IO uint32_t fcg0 = CM_PWC->FCG0; + __IO uint32_t fcg1 = CM_PWC->FCG1; + __IO uint32_t fcg2 = CM_PWC->FCG2; + __IO uint32_t fcg3 = CM_PWC->FCG3; + + DDL_ASSERT(IS_CLK_HCLK_DIV(u32Div & CMU_SCFGR_HCLKS)); + DDL_ASSERT(IS_CLK_PCLK1_DIV(u32Div & CMU_SCFGR_PCLK1S)); + DDL_ASSERT(IS_CLK_PCLK4_DIV(u32Div & CMU_SCFGR_PCLK4S)); + DDL_ASSERT(IS_CLK_EXCLK_DIV(u32Div & CMU_SCFGR_EXCKS)); + DDL_ASSERT(IS_CLK_PCLK0_DIV(u32Div & CMU_SCFGR_PCLK0S)); + DDL_ASSERT(IS_CLK_PCLK2_DIV(u32Div & CMU_SCFGR_PCLK2S)); + DDL_ASSERT(IS_CLK_PCLK3_DIV(u32Div & CMU_SCFGR_PCLK3S)); + DDL_ASSERT(IS_CLK_BUS_CLK_CATE(u32Clock)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + /* Only current system clock source or target system clock source is PLLH + need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source. + We need to backup fcg0~fcg3 before close them. */ + if (CLK_SYSCLK_SRC_PLL == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + u8TmpFlag = 1U; + DDL_ASSERT((CM_PWC->FCG0PC & PWC_FCG0PC_PRT0) == PWC_FCG0PC_PRT0); + /* Close FCGx. */ + WRITE_REG32(CM_PWC->FCG0, CLK_FCG0_DEFAULT); + WRITE_REG32(CM_PWC->FCG1, CLK_FCG1_DEFAULT); + WRITE_REG32(CM_PWC->FCG2, CLK_FCG2_DEFAULT); + WRITE_REG32(CM_PWC->FCG3, CLK_FCG3_DEFAULT); + /* Wait stable after close FCGx. */ + DDL_DelayUS(CLK_SYSCLK_SW_STB); + } + MODIFY_REG32(CM_CMU->SCFGR, u32Clock, u32Div); + DDL_DelayUS(CLK_SYSCLK_SW_STB); + if (1U == u8TmpFlag) { + WRITE_REG32(CM_PWC->FCG0, fcg0); + WRITE_REG32(CM_PWC->FCG1, fcg1); + WRITE_REG32(CM_PWC->FCG2, fcg2); + WRITE_REG32(CM_PWC->FCG3, fcg3); + /* Wait stable after open fcg. */ + DDL_DelayUS(CLK_SYSCLK_SW_STB); + } +} + +/** + * @} + */ + +/** + * @defgroup CLK_Global_Functions CLK Global Functions + * @{ + */ +/** + * @brief LRC function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: LRC operate successfully + * - LL_ERR_BUSY: LRC is the system clock, CANNOT stop it. + * @note DO NOT STOP LRC while using it as system clock. + */ +int32_t CLK_LrcCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_LRC == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(CM_CMU->LRCCR, CLK_LRC_OFF); + } + } else { + WRITE_REG8(CM_CMU->LRCCR, CLK_LRC_ON); + } + /* wait approx, 5 * LRC cycle */ + DDL_DelayUS(CLK_LRC_TIMEOUT); + + return i32Ret; +} + +/** + * @brief MRC function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: MRC operate successfully + * - LL_ERR_BUSY: MRC is the system clock, CANNOT stop it. + * @note DO NOT STOP MRC while using it as system clock. + */ +int32_t CLK_MrcCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_MRC == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(CM_CMU->MRCCR, CLK_MRC_OFF); + } + } else { + WRITE_REG8(CM_CMU->MRCCR, CLK_MRC_ON); + } + /* Wait approx. 5 * MRC cycle */ + DDL_DelayUS(CLK_MRC_TIMEOUT); + + return i32Ret; +} + +/** + * @brief HRC function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: HRC operate successfully + * - LL_ERR_BUSY: HRC is the system clock or as the PLL source clock, CANNOT stop it. + * - LL_ERR_TIMEOUT: HRC operate Timeout + * @note DO NOT STOP HRC while using it as system clock or as the PLL source clock. + */ +int32_t CLK_HrcCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_HRC == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else if (CLK_PLL_SRC_HRC == PLL_SRC) { + /* HRC as PLL clock source and PLL is working */ + if (0UL == PLL_EN_REG) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(CM_CMU->HRCCR, CLK_HRC_OFF); + } + } else { + WRITE_REG8(CM_CMU->HRCCR, CLK_HRC_OFF); + } + } else { + WRITE_REG8(CM_CMU->HRCCR, CLK_HRC_ON); + i32Ret = CLK_WaitStable(CLK_STB_FLAG_HRC, CLK_TIMEOUT); + } + + return i32Ret; +} + +/** + * @brief Set HRC trimming value. + * @param [in] i8TrimVal specifies the trimming value for HRC. + * @retval None + */ +void CLK_HrcTrim(int8_t i8TrimVal) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->HRCTRM, i8TrimVal); +} + +/** + * @brief Set MRC trimming value. + * @param [in] i8TrimVal specifies the trimming value for MRC. + * @retval None + */ +void CLK_MrcTrim(int8_t i8TrimVal) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->MRCTRM, i8TrimVal); +} + +/** + * @brief Set LRC trimming value. + * @param [in] i8TrimVal specifies the trimming value for LRC. + * @retval None + */ +void CLK_LrcTrim(int8_t i8TrimVal) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->LRCTRM, i8TrimVal); +} + +/** + * @brief Init Xtal initial structure with default value. + * @param [in] pstcXtalInit specifies the Parameter of XTAL. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t CLK_XtalStructInit(stc_clock_xtal_init_t *pstcXtalInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcXtalInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcXtalInit->u8State = CLK_XTAL_OFF; + pstcXtalInit->u8Mode = CLK_XTAL_MD_OSC; + pstcXtalInit->u8Drv = CLK_XTAL_DRV_HIGH; + pstcXtalInit->u8SuperDrv = CLK_XTAL_SUPDRV_ON; + pstcXtalInit->u8StableTime = CLK_XTAL_STB_2MS; + } + return i32Ret; +} + +/** + * @brief XTAL initialize. + * @param [in] pstcXtalInit specifies the XTAL initial config. + * @retval int32_t: + * - LL_OK: XTAL initial successfully. + * - LL_ERR_TIMEOUT: XTAL operate timeout. + * - LL_ERR_BUSY: XTAL is the system clock, CANNOT stop it. + * - LL_ERR_INVD_PARAM: NULL pointer. + * @note DO NOT STOP XTAL while using it as system clock. + */ +int32_t CLK_XtalInit(const stc_clock_xtal_init_t *pstcXtalInit) +{ + int32_t i32Ret; + + if (NULL == pstcXtalInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_CLK_XTAL_STATE(pstcXtalInit->u8State)); + DDL_ASSERT(IS_CLK_XTAL_DRV_MD(pstcXtalInit->u8Drv)); + DDL_ASSERT(IS_CLK_XTAL_MD(pstcXtalInit->u8Mode)); + DDL_ASSERT(IS_CLK_XTAL_SUPDRV_STATE(pstcXtalInit->u8SuperDrv)); + DDL_ASSERT(IS_CLK_XTAL_STB_SEL(pstcXtalInit->u8StableTime)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->XTALSTBCR, pstcXtalInit->u8StableTime); + WRITE_REG8(CM_CMU->XTALCFGR, (pstcXtalInit->u8SuperDrv | pstcXtalInit->u8Drv | pstcXtalInit->u8Mode)); + if (CLK_XTAL_ON == pstcXtalInit->u8State) { + i32Ret = CLK_XtalCmd(ENABLE); + } else { + i32Ret = CLK_XtalCmd(DISABLE); + } + } + + return i32Ret; +} + +/** + * @brief XTAL function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: XTAL operate successfully + * - LL_ERR_BUSY: XTAL is the system clock or as the PLL source clock, CANNOT stop it. + * - LL_ERR_TIMEOUT: XTAL operate timeout. + * @note DO NOT STOP XTAL while using it as system clock or as the PLL source clock. + */ +int32_t CLK_XtalCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_XTAL == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else if (CLK_PLL_SRC_XTAL == PLL_SRC) { + /* XTAL as PLL clock source and PLL is working */ + if (0UL == PLL_EN_REG) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(CM_CMU->XTALCR, CLK_XTAL_OFF); + } + } else { + WRITE_REG8(CM_CMU->XTALCR, CLK_XTAL_OFF); + } + } else { + WRITE_REG8(CM_CMU->XTALCR, CLK_XTAL_ON); + i32Ret = CLK_WaitStable(CLK_STB_FLAG_XTAL, CLK_TIMEOUT); + } + + return i32Ret; +} + +/** + * @brief Init XtalStd initial structure with default value. + * @param [in] pstcXtalStdInit specifies the Parameter of XTALSTD. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t CLK_XtalStdStructInit(stc_clock_xtalstd_init_t *pstcXtalStdInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcXtalStdInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcXtalStdInit->u8State = CLK_XTALSTD_OFF; + pstcXtalStdInit->u8Mode = CLK_XTALSTD_MD_INT; + pstcXtalStdInit->u8Int = CLK_XTALSTD_INT_OFF; + pstcXtalStdInit->u8Reset = CLK_XTALSTD_RST_OFF; + } + + return i32Ret; +} + +/** + * @brief Initialise the XTAL status detection. + * @param [in] pstcXtalStdInit specifies the Parameter of XTALSTD. + * @arg u8State: The new state of the XTALSTD. + * @arg u8Mode: The XTAL status detection occur interrupt or reset. + * @arg u8Int: The XTAL status detection interrupt on or off. + * @arg u8Reset: The XTAL status detection reset on or off. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t CLK_XtalStdInit(const stc_clock_xtalstd_init_t *pstcXtalStdInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcXtalStdInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameter valid check */ + DDL_ASSERT(IS_CLK_XTALSTD_STATE(pstcXtalStdInit->u8State)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + /* Parameter valid check */ + DDL_ASSERT(IS_CLK_XTALSTD_MD(pstcXtalStdInit->u8Mode)); + DDL_ASSERT(IS_CLK_XTALSTD_INT_STATE(pstcXtalStdInit->u8Int)); + DDL_ASSERT(IS_CLK_XTALSTD_RST_STATE(pstcXtalStdInit->u8Reset)); + + /* Configure and enable XTALSTD */ + WRITE_REG8(CM_CMU->XTALSTDCR, (pstcXtalStdInit->u8State | \ + pstcXtalStdInit->u8Mode | \ + pstcXtalStdInit->u8Int | \ + pstcXtalStdInit->u8Reset)); + } + + return i32Ret; +} + +/** + * @brief Clear the XTAL error flag. + * @param None + * @retval None + * @note The system clock should not be XTAL before call this function. + */ +void CLK_ClearXtalStdStatus(void) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (0x01U == READ_REG8(CM_CMU->XTALSTDSR)) { + /* Clear the XTAL STD flag */ + WRITE_REG8(CM_CMU->XTALSTDSR, 0x00U); + } +} + +/** + * @brief Get the XTAL error flag. + * @param None + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CLK_GetXtalStdStatus(void) +{ + return ((0x00U != READ_REG32(CM_CMU->XTALSTDSR)) ? SET : RESET); +} + +/** + * @brief Init Xtal32 initial structure with default value. + * @param [in] pstcXtal32Init specifies the Parameter of XTAL32. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t CLK_Xtal32StructInit(stc_clock_xtal32_init_t *pstcXtal32Init) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcXtal32Init) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcXtal32Init->u8State = CLK_XTAL32_ON; + pstcXtal32Init->u8Drv = CLK_XTAL32_DRV_MID; + pstcXtal32Init->u8Filter = CLK_XTAL32_FILTER_ALL_MD; + } + + return i32Ret; +} + +/** + * @brief XTAL32 initialize. + * @param [in] pstcXtal32Init specifies the XTAL32 initial config. + * @arg u8State : The new state of the XTAL32. + * @arg u8Drv : The XTAL32 drive capacity. + * @arg u8Filter : The XTAL32 noise filter on or off. + * @retval int32_t: + * - LL_OK: XTAL32 initial successfully. + * - LL_ERR_BUSY: XTAL32 is the system clock, CANNOT stop it. + * - LL_ERR_INVD_PARAM: NULL pointer. + * @note DO NOT STOP XTAL32 while using it as system clock. + */ +int32_t CLK_Xtal32Init(const stc_clock_xtal32_init_t *pstcXtal32Init) +{ + int32_t i32Ret; + + if (NULL == pstcXtal32Init) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameters check */ + DDL_ASSERT(IS_CLK_XTAL32_STATE(pstcXtal32Init->u8State)); + DDL_ASSERT(IS_CLK_XTAL32_DRV_MD(pstcXtal32Init->u8Drv)); + DDL_ASSERT(IS_CLK_XTAL32_FILT_SEL(pstcXtal32Init->u8Filter)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->XTAL32CFGR, pstcXtal32Init->u8Drv); + WRITE_REG8(CM_CMU->XTAL32NFR, pstcXtal32Init->u8Filter); + if (CLK_XTAL32_ON == pstcXtal32Init->u8State) { + i32Ret = CLK_Xtal32Cmd(ENABLE); + } else { + i32Ret = CLK_Xtal32Cmd(DISABLE); + } + } + + return i32Ret; +} + +/** + * @brief XTAL32 function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: XTAL32 operate successfully + * - LL_ERR_BUSY: XTAL32 is the system clock, CANNOT stop it. + * @note DO NOT STOP XTAL32 while using it as system clock. + */ +int32_t CLK_Xtal32Cmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_XTAL32 == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(CM_CMU->XTAL32CR, CLK_XTAL32_OFF); + } + } else { + WRITE_REG8(CM_CMU->XTAL32CR, CLK_XTAL32_ON); + /* wait stable*/ + } + /* wait approx. 5 * xtal32 cycle */ + DDL_DelayUS(CLK_XTAL32_TIMEOUT); + + return i32Ret; +} + +/** + * @brief Set PLL source clock. + * @param [in] u32PllSrc PLL source clock. + * @arg CLK_PLL_SRC_XTAL + * @arg CLK_PLL_SRC_HRC + * @retval None + */ +void CLK_SetPLLSrc(uint32_t u32PllSrc) +{ + DDL_ASSERT(IS_CLK_PLL_SRC(u32PllSrc)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + MODIFY_REG32(PLL_SRC_REG, PLL_SRC_BIT, u32PllSrc << PLL_SRC_POS); +} + +/** + * @brief Init PLL initial structure with default value. + * @param [in] pstcPLLInit specifies the Parameter of PLL. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t CLK_PLLStructInit(stc_clock_pll_init_t *pstcPLLInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcPLLInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcPLLInit->PLLCFGR = 0UL; + pstcPLLInit->PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL; + pstcPLLInit->PLLCFGR_f.PLLM = CLK_PLLM_DEFAULT; + pstcPLLInit->PLLCFGR_f.PLLN = CLK_PLLN_DEFAULT; + pstcPLLInit->PLLCFGR_f.PLLP = CLK_PLLP_DEFAULT; + pstcPLLInit->PLLCFGR_f.PLLQ = CLK_PLLQ_DEFAULT; + pstcPLLInit->PLLCFGR_f.PLLR = CLK_PLLR_DEFAULT; + pstcPLLInit->u8PLLState = CLK_PLL_OFF; + } + return i32Ret; +} + +/** + * @brief PLL initialize. + * @param [in] pstcPLLInit specifies the structure of PLLH initial config. + * @arg u8PLLState : The new state of the PLLH. + * @arg PLLCFGR : PLLH config. + * @retval int32_t: + * - LL_OK: PLLH initial successfully + * - LL_ERR_TIMEOUT: PLLH initial timeout + * - LL_ERR_BUSY: PLLH is the source clock, CANNOT stop it. + * - LL_ERR_INVD_PARAM: NULL pointer + * @note The pll_input/PLLM (VCOIN) must between 8 ~ 24MHz. + * The VCOIN*PLLN (VCOOUT) is between 600 ~ 1200MHz. + * The PLLH frequency (VCOOUT/PLLHP_Q_R) is between 40 ~ 240MHz. + */ +int32_t CLK_PLLInit(const stc_clock_pll_init_t *pstcPLLInit) +{ + int32_t i32Ret; +#ifdef __DEBUG + uint32_t vcoIn; + uint32_t vcoOut; +#endif + + if (NULL == pstcPLLInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_CLK_PLL_SRC(pstcPLLInit->PLLCFGR_f.PLLSRC)); + DDL_ASSERT(IS_CLK_PLLM_DIV(pstcPLLInit->PLLCFGR_f.PLLM + 1UL)); + DDL_ASSERT(IS_CLK_PLLN_MULTI(pstcPLLInit->PLLCFGR_f.PLLN + 1UL)); + DDL_ASSERT(IS_CLK_PLLP_DIV(pstcPLLInit->PLLCFGR_f.PLLP + 1UL)); +#ifdef __DEBUG + vcoIn = ((CLK_PLL_SRC_XTAL == pstcPLLInit->PLLCFGR_f.PLLSRC ? + XTAL_VALUE : HRC_VALUE) / (pstcPLLInit->PLLCFGR_f.PLLM + 1UL)); + vcoOut = vcoIn * (pstcPLLInit->PLLCFGR_f.PLLN + 1UL); + DDL_ASSERT(IS_CLK_PLL_VCO_IN(vcoIn)); + DDL_ASSERT(IS_CLK_PLL_VCO_OUT(vcoOut)); + DDL_ASSERT(IS_CLK_PLL_FREQ(vcoOut / (pstcPLLInit->PLLCFGR_f.PLLP + 1UL))); + DDL_ASSERT(IS_CLK_PLLQ_DIV(pstcPLLInit->PLLCFGR_f.PLLQ + 1UL)); + DDL_ASSERT(IS_CLK_PLLR_DIV(pstcPLLInit->PLLCFGR_f.PLLR + 1UL)); + DDL_ASSERT(IS_CLK_PLL_FREQ(vcoOut / (pstcPLLInit->PLLCFGR_f.PLLR + 1UL))); + DDL_ASSERT(IS_CLK_PLL_FREQ(vcoOut / (pstcPLLInit->PLLCFGR_f.PLLQ + 1UL))); +#endif /* __DEBUG */ + DDL_ASSERT(IS_CLK_PLL_STATE(pstcPLLInit->u8PLLState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + /* set PLL source in advance */ + MODIFY_REG32(PLL_SRC_REG, PLL_SRC_BIT, pstcPLLInit->PLLCFGR_f.PLLSRC << PLL_SRC_POS); + WRITE_REG32(CM_CMU->PLLCFGR, pstcPLLInit->PLLCFGR); + if (CLK_PLL_ON == pstcPLLInit->u8PLLState) { + i32Ret = CLK_PLLCmd(ENABLE); + } else { + i32Ret = CLK_PLLCmd(DISABLE); + } + } + + return i32Ret; +} + +/** + * @brief PLL function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: PLL operate successfully + * - LL_ERR_BUSY: PLL is the system clock, CANNOT stop it. + * - LL_ERR_TIMEOUT: PLL operate timeout + * @note DO NOT STOP PLL while using it as system clock. + */ +int32_t CLK_PLLCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_PLL == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(PLL_EN_REG, CLK_PLL_OFF); + } + } else { + if (CLK_PLL_SRC_XTAL == PLL_SRC) { + i32Ret = CLK_WaitStable(CLK_STB_FLAG_XTAL, CLK_TIMEOUT); + } else { + i32Ret = CLK_WaitStable(CLK_STB_FLAG_HRC, CLK_TIMEOUT); + } + if (LL_OK == i32Ret) { + WRITE_REG8(PLL_EN_REG, CLK_PLL_ON); + i32Ret = CLK_WaitStable(CLK_STB_FLAG_PLL, CLK_TIMEOUT); + } + } + + return i32Ret; +} + +/** + * @brief Init PLLx initial structure with default value. + * @param [in] pstcPLLxInit specifies the Parameter of PLLx. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + * @note Pllx for UPLL while HC32F460, HC32F451, HC32F452 + * Pllx for PLLA while HC32F4A0 + */ +int32_t CLK_PLLxStructInit(stc_clock_pllx_init_t *pstcPLLxInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcPLLxInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcPLLxInit->PLLCFGR = 0UL; + pstcPLLxInit->u8PLLState = CLK_PLLX_OFF; + pstcPLLxInit->PLLCFGR_f.PLLP = CLK_PLLXP_DEFAULT; + pstcPLLxInit->PLLCFGR_f.PLLQ = CLK_PLLXQ_DEFAULT; + pstcPLLxInit->PLLCFGR_f.PLLR = CLK_PLLXR_DEFAULT; + pstcPLLxInit->PLLCFGR_f.PLLN = CLK_PLLXN_DEFAULT; + pstcPLLxInit->PLLCFGR_f.PLLM = CLK_PLLXM_DEFAULT; + } + return i32Ret; +} + +/** + * @brief PLLx Initialize. + * @param [in] pstcPLLxInit specifies the structure of UPLL initial config. + * @arg u8PLLState : The new state of the UPLL. + * @arg PLLCFGR : UPLL config. + * @retval int32_t: + * - LL_OK: UPLL initial successfully + * - LL_ERR_TIMEOUT: UPLL initial timeout + * - LL_ERR_INVD_PARAM: NULL pointer + * @note The pll_input/PLLM (VCOIN) must between 1 ~ 24MHz. + * The VCOIN*PLLN (VCOOUT) is between 240 ~ 480MHz. + * The UPLL frequency (VCOOUT/UPLLP_Q_R) is between 15 ~ 240MHz. + */ +int32_t CLK_PLLxInit(const stc_clock_pllx_init_t *pstcPLLxInit) +{ + int32_t i32Ret; + + if (NULL == pstcPLLxInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { +#ifdef __DEBUG + PLLxParamCheck(pstcPLLxInit); +#endif + + WRITE_REG32(CM_CMU->UPLLCFGR, pstcPLLxInit->PLLCFGR); + if (CLK_PLLX_ON == pstcPLLxInit->u8PLLState) { + i32Ret = CLK_PLLxCmd(ENABLE); + } else { + i32Ret = CLK_PLLxCmd(DISABLE); + } + } + return i32Ret; +} + +/** + * @brief PLLx function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: UPLL operate successfully + * - LL_ERR_TIMEOUT: UPLL operate timeout + * @note PLLx for UPLL while HC32F460, HC32F451, HC32F452 + * PLLx for PLLA while HC32F4A0 + */ +int32_t CLK_PLLxCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + WRITE_REG8(PLLX_EN_REG, CLK_PLLX_OFF); + } else { + if (CLK_PLL_SRC_XTAL == PLL_SRC) { + i32Ret = CLK_WaitStable(CLK_STB_FLAG_XTAL, CLK_TIMEOUT); + } else { + i32Ret = CLK_WaitStable(CLK_STB_FLAG_HRC, CLK_TIMEOUT); + } + if (LL_OK == i32Ret) { + WRITE_REG8(PLLX_EN_REG, CLK_PLLX_ON); + i32Ret = CLK_WaitStable(CLK_STB_FLAG_PLLX, CLK_TIMEOUT); + } + } + + return i32Ret; +} + +/** + * @brief Selects the clock source to output on MCO pin. + * @param [in] u8Ch Specifies the MCO channel. @ref CLK_MCO_Channel_Sel + * @param [in] u8Src Specifies the clock source to output. @ref CLK_MCO_Clock_Source + * @param [in] u8Div Specifies the MCOx prescaler. @ref CLK_MCO_Clock_Prescaler + * @retval None + * @note MCO pin should be configured in alternate function 1 mode. + */ +void CLK_MCOConfig(uint8_t u8Ch, uint8_t u8Src, uint8_t u8Div) +{ + __IO uint8_t *MCOCFGRx; + + /* Check the parameters. */ + DDL_ASSERT(IS_CLK_MCO_SRC(u8Src)); + DDL_ASSERT(IS_CLK_MCO_DIV(u8Div)); + DDL_ASSERT(IS_CLK_MCO_CH(u8Ch)); + /* enable register write. */ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + MCOCFGRx = &(*(__IO uint8_t *)((uint32_t)&CM_CMU->MCO1CFGR + u8Ch)); + /* Config the MCO */ + MODIFY_REG8(*MCOCFGRx, (CMU_MCOCFGR_MCOSEL | CMU_MCOCFGR_MCODIV), (u8Src | u8Div)); +} + +/** + * @brief Enable or disable the MCO1 output. + * @param [in] u8Ch Specifies the MCO channel. @ref CLK_MCO_Channel_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CLK_MCOCmd(uint8_t u8Ch, en_functional_state_t enNewState) +{ + __IO uint8_t *MCOCFGRx; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + DDL_ASSERT(IS_CLK_MCO_CH(u8Ch)); + + MCOCFGRx = &(*(__IO uint8_t *)((uint32_t)&CM_CMU->MCO1CFGR + u8Ch)); + /* Enable or disable clock output. */ + MODIFY_REG8(*MCOCFGRx, CMU_MCOCFGR_MCOEN, (uint8_t)enNewState << CMU_MCOCFGR_MCOEN_POS); +} + +/** + * @brief PLL/XTAL/HRC stable flag read. + * @param [in] u8Flag specifies the stable flag to be read. @ref CLK_STB_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CLK_GetStableStatus(uint8_t u8Flag) +{ + DDL_ASSERT(IS_CLK_STB_FLAG(u8Flag)); + + return ((0x00U != READ_REG8_BIT(CM_CMU->OSCSTBSR, u8Flag)) ? SET : RESET); +} + +/** + * @brief Set the system clock source. + * @param [in] u8Src specifies the source of system clock. @ref CLK_System_Clock_Source + * @retval None + */ +void CLK_SetSysClockSrc(uint8_t u8Src) +{ + /* Set system clock source */ + SetSysClockSrc(u8Src); + /* Update system clock */ + SystemCoreClockUpdate(); +} + +/** + * @brief Get bus clock frequency. + * @param [out] pstcClockFreq specifies the pointer to get bus frequency. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t CLK_GetClockFreq(stc_clock_freq_t *pstcClockFreq) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcClockFreq) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + GetClockFreq(pstcClockFreq); + } + return i32Ret; +} + +/** + * @brief Get bus clock frequency. + * @param [in] u32Clock specifies the bus clock to get frequency. @ref CLK_Bus_Clock_Sel + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +uint32_t CLK_GetBusClockFreq(uint32_t u32Clock) +{ + uint32_t u32ClockFreq; + DDL_ASSERT(IS_CLK_BUS_CLK(u32Clock)); + + switch (u32Clock) { + case CLK_BUS_HCLK: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS); + break; + case CLK_BUS_PCLK1: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS); + break; + case CLK_BUS_PCLK4: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK4S) >> CMU_SCFGR_PCLK4S_POS); + break; + case CLK_BUS_PCLK3: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK3S) >> CMU_SCFGR_PCLK3S_POS); + break; + case CLK_BUS_EXCLK: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_EXCKS) >> CMU_SCFGR_EXCKS_POS); + break; + case CLK_BUS_PCLK0: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK0S) >> CMU_SCFGR_PCLK0S_POS); + break; + case CLK_BUS_PCLK2: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK2S) >> CMU_SCFGR_PCLK2S_POS); + break; + default: + u32ClockFreq = SystemCoreClock; + break; + } + return u32ClockFreq; +} + +/** + * @brief Get PLL clock frequency. + * @param [out] pstcPllClkFreq specifies the pointer to get PLL frequency. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + * @note PLL for MPLL, PLLx for UPLL + */ +int32_t CLK_GetPLLClockFreq(stc_pll_clock_freq_t *pstcPllClkFreq) +{ + int32_t i32Ret = LL_OK; + uint32_t pllin; + uint32_t plln; + uint32_t pllm; + uint32_t pllp; + uint32_t pllq; + uint32_t pllr; + uint32_t pllxn; + uint32_t pllxm; + uint32_t pllxp; + uint32_t pllxq; + uint32_t pllxr; + + if (NULL == pstcPllClkFreq) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pllp = (uint32_t)((CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLP) >> CMU_PLLCFGR_MPLLP_POS); + pllq = (uint32_t)((CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLQ) >> CMU_PLLCFGR_MPLLQ_POS); + pllr = (uint32_t)((CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLR) >> CMU_PLLCFGR_MPLLR_POS); + plln = (uint32_t)((CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLN) >> CMU_PLLCFGR_MPLLN_POS); + pllm = (uint32_t)((CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLM) >> CMU_PLLCFGR_MPLLM_POS); + + pllxp = (uint32_t)((CM_CMU->UPLLCFGR & CMU_UPLLCFGR_UPLLP) >> CMU_UPLLCFGR_UPLLP_POS); + pllxq = (uint32_t)((CM_CMU->UPLLCFGR & CMU_UPLLCFGR_UPLLQ) >> CMU_UPLLCFGR_UPLLQ_POS); + pllxr = (uint32_t)((CM_CMU->UPLLCFGR & CMU_UPLLCFGR_UPLLR) >> CMU_UPLLCFGR_UPLLR_POS); + pllxn = (uint32_t)((CM_CMU->UPLLCFGR & CMU_UPLLCFGR_UPLLN) >> CMU_UPLLCFGR_UPLLN_POS); + pllxm = (uint32_t)((CM_CMU->UPLLCFGR & CMU_UPLLCFGR_UPLLM) >> CMU_UPLLCFGR_UPLLM_POS); + + /* PLLHP is used as system clock. */ + if (CLK_PLL_SRC_XTAL == PLL_SRC) { + pllin = XTAL_VALUE; + } else { + pllin = HRC_VALUE; + } + pstcPllClkFreq->u32PllVcin = (pllin / (pllm + 1UL)); + pstcPllClkFreq->u32PllVco = ((pllin / (pllm + 1UL)) * (plln + 1UL)); + pstcPllClkFreq->u32PllP = ((pllin / (pllm + 1UL)) * (plln + 1UL)) / (pllp + 1UL); + pstcPllClkFreq->u32PllQ = ((pllin / (pllm + 1UL)) * (plln + 1UL)) / (pllq + 1UL); + pstcPllClkFreq->u32PllR = ((pllin / (pllm + 1UL)) * (plln + 1UL)) / (pllr + 1UL); + pstcPllClkFreq->u32PllxVcin = (pllin / (pllxm + 1UL)); + pstcPllClkFreq->u32PllxVco = ((pllin / (pllxm + 1UL)) * (pllxn + 1UL)); + pstcPllClkFreq->u32PllxP = ((pllin / (pllxm + 1UL)) * (pllxn + 1UL)) / (pllxp + 1UL); + pstcPllClkFreq->u32PllxQ = ((pllin / (pllxm + 1UL)) * (pllxn + 1UL)) / (pllxq + 1UL); + pstcPllClkFreq->u32PllxR = ((pllin / (pllxm + 1UL)) * (pllxn + 1UL)) / (pllxr + 1UL); + } + return i32Ret; +} + +/** + * @brief HCLK/PCLK divide setting. + * @param [in] u32Clock specifies the clock to be divided. @ref CLK_Bus_Clock_Sel + * @param [in] u32Div specifies the clock divide factor. @ref CLK_Clock_Divider + * @retval None + * @note u32Div could choose CLK_HCLK_Divider, CLK_PCLK0_Divider, CLK_PCLK1_Divider, + * CLK_PCLK2_Divider, CLK_PCLK3_Divider, CLK_PCLK4_Divider, CLK_EXCLK_Divider, according to the MCU + */ +void CLK_SetClockDiv(uint32_t u32Clock, uint32_t u32Div) +{ + /* Set clock divider */ + SetSysClockDiv(u32Clock, u32Div); + /* Update system clock */ + SystemCoreClockUpdate(); +} + +/** + * @brief Set peripheral clock source. + * @param [in] u16Src specifies the peripheral clock source. @ref CLK_PERIPH_Sel + * @retval None + * @note peripheral for ADC/DAC/TRNG + */ +void CLK_SetPeriClockSrc(uint16_t u16Src) +{ + DDL_ASSERT(IS_CLK_PERIPHCLK_SRC(u16Src)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG8(CM_CMU->PERICKSEL, u16Src); +} + +/** + * @brief USB clock source config. + * @param [in] u8Src specifies the USB clock source. @ref CLK_USBCLK_Sel + * @retval None + */ +void CLK_SetUSBClockSrc(uint8_t u8Src) +{ + DDL_ASSERT(IS_CLK_USBCLK_SRC(u8Src)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->USBCKCFGR, u8Src); + + DDL_DelayUS(CLK_SYSCLK_SW_STB); +} + +/** + * @brief I2S clock source config. + * @param [in] u8Unit specifies the I2S channel for clock source. @ref CLK_I2S_Sel + * @arg CLK_I2S1: I2S Channel 1 + * @arg CLK_I2S2: I2S Channel 2 + * @arg CLK_I2S3: I2S Channel 3 + * @arg CLK_I2S4: I2S Channel 4 + * @param [in] u8Src specifies the I2S clock source. @ref CLK_PERIPH_Sel + * @retval None + */ +void CLK_SetI2SClockSrc(uint8_t u8Unit, uint8_t u8Src) +{ + DDL_ASSERT(IS_CLK_I2S_UNIT(u8Unit)); + DDL_ASSERT(IS_CLK_PERIPHCLK_SRC(u8Src)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG16(CM_CMU->I2SCKSEL, (uint16_t)CMU_I2SCKSEL_I2S1CKSEL << (u8Unit * CMU_I2SCKSEL_I2S2CKSEL_POS), \ + (uint16_t)u8Src << (u8Unit * CMU_I2SCKSEL_I2S2CKSEL_POS)); +} + +/** + * @brief Enable or disable the TPIU clock. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CLK_TpiuClockCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + MODIFY_REG8(CM_CMU->TPIUCKCFGR, CMU_TPIUCKCFGR_TPIUCKOE, (uint8_t)enNewState << CMU_TPIUCKCFGR_TPIUCKOE_POS); +} + +/** + * @brief TPIU clock divider config. + * @param [in] u8Div specifies the TPIU clock divide factor. @ref CLK_TPIU_Divider + * @arg CLK_TPIUCLK_DIV1: TPIU clock no divide + * @arg CLK_TPIUCLK_DIV2: TPIU clock divide by 2 + * @arg CLK_TPIUCLK_DIV4: TPIU clock divide by 4 + * @retval None + */ +void CLK_SetTpiuClockDiv(uint8_t u8Div) +{ + DDL_ASSERT(IS_CLK_TPIUCLK_DIV(u8Div)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + MODIFY_REG8(CM_CMU->TPIUCKCFGR, CMU_TPIUCKCFGR_TPIUCKS, u8Div); +} +/** + * @} + */ + +#endif /* LL_CLK_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_cmp.c b/mcu/lib/src/hc32_ll_cmp.c new file mode 100644 index 0000000..9d08ba4 --- /dev/null +++ b/mcu/lib/src/hc32_ll_cmp.c @@ -0,0 +1,703 @@ +/** + ******************************************************************************* + * @file hc32_ll_cmp.c + * @brief This file provides firmware functions to manage the Comparator(CMP). + * + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Modify macro define for API + 2023-01-15 CDT Code refine for scan function + 2023-06-30 CDT Modify typo + 2023-09-30 CDT Add assert for IEN bit in GetCmpFuncStatusAndDisFunc function + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_cmp.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_CMP CMP + * @brief CMP Driver Library + * @{ + */ + +#if (LL_CMP_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CMP_Local_Macros CMP Local Macros + * @{ + */ + +/** + * @defgroup CMP_Check_Parameters_Validity CMP Check Parameters Validity + * @{ + */ +#define IS_CMP_UNIT(x) \ +( ((x) == CM_CMP1) || \ + ((x) == CM_CMP2) || \ + ((x) == CM_CMP3)) + +#define CMP1_INP4_MASK (CMP1_POSITIVE_PGAO | \ + CMP1_POSITIVE_PGAO_BP | \ + CMP1_POSITIVE_CMP1_INP4) +#define CMP1_POSITIVE_MASK (CMP_POSITIVE_NONE | \ + CMP1_POSITIVE_CMP1_INP1 | \ + CMP1_POSITIVE_CMP1_INP2 | \ + CMP1_POSITIVE_CMP1_INP3 | \ + CMP1_INP4_MASK) + +#define CMP2_INP4_MASK (CMP2_POSITIVE_PGAO | \ + CMP2_POSITIVE_PGAO_BP) +#define CMP2_POSITIVE_MASK (CMP_POSITIVE_NONE | \ + CMP2_POSITIVE_CMP2_INP1 | \ + CMP2_POSITIVE_CMP2_INP2 | \ + CMP2_POSITIVE_CMP2_INP3 | \ + CMP2_INP4_MASK) + +#define CMP3_POSITIVE_MASK (CMP_POSITIVE_NONE | \ + CMP3_POSITIVE_CMP3_INP1 | \ + CMP3_POSITIVE_CMP3_INP2 | \ + CMP3_POSITIVE_CMP3_INP3 | \ + CMP3_POSITIVE_CMP3_INP4) + +#define IS_CMP1_POSITIVE_IN(x) \ +( (((x) & (~CMP1_POSITIVE_MASK)) == 0U) && \ + ((((x) & CMP1_INP4_MASK) == 0U) || \ + (((x) & CMP1_INP4_MASK) == CMP1_POSITIVE_PGAO) || \ + (((x) & CMP1_INP4_MASK) == CMP1_POSITIVE_PGAO_BP) || \ + (((x) & CMP1_INP4_MASK) == CMP1_POSITIVE_CMP1_INP4))) + +#define IS_CMP2_POSITIVE_IN(x) \ +( (((x) & (~CMP2_POSITIVE_MASK)) == 0U) && \ + ((((x) & CMP2_INP4_MASK) == 0U) || \ + (((x) & CMP2_INP4_MASK) == CMP2_POSITIVE_PGAO) || \ + (((x) & CMP2_INP4_MASK) == CMP2_POSITIVE_PGAO_BP))) + +#define IS_CMP3_POSITIVE_IN(x) \ +( ((x) & (~CMP3_POSITIVE_MASK)) == 0U) + +#define IS_CMP_NEGATIVE_IN(x) \ +( ((x) == CMP_NEGATIVE_NONE) || \ + ((x) == CMP_NEGATIVE_INM1) || \ + ((x) == CMP_NEGATIVE_INM2) || \ + ((x) == CMP_NEGATIVE_INM3) || \ + ((x) == CMP_NEGATIVE_INM4)) + +#define IS_CMP_SCAN_STABLE(x) \ +( (x) <= 0x0FU) + +#define IS_CMP_SCAN_PERIOD(x) \ +( ((x) >= 0x0FU) && \ + ((x) <= 0xFFU)) + +#define IS_CMP_8_BIT_DAC_CH(x) \ +( ((x) == CMP_8BITDAC_CH1) || \ + ((x) == CMP_8BITDAC_CH2)) + +#define IS_CMP_8_BIT_DAC_DATA(x) \ +( (x) <= 0xFFU) + +#define IS_CMP_8_BIT_DAC_SW(x) \ +( ((x) == CMP_ADC_REF_VREF) || \ + ((x) == CMP_ADC_REF_DA2) || \ + ((x) == CMP_ADC_REF_DA1)) + +#define IS_CMP_OUT_POLARITY(x) \ +( ((x) == CMP_OUT_INVT_OFF) || \ + ((x) == CMP_OUT_INVT_ON)) + +#define IS_CMP_OUT_FILTER(x) \ +( ((x) == CMP_OUT_FILTER_NONE) || \ + ((x) == CMP_OUT_FILTER_CLK) || \ + ((x) == CMP_OUT_FILTER_CLK_DIV2) || \ + ((x) == CMP_OUT_FILTER_CLK_DIV4) || \ + ((x) == CMP_OUT_FILTER_CLK_DIV8) || \ + ((x) == CMP_OUT_FILTER_CLK_DIV16) || \ + ((x) == CMP_OUT_FILTER_CLK_DIV32) || \ + ((x) == CMP_OUT_FILTER_CLK_DIV64)) + +#define IS_CMP_OUT_DETECT_EDGE(x) \ +( ((x) == CMP_DETECT_EDGS_NONE) || \ + ((x) == CMP_DETECT_EDGS_RISING) || \ + ((x) == CMP_DETECT_EDGS_FALLING) || \ + ((x) == CMP_DETECT_EDGS_BOTH)) + +/** + * @} + */ +#define CMP_DADC_RVADC_REG_UNLOCK (0x5500U) + +#define CMP_SCAN_PERIOD_IMME (0x05U) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup CMP_Local_Functions CMP Local Functions + * @{ + */ + +/** + * @brief Delay function, delay us approximately + * @param [in] u32Count us + * @retval None + */ +static void CMP_DelayUS(uint32_t u32Count) +{ + __IO uint32_t i; + const uint32_t u32Cyc = HCLK_VALUE / 10000000UL; + + while (u32Count-- > 0UL) { + i = u32Cyc; + while (i-- > 0UL) { + ; + } + } +} + +/** + * @brief Get CMP function status and disable CMP + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @retval uint16_t The register value + */ +static uint16_t GetCmpFuncStatusAndDisFunc(CM_CMP_TypeDef *CMPx) +{ + uint16_t u16temp; + /* It is possible that the interrupt may occurs after CMP status switch. */ + DDL_ASSERT(READ_REG8_BIT(CMPx->CTRL, CMP_CTRL_IEN) == 0U); + + /* Read CMP status */ + u16temp = READ_REG16_BIT(CMPx->CTRL, CMP_CTRL_CMPON); + /* Stop CMP function */ + CLR_REG16_BIT(CMPx->CTRL, CMP_CTRL_CMPON); + return u16temp; +} + +/** + * @brief Recover CMP function status + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16CmpFuncStatus CMP function status backup value + * @retval None + */ +static void RecoverCmpFuncStatus(CM_CMP_TypeDef *CMPx, uint16_t u16CmpFuncStatus) +{ + if (u16CmpFuncStatus != 0U) { + /* Recover CMP status */ + MODIFY_REG16(CMPx->CTRL, CMP_CTRL_CMPON, u16CmpFuncStatus); + /* Delay 1us */ + CMP_DelayUS(1U); + } +} + +/** + * @} + */ + +/** + * @defgroup CMP_Global_Functions CMP Global Functions + * @{ + */ + +/** + * @brief Initialize structure stc_cmp_init_t variable with default value. + * @param [in] pstcCmpInit Pointer to a structure variable which will be initialized. @ref stc_cmp_init_t + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t CMP_StructInit(stc_cmp_init_t *pstcCmpInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + if (pstcCmpInit != NULL) { + pstcCmpInit->u16PositiveInput = CMP_POSITIVE_NONE; + pstcCmpInit->u16NegativeInput = CMP_NEGATIVE_NONE; + pstcCmpInit->u16OutPolarity = CMP_OUT_INVT_OFF; + pstcCmpInit->u16OutDetectEdge = CMP_DETECT_EDGS_NONE; + pstcCmpInit->u16OutFilter = CMP_OUT_FILTER_NONE; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief De-initialize CMP unit + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @retval None + */ +void CMP_DeInit(CM_CMP_TypeDef *CMPx) +{ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + + CLR_REG16(CMPx->CTRL); + CLR_REG16(CMPx->VLTSEL); + WRITE_REG16(CMPx->CVSSTB, 0x0005U); + WRITE_REG16(CMPx->CVSPRD, 0x000FU); + CLR_REG16(CM_CMPCR->DADR1); + CLR_REG16(CM_CMPCR->DADR2); + CLR_REG16(CM_CMPCR->DACR); + CLR_REG16(CM_CMPCR->RVADC); +} + +/** + * @brief CMP normal mode initialize + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] pstcCmpInit CMP function base parameter structure + * @arg pstcCmpInit->u16PositiveInput: @ref CMP_Positive_Input_Select + * @arg pstcCmpInit->u16NegativeInput: @ref CMP_Negative_Input_Select + * @arg pstcCmpInit->u16OutPolarity: @ref CMP_Out_Polarity_Select + * @arg pstcCmpInit->u16OutDetectEdge: @ref CMP_Out_Detect_Edge_Select + * @arg pstcCmpInit->u16OutFilter: @ref CMP_Out_Filter + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t CMP_NormalModeInit(CM_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcCmpInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + /* Check CMPx instance and configuration structure*/ + if (NULL != pstcCmpInit) { + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_OUT_POLARITY(pstcCmpInit->u16OutPolarity)); + DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE(pstcCmpInit->u16OutDetectEdge)); + DDL_ASSERT(IS_CMP_OUT_FILTER(pstcCmpInit->u16OutFilter)); + if (CM_CMP1 == CMPx) { + DDL_ASSERT(IS_CMP1_POSITIVE_IN(pstcCmpInit->u16PositiveInput)); + } else if (CM_CMP2 == CMPx) { + DDL_ASSERT(IS_CMP2_POSITIVE_IN(pstcCmpInit->u16PositiveInput)); + } else { + DDL_ASSERT(IS_CMP3_POSITIVE_IN(pstcCmpInit->u16PositiveInput)); + } + DDL_ASSERT(IS_CMP_NEGATIVE_IN(pstcCmpInit->u16NegativeInput)); + + /* Stop CMP compare */ + CLR_REG16_BIT(CMPx->CTRL, CMP_CTRL_CMPON); + + /* Set voltage in */ + WRITE_REG16(CMPx->VLTSEL, pstcCmpInit->u16PositiveInput | pstcCmpInit->u16NegativeInput); + + /* Delay 1us*/ + CMP_DelayUS(1U); + /* Start CMP compare */ + SET_REG16_BIT(CMPx->CTRL, CMP_CTRL_CMPON); + /* Delay 1us*/ + CMP_DelayUS(1U); + /* Set output filter and output detect edge and output polarity */ + MODIFY_REG16(CMPx->CTRL, CMP_CTRL_FLTSL | CMP_CTRL_EDGSL | CMP_CTRL_INV, (pstcCmpInit->u16OutFilter | pstcCmpInit->u16OutDetectEdge | pstcCmpInit->u16OutPolarity)); + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Voltage compare function command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_FuncCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check CMPx instance */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(CMPx->CTRL, CMP_CTRL_CMPON); + /* Delay 1us*/ + CMP_DelayUS(1U); + } else { + CLR_REG16_BIT(CMPx->CTRL, CMP_CTRL_CMPON); + } +} + +/** + * @brief Voltage compare interrupt function command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_IntCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(CMPx->CTRL, CMP_CTRL_IEN); + } else { + CLR_REG16_BIT(CMPx->CTRL, CMP_CTRL_IEN); + } +} + +/** + * @brief Voltage compare output command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_CompareOutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(CMPx->CTRL, CMP_CTRL_CMPOE); + } else { + CLR_REG16_BIT(CMPx->CTRL, CMP_CTRL_CMPOE); + } +} + +/** + * @brief Voltage compare output port VCOUT function command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_PinVcoutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(CMPx->CTRL, CMP_CTRL_OUTEN); + } else { + CLR_REG16_BIT(CMPx->CTRL, CMP_CTRL_OUTEN); + } +} + +/** + * @brief Voltage compare result flag read + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @retval An @ref en_flag_status_t enumeration type value. + * In normal mode + * - RESET: compare voltage < reference voltage + * - SET: compare voltage > reference voltage + * In Window mode + * - RESET: compare voltage < reference low voltage or compare voltage > reference high voltage + * - SET: reference low voltage < compare voltage < reference high voltage + */ +en_flag_status_t CMP_GetStatus(const CM_CMP_TypeDef *CMPx) +{ + en_flag_status_t enRet; + /* Check CMPx instance */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + enRet = (READ_REG16_BIT(CMPx->OUTMON, CMP_OUTMON_OMON) != 0U) ? SET : RESET; + return enRet; +} + +/** + * @brief Set output detect edge + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u8CmpEdges CMP output detect edge selection. @ref CMP_Out_Detect_Edge_Select + * @retval None + */ +void CMP_SetOutDetectEdge(CM_CMP_TypeDef *CMPx, uint8_t u8CmpEdges) +{ + uint16_t u16temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE(u8CmpEdges)); + /* Read CMP status */ + u16temp = GetCmpFuncStatusAndDisFunc(CMPx); + + /* CMP output detect edge selection */ + MODIFY_REG16(CMPx->CTRL, CMP_CTRL_EDGSL, u8CmpEdges); + /* Recover CMP function */ + RecoverCmpFuncStatus(CMPx, u16temp); +} + +/** + * @brief Set output filter + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u8CmpFilter CMP output filter selection. @ref CMP_Out_Filter + * @retval None + */ +void CMP_SetOutFilter(CM_CMP_TypeDef *CMPx, uint8_t u8CmpFilter) +{ + uint16_t u16temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_OUT_FILTER(u8CmpFilter)); + /* Read CMP status */ + u16temp = GetCmpFuncStatusAndDisFunc(CMPx); + /* CMP output filter selection */ + MODIFY_REG16(CMPx->CTRL, CMP_CTRL_FLTSL, u8CmpFilter); + /* Recover CMP function */ + RecoverCmpFuncStatus(CMPx, u16temp); +} + +/** + * @brief Set output polarity + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16CmpPolarity CMP output polarity selection. @ref CMP_Out_Polarity_Select + * @retval None + */ +void CMP_SetOutPolarity(CM_CMP_TypeDef *CMPx, uint16_t u16CmpPolarity) +{ + uint16_t u16temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_OUT_POLARITY(u16CmpPolarity)); + /* Read CMP status */ + u16temp = GetCmpFuncStatusAndDisFunc(CMPx); + + /* CMP output polarity selection */ + MODIFY_REG16(CMPx->CTRL, CMP_CTRL_INV, u16CmpPolarity); + /* Recover CMP function */ + RecoverCmpFuncStatus(CMPx, u16temp); +} + +/** + * @brief Set positive in(compare voltage) + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16PositiveInput @ref CMP_Positive_Input_Select + * @retval None + */ +void CMP_SetPositiveInput(CM_CMP_TypeDef *CMPx, uint16_t u16PositiveInput) +{ + uint16_t u16temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + if (CM_CMP1 == CMPx) { + DDL_ASSERT(IS_CMP1_POSITIVE_IN(u16PositiveInput)); + } else if (CM_CMP2 == CMPx) { + DDL_ASSERT(IS_CMP2_POSITIVE_IN(u16PositiveInput)); + } else { + DDL_ASSERT(IS_CMP3_POSITIVE_IN(u16PositiveInput)); + } + + /* Read CMP status */ + u16temp = GetCmpFuncStatusAndDisFunc(CMPx); + + /* Set voltage in */ + MODIFY_REG16(CMPx->VLTSEL, (CMP_VLTSEL_CVSL | CMP_VLTSEL_C4SL), u16PositiveInput); + + /* Recover CMP function */ + RecoverCmpFuncStatus(CMPx, u16temp); +} + +/** + * @brief Set negative in(reference voltage) + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16NegativeInput @ref CMP_Negative_Input_Select + * @retval None + */ +void CMP_SetNegativeInput(CM_CMP_TypeDef *CMPx, uint16_t u16NegativeInput) +{ + uint16_t u16temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_NEGATIVE_IN(u16NegativeInput)); + /* Read CMP status */ + u16temp = GetCmpFuncStatusAndDisFunc(CMPx); + + /* Set voltage in */ + MODIFY_REG16(CMPx->VLTSEL, CMP_VLTSEL_RVSL, u16NegativeInput); + + /* Recover CMP function */ + RecoverCmpFuncStatus(CMPx, u16temp); +} + +/** + * @brief Get CMP scan INP source + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @retval An uint32_t value @ref CMP_Scan_Inp_Status + */ +uint32_t CMP_GetScanInpSrc(CM_CMP_TypeDef *CMPx) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + return (uint32_t)READ_REG16_BIT(CMPx->OUTMON, CMP_OUTMON_CVST); +} + +/** + * @brief Get CMP scan function stable time and period configuration + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16Stable The CMP stable time = T(CMP clock) x u16Stable, The stable time is recommended + * greater than 100nS + * @arg range from 0x00U to 0x0FU + * @param [in] u16Period CMP scan period = T(CMP clock) x u16Period + * @arg range from 0x0F to 0xFF + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + * @note 1. u16Period > (u16Stable + u16OutFilter * 4 + CMP_SCAN_PERIOD_IMME) + * u16OutFilter is configured in CMP_NormalModeInit() function. + */ +int32_t CMP_ScanTimeConfig(CM_CMP_TypeDef *CMPx, uint16_t u16Stable, uint16_t u16Period) +{ + uint16_t u16Fltsl; + uint16_t u16FltslDiv; + int32_t i32Ret = LL_OK; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_SCAN_STABLE(u16Stable)); + DDL_ASSERT(IS_CMP_SCAN_PERIOD(u16Period)); + + u16Fltsl = READ_REG16_BIT(CMPx->CTRL, CMP_CTRL_FLTSL); + if (0U != u16Fltsl) { + u16FltslDiv = ((uint16_t)1U << (u16Fltsl - 1U)); + } else { + u16FltslDiv = 0U; + } + + if (u16Period <= (u16Stable + u16FltslDiv * 4U + CMP_SCAN_PERIOD_IMME)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + WRITE_REG16(CMPx->CVSSTB, u16Stable); + WRITE_REG16(CMPx->CVSPRD, u16Period); + } + return i32Ret; +} + +/** + * @brief CMP scan function command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_ScanCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + MODIFY_REG16(CMPx->CTRL, CMP_CTRL_CVSEN, (uint16_t)enNewState << CMP_CTRL_CVSEN_POS); +} + +/** + * @brief CMP 8 bit DAC reference voltage command + * @param [in] u8Ch The DAC channel @ref CMP_8Bit_Dac_Ch + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_8BitDAC_Cmd(uint8_t u8Ch, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_8_BIT_DAC_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(CM_CMPCR->DACR, u8Ch); + } else { + CLR_REG16_BIT(CM_CMPCR->DACR, u8Ch); + } +} + +/** + * @brief CMP 8 bit DAC connect to ADC reference voltage command + * @param [in] u16AdcRefSw @ref CMP_8BitDAC_Adc_Ref_Switch + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_8BitDAC_AdcRefCmd(uint16_t u16AdcRefSw, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_8_BIT_DAC_SW(u16AdcRefSw)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + uint16_t WrTmp; + if (ENABLE == enNewState) { + WrTmp = u16AdcRefSw; + } else { + WrTmp = 0U; + } + WRITE_REG16(CM_CMPCR->RVADC, CMP_DADC_RVADC_REG_UNLOCK); + WRITE_REG16(CM_CMPCR->RVADC, WrTmp); +} + +/** + * @brief Write raw data to DAC + * @param [in] u8Ch DAC channel @ref CMP_8Bit_Dac_Ch + * @param [in] u16DACData DAC voltage data + * @retval None + */ +void CMP_8BitDAC_WriteData(uint8_t u8Ch, uint16_t u16DACData) +{ + DDL_ASSERT(IS_CMP_8_BIT_DAC_CH(u8Ch)); + DDL_ASSERT(IS_CMP_8_BIT_DAC_DATA(u16DACData)); + + if (CMP_8BITDAC_CH1 == u8Ch) { + WRITE_REG16(CM_CMPCR->DADR1, u16DACData); + } else { + WRITE_REG16(CM_CMPCR->DADR2, u16DACData); + } +} + +/** + * @} + */ + +#endif /* LL_CMP_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_crc.c b/mcu/lib/src/hc32_ll_crc.c new file mode 100644 index 0000000..eddde8e --- /dev/null +++ b/mcu/lib/src/hc32_ll_crc.c @@ -0,0 +1,639 @@ +/** + ******************************************************************************* + * @file hc32_ll_crc.c + * @brief This file provides firmware functions to manage the Cyclic Redundancy + * Check(CRC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Add waiting time after write CRC data + 2023-06-30 CDT Reconstruct interface function relate to calculate CRC + Optimize CRC_DeInit function + 2023-09-30 CDT Delete and modify some of group/function relate to calculate CRC + Modify typo + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_crc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_CRC CRC + * @brief Cyclic Redundancy Check Driver Library + * @{ + */ + +#if (LL_CRC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CRC_Local_Macros CRC Local Macros + * @{ + */ + +/** + * @defgroup CRC_Check_Parameters_Validity CRC Check Parameters Validity + * @{ + */ +/*! Parameter validity check for CRC protocol. */ +#define IS_CRC_PROTOCOL(x) \ +( ((x) == CRC_CRC16) || \ + ((x) == CRC_CRC32)) + +/*! Parameter validity check for CRC data width. */ +#define IS_CRC_DATA_WIDTH(x) \ +( ((x) == CRC_DATA_WIDTH_8BIT) || \ + ((x) == CRC_DATA_WIDTH_16BIT) || \ + ((x) == CRC_DATA_WIDTH_32BIT)) + +/*! Parameter validity check for REFIN. */ +#define IS_CRC_REFIN(x) \ +( ((x) == CRC_REFIN_ENABLE) || \ + ((x) == CRC_REFIN_DISABLE)) + +/*! Parameter validity check for REFOUT. */ +#define IS_CRC_REFOUT(x) \ +( ((x) == CRC_REFOUT_ENABLE) || \ + ((x) == CRC_REFOUT_DISABLE)) + +/*! Parameter validity check for XOROUT. */ +#define IS_CRC_XOROUT(x) \ +( ((x) == CRC_XOROUT_ENABLE) || \ + ((x) == CRC_XOROUT_DISABLE)) +/** + * @} + */ + +/** + * @defgroup CRC_Registers_Reset_Value_definition CRC Registers Reset Value + * @{ + */ +#define CRC_CR_RST_VALUE (0x001CUL) +/** + * @} + */ + +/** + * @defgroup CRC_DATA_Register_Address CRC Data Register Address + * @{ + */ +#define CRC_DATA_ADDR ((uint32_t)(&CM_CRC->DAT0)) +/** + * @} + */ + +/** + * @defgroup CRC_Calculate_Clock_Count CRC Calculate Clock Count + * @{ + */ +#define CRC_CALC_CLK_COUNT (10UL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup CRC_Local_Functions CRC Local Functions + * @{ + */ + +/** + * @brief Convert CRC value. + * @param [in] u32CrcValue The CRC value of CRC16 or CRC32. + * @retval the converted CRC value + */ +static uint32_t CRC_ConvertCrcValue(uint32_t u32CrcValue) +{ + uint8_t i; + uint8_t u8Size; + uint8_t u8Offset; + uint32_t u32Temp; + uint32_t u32Config; + uint32_t u32FinalCrcValue = u32CrcValue; + const uint32_t u32ConvertFlag = (CRC_REFIN_ENABLE | CRC_REFOUT_ENABLE | CRC_XOROUT_ENABLE); + + u32Config = READ_REG32(CM_CRC->CR); + + if ((u32Config & u32ConvertFlag) != u32ConvertFlag) { + if ((u32Config & CRC_CR_CR) == CRC_CRC32) { + u8Size = 32U; + } else { + u8Size = 16U; + } + + if ((u32Config & CRC_CR_REFOUT) == CRC_REFOUT_DISABLE) { + u32FinalCrcValue = __RBIT(u32FinalCrcValue); /* Bits reversing. */ + if (u8Size == 16U) { + u32FinalCrcValue >>= 16U; + u32FinalCrcValue &= 0xFFFFUL; + } + } + + if ((u32Config & CRC_CR_XOROUT) == CRC_XOROUT_DISABLE) { + u32FinalCrcValue = ~u32FinalCrcValue; /* Bits NOT. */ + } + + if ((u32Config & CRC_CR_REFIN) == CRC_REFIN_DISABLE) { + u8Size /= 8U; + /* Bits reversing in bytes. */ + for (i = 0U; i < u8Size; i++) { + u8Offset = i * 8U; + u32Temp = (u32FinalCrcValue >> u8Offset) & 0xFFUL; + u32Temp = __RBIT(u32Temp); /* Bits reversing. */ + u32Temp = u32Temp >> (24U - u8Offset); + u32FinalCrcValue &= ~((uint32_t)0xFFUL << u8Offset); + u32FinalCrcValue |= u32Temp; + } + } + } + + return u32FinalCrcValue; +} + +/** + * @brief Calculate the CRC value of a 8-bit data buffer. + * @param [in] au8Data Pointer to the input data buffer. + * @param [in] u32Len The length(counted in byte) of the data to be calculated. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: The au8Data value is NULL or u32Len value is 0. + */ +static int32_t CRC_WriteData8(const uint8_t au8Data[], uint32_t u32Len) +{ + uint32_t i; + int32_t i32Ret = LL_ERR_INVD_PARAM; + const uint32_t u32DataAddr = CRC_DATA_ADDR; + + if ((au8Data != NULL) && (u32Len != 0UL)) { + for (i = 0UL; i < u32Len; i++) { + RW_MEM8(u32DataAddr) = au8Data[i]; + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Calculate the CRC value of a 16-bit data buffer. + * @param [in] au16Data Pointer to the input data buffer. + * @param [in] u32Len The length(counted in half-word) of the data to be calculated. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: The au16Data value is NULL or u32Len value is 0. + */ +static int32_t CRC_WriteData16(const uint16_t au16Data[], uint32_t u32Len) +{ + uint32_t i; + int32_t i32Ret = LL_ERR_INVD_PARAM; + const uint32_t u32DataAddr = CRC_DATA_ADDR; + + if ((au16Data != NULL) && (u32Len != 0UL)) { + for (i = 0UL; i < u32Len; i++) { + RW_MEM16(u32DataAddr) = au16Data[i]; + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Calculate the CRC value of a 32-bit data buffer. + * @param [in] au32Data Pointer to the input data buffer. + * @param [in] u32Len The length(counted in word) of the data to be calculated. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: The au32Data value is NULL or u32Len value is 0. + */ +static int32_t CRC_WriteData32(const uint32_t au32Data[], uint32_t u32Len) +{ + uint32_t i; + int32_t i32Ret = LL_ERR_INVD_PARAM; + const uint32_t u32DataAddr = CRC_DATA_ADDR; + + if ((au32Data != NULL) && (u32Len != 0UL)) { + for (i = 0UL; i < u32Len; i++) { + RW_MEM32(u32DataAddr) = au32Data[i]; + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @} + */ + +/** + * @defgroup CRC_Global_Functions CRC Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_crc_init_t to default values. + * @param [out] pstcCrcInit Pointer to a @ref stc_crc_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcCrcInit value is NULL. + */ +int32_t CRC_StructInit(stc_crc_init_t *pstcCrcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcCrcInit) { + pstcCrcInit->u32Protocol = CRC_CRC16; + pstcCrcInit->u32InitValue = CRC_INIT_VALUE_DEFAULT; + pstcCrcInit->u32RefIn = CRC_REFIN_ENABLE; + pstcCrcInit->u32RefOut = CRC_REFOUT_ENABLE; + pstcCrcInit->u32XorOut = CRC_XOROUT_ENABLE; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize the CRC. + * @param [in] pstcCrcInit Pointer to a @ref stc_crc_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcCrcInit value is NULL. + */ +int32_t CRC_Init(const stc_crc_init_t *pstcCrcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcCrcInit) { + DDL_ASSERT(IS_CRC_PROTOCOL(pstcCrcInit->u32Protocol)); + DDL_ASSERT(IS_CRC_REFIN(pstcCrcInit->u32RefIn)); + DDL_ASSERT(IS_CRC_REFOUT(pstcCrcInit->u32RefOut)); + DDL_ASSERT(IS_CRC_XOROUT(pstcCrcInit->u32XorOut)); + + WRITE_REG32(CM_CRC->CR, (pstcCrcInit->u32RefIn | pstcCrcInit->u32RefOut | pstcCrcInit->u32XorOut)); + + MODIFY_REG32(CM_CRC->CR, CRC_CRC32, pstcCrcInit->u32Protocol); + + /* Set initial value */ + if (CRC_CRC16 == (pstcCrcInit->u32Protocol & CRC_CRC32)) { + WRITE_REG16(CM_CRC->RESLT, (uint16_t)pstcCrcInit->u32InitValue); + } else { + WRITE_REG32(CM_CRC->RESLT, pstcCrcInit->u32InitValue); + } + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief De-initialize the CRC. + * @param None + * @retval int32_t: + * - LL_OK: Reset success. + */ +int32_t CRC_DeInit(void) +{ + int32_t i32Ret = LL_OK; + WRITE_REG32(CM_CRC->CR, CRC_CR_RST_VALUE); + + return i32Ret; +} + +/** + * @brief Get status of the CRC operation result. + * @param None + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CRC_GetResultStatus(void) +{ + uint32_t u32Status; + + if (READ_REG32_BIT(CM_CRC->CR, CRC_CR_CR) == CRC_CRC32) { + u32Status = READ_REG32_BIT(CM_CRC->FLG, CRC_FLG_CRCFLAG_32); + } else { + u32Status = READ_REG32_BIT(CM_CRC->RESLT, CRC_RESLT_CRCFLAG_16); + } + + return (u32Status > 0UL) ? SET : RESET; +} + +/** + * @brief Calculate the CRC16 value and start with the previously calculated CRC as initial value. + * @param [in] u8DataWidth Bit width of the data. + * This parameter can be one of the macros group @ref CRC_DATA_Bit_Width + * @arg CRC_DATA_WIDTH_8BIT: 8 Bit + * @arg CRC_DATA_WIDTH_16BIT: 16 Bit + * @arg CRC_DATA_WIDTH_32BIT: 32 Bit + * @param [in] pvData Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in bytes or half word or word, depending on + * the bit width) of the data to be calculated. + * @retval The CRC16 value. + * @note The function fetch data in byte or half word or word depending on the data bit width(the parameter u8DataWidth). + */ +uint16_t CRC_CRC16_AccumulateData(uint8_t u8DataWidth, const void *pvData, uint32_t u32Len) +{ + uint16_t u16CrcValue = 0U; + + if ((pvData != NULL) && (u32Len != 0UL)) { + DDL_ASSERT(IS_CRC_DATA_WIDTH(u8DataWidth)); + + /* Write data */ + if (CRC_DATA_WIDTH_32BIT == u8DataWidth) { + (void)CRC_WriteData32((const uint32_t *)pvData, u32Len); + } else if (CRC_DATA_WIDTH_16BIT == u8DataWidth) { + (void)CRC_WriteData16((const uint16_t *)pvData, u32Len); + } else { + (void)CRC_WriteData8((const uint8_t *)pvData, u32Len); + } + + /* Get checksum */ + u16CrcValue = (uint16_t)READ_REG16(CM_CRC->RESLT); + } + + return u16CrcValue; +} + +/** + * @brief Calculate the CRC32 value and start with the previously calculated CRC as initial value. + * @param [in] u8DataWidth Bit width of the data. + * This parameter can be one of the macros group @ref CRC_DATA_Bit_Width + * @arg CRC_DATA_WIDTH_8BIT: 8 Bit + * @arg CRC_DATA_WIDTH_16BIT: 16 Bit + * @arg CRC_DATA_WIDTH_32BIT: 32 Bit + * @param [in] pvData Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in bytes or half word or word, depending on + * the bit width) of the data to be calculated. + * @retval The CRC32 value. + * @note The function fetch data in byte or half word or word depending on the data bit width(the parameter u8DataWidth). + */ +uint32_t CRC_CRC32_AccumulateData(uint8_t u8DataWidth, const void *pvData, uint32_t u32Len) +{ + uint32_t u32CrcValue = 0UL; + + if ((pvData != NULL) && (u32Len != 0UL)) { + DDL_ASSERT(IS_CRC_DATA_WIDTH(u8DataWidth)); + + /* Write data */ + if (CRC_DATA_WIDTH_32BIT == u8DataWidth) { + (void)CRC_WriteData32((const uint32_t *)pvData, u32Len); + } else if (CRC_DATA_WIDTH_16BIT == u8DataWidth) { + (void)CRC_WriteData16((const uint16_t *)pvData, u32Len); + } else { + (void)CRC_WriteData8((const uint8_t *)pvData, u32Len); + } + + /* Get checksum */ + u32CrcValue = READ_REG32(CM_CRC->RESLT); + } + + return u32CrcValue; +} + +/** + * @brief Calculate the CRC16 value and start with the specified initial value. + * @param [in] u16InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] u8DataWidth Bit width of the data. + * This parameter can be one of the macros group @ref CRC_DATA_Bit_Width + * @arg CRC_DATA_WIDTH_8BIT: 8 Bit + * @arg CRC_DATA_WIDTH_16BIT: 16 Bit + * @arg CRC_DATA_WIDTH_32BIT: 32 Bit + * @param [in] pvData Pointer to the buffer containing the data to be computed. + * @param [in] u32Len The length(counted in bytes or half word or word, depending on + * the bit width) of the data to be computed. + * @retval The CRC16 value. + * @note The function fetch data in byte or half word or word depending on the data bit width(the parameter u8DataWidth). + */ +uint16_t CRC_CRC16_Calculate(uint16_t u16InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len) +{ + uint16_t u16CrcValue = 0U; + + if ((pvData != NULL) && (u32Len != 0UL)) { + /* Set initial value */ + WRITE_REG16(CM_CRC->RESLT, u16InitValue); + + u16CrcValue = CRC_CRC16_AccumulateData(u8DataWidth, pvData, u32Len); + } + + return u16CrcValue; +} + +/** + * @brief Calculate the CRC32 value and start with the specified initial value. + * @param [in] u32InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] u8DataWidth Bit width of the data. + * This parameter can be one of the macros group @ref CRC_DATA_Bit_Width + * @arg CRC_DATA_WIDTH_8BIT: 8 Bit + * @arg CRC_DATA_WIDTH_16BIT: 16 Bit + * @arg CRC_DATA_WIDTH_32BIT: 32 Bit + * @param [in] pvData Pointer to the buffer containing the data to be computed. + * @param [in] u32Len The length(counted in bytes or half word or word, depending on + * the bit width) of the data to be computed. + * @retval The CRC32 value. + * @note The function fetch data in byte or half word or word depending on the data bit width(the parameter u8DataWidth). + */ +uint32_t CRC_CRC32_Calculate(uint32_t u32InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len) +{ + uint32_t u32CrcValue = 0UL; + + if ((pvData != NULL) && (u32Len != 0UL)) { + /* Set initial value */ + WRITE_REG32(CM_CRC->RESLT, u32InitValue); + + u32CrcValue = CRC_CRC32_AccumulateData(u8DataWidth, pvData, u32Len); + } + + return u32CrcValue; +} + +/** + * @brief Check the CRC16 calculating result with the expected value. + * @param [in] u16InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] u8DataWidth Bit width of the data. + * This parameter can be one of the following values: + * @arg CRC_DATA_WIDTH_8BIT: 8 Bit + * @arg CRC_DATA_WIDTH_16BIT: 16 Bit + * @arg CRC_DATA_WIDTH_32BIT: 32 Bit + * @param [in] pvData Pointer to the buffer containing the data to be computed. + * @param [in] u32Len The length(counted in byte) of the data to be calculated. + * @param [in] u16ExpectValue The expected CRC value to be checked. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CRC_CRC16_CheckData(uint16_t u16InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len, uint16_t u16ExpectValue) +{ + __IO uint32_t u32Count = CRC_CALC_CLK_COUNT; + en_flag_status_t enStatus = RESET; + uint32_t u32Expect_Value = u16ExpectValue; + + if ((pvData != NULL) && (u32Len != 0UL)) { + (void)CRC_CRC16_Calculate(u16InitValue, u8DataWidth, pvData, u32Len); + + u32Expect_Value = CRC_ConvertCrcValue(u32Expect_Value); + + /* Writes the expected CRC value to be checked */ + (void)CRC_WriteData16((uint16_t *)((void *)&u32Expect_Value), 1UL); + + /* Delay for waiting CRC result flag */ + while (u32Count-- != 0UL) { + __NOP(); + } + + enStatus = CRC_GetResultStatus(); + } + + return enStatus; +} + +/** + * @brief Check the CRC32 calculating result with the expected value. + * @param [in] u32InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] u8DataWidth Bit width of the data. + * This parameter can be one of the following values: + * @arg CRC_DATA_WIDTH_8BIT: 8 Bit + * @arg CRC_DATA_WIDTH_16BIT: 16 Bit + * @arg CRC_DATA_WIDTH_32BIT: 32 Bit + * @param [in] pvData Pointer to the buffer containing the data to be computed. + * @param [in] u32Len The length(counted in byte) of the data to be calculated. + * @param [in] u32ExpectValue The expected CRC value to be checked. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CRC_CRC32_CheckData(uint32_t u32InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len, uint32_t u32ExpectValue) +{ + __IO uint32_t u32Count = CRC_CALC_CLK_COUNT; + en_flag_status_t enStatus = RESET; + uint32_t u32Expect_Value = u32ExpectValue; + + if ((pvData != NULL) && (u32Len != 0UL)) { + (void)CRC_CRC32_Calculate(u32InitValue, u8DataWidth, pvData, u32Len); + + u32Expect_Value = CRC_ConvertCrcValue(u32Expect_Value); + + /* Writes the expected CRC value to be checked */ + (void)CRC_WriteData32(&u32Expect_Value, 1UL); + + /* Delay for waiting CRC result flag */ + while (u32Count-- != 0UL) { + __NOP(); + } + + enStatus = CRC_GetResultStatus(); + } + + return enStatus; +} + +/** + * @brief Get the CRC16 check result with the expected value. + * @param [in] u16ExpectValue The expected CRC value to be checked. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CRC_CRC16_GetCheckResult(uint16_t u16ExpectValue) +{ + __IO uint32_t u32Count = CRC_CALC_CLK_COUNT; + en_flag_status_t enStatus; + uint32_t u32Expect_Value = u16ExpectValue; + + u32Expect_Value = CRC_ConvertCrcValue(u32Expect_Value); + + /* Writes the expected CRC value to be checked */ + (void)CRC_WriteData16((uint16_t *)((void *)&u32Expect_Value), 1UL); + + /* Delay for waiting CRC result flag */ + while (u32Count-- != 0UL) { + __NOP(); + } + + enStatus = CRC_GetResultStatus(); + + return enStatus; +} + +/** + * @brief Get the CRC32 check result with the expected value. + * @param [in] u32ExpectValue The expected CRC value to be checked. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CRC_CRC32_GetCheckResult(uint32_t u32ExpectValue) +{ + __IO uint32_t u32Count = CRC_CALC_CLK_COUNT; + en_flag_status_t enStatus; + uint32_t u32Expect_Value = u32ExpectValue; + + u32Expect_Value = CRC_ConvertCrcValue(u32Expect_Value); + + /* Writes the expected CRC value to be checked */ + (void)CRC_WriteData32(&u32Expect_Value, 1UL); + + /* Delay for waiting CRC result flag */ + while (u32Count-- != 0UL) { + __NOP(); + } + + enStatus = CRC_GetResultStatus(); + + return enStatus; +} + +/** + * @} + */ + +#endif /* LL_CRC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_dbgc.c b/mcu/lib/src/hc32_ll_dbgc.c new file mode 100644 index 0000000..f97c371 --- /dev/null +++ b/mcu/lib/src/hc32_ll_dbgc.c @@ -0,0 +1,209 @@ +/** + ******************************************************************************* + * @file hc32_ll_dbgc.c + * @brief This file provides firmware functions to manage the DBGC. + @verbatim + Change Logs: + Date Author Notes + 2023-09-30 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_dbgc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_DBGC DBGC + * @brief DBGC Driver Library + * @{ + */ + +#if (LL_DBGC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup DBGC_Local_Macros DBGC Local Macros + * @{ + */ + +/** + * @defgroup DBGC_Check_Parameters_Validity DBGC Check Parameters Validity + * @{ + */ +#define IS_SECURITY_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | DBGC_SECURITY_ALL) == DBGC_SECURITY_ALL)) + +/* Parameter valid check for debug trace mode */ +#define IS_DGBC_TRACE_MD(x) \ +( ((x) == DBGC_TRACE_ASYNC) || \ + ((x) == DBGC_TRACE_SYNC_1BIT) || \ + ((x) == DBGC_TRACE_SYNC_2BIT) || \ + ((x) == DBGC_TRACE_SYNC_4BIT)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup DBGC_Global_Functions DBGC Global Functions + * @{ + */ + +/** + * @brief Get MCU security status. + * @param [in] u32Flag Specify the flags to get, This parameter can be any combination of the member from + * @ref DBGC_MCU_Security_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t DBGC_GetSecurityStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_SECURITY_FLAG(u32Flag)); + return ((0UL != READ_REG32_BIT(CM_DBGC->MCUSTAT, u32Flag)) ? SET : RESET); +} + +/** + * @brief erase the chip. + * @param [in] u32Timeout Maximum count of trying to wait flash erase + * @retval int32_t: + * - LL_OK: erase successfully + * - LL_ERR: erase error + * - LL_ERR_TIMEOUT: erase timeout + */ +int32_t DBGC_FlashErase(uint32_t u32Timeout) +{ + __IO uint32_t u32TimeCnt = 0UL; + int32_t i32Ret = LL_ERR_TIMEOUT; + SET_REG32_BIT(CM_DBGC->FERSCTL, DBGC_FERSCTL_ERASEREQ); + /* Wait erase finish */ + while (u32TimeCnt <= u32Timeout) { + if (DBGC_FERSCTL_ERASEACK == READ_REG32_BIT(CM_DBGC->FERSCTL, DBGC_FERSCTL_ERASEACK)) { + i32Ret = LL_OK; + break; + } + u32TimeCnt++; + } + if (DBGC_FERSCTL_ERASEERR == READ_REG32_BIT(CM_DBGC->FERSCTL, DBGC_FERSCTL_ERASEERR)) { + i32Ret = LL_ERR; + } + return i32Ret; +} + +/** + * @brief Get authenticate ID. + * @param [out] pstcAuthID Authenticate ID struct + * @retval the value of the authenticate ID + */ +void DBGC_GetAuthID(stc_dbgc_auth_id_t *pstcAuthID) +{ + if (NULL != pstcAuthID) { + pstcAuthID->u32AuthID0 = READ_REG32(CM_DBGC->AUTHID0); + pstcAuthID->u32AuthID1 = READ_REG32(CM_DBGC->AUTHID1); + pstcAuthID->u32AuthID2 = READ_REG32(CM_DBGC->AUTHID2); + } +} + +/** + * @brief Whether to stop the peripheral while mcu core stop. + * @param [in] u32Periph Specifies the peripheral. @ref DBGC_Periph_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DBGC_PeriphCmd(uint32_t u32Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_DBGC->MCUSTPCTL, u32Periph); + } else { + SET_REG32_BIT(CM_DBGC->MCUSTPCTL, u32Periph); + } +} + +/** + * @brief Enable or disable the trace pin output. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DBGC_TraceIoCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_DBGC->MCUTRACECTL, DBGC_MCUTRACECTL_TRACEIOEN); + } else { + CLR_REG32_BIT(CM_DBGC->MCUTRACECTL, DBGC_MCUTRACECTL_TRACEIOEN); + } +} + +/** + * @brief Config trace mode. + * @param [in] u32TraceMode An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DBGC_TraceModeConfig(uint32_t u32TraceMode) +{ + DDL_ASSERT(IS_DGBC_TRACE_MD(u32TraceMode)); + + MODIFY_REG32(CM_DBGC->MCUTRACECTL, DBGC_MCUTRACECTL_TRACEMODE, u32TraceMode); +} + +/** + * @} + */ + +#endif /* LL_DBGC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_dcu.c b/mcu/lib/src/hc32_ll_dcu.c new file mode 100644 index 0000000..96073e0 --- /dev/null +++ b/mcu/lib/src/hc32_ll_dcu.c @@ -0,0 +1,539 @@ +/** + ******************************************************************************* + * @file hc32_ll_dcu.c + * @brief This file provides firmware functions to manage the DCU(Data Computing + * Unit). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Synchronize register: DCU_INTSEL -> DCU_INTEVTSEL + Modify function comments: DCU_IntCmd + 2023-06-30 CDT Modify typo + Modify API DCU_DeInit() + Add CM_DCU4 + Modify function DCU_IntCmd() for misra + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_dcu.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_DCU DCU + * @brief DCU Driver Library + * @{ + */ + +#if (LL_DCU_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DCU_Local_Macros DCU Local Macros + * @{ + */ + +/** + * @defgroup DCU_Check_Parameters_Validity DCU Check Parameters Validity + * @{ + */ + +#define IS_DCU_BASE_FUNC_UNIT(x) \ +( ((x) == CM_DCU1) || \ + ((x) == CM_DCU2) || \ + ((x) == CM_DCU3) || \ + ((x) == CM_DCU4)) + +#define IS_DCU_UNIT(x) (IS_DCU_BASE_FUNC_UNIT(x)) + +#define IS_DCU_BASE_FUNC_UNIT_MD(x) \ +( ((x) == DCU_MD_CMP) || \ + ((x) == DCU_MD_ADD) || \ + ((x) == DCU_MD_SUB) || \ + ((x) == DCU_MD_HW_ADD) || \ + ((x) == DCU_MD_HW_SUB) || \ + ((x) == DCU_MD_INVD)) + +#define IS_DCU_BASE_FUNC_UNIT_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & (~DCU_BASE_FUNC_UNIT_FLAG_MASK)))) + +#define IS_DCU_CMP_COND(x) \ +( ((x) == DCU_CMP_TRIG_DATA0) || \ + ((x) == DCU_CMP_TRIG_DATA0_DATA1_DATA2)) + +#define IS_DCU_DATA_WIDTH(x) \ +( ((x) == DCU_DATA_WIDTH_8BIT) || \ + ((x) == DCU_DATA_WIDTH_16BIT) || \ + ((x) == DCU_DATA_WIDTH_32BIT)) + +#define IS_DCU_INT_CATEGORY(x) \ +( ((x) == DCU_CATEGORY_OP) || \ + ((x) == DCU_CATEGORY_CMP_WIN) || \ + ((x) == DCU_CATEGORY_CMP_NON_WIN)) + +#define IS_DCU_INT_OP(x) ((x) == DCU_INT_OP_CARRY) + +#define IS_DCU_INT_CMP_WIN(x) \ +( ((x) == DCU_INT_CMP_WIN_INSIDE) || \ + ((x) == DCU_INT_CMP_WIN_OUTSIDE)) + +#define IS_DCU_INT_CMP_NON_WIN(x) \ +( ((x) != 0UL) || \ + (((x) | DCU_INT_CMP_NON_WIN_ALL) == DCU_INT_CMP_NON_WIN_ALL)) + +#define IS_DCU_INT_WAVE_MD(x) \ +( ((x) != 0UL) && \ + (((x) | DCU_INT_WAVE_MD_ALL) == DCU_INT_WAVE_MD_ALL)) + +#define IS_DCU_DATA_REG(x) \ +( ((x) == DCU_DATA0_IDX) || \ + ((x) == DCU_DATA1_IDX) || \ + ((x) == DCU_DATA2_IDX)) + +#define IS_DCU_WAVE_UPPER_LIMIT(x) ((x) <= 0xFFFUL) + +#define IS_DCU_WAVE_LOWER_LIMIT(x) ((x) <= 0xFFFUL) + +#define IS_DCU_WAVE_STEP(x) ((x) <= 0xFFFUL) +/** + * @} + */ + +/** + * @defgroup DCU_Flag_Mask DCU Flag Mask + * @{ + */ +#define DCU_BASE_FUNC_UNIT_FLAG_MASK (0x0E7FUL) +/** + * @} + */ + +/** + * @defgroup DCU_Register_Address DCU Register Address + * @{ + */ +#define DCU_REG_ADDR(_REG_) ((uint32_t)(&(_REG_))) +#define DCU_DATA_REG_ADDR(_UNITx_, _IDX_) (DCU_REG_ADDR((_UNITx_)->DATA0) + ((_IDX_) << 2UL)) + +#define DCU_DATA_REG8(_UNITx_, _IDX_) (*(__IO uint8_t *)DCU_DATA_REG_ADDR(_UNITx_, _IDX_)) +#define DCU_DATA_REG16(_UNITx_, _IDX_) (*(__IO uint16_t *)DCU_DATA_REG_ADDR(_UNITx_, _IDX_)) +#define DCU_DATA_REG32(_UNITx_, _IDX_) (*(__IO uint32_t *)DCU_DATA_REG_ADDR(_UNITx_, _IDX_)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup DCU_Global_Functions DCU Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_dcu_init_t to default values. + * @param [out] pstcDcuInit Pointer to a @ref stc_dcu_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcDcuInit value is NULL. + */ +int32_t DCU_StructInit(stc_dcu_init_t *pstcDcuInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcDcuInit) { + pstcDcuInit->u32Mode = DCU_MD_INVD; + pstcDcuInit->u32DataWidth = DCU_DATA_WIDTH_8BIT; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize DCU function. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] pstcDcuInit Pointer to a @ref stc_dcu_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcDcuInit value is NULL. + */ +int32_t DCU_Init(CM_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcDcuInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcDcuInit) { + DDL_ASSERT(IS_DCU_UNIT(DCUx) && IS_DCU_BASE_FUNC_UNIT_MD(pstcDcuInit->u32Mode)); + DDL_ASSERT(IS_DCU_DATA_WIDTH(pstcDcuInit->u32DataWidth)); + + /* Set register: CTL */ + WRITE_REG32(DCUx->CTL, (pstcDcuInit->u32Mode | pstcDcuInit->u32DataWidth)); + + /* Disable interrupt */ + WRITE_REG32(DCUx->INTEVTSEL, 0x00000000UL); + + /* Clear Flag */ + WRITE_REG32(DCUx->FLAGCLR, 0x0000007FUL); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-Initialize DCU function. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @retval int32_t: + * - LL_OK: De-Initialize success. + */ +int32_t DCU_DeInit(CM_DCU_TypeDef *DCUx) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + + /* Configures the registers to reset value. */ + WRITE_REG32(DCUx->CTL, 0x00000000UL); + WRITE_REG32(DCUx->INTEVTSEL, 0x00000000UL); + + /* Clear Flag */ + WRITE_REG32(DCUx->FLAGCLR, 0x0000007FUL); + return LL_OK; +} + +/** + * @brief Set DCU operation mode. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32Mode DCU mode + * This parameter can be one of the macros group @ref DCU_Mode. + * @retval None + */ +void DCU_SetMode(CM_DCU_TypeDef *DCUx, uint32_t u32Mode) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx) && IS_DCU_BASE_FUNC_UNIT_MD(u32Mode)); + + MODIFY_REG32(DCUx->CTL, DCU_CTL_MODE, u32Mode); +} + +/** + * @brief Set DCU data size. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataWidth DCU data width + * This parameter can be one of the macros group @ref DCU_Data_Width + * @arg DCU_DATA_WIDTH_8BIT: DCU data size 8 bit + * @arg DCU_DATA_WIDTH_16BIT: DCU data size 16 bit + * @arg DCU_DATA_WIDTH_32BIT: DCU data size 32 bit + * @retval None + */ +void DCU_SetDataWidth(CM_DCU_TypeDef *DCUx, uint32_t u32DataWidth) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_WIDTH(u32DataWidth)); + + MODIFY_REG32(DCUx->CTL, DCU_CTL_DATASIZE, u32DataWidth); +} + +/** + * @brief Set DCU compare trigger condition. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32Cond DCU compare trigger condition + * This parameter can be one of the macros group @ref DCU_Compare_Trigger_Condition + * @arg DCU_CMP_TRIG_DATA0: DCU compare triggered by DATA0. + * @arg DCU_CMP_TRIG_DATA0_DATA1_DATA2: DCU compare triggered by DATA0 or DATA1 or DATA2. + * @retval None + */ +void DCU_SetCompareCond(CM_DCU_TypeDef *DCUx, uint32_t u32Cond) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_CMP_COND(u32Cond)); + + MODIFY_REG32(DCUx->CTL, DCU_CTL_COMPTRG, u32Cond); +} + +/** + * @brief Get DCU flag. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32Flag The specified DCU flag + * This parameter can be any composed value of the macros group @ref DCU_Flag. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t DCU_GetStatus(const CM_DCU_TypeDef *DCUx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx) && IS_DCU_BASE_FUNC_UNIT_FLAG(u32Flag)); + + return (0UL == READ_REG32_BIT(DCUx->FLAG, u32Flag)) ? RESET : SET; +} + +/** + * @brief Clear DCU flag. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32Flag The specified DCU flag + * This parameter can be any composed value of the macros group @ref DCU_Mode. + * @retval None + */ +void DCU_ClearStatus(CM_DCU_TypeDef *DCUx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx) && IS_DCU_BASE_FUNC_UNIT_FLAG(u32Flag)); + + WRITE_REG32(DCUx->FLAGCLR, u32Flag); +} + +/** + * @brief Enable or disable DCU interrupt function. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DCU_GlobalIntCmd(CM_DCU_TypeDef *DCUx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(DCUx->CTL, DCU_CTL_INTEN); + } else { + CLR_REG32_BIT(DCUx->CTL, DCU_CTL_INTEN); + } +} + +/** + * @brief Enable/disable DCU the specified interrupt source. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32IntCategory DCU interrupt category + * This parameter can be one of the macros group @ref DCU_Category. + * @param [in] u32IntType DCU interrupt type + * This parameter can be one of the macros group @ref DCU_Interrupt_Type. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DCU_IntCmd(CM_DCU_TypeDef *DCUx, uint32_t u32IntCategory, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint32_t u32Type; + + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_INT_CATEGORY(u32IntCategory)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DCU_CATEGORY_OP == u32IntCategory) { + DDL_ASSERT(IS_DCU_INT_OP(u32IntType)); + u32Type = (u32IntType & DCU_INT_OP_CARRY); + } else if (DCU_CATEGORY_CMP_WIN == u32IntCategory) { + DDL_ASSERT(IS_DCU_INT_CMP_WIN(u32IntType)); + u32Type = (u32IntType & DCU_INT_CMP_WIN_ALL); + } else { + DDL_ASSERT(IS_DCU_INT_CMP_NON_WIN(u32IntType)); + u32Type = (u32IntType & DCU_INT_CMP_NON_WIN_ALL); + } + + if (ENABLE == enNewState) { + SET_REG32_BIT(DCUx->INTEVTSEL, u32Type); + } else { + CLR_REG32_BIT(DCUx->INTEVTSEL, u32Type); + } +} + +/** + * @brief Read DCU register DATA for byte. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @retval DCU register DATA value for byte + */ +uint8_t DCU_ReadData8(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + return READ_REG8(DCU_DATA_REG8(DCUx, u32DataIndex)); +} + +/** + * @brief Write DCU register DATA for byte. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @param [in] u8Data The data to write. + * @retval None + */ +void DCU_WriteData8(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint8_t u8Data) +{ + __IO uint8_t *DATA; + + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + DATA = &DCU_DATA_REG8(DCUx, u32DataIndex); + WRITE_REG8(*DATA, u8Data); +} + +/** + * @brief Read DCU register DATA for half-word. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @retval DCU register DATA value for half-word + */ +uint16_t DCU_ReadData16(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + return READ_REG16(DCU_DATA_REG16(DCUx, u32DataIndex)); +} + +/** + * @brief Write DCU register DATA for half-word. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @param [in] u16Data The data to write. + * @retval None + */ +void DCU_WriteData16(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint16_t u16Data) +{ + __IO uint16_t *DATA; + + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + DATA = &DCU_DATA_REG16(DCUx, u32DataIndex); + WRITE_REG16(*DATA, u16Data); +} + +/** + * @brief Read DCU register DATA for word. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @retval DCU register DATA value for word + */ +uint32_t DCU_ReadData32(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + return READ_REG32(DCU_DATA_REG32(DCUx, u32DataIndex)); +} + +/** + * @brief Write DCU register DATA0 for word. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @param [in] u32Data The data to write. + * @retval None + */ +void DCU_WriteData32(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint32_t u32Data) +{ + __IO uint32_t *DATA; + + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + DATA = &DCU_DATA_REG32(DCUx, u32DataIndex); + WRITE_REG32(*DATA, u32Data); +} + +/** + * @} + */ + +#endif /* LL_DCU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_dma.c b/mcu/lib/src/hc32_ll_dma.c new file mode 100644 index 0000000..52b213d --- /dev/null +++ b/mcu/lib/src/hc32_ll_dma.c @@ -0,0 +1,1426 @@ +/** + ******************************************************************************* + * @file hc32_ll_dma.c + * @brief This file provides firmware functions to manage the Direct Memory + * Access (DMA). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Modify DMA_StructInit() default value + 2022-10-31 CDT Modify DMA config API + 2023-01-15 CDT Modify API DMA_DeInit and add LLP address assert + 2023-06-30 CDT Modify typo + Modify blocksize assert, 1024U is valid + Add API DMA_SetDataWidth() + Optimize set blocksize & repeat count process + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_dma.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_DMA DMA + * @brief Direct Memory Access Driver Library + * @{ + */ + +#if (LL_DMA_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DMA_Local_Macros DMA Local Macros + * @{ + */ +#define DMA_CH_REG(reg_base, ch) (*(__IO uint32_t *)((uint32_t)(&(reg_base)) + ((ch) * 0x40UL))) + +#define DMA_CNT (10U) +#define DMA_IDLE (0U) +#define DMA_BUSY (1U) +#define DMATIMEOUT1 (0x5000U) +#define DMATIMEOUT2 (0x1000u) + +/** + * @defgroup DMA_Check_Parameters_Validity DMA Check Parameters Validity + * @{ + */ +/* Parameter valid check for DMA unit. */ +#define IS_DMA_UNIT(x) \ +( ((x) == CM_DMA1) || \ + ((x) == CM_DMA2)) + +/* Parameter valid check for DMA channel. */ +#define IS_DMA_CH(x) ((x) <= DMA_CH3) + +/* Parameter valid check for DMA multiplex channel. */ +#define IS_DMA_MX_CH(x) \ +( ((x) != 0x00UL) && \ + (((x) | DMA_MX_CH_ALL) == DMA_MX_CH_ALL)) + +/* Parameter valid check for DMA block size. */ +#define IS_DMA_BLOCK_SIZE(x) ((x) <= 1024U) + +/* Parameter valid check for DMA non-sequence transfer count. */ +#define IS_DMA_NON_SEQ_TRANS_CNT(x) ((x) < 4096U) + +/* Parameter valid check for DMA non-sequence offset. */ +#define IS_DMA_NON_SEQ_OFFSET(x) ((x) <= ((1UL << 20U) - 1UL)) + +/* Parameter valid check for DMA LLP function. */ +#define IS_DMA_LLP_EN(x) \ +( ((x) == DMA_LLP_ENABLE) || \ + ((x) == DMA_LLP_DISABLE)) + +/* Parameter valid check for DMA linked-list-pointer mode. */ +#define IS_DMA_LLP_MD(x) \ +( ((x) == DMA_LLP_RUN) || \ + ((x) == DMA_LLP_WAIT)) + +/* Parameter valid check for address alignment of DMA linked-list-pointer descriptor */ +#define IS_DMA_LLP_ADDR_ALIGN(x) IS_ADDR_ALIGN_WORD(x) + +/* Parameter valid check for DMA error flag. */ +#define IS_DMA_ERR_FLAG(x) \ +( ((x)!= 0x00000000UL) && \ + (((x)| DMA_FLAG_ERR_MASK) == DMA_FLAG_ERR_MASK)) + +/* Parameter valid check for DMA transfer flag. */ +#define IS_DMA_TRANS_FLAG(x) \ +( ((x)!= 0x00000000UL) && \ + (((x)| DMA_FLAG_TRANS_MASK) == DMA_FLAG_TRANS_MASK)) + +/* Parameter valid check for DMA error interrupt. */ +#define IS_DMA_ERR_INT(x) \ +( ((x)!= 0x00000000UL) && \ + (((x)| DMA_INT_ERR_MASK) == DMA_INT_ERR_MASK)) + +/* Parameter valid check for DMA transfer interrupt. */ +#define IS_DMA_TRANS_INT(x) \ +( ((x)!= 0x00000000UL) && \ + (((x)| DMA_INT_TRANS_MASK) == DMA_INT_TRANS_MASK)) + +/* Parameter valid check for DMA request status. */ +#define IS_DMA_REQ_STAT(x) \ +( ((x) != 0x00000000UL) && \ + (((x) | DMA_STAT_REQ_MASK) == DMA_STAT_REQ_MASK)) + +/* Parameter valid check for DMA transfer status. */ +#define IS_DMA_TRANS_STAT(x) \ +( ((x) != 0x00000000UL) && \ + (((x) | DMA_STAT_TRANS_MASK) == DMA_STAT_TRANS_MASK)) + +/* Parameter valid check for DMA transfer data width. */ +#define IS_DMA_DATA_WIDTH(x) \ +( ((x) == DMA_DATAWIDTH_8BIT) || \ + ((x) == DMA_DATAWIDTH_16BIT) || \ + ((x) == DMA_DATAWIDTH_32BIT)) + +/* Parameter valid check for DMA source address mode. */ +#define IS_DMA_SADDR_MD(x) \ +( ((x) == DMA_SRC_ADDR_FIX) || \ + ((x) == DMA_SRC_ADDR_INC) || \ + ((x) == DMA_SRC_ADDR_DEC)) + +/* Parameter valid check for DMA destination address mode. */ +#define IS_DMA_DADDR_MD(x) \ +( ((x) == DMA_DEST_ADDR_FIX) || \ + ((x) == DMA_DEST_ADDR_INC) || \ + ((x) == DMA_DEST_ADDR_DEC)) + +/* Parameter valid check for DMA repeat mode. */ +#define IS_DMA_RPT_MD(x) \ +( ((x) == DMA_RPT_NONE) || \ + ((x) == DMA_RPT_SRC) || \ + ((x) == DMA_RPT_DEST) || \ + ((x) == DMA_RPT_BOTH)) + +/* Parameter valid check for DMA non_sequence mode. */ +#define IS_DMA_NON_SEQ_MD(x) \ +( ((x) == DMA_NON_SEQ_NONE) || \ + ((x) == DMA_NON_SEQ_SRC) || \ + ((x) == DMA_NON_SEQ_DEST) || \ + ((x) == DMA_NON_SEQ_BOTH)) + +/* Parameter valid check for DMA global interrupt function. */ +#define IS_DMA_INT_FUNC(x) \ +( ((x) == DMA_INT_ENABLE) || \ + ((x) == DMA_INT_DISABLE)) + +/* Parameter valid check for DMA reconfig count mode. */ +#define IS_DMA_RC_CNT_MD(x) \ +( ((x) == DMA_RC_CNT_KEEP) || \ + ((x) == DMA_RC_CNT_SRC) || \ + ((x) == DMA_RC_CNT_DEST)) + +/* Parameter valid check for DMA reconfig destination address mode. */ +#define IS_DMA_RC_DA_MD(x) \ +( ((x) == DMA_RC_DEST_ADDR_KEEP) || \ + ((x) == DMA_RC_DEST_ADDR_NS) || \ + ((x) == DMA_RC_DEST_ADDR_RPT)) + +/* Parameter valid check for DMA reconfig source address mode. */ +#define IS_DMA_RC_SA_MD(x) \ +( ((x) == DMA_RC_SRC_ADDR_KEEP) || \ + ((x) == DMA_RC_SRC_ADDR_NS) || \ + ((x) == DMA_RC_SRC_ADDR_RPT)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup DMA_Global_Functions DMA Global Functions + * @{ + */ + +/** + * @brief DMA global function config. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_Cmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Global setting, ENABLE or DISABLE DMA */ + WRITE_REG32(DMAx->EN, enNewState); +} + +/** + * @brief DMA error IRQ function config. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32ErrInt DMA error IRQ flag. @ref DMA_Int_Request_Err_Sel, @ref DMA_Int_Trans_Err_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_ErrIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32ErrInt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_ERR_INT(u32ErrInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE == enNewState) { + SET_REG32_BIT(DMAx->INTMASK0, u32ErrInt); + } else { + CLR_REG32_BIT(DMAx->INTMASK0, u32ErrInt); + } +} + +/** + * @brief Get DMA error flag. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Flag DMA error IRQ flag. @ref DMA_Flag_Trans_Err_Sel, @ref DMA_Flag_Request_Err_Sel + * @retval An @ref en_flag_status_t enumeration type value. + * @note Include transfer error flag & request error flag + */ +en_flag_status_t DMA_GetErrStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_ERR_FLAG(u32Flag)); + + return (0U != READ_REG32_BIT(DMAx->INTSTAT0, u32Flag) ? SET : RESET); +} + +/** + * @brief Clear DMA error flag. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Flag DMA error IRQ flag. @ref DMA_Flag_Trans_Err_Sel, @ref DMA_Flag_Request_Err_Sel + * @retval None + * @note Include transfer error flag & request error flag + */ +void DMA_ClearErrStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_ERR_FLAG(u32Flag)); + + SET_REG32_BIT(DMAx->INTCLR0, u32Flag); +} + +/** + * @brief DMA transfer IRQ function config. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32TransCompleteInt DMA transfer complete IRQ flag. @ref DMA_Int_Btc_Sel, @ref DMA_Int_Tc_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_TransCompleteIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32TransCompleteInt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_TRANS_INT(u32TransCompleteInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE == enNewState) { + SET_REG32_BIT(DMAx->INTMASK1, u32TransCompleteInt); + } else { + CLR_REG32_BIT(DMAx->INTMASK1, u32TransCompleteInt); + } +} + +/** + * @brief Get DMA transfer flag. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Flag DMA transfer IRQ flag. @ref DMA_Flag_Btc_Sel, @ref DMA_Flag_Tc_Sel + * @retval An @ref en_flag_status_t enumeration type value. + * @note Include transfer complete flag & block transfer complete flag + */ +en_flag_status_t DMA_GetTransCompleteStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DMA_TRANS_FLAG(u32Flag)); + return ((0U != READ_REG32_BIT(DMAx->INTSTAT1, u32Flag)) ? SET : RESET); +} + +/** + * @brief Clear DMA transfer flag. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Flag DMA transfer complete flag. @ref DMA_Flag_Btc_Sel, @ref DMA_Flag_Tc_Sel + * @retval None + * @note Include transfer complete flag & block transfer complete flag + */ +void DMA_ClearTransCompleteStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_TRANS_FLAG(u32Flag)); + + SET_REG32_BIT(DMAx->INTCLR1, u32Flag); +} + +/** + * @brief DMA channel function config. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t + */ +int32_t DMA_ChCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + static __IO uint8_t u8DmaChEnState = DMA_IDLE; + + uint16_t u16Timeout = 0U; + uint32_t u32Temp; + uint32_t u32Count; + uint32_t u32MonCount; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DMA_IDLE == u8DmaChEnState) { + u8DmaChEnState = DMA_BUSY; + + /* Read back channel enable register except current channel */ + u32Temp = (DMAx->CHEN & (~(1UL << u8Ch))); + if (0UL != u32Temp) { + if (((DMAx->CHEN & DMA_CHEN_CHEN_0) == DMA_CHEN_CHEN_0) && (u8Ch != DMA_CH0)) { + u32Count = (DMAx->DTCTL0 & DMA_DTCTL_CNT) >> DMA_DTCTL_CNT_POS; + u32MonCount = (DMAx->MONDTCTL0 & DMA_MONDTCTL_CNT) >> DMA_MONDTCTL_CNT_POS; + if (u32MonCount > DMA_CNT) { + /* not wait. */ + } else if (u32MonCount < u32Count) { + while (0UL != (DMAx->CHEN & DMA_CHEN_CHEN_0)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT1) { + u8DmaChEnState = DMA_IDLE; + return LL_ERR_TIMEOUT; + } + } + } else { + /* else */ + } + } + if (((DMAx->CHEN & DMA_CHEN_CHEN_1) == DMA_CHEN_CHEN_1) && (u8Ch != DMA_CH1)) { + u32Count = (DMAx->DTCTL1 & DMA_DTCTL_CNT) >> DMA_DTCTL_CNT_POS; + u32MonCount = (DMAx->MONDTCTL1 & DMA_MONDTCTL_CNT) >> DMA_MONDTCTL_CNT_POS; + if (u32MonCount > DMA_CNT) { + /* not wait. */ + } else if (u32MonCount < u32Count) { + u16Timeout = 0U; + while (0UL != (DMAx->CHEN & DMA_CHEN_CHEN_1)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT1) { + u8DmaChEnState = DMA_IDLE; + return LL_ERR_TIMEOUT; + } + } + } else { + /* else */ + } + } + if (((DMAx->CHEN & DMA_CHEN_CHEN_2) == DMA_CHEN_CHEN_2) && (u8Ch != DMA_CH2)) { + u16Timeout = 0U; + u32Count = (DMAx->DTCTL2 & DMA_DTCTL_CNT) >> DMA_DTCTL_CNT_POS; + u32MonCount = (DMAx->MONDTCTL2 & DMA_MONDTCTL_CNT) >> DMA_MONDTCTL_CNT_POS; + if (u32MonCount > DMA_CNT) { + /* not wait. */ + } else if (u32MonCount < u32Count) { + while (0UL != (DMAx->CHEN & DMA_CHEN_CHEN_2)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT1) { + u8DmaChEnState = DMA_IDLE; + return LL_ERR_TIMEOUT; + } + } + } else { + /* else */ + } + } + if (((DMAx->CHEN & DMA_CHEN_CHEN_3) == DMA_CHEN_CHEN_3) && (u8Ch != DMA_CH3)) { + u16Timeout = 0U; + u32Count = (DMAx->DTCTL3 & DMA_DTCTL_CNT) >> DMA_DTCTL_CNT_POS; + u32MonCount = (DMAx->MONDTCTL3 & DMA_MONDTCTL_CNT) >> DMA_MONDTCTL_CNT_POS; + if (u32MonCount > DMA_CNT) { + /* not wait. */ + } else if (u32MonCount < u32Count) { + while (0UL != (DMAx->CHEN & DMA_CHEN_CHEN_3)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT1) { + u8DmaChEnState = DMA_IDLE; + return LL_ERR_TIMEOUT; + } + } + } else { + /* else */ + } + } + } + + if (ENABLE == enNewState) { + DMAx->CHEN |= (1UL << u8Ch) & DMA_CHEN_CHEN; + } else { + DMAx->CHEN &= (~(1UL << u8Ch)) & DMA_CHEN_CHEN; + } + + u8DmaChEnState = DMA_IDLE; + return LL_OK; + } + + return LL_ERR; +} + +/** + * @brief Get DMA transfer status. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Status DMA transfer status. @ref DMA_Trans_Status_Sel + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t DMA_GetTransStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_TRANS_STAT(u32Status)); + + return ((0U != READ_REG32_BIT(DMAx->CHSTAT, u32Status)) ? SET : RESET); +} + +/** + * @brief Get DMA request status. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Status DMA request status. @ref DMA_Req_Status_Sel + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t DMA_GetRequestStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_REQ_STAT(u32Status)); + + return ((0U != READ_REG32_BIT(DMAx->REQSTAT, u32Status)) ? SET : RESET); +} + +/** + * @brief Config DMA source address. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Addr DMA source address. + * @retval int32_t + */ +int32_t DMA_SetSrcAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr) +{ + uint16_t u16Timeout = 0U; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + WRITE_REG32(DMA_CH_REG(DMAx->SAR0, u8Ch), u32Addr); + + /* Ensure the address has been written */ + while (u32Addr != READ_REG32(DMA_CH_REG(DMAx->MONSAR0, u8Ch))) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT2) { + return LL_ERR_TIMEOUT; + } else { + WRITE_REG32(DMA_CH_REG(DMAx->SAR0, u8Ch), u32Addr); + } + } + return LL_OK; +} + +/** + * @brief Config DMA destination address. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Addr DMA destination address. + * @retval int32_t + */ +int32_t DMA_SetDestAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr) +{ + uint16_t u16Timeout = 0U; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + WRITE_REG32(DMA_CH_REG(DMAx->DAR0, u8Ch), u32Addr); + + /* Ensure the address has been written */ + while (u32Addr != READ_REG32(DMA_CH_REG(DMAx->MONDAR0, u8Ch))) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT2) { + return LL_ERR_TIMEOUT; + } else { + WRITE_REG32(DMA_CH_REG(DMAx->DAR0, u8Ch), u32Addr); + } + } + return LL_OK; +} + +/** + * @brief Config DMA transfer count. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u16Count DMA transfer count (0: infinite, 1 ~ 65535). + * @retval int32_t + */ +int32_t DMA_SetTransCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Count) +{ + uint16_t u16Timeout = 0U; + __IO uint32_t *MONDTCTLx; + __IO uint32_t *DTCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + DTCTLx = &DMA_CH_REG(DMAx->DTCTL0, u8Ch); + MODIFY_REG32(*DTCTLx, DMA_DTCTL_CNT, ((uint32_t)(u16Count) << DMA_DTCTL_CNT_POS)); + MONDTCTLx = &DMA_CH_REG(DMAx->MONDTCTL0, u8Ch); + /* Ensure the transfer count has been written */ + while (u16Count != (READ_REG32_BIT(*MONDTCTLx, DMA_MONDTCTL_CNT) >> DMA_MONDTCTL_CNT_POS)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT2) { + return LL_ERR_TIMEOUT; + } else { + MODIFY_REG32(*DTCTLx, DMA_DTCTL_CNT, ((uint32_t)(u16Count) << DMA_DTCTL_CNT_POS)); + } + } + return LL_OK; +} + +/** + * @brief Config DMA block size per transfer. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u16Size DMA block size (range: 0~1024, 0 is for 1024). + * @retval int32_t + */ +int32_t DMA_SetBlockSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0U; + __IO uint32_t *MONDTCTLx; + __IO uint32_t *DTCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_BLOCK_SIZE(u16Size)); + + DTCTLx = &DMA_CH_REG(DMAx->DTCTL0, u8Ch); + MODIFY_REG32(*DTCTLx, DMA_DTCTL_BLKSIZE, u16Size); + + MONDTCTLx = &DMA_CH_REG(DMAx->MONDTCTL0, u8Ch); + /* Ensure the block size has been written */ + while (u16Size != READ_REG32_BIT(*MONDTCTLx, DMA_MONDTCTL_BLKSIZE)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT2) { + return LL_ERR_TIMEOUT; + } else { + MODIFY_REG32(*DTCTLx, DMA_DTCTL_BLKSIZE, u16Size); + } + } + + return LL_OK; +} + +/** + * @brief Config DMA data width per transfer. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32DataWidth DMA data width. @ref DMA_DataWidth_Sel + * @retval int32_t + */ +int32_t DMA_SetDataWidth(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32DataWidth) +{ + __IO uint32_t *CHxCTL0; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_DATA_WIDTH(u32DataWidth)); + + CHxCTL0 = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHxCTL0, DMA_CHCTL_HSIZE, u32DataWidth); + + return LL_OK; +} + +/** + * @brief Config DMA source repeat size. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u16Size DMA source repeat size (0, 1024: 1024, 1 ~ 1023). + * @retval int32_t + */ +int32_t DMA_SetSrcRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0U; + __IO uint32_t *MONRPTx; + __IO uint32_t *RPTx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_BLOCK_SIZE(u16Size)); + + RPTx = &DMA_CH_REG(DMAx->RPT0, u8Ch); + MODIFY_REG32(*RPTx, DMA_RPT_SRPT, ((uint32_t)(u16Size) << DMA_RPT_SRPT_POS)); + + MONRPTx = &DMA_CH_REG(DMAx->MONRPT0, u8Ch); + /* Ensure the repeat size has been written */ + while (u16Size != (READ_REG32_BIT(*MONRPTx, DMA_MONRPT_SRPT) >> DMA_MONRPT_SRPT_POS)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT2) { + return LL_ERR_TIMEOUT; + } else { + MODIFY_REG32(*RPTx, DMA_RPT_SRPT, ((uint32_t)(u16Size) << DMA_RPT_SRPT_POS)); + } + } + + return LL_OK; +} + +/** + * @brief Config DMA destination repeat size. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u16Size DMA destination repeat size (0, 1024: 1024, 1 ~ 1023). + * @retval int32_t + */ +int32_t DMA_SetDestRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0U; + __IO uint32_t *MONRPTx; + __IO uint32_t *RPTx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_BLOCK_SIZE(u16Size)); + + RPTx = &DMA_CH_REG(DMAx->RPT0, u8Ch); + MODIFY_REG32(*RPTx, DMA_RPT_DRPT, ((uint32_t)(u16Size) << DMA_RPT_DRPT_POS)); + + MONRPTx = &DMA_CH_REG(DMAx->MONRPT0, u8Ch); + /* Ensure the repeat size has been written */ + while (u16Size != (READ_REG32_BIT(*MONRPTx, DMA_MONRPT_DRPT) >> DMA_MONRPT_DRPT_POS)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT2) { + return LL_ERR_TIMEOUT; + } else { + MODIFY_REG32(*RPTx, DMA_RPT_DRPT, ((uint32_t)(u16Size) << DMA_RPT_DRPT_POS)); + } + } + + return LL_OK; +} + +/** + * @brief Config DMA source transfer count under non-sequence mode. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Count DMA source transfer count (0, 4096: 4096, 1 ~ 4095). + * @retval int32_t + */ +int32_t DMA_SetNonSeqSrcCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count) +{ + uint16_t u16Timeout = 0U; + __IO uint32_t *MONSNSEQCTLx; + __IO uint32_t *SNSEQCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_NON_SEQ_TRANS_CNT(u32Count)); + + SNSEQCTLx = &DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch); + MODIFY_REG32(*SNSEQCTLx, DMA_SNSEQCTL_SNSCNT, (u32Count << DMA_SNSEQCTL_SNSCNT_POS)); + + MONSNSEQCTLx = &DMA_CH_REG(DMAx->MONSNSEQCTL0, u8Ch); + /* Ensure the count has been written */ + while (u32Count != (READ_REG32_BIT(*MONSNSEQCTLx, DMA_MONSNSEQCTL_SNSCNT) >> DMA_MONSNSEQCTL_SNSCNT_POS)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT2) { + return LL_ERR_TIMEOUT; + } else { + MODIFY_REG32(*SNSEQCTLx, DMA_SNSEQCTL_SNSCNT, (u32Count << DMA_SNSEQCTL_SNSCNT_POS)); + } + } + + return LL_OK; +} + +/** + * @brief Config DMA destination transfer count under non-sequence mode. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Count DMA destination transfer count (0, 4096: 4096, 1 ~ 4095). + * @retval int32_t + */ +int32_t DMA_SetNonSeqDestCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count) +{ + uint16_t u16Timeout = 0U; + __IO uint32_t *MONDNSEQCTLx; + __IO uint32_t *DNSEQCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_NON_SEQ_TRANS_CNT(u32Count)); + + DNSEQCTLx = &DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch); + MODIFY_REG32(*DNSEQCTLx, DMA_DNSEQCTL_DNSCNT, (u32Count << DMA_DNSEQCTL_DNSCNT_POS)); + + MONDNSEQCTLx = &DMA_CH_REG(DMAx->MONDNSEQCTL0, u8Ch); + /* Ensure the count has been written */ + while (u32Count != (READ_REG32_BIT(*MONDNSEQCTLx, DMA_MONDNSEQCTL_DNSCNT) >> DMA_MONDNSEQCTL_DNSCNT_POS)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT2) { + return LL_ERR_TIMEOUT; + } else { + MODIFY_REG32(*DNSEQCTLx, DMA_DNSEQCTL_DNSCNT, (u32Count << DMA_DNSEQCTL_DNSCNT_POS)); + } + } + + return LL_OK; +} + +/** + * @brief Config DMA source offset number under non-sequence mode. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Offset DMA source offset (0 ~ 2^20 - 1). + * @retval int32_t + */ +int32_t DMA_SetNonSeqSrcOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset) +{ + uint16_t u16Timeout = 0U; + __IO uint32_t *MONSNSEQCTLx; + __IO uint32_t *SNSEQCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_NON_SEQ_OFFSET(u32Offset)); + + SNSEQCTLx = &DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch); + MODIFY_REG32(*SNSEQCTLx, DMA_SNSEQCTL_SOFFSET, u32Offset); + + MONSNSEQCTLx = &DMA_CH_REG(DMAx->MONSNSEQCTL0, u8Ch); + /* Ensure the offset has been written */ + while (u32Offset != READ_REG32_BIT(*MONSNSEQCTLx, DMA_MONSNSEQCTL_SOFFSET)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT2) { + return LL_ERR_TIMEOUT; + } else { + MODIFY_REG32(*SNSEQCTLx, DMA_SNSEQCTL_SOFFSET, u32Offset); + } + } + + return LL_OK; +} + +/** + * @brief Config DMA destination offset number under non-sequence mode. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Offset DMA destination offset (0 ~ 2^20 - 1). + * @retval int32_t + */ +int32_t DMA_SetNonSeqDestOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset) +{ + uint16_t u16Timeout = 0U; + __IO uint32_t *MONDNSEQCTLx; + __IO uint32_t *DNSEQCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_NON_SEQ_OFFSET(u32Offset)); + + DNSEQCTLx = &DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch); + MODIFY_REG32(*DNSEQCTLx, DMA_DNSEQCTL_DOFFSET, u32Offset); + + MONDNSEQCTLx = &DMA_CH_REG(DMAx->MONDNSEQCTL0, u8Ch); + /* Ensure the offset has been written */ + while (u32Offset != READ_REG32_BIT(*MONDNSEQCTLx, DMA_MONDNSEQCTL_DOFFSET)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT2) { + return LL_ERR_TIMEOUT; + } else { + MODIFY_REG32(*DNSEQCTLx, DMA_DNSEQCTL_DOFFSET, u32Offset); + } + } + + return LL_OK; +} + +/** + * @brief De-Initialize DMA channel function. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval None + */ +void DMA_DeInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + /* Disable */ + CLR_REG32_BIT(DMAx->CHEN, DMA_CHEN_CHEN_0 << u8Ch); + + /* Set default value. */ + WRITE_REG32(DMA_CH_REG(DMAx->SAR0, u8Ch), 0UL); + WRITE_REG32(DMA_CH_REG(DMAx->DAR0, u8Ch), 0UL); + CLR_REG32_BIT(DMAx->INTMASK0, (DMA_INTMASK0_MSKTRNERR_0 | DMA_INTMASK0_MSKREQERR_0) << u8Ch); + CLR_REG32_BIT(DMAx->INTMASK1, (DMA_INTMASK1_MSKTC_0 | DMA_INTMASK1_MSKBTC_0) << u8Ch); + SET_REG32_BIT(DMAx->INTCLR0, (DMA_INTCLR0_CLRTRNERR_0 | DMA_INTCLR0_CLRREQERR_0) << u8Ch); + SET_REG32_BIT(DMAx->INTCLR1, (DMA_INTCLR1_CLRTC_0 | DMA_INTCLR1_CLRBTC_0) << u8Ch); + + WRITE_REG32(DMA_CH_REG(DMAx->DTCTL0, u8Ch), 1UL); + WRITE_REG32(DMA_CH_REG(DMAx->CHCTL0, u8Ch), 0x00001000UL); + WRITE_REG32(DMA_CH_REG(DMAx->RPT0, u8Ch), 0UL); + WRITE_REG32(DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch), 0UL); + WRITE_REG32(DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch), 0UL); + WRITE_REG32(DMA_CH_REG(DMAx->LLP0, u8Ch), 0UL); + +} + +/** + * @brief Initialize DMA config structure. Fill each pstcDmaInit with default value + * @param [in] pstcDmaInit Pointer to a stc_dma_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_StructInit(stc_dma_init_t *pstcDmaInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaInit->u32IntEn = DMA_INT_DISABLE; + pstcDmaInit->u32SrcAddr = 0x00UL; + pstcDmaInit->u32DestAddr = 0x00UL; + pstcDmaInit->u32DataWidth = DMA_DATAWIDTH_8BIT; + pstcDmaInit->u32BlockSize = 0x01UL; + pstcDmaInit->u32TransCount = 0x00UL; + pstcDmaInit->u32SrcAddrInc = DMA_SRC_ADDR_FIX; + pstcDmaInit->u32DestAddrInc = DMA_DEST_ADDR_FIX; + } + return i32Ret; +} + +/** + * @brief DMA basic function initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaInit DMA config structure. + * @arg u32IntEn DMA interrupt ENABLE or DISABLE. + * @arg u32SrcAddr DMA source address. + * @arg u32DestAddr DMA destination address. + * @arg u32DataWidth DMA data width. + * @arg u32BlockSize DMA block size. + * @arg u32TransCount DMA transfer count. + * @arg u32SrcAddrInc DMA source address direction. + * @arg u32DestAddrInc DMA destination address direction. + * @retval int32_t: + * - LL_OK: DMA basic function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_Init(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_init_t *pstcDmaInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_DATA_WIDTH(pstcDmaInit->u32DataWidth)); + DDL_ASSERT(IS_DMA_SADDR_MD(pstcDmaInit->u32SrcAddrInc)); + DDL_ASSERT(IS_DMA_DADDR_MD(pstcDmaInit->u32DestAddrInc)); + DDL_ASSERT(IS_DMA_BLOCK_SIZE(pstcDmaInit->u32BlockSize)); + DDL_ASSERT(IS_DMA_INT_FUNC(pstcDmaInit->u32IntEn)); + + WRITE_REG32(DMA_CH_REG(DMAx->SAR0, u8Ch), pstcDmaInit->u32SrcAddr); + WRITE_REG32(DMA_CH_REG(DMAx->DAR0, u8Ch), pstcDmaInit->u32DestAddr); + + WRITE_REG32(DMA_CH_REG(DMAx->DTCTL0, u8Ch), ((pstcDmaInit->u32BlockSize & DMA_DTCTL_BLKSIZE) | \ + (pstcDmaInit->u32TransCount << DMA_DTCTL_CNT_POS))); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, (DMA_CHCTL_SINC | DMA_CHCTL_DINC | DMA_CHCTL_HSIZE | DMA_CHCTL_IE), \ + (pstcDmaInit->u32IntEn | pstcDmaInit->u32DataWidth | pstcDmaInit->u32SrcAddrInc | \ + pstcDmaInit->u32DestAddrInc)); + + } + return i32Ret; +} + +/** + * @brief Initialize DMA repeat mode config structure. + * Fill each pstcDmaInit with default value + * @param [in] pstcDmaRepeatInit Pointer to a stc_dma_repeat_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA repeat mode config structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_RepeatStructInit(stc_dma_repeat_init_t *pstcDmaRepeatInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaRepeatInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaRepeatInit->u32Mode = DMA_RPT_NONE; + pstcDmaRepeatInit->u32SrcCount = 0x00UL; + pstcDmaRepeatInit->u32DestCount = 0x00UL; + } + return i32Ret; +} + +/** + * @brief DMA repeat mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaRepeatInit DMA repeat mode config structure. + * @note Call this function after DMA_Init(); + */ +int32_t DMA_RepeatInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_repeat_init_t *pstcDmaRepeatInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaRepeatInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_RPT_MD(pstcDmaRepeatInit->u32Mode)); + DDL_ASSERT(IS_DMA_BLOCK_SIZE(pstcDmaRepeatInit->u32DestCount)); + DDL_ASSERT(IS_DMA_BLOCK_SIZE(pstcDmaRepeatInit->u32SrcCount)); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, (DMA_CHCTL_SRPTEN | DMA_CHCTL_DRPTEN), pstcDmaRepeatInit->u32Mode); + + WRITE_REG32(DMA_CH_REG(DMAx->RPT0, u8Ch), \ + ((pstcDmaRepeatInit->u32DestCount << DMA_RPT_DRPT_POS) | pstcDmaRepeatInit->u32SrcCount) & \ + (DMA_RPT_DRPT | DMA_RPT_SRPT)); + + } + return i32Ret; +} + +/** + * @brief Initialize DMA non-sequence mode config structure. + * Fill each pstcDmaInit with default value + * @param [in] pstcDmaNonSeqInit Pointer to a stc_dma_nonseq_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA non-sequence mode structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_NonSeqStructInit(stc_dma_nonseq_init_t *pstcDmaNonSeqInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaNonSeqInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaNonSeqInit->u32Mode = DMA_NON_SEQ_NONE; + pstcDmaNonSeqInit->u32SrcCount = 0x00UL; + pstcDmaNonSeqInit->u32SrcOffset = 0x00UL; + pstcDmaNonSeqInit->u32DestCount = 0x00UL; + pstcDmaNonSeqInit->u32DestOffset = 0x00UL; + } + return i32Ret; +} + +/** + * @brief DMA non-sequence mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaNonSeqInit DMA non-sequence mode config structure. + * @retval int32_t: + * - LL_OK: DMA non-sequence function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + * @note Call this function after DMA_Init(); + */ +int32_t DMA_NonSeqInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_nonseq_init_t *pstcDmaNonSeqInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaNonSeqInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_NON_SEQ_MD(pstcDmaNonSeqInit->u32Mode)); + + DDL_ASSERT(IS_DMA_NON_SEQ_TRANS_CNT(pstcDmaNonSeqInit->u32SrcCount)); + DDL_ASSERT(IS_DMA_NON_SEQ_TRANS_CNT(pstcDmaNonSeqInit->u32DestCount)); + DDL_ASSERT(IS_DMA_NON_SEQ_OFFSET(pstcDmaNonSeqInit->u32SrcOffset)); + DDL_ASSERT(IS_DMA_NON_SEQ_OFFSET(pstcDmaNonSeqInit->u32DestOffset)); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, (DMA_CHCTL_SNSEQEN | DMA_CHCTL_DNSEQEN), pstcDmaNonSeqInit->u32Mode); + + WRITE_REG32(DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch), ((pstcDmaNonSeqInit->u32SrcCount << DMA_SNSEQCTL_SNSCNT_POS) | \ + pstcDmaNonSeqInit->u32SrcOffset)); + WRITE_REG32(DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch), ((pstcDmaNonSeqInit->u32DestCount << DMA_DNSEQCTL_DNSCNT_POS) | \ + pstcDmaNonSeqInit->u32DestOffset)); + + } + return i32Ret; +} + +/** + * @brief Initialize DMA Linked List Pointer (hereafter, LLP) mode config structure. + * Fill each pstcDmaInit with default value + * @param [in] pstcDmaLlpInit Pointer to a stc_dma_llp_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA LLP mode config structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_LlpStructInit(stc_dma_llp_init_t *pstcDmaLlpInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaLlpInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaLlpInit->u32State = DMA_LLP_DISABLE; + pstcDmaLlpInit->u32Mode = DMA_LLP_WAIT; + pstcDmaLlpInit->u32Addr = 0x00UL; + } + return i32Ret; +} + +/** + * @brief DMA LLP mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaLlpInit DMA LLP config structure. + * @arg u32State DMA LLP ENABLE or DISABLE. + * @arg u32Mode DMA LLP auto-run or wait request. + * @arg u32Addr DMA LLP next list pointer address. + * @arg u32AddrSelect DMA LLP address mode. + * @retval int32_t: + * - LL_OK: DMA LLP function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + * @note Call this function after DMA_Init(); + */ +int32_t DMA_LlpInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_llp_init_t *pstcDmaLlpInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaLlpInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_LLP_EN(pstcDmaLlpInit->u32State)); + DDL_ASSERT(IS_DMA_LLP_MD(pstcDmaLlpInit->u32Mode)); + DDL_ASSERT(IS_DMA_LLP_ADDR_ALIGN(pstcDmaLlpInit->u32Addr)); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, (DMA_CHCTL_LLPEN | DMA_CHCTL_LLPRUN), \ + (pstcDmaLlpInit->u32State | pstcDmaLlpInit->u32Mode)); + + WRITE_REG32(DMA_CH_REG(DMAx->LLP0, u8Ch), pstcDmaLlpInit->u32Addr & DMA_LLP_LLP); + + } + + return i32Ret; +} + +/** + * @brief Config DMA LLP value. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Addr Next link pointer address for DMA LLP mode. + * @retval None + */ +void DMA_SetLlpAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr) +{ + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_LLP_ADDR_ALIGN(u32Addr)); + + WRITE_REG32(DMA_CH_REG(DMAx->LLP0, u8Ch), (u32Addr & DMA_LLP_LLP)); +} + +/** + * @brief DMA LLP ENABLE or DISABLE. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_LlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(DMA_CH_REG(DMAx->CHCTL0, u8Ch), DMA_CHCTL_LLPEN); + + } else { + CLR_REG32_BIT(DMA_CH_REG(DMAx->CHCTL0, u8Ch), DMA_CHCTL_LLPEN); + + } +} + +/** + * @brief DMA reconfig function ENABLE or DISABLE. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_ReconfigCmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(DMAx->RCFGCTL, 1UL); + } else { + CLR_REG32_BIT(DMAx->RCFGCTL, 1UL); + } +} + +/** + * @brief DMA LLP ENABLE or DISABLE for reconfig function. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_ReconfigLlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(DMAx->RCFGCTL, DMA_RCFGCTL_RCFGCHS | DMA_RCFGCTL_RCFGLLP, \ + ((uint32_t)(u8Ch) << DMA_RCFGCTL_RCFGCHS_POS) | ((uint32_t)enNewState << DMA_RCFGCTL_RCFGLLP_POS)); +} + +/** + * @brief Initialize DMA re-config mode config structure. + * Fill each pstcDmaRCInit with default value + * @param [in] pstcDmaRCInit Pointer to a stc_dma_reconfig_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA reconfig mode config structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_ReconfigStructInit(stc_dma_reconfig_init_t *pstcDmaRCInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaRCInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaRCInit->u32CountMode = DMA_RC_CNT_KEEP; + pstcDmaRCInit->u32DestAddrMode = DMA_RC_DEST_ADDR_KEEP; + pstcDmaRCInit->u32SrcAddrMode = DMA_RC_SRC_ADDR_KEEP; + } + return i32Ret; +} + +/** + * @brief DMA reconfig mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaRCInit DMA reconfig mode config structure + * @arg u32CountMode DMA reconfig count mode. + * @arg u32DestAddrMode DMA reconfig destination address mode. + * @arg u32SrcAddrMode DMA reconfig source address mode. + * @retval int32_t: + * - LL_OK: DMA reconfig function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer +*/ +int32_t DMA_ReconfigInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_reconfig_init_t *pstcDmaRCInit) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaRCInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_RC_CNT_MD(pstcDmaRCInit->u32CountMode)); + DDL_ASSERT(IS_DMA_RC_DA_MD(pstcDmaRCInit->u32DestAddrMode)); + DDL_ASSERT(IS_DMA_RC_SA_MD(pstcDmaRCInit->u32SrcAddrMode)); + + MODIFY_REG32(DMAx->RCFGCTL, \ + (DMA_RCFGCTL_RCFGCHS | DMA_RCFGCTL_SARMD | DMA_RCFGCTL_DARMD | DMA_RCFGCTL_CNTMD), \ + (pstcDmaRCInit->u32CountMode | pstcDmaRCInit->u32SrcAddrMode | \ + pstcDmaRCInit->u32DestAddrMode | ((uint32_t)(u8Ch) << DMA_RCFGCTL_RCFGCHS_POS))); + } + return i32Ret; +} + +/** + * @brief DMA get current source address + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current source address. + */ +uint32_t DMA_GetSrcAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return READ_REG32(DMA_CH_REG(DMAx->MONSAR0, u8Ch)); +} + +/** + * @brief DMA get current destination address + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current destination address. + */ +uint32_t DMA_GetDestAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return READ_REG32(DMA_CH_REG(DMAx->MONDAR0, u8Ch)); +} + +/** + * @brief DMA get current transfer count + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current transfer count. + */ +uint32_t DMA_GetTransCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return ((READ_REG32(DMA_CH_REG(DMAx->MONDTCTL0, u8Ch)) >> DMA_DTCTL_CNT_POS) & 0xFFFFUL); +} + +/** + * @brief DMA get current block size + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current block size. + */ +uint32_t DMA_GetBlockSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONDTCTL0, u8Ch), DMA_DTCTL_BLKSIZE)); +} + +/** + * @brief DMA get current source repeat size + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current source repeat size. + */ +uint32_t DMA_GetSrcRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONRPT0, u8Ch), DMA_RPT_SRPT)); +} + +/** + * @brief DMA get current destination repeat size + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current destination repeat size. + */ +uint32_t DMA_GetDestRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return ((READ_REG32(DMA_CH_REG(DMAx->MONRPT0, u8Ch)) >> DMA_RPT_DRPT_POS) & 0x3FFUL); +} + +/** + * @brief DMA get current source count in non-sequence mode + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current source count in non-sequence mode. + */ +uint32_t DMA_GetNonSeqSrcCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return ((READ_REG32(DMA_CH_REG(DMAx->MONSNSEQCTL0, u8Ch)) >> DMA_SNSEQCTLB_SNSCNTB_POS) & 0xFFFUL); +} + +/** + * @brief DMA get current destination count in non-sequence mode + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA,, x can be 0-1 + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current destination count in non-sequence mode. + */ +uint32_t DMA_GetNonSeqDestCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return ((READ_REG32(DMA_CH_REG(DMAx->MONDNSEQCTL0, u8Ch)) >> DMA_DNSEQCTL_DNSCNT_POS) & 0xFFFUL); +} + +/** + * @brief DMA get current source offset in non-sequence mode + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current source offset in non-sequence mode. + */ +uint32_t DMA_GetNonSeqSrcOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONSNSEQCTL0, u8Ch), DMA_SNSEQCTL_SOFFSET)); +} + +/** + * @brief DMA get current destination offset in non-sequence mode + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current destination offset in non-sequence mode. + */ +uint32_t DMA_GetNonSeqDestOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONDNSEQCTL0, u8Ch), DMA_DNSEQCTL_DOFFSET)); +} + +/** + * @} + */ + +#endif /* LL_DMA_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_efm.c b/mcu/lib/src/hc32_ll_efm.c new file mode 100644 index 0000000..78ff6df --- /dev/null +++ b/mcu/lib/src/hc32_ll_efm.c @@ -0,0 +1,1250 @@ +/** + ******************************************************************************* + * @file hc32_ll_efm.c + * @brief This file provides firmware functions to manage the Embedded Flash + * Memory unit (EFM). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-10-31 CDT Add API EFM_Protect_Enable & EFM_WriteSecurityCode + Modify API EFM_Read & EFM_Program + 2023-01-15 CDT Code refine + 2023-06-30 CDT Modify API EFM_Program() + Modify assert IS_EFM_ADDR() range + Modify API EFM_Protect_Enable() + Modify typo + Modify API EFM_WriteSecurityCode(), switch to read_only mode before exit + 2023-09-30 CDT Remove address assert from EFM_ReadByte() + Refine EFM_SequenceProgram() & EFM_ChipErase(), and put them in RAM + Fix bug of EFM_GetSwapStatus() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_efm.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_EFM EFM + * @brief Embedded Flash Management Driver Library + * @{ + */ + +#if (LL_EFM_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EFM_Local_Macros EFM Local Macros + * @{ + */ +#ifndef __EFM_FUNC +#define __EFM_FUNC __RAM_FUNC +#endif + +#define REG_LEN (32U) +#define EFM_TIMEOUT (HCLK_VALUE / 20000UL) /* EFM wait read timeout */ +#define EFM_PGM_TIMEOUT (HCLK_VALUE / 20000UL) /* EFM Program timeout max 53us */ +#define EFM_ERASE_TIMEOUT (HCLK_VALUE / 50UL) /* EFM Erase timeout max 20ms */ +#define EFM_SEQ_PGM_TIMEOUT (HCLK_VALUE / 62500UL) /* EFM Sequence Program timeout max 16us */ + +#define REMCR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_EFM->MMF_REMCR0) + (4UL * (x)))) + +/** + * @defgroup EFM_Configuration_Bit_Mask EFM Configuration Bit Mask + * @{ + */ +#define EFM_CACHE_ALL (EFM_FRMC_CRST | EFM_FRMC_CACHE) + +/** + * @} + */ + +/** + * @defgroup EFM_protect EFM protect define + * @{ + */ +#define EFM_SECURITY_LEN (12UL) +#define EFM_PROTECT1_KEY (0xAF180402UL) +#define EFM_PROTECT2_KEY (0xA85173AEUL) + +#define EFM_PROTECT1_ADDR (0x00000410UL) +#define EFM_PROTECT2_ADDR (0x00000414UL) +#define EFM_SECURITY_ADDR (0x0317FFECUL) +#define EFM_SECURITY_ADDR1 (0x0317FFE0UL) +/** + * @} + */ + +/** + * @defgroup EFM_Check_Parameters_Validity EFM Check Parameters Validity + * @{ + */ +/* Parameter validity check for efm chip . */ +#define IS_EFM_CHIP(x) ((x) == EFM_CHIP_ALL) + +/* Parameter validity check for flash latency. */ +#define IS_EFM_WAIT_CYCLE(x) ((x) <= EFM_WAIT_CYCLE15) + +/* Parameter validity check for operate mode. */ +#define IS_EFM_OPERATE_MD(x) \ +( ((x) == EFM_MD_PGM_SINGLE) || \ + ((x) == EFM_MD_PGM_READBACK) || \ + ((x) == EFM_MD_PGM_SEQ) || \ + ((x) == EFM_MD_ERASE_SECTOR) || \ + ((x) == EFM_MD_ERASE_ALL_CHIP) || \ + ((x) == EFM_MD_READONLY)) + +/* Parameter validity check for flash interrupt select. */ +#define IS_EFM_INT_SEL(x) (((x) | EFM_INT_ALL) == EFM_INT_ALL) + +/* Parameter validity check for flash flag. */ +#define IS_EFM_FLAG(x) (((x) | EFM_FLAG_ALL) == EFM_FLAG_ALL) + +/* Parameter validity check for flash clear flag. */ +#define IS_EFM_CLRFLAG(x) (((x) | EFM_FLAG_ALL) == EFM_FLAG_ALL) + +/* Parameter validity check for bus status while flash program or erase. */ +#define IS_EFM_BUS_STATUS(x) \ +( ((x) == EFM_BUS_HOLD) || \ + ((x) == EFM_BUS_RELEASE)) + +/* Parameter validity check for efm address. */ +#define IS_EFM_ADDR(x) \ +( ((x) <= EFM_END_ADDR) || \ + (((x) >= EFM_OTP_START_ADDR) && ((x) <= EFM_OTP_END_ADDR)) || \ + (((x) >= EFM_SECURITY_START_ADDR) && ((x) <= EFM_SECURITY_END_ADDR))) + +/* Parameter validity check for efm erase address. */ +#define IS_EFM_ERASE_ADDR(x) ((x) <= EFM_END_ADDR) + +/* Parameter validity check for efm erase mode . */ +#define IS_EFM_ERASE_MD(x) \ +( ((x) == EFM_MD_ERASE_ONE_CHIP) || \ + ((x) == EFM_MD_ERASE_FULL)) + +/* Parameter validity check for EFM lock status. */ +#define IS_EFM_REG_UNLOCK() (CM_EFM->FAPRT == 0x00000001UL) + +/* Parameter validity check for EFM_FWMC register lock status. */ +#define IS_EFM_FWMC_UNLOCK() (bCM_EFM->FWMC_b.PEMODE == 1U) + +/* Parameter validity check for EFM remap lock status. */ +#define IS_EFM_REMAP_UNLOCK() (CM_EFM->MMF_REMPRT == 0x00000001UL) + +/* Parameter validity check for EFM remap index */ +#define IS_EFM_REMAP_IDX(x) \ +( ((x) == EFM_REMAP_IDX0) || \ + ((x) == EFM_REMAP_IDX1)) + +/* Parameter validity check for EFM remap size */ +#define IS_EFM_REMAP_SIZE(x) \ +( ((x) >= EFM_REMAP_4K) && \ + ((x) <= EFM_REMAP_512K)) + +/* Parameter validity check for EFM remap address */ +#define IS_EFM_REMAP_ADDR(x) \ +( ((x) <= EFM_REMAP_ROM_END_ADDR) || \ + (((x) >= EFM_REMAP_RAM_START_ADDR) && \ + ((x) <= EFM_REMAP_RAM_END_ADDR))) + +/* Parameter validity check for EFM remap state */ +#define IS_EFM_REMAP_STATE(x) \ +( ((x) == EFM_REMAP_OFF) || \ + ((x) == EFM_REMAP_ON)) + +/* Parameter validity check for EFM security code length */ +#define IS_EFM_SECURITY_CODE_LEN(x) ((x) <= EFM_SECURITY_LEN) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup EFM_Local_Functions EFM Local Functions + * @{ + */ +/** + * @brief Wait EFM flag. + * @param [in] u32Flag Specifies the flag to be wait. @ref EFM_Flag_Sel + * @param [in] u32Time Specifies the time to wait while the flag not be set. + * @retval int32_t: + * - LL_OK: Flag was set. + * - LL_ERR_TIMEOUT: Flag was not set. + */ +static int32_t EFM_WaitFlag(uint32_t u32Flag, uint32_t u32Time) +{ + __IO uint32_t u32Timeout = 0UL; + int32_t i32Ret = LL_OK; + + while (SET != EFM_GetStatus(u32Flag)) { + u32Timeout++; + if (u32Timeout > u32Time) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} + +/** + * @} + */ + +/** + * @defgroup EFM_Global_Functions EFM Global Functions + * @{ + */ + +/** + * @brief Enable or disable EFM. + * @param [in] u32Flash Specifies the FLASH. @ref EFM_Chip_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EFM_Cmd(uint32_t u32Flash, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_CHIP(u32Flash)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_EFM->FSTP, u32Flash); + } else { + SET_REG32_BIT(CM_EFM->FSTP, u32Flash); + } +} + +/** + * @brief Set the efm read wait cycles. + * @param [in] u32WaitCycle Specifies the efm read wait cycles. + * @arg This parameter can be of a value of @ref EFM_Wait_Cycle + * @retval int32_t: + * - LL_OK: Program successfully. + * - LL_ERR_TIMEOUT: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_SetWaitCycle(uint32_t u32WaitCycle) +{ + uint32_t u32Timeout = 0UL; + + /* Param valid check */ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_WAIT_CYCLE(u32WaitCycle)); + + MODIFY_REG32(CM_EFM->FRMC, EFM_FRMC_FLWT, u32WaitCycle); + while (u32WaitCycle != READ_REG32_BIT(CM_EFM->FRMC, EFM_FRMC_FLWT)) { + u32Timeout++; + if (u32Timeout > EFM_TIMEOUT) { + return LL_ERR_TIMEOUT; + } + } + return LL_OK; +} + +/** + * @brief Enable or disable the flash data cache reset. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EFM_DataCacheResetCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + WRITE_REG32(bCM_EFM->FRMC_b.CRST, enNewState); +} + +/** + * @brief Enable or disable the flash data cache and instruction cache. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_CacheCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + WRITE_REG32(bCM_EFM->FRMC_b.CACHE, enNewState); +} + +/** + * @brief Enable or disable the Read of low-voltage mode. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_LowVoltageReadCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + WRITE_REG32(bCM_EFM->FRMC_b.SLPMD, enNewState); +} + +/** + * @brief Enable or disable the EFM swap function. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: Program successfully. + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_SwapCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + if (enNewState == ENABLE) { + /* Set Program single mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE); + /* Enable flash swap function */ + RW_MEM32(EFM_SWAP_ADDR) = EFM_SWAP_DATA; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND); + } else { + /* Set Sector erase mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR); + /* Disable flash switch function */ + RW_MEM32(EFM_SWAP_ADDR) = 0x0UL; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_ERASE_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND); + } + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + + return i32Ret; +} + +/** + * @brief Checks whether the swap function enable or disable. + * @param None + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EFM_GetSwapStatus(void) +{ + return ((0UL == READ_REG32(bCM_EFM->FSWP_b.FSWP)) ? SET : RESET); +} + +/** + * @brief Enable or disable the EFM low-voltage mode. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_LowVoltageCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(bCM_EFM->FRMC_b.LVM, enNewState); +} + +/** + * @brief Set the FLASH erase program mode . + * @param [in] u32Mode Specifies the FLASH erase program mode. + * @arg This parameter can be of a value of @ref EFM_OperateMode_Sel + * @retval int32_t: + * - LL_OK: Set mode successfully. + * - LL_ERR_NOT_RDY: EFM is not ready. + */ +int32_t EFM_SetOperateMode(uint32_t u32Mode) +{ + int32_t i32Ret = LL_OK; + DDL_ASSERT(IS_EFM_OPERATE_MD(u32Mode)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_SEQ_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + + if (i32Ret == LL_OK) { + /* Set the program or erase mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, u32Mode); + } + return i32Ret; +} + +/** + * @brief Enable or Disable EFM interrupt. + * @param [in] u32EfmInt Specifies the FLASH interrupt source and status. @ref EFM_Interrupt_Sel + * @arg EFM_INT_OPTEND: End of EFM Operation Interrupt source + * @arg EFM_INT_PEERR: Program/erase error Interrupt source + * @arg EFM_INT_COLERR: Read collide error Interrupt source + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_IntCmd(uint32_t u32EfmInt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_INT_SEL(u32EfmInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_EFM->FITE, u32EfmInt); + } else { + CLR_REG32_BIT(CM_EFM->FITE, u32EfmInt); + } +} + +/** + * @brief Check any of the specified flag is set or not. + * @param [in] u32Flag Specifies the FLASH flag to check. + * @arg This parameter can be of a value of @ref EFM_Flag_Sel + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EFM_GetAnyStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_EFM_FLAG(u32Flag)); + + return ((0UL == READ_REG32_BIT(CM_EFM->FSR, u32Flag)) ? RESET : SET); +} + +/** + * @brief Check all the specified flag is set or not. + * @param [in] u32Flag Specifies the FLASH flag to check. + * @arg This parameter can be of a value of @ref EFM_Flag_Sel + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EFM_GetStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_EFM_FLAG(u32Flag)); + + return ((u32Flag == READ_REG32_BIT(CM_EFM->FSR, u32Flag)) ? SET : RESET); +} + +/** + * @brief Clear the flash flag. + * @param [in] u32Flag Specifies the FLASH flag to clear. + * @arg This parameter can be of a value of @ref EFM_Flag_Sel + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_ClearStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_CLRFLAG(u32Flag)); + + SET_REG32_BIT(CM_EFM->FSCLR, u32Flag); +} + +/** + * @brief Set bus status while flash program or erase. + * @param [in] u32Status Specifies the new bus status while flash program or erase. + * This parameter can be one of the following values: + * @arg EFM_BUS_HOLD: Bus busy while flash program or erase. + * @arg EFM_BUS_RELEASE: Bus release while flash program or erase. + * @retval None + */ +void EFM_SetBusStatus(uint32_t u32Status) +{ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_BUS_STATUS(u32Status)); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + + WRITE_REG32(bCM_EFM->FWMC_b.BUSHLDCTL, u32Status); +} + +/** + * @brief EFM read byte. + * @param [in] u32Addr The specified address to read. + * @param [in] pu8ReadBuf The specified read buffer. + * @param [in] u32ByteLen The specified length to read. + * @retval int32_t: + * - LL_OK: Read successfully + * - LL_ERR_INVD_PARAM: Invalid parameter + * - LL_ERR_NOT_RDY: EFM is not ready. + */ +int32_t EFM_ReadByte(uint32_t u32Addr, uint8_t *pu8ReadBuf, uint32_t u32ByteLen) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + __IO uint8_t *pu8Buf = (uint8_t *)u32Addr; + uint32_t u32Len = u32ByteLen; + uint32_t u32ReadyFlag = EFM_FLAG_RDY; + + DDL_ASSERT(IS_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_EFM_ADDR(u32Addr + u32ByteLen - 1UL)); + + if (NULL != pu8ReadBuf) { + + if (LL_OK == EFM_WaitFlag(u32ReadyFlag, EFM_TIMEOUT)) { + while (0UL != u32Len) { + *(pu8ReadBuf++) = *(pu8Buf++); + u32Len--; + } + i32Ret = LL_OK; + } else { + i32Ret = LL_ERR_NOT_RDY; + } + } + + return i32Ret; +} + +/** + * @brief EFM program (single program mode). + * @param [in] u32Addr The specified program address. + * @param [in] pu8Buf The pointer of specified program data. + * @param [in] u32Len The length of specified program data. + * @retval int32_t: + * - LL_OK: Program successful. + * - LL_ERR_NOT_RDY: EFM if not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_Program(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint8_t u8Shift; + uint32_t u32LoopWords = u32Len >> 2UL; + uint32_t u32RemainBytes = u32Len % 4UL; + uint32_t *u32pSource = (uint32_t *)(uint32_t)pu8Buf; + uint32_t *u32pDest = (uint32_t *)u32Addr; + uint32_t u32LastWord; + + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_EFM_ADDR(u32Addr + u32Len - 1UL)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + + u8Shift = 0U; + + /* CLear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + /* Set single program mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE); + + while (u32LoopWords-- > 0UL) { + /* program data. */ + *u32pDest++ = *u32pSource++; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + } + + if (0U != u32RemainBytes) { + u32LastWord = *u32pSource; + u32LastWord |= 0xFFFFFFFFUL << (u32RemainBytes * 8UL); + *u32pDest++ = u32LastWord; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + + } + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + /* Reset cache data */ + /* Recover CACHE function */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + return i32Ret; +} + +/** + * @brief EFM single program mode(Word). + * @param [in] u32Addr The specified program address. + * @param [in] u32Data The specified program data. + * @retval int32_t: + * - LL_OK: Program successfully + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_ProgramWord(uint32_t u32Addr, uint32_t u32Data) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint8_t u8Shift; + + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + + /* Clear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE function */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + u8Shift = 0U; + /* Set single program mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE); + /* Program data. */ + RW_MEM32(u32Addr) = u32Data; + + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* Recover CACHE function */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + + return i32Ret; +} + +/** + * @brief EFM single program with read back(Word). + * @param [in] u32Addr The specified program address. + * @param [in] u32Data The specified program data. + * @retval int32_t: + * - LL_OK: Program successfully + * - LL_ERR: program error + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_ProgramWordReadBack(uint32_t u32Addr, uint32_t u32Data) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint8_t u8Shift; + + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + + /* Clear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + u8Shift = 0U; + /* Set Program and read back mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_READBACK); + /* Program data. */ + RW_MEM32(u32Addr) = (uint32_t)u32Data; + + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + + /* Get the flag PGMISMTCH */ + if (SET == EFM_GetStatus(EFM_FLAG_PGMISMTCH << u8Shift)) { + /* Clear flag PGMISMTCH */ + EFM_ClearStatus(EFM_FLAG_PGMISMTCH << u8Shift); + i32Ret = LL_ERR; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* recover CACHE function */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + + return i32Ret; +} + +/** + * @brief EFM program (sequence program mode). + * @param [in] u32Addr The specified program address. + * @param [in] pu8Buf The pointer of specified program data. + * @param [in] u32Len The length of specified program data. + * @retval int32_t: + * - LL_OK: Program successfully + * - LL_ERR_TIMEOUT: program error timeout + * @note Call EFM_REG_Unlock() unlock EFM register first. + * __EFM_FUNC default value is __RAM_FUNC. + */ +__EFM_FUNC int32_t EFM_SequenceProgram(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint32_t u32LoopWords = u32Len >> 2UL; + uint32_t u32RemainBytes = u32Len % 4UL; + uint32_t *u32pSource = (uint32_t *)(uint32_t)pu8Buf; + uint32_t *u32pDest = (uint32_t *)u32Addr; + uint32_t u32Timeout; + uint32_t u32LastWord; + + /* Assert */ + if (!IS_EFM_REG_UNLOCK()) { + return LL_ERR_NOT_RDY; + } + if ((!IS_EFM_FWMC_UNLOCK()) || (!IS_EFM_ADDR(u32Addr)) || (!IS_EFM_ADDR(u32Addr + u32Len - 1UL))) { + return LL_ERR_INVD_PARAM; + } + if (!IS_ADDR_ALIGN_WORD(u32Addr)) { + return LL_ERR_INVD_PARAM; + } + + /* CLear the error flag. */ + SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Set sequence program mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SEQ); + + while (u32LoopWords-- > 0UL) { + /* program data. */ + *u32pDest++ = *u32pSource++; + /* wait for operation end flag. */ + u32Timeout = 0UL; + while (EFM_FLAG_OPTEND != READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_OPTEND)) { + if (u32Timeout++ >= EFM_PGM_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + /* Clear operation end flag */ + u32Timeout = 0UL; + while (EFM_FLAG_OPTEND == READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_OPTEND)) { + SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_OPTEND); + if (u32Timeout++ >= EFM_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + } + + if (0U != u32RemainBytes) { + u32LastWord = *u32pSource; + u32LastWord |= 0xFFFFFFFFUL << (u32RemainBytes * 8UL); + *u32pDest++ = u32LastWord; + + /* wait for operation end flag. */ + u32Timeout = 0UL; + while (EFM_FLAG_OPTEND != READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_OPTEND)) { + if (u32Timeout++ >= EFM_PGM_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + /* Clear operation end flag */ + u32Timeout = 0UL; + while (EFM_FLAG_OPTEND == READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_OPTEND)) { + SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_OPTEND); + if (u32Timeout++ >= EFM_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + } + + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + /* Wait for ready flag. */ + u32Timeout = 0UL; + while (EFM_FLAG_RDY != READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_RDY)) { + if (u32Timeout++ >= EFM_PGM_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + /* Recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + return i32Ret; +} + +/** + * @brief EFM sector erase. + * @param [in] u32Addr The address in the specified sector. + * @retval int32_t: + * - LL_OK: Erase successful. + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_SectorErase(uint32_t u32Addr) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint8_t u8Shift; + + DDL_ASSERT(IS_EFM_ERASE_ADDR(u32Addr)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + + /* CLear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + u8Shift = 0U; + /* Set sector erase mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR); + + /* Erase */ + RW_MEM32(u32Addr) = 0UL; + + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_ERASE_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* Clear the operation end flag */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + /* Recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + + return i32Ret; +} + +/** + * @brief EFM chip erase. + * @param [in] u8Chip Specifies the chip to be erased @ref EFM_Chip_Sel + * @retval int32_t: + * - LL_OK: Erase successfully + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + * __EFM_FUNC default value is __RAM_FUNC. + */ +__EFM_FUNC int32_t EFM_ChipErase(uint8_t u8Chip) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint32_t u32Addr = 0UL; + uint8_t u8Shift; + uint32_t u32Timeout; + + /* Assert */ + if (!IS_EFM_REG_UNLOCK()) { + return LL_ERR_NOT_RDY; + } + if ((!IS_EFM_FWMC_UNLOCK()) || !IS_EFM_CHIP(u8Chip)) { + return LL_ERR_INVD_PARAM; + } + + u8Shift = 0U; + + /* CLear the error flag. */ + SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + if (EFM_CHIP_ALL == u8Chip) { + if (1UL == (READ_REG32(bCM_EFM->FSWP_b.FSWP))) { + /* Set Sector erase mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR); + /* Disable flash switch function */ + RW_MEM32(EFM_SWAP_ADDR) = 0x0UL; + /* wait for operation end flag. */ + u32Timeout = 0UL; + while (EFM_FLAG_OPTEND != READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_OPTEND)) { + if (u32Timeout++ >= EFM_PGM_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + /* CLear the operation end flag */ + SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_OPTEND); + } + } + + /* Set chip erase mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_ALL_CHIP); + /* Erase */ + RW_MEM32(u32Addr) = 0UL; + /* Wait for ready flag. */ + u32Timeout = 0UL; + while ((EFM_FLAG_RDY << u8Shift) != READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_RDY << u8Shift)) { + if (u32Timeout++ >= EFM_ERASE_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + /* CLear the operation end flag. */ + SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_OPTEND << u8Shift); + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + return i32Ret; +} + +/** + * @brief FWMC register write enable or disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EFM_FWMC_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_EFM->FWMC_b.PEMODE, enNewState); +} + +/** + * @brief EFM OTP lock. + * @param [in] u32Addr Specifies the OTP block + * @retval int32_t: + * - LL_OK: Lock successfully + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note The address should be word align. + * Call EFM_REG_Unlock() and EFM_OTP_WP_Unlock() unlock EFM_FWMC register first. + */ +int32_t EFM_OTP_Lock(uint32_t u32Addr) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + + if ((u32Addr >= EFM_OTP_LOCK_ADDR_START) && (u32Addr < EFM_OTP_LOCK_ADDR_END)) { + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + /* Set single program mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE); + + /* OTP latch */ + RW_MEM32(u32Addr) = (uint32_t)0UL; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_ERASE_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND); + + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* Recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + } + + return i32Ret; +} + +/** + * @brief Set flash protect area. + * @param [in] u32StartAddr Start address of protect area. + * @param [in] u32EndAddr End address of protect area. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_SetWindowProtectAddr(uint32_t u32StartAddr, uint32_t u32EndAddr) +{ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_ADDR(u32StartAddr)); + DDL_ASSERT(IS_EFM_ADDR(u32EndAddr)); + /* Set protect area start address */ + WRITE_REG32(CM_EFM->FPMTSW, u32StartAddr); + /* Set protect area end address */ + WRITE_REG32(CM_EFM->FPMTEW, u32EndAddr); +} + +/** + * @brief Get unique ID. + * @param [out] pstcUID Unique ID struct + * @retval Returns the value of the unique ID + */ +void EFM_GetUID(stc_efm_unique_id_t *pstcUID) +{ + if (NULL != pstcUID) { + pstcUID->u32UniqueID0 = READ_REG32(CM_EFM->UQID0); + pstcUID->u32UniqueID1 = READ_REG32(CM_EFM->UQID1); + pstcUID->u32UniqueID2 = READ_REG32(CM_EFM->UQID2); + } +} + +/** + * @brief Init REMAP initial structure with default value. + * @param [in] pstcEfmRemapInit specifies the Parameter of REMAP. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EFM_REMAP_StructInit(stc_efm_remap_init_t *pstcEfmRemapInit) +{ + int32_t i32Ret = LL_OK; + if (NULL == pstcEfmRemapInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcEfmRemapInit->u32State = EFM_REMAP_OFF; + pstcEfmRemapInit->u32Addr = 0UL; + pstcEfmRemapInit->u32Size = EFM_REMAP_4K; + } + return i32Ret; +} + +/** + * @brief REMAP initialize. + * @param [in] u8RemapIdx Specifies the remap ID. + * @param [in] pstcEfmRemapInit specifies the Parameter of REMAP. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EFM_REMAP_Init(uint8_t u8RemapIdx, stc_efm_remap_init_t *pstcEfmRemapInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *REMCRx; + + if (NULL == pstcEfmRemapInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_EFM_REMAP_UNLOCK()); + DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx)); + DDL_ASSERT(IS_EFM_REMAP_SIZE(pstcEfmRemapInit->u32Size)); + DDL_ASSERT(IS_EFM_REMAP_ADDR(pstcEfmRemapInit->u32Addr)); + DDL_ASSERT(IS_EFM_REMAP_STATE(pstcEfmRemapInit->u32State)); + if ((pstcEfmRemapInit->u32Addr % (1UL << pstcEfmRemapInit->u32Size)) != 0U) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + REMCRx = &REMCR_REG(u8RemapIdx); + MODIFY_REG32(*REMCRx, EFM_MMF_REMCR_EN | EFM_MMF_REMCR_RMTADDR | EFM_MMF_REMCR_RMSIZE, \ + pstcEfmRemapInit->u32State | pstcEfmRemapInit->u32Addr | pstcEfmRemapInit->u32Size); + } + } + return i32Ret; +} + +/** + * @brief EFM REMAP de-initialize. + * @param None + * @retval None + */ +void EFM_REMAP_DeInit(void) +{ + DDL_ASSERT(IS_EFM_REMAP_UNLOCK()); + + WRITE_REG32(CM_EFM->MMF_REMCR0, 0UL); + WRITE_REG32(CM_EFM->MMF_REMCR1, 0UL); +} + +/** + * @brief Enable or disable REMAP function. + * @param [in] u8RemapIdx Specifies the remap ID. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EFM_REMAP_Cmd(uint8_t u8RemapIdx, en_functional_state_t enNewState) +{ + __IO uint32_t *REMCRx; + + DDL_ASSERT(IS_EFM_REMAP_UNLOCK()); + DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + REMCRx = &REMCR_REG(u8RemapIdx); + if (ENABLE == enNewState) { + SET_REG32_BIT(*REMCRx, EFM_MMF_REMCR_EN); + } else { + CLR_REG32_BIT(*REMCRx, EFM_MMF_REMCR_EN); + } +} + +/** + * @brief Set specified REMAP target address. + * @param [in] u8RemapIdx Specifies the remap ID. + * @param [in] u32Addr Specifies the target address. + * @retval None + */ +void EFM_REMAP_SetAddr(uint8_t u8RemapIdx, uint32_t u32Addr) +{ + __IO uint32_t *REMCRx; + + DDL_ASSERT(IS_EFM_REMAP_UNLOCK()); + DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx)); + DDL_ASSERT(IS_EFM_REMAP_ADDR(u32Addr)); + + REMCRx = &REMCR_REG(u8RemapIdx); + MODIFY_REG32(*REMCRx, EFM_MMF_REMCR_RMTADDR, u32Addr); +} + +/** + * @brief Set specified REMAP size. + * @param [in] u8RemapIdx Specifies the remap ID. + * @param [in] u32Size Specifies the remap size. + * @retval None + */ +void EFM_REMAP_SetSize(uint8_t u8RemapIdx, uint32_t u32Size) +{ + __IO uint32_t *REMCRx; + + DDL_ASSERT(IS_EFM_REMAP_UNLOCK()); + DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx)); + DDL_ASSERT(IS_EFM_REMAP_SIZE(u32Size)); + + REMCRx = &REMCR_REG(u8RemapIdx); + MODIFY_REG32(*REMCRx, EFM_MMF_REMCR_RMSIZE, u32Size); +} + +/** + * @brief Enable efm protect. + * @param [in] u8Level Specifies the protect level. @ref EFM_Protect_Level + * @retval None + */ +void EFM_Protect_Enable(uint8_t u8Level) +{ + uint8_t u8Code[12] = {0}; + + (void)EFM_Program(EFM_SECURITY_ADDR1, u8Code, sizeof(u8Code)); + if (EFM_PROTECT_LEVEL1 == u8Level) { + (void)EFM_ProgramWord(EFM_PROTECT1_ADDR, EFM_PROTECT1_KEY); + } else if (EFM_PROTECT_LEVEL2 == u8Level) { + (void)EFM_ProgramWord(EFM_PROTECT2_ADDR, EFM_PROTECT2_KEY); + } else { + /* rsvd */ + } +} + +/** + * @brief Write the security code. + * @param [in] pu8Buf Specifies the security code. + * @param [in] u32Len Specified the length of the security code. + * @retval int32_t + */ +int32_t EFM_WriteSecurityCode(uint8_t *pu8Buf, uint32_t u32Len) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint32_t u32LoopWords = u32Len >> 2UL; + uint32_t *u32pSource = (uint32_t *)(uint32_t)pu8Buf; + uint32_t *u32pDest = (uint32_t *)EFM_SECURITY_ADDR; + + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_SECURITY_CODE_LEN(u32Len)); + + /* CLear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + /* Set sector erase mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR); + /* Erase */ + RW_MEM32(EFM_SECURITY_ADDR) = 0UL; + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND); + + /* Set single program mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE); + + while (u32LoopWords-- > 0UL) { + /* program data. */ + *u32pDest++ = *u32pSource++; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND); + } + + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* Recover CACHE function */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_EFM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_emb.c b/mcu/lib/src/hc32_ll_emb.c new file mode 100644 index 0000000..78602da --- /dev/null +++ b/mcu/lib/src/hc32_ll_emb.c @@ -0,0 +1,493 @@ +/** + ******************************************************************************* + * @file hc32_ll_emb.c + * @brief This file provides firmware functions to manage the EMB + * (Emergency Brake). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Optimize function: EMB_TMR4_Init + Optimize function: EMB_TMR6_Init + 2023-06-30 CDT Function EMB_TMR4_Init don't call EMB_DeInit + Function EMB_TMR6_Init don't call EMB_DeInit + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_emb.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_EMB EMB + * @brief Emergency Brake Driver Library + * @{ + */ + +#if (LL_EMB_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EMB_Local_Macros EMB Local Macros + * @{ + */ + +/** + * @defgroup EMB_Check_Parameters_Validity EMB Check Parameters Validity + * @{ + */ +#define IS_EMB_GROUP(x) \ +( ((x) == CM_EMB0) || \ + ((x) == CM_EMB1) || \ + ((x) == CM_EMB2) || \ + ((x) == CM_EMB3)) +#define IS_EMB_TMR4_GROUP(x) \ +( ((x) == CM_EMB1) || \ + ((x) == CM_EMB2) || \ + ((x) == CM_EMB3)) +#define IS_EMB_TMR6_GROUP(x) ((x) == CM_EMB0) + +#define IS_EMB_OSC_STAT(x) \ +( ((x) == EMB_OSC_ENABLE) || \ + ((x) == EMB_OSC_DISABLE)) + +#define IS_EMB_TMR4_PWM_W_STAT(x) \ +( ((x) == EMB_TMR4_PWM_W_ENABLE) || \ + ((x) == EMB_TMR4_PWM_W_DISABLE)) + +#define IS_EMB_DETECT_TMR4_PWM_W_LVL(x) \ +( ((x) == EMB_DETECT_TMR4_PWM_W_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR4_PWM_W_BOTH_HIGH)) + +#define IS_EMB_TMR4_PWM_V_STAT(x) \ +( ((x) == EMB_TMR4_PWM_V_ENABLE) || \ + ((x) == EMB_TMR4_PWM_V_DISABLE)) + +#define IS_EMB_DETECT_TMR4_PWM_V_LVL(x) \ +( ((x) == EMB_DETECT_TMR4_PWM_V_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR4_PWM_V_BOTH_HIGH)) + +#define IS_EMB_TMR4_PWM_U_STAT(x) \ +( ((x) == EMB_TMR4_PWM_U_ENABLE) || \ + ((x) == EMB_TMR4_PWM_U_DISABLE)) + +#define IS_EMB_DETECT_TMR4_PWM_U_LVL(x) \ +( ((x) == EMB_DETECT_TMR4_PWM_U_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR4_PWM_U_BOTH_HIGH)) + +#define IS_EMB_CMP1_STAT(x) \ +( ((x) == EMB_CMP1_ENABLE) || \ + ((x) == EMB_CMP1_DISABLE)) + +#define IS_EMB_CMP2_STAT(x) \ +( ((x) == EMB_CMP2_ENABLE) || \ + ((x) == EMB_CMP2_DISABLE)) + +#define IS_EMB_CMP3_STAT(x) \ +( ((x) == EMB_CMP3_ENABLE) || \ + ((x) == EMB_CMP3_DISABLE)) + +#define IS_EMB_PORT1_STAT(x) \ +( ((x) == EMB_PORT1_ENABLE) || \ + ((x) == EMB_PORT1_DISABLE)) + +#define IS_EMB_PORT1_DETECT_LVL(x) \ +( ((x) == EMB_PORT1_DETECT_LVL_LOW) || \ + ((x) == EMB_PORT1_DETECT_LVL_HIGH)) + +#define IS_EMB_PORT1_FILTER_STAT(x) \ +( ((x) == EMB_PORT1_FILTER_ENABLE) || \ + ((x) == EMB_PORT1_FILTER_DISABLE)) + +#define IS_EMB_PORT1_FILTER_DIV(x) (((x) & (~EMB_PORT1_FILTER_CLK_DIV_MASK)) == 0UL) + +#define IS_EMB_TMR6_1_PWM_STAT(x) \ +( ((x) == EMB_TMR6_1_PWM_ENABLE) || \ + ((x) == EMB_TMR6_1_PWM_DISABLE)) + +#define IS_EMB_DETECT_TMR6_1_PWM_LVL(x) \ +( ((x) == EMB_DETECT_TMR6_1_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_1_PWM_BOTH_HIGH)) + +#define IS_EMB_TMR6_2_PWM_STAT(x) \ +( ((x) == EMB_TMR6_2_PWM_ENABLE) || \ + ((x) == EMB_TMR6_2_PWM_DISABLE)) + +#define IS_EMB_DETECT_TMR6_2_PWM_LVL(x) \ +( ((x) == EMB_DETECT_TMR6_2_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_2_PWM_BOTH_HIGH)) + +#define IS_EMB_TMR6_3_PWM_STAT(x) \ +( ((x) == EMB_TMR6_3_PWM_ENABLE) || \ + ((x) == EMB_TMR6_3_PWM_DISABLE)) + +#define IS_EMB_DETECT_TMR6_3_PWM_LVL(x) \ +( ((x) == EMB_DETECT_TMR6_3_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_3_PWM_BOTH_HIGH)) + +#define IS_VALID_EMB_INT(x) \ +( ((x) != 0UL) && \ + (((x) | EMB_INT_ALL) == EMB_INT_ALL)) + +#define IS_EMB_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | EMB_FLAG_ALL) == EMB_FLAG_ALL)) + +/** + * @} + */ + +#define EMB_PORT1_FILTER_CLK_DIV_MASK EMB_PORT1_FILTER_CLK_DIV128 +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup EMB_Global_Functions EMB Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_emb_tmr4_init_t to default values + * @param [out] pstcEmbInit Pointer to a @ref stc_emb_tmr4_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcEmbInit value is NULL. + */ +int32_t EMB_TMR4_StructInit(stc_emb_tmr4_init_t *pstcEmbInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcEmbInit) { + /* OSC */ + pstcEmbInit->stcOsc.u32OscState = EMB_OSC_DISABLE; + + /* CMP */ + pstcEmbInit->stcCmp.u32Cmp1State = EMB_CMP1_DISABLE; + pstcEmbInit->stcCmp.u32Cmp2State = EMB_CMP2_DISABLE; + pstcEmbInit->stcCmp.u32Cmp3State = EMB_CMP3_DISABLE; + + /* Port */ + pstcEmbInit->stcPort.stcPort1.u32PortState = EMB_PORT1_DISABLE; + pstcEmbInit->stcPort.stcPort1.u32PortLevel = EMB_PORT1_DETECT_LVL_HIGH; + pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv = EMB_PORT1_FILTER_CLK_DIV1; + pstcEmbInit->stcPort.stcPort1.u32PortFilterState = EMB_PORT1_FILTER_DISABLE; + + /* PWM */ + pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmState = EMB_TMR4_PWM_U_DISABLE; + pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmLevel = EMB_DETECT_TMR4_PWM_U_BOTH_LOW; + pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmState = EMB_TMR4_PWM_V_DISABLE; + pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmLevel = EMB_DETECT_TMR4_PWM_V_BOTH_LOW; + pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmState = EMB_TMR4_PWM_W_DISABLE; + pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmLevel = EMB_DETECT_TMR4_PWM_W_BOTH_LOW; + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize EMB for TMR4. + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] pstcEmbInit Pointer to a @ref stc_emb_tmr4_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcEmbInit value is NULL. + */ +int32_t EMB_TMR4_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr4_init_t *pstcEmbInit) +{ + uint32_t u32Reg1Value; + uint32_t u32Reg2Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcEmbInit) { + DDL_ASSERT(IS_EMB_TMR4_GROUP(EMBx)); + DDL_ASSERT(IS_EMB_OSC_STAT(pstcEmbInit->stcOsc.u32OscState)); + DDL_ASSERT(IS_EMB_CMP1_STAT(pstcEmbInit->stcCmp.u32Cmp1State)); + DDL_ASSERT(IS_EMB_CMP2_STAT(pstcEmbInit->stcCmp.u32Cmp2State)); + DDL_ASSERT(IS_EMB_CMP3_STAT(pstcEmbInit->stcCmp.u32Cmp3State)); + DDL_ASSERT(IS_EMB_PORT1_STAT(pstcEmbInit->stcPort.stcPort1.u32PortState)); + DDL_ASSERT(IS_EMB_PORT1_DETECT_LVL(pstcEmbInit->stcPort.stcPort1.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT1_FILTER_DIV(pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT1_FILTER_STAT(pstcEmbInit->stcPort.stcPort1.u32PortFilterState)); + DDL_ASSERT(IS_EMB_TMR4_PWM_U_STAT(pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR4_PWM_U_LVL(pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR4_PWM_V_STAT(pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR4_PWM_V_LVL(pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR4_PWM_W_STAT(pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR4_PWM_W_LVL(pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmLevel)); + + /* OSC */ + u32Reg1Value = pstcEmbInit->stcOsc.u32OscState; + u32Reg2Value = 0UL; + + /* PWM */ + u32Reg1Value |= (pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmState | pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmState | \ + pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmState); + u32Reg2Value |= (pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmLevel | pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmLevel | \ + pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmLevel); + + /* CMP */ + u32Reg1Value |= (pstcEmbInit->stcCmp.u32Cmp1State | pstcEmbInit->stcCmp.u32Cmp2State | \ + pstcEmbInit->stcCmp.u32Cmp3State); + + /* PORT */ + u32Reg1Value |= (pstcEmbInit->stcPort.stcPort1.u32PortState | pstcEmbInit->stcPort.stcPort1.u32PortLevel | \ + pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort1.u32PortFilterState); + + WRITE_REG32(EMBx->PWMLV, u32Reg2Value); + WRITE_REG32(EMBx->CTL, u32Reg1Value); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_emb_tmr6_init_t to default values + * @param [out] pstcEmbInit Pointer to a @ref stc_emb_tmr6_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcEmbInit value is NULL. + */ +int32_t EMB_TMR6_StructInit(stc_emb_tmr6_init_t *pstcEmbInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcEmbInit) { + /* OSC */ + pstcEmbInit->stcOsc.u32OscState = EMB_OSC_DISABLE; + + /* CMP */ + pstcEmbInit->stcCmp.u32Cmp1State = EMB_CMP1_DISABLE; + pstcEmbInit->stcCmp.u32Cmp2State = EMB_CMP2_DISABLE; + pstcEmbInit->stcCmp.u32Cmp3State = EMB_CMP3_DISABLE; + + /* Port */ + pstcEmbInit->stcPort.stcPort1.u32PortState = EMB_PORT1_DISABLE; + pstcEmbInit->stcPort.stcPort1.u32PortLevel = EMB_PORT1_DETECT_LVL_HIGH; + pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv = EMB_PORT1_FILTER_CLK_DIV1; + pstcEmbInit->stcPort.stcPort1.u32PortFilterState = EMB_PORT1_FILTER_DISABLE; + + /* PWM */ + pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmLevel = EMB_DETECT_TMR6_1_PWM_BOTH_LOW; + pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmState = EMB_TMR6_1_PWM_DISABLE; + pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmLevel = EMB_DETECT_TMR6_2_PWM_BOTH_LOW; + pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmState = EMB_TMR6_2_PWM_DISABLE; + pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmLevel = EMB_DETECT_TMR6_3_PWM_BOTH_LOW; + pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmState = EMB_TMR6_3_PWM_DISABLE; + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize EMB for TMR6. + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] pstcEmbInit Pointer to a @ref stc_emb_tmr6_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcEmbInit value is NULL. + */ +int32_t EMB_TMR6_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr6_init_t *pstcEmbInit) +{ + uint32_t u32Reg1Value; + uint32_t u32Reg2Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcEmbInit) { + DDL_ASSERT(IS_EMB_TMR6_GROUP(EMBx)); + DDL_ASSERT(IS_EMB_OSC_STAT(pstcEmbInit->stcOsc.u32OscState)); + DDL_ASSERT(IS_EMB_CMP1_STAT(pstcEmbInit->stcCmp.u32Cmp1State)); + DDL_ASSERT(IS_EMB_CMP2_STAT(pstcEmbInit->stcCmp.u32Cmp2State)); + DDL_ASSERT(IS_EMB_CMP3_STAT(pstcEmbInit->stcCmp.u32Cmp3State)); + DDL_ASSERT(IS_EMB_PORT1_STAT(pstcEmbInit->stcPort.stcPort1.u32PortState)); + DDL_ASSERT(IS_EMB_PORT1_DETECT_LVL(pstcEmbInit->stcPort.stcPort1.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT1_FILTER_DIV(pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT1_FILTER_STAT(pstcEmbInit->stcPort.stcPort1.u32PortFilterState)); + DDL_ASSERT(IS_EMB_TMR6_1_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR6_1_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR6_2_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR6_2_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR6_3_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR6_3_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmLevel)); + + /* OSC */ + u32Reg2Value = 0UL; + u32Reg1Value = pstcEmbInit->stcOsc.u32OscState; + + /* PWM */ + u32Reg1Value |= (pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmState | pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmState | \ + pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmState); + u32Reg2Value |= (pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmLevel | pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmLevel | \ + pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmLevel); + + /* CMP */ + u32Reg1Value |= (pstcEmbInit->stcCmp.u32Cmp1State | pstcEmbInit->stcCmp.u32Cmp2State | \ + pstcEmbInit->stcCmp.u32Cmp3State); + + /* PORT */ + u32Reg1Value |= (pstcEmbInit->stcPort.stcPort1.u32PortState | pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv | \ + pstcEmbInit->stcPort.stcPort1.u32PortLevel | pstcEmbInit->stcPort.stcPort1.u32PortFilterState); + + WRITE_REG32(EMBx->PWMLV, u32Reg2Value); + WRITE_REG32(EMBx->CTL, u32Reg1Value); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-Initialize EMB function + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @retval None + */ +void EMB_DeInit(CM_EMB_TypeDef *EMBx) +{ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + + WRITE_REG32(EMBx->SOE, 0x00UL); + WRITE_REG32(EMBx->INTEN, 0x00UL); +} + +/** + * @brief Set the EMB interrupt function + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] u32IntType EMB interrupt source + * This parameter can be any composed value of the macros group @ref EMB_Interrupt. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EMB_IntCmd(CM_EMB_TypeDef *EMBx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + DDL_ASSERT(IS_VALID_EMB_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(EMBx->INTEN, u32IntType); + } else { + CLR_REG32_BIT(EMBx->INTEN, u32IntType); + } +} + +/** + * @brief Get EMB flag status. + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] u32Flag EMB flag + * This parameter can be any composed value(prefix with EMB_FLAG) of the macros group @ref EMB_Flag_State. + * @retval None + * @note This parameter u32Flag prefix with EMB_FLAG(eg EMB_FLAG_CMP) of the macros group @ref EMB_Flag_State. + */ +void EMB_ClearStatus(CM_EMB_TypeDef *EMBx, uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + DDL_ASSERT(IS_EMB_FLAG(u32Flag)); + + SET_REG32_BIT(EMBx->STATCLR, u32Flag); +} + +/** + * @brief Clear EMB flag status. + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] u32Flag EMB flag + * This parameter can be any composed value of the macros group @ref EMB_Flag_State. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EMB_GetStatus(const CM_EMB_TypeDef *EMBx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + DDL_ASSERT(IS_EMB_FLAG(u32Flag)); + + return (READ_REG32_BIT(EMBx->STAT, u32Flag) == 0UL) ? RESET : SET; +} + +/** + * @brief Start/stop EMB brake by software control + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EMB_SWBrake(CM_EMB_TypeDef *EMBx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(EMBx->SOE, enNewState); +} + +/** + * @} + */ + +#endif /* LL_EMB_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_event_port.c b/mcu/lib/src/hc32_ll_event_port.c new file mode 100644 index 0000000..bdb652a --- /dev/null +++ b/mcu/lib/src/hc32_ll_event_port.c @@ -0,0 +1,444 @@ +/** + ******************************************************************************* + * @file hc32_ll_event_port.c + * @brief This file provides firmware functions to manage the Event Port (EP). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-09-30 CDT Modify typo + Modify for new head file + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_event_port.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_EVENT_PORT EVENT_PORT + * @brief Event Port Driver Library + * @{ + */ + +#if (LL_EVENT_PORT_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EP_Local_Macros Event Port Local Macros + * @{ + */ +#define EP_OFFSET (0x1CUL) +#define PEVNTDIR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTDIRR1) + (EP_OFFSET * (x)))) +#define PEVNTIDR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTIDR1) + (EP_OFFSET * (x)))) +#define PEVNTODR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTODR1) + (EP_OFFSET * (x)))) +#define PEVNTORR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTORR1) + (EP_OFFSET * (x)))) +#define PEVNTOSR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTOSR1) + (EP_OFFSET * (x)))) +#define PEVNTRIS_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTRISR1) + (EP_OFFSET * (x)))) +#define PEVNTFAL_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTFALR1) + (EP_OFFSET * (x)))) +#define PEVNTTRGSR_RST_VALUE (0x1FFUL) +#define EP_PIN_MAX (16U) + +/** + * @defgroup EP_Check_Parameters_Validity Event Port Check Parameters Validity + * @{ + */ +/*! Parameter validity check for port group. */ +#define IS_EVENT_PORT(port) \ +( ((port) == EVT_PORT_1) || \ + ((port) == EVT_PORT_2) || \ + ((port) == EVT_PORT_3) || \ + ((port) == EVT_PORT_4)) + +/*! Parameter valid check for event port trigger edge. */ +#define IS_EP_TRIG_EDGE(edge) \ +( ((edge) == EP_TRIG_NONE) || \ + ((edge) == EP_TRIG_FALLING) || \ + ((edge) == EP_TRIG_RISING) || \ + ((edge) == EP_TRIG_BOTH)) + +/*! Parameter valid check for event port initial output state. */ +#define IS_EP_STATE(state) \ +( ((state) == EVT_PIN_RESET) || \ + ((state) == EVT_PIN_SET)) + +/*! Parameter valid check for event port filter function. */ +#define IS_EP_FILTER(filter) \ +( ((filter) == EP_FILTER_OFF) || \ + ((filter) == EP_FILTER_ON)) + +/*! Parameter validity check for pin. */ +#define IS_EVENT_PIN(pin) (((pin) & EVT_PIN_MASK ) != 0x0000U) + +/*! Parameter valid check for event port operation after triggered. */ +#define IS_EP_OPS(ops) \ +( ((ops) == EP_OPS_NONE) || \ + ((ops) == EP_OPS_LOW) || \ + ((ops) == EP_OPS_HIGH) || \ + ((ops) == EP_OPS_TOGGLE)) + +/*! Parameter valid check for event port direction. */ +#define IS_EP_DIR(dir) \ +( ((dir) == EP_DIR_IN) || \ + ((dir) == EP_DIR_OUT)) + +/*! Parameter valid check for event port filter clock div. */ +#define IS_EP_FILTER_CLK(clk) \ +( ((clk) == EP_FCLK_DIV1) || \ + ((clk) == EP_FCLK_DIV8) || \ + ((clk) == EP_FCLK_DIV32) || \ + ((clk) == EP_FCLK_DIV64)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup EP_Global_Functions Event Port Global Functions + * @{ + */ + +/** + * @brief Initialize Event Port. + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP port peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @param [in] pstcEventPortInit Pointer to a stc_ep_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: Event Port initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EP_Init(uint8_t u8EventPort, uint16_t u16EventPin, const stc_ep_init_t *pstcEventPortInit) +{ + uint16_t u16PinPos; + int32_t i32Ret = LL_OK; + + if (NULL == pstcEventPortInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + DDL_ASSERT(IS_EP_OPS(pstcEventPortInit->u32PinTriggerOps)); + DDL_ASSERT(IS_EP_DIR(pstcEventPortInit->u32PinDir)); + DDL_ASSERT(IS_EP_STATE(pstcEventPortInit->enPinState)); + DDL_ASSERT(IS_EP_TRIG_EDGE(pstcEventPortInit->u32Edge)); + DDL_ASSERT(IS_EP_FILTER(pstcEventPortInit->u32Filter)); + DDL_ASSERT(IS_EP_FILTER_CLK(pstcEventPortInit->u32FilterClock)); + + for (u16PinPos = 0U; u16PinPos < EP_PIN_MAX; u16PinPos++) { + if ((u16EventPin & (1UL << u16PinPos)) != 0U) { + /* Direction config */ + if (EP_DIR_OUT == pstcEventPortInit->u32PinDir) { + SET_REG32_BIT(PEVNTDIR_REG(u8EventPort), u16EventPin); + } else { + CLR_REG32_BIT(PEVNTDIR_REG(u8EventPort), u16EventPin); + } + /* Set pin initial output value */ + if (EVT_PIN_SET == pstcEventPortInit->enPinState) { + SET_REG32_BIT(PEVNTODR_REG(u8EventPort), u16EventPin); + } else { + CLR_REG32_BIT(PEVNTODR_REG(u8EventPort), u16EventPin); + } + /* Set Pin operation after triggered */ + (void)EP_SetTriggerOps(u8EventPort, u16EventPin, pstcEventPortInit->u32PinTriggerOps); + /* Set trigger edge */ + (void)EP_SetTriggerEdge(u8EventPort, u16EventPin, pstcEventPortInit->u32Edge); + } + MODIFY_REG32(CM_AOS->PEVNTNFCR, \ + ((AOS_PEVNTNFCR_NFEN1 | AOS_PEVNTNFCR_DIVS1) << (u8EventPort * 8UL)), \ + ((pstcEventPortInit->u32Filter | pstcEventPortInit->u32FilterClock) << (u8EventPort * 8UL))); + } + } + return i32Ret; +} + +/** + * @brief De-init Event Port register to default value + * @param None + * @retval None + */ +void EP_DeInit(void) +{ + uint8_t u8EventPort; + + /* Restore all registers to default value */ + WRITE_REG32(CM_AOS->PEVNT_TRGSEL12, PEVNTTRGSR_RST_VALUE); + WRITE_REG32(CM_AOS->PEVNT_TRGSEL34, PEVNTTRGSR_RST_VALUE); + WRITE_REG32(CM_AOS->PEVNTNFCR, 0UL); + for (u8EventPort = EVT_PORT_1; u8EventPort < EVT_PORT_4; u8EventPort++) { + WRITE_REG32(PEVNTDIR_REG(u8EventPort), 0UL); + WRITE_REG32(PEVNTODR_REG(u8EventPort), 0UL); + WRITE_REG32(PEVNTORR_REG(u8EventPort), 0UL); + WRITE_REG32(PEVNTOSR_REG(u8EventPort), 0UL); + WRITE_REG32(PEVNTRIS_REG(u8EventPort), 0UL); + WRITE_REG32(PEVNTFAL_REG(u8EventPort), 0UL); + } +} + +/** + * @brief Initialize Event Port config structure. Fill each pstcEventPortInit with default value + * @param [in] pstcEventPortInit: Pointer to a stc_ep_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: Event Port structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EP_StructInit(stc_ep_init_t *pstcEventPortInit) +{ + int32_t i32Ret = LL_OK; + /* Check if pointer is NULL */ + if (NULL == pstcEventPortInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Reset Event Port init structure parameters values */ + pstcEventPortInit->u32PinDir = EP_DIR_IN; + pstcEventPortInit->enPinState = EVT_PIN_RESET; + pstcEventPortInit->u32PinTriggerOps = EP_OPS_NONE; + pstcEventPortInit->u32Edge = EP_TRIG_NONE; + pstcEventPortInit->u32Filter = EP_FILTER_OFF; + pstcEventPortInit->u32FilterClock = EP_FCLK_DIV1; + } + return i32Ret; +} + +/** + * @brief Set event port trigger edge. + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP port peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @param [in] u32Edge: Trigger edge, @ref EP_Trigger_Sel for details + * @retval int32_t: + * - LL_OK: Trigger edge set successful + * - LL_ERR_INVD_PARAM: Undefined edge + */ +int32_t EP_SetTriggerEdge(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Edge) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + DDL_ASSERT(IS_EP_TRIG_EDGE(u32Edge)); + + /* Set trigger edge */ + switch (u32Edge) { + case EP_TRIG_NONE: + CLR_REG32_BIT(PEVNTFAL_REG(u8EventPort), u16EventPin); + CLR_REG32_BIT(PEVNTRIS_REG(u8EventPort), u16EventPin); + break; + case EP_TRIG_FALLING: + SET_REG32_BIT(PEVNTFAL_REG(u8EventPort), u16EventPin); + CLR_REG32_BIT(PEVNTRIS_REG(u8EventPort), u16EventPin); + break; + case EP_TRIG_RISING: + CLR_REG32_BIT(PEVNTFAL_REG(u8EventPort), u16EventPin); + SET_REG32_BIT(PEVNTRIS_REG(u8EventPort), u16EventPin); + break; + case EP_TRIG_BOTH: + SET_REG32_BIT(PEVNTFAL_REG(u8EventPort), u16EventPin); + SET_REG32_BIT(PEVNTRIS_REG(u8EventPort), u16EventPin); + break; + default: + i32Ret = LL_ERR_INVD_PARAM; + break; + } + return i32Ret; +} + +/** + * @brief Set event port operation after triggered + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @param [in] u32Ops: The operation after triggered, @ref EP_TriggerOps_Sel for details + * @retval Specified Event port pin input value + */ +int32_t EP_SetTriggerOps(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Ops) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + DDL_ASSERT(IS_EP_OPS(u32Ops)); + + switch (u32Ops) { + case EP_OPS_NONE: + CLR_REG32_BIT(PEVNTORR_REG(u8EventPort), u16EventPin); + CLR_REG32_BIT(PEVNTOSR_REG(u8EventPort), u16EventPin); + break; + case EP_OPS_LOW: + SET_REG32_BIT(PEVNTORR_REG(u8EventPort), u16EventPin); + CLR_REG32_BIT(PEVNTOSR_REG(u8EventPort), u16EventPin); + break; + case EP_OPS_HIGH: + CLR_REG32_BIT(PEVNTORR_REG(u8EventPort), u16EventPin); + SET_REG32_BIT(PEVNTOSR_REG(u8EventPort), u16EventPin); + break; + case EP_OPS_TOGGLE: + SET_REG32_BIT(PEVNTORR_REG(u8EventPort), u16EventPin); + SET_REG32_BIT(PEVNTOSR_REG(u8EventPort), u16EventPin); + break; + default: + i32Ret = LL_ERR_INVD_PARAM; + break; + } + return i32Ret; +} + +/** + * @brief Read specified Event port input data port pins + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @retval Specified Event port pin input value + */ +en_ep_state_t EP_ReadInputPins(uint8_t u8EventPort, uint16_t u16EventPin) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + + return ((READ_REG32(PEVNTIDR_REG(u8EventPort)) & (u16EventPin)) != 0UL) ? EVT_PIN_SET : EVT_PIN_RESET; +} + +/** + * @brief Read specified Event port input data port + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the Event Port peripheral + * @retval Specified Event Port input value + */ +uint16_t EP_ReadInputPort(uint8_t u8EventPort) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + + return (uint16_t)(READ_REG32(PEVNTIDR_REG(u8EventPort)) & 0xFFFFUL); +} + +/** + * @brief Read specified Event port output data port pins + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @retval Specified Event port pin output value + */ +en_ep_state_t EP_ReadOutputPins(uint8_t u8EventPort, uint16_t u16EventPin) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + + return ((READ_REG32(PEVNTODR_REG(u8EventPort)) & (u16EventPin)) != 0UL) ? EVT_PIN_SET : EVT_PIN_RESET; +} + +/** + * @brief Read specified Event port output data port + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the Event Port peripheral + * @retval Specified Event Port output value + */ +uint16_t EP_ReadOutputPort(uint8_t u8EventPort) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + + return (uint16_t)(READ_REG32(PEVNTODR_REG(u8EventPort)) & 0xFFFFUL); +} + +/** + * @brief Set specified Event port output data port pins + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @retval None + */ +void EP_SetPins(uint8_t u8EventPort, uint16_t u16EventPin) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + + SET_REG32_BIT(PEVNTODR_REG(u8EventPort), u16EventPin); +} + +/** + * @brief Reset specified Event port output data port pins + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @retval None + */ +void EP_ResetPins(uint8_t u8EventPort, uint16_t u16EventPin) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + + CLR_REG32_BIT(PEVNTODR_REG(u8EventPort), u16EventPin); +} + +/** + * @brief Set specified Event port pins direction + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @param [in] u32Dir: Pin direction + * @arg EP_DIR_IN + * @arg EP_DIR_OUT + * @retval None + */ +void EP_SetDir(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Dir) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + DDL_ASSERT(IS_EP_DIR(u32Dir)); + + if (EP_DIR_OUT == u32Dir) { + SET_REG32_BIT(PEVNTDIR_REG(u8EventPort), u16EventPin); + } else { + CLR_REG32_BIT(PEVNTDIR_REG(u8EventPort), u16EventPin); + } +} + +/** + * @} + */ + +#endif /* LL_EVENT_PORT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_fcg.c b/mcu/lib/src/hc32_ll_fcg.c new file mode 100644 index 0000000..9c644e9 --- /dev/null +++ b/mcu/lib/src/hc32_ll_fcg.c @@ -0,0 +1,194 @@ +/** + ******************************************************************************* + * @file hc32_ll_fcg.c + * @brief This file provides firmware functions to manage the Function Clock + * Gate (FCG). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_fcg.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_FCG FCG + * @brief FCG Driver Library + * @{ + */ + +#if (LL_FCG_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup FCG_Local_Macros FCG Local Macros + * @{ + */ +#define IS_FCG0_UNLOCKED() ((CM_PWC->FCG0PC & PWC_FCG0PC_PRT0) == PWC_FCG0PC_PRT0) + +/** + * @defgroup FCG_Check_Parameters_Validity FCG Check Parameters Validity + * @{ + */ +/* Parameter validity check for peripheral in fcg0. */ +#define IS_FCG0_PERIPH(per) \ +( ((per) != 0x00UL) && \ + (((per) | FCG_FCG0_PERIPH_MASK) == FCG_FCG0_PERIPH_MASK)) + +/* Parameter validity check for peripheral in fcg1. */ +#define IS_FCG1_PERIPH(per) \ +( ((per) != 0x00UL) && \ + (((per) | FCG_FCG1_PERIPH_MASK) == FCG_FCG1_PERIPH_MASK)) + +/* Parameter validity check for peripheral in fcg2. */ +#define IS_FCG2_PERIPH(per) \ +( ((per) != 0x00UL) && \ + (((per) | FCG_FCG2_PERIPH_MASK) == FCG_FCG2_PERIPH_MASK)) + +/* Parameter validity check for peripheral in fcg3. */ +#define IS_FCG3_PERIPH(per) \ +( ((per) != 0x00UL) && \ + (((per) | FCG_FCG3_PERIPH_MASK) == FCG_FCG3_PERIPH_MASK)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup FCG_Global_Functions FCG Global Functions + * @{ + */ + +/** + * @brief Enable or disable the FCG0 peripheral clock. + * @param [in] u32Fcg0Periph The peripheral in FCG0 @ref FCG_FCG0_Peripheral. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCG_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FCG0_PERIPH(u32Fcg0Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_FCG0_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_PWC->FCG0, u32Fcg0Periph); + } else { + SET_REG32_BIT(CM_PWC->FCG0, u32Fcg0Periph); + } +} + +/** + * @brief Enable or disable the FCG1 peripheral clock. + * @param [in] u32Fcg1Periph The peripheral in FCG1 @ref FCG_FCG1_Peripheral. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCG_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FCG1_PERIPH(u32Fcg1Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_PWC->FCG1, u32Fcg1Periph); + } else { + SET_REG32_BIT(CM_PWC->FCG1, u32Fcg1Periph); + } +} + +/** + * @brief Enable or disable the FCG2 peripheral clock. + * @param [in] u32Fcg2Periph The peripheral in FCG2 @ref FCG_FCG2_Peripheral. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCG_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FCG2_PERIPH(u32Fcg2Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_PWC->FCG2, u32Fcg2Periph); + } else { + SET_REG32_BIT(CM_PWC->FCG2, u32Fcg2Periph); + } +} + +/** + * @brief Enable or disable the FCG3 peripheral clock. + * @param [in] u32Fcg3Periph The peripheral in FCG3 @ref FCG_FCG3_Peripheral. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCG_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FCG3_PERIPH(u32Fcg3Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_PWC->FCG3, u32Fcg3Periph); + } else { + SET_REG32_BIT(CM_PWC->FCG3, u32Fcg3Periph); + } +} + +#endif /* LL_FCG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_fcm.c b/mcu/lib/src/hc32_ll_fcm.c new file mode 100644 index 0000000..80eddfe --- /dev/null +++ b/mcu/lib/src/hc32_ll_fcm.c @@ -0,0 +1,388 @@ +/** + ******************************************************************************* + * @file hc32_ll_fcm.c + * @brief This file provides firmware functions to manage the Frequency Clock + * Measurement (FCM). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-10-31 CDT Modify parameter check for reference clock source + 2023-06-30 CDT Modify API FCM_DeInit() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_fcm.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_FCM FCM + * @brief FCM Driver Library + * @{ + */ + +#if (LL_FCM_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup FCM_Local_Macros FCM Local Macros + * @{ + */ + +/* FCM Registers RESET Value */ +#define FCM_REG_RST_VALUE (0x00000000UL) + +/* FCM interrupt mask */ +#define FCM_INT_MASK (FCM_INT_OVF | FCM_INT_END | FCM_INT_ERR) +/* FCM status flag mask */ +#define FCM_FLAG_MASK (FCM_SR_ERRF | FCM_SR_MENDF | FCM_SR_OVF) + +/** + * @defgroup FCM_Check_Parameters_Validity FCM Check Parameters Validity + * @{ + */ + +/* Parameter validity check for FCM target and reference clock source. */ +#define IS_FCM_TARGET_SRC(x) \ +( ((x) == FCM_TARGET_CLK_XTAL) || \ + ((x) == FCM_TARGET_CLK_XTAL32) || \ + ((x) == FCM_TARGET_CLK_HRC) || \ + ((x) == FCM_TARGET_CLK_LRC) || \ + ((x) == FCM_TARGET_CLK_SWDTLRC) || \ + ((x) == FCM_TARGET_CLK_PCLK1) || \ + ((x) == FCM_TARGET_CLK_UPLLP) || \ + ((x) == FCM_TARGET_CLK_MRC) || \ + ((x) == FCM_TARGET_CLK_MPLLP)) + +#define IS_FCM_REF_SRC(x) \ +( ((x) == FCM_REF_CLK_EXTCLK) || \ + ((x) == FCM_REF_CLK_XTAL) || \ + ((x) == FCM_REF_CLK_XTAL32) || \ + ((x) == FCM_REF_CLK_HRC) || \ + ((x) == FCM_REF_CLK_LRC) || \ + ((x) == FCM_REF_CLK_SWDTLRC) || \ + ((x) == FCM_REF_CLK_PCLK1) || \ + ((x) == FCM_REF_CLK_UPLLP) || \ + ((x) == FCM_REF_CLK_MRC) || \ + ((x) == FCM_REF_CLK_MPLLP)) + +/* Parameter validity check for FCM target clock division. */ +#define IS_FCM_TARGET_DIV(x) \ +( ((x) == FCM_TARGET_CLK_DIV1) || \ + ((x) == FCM_TARGET_CLK_DIV4) || \ + ((x) == FCM_TARGET_CLK_DIV8) || \ + ((x) == FCM_TARGET_CLK_DIV32)) + +/* Parameter validity check for FCM external reference input function. */ +#define IS_FCM_EXT_REF_FUNC(x) \ +( ((x) == FCM_EXT_REF_OFF) || \ + ((x) == FCM_EXT_REF_ON)) + +/* Parameter validity check for FCM reference clock edge. */ +#define IS_FCM_REF_EDGE(x) \ +( ((x) == FCM_REF_CLK_RISING) || \ + ((x) == FCM_REF_CLK_FALLING) || \ + ((x) == FCM_REF_CLK_BOTH)) + +/* Parameter validity check for FCM digital filter function. */ +#define IS_FCM_DIG_FILTER(x) \ +( ((x) == FCM_DIG_FILTER_OFF) || \ + ((x) == FCM_DIG_FILTER_DIV1) || \ + ((x) == FCM_DIG_FILTER_DIV4) || \ + ((x) == FCM_DIG_FILTER_DIV16)) + +/* Parameter validity check for FCM reference clock division. */ +#define IS_FCM_REF_DIV(x) \ +( ((x) == FCM_REF_CLK_DIV32) || \ + ((x) == FCM_REF_CLK_DIV128) || \ + ((x) == FCM_REF_CLK_DIV1024) || \ + ((x) == FCM_REF_CLK_DIV8192)) + +/* Parameter validity check for FCM exception type function. */ +#define IS_FCM_EXP_TYPE(x) \ +( ((x) == FCM_EXP_TYPE_INT) || \ + ((x) == FCM_EXP_TYPE_RST)) + +/* Parameter validity check for FCM interrupt. */ +#define IS_FCM_INT(x) (((x) | FCM_INT_MASK) == FCM_INT_MASK) + +/* Parameter validity check for FCM flag state. */ +#define IS_FCM_FLAG(x) \ +( ((x) != 0x00UL) && \ + (((x) | FCM_FLAG_MASK) == FCM_FLAG_MASK)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup FCM_Global_Functions FCM Global Functions + * @{ + */ + +/** + * @brief Initialize FCM. + * @param [in] pstcFcmInit Pointer to a @ref stc_fcm_init_t structure + * that contains configuration information. + * @retval int32_t: + * - LL_OK: FCM initialize successful + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t FCM_Init(const stc_fcm_init_t *pstcFcmInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcFcmInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameter validity checking */ + DDL_ASSERT(IS_FCM_TARGET_SRC(pstcFcmInit->u32TargetClock)); + DDL_ASSERT(IS_FCM_TARGET_DIV(pstcFcmInit->u32TargetClockDiv)); + DDL_ASSERT(IS_FCM_EXT_REF_FUNC(pstcFcmInit->u32ExtRefClockEnable)); + DDL_ASSERT(IS_FCM_REF_EDGE(pstcFcmInit->u32RefClockEdge)); + DDL_ASSERT(IS_FCM_DIG_FILTER(pstcFcmInit->u32DigitalFilter)); + DDL_ASSERT(IS_FCM_REF_SRC(pstcFcmInit->u32RefClock)); + DDL_ASSERT(IS_FCM_REF_DIV(pstcFcmInit->u32RefClockDiv)); + DDL_ASSERT(IS_FCM_EXP_TYPE(pstcFcmInit->u32ExceptionType)); + + WRITE_REG32(CM_FCM->LVR, pstcFcmInit->u16LowerLimit); + WRITE_REG32(CM_FCM->UVR, pstcFcmInit->u16UpperLimit); + WRITE_REG32(CM_FCM->MCCR, (pstcFcmInit->u32TargetClock | pstcFcmInit->u32TargetClockDiv)); + WRITE_REG32(CM_FCM->RCCR, (pstcFcmInit->u32ExtRefClockEnable | pstcFcmInit->u32RefClockEdge | + pstcFcmInit->u32DigitalFilter | pstcFcmInit->u32RefClock | + pstcFcmInit->u32RefClockDiv)); + MODIFY_REG32(CM_FCM->RIER, FCM_RIER_ERRINTRS, pstcFcmInit->u32ExceptionType); + } + return i32Ret; +} + +/** + * @brief Initialize FCM structure. Fill each pstcFcmInit with default value. + * @param [in] pstcFcmInit Pointer to a @ref stc_fcm_init_t structure + * that contains configuration information. + * @retval int32_t: + * - LL_OK: FCM structure initialize successful + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t FCM_StructInit(stc_fcm_init_t *pstcFcmInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcFcmInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* RESET FCM init structure parameters values */ + pstcFcmInit->u16LowerLimit = 0U; + pstcFcmInit->u16UpperLimit = 0U; + pstcFcmInit->u32TargetClock = FCM_TARGET_CLK_XTAL; + pstcFcmInit->u32TargetClockDiv = FCM_TARGET_CLK_DIV1; + pstcFcmInit->u32ExtRefClockEnable = FCM_EXT_REF_OFF; + pstcFcmInit->u32RefClockEdge = FCM_REF_CLK_RISING; + pstcFcmInit->u32DigitalFilter = FCM_DIG_FILTER_OFF; + pstcFcmInit->u32RefClock = FCM_REF_CLK_XTAL; + pstcFcmInit->u32RefClockDiv = FCM_REF_CLK_DIV32; + pstcFcmInit->u32ExceptionType = FCM_EXP_TYPE_INT; + } + return i32Ret; +} + +/** + * @brief De-Initialize FCM. + * @param None + * @retval int32_t: + * - LL_OK: De-Initialize success. + */ +int32_t FCM_DeInit(void) +{ + WRITE_REG32(CM_FCM->STR, FCM_REG_RST_VALUE); + WRITE_REG32(CM_FCM->CLR, FCM_FLAG_MASK); + WRITE_REG32(CM_FCM->LVR, FCM_REG_RST_VALUE); + WRITE_REG32(CM_FCM->UVR, FCM_REG_RST_VALUE); + WRITE_REG32(CM_FCM->MCCR, FCM_REG_RST_VALUE); + WRITE_REG32(CM_FCM->RCCR, FCM_REG_RST_VALUE); + WRITE_REG32(CM_FCM->RIER, FCM_REG_RST_VALUE); + return LL_OK; +} + +/** + * @brief Get FCM state, get FCM overflow, complete, error flag. + * @param [in] u32Flag FCM flags.This parameter can be one or any + * combination of the following values: @ref FCM_Flag_Sel + * @arg FCM_FLAG_ERR: FCM error. + * @arg FCM_FLAG_END: FCM measure end. + * @arg FCM_FLAG_OVF: FCM overflow. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t FCM_GetStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_FCM_FLAG(u32Flag)); + + return ((READ_REG32_BIT(CM_FCM->SR, u32Flag) != 0UL) ? SET : RESET); +} + +/** + * @brief Clear FCM state, Clear FCM overflow, complete, error flag. + * @param [in] u32Flag FCM flags.This parameter can be one or any + * combination of the following values: @ref FCM_Flag_Sel + * @arg FCM_FLAG_ERR: FCM error. + * @arg FCM_FLAG_END: FCM measure end. + * @arg FCM_FLAG_OVF: FCM overflow. + * @retval None. + */ +void FCM_ClearStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_FCM_FLAG(u32Flag)); + + SET_REG32_BIT(CM_FCM->CLR, u32Flag); +} + +/** + * @brief Get FCM counter value. + * @param None + * @retval FCM counter value. + */ +uint16_t FCM_GetCountValue(void) +{ + return (uint16_t)(READ_REG32(CM_FCM->CNTR) & 0xFFFFU); +} + +/** + * @brief FCM target clock type and division config. + * @param [in] u32ClockSrc Target clock type. @ref FCM_Target_Clock_Src + * @param [in] u32Div Target clock division. @ref FCM_Target_Clock_Div + * @arg FCM_TARGET_CLK_DIV1 + * @arg FCM_TARGET_CLK_DIV4 + * @arg FCM_TARGET_CLK_DIV8 + * @arg FCM_TARGET_CLK_DIV32 + * @retval None. + */ +void FCM_SetTargetClock(uint32_t u32ClockSrc, uint32_t u32Div) +{ + DDL_ASSERT(IS_FCM_TARGET_SRC(u32ClockSrc)); + DDL_ASSERT(IS_FCM_TARGET_DIV(u32Div)); + WRITE_REG32(CM_FCM->MCCR, (u32ClockSrc | u32Div)); +} + +/** + * @brief FCM reference clock type and division config. + * @param [in] u32ClockSrc Reference clock type. @ref FCM_Ref_Clock_Src + * @param [in] u32Div Reference clock division. @ref FCM_Ref_Clock_Div + * @arg FCM_REF_CLK_DIV32 + * @arg FCM_REF_CLK_DIV128 + * @arg FCM_REF_CLK_DIV1024 + * @arg FCM_REF_CLK_DIV8192 + * @retval None. + */ +void FCM_SetRefClock(uint32_t u32ClockSrc, uint32_t u32Div) +{ + DDL_ASSERT(IS_FCM_REF_SRC(u32ClockSrc)); + DDL_ASSERT(IS_FCM_REF_DIV(u32Div)); + MODIFY_REG32(CM_FCM->RCCR, (FCM_RCCR_INEXS | FCM_RCCR_RCKS | FCM_RCCR_RDIVS), (u32ClockSrc | u32Div)); +} + +/** + * @brief Enable or disable the FCM reset + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCM_ResetCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_FCM->RIER_b.ERRE, enNewState); +} + +/** + * @brief Enable or disable the FCM interrupt + * @param [in] u32IntType The FCM interrupt type. This parameter can be + * one or any combination @ref FCM_Int_Type + * @arg FCM_INT_OVF: FCM overflow interrupt + * @arg FCM_INT_END: FCM calculate end interrupt + * @arg FCM_INT_ERR: FCM frequency abnormal interrupt + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCM_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FCM_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_FCM->RIER, u32IntType); + } else { + CLR_REG32_BIT(CM_FCM->RIER, u32IntType); + } +} + +/** + * @brief FCM function config. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None. + */ +void FCM_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(bCM_FCM->STR_b.START, enNewState); +} + +/** + * @} + */ + +#endif /* LL_FCM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_gpio.c b/mcu/lib/src/hc32_ll_gpio.c new file mode 100644 index 0000000..8d072d2 --- /dev/null +++ b/mcu/lib/src/hc32_ll_gpio.c @@ -0,0 +1,706 @@ +/** + ******************************************************************************* + * @file hc32_ll_gpio.c + * @brief This file provides firmware functions to manage the General Purpose + * Input/Output(GPIO). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Add API GPIO_AnalogCmd() and GPIO_ExIntCmd() + 2023-06-30 CDT Modify GPIO_SetFunc() + Rename GPIO_ExIntCmd() as GPIO_ExtIntCmd + Optimize API: GPIO_Init(), GPIO_SetFunc(), GPIO_SubFuncCmd(), GPIO_InputMOSCmd(), GPIO_AnalogCmd(), GPIO_ExtIntCmd() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_gpio.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_GPIO GPIO + * @brief GPIO Driver Library + * @{ + */ + +#if (LL_GPIO_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup GPIO_Local_Types GPIO Local Typedefs + * @{ + */ +/** + * @brief GPIO port pin table definition + */ +typedef struct { + uint8_t u8Port; /*!< GPIO Port Source, @ref GPIO_Port_Source for details */ + uint16_t u16PinMask; /*!< Pin active or inactive, @ref GPIO_All_Pins_Define for details */ +} stc_gpio_port_pin_tbl_t; +/** + * @} + */ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup GPIO_Local_Macros GPIO Local Macros + * @{ + */ +/** + * @defgroup GPIO_Registers_Setting_definition GPIO Registers setting definition + * @{ + */ +#define GPIO_PSPCR_RST_VALUE (0x001FU) +#define GPIO_PCCR_RST_VALUE (0x4000U) +#define GPIO_PINAER_RST_VALUE (0x0000U) +#define GPIO_PIN_NUM_MAX (16U) +#define GPIO_PORT_OFFSET (0x40UL) +#define GPIO_PIN_OFFSET (0x04UL) +#define GPIO_REG_OFFSET (0x10UL) +#define GPIO_REG_TYPE uint16_t +#define GPIO_PIDR_BASE ((uint32_t)(&CM_GPIO->PIDRA)) +#define GPIO_PODR_BASE ((uint32_t)(&CM_GPIO->PODRA)) +#define GPIO_POSR_BASE ((uint32_t)(&CM_GPIO->POSRA)) +#define GPIO_PORR_BASE ((uint32_t)(&CM_GPIO->PORRA)) +#define GPIO_POTR_BASE ((uint32_t)(&CM_GPIO->POTRA)) +#define GPIO_POER_BASE ((uint32_t)(&CM_GPIO->POERA)) +#define GPIO_PCR_BASE ((uint32_t)(&CM_GPIO->PCRA0)) +#define GPIO_PFSR_BASE ((uint32_t)(&CM_GPIO->PFSRA0)) + +#define PIDR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_PIDR_BASE + GPIO_REG_OFFSET * (x))) +#define PODR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_PODR_BASE + GPIO_REG_OFFSET * (x))) +#define POSR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_POSR_BASE + GPIO_REG_OFFSET * (x))) +#define PORR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_PORR_BASE + GPIO_REG_OFFSET * (x))) +#define POTR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_POTR_BASE + GPIO_REG_OFFSET * (x))) +#define POER_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_POER_BASE + GPIO_REG_OFFSET * (x))) +#define PCR_REG(x, y) (*(__IO uint16_t *)(GPIO_PCR_BASE + (uint32_t)((x) * GPIO_PORT_OFFSET) + (y) * GPIO_PIN_OFFSET)) +#define PFSR_REG(x, y) (*(__IO uint16_t *)(GPIO_PFSR_BASE + (uint32_t)((x) * GPIO_PORT_OFFSET) + (y) * GPIO_PIN_OFFSET)) +/** + * @} + */ + +/** + * @defgroup GPIO_Check_Parameters_Validity GPIO Check Parameters Validity + * @{ + */ +/*! Parameter validity check for pin state. */ +#define IS_GPIO_PIN_STATE(state) \ +( ((state) == PIN_STAT_RST) || \ + ((state) == PIN_STAT_SET)) + +/*! Parameter validity check for pin direction. */ +#define IS_GPIO_DIR(dir) \ +( ((dir) == PIN_DIR_IN) || \ + ((dir) == PIN_DIR_OUT)) + +/*! Parameter validity check for pin output type. */ +#define IS_GPIO_OUT_TYPE(type) \ +( ((type) == PIN_OUT_TYPE_CMOS) || \ + ((type) == PIN_OUT_TYPE_NMOS)) + +/*! Parameter validity check for pin driver capacity. */ +#define IS_GPIO_PIN_DRV(drv) \ +( ((drv) == PIN_LOW_DRV) || \ + ((drv) == PIN_MID_DRV) || \ + ((drv) == PIN_HIGH_DRV)) + +/*! Parameter validity check for pin attribute. */ +#define IS_GPIO_ATTR(attr) \ +( ((attr) == PIN_ATTR_DIGITAL) || \ + ((attr) == PIN_ATTR_ANALOG)) + +/*! Parameter validity check for pin latch function. */ +#define IS_GPIO_LATCH(latch) \ +( ((latch) == PIN_LATCH_OFF) || \ + ((latch) == PIN_LATCH_ON)) + +/*! Parameter validity check for internal pull-up resistor. */ +#define IS_GPIO_PIN_PU(pu) \ +( ((pu) == PIN_PU_OFF) || \ + ((pu) == PIN_PU_ON)) + +/*! Parameter validity check for pin state invert. */ +#define IS_GPIO_PIN_INVERT(invert) \ +( ((invert) == PIN_INVT_OFF) || \ + ((invert) == PIN_INVT_ON)) + +/*! Parameter validity check for external interrupt function. */ +#define IS_GPIO_EXTINT(extint) \ +( ((extint) == PIN_EXTINT_OFF) || \ + ((extint) == PIN_EXTINT_ON)) + +/*! Parameter validity check for pin number. */ +#define IS_GPIO_PIN(pin) \ +( ((pin) != 0U) && \ + (((pin) & GPIO_PIN_ALL) != 0U)) + +/*! Parameter validity check for port source. */ +#define IS_GPIO_PORT(port) \ +( ((port) == GPIO_PORT_A) || \ + ((port) == GPIO_PORT_B) || \ + ((port) == GPIO_PORT_C) || \ + ((port) == GPIO_PORT_D) || \ + ((port) == GPIO_PORT_E) || \ + ((port) == GPIO_PORT_H)) + +/*! Parameter validity check for pin function. */ +#define IS_GPIO_FUNC(func) \ +( ((func) <= GPIO_FUNC_15) || \ + (((func) >= GPIO_FUNC_32) && ((func) <= GPIO_FUNC_59))) + +/*! Parameter validity check for debug pin definition. */ +#define IS_GPIO_DEBUG_PORT(port) \ +( ((port) != 0U) && \ + (((port) | GPIO_PIN_DEBUG) == GPIO_PIN_DEBUG)) + +/*! Parameter validity check for pin read wait cycle. */ +#define IS_GPIO_READ_WAIT(wait) \ +( ((wait) == GPIO_RD_WAIT0) || \ + ((wait) == GPIO_RD_WAIT1) || \ + ((wait) == GPIO_RD_WAIT2) || \ + ((wait) == GPIO_RD_WAIT3)) + +/* Check GPIO register lock status. */ +#define IS_GPIO_UNLOCK() (GPIO_PWPR_WE == (CM_GPIO->PWPR & GPIO_PWPR_WE)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup GPIO_Local_Variables GPIO Local Variables + * @{ + */ +static const stc_gpio_port_pin_tbl_t m_astcGpioPortPinTbl[] = { + {GPIO_PORT_A, GPIO_PIN_A_ALL}, + {GPIO_PORT_B, GPIO_PIN_B_ALL}, + {GPIO_PORT_C, GPIO_PIN_C_ALL}, + {GPIO_PORT_D, GPIO_PIN_D_ALL}, + {GPIO_PORT_E, GPIO_PIN_E_ALL}, + {GPIO_PORT_H, GPIO_PIN_H_ALL}, + +}; +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup GPIO_Global_Functions GPIO Global Functions + * @{ + */ + +/** + * @brief Initialize GPIO. + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] pstcGpioInit: Pointer to a stc_gpio_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: GPIO initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t GPIO_Init(uint8_t u8Port, uint16_t u16Pin, const stc_gpio_init_t *pstcGpioInit) +{ + uint8_t u8PinPos; + uint16_t u16PCRVal; + uint16_t u16PCRMask; + int32_t i32Ret = LL_OK; + __IO uint16_t *PCRx; + + /* Check if pointer is NULL */ + if (NULL == pstcGpioInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_UNLOCK()); + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + DDL_ASSERT(IS_GPIO_PIN_STATE(pstcGpioInit->u16PinState)); + DDL_ASSERT(IS_GPIO_DIR(pstcGpioInit->u16PinDir)); + DDL_ASSERT(IS_GPIO_OUT_TYPE(pstcGpioInit->u16PinOutputType)); + DDL_ASSERT(IS_GPIO_PIN_DRV(pstcGpioInit->u16PinDrv)); + DDL_ASSERT(IS_GPIO_LATCH(pstcGpioInit->u16Latch)); + DDL_ASSERT(IS_GPIO_PIN_PU(pstcGpioInit->u16PullUp)); + DDL_ASSERT(IS_GPIO_PIN_INVERT(pstcGpioInit->u16Invert)); + DDL_ASSERT(IS_GPIO_EXTINT(pstcGpioInit->u16ExtInt)); + DDL_ASSERT(IS_GPIO_ATTR(pstcGpioInit->u16PinAttr)); + + for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) { + if ((u16Pin & 1U) != 0U) { + u16PCRVal = pstcGpioInit->u16PinState | pstcGpioInit->u16PinDir | pstcGpioInit->u16PinOutputType | \ + pstcGpioInit->u16PinDrv | pstcGpioInit->u16PullUp | pstcGpioInit->u16Invert | \ + pstcGpioInit->u16ExtInt | pstcGpioInit->u16Latch; + + u16PCRMask = GPIO_PCR_POUT | GPIO_PCR_POUTE | GPIO_PCR_NOD | \ + GPIO_PCR_DRV | GPIO_PCR_PUU | GPIO_PCR_INVE | \ + GPIO_PCR_INTE | GPIO_PCR_LTE ; + u16PCRVal |= pstcGpioInit->u16PinAttr; + u16PCRMask |= GPIO_PCR_DDIS; + + PCRx = &PCR_REG(u8Port, u8PinPos); + MODIFY_REG16(*PCRx, u16PCRMask, u16PCRVal); + } + u16Pin >>= 1U; + if (0U == u16Pin) { + break; + } + } + } + return i32Ret; +} + +/** + * @brief De-init GPIO register to default value + * @param None + * @retval None + */ +void GPIO_DeInit(void) +{ + stc_gpio_init_t stcGpioInit; + uint8_t i; + DDL_ASSERT(IS_GPIO_UNLOCK()); + + (void)GPIO_StructInit(&stcGpioInit); + + for (i = 0U; i < ARRAY_SZ(m_astcGpioPortPinTbl); i++) { + (void)GPIO_Init(m_astcGpioPortPinTbl[i].u8Port, m_astcGpioPortPinTbl[i].u16PinMask, &stcGpioInit); + } + /* GPIO global register reset */ + WRITE_REG16(CM_GPIO->PSPCR, GPIO_PSPCR_RST_VALUE); + WRITE_REG16(CM_GPIO->PCCR, GPIO_PCCR_RST_VALUE); + + WRITE_REG16(CM_GPIO->PINAER, GPIO_PINAER_RST_VALUE); +} + +/** + * @brief Initialize GPIO config structure. Fill each pstcGpioInit with default value + * @param [in] pstcGpioInit: Pointer to a stc_gpio_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: GPIO structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t GPIO_StructInit(stc_gpio_init_t *pstcGpioInit) +{ + int32_t i32Ret = LL_OK; + /* Check if pointer is NULL */ + if (NULL == pstcGpioInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Reset GPIO init structure parameters values */ + pstcGpioInit->u16PinState = PIN_STAT_RST; + pstcGpioInit->u16PinDir = PIN_DIR_IN; + pstcGpioInit->u16PinDrv = PIN_LOW_DRV; + pstcGpioInit->u16PinAttr = PIN_ATTR_DIGITAL; + + pstcGpioInit->u16Latch = PIN_LATCH_OFF; + pstcGpioInit->u16PullUp = PIN_PU_OFF; + pstcGpioInit->u16Invert = PIN_INVT_OFF; + pstcGpioInit->u16ExtInt = PIN_EXTINT_OFF; + pstcGpioInit->u16PinOutputType = PIN_OUT_TYPE_CMOS; + } + return i32Ret; +} + +/** + * @brief GPIO debug port configure. Set debug pins to GPIO + * @param [in] u8DebugPort: @ref GPIO_DebugPin_Sel for each product + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @arg ENABLE: set to debug port (SWD/JTAG) + * @arg DISABLE: set to GPIO + * @retval None + */ +void GPIO_SetDebugPort(uint8_t u8DebugPort, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_DEBUG_PORT(u8DebugPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + if (ENABLE == enNewState) { + SET_REG16_BIT(CM_GPIO->PSPCR, ((uint16_t)u8DebugPort & GPIO_PSPCR_SPFE)); + } else { + CLR_REG16_BIT(CM_GPIO->PSPCR, ((uint16_t)u8DebugPort & GPIO_PSPCR_SPFE)); + } +} + +/** + * @brief Set specified Port Pin function + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] u16Func: GPIO_FUNC_x, x can be the suffix in @ref GPIO_Function_Sel for each product + * @retval None + */ +void GPIO_SetFunc(uint8_t u8Port, uint16_t u16Pin, uint16_t u16Func) +{ + uint8_t u8PinPos; + __IO uint16_t *PFSRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + DDL_ASSERT(IS_GPIO_FUNC(u16Func)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) { + if ((u16Pin & 1U) != 0U) { + PFSRx = &PFSR_REG(u8Port, u8PinPos); + MODIFY_REG16(*PFSRx, GPIO_PFSR_FSEL, u16Func); + } + u16Pin >>= 1U; + if (0U == u16Pin) { + break; + } + } +} + +/** + * @brief GPIO pin sub-function ENABLE. + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void GPIO_SubFuncCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState) +{ + uint8_t u8PinPos; + __IO uint16_t *PFSRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) { + if ((u16Pin & 1U) != 0U) { + PFSRx = &PFSR_REG(u8Port, u8PinPos); + if (ENABLE == enNewState) { + SET_REG16_BIT(*PFSRx, PIN_SUBFUNC_ENABLE); + } else { + CLR_REG16_BIT(*PFSRx, PIN_SUBFUNC_ENABLE); + } + } + u16Pin >>= 1U; + if (0U == u16Pin) { + break; + } + } +} + +/** + * @brief Set the sub-function, it's a global configuration + * @param [in] u8Func: GPIO_FUNC_x, x can be the suffix in @ref GPIO_Function_Sel for each product + * @retval None + */ +void GPIO_SetSubFunc(uint8_t u8Func) +{ + DDL_ASSERT(IS_GPIO_FUNC(u8Func)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + MODIFY_REG16(CM_GPIO->PCCR, GPIO_PCCR_BFSEL, u8Func); +} + +/** + * @brief GPIO output ENABLE. + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void GPIO_OutputCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState) +{ + __IO GPIO_REG_TYPE *POERx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + POERx = &POER_REG(u8Port); + if (ENABLE == enNewState) { + SET_REG_BIT(*POERx, (GPIO_REG_TYPE)u16Pin); + } else { + CLR_REG_BIT(*POERx, (GPIO_REG_TYPE)u16Pin); + } +} + +/** + * @brief GPIO read wait cycle configure. + * @param [in] u16ReadWait: @ref GPIO_ReadCycle_Sel for each product + * @retval None + */ +void GPIO_SetReadWaitCycle(uint16_t u16ReadWait) +{ + DDL_ASSERT(IS_GPIO_READ_WAIT(u16ReadWait)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + MODIFY_REG16(CM_GPIO->PCCR, GPIO_PCCR_RDWT, u16ReadWait); +} + +/** + * @brief GPIO input MOS always ON configure. + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @arg ENABLE: set input MOS always ON + * @arg DISABLE: set input MOS turns on while read operation + * @retval None + */ +void GPIO_InputMOSCmd(uint8_t u8Port, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + if (ENABLE == enNewState) { + SET_REG16_BIT(CM_GPIO->PINAER, (1UL << u8Port)); + } else { + CLR_REG16_BIT(CM_GPIO->PINAER, (1UL << u8Port)); + } +} + +/** + * @brief Read specified GPIO input data port pins + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @retval Specified GPIO port pin input value + */ +en_pin_state_t GPIO_ReadInputPins(uint8_t u8Port, uint16_t u16Pin) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + return ((READ_REG(PIDR_REG(u8Port)) & (u16Pin)) != 0U) ? PIN_SET : PIN_RESET; +} + +/** + * @brief Read specified GPIO input data port + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @retval Specified GPIO port input value + */ +uint16_t GPIO_ReadInputPort(uint8_t u8Port) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + + return READ_REG(PIDR_REG(u8Port)); +} + +/** + * @brief Read specified GPIO output data port pins + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @retval Specified GPIO port pin output value + */ +en_pin_state_t GPIO_ReadOutputPins(uint8_t u8Port, uint16_t u16Pin) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + return ((READ_REG(PODR_REG(u8Port)) & (u16Pin)) != 0U) ? PIN_SET : PIN_RESET; +} + +/** + * @brief Read specified GPIO output data port + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @retval Specified GPIO port output value + */ +uint16_t GPIO_ReadOutputPort(uint8_t u8Port) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + + return READ_REG(PODR_REG(u8Port)); +} + +/** + * @brief Set specified GPIO output data port pins + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @retval None + */ +void GPIO_SetPins(uint8_t u8Port, uint16_t u16Pin) +{ + __IO GPIO_REG_TYPE *POSRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + POSRx = &POSR_REG(u8Port); + SET_REG_BIT(*POSRx, (GPIO_REG_TYPE)u16Pin); +} + +/** + * @brief Reset specified GPIO output data port pins + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @retval None + */ +void GPIO_ResetPins(uint8_t u8Port, uint16_t u16Pin) +{ + __IO GPIO_REG_TYPE *PORRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + PORRx = &PORR_REG(u8Port); + SET_REG_BIT(*PORRx, (GPIO_REG_TYPE)u16Pin); +} + +/** + * @brief Write specified GPIO data port + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16PortVal: Pin output value + * @retval None + */ +void GPIO_WritePort(uint8_t u8Port, uint16_t u16PortVal) +{ + __IO GPIO_REG_TYPE *PODRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + + PODRx = &PODR_REG(u8Port); + WRITE_REG(*PODRx, (GPIO_REG_TYPE)u16PortVal); +} + +/** + * @brief Toggle specified GPIO output data port pin + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @retval None + */ +void GPIO_TogglePins(uint8_t u8Port, uint16_t u16Pin) +{ + __IO GPIO_REG_TYPE *POTRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + POTRx = &POTR_REG(u8Port); + SET_REG_BIT(*POTRx, (GPIO_REG_TYPE)u16Pin); +} + +/** + * @brief GPIO Analog command. + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void GPIO_AnalogCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState) +{ + __IO uint16_t *PCRx; + uint8_t u8PinPos; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) { + if ((u16Pin & 1U) != 0U) { + PCRx = &PCR_REG(u8Port, u8PinPos); + if (ENABLE == enNewState) { + SET_REG16_BIT(*PCRx, GPIO_PCR_DDIS); + } else { + CLR_REG16_BIT(*PCRx, GPIO_PCR_DDIS); + } + } + u16Pin >>= 1U; + if (0U == u16Pin) { + break; + } + } +} + +/** + * @brief GPIO external interrupt command. + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void GPIO_ExtIntCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState) +{ + __IO uint16_t *PCRx; + uint8_t u8PinPos; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) { + if ((u16Pin & 1U) != 0U) { + PCRx = &PCR_REG(u8Port, u8PinPos); + if (ENABLE == enNewState) { + SET_REG16_BIT(*PCRx, GPIO_PCR_INTE); + } else { + CLR_REG16_BIT(*PCRx, GPIO_PCR_INTE); + } + } + u16Pin >>= 1U; + if (0U == u16Pin) { + break; + } + } +} +/** + * @} + */ + +#endif /* LL_GPIO_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_hash.c b/mcu/lib/src/hc32_ll_hash.c new file mode 100644 index 0000000..6a73d95 --- /dev/null +++ b/mcu/lib/src/hc32_ll_hash.c @@ -0,0 +1,336 @@ +/** + ******************************************************************************* + * @file hc32_ll_hash.c + * @brief This file provides firmware functions to manage the HASH. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-06-30 CDT Add HASH_DeInit function + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_hash.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_HASH HASH + * @brief HASH Driver Library + * @{ + */ + +#if (LL_HASH_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup HASH_Local_Macros HASH Local Macros + * @{ + */ + +/** + * @defgroup HASH_Miscellaneous_Macros HASH Miscellaneous Macros + * @{ + */ +#define HASH_GROUP_SIZE (64U) +#define HASH_GROUP_SIZE_WORD (HASH_GROUP_SIZE / 4U) +#define HASH_LAST_GROUP_SIZE_MAX (56U) +#define HASH_TIMEOUT (6000U) +#define HASH_MSG_DIGEST_SIZE_WORD (8U) + +/** + * @} + */ + +/** + * @defgroup HASH_Action HASH Action + * @{ + */ +#define HASH_ACTION_START (HASH_CR_START) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup HASH_Local_Functions HASH Local Functions + * @{ + */ + +/** + * @brief Writes the input buffer in data register. + * @param [in] pu8Data The buffer for source data + * @retval None + */ +static void HASH_WriteData(const uint8_t *pu8Data) +{ + uint8_t i; + __IO uint32_t *regDR = &CM_HASH->DR15; + const uint32_t *pu32Data = (const uint32_t *)((uint32_t)pu8Data); + + for (i = 0U; i < HASH_GROUP_SIZE_WORD; i++) { + regDR[i] = __REV(pu32Data[i]); + } +} + +/** + * @brief Memory copy. + * @param [in] pu8Dest Pointer to a destination address. + * @param [in] pu8Src Pointer to a source address. + * @param [in] u32Size Data size. + * @retval None + */ +static void HASH_MemCopy(uint8_t *pu8Dest, const uint8_t *pu8Src, uint32_t u32Size) +{ + uint32_t i = 0UL; + while (i < u32Size) { + pu8Dest[i] = pu8Src[i]; + i++; + } +} + +/** + * @brief Memory set. + * @param [in] pu8Mem Pointer to an address. + * @param [in] u8Value Data value. + * @param [in] u32Size Data size. + * @retval None + */ +static void HASH_MemSet(uint8_t *pu8Mem, uint8_t u8Value, uint32_t u32Size) +{ + uint32_t i = 0UL; + while (i < u32Size) { + pu8Mem[i] = u8Value; + i++; + } +} + +/** + * @brief Wait for the HASH to stop + * @param [in] u32Action HASH action. This parameter can be a value of @ref HASH_Action. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: Works timeout + */ +static int32_t HASH_Wait(uint32_t u32Action) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32TimeCount = 0UL; + + /* Wait for the HASH to stop */ + while (READ_REG32_BIT(CM_HASH->CR, u32Action) != 0UL) { + if (u32TimeCount++ > HASH_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} + +/** + * @brief HASH Filling data + * @param [in] pu8Data The source data buffer + * @param [in] u32DataSize Length of the input buffer in bytes + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: Works timeout + */ +static int32_t HASH_DoCalc(const uint8_t *pu8Data, uint32_t u32DataSize) +{ + uint8_t u8FillBuffer[HASH_GROUP_SIZE]; + uint32_t u32BitLenHigh; + uint32_t u32BitLenLow; + uint32_t u32Index = 0U; + uint8_t u8FirstGroup = 1U; + uint8_t u8HashEnd = 0U; + uint8_t u8DataEndMark = 0U; + int32_t i32Ret; + + u32BitLenHigh = (u32DataSize >> 29U) & 0x7U; + u32BitLenLow = (u32DataSize << 3U); + + /* Stop hash calculating. */ + i32Ret = HASH_Wait(HASH_ACTION_START); + + while ((i32Ret == LL_OK) && (u8HashEnd == 0U)) { + if (u32DataSize >= HASH_GROUP_SIZE) { + HASH_WriteData(&pu8Data[u32Index]); + u32DataSize -= HASH_GROUP_SIZE; + u32Index += HASH_GROUP_SIZE; + } else if (u32DataSize >= HASH_LAST_GROUP_SIZE_MAX) { + HASH_MemSet(u8FillBuffer, 0, HASH_GROUP_SIZE); + HASH_MemCopy(u8FillBuffer, &pu8Data[u32Index], u32DataSize); + u8FillBuffer[u32DataSize] = 0x80U; + u8DataEndMark = 1U; + HASH_WriteData(u8FillBuffer); + u32DataSize = 0U; + } else { + u8HashEnd = 1U; + } + + if (u8HashEnd != 0U) { + HASH_MemSet(u8FillBuffer, 0, HASH_GROUP_SIZE); + if (u32DataSize > 0U) { + HASH_MemCopy(u8FillBuffer, &pu8Data[u32Index], u32DataSize); + } + if (u8DataEndMark == 0U) { + u8FillBuffer[u32DataSize] = 0x80U; + } + u8FillBuffer[63U] = (uint8_t)(u32BitLenLow); + u8FillBuffer[62U] = (uint8_t)(u32BitLenLow >> 8U); + u8FillBuffer[61U] = (uint8_t)(u32BitLenLow >> 16U); + u8FillBuffer[60U] = (uint8_t)(u32BitLenLow >> 24U); + u8FillBuffer[59U] = (uint8_t)(u32BitLenHigh); + u8FillBuffer[58U] = (uint8_t)(u32BitLenHigh >> 8U); + u8FillBuffer[57U] = (uint8_t)(u32BitLenHigh >> 16U); + u8FillBuffer[56U] = (uint8_t)(u32BitLenHigh >> 24U); + HASH_WriteData(u8FillBuffer); + } + + /* First group and last group check */ + /* check if first group */ + if (u8FirstGroup != 0U) { + u8FirstGroup = 0U; + /* Set first group. */ + WRITE_REG32(bCM_HASH->CR_b.FST_GRP, 1U); + } else { + /* Set continuous group. */ + WRITE_REG32(bCM_HASH->CR_b.FST_GRP, 0U); + } + + /* Start hash calculating. */ + WRITE_REG32(bCM_HASH->CR_b.START, 1U); + i32Ret = HASH_Wait(HASH_ACTION_START); + } + /* Stop hash calculating. */ + WRITE_REG32(bCM_HASH->CR_b.START, 0U); + + return i32Ret; +} + +/** + * @brief Read message digest. + * @param [out] pu8MsgDigest Buffer for message digest. + * @retval None + */ +static void HASH_ReadMsgDigest(uint8_t *pu8MsgDigest) +{ + uint8_t i; + __IO uint32_t *regHR = &CM_HASH->HR7; + uint32_t *pu32MsgDigest = (uint32_t *)((uint32_t)pu8MsgDigest); + + for (i = 0U; i < HASH_MSG_DIGEST_SIZE_WORD; i++) { + pu32MsgDigest[i] = __REV(regHR[i]); + } +} + +/** + * @} + */ + +/** + * @defgroup HASH_Global_Functions HASH Global Functions + * @{ + */ + +/** + * @brief De-initializes HASH. + * @param None + * @retval int32_t: + * - LL_OK: No error occurred. + */ +int32_t HASH_DeInit(void) +{ + uint8_t i; + __IO uint32_t *regDR = &CM_HASH->DR15; + + WRITE_REG32(CM_HASH->CR, 0UL); + for (i = 0U; i < HASH_GROUP_SIZE_WORD; i++) { + WRITE_REG32(regDR[i], 0UL); + } + return LL_OK; +} + +/** + * @brief HASH calculate. + * @param [in] pu8SrcData Pointer to the source data buffer. + * @param [in] u32SrcDataSize Length of the source data buffer in bytes. + * @param [out] pu8MsgDigest Buffer of the digest. The size must be 32 bytes. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: Parameter error. + * - LL_ERR_TIMEOUT: Works timeout. + */ +int32_t HASH_Calculate(const uint8_t *pu8SrcData, uint32_t u32SrcDataSize, uint8_t *pu8MsgDigest) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pu8SrcData != NULL) && (u32SrcDataSize != 0UL) && (pu8MsgDigest != NULL)) { + /* Set HASH mode */ + i32Ret = HASH_DoCalc(pu8SrcData, u32SrcDataSize); + if (i32Ret == LL_OK) { + /* Get the message digest result */ + HASH_ReadMsgDigest(pu8MsgDigest); + } + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_HASH_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_i2c.c b/mcu/lib/src/hc32_ll_i2c.c new file mode 100644 index 0000000..283df07 --- /dev/null +++ b/mcu/lib/src/hc32_ll_i2c.c @@ -0,0 +1,1224 @@ +/** + ******************************************************************************* + * @file hc32_ll_i2c.c + * @brief This file provides firmware functions to manage the Inter-Integrated + * Circuit(I2C). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Add API I2C_SlaveAddrCmd(), modify API I2C_SlaveAddrConfig() + 2023-06-30 CDT Disable slave address function in I2C_Init() + Move macro define I2C_SRC_CLK to head file + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_i2c.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_I2C I2C + * @brief I2C Driver Library + * @{ + */ + +#if (LL_I2C_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup I2C_Local_Macros I2C Local Macros + * @{ + */ +#define I2C_BAUDRATE_MAX (400000UL) + +#define I2C_SCL_HIGHT_LOW_LVL_SUM_MAX ((float32_t)0x3E) +#define I2C_7BIT_MAX (0x7FUL) +#define I2C_10BIT_MAX (0x3FFUL) + +/** + * @defgroup I2C_Check_Parameters_Validity I2C Check Parameters Validity + * @{ + */ + +#define IS_I2C_UNIT(x) (((x) == CM_I2C1) || ((x) == CM_I2C2) || ((x) == CM_I2C3)) + +#define IS_I2C_DIG_FILTER_CLK(x) ((x) <= I2C_DIG_FILTER_CLK_DIV4) + +#define IS_I2C_7BIT_ADDR(x) ((x) <= I2C_7BIT_MAX) +#define IS_I2C_10BIT_ADDR(x) ((x) <= I2C_10BIT_MAX) + +#define IS_I2C_SPEED(x) \ +( ((x) != 0U) && \ + ((x) <= I2C_BAUDRATE_MAX)) + +#define IS_I2C_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | I2C_FLAG_ALL) == I2C_FLAG_ALL)) + +#define IS_I2C_CLR_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | I2C_FLAG_CLR_ALL) == I2C_FLAG_CLR_ALL)) + +#define IS_I2C_INT_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | I2C_INT_ALL) == I2C_INT_ALL)) + +#define IS_I2C_SMBUS_CONFIG(x) \ +( ((x) != 0U) && \ + (((x) | I2C_SMBUS_MATCH_ALL) == I2C_SMBUS_MATCH_ALL)) + +#define IS_I2C_ADDR(mode, addr) \ +( ((I2C_ADDR_7BIT == (mode)) && ((addr) <= 0x7FU)) || \ + ((I2C_ADDR_10BIT == (mode)) && ((addr) <= 0x3FFU)) || \ + (I2C_ADDR_DISABLE == (mode))) + +#define IS_I2C_ADDR_NUM(x) \ +( ((x) == I2C_ADDR0) || \ + ((x) == I2C_ADDR1)) + +#define IS_I2C_CLK_DIV(x) \ +( (x) <= I2C_CLK_DIV128) + +#define IS_I2C_TRANS_DIR(x) \ +( ((x) == I2C_DIR_TX) || \ + ((x) == I2C_DIR_RX)) + +#define IS_I2C_ACK_CONFIG(x) \ +( ((x) == I2C_ACK) || \ + ((x) == I2C_NACK)) + +#define IS_I2C_FLAG_STD(x) \ +( ((x) == RESET) || \ + ((x) == SET)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup I2C_Global_Functions I2C Global Functions + * @{ + */ + +/** + * @brief Try to wait a status of specified flags + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Flag Specify the flags to check, This parameter can be any combination of the member from + * @ref I2C_Flag values: + * @param [in] enStatus Expected status @ref en_flag_status_t + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + */ +int32_t I2C_WaitStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_ERR_TIMEOUT; + uint32_t u32RegStatusBit; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_FLAG(u32Flag)); + DDL_ASSERT(IS_I2C_FLAG_STD(enStatus)); + + for (;;) { + u32RegStatusBit = (READ_REG32_BIT(I2Cx->SR, u32Flag)); + if (((enStatus == SET) && (u32Flag == u32RegStatusBit)) || ((enStatus == RESET) && (0UL == u32RegStatusBit))) { + i32Ret = LL_OK; + } + + if ((LL_OK == i32Ret) || (0UL == u32Timeout)) { + break; + } else { + u32Timeout--; + } + } + return i32Ret; +} + +/** + * @brief I2C generate start condition + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval None + */ +void I2C_GenerateStart(CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_START); +} + +/** + * @brief I2C generate restart condition + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval None + */ +void I2C_GenerateRestart(CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_RESTART); +} + +/** + * @brief I2C generate stop condition + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval None + */ +void I2C_GenerateStop(CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_STOP); +} + +/** + * @brief Set the baudrate for I2C peripheral. + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] pstcI2cInit Pointer to I2C config structure @ref stc_i2c_init_t + * @arg pstcI2cInit->u32ClockDiv: Division of i2c source clock, reference as: + * step1: calculate div = (I2cSrcClk/Baudrate/(Imme+2*Dnfsum+SclTime) + * I2cSrcClk -- I2c source clock + * Baudrate -- baudrate of i2c + * SclTime -- =(SCL rising time + SCL falling time)/period of i2c clock + * according to i2c bus hardware parameter. + * Dnfsum -- 0 if digital filter off; + * Filter capacity if digital filter on(1 ~ 4) + * Imme -- An Immediate data, 68 + * step2: chose a division item which is similar and bigger than div from @ref I2C_Clock_Division. + * @arg pstcI2cInit->u32Baudrate : Baudrate configuration + * @arg pstcI2cInit->u32SclTime : Indicate SCL pin rising and falling + * time, should be number of T(i2c clock period time) + * @param [out] pf32Error Baudrate error + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_BaudrateConfig(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error) +{ + int32_t i32Ret = LL_OK; + uint32_t I2cSrcClk; + uint32_t I2cDivClk; + uint32_t SclCnt; + uint32_t Baudrate; + uint32_t Dnfsum = 0UL; + uint32_t Divsum = 2UL; + uint32_t TheoryBaudrate; + float32_t WidthTotal; + float32_t SumTotal; + float32_t WidthHL; + float32_t fErr = 0.0F; + + if ((NULL == pstcI2cInit) || (NULL == pf32Error)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_SPEED(pstcI2cInit->u32Baudrate)); + DDL_ASSERT(IS_I2C_CLK_DIV(pstcI2cInit->u32ClockDiv)); + + /* Get configuration for i2c */ + I2cSrcClk = I2C_SRC_CLK; + I2cDivClk = 1UL << pstcI2cInit->u32ClockDiv; + SclCnt = pstcI2cInit->u32SclTime; + Baudrate = pstcI2cInit->u32Baudrate; + + /* Judge digital filter status */ + if (0U != READ_REG32_BIT(I2Cx->FLTR, I2C_FLTR_DNFEN)) { + Dnfsum = (READ_REG32_BIT(I2Cx->FLTR, I2C_FLTR_DNF) >> I2C_FLTR_DNF_POS) + 1U; + } + + /* Judge if clock divider on*/ + if (I2C_CLK_DIV1 == pstcI2cInit->u32ClockDiv) { + Divsum = 3UL; + } + + if (I2cDivClk != 0UL) { + WidthTotal = (float32_t)I2cSrcClk / (float32_t)Baudrate / (float32_t)I2cDivClk; + SumTotal = (2.0F * (float32_t)Divsum) + (2.0F * (float32_t)Dnfsum) + (float32_t)SclCnt; + WidthHL = WidthTotal - SumTotal; + + /* Integer for WidthTotal, rounding off */ + if ((WidthTotal - (float32_t)((uint32_t)WidthTotal)) >= 0.5F) { + WidthTotal = (float32_t)((uint32_t)WidthTotal) + 1.0F; + } else { + WidthTotal = (float32_t)((uint32_t)WidthTotal); + } + + if (WidthTotal <= SumTotal) { + /* Err, Should set a smaller division value for pstcI2cInit->u32ClockDiv */ + i32Ret = LL_ERR_INVD_PARAM; + } else { + if (WidthHL > I2C_SCL_HIGHT_LOW_LVL_SUM_MAX) { + /* Err, Should set a bigger division value for pstcI2cInit->u32ClockDiv */ + i32Ret = LL_ERR_INVD_PARAM; + } else { + TheoryBaudrate = I2cSrcClk / (uint32_t)WidthTotal / I2cDivClk; + fErr = ((float32_t)Baudrate - (float32_t)TheoryBaudrate) / (float32_t)TheoryBaudrate; + WRITE_REG32(I2Cx->CCR, \ + (pstcI2cInit->u32ClockDiv << I2C_CCR_FREQ_POS) | \ + (((uint32_t)WidthHL / 2U) << I2C_CCR_SLOWW_POS) | \ + (((uint32_t)WidthHL - (((uint32_t)WidthHL) / 2U)) << I2C_CCR_SHIGHW_POS)); + } + } + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + } + + if ((NULL != pf32Error) && (LL_OK == i32Ret)) { + *pf32Error = fErr; + } + + return i32Ret; +} + +/** + * @brief De-initialize I2C unit + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval None + */ +void I2C_DeInit(CM_I2C_TypeDef *I2Cx) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + /* RESET peripheral register and internal status*/ + CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_PE); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_SWRST); +} + +/** + * @brief Initialize I2C peripheral according to the structure + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] pstcI2cInit Pointer to I2C config structure @ref stc_i2c_init_t + * @arg pstcI2cInit->u32ClockDiv: Division of i2c source clock, reference as: + * step1: calculate div = (I2cSrcClk/Baudrate/(Imme+2*Dnfsum+SclTime) + * I2cSrcClk -- I2c source clock + * Baudrate -- baudrate of i2c + * SclTime -- =(SCL rising time + SCL falling time)/period of i2c clock + * according to i2c bus hardware parameter. + * Dnfsum -- 0 if digital filter off; + * Filter capacity if digital filter on(1 ~ 4) + * Imme -- An Immediate data, 68 + * step2: chose a division item which is similar and bigger than div + * from @ref I2C_Clock_Division. + * @arg pstcI2cInit->u32Baudrate : Baudrate configuration + * @arg pstcI2cInit->u32SclTime : Indicate SCL pin rising and falling + * time, should be number of T(i2c clock period time) + * @param [out] pf32Error Baudrate error + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_Init(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error) +{ + int32_t i32Ret; + + if (NULL == pstcI2cInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_SPEED(pstcI2cInit->u32Baudrate)); + DDL_ASSERT(IS_I2C_CLK_DIV(pstcI2cInit->u32ClockDiv)); + + /* Register and internal status reset */ + CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_PE); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_SWRST); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_PE); + + /* I2C baudrate config */ + i32Ret = I2C_BaudrateConfig(I2Cx, pstcI2cInit, pf32Error); + + /* Disable global broadcast address function */ + CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_ENGC); + /* Release software reset */ + CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_SWRST); + /* Disable I2C peripheral */ + CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_PE); + /* Disable slave address function */ + CLR_REG32_BIT(I2Cx->SLR0, I2C_SLR0_SLADDR0EN); + } + return i32Ret; +} + +/** + * @brief I2C slave address config + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32AddrNum I2C address 0 or address 1 @ref I2C_Address_Num + * @param [in] u32AddrMode Address mode configuration @ref I2C_Addr_Config + * @param [in] u32Addr The slave address + * @retval None + */ +void I2C_SlaveAddrConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32Addr) +{ + __IO uint32_t *const pu32SLRx = (__IO uint32_t *)((uint32_t)&I2Cx->SLR0 + (u32AddrNum * 4UL)); + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_ADDR_NUM(u32AddrNum)); + DDL_ASSERT(IS_I2C_ADDR(u32AddrMode, u32Addr)); + + if (I2C_ADDR_DISABLE == u32AddrMode) { + CLR_REG32_BIT(*pu32SLRx, I2C_SLR0_SLADDR0EN); + } else { + if (I2C_ADDR_10BIT == u32AddrMode) { + MODIFY_REG32(*pu32SLRx, I2C_SLR0_SLADDR0EN | I2C_SLR0_ADDRMOD0 | I2C_SLR0_SLADDR0, + u32AddrMode + u32Addr); + } else { + MODIFY_REG32(*pu32SLRx, I2C_SLR0_SLADDR0EN | I2C_SLR0_ADDRMOD0 | I2C_SLR0_SLADDR0, + u32AddrMode + (u32Addr << 1U)); + } + } +} + +/** + * @brief I2C slave address config + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32AddrNum I2C address 0 or address 1 @ref I2C_Address_Num + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SlaveAddrCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, en_functional_state_t enNewState) +{ + __IO uint32_t *const pu32SLRx = (__IO uint32_t *)((uint32_t)&I2Cx->SLR0 + (u32AddrNum * 4UL)); + /* Check parameters */ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_ADDR_NUM(u32AddrNum)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(*pu32SLRx, I2C_SLR0_SLADDR0EN, (uint32_t)enNewState << I2C_SLR0_SLADDR0EN_POS); +} + +/** + * @brief I2C function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_Cmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_PE, (uint32_t)enNewState << I2C_CR1_PE_POS); +} + +/** + * @brief I2C fast ACK config + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_FastAckCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + if (ENABLE == enNewState) { + CLR_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN); + } else { + SET_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN); + } +} + +/** + * @brief I2C bus wait function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_BusWaitCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR4, I2C_CR4_BUSWAIT); + } else { + CLR_REG32_BIT(I2Cx->CR4, I2C_CR4_BUSWAIT); + } +} + +/** + * @brief I2C SMBUS function configuration + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32SmbusConfig Indicate the SMBUS address match function configuration. @ref I2C_Smbus_Match_Config + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SmbusConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32SmbusConfig, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_SMBUS_CONFIG(u32SmbusConfig)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR1, u32SmbusConfig); + } else { + CLR_REG32_BIT(I2Cx->CR1, u32SmbusConfig); + } +} + +/** + * @brief I2C SMBUS function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SmbusCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_SMBUS, (uint32_t)enNewState << I2C_CR1_SMBUS_POS); +} + +/** + * @brief I2C digital filter function configuration + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32FilterClock Chose the digital filter clock, @ref I2C_Digital_Filter_Clock + * @retval None + */ +void I2C_DigitalFilterConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32FilterClock) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_DIG_FILTER_CLK(u32FilterClock)); + + MODIFY_REG32(I2Cx->FLTR, I2C_FLTR_DNF, u32FilterClock); +} + +/** + * @brief I2C digital filter command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_DigitalFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->FLTR, I2C_FLTR_DNFEN, (uint32_t)enNewState << I2C_FLTR_DNFEN_POS); +} + +/** + * @brief I2C analog filter function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_AnalogFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->FLTR, I2C_FLTR_ANFEN, (uint32_t)enNewState << I2C_FLTR_ANFEN_POS); +} + +/** + * @brief I2C general call command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_GeneralCallCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + MODIFY_REG32(I2Cx->CR1, I2C_CR1_ENGC, (uint32_t)enNewState << I2C_CR1_ENGC_POS); +} + +/** + * @brief I2C flags status get + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Flag Specify the flags to check, This parameter can be any combination of the member from + * @ref I2C_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t I2C_GetStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_FLAG(u32Flag)); + + return ((0UL != READ_REG32_BIT(I2Cx->SR, u32Flag)) ? SET : RESET); +} + +/** + * @brief Clear I2C flags + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Flag Specifies the flag to clear, This parameter + * can be any combination of the following values + * @arg I2C_FLAG_START : Start flag clear + * @arg I2C_FLAG_MATCH_ADDR0 : Address 0 detected flag clear + * @arg I2C_FLAG_MATCH_ADDR1 : Address 1 detected flag clear + * @arg I2C_FLAG_TX_CPLT : Transfer end flag clear + * @arg I2C_FLAG_STOP : Stop flag clear + * @arg I2C_FLAG_RX_FULL : Receive buffer full flag clear + * @arg I2C_FLAG_TX_EMPTY : Transfer buffer empty flag clear + * @arg I2C_FLAG_ARBITRATE_FAIL : Arbitration fails flag clear + * @arg I2C_FLAG_NACKF : Nack detected flag clear + * @arg I2C_FLAG_GENERAL_CALL : General call address detected flag clear + * @arg I2C_FLAG_SMBUS_DEFAULT_MATCH: Smbus default address detected flag clear + * @arg I2C_FLAG_SMBUS_HOST_MATCH : Smbus host address detected flag clear + * @arg I2C_FLAG_SMBUS_ALARM_MATCH : Smbus alarm address detected flag clear + * @retval None + */ +void I2C_ClearStatus(CM_I2C_TypeDef *I2Cx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_CLR_FLAG(u32Flag)); + + WRITE_REG32(I2Cx->CLR, u32Flag); +} + +/** + * @brief I2C software reset function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SWResetCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_SWRST, (uint32_t)enNewState << I2C_CR1_SWRST_POS); +} + +/** + * @brief I2C interrupt command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32IntType Specifies the I2C interrupts @ref I2C_Int_Flag + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_IntCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_INT_FLAG(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR2, u32IntType); + } else { + CLR_REG32_BIT(I2Cx->CR2, u32IntType); + } +} + +/** + * @brief I2C send data + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u8Data The data to be send + * @retval None + */ +void I2C_WriteData(CM_I2C_TypeDef *I2Cx, uint8_t u8Data) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + WRITE_REG8(I2Cx->DTR, u8Data); +} + +/** + * @brief I2C read data from register + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval uint8_t The value of the received data + */ +uint8_t I2C_ReadData(const CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + return READ_REG8(I2Cx->DRR); +} + +/** + * @brief I2C ACK status configuration + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32AckConfig I2C ACK configure. @ref I2C_Ack_Config + * @retval None + */ +void I2C_AckConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AckConfig) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_ACK_CONFIG(u32AckConfig)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_ACK, u32AckConfig); +} + +/** + * @brief I2C SCL high level timeout configuration + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u16TimeoutH Clock timeout period for high level + * @retval None + */ +void I2C_SCLHighTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutH) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + MODIFY_REG32(I2Cx->SLTR, I2C_SLTR_TOUTHIGH, (uint32_t)u16TimeoutH << I2C_SLTR_TOUTHIGH_POS); +} + +/** + * @brief I2C SCL low level timeout configuration + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u16TimeoutL Clock timeout period for low level + * @retval None + */ +void I2C_SCLLowTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutL) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + MODIFY_REG32(I2Cx->SLTR, I2C_SLTR_TOUTLOW, u16TimeoutL); +} + +/** + * @brief Enable or disable I2C SCL high level timeout function + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SCLHighTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR3, I2C_CR3_HTMOUT); + } else { + CLR_REG32_BIT(I2Cx->CR3, I2C_CR3_HTMOUT); + } +} + +/** + * @brief Enable or disable I2C SCL low level timeout function + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SCLLowTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR3, I2C_CR3_LTMOUT); + } else { + CLR_REG32_BIT(I2Cx->CR3, I2C_CR3_LTMOUT); + } +} + +/** + * @brief Enable or disable I2C SCL timeout function + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SCLTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR3, I2C_CR3_TMOUTEN); + } else { + CLR_REG32_BIT(I2Cx->CR3, I2C_CR3_TMOUTEN); + } +} + +/** + * @brief I2Cx start + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + */ +int32_t I2C_Start(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_BUSY, RESET, u32Timeout); + + if (LL_OK == i32Ret) { + /* generate start signal */ + I2C_GenerateStart(I2Cx); + /* Judge if start success*/ + i32Ret = I2C_WaitStatus(I2Cx, (I2C_FLAG_BUSY | I2C_FLAG_START), SET, u32Timeout); + } + + return i32Ret; +} + +/** + * @brief I2Cx restart + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + */ +int32_t I2C_Restart(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + /* Clear start status flag */ + I2C_ClearStatus(I2Cx, I2C_FLAG_START); + /* Send restart condition */ + I2C_GenerateRestart(I2Cx); + /* Judge if start success*/ + i32Ret = I2C_WaitStatus(I2Cx, (I2C_FLAG_BUSY | I2C_FLAG_START), SET, u32Timeout); + + return i32Ret; +} + +/** + * @brief I2Cx send address + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u16Addr The address to be sent + * @param [in] u8Dir Transfer direction, @ref I2C_Trans_Dir + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR: NACK received + */ +int32_t I2C_TransAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_TRANS_DIR(u8Dir)); + DDL_ASSERT(IS_I2C_7BIT_ADDR(u16Addr)); + + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_EMPTY, SET, u32Timeout); + + if (LL_OK == i32Ret) { + /* Send I2C address */ + I2C_WriteData(I2Cx, (uint8_t)(u16Addr << 1U) | u8Dir); + + if (I2C_DIR_TX == u8Dir) { + /* If in master transfer process, Need wait transfer end */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_CPLT, SET, u32Timeout); + } else { + /* If in master receive process, wait I2C_FLAG_TRA changed to receive */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TRA, RESET, u32Timeout); + } + + if (i32Ret == LL_OK) { + if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == SET) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/** + * @brief I2Cx send 10 bit address + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u16Addr The address to be sent + * @param [in] u8Dir Transfer direction @ref I2C_Trans_Dir + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR: NACK received + */ +int32_t I2C_Trans10BitAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_TRANS_DIR(u8Dir)); + DDL_ASSERT(IS_I2C_10BIT_ADDR(u16Addr)); + + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_EMPTY, SET, u32Timeout); + + if (LL_OK == i32Ret) { + /* Write 11110 + SLA(bit9:8) + W#(1bit) */ + I2C_WriteData(I2Cx, (uint8_t)((u16Addr >> 7U) & 0x06U) | 0xF0U | I2C_DIR_TX); + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_CPLT, SET, u32Timeout); + + if (LL_OK == i32Ret) { + /* If receive ACK */ + if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == RESET) { + /* Write SLA(bit7:0)*/ + I2C_WriteData(I2Cx, (uint8_t)(u16Addr & 0xFFU)); + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_CPLT, SET, u32Timeout); + + if (LL_OK == i32Ret) { + if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == SET) { + i32Ret = LL_ERR; + } + } + } else { + i32Ret = LL_ERR; + } + } + } + + if ((u8Dir == I2C_DIR_RX) && (LL_OK == i32Ret)) { + /* Restart */ + I2C_ClearStatus(I2Cx, I2C_FLAG_START); + I2C_GenerateRestart(I2Cx); + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_START, SET, u32Timeout); + + if (LL_OK == i32Ret) { + /* Write 11110 + SLA(bit9:8) + R(1bit) */ + I2C_WriteData(I2Cx, (uint8_t)((u16Addr >> 7U) & 0x06U) | 0xF0U | I2C_DIR_RX); + /* If in master receive process, Need wait TRA flag */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TRA, RESET, u32Timeout); + + if (LL_OK == i32Ret) { + /* If receive NACK */ + if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == SET) { + i32Ret = LL_ERR; + } + } + } + } + + return i32Ret; +} + +/** + * @brief I2Cx send data + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] au8TxData The data array to be sent + * @param [in] u32Size Number of data in array pau8TxData + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_TransData(CM_I2C_TypeDef *I2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32Count = 0UL; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + if (au8TxData != NULL) { + while ((u32Count != u32Size) && (i32Ret == LL_OK)) { + /* Wait tx buffer empty */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_EMPTY, SET, u32Timeout); + + if (i32Ret == LL_OK) { + /* Send one byte data */ + I2C_WriteData(I2Cx, au8TxData[u32Count]); + + /* Wait transfer end */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_CPLT, SET, u32Timeout); + + /* If receive NACK */ + if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == SET) { + break; + } + u32Count++; + } + } + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + + return i32Ret; +} + +/** + * @brief I2Cx receive data + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [out] au8RxData Array to hold the received data + * @param [in] u32Size Number of data to be received + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_ReceiveData(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + uint32_t i; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + if (au8RxData != NULL) { + uint32_t u32FastAckDis = READ_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN); + for (i = 0UL; i < u32Size; i++) { + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_RX_FULL, SET, u32Timeout); + + if (0UL == u32FastAckDis) { + if ((u32Size >= 2UL) && (i == (u32Size - 2UL))) { + I2C_AckConfig(I2Cx, I2C_NACK); + } + } else { + if (i != (u32Size - 1UL)) { + I2C_AckConfig(I2Cx, I2C_ACK); + } else { + I2C_AckConfig(I2Cx, I2C_NACK); + } + } + + if (i32Ret == LL_OK) { + /* read data from register */ + au8RxData[i] = I2C_ReadData(I2Cx); + } else { + break; + } + } + I2C_AckConfig(I2Cx, I2C_ACK); + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + + return i32Ret; +} + +/** + * @brief I2Cx receive data and stop(for master) + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [out] au8RxData Array to hold the received data + * @param [in] u32Size Number of data to be received + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_MasterReceiveDataAndStop(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + uint32_t i; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + if (au8RxData != NULL) { + uint32_t u32FastAckDis = READ_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN); + + for (i = 0UL; i < u32Size; i++) { + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_RX_FULL, SET, u32Timeout); + + if (0UL == u32FastAckDis) { + if ((u32Size >= 2UL) && (i == (u32Size - 2UL))) { + I2C_AckConfig(I2Cx, I2C_NACK); + } + } else { + if (i != (u32Size - 1UL)) { + I2C_AckConfig(I2Cx, I2C_ACK); + } else { + I2C_AckConfig(I2Cx, I2C_NACK); + } + } + + if (i32Ret == LL_OK) { + /* Stop before read last data */ + if (i == (u32Size - 1UL)) { + I2C_ClearStatus(I2Cx, I2C_FLAG_STOP); + I2C_GenerateStop(I2Cx); + } + /* read data from register */ + au8RxData[i] = I2C_ReadData(I2Cx); + + if (i == (u32Size - 1UL)) { + /* Wait stop flag after DRR read */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_STOP, SET, u32Timeout); + } + } else { + break; + } + } + I2C_AckConfig(I2Cx, I2C_ACK); + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + + return i32Ret; +} + +/** + * @brief I2Cx stop + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + */ +int32_t I2C_Stop(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + /* Clear stop flag */ + while ((SET == I2C_GetStatus(I2Cx, I2C_FLAG_STOP)) && (u32Timeout > 0UL)) { + I2C_ClearStatus(I2Cx, I2C_FLAG_STOP); + u32Timeout--; + } + I2C_GenerateStop(I2Cx); + /* Wait stop flag */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_STOP, SET, u32Timeout); + + return i32Ret; +} + +/** + * @brief Initialize structure stc_i2c_init_t variable with default value. + * @param [out] pstcI2cInit Pointer to a stc_i2c_init_t structure variable which will be initialized. + * @ref stc_i2c_init_t. + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_StructInit(stc_i2c_init_t *pstcI2cInit) +{ + int32_t i32Ret = LL_OK; + if (pstcI2cInit == NULL) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcI2cInit->u32Baudrate = 50000UL; + pstcI2cInit->u32SclTime = 0UL; + pstcI2cInit->u32ClockDiv = I2C_CLK_DIV1; + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_I2C_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_i2s.c b/mcu/lib/src/hc32_ll_i2s.c new file mode 100644 index 0000000..c6058cf --- /dev/null +++ b/mcu/lib/src/hc32_ll_i2s.c @@ -0,0 +1,1035 @@ +/** + ******************************************************************************* + * @file hc32_ll_i2s.c + * @brief This file provides firmware functions to manage the Inter IC Sound Bus + * (I2S). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-09-30 CDT Modify I2S_ClearStatus function + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_i2s.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_I2S I2S + * @brief Inter IC Sound Bus Driver Library + * @{ + */ + +#if (LL_I2S_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup I2S_Local_Macros I2S Local Macros + * @{ + */ +/* CMU registers define */ +#define I2S_CLK_SRC_PCLK (0x00U << CMU_I2SCKSEL_I2S1CKSEL_POS) +#define I2S_CLK_SRC_PLLP (0x08U << CMU_I2SCKSEL_I2S1CKSEL_POS) +#define I2S_CLK_SRC_PLLQ (0x09U << CMU_I2SCKSEL_I2S1CKSEL_POS) +#define I2S_CLK_SRC_PLLR (0x0AU << CMU_I2SCKSEL_I2S1CKSEL_POS) +#define I2S_CLK_SRC_PLLXP (0x0BU << CMU_I2SCKSEL_I2S1CKSEL_POS) +#define I2S_CLK_SRC_PLLXQ (0x0CU << CMU_I2SCKSEL_I2S1CKSEL_POS) +#define I2S_CLK_SRC_PLLXR (0x0DU << CMU_I2SCKSEL_I2S1CKSEL_POS) + +#define I2S_CMU_PLLCFGR PLLCFGR +#define I2S_CMU_PLLCFGR_PLLSRC CMU_PLLCFGR_PLLSRC + +#define I2S_CMU_PLLXCFGR UPLLCFGR + +#define I2S_CMU_SCFGR SCFGR +#define I2S_CMU_SCFGR_PCLK CMU_SCFGR_PCLK1S +#define I2S_CMU_SCFGR_PCLK_POS CMU_SCFGR_PCLK1S_POS + +#define I2S_CMU_PLLCFGR_PLLM CMU_PLLCFGR_MPLLM +#define I2S_CMU_PLLCFGR_PLLM_POS CMU_PLLCFGR_MPLLM_POS +#define I2S_CMU_PLLCFGR_PLLN CMU_PLLCFGR_MPLLN +#define I2S_CMU_PLLCFGR_PLLN_POS CMU_PLLCFGR_MPLLN_POS +#define I2S_CMU_PLLCFGR_PLLP CMU_PLLCFGR_MPLLP +#define I2S_CMU_PLLCFGR_PLLP_POS CMU_PLLCFGR_MPLLP_POS +#define I2S_CMU_PLLCFGR_PLLQ CMU_PLLCFGR_MPLLQ +#define I2S_CMU_PLLCFGR_PLLQ_POS CMU_PLLCFGR_MPLLQ_POS +#define I2S_CMU_PLLCFGR_PLLR CMU_PLLCFGR_MPLLR +#define I2S_CMU_PLLCFGR_PLLR_POS CMU_PLLCFGR_MPLLR_POS + +#define I2S_CMU_PLLCFGR_PLLXM CMU_UPLLCFGR_UPLLM +#define I2S_CMU_PLLCFGR_PLLXM_POS CMU_UPLLCFGR_UPLLM_POS +#define I2S_CMU_PLLCFGR_PLLXN CMU_UPLLCFGR_UPLLN +#define I2S_CMU_PLLCFGR_PLLXN_POS CMU_UPLLCFGR_UPLLN_POS +#define I2S_CMU_PLLCFGR_PLLXP CMU_UPLLCFGR_UPLLP +#define I2S_CMU_PLLCFGR_PLLXP_POS CMU_UPLLCFGR_UPLLP_POS +#define I2S_CMU_PLLCFGR_PLLXQ CMU_UPLLCFGR_UPLLQ +#define I2S_CMU_PLLCFGR_PLLXQ_POS CMU_UPLLCFGR_UPLLQ_POS +#define I2S_CMU_PLLCFGR_PLLXR CMU_UPLLCFGR_UPLLR +#define I2S_CMU_PLLCFGR_PLLXR_POS CMU_UPLLCFGR_UPLLR_POS + +/* I2S CTRL register Mask */ +#define I2S_CTRL_CLR_MASK (I2S_CTRL_WMS | I2S_CTRL_ODD | I2S_CTRL_MCKOE | \ + I2S_CTRL_TXBIRQWL | I2S_CTRL_RXBIRQWL | I2S_CTRL_I2SPLLSEL | \ + I2S_CTRL_SDOE | I2S_CTRL_LRCKOE | I2S_CTRL_CKOE | \ + I2S_CTRL_DUPLEX | I2S_CTRL_CLKSEL) + +/** + * @defgroup I2S_Check_Parameters_Validity I2S Check Parameters Validity + * @{ + */ +#define IS_I2S_UNIT(x) \ +( ((x) == CM_I2S1) || \ + ((x) == CM_I2S2) || \ + ((x) == CM_I2S3) || \ + ((x) == CM_I2S4)) + +#define IS_I2S_CLK_SRC(x) \ +( ((x) == I2S_CLK_SRC_PLL) || \ + ((x) == I2S_CLK_SRC_EXT)) + +#define IS_I2S_MD(x) \ +( ((x) == I2S_MD_MASTER) || \ + ((x) == I2S_MD_SLAVE)) + +#define IS_I2S_PROTOCOL(x) \ +( ((x) == I2S_PROTOCOL_PHILLIPS) || \ + ((x) == I2S_PROTOCOL_MSB) || \ + ((x) == I2S_PROTOCOL_LSB) || \ + ((x) == I2S_PROTOCOL_PCM_SHORT) || \ + ((x) == I2S_PROTOCOL_PCM_LONG)) + +#define IS_I2S_TRANS_MD(x) \ +( ((x) == I2S_TRANS_MD_HALF_DUPLEX_RX) || \ + ((x) == I2S_TRANS_MD_HALF_DUPLEX_TX) || \ + ((x) == I2S_TRANS_MD_FULL_DUPLEX)) + +#define IS_I2S_AUDIO_FREQ(x) \ +( ((x) == I2S_AUDIO_FREQ_DEFAULT) || \ + (((x) >= I2S_AUDIO_FREQ_8K) && ((x) <= I2S_AUDIO_FREQ_192K))) + +#define IS_I2S_CH_LEN(x) \ +( ((x) == I2S_CH_LEN_16BIT) || \ + ((x) == I2S_CH_LEN_32BIT)) + +#define IS_I2S_DATA_LEN(x) \ +( ((x) == I2S_DATA_LEN_16BIT) || \ + ((x) == I2S_DATA_LEN_24BIT) || \ + ((x) == I2S_DATA_LEN_32BIT)) + +#define IS_I2S_MCK_OUTPUT(x) \ +( ((x) == I2S_MCK_OUTPUT_DISABLE) || \ + ((x) == I2S_MCK_OUTPUT_ENABLE)) + +#define IS_I2S_TRANS_LVL(x) \ +( ((x) == I2S_TRANS_LVL0) || \ + ((x) == I2S_TRANS_LVL1) || \ + ((x) == I2S_TRANS_LVL2)) + +#define IS_I2S_RECEIVE_LVL(x) \ +( ((x) == I2S_RECEIVE_LVL0) || \ + ((x) == I2S_RECEIVE_LVL1) || \ + ((x) == I2S_RECEIVE_LVL2)) + +#define IS_I2S_FUNC(x) \ +( ((x) != 0U) && \ + (((x) | I2S_FUNC_ALL) == I2S_FUNC_ALL)) + +#define IS_I2S_RST_TYPE(x) \ +( ((x) != 0U) && \ + (((x) | I2S_RST_TYPE_ALL) == I2S_RST_TYPE_ALL)) + +#define IS_I2S_INT(x) \ +( ((x) != 0U) && \ + (((x) | I2S_INT_ALL) == I2S_INT_ALL)) + +#define IS_I2S_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | I2S_FLAG_ALL) == I2S_FLAG_ALL)) + +#define IS_I2S_CLR_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | I2S_FLAG_CLR_ALL) == I2S_FLAG_CLR_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup I2S_Global_Functions I2S Global Functions + * @{ + */ + +/** + * @brief Get I2S clock frequency. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @retval uint32_t The I2S clock frequency + */ +static uint32_t I2S_GetClockFreq(const CM_I2S_TypeDef *I2Sx) +{ + uint32_t u32ClockShift; + uint16_t u16ClockSrc; + uint32_t u32ClockFreq; + uint32_t u32PllP; + uint32_t u32PllQ; + uint32_t u32PllR; + uint32_t u32PllN; + uint32_t u32PllM; + uint32_t u32PllIn; + uint32_t u32Temp; + + /* Get the offset of the I2S clock source in CMU_I2SCKSEL */ + if (CM_I2S1 == I2Sx) { + u32ClockShift = CMU_I2SCKSEL_I2S1CKSEL_POS; + } else if (CM_I2S2 == I2Sx) { + u32ClockShift = CMU_I2SCKSEL_I2S2CKSEL_POS; + } else if (CM_I2S3 == I2Sx) { + u32ClockShift = CMU_I2SCKSEL_I2S3CKSEL_POS; + } else if (CM_I2S4 == I2Sx) { + u32ClockShift = CMU_I2SCKSEL_I2S4CKSEL_POS; + } else { + u32ClockShift = 0UL; + } + + u16ClockSrc = (READ_REG16(CM_CMU->I2SCKSEL) >> u32ClockShift) & CMU_I2SCKSEL_I2S1CKSEL; + if (0UL != READ_REG32_BIT(CM_CMU->I2S_CMU_PLLCFGR, I2S_CMU_PLLCFGR_PLLSRC)) { + u32PllIn = HRC_VALUE; + } else { + u32PllIn = XTAL_VALUE; + } + /* Calculate the clock frequency */ + switch (u16ClockSrc) { + case I2S_CLK_SRC_PCLK: + u32ClockFreq = SystemCoreClock >> ((READ_REG32_BIT(CM_CMU->I2S_CMU_SCFGR, + I2S_CMU_SCFGR_PCLK) >> I2S_CMU_SCFGR_PCLK_POS)); + break; + case I2S_CLK_SRC_PLLP: + u32Temp = READ_REG32(CM_CMU->I2S_CMU_PLLCFGR); + u32PllM = (u32Temp & I2S_CMU_PLLCFGR_PLLM) >> I2S_CMU_PLLCFGR_PLLM_POS; + u32PllN = (u32Temp & I2S_CMU_PLLCFGR_PLLN) >> I2S_CMU_PLLCFGR_PLLN_POS; + u32PllP = (u32Temp & I2S_CMU_PLLCFGR_PLLP) >> I2S_CMU_PLLCFGR_PLLP_POS; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllP + 1UL); + break; + case I2S_CLK_SRC_PLLQ: + u32Temp = READ_REG32(CM_CMU->I2S_CMU_PLLCFGR); + u32PllM = (u32Temp & I2S_CMU_PLLCFGR_PLLM) >> I2S_CMU_PLLCFGR_PLLM_POS; + u32PllN = (u32Temp & I2S_CMU_PLLCFGR_PLLN) >> I2S_CMU_PLLCFGR_PLLN_POS; + u32PllQ = (u32Temp & I2S_CMU_PLLCFGR_PLLQ) >> I2S_CMU_PLLCFGR_PLLQ_POS; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllQ + 1UL); + break; + case I2S_CLK_SRC_PLLR: + u32Temp = READ_REG32(CM_CMU->I2S_CMU_PLLCFGR); + u32PllM = (u32Temp & I2S_CMU_PLLCFGR_PLLM) >> I2S_CMU_PLLCFGR_PLLM_POS; + u32PllN = (u32Temp & I2S_CMU_PLLCFGR_PLLN) >> I2S_CMU_PLLCFGR_PLLN_POS; + u32PllR = (u32Temp & I2S_CMU_PLLCFGR_PLLR) >> I2S_CMU_PLLCFGR_PLLR_POS; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllR + 1UL); + break; + case I2S_CLK_SRC_PLLXP: + u32Temp = READ_REG32(CM_CMU->I2S_CMU_PLLXCFGR); + u32PllM = (u32Temp & I2S_CMU_PLLCFGR_PLLXM) >> I2S_CMU_PLLCFGR_PLLXM_POS; + u32PllN = (u32Temp & I2S_CMU_PLLCFGR_PLLXN) >> I2S_CMU_PLLCFGR_PLLXN_POS; + u32PllP = (u32Temp & I2S_CMU_PLLCFGR_PLLXP) >> I2S_CMU_PLLCFGR_PLLXP_POS; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllP + 1UL); + break; + case I2S_CLK_SRC_PLLXQ: + u32Temp = READ_REG32(CM_CMU->I2S_CMU_PLLXCFGR); + u32PllM = (u32Temp & I2S_CMU_PLLCFGR_PLLXM) >> I2S_CMU_PLLCFGR_PLLXM_POS; + u32PllN = (u32Temp & I2S_CMU_PLLCFGR_PLLXN) >> I2S_CMU_PLLCFGR_PLLXN_POS; + u32PllQ = (u32Temp & I2S_CMU_PLLCFGR_PLLXQ) >> I2S_CMU_PLLCFGR_PLLXQ_POS; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllQ + 1UL); + break; + case I2S_CLK_SRC_PLLXR: + u32Temp = READ_REG32(CM_CMU->I2S_CMU_PLLXCFGR); + u32PllM = (u32Temp & I2S_CMU_PLLCFGR_PLLXM) >> I2S_CMU_PLLCFGR_PLLXM_POS; + u32PllN = (u32Temp & I2S_CMU_PLLCFGR_PLLXN) >> I2S_CMU_PLLCFGR_PLLXN_POS; + u32PllR = (u32Temp & I2S_CMU_PLLCFGR_PLLXR) >> I2S_CMU_PLLCFGR_PLLXR_POS; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllR + 1UL); + break; + default: + u32ClockFreq = 0UL; + break; + } + + return u32ClockFreq; +} + +/** + * @brief Wait for the flag status of I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Flag I2S flag type + * This parameter can be one of the following values: + * @arg I2S_FLAG_TX_ALARM: Transfer buffer alarm flag + * @arg I2S_FLAG_RX_ALARM: Receive buffer alarm flag + * @arg I2S_FLAG_TX_EMPTY: Transfer buffer empty flag + * @arg I2S_FLAG_TX_FULL: Transfer buffer full flag + * @arg I2S_FLAG_RX_EMPTY: Receive buffer empty flag + * @arg I2S_FLAG_RX_FULL: Receive buffer full flag + * @arg I2S_FLAG_TX_ERR: Transfer overflow or underflow flag + * @arg I2S_FLAG_RX_ERR: Receive overflow flag + * @param [in] enStatus The flag status + * This parameter can be one of the following values: + * @arg SET: Wait for the flag to set + * @arg RESET: Wait for the flag to reset + * @param [in] u32Timeout Wait the flag timeout(ms) + * @retval int32_t: + * - LL_OK: Wait status success + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t I2S_WaitStatus(const CM_I2S_TypeDef *I2Sx, uint32_t u32Flag, + en_flag_status_t enStatus, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32Count; + + /* Waiting for the flag status to change to the enStatus */ + u32Count = u32Timeout * (HCLK_VALUE / 20000UL); + while (enStatus != I2S_GetStatus(I2Sx, u32Flag)) { + if (u32Count == 0UL) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + return i32Ret; +} + +/** + * @brief De-Initialize I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @retval None + */ +void I2S_DeInit(CM_I2S_TypeDef *I2Sx) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + /* Reset all registers of I2S */ + WRITE_REG32(I2Sx->CTRL, 0x00004400UL); + WRITE_REG32(I2Sx->ER, 0x00000003UL); + WRITE_REG32(I2Sx->CFGR, 0x00000000UL); + WRITE_REG32(I2Sx->PR, 0x00000002UL); + SET_REG32_BIT(I2Sx->CTRL, I2S_RST_TYPE_ALL); + CLR_REG32_BIT(I2Sx->CTRL, I2S_RST_TYPE_ALL); +} + +/** + * @brief Initialize I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] pstcI2sInit Pointer to a @ref stc_i2s_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + * - LL_ERR: Set frequency failed + */ +int32_t I2S_Init(CM_I2S_TypeDef *I2Sx, const stc_i2s_init_t *pstcI2sInit) +{ + int32_t i32Ret = LL_OK; + uint32_t u32I2sClk; + uint32_t u32Temp; + uint32_t u32I2sDiv = 2UL; + uint32_t u32I2sOdd = 0UL; + uint32_t u32ChWidth; + + if (NULL == pstcI2sInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_CLK_SRC(pstcI2sInit->u32ClockSrc)); + DDL_ASSERT(IS_I2S_MD(pstcI2sInit->u32Mode)); + DDL_ASSERT(IS_I2S_PROTOCOL(pstcI2sInit->u32Protocol)); + DDL_ASSERT(IS_I2S_TRANS_MD(pstcI2sInit->u32TransMode)); + DDL_ASSERT(IS_I2S_AUDIO_FREQ(pstcI2sInit->u32AudioFreq)); + DDL_ASSERT(IS_I2S_CH_LEN(pstcI2sInit->u32ChWidth)); + DDL_ASSERT(IS_I2S_DATA_LEN(pstcI2sInit->u32DataWidth)); + DDL_ASSERT(IS_I2S_MCK_OUTPUT(pstcI2sInit->u32MCKOutput)); + DDL_ASSERT(IS_I2S_TRANS_LVL(pstcI2sInit->u32TransFIFOLevel)); + DDL_ASSERT(IS_I2S_RECEIVE_LVL(pstcI2sInit->u32ReceiveFIFOLevel)); + + if (I2S_AUDIO_FREQ_DEFAULT != pstcI2sInit->u32AudioFreq) { + /* Get I2S source Clock frequency */ + if (I2S_CLK_SRC_EXT == pstcI2sInit->u32ClockSrc) { + /* If the external clock frequency is different from the default value, + you need to redefine the macro value (I2S_EXT_CLK_FREQ). */ + u32I2sClk = I2S_EXT_CLK_FREQ; + } else { + u32I2sClk = I2S_GetClockFreq(I2Sx); + } + /* The actual frequency division value is calculated according to the output state of MCK */ + if (I2S_CH_LEN_16BIT != pstcI2sInit->u32ChWidth) { + u32ChWidth = 32UL; + } else { + u32ChWidth = 16UL; + } + + if (I2S_MCK_OUTPUT_ENABLE == pstcI2sInit->u32MCKOutput) { + if (I2S_CH_LEN_16BIT != pstcI2sInit->u32ChWidth) { + u32Temp = (((u32I2sClk / (u32ChWidth * 2U * 4U)) * 10U) / pstcI2sInit->u32AudioFreq) + 5U; + } else { + u32Temp = (((u32I2sClk / (u32ChWidth * 2U * 8U)) * 10U) / pstcI2sInit->u32AudioFreq) + 5U; + } + } else { + u32Temp = (((u32I2sClk / (u32ChWidth * 2U)) * 10U) / pstcI2sInit->u32AudioFreq) + 5U; + } + u32Temp = u32Temp / 10U; + u32I2sOdd = u32Temp & 0x01U; + u32I2sDiv = (u32Temp - u32I2sOdd) / 2U; + } + + if ((u32I2sDiv < 2U) || (u32I2sDiv > 0xFFU)) { + /* Set the default values */ + u32I2sOdd = 0U; + u32I2sDiv = 2U; + i32Ret = LL_ERR; + } + u32Temp = pstcI2sInit->u32ClockSrc | pstcI2sInit->u32Mode | + pstcI2sInit->u32Protocol | pstcI2sInit->u32TransMode | + pstcI2sInit->u32ChWidth | pstcI2sInit->u32DataWidth | + pstcI2sInit->u32MCKOutput | pstcI2sInit->u32TransFIFOLevel | + pstcI2sInit->u32ReceiveFIFOLevel | (u32I2sOdd << I2S_CTRL_ODD_POS); + if (I2S_MD_MASTER == pstcI2sInit->u32Mode) { + u32Temp |= (I2S_CTRL_CKOE | I2S_CTRL_LRCKOE); + } + /* Set I2S_CFGR register */ + WRITE_REG32(I2Sx->CFGR, (pstcI2sInit->u32Protocol | pstcI2sInit->u32ChWidth | pstcI2sInit->u32DataWidth)); + /* set I2S_PR register */ + WRITE_REG32(I2Sx->PR, u32I2sDiv); + /* Set I2S_CTRL register */ + MODIFY_REG32(I2Sx->CTRL, I2S_CTRL_CLR_MASK, u32Temp); + } + + return i32Ret; +} + +/** + * @brief Fills each stc_i2s_init_t member with default value. + * @param [out] pstcI2sInit Pointer to a @ref stc_i2s_init_t structure + * @retval int32_t: + * - LL_OK: stc_i2s_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t I2S_StructInit(stc_i2s_init_t *pstcI2sInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcI2sInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcI2sInit->u32ClockSrc = I2S_CLK_SRC_PLL; + pstcI2sInit->u32Mode = I2S_MD_MASTER; + pstcI2sInit->u32Protocol = I2S_PROTOCOL_PHILLIPS; + pstcI2sInit->u32TransMode = I2S_TRANS_MD_HALF_DUPLEX_RX; + pstcI2sInit->u32AudioFreq = I2S_AUDIO_FREQ_DEFAULT; + pstcI2sInit->u32ChWidth = I2S_CH_LEN_16BIT; + pstcI2sInit->u32DataWidth = I2S_DATA_LEN_16BIT; + pstcI2sInit->u32MCKOutput = I2S_MCK_OUTPUT_DISABLE; + pstcI2sInit->u32TransFIFOLevel = I2S_TRANS_LVL2; + pstcI2sInit->u32ReceiveFIFOLevel = I2S_RECEIVE_LVL2; + } + + return i32Ret; +} + +/** + * @brief Software reset of I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Type Software reset type + * This parameter can be one or any combination of the following values: + * @arg @ref I2S_Reset_Type + * @retval None + */ +void I2S_SWReset(CM_I2S_TypeDef *I2Sx, uint32_t u32Type) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_RST_TYPE(u32Type)); + + SET_REG32_BIT(I2Sx->CTRL, u32Type); + CLR_REG32_BIT(I2Sx->CTRL, u32Type); +} + +/** + * @brief Set the transfer mode for the I2S communication. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Mode Transfer mode + * This parameter can be one of the following values: + * @arg I2S_TRANS_MD_HALF_DUPLEX_RX: Receive only and half duplex mode + * @arg I2S_TRANS_MD_HALF_DUPLEX_TX: Send only and half duplex mode + * @arg I2S_TRANS_MD_FULL_DUPLEX: Full duplex mode + * @retval None + */ +void I2S_SetTransMode(CM_I2S_TypeDef *I2Sx, uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_TRANS_MD(u32Mode)); + + MODIFY_REG32(I2Sx->CTRL, (I2S_CTRL_DUPLEX | I2S_CTRL_SDOE), u32Mode); +} + +/** + * @brief Set the transfer FIFO level of I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Level Transfer FIFO level + * This parameter can be one of the following values: + * @arg @ref I2S_Trans_Level + * @retval None + */ +void I2S_SetTransFIFOLevel(CM_I2S_TypeDef *I2Sx, uint32_t u32Level) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_TRANS_LVL(u32Level)); + + MODIFY_REG32(I2Sx->CTRL, I2S_CTRL_TXBIRQWL, u32Level); +} + +/** + * @brief Set the receive FIFO level of I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Level Receive FIFO level + * This parameter can be one of the following values: + * @arg @ref I2S_Receive_Level + * @retval None + */ +void I2S_SetReceiveFIFOLevel(CM_I2S_TypeDef *I2Sx, uint32_t u32Level) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_RECEIVE_LVL(u32Level)); + + MODIFY_REG32(I2Sx->CTRL, I2S_CTRL_RXBIRQWL, u32Level); +} + +/** + * @brief Set the communication protocol of I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Protocol Communication protocol + * This parameter can be one of the following values: + * @arg I2S_PROTOCOL_PHILLIPS: Phillips protocol + * @arg I2S_PROTOCOL_MSB: MSB justified protocol + * @arg I2S_PROTOCOL_LSB: LSB justified protocol + * @arg I2S_PROTOCOL_PCM_SHORT: PCM short-frame protocol + * @arg I2S_PROTOCOL_PCM_LONG: PCM long-frame protocol + * @retval None + */ +void I2S_SetProtocol(CM_I2S_TypeDef *I2Sx, uint32_t u32Protocol) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_PROTOCOL(u32Protocol)); + + MODIFY_REG32(I2Sx->CFGR, (I2S_CFGR_I2SSTD | I2S_CFGR_PCMSYNC), u32Protocol); +} + +/** + * @brief Set the audio frequency for the I2S communication. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Freq Audio frequency + * This parameter can be 'I2S_AUDIO_FREQ_DEFAULT' or between + * 'I2S_AUDIO_FREQ_8K' and 'I2S_AUDIO_FREQ_192K': + * @arg I2S_AUDIO_FREQ_192K: FS = 192000Hz + * @arg I2S_AUDIO_FREQ_8K: FS = 8000Hz + * @arg I2S_AUDIO_FREQ_DEFAULT + * @retval int32_t: + * - LL_OK: Set success + * - LL_ERR: Set frequency failed + */ +int32_t I2S_SetAudioFreq(CM_I2S_TypeDef *I2Sx, uint32_t u32Freq) +{ + int32_t i32Ret = LL_OK; + uint32_t u32I2sClk; + uint32_t u32Temp; + uint32_t u32I2sDiv = 2UL; + uint32_t u32I2sOdd = 0UL; + uint32_t u32ChWidth; + + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_AUDIO_FREQ(u32Freq)); + + if (I2S_AUDIO_FREQ_DEFAULT != u32Freq) { + /* Get I2S source Clock frequency */ + if (I2S_CLK_SRC_EXT == READ_REG32_BIT(I2Sx->CTRL, I2S_CTRL_CLKSEL)) { + /* If the external clock frequency is different from the default value, + you need to redefine the macro value (I2S_EXT_CLK_FREQ). */ + u32I2sClk = I2S_EXT_CLK_FREQ; + } else { + u32I2sClk = I2S_GetClockFreq(I2Sx); + } + /* The actual frequency division value is calculated according to the output state of MCK */ + if (I2S_CH_LEN_16BIT != READ_REG32_BIT(I2Sx->CFGR, I2S_CFGR_CHLEN)) { + u32ChWidth = 32UL; + } else { + u32ChWidth = 16UL; + } + + if (I2S_MCK_OUTPUT_ENABLE == READ_REG32_BIT(I2Sx->CTRL, I2S_CTRL_MCKOE)) { + if (I2S_CH_LEN_16BIT != READ_REG32_BIT(I2Sx->CFGR, I2S_CFGR_CHLEN)) { + u32Temp = (((u32I2sClk / (u32ChWidth * 2U * 4U)) * 10U) / u32Freq) + 5U; + } else { + u32Temp = (((u32I2sClk / (u32ChWidth * 2U * 8U)) * 10U) / u32Freq) + 5U; + } + } else { + u32Temp = (((u32I2sClk / (u32ChWidth * 2U)) * 10U) / u32Freq) + 5U; + } + u32Temp = u32Temp / 10U; + u32I2sOdd = u32Temp & 0x01U; + u32I2sDiv = (u32Temp - u32I2sOdd) / 2U; + } + + if ((u32I2sDiv < 2U) || (u32I2sDiv > 0xFFU)) { + i32Ret = LL_ERR; + } else { + /* Set clock division */ + WRITE_REG32(I2Sx->PR, u32I2sDiv); + MODIFY_REG32(I2Sx->CTRL, I2S_CTRL_ODD, (u32I2sOdd << I2S_CTRL_ODD_POS)); + } + + return i32Ret; +} + +/** + * @brief Enable or disable MCK clock output. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2S_MCKOutputCmd(CM_I2S_TypeDef *I2Sx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG32_BIT(I2Sx->CTRL, I2S_CTRL_MCKOE); + } else { + CLR_REG32_BIT(I2Sx->CTRL, I2S_CTRL_MCKOE); + } +} + +/** + * @brief Enable or disable the function of I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Func I2S function + * This parameter can be one or any combination of the following values: + * @arg I2S_FUNC_TX: Transfer function + * @arg I2S_FUNC_RX: Receive function + * @arg I2S_FUNC_ALL: All of the above + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2S_FuncCmd(CM_I2S_TypeDef *I2Sx, uint32_t u32Func, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_FUNC(u32Func)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG32_BIT(I2Sx->CTRL, u32Func); + } else { + CLR_REG32_BIT(I2Sx->CTRL, u32Func); + } +} + +/** + * @brief I2S send data. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Data Send data + * @retval None + */ +void I2S_WriteData(CM_I2S_TypeDef *I2Sx, uint32_t u32Data) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + WRITE_REG32(I2Sx->TXBUF, u32Data); +} + +/** + * @brief I2S receive data. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @retval uint32_t Receive data + */ +uint32_t I2S_ReadData(const CM_I2S_TypeDef *I2Sx) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + return READ_REG32(I2Sx->RXBUF); +} + +/** + * @brief I2S transmit data in polling mode. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] pvTxBuf The pointer to data transmitted buffer + * @param [in] u32Len Data length + * @param [in] u32Timeout Transfer timeout(ms) + * @retval int32_t: + * - LL_OK: Transmit data success + * - LL_ERR_INVD_PARAM: Invalid parameter + * - LL_ERR_TIMEOUT: Transmission timeout + */ +int32_t I2S_Trans(CM_I2S_TypeDef *I2Sx, const void *pvTxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + uint32_t i; + uint32_t u32DataWidth; + + if ((NULL == pvTxBuf) || (0UL == u32Len)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + u32DataWidth = READ_REG32_BIT(I2Sx->CFGR, I2S_CFGR_DATLEN); + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + if (I2S_DATA_LEN_16BIT == u32DataWidth) { + DDL_ASSERT(IS_ADDR_ALIGN_HALFWORD(&((const uint16_t *)pvTxBuf)[0])); + } else { + DDL_ASSERT(IS_ADDR_ALIGN_WORD(&((const uint32_t *)pvTxBuf)[0])); + } + + for (i = 0UL; i < u32Len; i++) { + i32Ret = I2S_WaitStatus(I2Sx, I2S_FLAG_TX_FULL, RESET, u32Timeout); + if (LL_OK != i32Ret) { + break; + } + + if (I2S_DATA_LEN_16BIT == u32DataWidth) { + WRITE_REG32(I2Sx->TXBUF, ((const uint16_t *)pvTxBuf)[i]); + } else { + WRITE_REG32(I2Sx->TXBUF, ((const uint32_t *)pvTxBuf)[i]); + } + } + } + + return i32Ret; +} + +/** + * @brief I2S receive data in polling mode. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] pvRxBuf The pointer to data received buffer + * @param [in] u32Len Data length + * @param [in] u32Timeout Transfer timeout(ms) + * @retval int32_t: + * - LL_OK: Receive data success + * - LL_ERR_INVD_PARAM: Invalid parameter + * - LL_ERR_TIMEOUT: Transmission timeout + */ +int32_t I2S_Receive(const CM_I2S_TypeDef *I2Sx, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + uint32_t i; + uint32_t u32DataWidth; + uint32_t u32Temp; + + if ((NULL == pvRxBuf) || (0UL == u32Len)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + u32DataWidth = READ_REG32_BIT(I2Sx->CFGR, I2S_CFGR_DATLEN); + if (((I2S_DATA_LEN_16BIT == u32DataWidth) && IS_ADDR_ALIGN_HALFWORD(&((const uint16_t *)pvRxBuf)[0])) || + (IS_ADDR_ALIGN_WORD(&((const uint32_t *)pvRxBuf)[0]))) { + for (i = 0UL; i < u32Len; i++) { + i32Ret = I2S_WaitStatus(I2Sx, I2S_FLAG_RX_EMPTY, RESET, u32Timeout); + if (LL_OK != i32Ret) { + break; + } + + u32Temp = READ_REG32(I2Sx->RXBUF); + if (I2S_DATA_LEN_16BIT == u32DataWidth) { + ((uint16_t *)pvRxBuf)[i] = (uint16_t)(u32Temp & 0xFFFFUL); + } else if (I2S_DATA_LEN_24BIT == u32DataWidth) { + ((uint32_t *)pvRxBuf)[i] = u32Temp & 0xFFFFFFUL; + } else { + ((uint32_t *)pvRxBuf)[i] = u32Temp; + } + } + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + } + + return i32Ret; +} + +/** + * @brief I2S transmit and receive data in polling mode. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] pvTxBuf The pointer to data transmitted buffer + * @param [in] pvRxBuf The pointer to data received buffer + * @param [in] u32Len Data length + * @param [in] u32Timeout Transfer timeout(ms) + * @retval int32_t: + * - LL_OK: Receive data success + * - LL_ERR_INVD_PARAM: Invalid parameter + * - LL_ERR_TIMEOUT: Transmission timeout + */ +int32_t I2S_TransReceive(CM_I2S_TypeDef *I2Sx, const void *pvTxBuf, + void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + int32_t i32Ret; + uint32_t u32TxCnt = 0U; + uint32_t u32RxCnt = 0U; + uint32_t u32DataWidth; + uint32_t u32Temp; + uint8_t u8BreakFlag = 0U; + + if ((NULL == pvTxBuf) || (NULL == pvRxBuf) || (0UL == u32Len)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + u32DataWidth = READ_REG32_BIT(I2Sx->CFGR, I2S_CFGR_DATLEN); + if (((I2S_DATA_LEN_16BIT == u32DataWidth) && IS_ADDR_ALIGN_HALFWORD(&((const uint16_t *)pvTxBuf)[0]) && IS_ADDR_ALIGN_HALFWORD(&((const uint16_t *)pvRxBuf)[0])) || + (IS_ADDR_ALIGN_WORD(&((const uint32_t *)pvTxBuf)[0]) && IS_ADDR_ALIGN_WORD(&((const uint32_t *)pvRxBuf)[0]))) { + i32Ret = I2S_WaitStatus(I2Sx, I2S_FLAG_TX_FULL, RESET, u32Timeout); + if (LL_OK == i32Ret) { + /* Preload data */ + if (I2S_DATA_LEN_16BIT == u32DataWidth) { + WRITE_REG32(I2Sx->TXBUF, ((const uint16_t *)pvTxBuf)[u32TxCnt]); + } else { + WRITE_REG32(I2Sx->TXBUF, ((const uint32_t *)pvTxBuf)[u32TxCnt]); + } + u32TxCnt++; + + for (;;) { + /* Transmit data */ + if (u32TxCnt < u32Len) { + i32Ret = I2S_WaitStatus(I2Sx, I2S_FLAG_TX_FULL, RESET, u32Timeout); + if (LL_OK != i32Ret) { + u8BreakFlag = 1U; + } else { + if (I2S_DATA_LEN_16BIT == u32DataWidth) { + WRITE_REG32(I2Sx->TXBUF, ((const uint16_t *)pvTxBuf)[u32TxCnt]); + } else { + WRITE_REG32(I2Sx->TXBUF, ((const uint32_t *)pvTxBuf)[u32TxCnt]); + } + u32TxCnt++; + } + } + /* Receive data */ + if ((1U != u8BreakFlag) && (u32RxCnt < u32Len)) { + i32Ret = I2S_WaitStatus(I2Sx, I2S_FLAG_RX_EMPTY, RESET, u32Timeout); + if (LL_OK != i32Ret) { + u8BreakFlag = 1U; + } else { + u32Temp = READ_REG32(I2Sx->RXBUF); + if (I2S_DATA_LEN_16BIT == u32DataWidth) { + ((uint16_t *)pvRxBuf)[u32RxCnt] = (uint16_t)(u32Temp & 0xFFFFUL); + } else if (I2S_DATA_LEN_24BIT == u32DataWidth) { + ((uint32_t *)pvRxBuf)[u32RxCnt] = u32Temp & 0xFFFFFFUL; + } else { + ((uint32_t *)pvRxBuf)[u32RxCnt] = u32Temp; + } + u32RxCnt++; + } + } + + /* Complete the transmission */ + if ((1U == u8BreakFlag) || ((u32Len == u32TxCnt) && (u32Len == u32RxCnt))) { + break; + } + } + } + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + } + + return i32Ret; +} + +/** + * @brief Enable or disable specified I2S interrupt. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32IntType Interrupt type + * This parameter can be one or any combination of the following values: + * @arg I2S_INT_TX: Transfer interrupt + * @arg I2S_INT_RX: Receive interrupt + * @arg I2S_INT_ERR: Communication error interrupt + * @arg I2S_INT_ALL: All of the above + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2S_IntCmd(CM_I2S_TypeDef *I2Sx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG32_BIT(I2Sx->CTRL, u32IntType); + } else { + CLR_REG32_BIT(I2Sx->CTRL, u32IntType); + } +} + +/** + * @brief Get I2S flag status. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Flag I2S flag type + * This parameter can be one or any combination of the following values: + * @arg I2S_FLAG_TX_ALARM: Transfer buffer alarm flag + * @arg I2S_FLAG_RX_ALARM: Receive buffer alarm flag + * @arg I2S_FLAG_TX_EMPTY: Transfer buffer empty flag + * @arg I2S_FLAG_TX_FULL: Transfer buffer full flag + * @arg I2S_FLAG_RX_EMPTY: Receive buffer empty flag + * @arg I2S_FLAG_RX_FULL: Receive buffer full flag + * @arg I2S_FLAG_TX_ERR: Transfer overflow or underflow flag + * @arg I2S_FLAG_RX_ERR: Receive overflow flag + * @arg I2S_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t I2S_GetStatus(const CM_I2S_TypeDef *I2Sx, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + uint32_t u32NormalFlag; + uint32_t u32ErrorFlag; + + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_FLAG(u32Flag)); + + u32NormalFlag = u32Flag & 0xFFFFUL; + u32ErrorFlag = u32Flag >> 16U; + if (0UL != u32NormalFlag) { + if (0UL != (READ_REG32_BIT(I2Sx->SR, u32NormalFlag))) { + enFlagSta = SET; + } + } + if ((RESET == enFlagSta) && (0UL != u32ErrorFlag)) { + if (0UL != (READ_REG32_BIT(I2Sx->ER, u32ErrorFlag))) { + enFlagSta = SET; + } + } + + return enFlagSta; +} + +/** + * @brief Clear I2S flag. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Flag I2S flag type + * This parameter can be one or any combination of the following values: + * @arg I2S_FLAG_TX_ERR: Transfer overflow or underflow flag + * @arg I2S_FLAG_RX_ERR: Receive overflow flag + * @arg I2S_FLAG_CLR_ALL: All of the above + * @retval None + */ +void I2S_ClearStatus(CM_I2S_TypeDef *I2Sx, uint32_t u32Flag) +{ + uint32_t u32ErrorFlag; + + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_CLR_FLAG(u32Flag)); + + u32ErrorFlag = u32Flag >> 16U; + WRITE_REG32(I2Sx->ER, u32ErrorFlag); +} + +/** + * @} + */ + +#endif /* LL_I2S_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_icg.c b/mcu/lib/src/hc32_ll_icg.c new file mode 100644 index 0000000..e8e40d5 --- /dev/null +++ b/mcu/lib/src/hc32_ll_icg.c @@ -0,0 +1,118 @@ +/** + ******************************************************************************* + * @file hc32_ll_icg.c + * @brief This file provides firmware functions to manage the Initial + * Configuration(ICG). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_icg.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_ICG ICG + * @brief Initial Configuration Driver Library + * @{ + */ + +#if (LL_ICG_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ICG_Local_Macros ICG Local Macros + * @{ + */ + +/** + * @brief ICG Start Address + */ +#define ICG_START_ADDR 0x400 +#define ICG_START_ADDR_AC6 ".ARM.__at_0x400" + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @brief ICG parameters configuration + */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +const uint32_t u32ICGValue[] __attribute__((section(ICG_START_ADDR_AC6))) = +#elif defined (__GNUC__) && !defined (__CC_ARM) +const uint32_t u32ICGValue[] __attribute__((section(".icg_sec"))) = +#elif defined (__CC_ARM) +const uint32_t u32ICGValue[] __attribute__((at(ICG_START_ADDR))) = +#elif defined (__ICCARM__) +#pragma location = ICG_START_ADDR +__root static const uint32_t u32ICGValue[] = +#else +#error "unsupported compiler!!" +#endif +{ + /* ICG 0~1 */ + ICG_REG_CFG0_CONST, + ICG_REG_CFG1_CONST, + /* Reserved 2~7 */ + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, +}; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +#endif /* LL_ICG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ + diff --git a/mcu/lib/src/hc32_ll_interrupts.c b/mcu/lib/src/hc32_ll_interrupts.c new file mode 100644 index 0000000..89158b9 --- /dev/null +++ b/mcu/lib/src/hc32_ll_interrupts.c @@ -0,0 +1,2196 @@ +/** + ******************************************************************************* + * @file hc32_ll_interrupts.c + * @brief This file provides firmware functions to manage the Interrupt Controller + * (INTC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-10-31 CDT Delete comment code + 2023-01-15 CDT Add macro-definition: EIRQFR_REG/NMIENR_REG/INTWKEN_REG + 2023-06-30 CDT IRQxxx_Handler add __DSB for Arm Errata 838869 + 2023-09-30 CDT Modify micro define EIRQCFR_REG and EIRQFR_REG base RM + Remove space line + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_interrupts.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_INTERRUPTS INTERRUPTS + * @brief INTC Driver Library + * @{ + */ + +#if (LL_INTERRUPTS_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup INTC_Local_Macros INTC Local Macros + * @{ + */ +/** + * @brief Maximum IRQ handler number + */ +#define IRQ_NUM_MAX (128U) +#define IRQn_MIN (INT000_IRQn) +#define IRQn_MAX (INT127_IRQn) +#define IRQn_OFFSET (0U) +#define EXTINT_CH_NUM_MAX (16U) +#define EIRQCFR_REG (CM_INTC->EIFCR) +#define EIRQFR_REG (CM_INTC->EIFR) +#define NMIENR_REG (CM_INTC->NMIENR) +#define NMICFR_REG (CM_INTC->NMICFR) +#define INTSEL_REG (uint32_t)(&CM_INTC->SEL0) +#define INTWKEN_REG (CM_INTC->WUPEN) +#define INTSEL_RST_VALUE (0x1FFUL) +#define IRQ_GRP_MOD (32UL) +#define IRQ_GRP_NUM (6UL) +#define IRQ_GRP_LOW (32UL) +#define IRQ_GRP_HIGH (37UL) +#define IRQ_GRP_BASE (32UL) + +/** + * @defgroup INTC_Check_Parameters_Validity INTC Check Parameters Validity + * @{ + */ +/*! Parameter validity check for wakeup source from stop mode. */ +#define IS_INTC_WKUP_SRC(src) \ +( ((src) != 0x00UL) && \ + (((src) | INTC_WUPEN_ALL) == INTC_WUPEN_ALL)) + +/*! Parameter validity check for event index. */ +#define IS_INTC_EVT(event) \ +( ((event) != 0x00UL) && \ + (((event) | INTC_EVT_ALL) == INTC_EVT_ALL)) + +/*! Parameter validity check for interrupt index. */ +#define IS_INTC_INT(it) \ +( ((it) != 0x00UL) && \ + (((it) | INTC_INT_ALL) == INTC_INT_ALL)) + +/*! Parameter validity check for software interrupt index. */ +#define IS_INTC_SWI(swi) \ +( ((swi) != 0x00UL) && \ + (((swi) | SWINT_ALL) == SWINT_ALL)) + +/*! Parameter validity check for NMI trigger source. */ +#define IS_NMI_SRC(src) \ +( ((src) != 0x00UL) && \ + (((src) | NMI_SRC_ALL) == NMI_SRC_ALL)) + +/*! Parameter validity check for NMI trigger edge. */ +#define IS_NMI_TRIG(trigger) \ +( ((trigger) == NMI_TRIG_FALLING) || \ + ((trigger) == NMI_TRIG_RISING)) + +/*! Parameter validity check for NMI filter A function. */ +#define IS_NMI_FAE(fae) \ +( ((fae) == NMI_FILTER_OFF) || \ + ((fae) == NMI_FILTER_ON)) + +/*! Parameter validity check for NMI filter A clock division. */ +#define IS_NMI_FACLK(faclk) \ +( ((faclk) == NMI_FCLK_DIV1) || \ + ((faclk) == NMI_FCLK_DIV8) || \ + ((faclk) == NMI_FCLK_DIV32) || \ + ((faclk) == NMI_FCLK_DIV64)) + +/*! Parameter validity check for EXTINT filter A function. */ +#define IS_EXTINT_FAE(fae) \ +( ((fae) == EXTINT_FILTER_OFF) || \ + ((fae) == EXTINT_FILTER_ON)) + +/*! Parameter validity check for EXTINT filter A clock division. */ +#define IS_EXTINT_FACLK(faclk) \ +( ((faclk) == EXTINT_FCLK_DIV1) || \ + ((faclk) == EXTINT_FCLK_DIV8) || \ + ((faclk) == EXTINT_FCLK_DIV32) || \ + ((faclk) == EXTINT_FCLK_DIV64)) + +/*! Parameter validity check for EXTINT trigger edge. */ +#define IS_EXTINT_TRIG(trigger) \ +( ((trigger) == EXTINT_TRIG_LOW) || \ + ((trigger) == EXTINT_TRIG_RISING) || \ + ((trigger) == EXTINT_TRIG_FALLING) || \ + ((trigger) == EXTINT_TRIG_BOTH)) + +/*! Parameter validity check for EXTINT channel. */ +#define IS_EXTINT_CH(ch) \ +( ((ch) != 0x00UL) && \ + (((ch) | EXTINT_CH_ALL) == EXTINT_CH_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +/** + * @defgroup INTC_Local_Variable INTC Local Variable + * @{ + */ +static func_ptr_t m_apfnIrqHandler[IRQ_NUM_MAX] = {NULL}; +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup INTC_Global_Functions INTC Global Functions + * @{ + */ +/** + * @brief IRQ sign in function + * @param [in] pstcIrqSignConfig: pointer of IRQ registration structure + * @arg enIntSrc: can be any value @ref en_int_src_t + * @arg enIRQn: can be any value from IRQn_MIN ~ IRQn_MAX for different product + * @arg pfnCallback: Callback function + * @retval int32_t: + * - LL_OK: IRQ register successfully + * - LL_ERR_INVD_PARAM: IRQ No. and Peripheral Int source are not match; NULL pointer. + * - LL_ERR_UNINIT: Specified IRQ entry was signed before. + */ +int32_t INTC_IrqSignIn(const stc_irq_signin_config_t *pstcIrqSignConfig) +{ + __IO uint32_t *INTC_SELx; + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcIrqSignConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(pstcIrqSignConfig->enIntSrc <= INT_SRC_MAX); + /* IRQ032~127 whether out of range */ + if ((((((uint32_t)pstcIrqSignConfig->enIntSrc / IRQ_GRP_MOD) * IRQ_GRP_NUM + IRQ_GRP_LOW) > \ + (uint32_t)pstcIrqSignConfig->enIRQn) || \ + ((((uint32_t)pstcIrqSignConfig->enIntSrc / IRQ_GRP_MOD) * IRQ_GRP_NUM + IRQ_GRP_HIGH) < \ + (uint32_t)pstcIrqSignConfig->enIRQn)) && \ + ((uint32_t)pstcIrqSignConfig->enIRQn >= IRQ_GRP_BASE)) { + i32Ret = LL_ERR_INVD_PARAM; + } + + else { + INTC_SELx = (__IO uint32_t *)(INTSEL_REG + (4U * (uint32_t)(pstcIrqSignConfig->enIRQn))); + /* for MISRAC2004-12.4 */ + if (INTSEL_RST_VALUE == ((*INTC_SELx) & INTSEL_RST_VALUE)) { + WRITE_REG32(*INTC_SELx, pstcIrqSignConfig->enIntSrc); + m_apfnIrqHandler[pstcIrqSignConfig->enIRQn] = pstcIrqSignConfig->pfnCallback; + } else if ((uint32_t)(pstcIrqSignConfig->enIntSrc) == ((*INTC_SELx) & INTSEL_RST_VALUE)) { + m_apfnIrqHandler[pstcIrqSignConfig->enIRQn] = pstcIrqSignConfig->pfnCallback; + } else { + i32Ret = LL_ERR_UNINIT; + } + } + } + return i32Ret; +} + +/** + * @brief IRQ sign out function + * @param [in] enIRQn: can be any value from IRQn_MIN ~ IRQn_MAX for different product + * @retval int32_t: + * - LL_OK: IRQ sign out successfully + * - LL_ERR_INVD_PARAM: IRQ No. is out of range + */ +int32_t INTC_IrqSignOut(IRQn_Type enIRQn) +{ + __IO uint32_t *INTC_SELx; + int32_t i32Ret = LL_OK; + + if ((enIRQn < IRQn_MIN) || (enIRQn > IRQn_MAX)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + INTC_SELx = (__IO uint32_t *)(INTSEL_REG + (4UL * (uint32_t)enIRQn)); + WRITE_REG32(*INTC_SELx, INTSEL_RST_VALUE); + m_apfnIrqHandler[(uint8_t)enIRQn - IRQn_OFFSET] = NULL; + } + return i32Ret; +} + +/** + * @brief Stop mode wake-up source configure + * @param [in] u32WakeupSrc: Wake-up source, @ref INTC_Stop_Wakeup_Source_Sel for details + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void INTC_WakeupSrcCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_INTC_WKUP_SRC(u32WakeupSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(INTWKEN_REG, u32WakeupSrc); + } else { + CLR_REG32_BIT(INTWKEN_REG, u32WakeupSrc); + } +} + +/** + * @brief Event or Interrupt output configure + * @param [in] u32Event: Event index, @ref INTC_Event_Channel_Sel for details + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void INTC_EventCmd(uint32_t u32Event, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_INTC_EVT(u32Event)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_INTC->EVTER, u32Event); + } else { + CLR_REG32_BIT(CM_INTC->EVTER, u32Event); + } +} + +/** + * @brief Interrupt function configure + * @param [in] u32Int: Interrupt index, @ref INT_Channel_Sel for details + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void INTC_IntCmd(uint32_t u32Int, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_INTC_INT(u32Int)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_INTC->IER, u32Int); + } else { + CLR_REG32_BIT(CM_INTC->IER, u32Int); + } +} + +/** + * @brief Software Interrupt initialize function + * @param [in] u32Ch: Software Interrupt channel, @ref SWINT_Channel_Sel for details + * @param [in] pfnCallback: Callback function + * @param [in] u32Priority: Software interrupt priority + * @retval None + */ +void INTC_SWIntInit(uint32_t u32Ch, const func_ptr_t pfnCallback, uint32_t u32Priority) +{ + stc_irq_signin_config_t stcIrqSignConfig; + + stcIrqSignConfig.enIRQn = (IRQn_Type)(__CLZ(__RBIT(u32Ch))); + stcIrqSignConfig.enIntSrc = (en_int_src_t)(__CLZ(__RBIT(u32Ch))); + /* Callback function */ + stcIrqSignConfig.pfnCallback = pfnCallback; + (void)INTC_IrqSignIn(&stcIrqSignConfig); + + NVIC_ClearPendingIRQ(stcIrqSignConfig.enIRQn); + NVIC_SetPriority(stcIrqSignConfig.enIRQn, u32Priority); + NVIC_EnableIRQ(stcIrqSignConfig.enIRQn); +} + +/** + * @brief Software Interrupt function configure + * @param [in] u32SWInt: Software Interrupt channel, @ref SWINT_Channel_Sel for details + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void INTC_SWIntCmd(uint32_t u32SWInt, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_INTC_SWI(u32SWInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_INTC->SWIER, u32SWInt); + } else { + CLR_REG32_BIT(CM_INTC->SWIER, u32SWInt); + } +} + +/** + * @brief Initialize NMI. Fill each pstcNmiInit with default value + * @param [in] pstcNmiInit: Pointer to a stc_nmi_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: NMI structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t NMI_StructInit(stc_nmi_init_t *pstcNmiInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcNmiInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcNmiInit->u32Src = 0UL; + pstcNmiInit->u32Edge = NMI_TRIG_FALLING; + pstcNmiInit->u32Filter = NMI_FILTER_OFF; + pstcNmiInit->u32FilterClock = NMI_FCLK_DIV1; + } + return i32Ret; +} + +/** + * @brief Initialize NMI. + * @param [in] pstcNmiInit: Pointer to a pstcNmiInit structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: NMI initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t NMI_Init(const stc_nmi_init_t *pstcNmiInit) +{ + int32_t i32Ret = LL_OK; + uint32_t u32NMICR = 0UL; + + /* Check if pointer is NULL */ + if (NULL == pstcNmiInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameter validity checking */ + DDL_ASSERT(IS_NMI_SRC(pstcNmiInit->u32Src)); + /* Clear all NMI trigger source before set */ + WRITE_REG32(NMICFR_REG, NMI_SRC_ALL); + + /* NMI trigger source configure */ + WRITE_REG32(NMIENR_REG, pstcNmiInit->u32Src); + + DDL_ASSERT(IS_NMI_TRIG(pstcNmiInit->u32Edge)); + DDL_ASSERT(IS_NMI_FAE(pstcNmiInit->u32Filter)); + DDL_ASSERT(IS_NMI_FACLK(pstcNmiInit->u32FilterClock)); + u32NMICR |= pstcNmiInit->u32Edge | pstcNmiInit->u32Filter | pstcNmiInit->u32FilterClock; + WRITE_REG32(CM_INTC->NMICR, u32NMICR); + } + return i32Ret; +} + +/** + * @brief Get NMI trigger source + * @param [in] u32Src: NMI trigger source, @ref NMI_TriggerSrc_Sel for details + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t NMI_GetNmiStatus(uint32_t u32Src) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_NMI_SRC(u32Src)); + + return (((READ_REG32(CM_INTC->NMIFR) & u32Src)) != 0UL) ? SET : RESET; +} + +/** + * @brief Set NMI trigger source + * @param [in] u32Src: NMI trigger source, @ref NMI_TriggerSrc_Sel for details + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void NMI_NmiSrcCmd(uint32_t u32Src, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_NMI_SRC(u32Src)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(NMIENR_REG, u32Src); + } else { + CLR_REG32_BIT(NMIENR_REG, u32Src); + } +} + +/** + * @brief Clear specified NMI trigger source + * @param [in] u32Src: NMI trigger source, @ref NMI_TriggerSrc_Sel for diff. MCU in details + * @retval None + */ +void NMI_ClearNmiStatus(uint32_t u32Src) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_NMI_SRC(u32Src)); + + SET_REG32_BIT(NMICFR_REG, u32Src); +} + +/** + * @brief Initialize External interrupt. + * @param [in] u32Ch: ExtInt channel. + * @param [in] pstcExtIntInit: Pointer to a stc_extint_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: EXTINT initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EXTINT_Init(uint32_t u32Ch, const stc_extint_init_t *pstcExtIntInit) +{ + uint8_t u8ExtIntPos; + int32_t i32Ret = LL_OK; + uint32_t EIRQCRVal; + __IO uint32_t *EIRQCRx; + + /* Check if pointer is NULL */ + if (NULL == pstcExtIntInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameter validity checking */ + DDL_ASSERT(IS_EXTINT_CH(u32Ch)); + DDL_ASSERT(IS_EXTINT_FAE(pstcExtIntInit->u32Filter)); + DDL_ASSERT(IS_EXTINT_FACLK(pstcExtIntInit->u32FilterClock)); + DDL_ASSERT(IS_EXTINT_TRIG(pstcExtIntInit->u32Edge)); + for (u8ExtIntPos = 0U; u8ExtIntPos < EXTINT_CH_NUM_MAX; u8ExtIntPos++) { + if (0UL != (u32Ch & (1UL << u8ExtIntPos))) { + EIRQCRVal = pstcExtIntInit->u32Filter | pstcExtIntInit->u32FilterClock | \ + pstcExtIntInit->u32Edge; + EIRQCRx = (__IO uint32_t *)((uint32_t)&CM_INTC->EIRQCR0 + 4UL * u8ExtIntPos); + WRITE_REG32(*EIRQCRx, EIRQCRVal); + } + } + } + return i32Ret; +} + +/** + * @brief Initialize ExtInt. Fill each pstcExtIntInit with default value + * @param [in] pstcExtIntInit: Pointer to a stc_extint_init_t structure + * that contains configuration information. + * @retval int32_t: + * - LL_OK: EXTINT structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EXTINT_StructInit(stc_extint_init_t *pstcExtIntInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcExtIntInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcExtIntInit->u32Filter = EXTINT_FILTER_OFF; + pstcExtIntInit->u32FilterClock = EXTINT_FCLK_DIV1; + pstcExtIntInit->u32Edge = EXTINT_TRIG_FALLING; + } + return i32Ret; +} + +/** + * @brief Clear specified External interrupt trigger source + * @param [in] u32ExtIntCh: External interrupt channel, @ref EXTINT_Channel_Sel for details + * @retval None + */ +void EXTINT_ClearExtIntStatus(uint32_t u32ExtIntCh) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_EXTINT_CH(u32ExtIntCh)); + + SET_REG32_BIT(EIRQCFR_REG, u32ExtIntCh); +} + +/** + * @brief Get specified External interrupt trigger source + * @param [in] u32ExtIntCh: External interrupt channel, @ref EXTINT_Channel_Sel for details + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EXTINT_GetExtIntStatus(uint32_t u32ExtIntCh) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_EXTINT_CH(u32ExtIntCh)); + + return ((READ_REG16(EIRQFR_REG) & u32ExtIntCh) != 0U) ? SET : RESET; +} + +/** + * @brief Interrupt No.000 IRQ handler + * @param None + * @retval None + */ +void IRQ000_Handler(void) +{ + m_apfnIrqHandler[INT000_IRQn](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.001 IRQ handler + * @param None + * @retval None + */ +void IRQ001_Handler(void) +{ + m_apfnIrqHandler[INT001_IRQn](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.002 IRQ handler + * @param None + * @retval None + */ +void IRQ002_Handler(void) +{ + m_apfnIrqHandler[INT002_IRQn](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.003 IRQ handler + * @param None + * @retval None + */ +void IRQ003_Handler(void) +{ + m_apfnIrqHandler[INT003_IRQn](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.004 IRQ handler + * @param None + * @retval None + */ +void IRQ004_Handler(void) +{ + m_apfnIrqHandler[INT004_IRQn](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.005 IRQ handler + * @param None + * @retval None + */ +void IRQ005_Handler(void) +{ + m_apfnIrqHandler[INT005_IRQn](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.006 IRQ handler + * @param None + * @retval None + */ +void IRQ006_Handler(void) +{ + m_apfnIrqHandler[INT006_IRQn](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.007 IRQ handler + * @param None + * @retval None + */ +void IRQ007_Handler(void) +{ + m_apfnIrqHandler[INT007_IRQn](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.008 IRQ handler + * @param None + * @retval None + */ +void IRQ008_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT008_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.009 IRQ handler + * @param None + * @retval None + */ +void IRQ009_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT009_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.010 IRQ handler + * @param None + * @retval None + */ +void IRQ010_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT010_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.011 IRQ handler + * @param None + * @retval None + */ +void IRQ011_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT011_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.012 IRQ handler + * @param None + * @retval None + */ +void IRQ012_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT012_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.013 IRQ handler + * @param None + * @retval None + */ +void IRQ013_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT013_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.014 IRQ handler + * @param None + * @retval None + */ +void IRQ014_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT014_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.015 IRQ handler + * @param None + * @retval None + */ +void IRQ015_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT015_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.016 IRQ handler + * @param None + * @retval None + */ +void IRQ016_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT016_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.017 IRQ handler + * @param None + * @retval None + */ +void IRQ017_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT017_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.018 IRQ handler + * @param None + * @retval None + */ +void IRQ018_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT018_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.019 IRQ handler + * @param None + * @retval None + */ +void IRQ019_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT019_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.020 IRQ handler + * @param None + * @retval None + */ +void IRQ020_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT020_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.021 IRQ handler + * @param None + * @retval None + */ +void IRQ021_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT021_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.022 IRQ handler + * @param None + * @retval None + */ +void IRQ022_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT022_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.023 IRQ handler + * @param None + * @retval None + */ +void IRQ023_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT023_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.024 IRQ handler + * @param None + * @retval None + */ +void IRQ024_Handler(void) +{ + m_apfnIrqHandler[INT024_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.025 IRQ handler + * @param None + * @retval None + */ +void IRQ025_Handler(void) +{ + m_apfnIrqHandler[INT025_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.026 IRQ handler + * @param None + * @retval None + */ +void IRQ026_Handler(void) +{ + m_apfnIrqHandler[INT026_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.027 IRQ handler + * @param None + * @retval None + */ +void IRQ027_Handler(void) +{ + m_apfnIrqHandler[INT027_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.028 IRQ handler + * @param None + * @retval None + */ +void IRQ028_Handler(void) +{ + m_apfnIrqHandler[INT028_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.029 IRQ handler + * @param None + * @retval None + */ +void IRQ029_Handler(void) +{ + m_apfnIrqHandler[INT029_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.030 IRQ handler + * @param None + * @retval None + */ +void IRQ030_Handler(void) +{ + m_apfnIrqHandler[INT030_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.031 IRQ handler + * @param None + * @retval None + */ +void IRQ031_Handler(void) +{ + m_apfnIrqHandler[INT031_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.032 IRQ handler + * @param None + * @retval None + */ +void IRQ032_Handler(void) +{ + m_apfnIrqHandler[INT032_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.033 IRQ handler + * @param None + * @retval None + */ +void IRQ033_Handler(void) +{ + m_apfnIrqHandler[INT033_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.034 IRQ handler + * @param None + * @retval None + */ +void IRQ034_Handler(void) +{ + m_apfnIrqHandler[INT034_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.035 IRQ handler + * @param None + * @retval None + */ +void IRQ035_Handler(void) +{ + m_apfnIrqHandler[INT035_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.036 IRQ handler + * @param None + * @retval None + */ +void IRQ036_Handler(void) +{ + m_apfnIrqHandler[INT036_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.037 IRQ handler + * @param None + * @retval None + */ +void IRQ037_Handler(void) +{ + m_apfnIrqHandler[INT037_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.038 IRQ handler + * @param None + * @retval None + */ +void IRQ038_Handler(void) +{ + m_apfnIrqHandler[INT038_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.039 IRQ handler + * @param None + * @retval None + */ +void IRQ039_Handler(void) +{ + m_apfnIrqHandler[INT039_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.040 IRQ handler + * @param None + * @retval None + */ +void IRQ040_Handler(void) +{ + m_apfnIrqHandler[INT040_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.041 IRQ handler + * @param None + * @retval None + */ +void IRQ041_Handler(void) +{ + m_apfnIrqHandler[INT041_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.042 IRQ handler + * @param None + * @retval None + */ +void IRQ042_Handler(void) +{ + m_apfnIrqHandler[INT042_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.043 IRQ handler + * @param None + * @retval None + */ +void IRQ043_Handler(void) +{ + m_apfnIrqHandler[INT043_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.044 IRQ handler + * @param None + * @retval None + */ +void IRQ044_Handler(void) +{ + m_apfnIrqHandler[INT044_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.045 IRQ handler + * @param None + * @retval None + */ +void IRQ045_Handler(void) +{ + m_apfnIrqHandler[INT045_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.046 IRQ handler + * @param None + * @retval None + */ +void IRQ046_Handler(void) +{ + m_apfnIrqHandler[INT046_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.047 IRQ handler + * @param None + * @retval None + */ +void IRQ047_Handler(void) +{ + m_apfnIrqHandler[INT047_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.048 IRQ handler + * @param None + * @retval None + */ +void IRQ048_Handler(void) +{ + m_apfnIrqHandler[INT048_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.049 IRQ handler + * @param None + * @retval None + */ +void IRQ049_Handler(void) +{ + m_apfnIrqHandler[INT049_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.050 IRQ handler + * @param None + * @retval None + */ +void IRQ050_Handler(void) +{ + m_apfnIrqHandler[INT050_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.051 IRQ handler + * @param None + * @retval None + */ +void IRQ051_Handler(void) +{ + m_apfnIrqHandler[INT051_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.052 IRQ handler + * @param None + * @retval None + */ +void IRQ052_Handler(void) +{ + m_apfnIrqHandler[INT052_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.053 IRQ handler + * @param None + * @retval None + */ +void IRQ053_Handler(void) +{ + m_apfnIrqHandler[INT053_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.054 IRQ handler + * @param None + * @retval None + */ +void IRQ054_Handler(void) +{ + m_apfnIrqHandler[INT054_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.055 IRQ handler + * @param None + * @retval None + */ +void IRQ055_Handler(void) +{ + m_apfnIrqHandler[INT055_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.056 IRQ handler + * @param None + * @retval None + */ +void IRQ056_Handler(void) +{ + m_apfnIrqHandler[INT056_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.057 IRQ handler + * @param None + * @retval None + */ +void IRQ057_Handler(void) +{ + m_apfnIrqHandler[INT057_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.058 IRQ handler + * @param None + * @retval None + */ +void IRQ058_Handler(void) +{ + m_apfnIrqHandler[INT058_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.059 IRQ handler + * @param None + * @retval None + */ +void IRQ059_Handler(void) +{ + m_apfnIrqHandler[INT059_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.060 IRQ handler + * @param None + * @retval None + */ +void IRQ060_Handler(void) +{ + m_apfnIrqHandler[INT060_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.061 IRQ handler + * @param None + * @retval None + */ +void IRQ061_Handler(void) +{ + m_apfnIrqHandler[INT061_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.062 IRQ handler + * @param None + * @retval None + */ +void IRQ062_Handler(void) +{ + m_apfnIrqHandler[INT062_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.063 IRQ handler + * @param None + * @retval None + */ +void IRQ063_Handler(void) +{ + m_apfnIrqHandler[INT063_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.064 IRQ handler + * @param None + * @retval None + */ +void IRQ064_Handler(void) +{ + m_apfnIrqHandler[INT064_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.065 IRQ handler + * @param None + * @retval None + */ +void IRQ065_Handler(void) +{ + m_apfnIrqHandler[INT065_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.066 IRQ handler + * @param None + * @retval None + */ +void IRQ066_Handler(void) +{ + m_apfnIrqHandler[INT066_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.067 IRQ handler + * @param None + * @retval None + */ +void IRQ067_Handler(void) +{ + m_apfnIrqHandler[INT067_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.068 IRQ handler + * @param None + * @retval None + */ +void IRQ068_Handler(void) +{ + m_apfnIrqHandler[INT068_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.069 IRQ handler + * @param None + * @retval None + */ +void IRQ069_Handler(void) +{ + m_apfnIrqHandler[INT069_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.070 IRQ handler + * @param None + * @retval None + */ +void IRQ070_Handler(void) +{ + m_apfnIrqHandler[INT070_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.071 IRQ handler + * @param None + * @retval None + */ +void IRQ071_Handler(void) +{ + m_apfnIrqHandler[INT071_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.072 IRQ handler + * @param None + * @retval None + */ +void IRQ072_Handler(void) +{ + m_apfnIrqHandler[INT072_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.073 IRQ handler + * @param None + * @retval None + */ +void IRQ073_Handler(void) +{ + m_apfnIrqHandler[INT073_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.074 IRQ handler + * @param None + * @retval None + */ +void IRQ074_Handler(void) +{ + m_apfnIrqHandler[INT074_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.075 IRQ handler + * @param None + * @retval None + */ +void IRQ075_Handler(void) +{ + m_apfnIrqHandler[INT075_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.076 IRQ handler + * @param None + * @retval None + */ +void IRQ076_Handler(void) +{ + m_apfnIrqHandler[INT076_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.077 IRQ handler + * @param None + * @retval None + */ +void IRQ077_Handler(void) +{ + m_apfnIrqHandler[INT077_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.078 IRQ handler + * @param None + * @retval None + */ +void IRQ078_Handler(void) +{ + m_apfnIrqHandler[INT078_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.079 IRQ handler + * @param None + * @retval None + */ +void IRQ079_Handler(void) +{ + m_apfnIrqHandler[INT079_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.080 IRQ handler + * @param None + * @retval None + */ +void IRQ080_Handler(void) +{ + m_apfnIrqHandler[INT080_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.081 IRQ handler + * @param None + * @retval None + */ +void IRQ081_Handler(void) +{ + m_apfnIrqHandler[INT081_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.082 IRQ handler + * @param None + * @retval None + */ +void IRQ082_Handler(void) +{ + m_apfnIrqHandler[INT082_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.083 IRQ handler + * @param None + * @retval None + */ +void IRQ083_Handler(void) +{ + m_apfnIrqHandler[INT083_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.084 IRQ handler + * @param None + * @retval None + */ +void IRQ084_Handler(void) +{ + m_apfnIrqHandler[INT084_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.085 IRQ handler + * @param None + * @retval None + */ +void IRQ085_Handler(void) +{ + m_apfnIrqHandler[INT085_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.086 IRQ handler + * @param None + * @retval None + */ +void IRQ086_Handler(void) +{ + m_apfnIrqHandler[INT086_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.087 IRQ handler + * @param None + * @retval None + */ +void IRQ087_Handler(void) +{ + m_apfnIrqHandler[INT087_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.088 IRQ handler + * @param None + * @retval None + */ +void IRQ088_Handler(void) +{ + m_apfnIrqHandler[INT088_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.089 IRQ handler + * @param None + * @retval None + */ +void IRQ089_Handler(void) +{ + m_apfnIrqHandler[INT089_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.090 IRQ handler + * @param None + * @retval None + */ +void IRQ090_Handler(void) +{ + m_apfnIrqHandler[INT090_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.091 IRQ handler + * @param None + * @retval None + */ +void IRQ091_Handler(void) +{ + m_apfnIrqHandler[INT091_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.092 IRQ handler + * @param None + * @retval None + */ +void IRQ092_Handler(void) +{ + m_apfnIrqHandler[INT092_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.093 IRQ handler + * @param None + * @retval None + */ +void IRQ093_Handler(void) +{ + m_apfnIrqHandler[INT093_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.094 IRQ handler + * @param None + * @retval None + */ +void IRQ094_Handler(void) +{ + m_apfnIrqHandler[INT094_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.095 IRQ handler + * @param None + * @retval None + */ +void IRQ095_Handler(void) +{ + m_apfnIrqHandler[INT095_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.096 IRQ handler + * @param None + * @retval None + */ +void IRQ096_Handler(void) +{ + m_apfnIrqHandler[INT096_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.097 IRQ handler + * @param None + * @retval None + */ +void IRQ097_Handler(void) +{ + m_apfnIrqHandler[INT097_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.098 IRQ handler + * @param None + * @retval None + */ +void IRQ098_Handler(void) +{ + m_apfnIrqHandler[INT098_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.099 IRQ handler + * @param None + * @retval None + */ +void IRQ099_Handler(void) +{ + m_apfnIrqHandler[INT099_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.100 IRQ handler + * @param None + * @retval None + */ +void IRQ100_Handler(void) +{ + m_apfnIrqHandler[INT100_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.101 IRQ handler + * @param None + * @retval None + */ +void IRQ101_Handler(void) +{ + m_apfnIrqHandler[INT101_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.102 IRQ handler + * @param None + * @retval None + */ +void IRQ102_Handler(void) +{ + m_apfnIrqHandler[INT102_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.103 IRQ handler + * @param None + * @retval None + */ +void IRQ103_Handler(void) +{ + m_apfnIrqHandler[INT103_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.104 IRQ handler + * @param None + * @retval None + */ +void IRQ104_Handler(void) +{ + m_apfnIrqHandler[INT104_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.105 IRQ handler + * @param None + * @retval None + */ +void IRQ105_Handler(void) +{ + m_apfnIrqHandler[INT105_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.106 IRQ handler + * @param None + * @retval None + */ +void IRQ106_Handler(void) +{ + m_apfnIrqHandler[INT106_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.107 IRQ handler + * @param None + * @retval None + */ +void IRQ107_Handler(void) +{ + m_apfnIrqHandler[INT107_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.108 IRQ handler + * @param None + * @retval None + */ +void IRQ108_Handler(void) +{ + m_apfnIrqHandler[INT108_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.109 IRQ handler + * @param None + * @retval None + */ +void IRQ109_Handler(void) +{ + m_apfnIrqHandler[INT109_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.110 IRQ handler + * @param None + * @retval None + */ +void IRQ110_Handler(void) +{ + m_apfnIrqHandler[INT110_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.111 IRQ handler + * @param None + * @retval None + */ +void IRQ111_Handler(void) +{ + m_apfnIrqHandler[INT111_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.112 IRQ handler + * @param None + * @retval None + */ +void IRQ112_Handler(void) +{ + m_apfnIrqHandler[INT112_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.113 IRQ handler + * @param None + * @retval None + */ +void IRQ113_Handler(void) +{ + m_apfnIrqHandler[INT113_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.114 IRQ handler + * @param None + * @retval None + */ +void IRQ114_Handler(void) +{ + m_apfnIrqHandler[INT114_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.115 IRQ handler + * @param None + * @retval None + */ +void IRQ115_Handler(void) +{ + m_apfnIrqHandler[INT115_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.116 IRQ handler + * @param None + * @retval None + */ +void IRQ116_Handler(void) +{ + m_apfnIrqHandler[INT116_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.117 IRQ handler + * @param None + * @retval None + */ +void IRQ117_Handler(void) +{ + m_apfnIrqHandler[INT117_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.118 IRQ handler + * @param None + * @retval None + */ +void IRQ118_Handler(void) +{ + m_apfnIrqHandler[INT118_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.119 IRQ handler + * @param None + * @retval None + */ +void IRQ119_Handler(void) +{ + m_apfnIrqHandler[INT119_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.120 IRQ handler + * @param None + * @retval None + */ +void IRQ120_Handler(void) +{ + m_apfnIrqHandler[INT120_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.121 IRQ handler + * @param None + * @retval None + */ +void IRQ121_Handler(void) +{ + m_apfnIrqHandler[INT121_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.122 IRQ handler + * @param None + * @retval None + */ +void IRQ122_Handler(void) +{ + m_apfnIrqHandler[INT122_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.123 IRQ handler + * @param None + * @retval None + */ +void IRQ123_Handler(void) +{ + m_apfnIrqHandler[INT123_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.124 IRQ handler + * @param None + * @retval None + */ +void IRQ124_Handler(void) +{ + m_apfnIrqHandler[INT124_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.125 IRQ handler + * @param None + * @retval None + */ +void IRQ125_Handler(void) +{ + m_apfnIrqHandler[INT125_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.126 IRQ handler + * @param None + * @retval None + */ +void IRQ126_Handler(void) +{ + m_apfnIrqHandler[INT126_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.127 IRQ handler + * @param None + * @retval None + */ +void IRQ127_Handler(void) +{ + m_apfnIrqHandler[INT127_IRQn](); + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @} + */ + +#endif /* LL_INTERRUPTS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_keyscan.c b/mcu/lib/src/hc32_ll_keyscan.c new file mode 100644 index 0000000..094d3b8 --- /dev/null +++ b/mcu/lib/src/hc32_ll_keyscan.c @@ -0,0 +1,242 @@ +/** + ******************************************************************************* + * @file hc32_ll_keyscan.c + * @brief This file provides firmware functions to manage the matrix keyscan + * function (KEYSCAN). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-06-30 CDT Add function KEYSCAN_DeInit + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_keyscan.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_KEYSCAN KEYSCAN + * @brief Matrix keyscan Driver Library + * @{ + */ + +#if (LL_KEYSCAN_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup KEYSCAN_Local_Macros KEYSCAN Local Macros + * @{ + */ + +/** + * @defgroup KEYSCAN_Check_Parameters_Validity KEYSCAN Check Parameters Validity + * @{ + */ +/*! Parameter valid check for KEYSCAN HiZ state cycles. */ +#define IS_KEYSCAN_HIZ_CYCLE(clc) \ +( ((clc) == KEYSCAN_HIZ_CYCLE_4) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_8) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_16) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_32) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_64) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_256) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_512) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_1024)) + +/*! Parameter valid check for KEYSCAN low level output cycles. */ +#define IS_KEYSCAN_LOW_CYCLE(clc) \ +( ((clc) == KEYSCAN_LOW_CYCLE_4) || \ + ((clc) == KEYSCAN_LOW_CYCLE_8) || \ + ((clc) == KEYSCAN_LOW_CYCLE_16) || \ + ((clc) == KEYSCAN_LOW_CYCLE_32) || \ + ((clc) == KEYSCAN_LOW_CYCLE_64) || \ + ((clc) == KEYSCAN_LOW_CYCLE_128) || \ + ((clc) == KEYSCAN_LOW_CYCLE_256) || \ + ((clc) == KEYSCAN_LOW_CYCLE_512) || \ + ((clc) == KEYSCAN_LOW_CYCLE_1K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_2K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_4K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_8K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_16K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_32K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_64K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_128K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_256K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_512K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_1M) || \ + ((clc) == KEYSCAN_LOW_CYCLE_2M) || \ + ((clc) == KEYSCAN_LOW_CYCLE_4M) || \ + ((clc) == KEYSCAN_LOW_CYCLE_8M) || \ + ((clc) == KEYSCAN_LOW_CYCLE_16M)) + +/*! Parameter valid check for KEYSCAN scan clock. */ +#define IS_KEYSCAN_CLK(clk) \ +( ((clk) == KEYSCAN_CLK_HCLK) || \ + ((clk) == KEYSCAN_CLK_LRC) || \ + ((clk) == KEYSCAN_CLK_XTAL32)) + +/*! Parameter valid check for KEYSCAN keyout pins. */ +#define IS_KEYSCAN_OUT(out) \ +( ((out) == KEYSCAN_OUT_0T1) || \ + ((out) == KEYSCAN_OUT_0T2) || \ + ((out) == KEYSCAN_OUT_0T3) || \ + ((out) == KEYSCAN_OUT_0T4) || \ + ((out) == KEYSCAN_OUT_0T5) || \ + ((out) == KEYSCAN_OUT_0T6) || \ + ((out) == KEYSCAN_OUT_0T7)) + +/*! Parameter valid check for KEYSCAN keyin(EIRQ) pins. */ +#define IS_KEYSCAN_IN(in) \ +( ((in) != 0x00U) && \ + (((in) | KEYSCAN_IN_ALL) == KEYSCAN_IN_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup KEYSCAN_Global_Functions KEYSCAN Global Functions + * @{ + */ + +/** + * @brief KEYSCAN function config. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void KEYSCAN_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(CM_KEYSCAN->SER, enNewState); +} + +/** + * @brief Initialize KEYSCAN config structure. Fill each pstcKeyscanInit with default value + * @param [in] pstcKeyscanInit Pointer to a stc_keyscan_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: KEYSCAN structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t KEYSCAN_StructInit(stc_keyscan_init_t *pstcKeyscanInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcKeyscanInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcKeyscanInit->u32HizCycle = KEYSCAN_HIZ_CYCLE_4; + pstcKeyscanInit->u32LowCycle = KEYSCAN_LOW_CYCLE_4; + pstcKeyscanInit->u32KeyClock = KEYSCAN_CLK_HCLK; + pstcKeyscanInit->u32KeyOut = KEYSCAN_OUT_0T1; + pstcKeyscanInit->u32KeyIn = KEYSCAN_IN_0; + } + return i32Ret; +} + +/** + * @brief KEYSCAN initialize. + * @param [in] pstcKeyscanInit KEYSCAN config structure. + * @arg u32HizCycle Hiz state keep cycles during low level output. + * @arg u32LowCycle Low level output cycles. + * @arg u32KeyClock Scan clock. + * @arg u32KeyOut KEYOUT selection. + * @arg u32KeyIn KEYIN(EIRQ) selection. + * @retval int32_t: + * - LL_OK: KEYSCAN function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t KEYSCAN_Init(const stc_keyscan_init_t *pstcKeyscanInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcKeyscanInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_KEYSCAN_HIZ_CYCLE(pstcKeyscanInit->u32HizCycle)); + DDL_ASSERT(IS_KEYSCAN_LOW_CYCLE(pstcKeyscanInit->u32LowCycle)); + DDL_ASSERT(IS_KEYSCAN_CLK(pstcKeyscanInit->u32KeyClock)); + DDL_ASSERT(IS_KEYSCAN_OUT(pstcKeyscanInit->u32KeyOut)); + DDL_ASSERT(IS_KEYSCAN_IN(pstcKeyscanInit->u32KeyIn)); + + WRITE_REG32(CM_KEYSCAN->SCR, \ + (pstcKeyscanInit->u32HizCycle | pstcKeyscanInit->u32LowCycle | \ + pstcKeyscanInit->u32KeyClock | pstcKeyscanInit->u32KeyOut | \ + pstcKeyscanInit->u32KeyIn)); + } + return i32Ret; +} + +/** + * @brief De-initialize the KEYSCAN. + * @param None + * @retval int32_t: + * - LL_OK: De-Initialize success. + */ +int32_t KEYSCAN_DeInit(void) +{ + int32_t i32Ret = LL_OK; + WRITE_REG32(CM_KEYSCAN->SER, 0UL); + WRITE_REG32(CM_KEYSCAN->SCR, 0UL); + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_KEYSCAN_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_mpu.c b/mcu/lib/src/hc32_ll_mpu.c new file mode 100644 index 0000000..3cb9988 --- /dev/null +++ b/mcu/lib/src/hc32_ll_mpu.c @@ -0,0 +1,893 @@ +/** + ******************************************************************************* + * @file hc32_ll_mpu.c + * @brief This file provides firmware functions to manage the Memory Protection + * Unit(MPU). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-09-30 CDT Modify typo + Optimize MPU_ClearStatus function + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_mpu.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_MPU MPU + * @brief Memory Protection Unit Driver Library + * @{ + */ + +#if (LL_MPU_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup MPU_Local_Macros MPU Local Macros + * @{ + */ + +/* Number of MPU region */ +#define MPU_REGION_MAX_NUM (16UL) + +/* Number of MPU unit */ +#define MPU_UNIT_MAX_NUM (3UL) +/* MPU Register Combination Mask */ +#define MPU_UNIT_CONFIG_MASK (MPU_CR_SMPU2BRP | MPU_CR_SMPU2BWP | MPU_CR_SMPU2ACT | \ + MPU_CR_SMPU1BRP | MPU_CR_SMPU1BWP | MPU_CR_SMPU1ACT | \ + MPU_CR_FMPUBRP | MPU_CR_FMPUBWP | MPU_CR_FMPUACT) +/* DMA units have 16 regions */ +#define MPU_16REGION_UNIT (MPU_UNIT_DMA1 | MPU_UNIT_DMA2) + +/* Get the specified register address of the MPU Intrusion Control */ +#define MPU_RGD_ADDR(__NUM__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->RGD0)) + ((uint32_t)(__NUM__) << 2U)) +#define MPU_RGCR_ADDR(__NUM__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->RGCR0)) + ((uint32_t)(__NUM__) << 2U)) + +/** + * @defgroup MPU_Check_Parameters_Validity MPU Check Parameters Validity + * @{ + */ +#define IS_MPU_UNIT(x) \ +( ((x) != 0UL) && \ + (((x) | MPU_UNIT_ALL) == MPU_UNIT_ALL)) + +#define IS_MPU_REGION(x) ((x) <= MPU_REGION_NUM15) + +#define IS_MPU_UNIT_REGION(unit, region) \ +( (((unit) | MPU_16REGION_UNIT) == MPU_16REGION_UNIT) || \ + ((region) <= MPU_REGION_NUM7)) + +#define IS_MPU_BACKGROUND_WR(x) \ +( ((x) == MPU_BACKGROUND_WR_DISABLE) || \ + ((x) == MPU_BACKGROUND_WR_ENABLE)) + +#define IS_MPU_BACKGROUND_RD(x) \ +( ((x) == MPU_BACKGROUND_RD_DISABLE) || \ + ((x) == MPU_BACKGROUND_RD_ENABLE)) + +#define IS_MPU_EXP_TYPE(x) \ +( ((x) == MPU_EXP_TYPE_NONE) || \ + ((x) == MPU_EXP_TYPE_BUS_ERR) || \ + ((x) == MPU_EXP_TYPE_NMI) || \ + ((x) == MPU_EXP_TYPE_RST)) + +#define IS_MPU_REGION_WR(x) \ +( ((x) == MPU_REGION_WR_DISABLE) || \ + ((x) == MPU_REGION_WR_ENABLE)) + +#define IS_MPU_REGION_RD(x) \ +( ((x) == MPU_REGION_RD_DISABLE) || \ + ((x) == MPU_REGION_RD_ENABLE)) + +#define IS_MPU_REGION_SIZE(x) \ +( ((x) >= MPU_REGION_SIZE_32BYTE) && \ + ((x) <= MPU_REGION_SIZE_4GBYTE)) + +#define IS_MPU_REGION_BASE_ADDER(addr, size) \ +( ((addr) & ((uint32_t)(~((uint64_t)0xFFFFFFFFUL << ((size) + 1U))))) == 0UL) + +#define IS_MPU_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | MPU_FLAG_ALL) == MPU_FLAG_ALL)) + +#define IS_MPU_IP_TYPE(x) \ +( ((x) != 0UL) && \ + (((x) | MPU_IP_ALL) == MPU_IP_ALL)) + +#define IS_MPU_IP_EXP_TYPE(x) \ +( ((x) == MPU_IP_EXP_TYPE_NONE) || \ + ((x) == MPU_IP_EXP_TYPE_BUS_ERR)) + +#define IS_MPU_UNLOCK() ((CM_MPU->WP & MPU_WP_MPUWE) == MPU_WP_MPUWE) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup MPU_Global_Functions MPU Global Functions + * @{ + */ + +/** + * @brief De-Initialize MPU. + * @param None + * @retval None + */ +void MPU_DeInit(void) +{ + uint32_t i; + __IO uint32_t *RGD; + __IO uint32_t *RGE; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + + for (i = 0UL; i < MPU_REGION_MAX_NUM; i++) { + RGD = MPU_RGD_ADDR(i); + WRITE_REG32(*RGD, 0UL); + RGE = MPU_RGCR_ADDR(i); + WRITE_REG32(*RGE, 0UL); + } + WRITE_REG32(CM_MPU->ECLR, MPU_FLAG_ALL); + WRITE_REG32(CM_MPU->IPPR, 0UL); + WRITE_REG32(CM_MPU->CR, 0UL); +} + +/** + * @brief Initialize MPU. + * @param [in] pstcMpuInit Pointer to a @ref stc_mpu_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t MPU_Init(const stc_mpu_init_t *pstcMpuInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcMpuInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcDma1.u32ExceptionType)); + DDL_ASSERT(IS_MPU_BACKGROUND_WR(pstcMpuInit->stcDma1.u32BackgroundWrite)); + DDL_ASSERT(IS_MPU_BACKGROUND_RD(pstcMpuInit->stcDma1.u32BackgroundRead)); + DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcDma2.u32ExceptionType)); + DDL_ASSERT(IS_MPU_BACKGROUND_WR(pstcMpuInit->stcDma2.u32BackgroundWrite)); + DDL_ASSERT(IS_MPU_BACKGROUND_RD(pstcMpuInit->stcDma2.u32BackgroundRead)); + DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcUsbFSDma.u32ExceptionType)); + DDL_ASSERT(IS_MPU_BACKGROUND_WR(pstcMpuInit->stcUsbFSDma.u32BackgroundWrite)); + DDL_ASSERT(IS_MPU_BACKGROUND_RD(pstcMpuInit->stcUsbFSDma.u32BackgroundRead)); + MODIFY_REG32(CM_MPU->CR, MPU_UNIT_CONFIG_MASK, + (pstcMpuInit->stcDma2.u32ExceptionType | pstcMpuInit->stcDma2.u32BackgroundWrite | + pstcMpuInit->stcDma2.u32BackgroundRead) | + ((pstcMpuInit->stcDma1.u32ExceptionType | pstcMpuInit->stcDma1.u32BackgroundWrite | + pstcMpuInit->stcDma1.u32BackgroundRead) << 8U) | + ((pstcMpuInit->stcUsbFSDma.u32ExceptionType | pstcMpuInit->stcUsbFSDma.u32BackgroundWrite | + pstcMpuInit->stcUsbFSDma.u32BackgroundRead) << 16U)); + } + + return i32Ret; +} + +/** + * @brief Fills each stc_mpu_init_t member with default value. + * @param [out] pstcMpuInit Pointer to a @ref stc_mpu_init_t structure + * @retval int32_t: + * - LL_OK: stc_mpu_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t MPU_StructInit(stc_mpu_init_t *pstcMpuInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcMpuInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcMpuInit->stcDma1.u32ExceptionType = MPU_EXP_TYPE_NONE; + pstcMpuInit->stcDma1.u32BackgroundWrite = MPU_BACKGROUND_WR_DISABLE; + pstcMpuInit->stcDma1.u32BackgroundRead = MPU_BACKGROUND_RD_DISABLE; + pstcMpuInit->stcDma2.u32ExceptionType = MPU_EXP_TYPE_NONE; + pstcMpuInit->stcDma2.u32BackgroundWrite = MPU_BACKGROUND_WR_DISABLE; + pstcMpuInit->stcDma2.u32BackgroundRead = MPU_BACKGROUND_RD_DISABLE; + pstcMpuInit->stcUsbFSDma.u32ExceptionType = MPU_EXP_TYPE_NONE; + pstcMpuInit->stcUsbFSDma.u32BackgroundWrite = MPU_BACKGROUND_WR_DISABLE; + pstcMpuInit->stcUsbFSDma.u32BackgroundRead = MPU_BACKGROUND_RD_DISABLE; + } + + return i32Ret; +} + +/** + * @brief Set the exception type of the unit. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] u32Type Exception type of MPU unit. + * This parameter can be one of the following values: + * @arg MPU_EXP_TYPE_NONE: The host unit access protection regions will be ignored + * @arg MPU_EXP_TYPE_BUS_ERR: The host unit access protection regions will be ignored and a bus error will be triggered + * @arg MPU_EXP_TYPE_NMI: The host unit access protection regions will be ignored and a NMI interrupt will be triggered + * @arg MPU_EXP_TYPE_RST: The host unit access protection regions will trigger the reset + * @retval None + */ +void MPU_SetExceptionType(uint32_t u32Unit, uint32_t u32Type) +{ + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_EXP_TYPE(u32Type)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + MODIFY_REG32(CM_MPU->CR, MPU_CR_SMPU2ACT << (u32UnitPos << 3U), u32Type << (u32UnitPos << 3U)); + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the write of the unit for background space. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_BackgroundWriteCmd(uint32_t u32Unit, en_functional_state_t enNewState) +{ + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + if (DISABLE != enNewState) { + CLR_REG32_BIT(CM_MPU->CR, MPU_CR_SMPU2BWP << (u32UnitPos << 3U)); + } else { + SET_REG32_BIT(CM_MPU->CR, MPU_CR_SMPU2BWP << (u32UnitPos << 3U)); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the read of the unit for background space. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_BackgroundReadCmd(uint32_t u32Unit, en_functional_state_t enNewState) +{ + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + if (DISABLE != enNewState) { + CLR_REG32_BIT(CM_MPU->CR, MPU_CR_SMPU2BRP << (u32UnitPos << 3U)); + } else { + SET_REG32_BIT(CM_MPU->CR, MPU_CR_SMPU2BRP << (u32UnitPos << 3U)); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the access control of the unit. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_UnitCmd(uint32_t u32Unit, en_functional_state_t enNewState) +{ + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + if (DISABLE != enNewState) { + SET_REG32_BIT(CM_MPU->CR, MPU_CR_SMPU2E << (u32UnitPos << 3U)); + } else { + CLR_REG32_BIT(CM_MPU->CR, MPU_CR_SMPU2E << (u32UnitPos << 3U)); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Gets the status of MPU flag. + * @param [in] u32Flag The type of MPU flag. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t MPU_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(CM_MPU->SR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear the flag of MPU. + * @param [in] u32Flag The type of MPU flag. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Flag + * @retval None + */ +void MPU_ClearStatus(uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_MPU_FLAG(u32Flag)); + + WRITE_REG32(CM_MPU->ECLR, u32Flag); +} + +/** + * @brief Initialize the region. + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @note The effective bits of the 'u32BaseAddr' are related to the 'u32Size' of the region, + * and the low 'u32Size+1' bits are fixed at 0. + * @param [in] u32Num The number of the region. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] pstcRegionInit Pointer to a @ref stc_mpu_region_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t MPU_RegionInit(uint32_t u32Num, const stc_mpu_region_init_t *pstcRegionInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *RGD; + __IO uint32_t *RGWP; + uint32_t i; + uint32_t u32UnitNum = MPU_UNIT_MAX_NUM; + stc_mpu_region_permission_t RegionBuffer[MPU_UNIT_MAX_NUM]; + + if (NULL == pstcRegionInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_REGION_SIZE(pstcRegionInit->u32Size)); + DDL_ASSERT(IS_MPU_REGION_BASE_ADDER(pstcRegionInit->u32BaseAddr, pstcRegionInit->u32Size)); + DDL_ASSERT(IS_MPU_REGION_WR(pstcRegionInit->stcDma1.u32RegionWrite)); + DDL_ASSERT(IS_MPU_REGION_RD(pstcRegionInit->stcDma1.u32RegionRead)); + DDL_ASSERT(IS_MPU_REGION_WR(pstcRegionInit->stcDma2.u32RegionWrite)); + DDL_ASSERT(IS_MPU_REGION_RD(pstcRegionInit->stcDma2.u32RegionRead)); + DDL_ASSERT(IS_MPU_REGION_WR(pstcRegionInit->stcUsbFSDma.u32RegionWrite)); + DDL_ASSERT(IS_MPU_REGION_RD(pstcRegionInit->stcUsbFSDma.u32RegionRead)); + + RGD = MPU_RGD_ADDR(u32Num); + WRITE_REG32(*RGD, (pstcRegionInit->u32Size | pstcRegionInit->u32BaseAddr)); + /* Configure the read/write permission for the region */ + RegionBuffer[0] = pstcRegionInit->stcDma1; + RegionBuffer[1] = pstcRegionInit->stcDma2; + RegionBuffer[2] = pstcRegionInit->stcUsbFSDma; + if ((u32Num >= MPU_REGION_NUM8) && (u32Num <= MPU_REGION_NUM15)) { + u32UnitNum = 2UL; + } + for (i = 0UL; i < u32UnitNum; i++) { + /* Configure the write permission for the region */ + RGWP = MPU_RGCR_ADDR(u32Num); + if (MPU_REGION_WR_DISABLE != RegionBuffer[i].u32RegionWrite) { + CLR_REG32_BIT(*RGWP, MPU_RGCR_S2RGWP << (i << 3U)); + } else { + SET_REG32_BIT(*RGWP, MPU_RGCR_S2RGWP << (i << 3U)); + } + /* Configure the read permission for the region */ + if (MPU_REGION_WR_DISABLE != RegionBuffer[i].u32RegionRead) { + CLR_REG32_BIT(*RGWP, MPU_RGCR_S2RGRP << (i << 3U)); + } else { + SET_REG32_BIT(*RGWP, MPU_RGCR_S2RGRP << (i << 3U)); + } + } + } + + return i32Ret; +} + +/** + * @brief Fills each stc_mpu_region_init_t member with default value. + * @param [out] pstcRegionInit Pointer to a @ref stc_mpu_region_init_t structure + * @retval int32_t: + * - LL_OK: stc_mpu_region_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t MPU_RegionStructInit(stc_mpu_region_init_t *pstcRegionInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRegionInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcRegionInit->u32BaseAddr = 0UL; + pstcRegionInit->u32Size = MPU_REGION_SIZE_32BYTE; + pstcRegionInit->stcDma1.u32RegionWrite = MPU_REGION_WR_DISABLE; + pstcRegionInit->stcDma1.u32RegionRead = MPU_REGION_RD_DISABLE; + pstcRegionInit->stcDma2.u32RegionWrite = MPU_REGION_WR_DISABLE; + pstcRegionInit->stcDma2.u32RegionRead = MPU_REGION_RD_DISABLE; + pstcRegionInit->stcUsbFSDma.u32RegionWrite = MPU_REGION_WR_DISABLE; + pstcRegionInit->stcUsbFSDma.u32RegionRead = MPU_REGION_RD_DISABLE; + } + + return i32Ret; +} + +/** + * @brief Set the base address of the region. + * @note The effective bits of the 'u32Addr' are related to the 'size' of the region, + * and the low 'size+1' bits are fixed at 0. + * @param [in] u32Num The number of the region. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Addr The base address of the region. + * @retval None + */ +void MPU_SetRegionBaseAddr(uint32_t u32Num, uint32_t u32Addr) +{ + __IO uint32_t *RGD; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + + RGD = MPU_RGD_ADDR(u32Num); + /* Check parameters */ + DDL_ASSERT(IS_MPU_REGION_BASE_ADDER(u32Addr, READ_REG32_BIT(*RGD, MPU_RGD_MPURGSIZE))); + + MODIFY_REG32(*RGD, MPU_RGD_MPURGADDR, u32Addr); +} + +/** + * @brief Set the size of the region. + * @param [in] u32Num The number of the region. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Size The size of the region. + * This parameter can be one of the following values: + * @arg MPU_REGION_SIZE_32BYTE: 32 Byte + * @arg MPU_REGION_SIZE_64BYTE: 64 Byte + * @arg MPU_REGION_SIZE_128BYTE: 126 Byte + * @arg MPU_REGION_SIZE_256BYTE: 256 Byte + * @arg MPU_REGION_SIZE_512BYTE: 512 Byte + * @arg MPU_REGION_SIZE_1KBYTE: 1K Byte + * @arg MPU_REGION_SIZE_2KBYTE: 2K Byte + * @arg MPU_REGION_SIZE_4KBYTE: 4K Byte + * @arg MPU_REGION_SIZE_8KBYTE: 8K Byte + * @arg MPU_REGION_SIZE_16KBYTE: 16K Byte + * @arg MPU_REGION_SIZE_32KBYTE: 32K Byte + * @arg MPU_REGION_SIZE_64KBYTE: 64K Byte + * @arg MPU_REGION_SIZE_128KBYTE: 128K Byte + * @arg MPU_REGION_SIZE_256KBYTE: 256K Byte + * @arg MPU_REGION_SIZE_512KBYTE: 512K Byte + * @arg MPU_REGION_SIZE_1MBYTE: 1M Byte + * @arg MPU_REGION_SIZE_2MBYTE: 2M Byte + * @arg MPU_REGION_SIZE_4MBYTE: 4M Byte + * @arg MPU_REGION_SIZE_8MBYTE: 8M Byte + * @arg MPU_REGION_SIZE_16MBYTE: 16M Byte + * @arg MPU_REGION_SIZE_32MBYTE: 32M Byte + * @arg MPU_REGION_SIZE_64MBYTE: 64M Byte + * @arg MPU_REGION_SIZE_128MBYTE: 128M Byte + * @arg MPU_REGION_SIZE_256MBYTE: 256M Byte + * @arg MPU_REGION_SIZE_512MBYTE: 512M Byte + * @arg MPU_REGION_SIZE_1GBYTE: 1G Byte + * @arg MPU_REGION_SIZE_2GBYTE: 2G Byte + * @arg MPU_REGION_SIZE_4GBYTE: 4G Byte + * @retval None + */ +void MPU_SetRegionSize(uint32_t u32Num, uint32_t u32Size) +{ + __IO uint32_t *RGD; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_REGION_SIZE(u32Size)); + + RGD = MPU_RGD_ADDR(u32Num); + MODIFY_REG32(*RGD, MPU_RGD_MPURGSIZE, u32Size); +} + +/** + * @brief Enable or disable the write of the unit for the region. + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @param [in] u32Num The number of the region. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_RegionWriteCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *RGWP; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_UNIT_REGION(u32Unit, u32Num)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + RGWP = MPU_RGCR_ADDR(u32Num); + if (DISABLE != enNewState) { + CLR_REG32_BIT(*RGWP, MPU_RGCR_S2RGWP << (u32UnitPos << 3U)); + } else { + SET_REG32_BIT(*RGWP, MPU_RGCR_S2RGWP << (u32UnitPos << 3U)); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the read of the unit for the region. + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @param [in] u32Num The number of the region. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_RegionReadCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *RGRP; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_UNIT_REGION(u32Unit, u32Num)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + RGRP = MPU_RGCR_ADDR(u32Num); + if (DISABLE != enNewState) { + CLR_REG32_BIT(*RGRP, MPU_RGCR_S2RGRP << (u32UnitPos << 3U)); + } else { + SET_REG32_BIT(*RGRP, MPU_RGCR_S2RGRP << (u32UnitPos << 3U)); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the access control of the unit for the region. + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @param [in] u32Num The number of the region. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_RegionCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *RGE; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_UNIT_REGION(u32Unit, u32Num)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + RGE = MPU_RGCR_ADDR(u32Num); + if (DISABLE != enNewState) { + SET_REG32_BIT(*RGE, MPU_RGCR_S2RGE << (u32UnitPos << 3U)); + } else { + CLR_REG32_BIT(*RGE, MPU_RGCR_S2RGE << (u32UnitPos << 3U)); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Set the type of exception to access the protected IP. + * @param [in] u32Type Exception type of MPU IP. + * This parameter can be one of the following values: + * @arg MPU_IP_EXP_TYPE_NONE: Access to the protected IP will be ignored + * @arg MPU_IP_EXP_TYPE_BUS_ERR: Access to the protected IP will trigger a bus error + * @retval None + */ +void MPU_IP_SetExceptionType(uint32_t u32Type) +{ + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_IP_EXP_TYPE(u32Type)); + + WRITE_REG32(bCM_MPU->IPPR_b.BUSERRE, (u32Type >> MPU_IPPR_BUSERRE_POS)); +} + +/** + * @brief Enable or disable write for the IP. + * @param [in] u32Periph The peripheral of the chip. + * This parameter can be one or any combination of the following values: + * @arg MPU_IP_AES: AES module + * @arg MPU_IP_HASH: HASH module + * @arg MPU_IP_TRNG: TRNG module + * @arg MPU_IP_CRC: CRC module + * @arg MPU_IP_EFM: EFM module + * @arg MPU_IP_WDT: WDT module + * @arg MPU_IP_SWDT: SWDT module + * @arg MPU_IP_BKSRAM: BKSRAM module + * @arg MPU_IP_RTC: RTC module + * @arg MPU_IP_MPU: MPU module + * @arg MPU_IP_SRAMC: SRAMC module + * @arg MPU_IP_INTC: INTC module + * @arg MPU_IP_RMU_CMU_PWC: RMU, CMU and PWC modules + * @arg MPU_IP_FCG: PWR_FCG0/1/2/3 and PWR_FCG0PC registers + * @arg MPU_IP_ALL: All of the above + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_IP_WriteCmd(uint32_t u32Periph, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_IP_TYPE(u32Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + CLR_REG32_BIT(CM_MPU->IPPR, (u32Periph << 1U)); + } else { + SET_REG32_BIT(CM_MPU->IPPR, (u32Periph << 1U)); + } +} + +/** + * @brief Enable or disable read for the IP. + * @param [in] u32Periph The peripheral of the chip. + * This parameter can be one or any combination of the following values: + * @arg MPU_IP_AES: AES module + * @arg MPU_IP_HASH: HASH module + * @arg MPU_IP_TRNG: TRNG module + * @arg MPU_IP_CRC: CRC module + * @arg MPU_IP_EFM: EFM module + * @arg MPU_IP_WDT: WDT module + * @arg MPU_IP_SWDT: SWDT module + * @arg MPU_IP_BKSRAM: BKSRAM module + * @arg MPU_IP_RTC: RTC module + * @arg MPU_IP_MPU: MPU module + * @arg MPU_IP_SRAMC: SRAMC module + * @arg MPU_IP_INTC: INTC module + * @arg MPU_IP_RMU_CMU_PWC: RMU, CMU and PWC modules + * @arg MPU_IP_FCG: PWR_FCG0/1/2/3 and PWR_FCG0PC registers + * @arg MPU_IP_ALL: All of the above + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_IP_ReadCmd(uint32_t u32Periph, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_IP_TYPE(u32Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + CLR_REG32_BIT(CM_MPU->IPPR, u32Periph); + } else { + SET_REG32_BIT(CM_MPU->IPPR, u32Periph); + } +} + +/** + * @} + */ + +#endif /* LL_MPU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_ots.c b/mcu/lib/src/hc32_ll_ots.c new file mode 100644 index 0000000..668f0f2 --- /dev/null +++ b/mcu/lib/src/hc32_ll_ots.c @@ -0,0 +1,334 @@ +/** + ******************************************************************************* + * @file hc32_ll_ots.c + * @brief This file provides firmware functions to manage the OTS. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-10-31 CDT API fixed: OTS_CalculateTemp() + 2023-06-30 CDT Modify typo + Modify API OTS_DeInit() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_ots.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_OTS OTS + * @brief OTS Driver Library + * @{ + */ + +#if (LL_OTS_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup OTS_Local_Macros OTS Local Macros + * @{ + */ + +/** + * @defgroup OTS_Configuration_Bit_Mask OTS Configuration Bit Mask + * @{ + */ +#define OTS_CTL_INIT_MSK (OTS_CTL_OTSCK | OTS_CTL_TSSTP) +/** + * @} + */ + +/** + * @defgroup OTS_Factor OTS Factor + * @{ + */ +#define OTS_DR1_FACTOR (1.0F) + +#define OTS_DR2_FACTOR (1.0F) +#define OTS_ECR_XTAL_FACTOR (1.0F) +/** + * @} + */ + +/** + * @defgroup OTS_Check_Parameters_Validity OTS check parameters validity + * @{ + */ +#define IS_OTS_CLK(x) (((x) == OTS_CLK_HRC) || ((x) == OTS_CLK_XTAL)) + +#define IS_OTS_AUTO_OFF_EN(x) (((x) == OTS_AUTO_OFF_DISABLE) || ((x) == OTS_AUTO_OFF_ENABLE)) +/** + * @} + */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup OTS_Local_Variables OTS Local Variables + * @{ + */ +static float32_t m_f32SlopeK = 0.0F; +static float32_t m_f32OffsetM = 0.0F; +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup OTS_Global_Functions OTS Global Functions + * @{ + */ + +/** + * @brief Initializes OTS according to the specified parameters in the structure stc_ots_init_t. + * @param [in] pstcOTSInit Pointer to a stc_ots_init_t structure value that + * contains the configuration information for OTS. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcOTSInit == NULL. + */ +int32_t OTS_Init(const stc_ots_init_t *pstcOTSInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcOTSInit != NULL) { + DDL_ASSERT(IS_OTS_CLK(pstcOTSInit->u16ClockSrc)); + DDL_ASSERT(IS_OTS_AUTO_OFF_EN(pstcOTSInit->u16AutoOffEn)); + + /* Stop OTS sampling. */ + OTS_Stop(); + WRITE_REG16(CM_OTS->CTL, (pstcOTSInit->u16ClockSrc | pstcOTSInit->u16AutoOffEn)); + m_f32SlopeK = pstcOTSInit->f32SlopeK; + m_f32OffsetM = pstcOTSInit->f32OffsetM; + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set a default value for OTS initialization structure. + * @param [in] pstcOTSInit Pointer to a stc_ots_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcOTSInit == NULL. + */ +int32_t OTS_StructInit(stc_ots_init_t *pstcOTSInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcOTSInit != NULL) { + pstcOTSInit->u16ClockSrc = OTS_CLK_HRC; + pstcOTSInit->f32SlopeK = 0.0F; + pstcOTSInit->f32OffsetM = 0.0F; + pstcOTSInit->u16AutoOffEn = OTS_AUTO_OFF_ENABLE; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-initializes OTS peripheral. Reset the registers of OTS. + * @param None + * @retval int32_t: + * - LL_OK: De-Initialize success. + */ +int32_t OTS_DeInit(void) +{ + /* Stop OTS. */ + OTS_Stop(); + /* Set the value of all registers to the reset value. */ + WRITE_REG16(CM_OTS->CTL, 0U); + WRITE_REG16(CM_OTS->DR1, 0U); + WRITE_REG16(CM_OTS->DR2, 0U); + WRITE_REG16(CM_OTS->ECR, 0U); + return LL_OK; +} + +/** + * @brief Get temperature via normal mode. + * @param [out] pf32Temp Pointer to a float32_t type address that the temperature value to be stored. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Works timeout. + * - LL_ERR_INVD_PARAM: pf32Temp == NULL. + */ +int32_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout) +{ + __IO uint32_t u32TimeCount = u32Timeout; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pf32Temp != NULL) { + i32Ret = LL_ERR_TIMEOUT; + OTS_Start(); + while (u32TimeCount-- != 0U) { + if (READ_REG32(bCM_OTS->CTL_b.OTSST) == 0UL) { + *pf32Temp = OTS_CalculateTemp(); + i32Ret = LL_OK; + break; + } + } + OTS_Stop(); + } + + return i32Ret; +} + +/** + * @brief Enable or disable the OTS interrupt. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void OTS_IntCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(bCM_OTS->CTL_b.OTSIE, enNewState); +} + +/** + * @brief OTS scaling experiment. Get the value of the data register at the specified temperature to calculate K and M. + * @param [out] pu16Dr1: Pointer to an address to store the value of data register 1. + * @param [out] pu16Dr2: Pointer to an address to store the value of data register 2. + * @param [out] pu16Ecr: Pointer to an address to store the value of register ECR. + * @param [out] pf32A: Pointer to an address to store the parameter A. + * @param [in] u32Timeout: Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Works timeout. + * - LL_ERR_INVD_PARAM: If one the following cases matches: + * - pu16Dr1 == NULL. + * - pu16Dr2 == NULL. + * - pu16Ecr == NULL. + * - pf32A == NULL. + */ +int32_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2, + uint16_t *pu16Ecr, float32_t *pf32A, + uint32_t u32Timeout) +{ + float32_t f32Dr1; + float32_t f32Dr2; + float32_t f32Ecr; + __IO uint32_t u32TimeCount = u32Timeout; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((NULL != pu16Dr1) && (NULL != pu16Dr2) && \ + (NULL != pu16Ecr) && (NULL != pf32A)) { + i32Ret = LL_ERR_TIMEOUT; + OTS_Start(); + while (u32TimeCount-- != 0U) { + if (READ_REG32(bCM_OTS->CTL_b.OTSST) == 0UL) { + i32Ret = LL_OK; + break; + } + } + OTS_Stop(); + + if (i32Ret == LL_OK) { + *pu16Dr1 = READ_REG16(CM_OTS->DR1); + *pu16Dr2 = READ_REG16(CM_OTS->DR2); + + f32Dr1 = (float32_t)(*pu16Dr1); + f32Dr2 = (float32_t)(*pu16Dr2); + + if (READ_REG8_BIT(CM_OTS->CTL, OTS_CTL_OTSCK) == OTS_CLK_HRC) { + *pu16Ecr = READ_REG16(CM_OTS->ECR); + f32Ecr = (float32_t)(*pu16Ecr); + } else { + *pu16Ecr = 1U; + f32Ecr = OTS_ECR_XTAL_FACTOR; + } + + if ((f32Dr1 != 0.0F) && (f32Dr2 != 0.0F) && (f32Ecr != 0.0F)) { + *pf32A = ((OTS_DR1_FACTOR / f32Dr1) - (OTS_DR2_FACTOR / f32Dr2)) * f32Ecr; + } + } + } + + return i32Ret; +} + +/** + * @brief Calculate the temperature value. + * @param None + * @retval A float32_t type value of temperature. + */ +float32_t OTS_CalculateTemp(void) +{ + float32_t f32Ret = -300.0F; + uint16_t u16Dr1 = READ_REG16(CM_OTS->DR1); + uint16_t u16Dr2 = READ_REG16(CM_OTS->DR2); + uint16_t u16Ecr = READ_REG16(CM_OTS->ECR); + float32_t f32Dr1 = (float32_t)u16Dr1; + float32_t f32Dr2 = (float32_t)u16Dr2; + float32_t f32Ecr = (float32_t)u16Ecr; + + if (READ_REG8_BIT(CM_OTS->CTL, OTS_CTL_OTSCK) == OTS_CLK_XTAL) { + f32Ecr = OTS_ECR_XTAL_FACTOR; + } + + if ((f32Dr1 != 0.0F) && (f32Dr2 != 0.0F) && (f32Ecr != 0.0F)) { + f32Ret = m_f32SlopeK * ((OTS_DR1_FACTOR / f32Dr1) - (OTS_DR2_FACTOR / f32Dr2)) * f32Ecr + m_f32OffsetM; + } + + return f32Ret; +} + +/** + * @} + */ + +#endif /* LL_OTS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_pwc.c b/mcu/lib/src/hc32_ll_pwc.c new file mode 100644 index 0000000..9c28501 --- /dev/null +++ b/mcu/lib/src/hc32_ll_pwc.c @@ -0,0 +1,1682 @@ +/** + ******************************************************************************* + * @file hc32_ll_pwc.c + * @brief This file provides firmware functions to manage the Power Control(PWC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Refine API PWC_STOP_Enter() + 2022-10-31 CDT Bug fixed# PWC_PD_VdrCmd() and disable VDDR when enter PD3/4 + 2023-01-15 CDT Optimize API PWC_STOP_ClockSelect() & comment + Modify API PWC_HighSpeedToLowSpeed() & PWC_HighPerformanceToLowSpeed() base um_Rev1.42 + 2023-06-30 CDT Modify typo + Add api PWC_LVD_DeInit() + Modify API PWC_STOP_Enter() & add assert IS_PWC_STOP_TYPE() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_pwc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_PWC PWC + * @brief Power Control Driver Library + * @{ + */ + +#if (LL_PWC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup PWC_Local_Macros PWC Local Macros + * @{ + */ + +/* Get the backup register address of PWC */ + +#define PWC_SYSCLK_SRC_HRC (0U) +#define PWC_SYSCLK_SRC_PLL (5U) + +#define PWC_MD_SWITCH_TIMEOUT (30UL) +#define PWC_MD_SWITCH_TIMEOUT2 (0x1000UL) +#define PWC_MD_SWITCH_CMD (0x10U) + +#define PWC_LVD_EN_REG (CM_PWC->PVDCR0) +#define PWC_LVD_EN_BIT (PWC_PVDCR0_PVD1EN) +#define PWC_LVD_EXT_INPUT_EN_REG (CM_PWC->PVDCR0) +#define PWC_LVD_EXT_INPUT_EN_BIT (PWC_PVDCR0_EXVCCINEN) +#define PWC_LVD_CMP_OUTPUT_EN_REG (CM_PWC->PVDCR1) +#define PWC_LVD_CMP_OUTPUT_EN_BIT (PWC_PVDCR1_PVD1CMPOE) +#define PWC_LVD_FILTER_EN_REG (CM_PWC->PVDFCR) +#define PWC_LVD_FILTER_EN_BIT (PWC_PVDFCR_PVD1NFDIS) +#define PWC_LVD_STATUS_REG (CM_PWC->PVDDSR) + +#define PWC_LVD2_POS (4U) +#define PWC_LVD_BIT_OFFSET(x) ((uint8_t)((x) * PWC_LVD2_POS)) +#define PWC_LVD_EN_BIT_OFFSET(x) (x) + +#define PWC_PRAM_MASK (PWC_RAM_PD_SRAM1 | PWC_RAM_PD_SDIO0 | \ + PWC_RAM_PD_SRAM2 | PWC_RAM_PD_SDIO1 | \ + PWC_RAM_PD_SRAM3 | PWC_RAM_PD_CAN | \ + PWC_RAM_PD_SRAMH | PWC_RAM_PD_CACHE | \ + PWC_RAM_PD_USBFS) + +#define PWC_LVD_FLAG_MASK (PWC_LVD1_FLAG_MON | PWC_LVD1_FLAG_DETECT | \ + PWC_LVD2_FLAG_MON | PWC_LVD2_FLAG_DETECT) + +#define PWC_LVD_EXP_NMI_POS (8U) + +/** + * @defgroup PWC_Check_Parameters_Validity PWC Check Parameters Validity + * @{ + */ +/* Check CLK register lock status. */ +#define IS_PWC_CLK_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB0) == PWC_FPRC_FPRCB0) + +/* Check PWC register lock status. */ +#define IS_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1) +/* Check PWC LVD register lock status. */ +#define IS_PWC_LVD_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB3) == PWC_FPRC_FPRCB3) +/* Parameter validity check for EFM lock status. */ +#define IS_PWC_EFM_UNLOCKED() (CM_EFM->FAPRT == 0x00000001UL) + +/* Parameter validity check for stop type */ +#define IS_PWC_STOP_TYPE(x) \ +( ((x) == PWC_STOP_WFI) || \ + ((x) == PWC_STOP_WFE_INT) || \ + ((x) == PWC_STOP_WFE_EVT)) + +/* Parameter validity check for stop wake-up source */ +#define IS_PWC_STOP_WKUP_SRC(x) \ +( ((x) == INT_SRC_USART1_WUPI) || \ + ((x) == INT_SRC_TMR0_1_CMP_A) || \ + ((x) == INT_SRC_RTC_ALM) || \ + ((x) == INT_SRC_RTC_PRD) || \ + ((x) == INT_SRC_WKTM_PRD) || \ + ((x) == INT_SRC_CMP1) || \ + ((x) == INT_SRC_LVD1) || \ + ((x) == INT_SRC_LVD2) || \ + ((x) == INT_SRC_SWDT_REFUDF) || \ + ((x) == INT_SRC_PORT_EIRQ0) || \ + ((x) == INT_SRC_PORT_EIRQ1) || \ + ((x) == INT_SRC_PORT_EIRQ2) || \ + ((x) == INT_SRC_PORT_EIRQ3) || \ + ((x) == INT_SRC_PORT_EIRQ4) || \ + ((x) == INT_SRC_PORT_EIRQ5) || \ + ((x) == INT_SRC_PORT_EIRQ6) || \ + ((x) == INT_SRC_PORT_EIRQ7) || \ + ((x) == INT_SRC_PORT_EIRQ8) || \ + ((x) == INT_SRC_PORT_EIRQ9) || \ + ((x) == INT_SRC_PORT_EIRQ10) || \ + ((x) == INT_SRC_PORT_EIRQ11) || \ + ((x) == INT_SRC_PORT_EIRQ12) || \ + ((x) == INT_SRC_PORT_EIRQ13) || \ + ((x) == INT_SRC_PORT_EIRQ14) || \ + ((x) == INT_SRC_PORT_EIRQ15)) + +/* Parameter validity check for peripheral RAM setting of power mode control */ +#define IS_PWC_PRAM_CONTROL(x) \ +( ((x) != 0x00UL) && \ + (((x) | PWC_PRAM_MASK) == PWC_PRAM_MASK)) + +/* Parameter validity check for RAM setting of MCU operating mode */ +#define IS_PWC_RAM_MD(x) \ +( ((x) == PWC_RAM_HIGH_SPEED) || \ + ((x) == PWC_RAM_ULOW_SPEED)) + +/* Parameter validity check for LVD channel. */ +#define IS_PWC_LVD_CH(x) \ +( ((x) == PWC_LVD_CH1) || \ + ((x) == PWC_LVD_CH2)) + +/* Parameter validity check for LVD function setting. */ +#define IS_PWC_LVD_EN(x) \ +( ((x) == PWC_LVD_ON) || \ + ((x) == PWC_LVD_OFF)) + +/* Parameter validity check for LVD compare output setting. */ +#define IS_PWC_LVD_CMP_EN(x) \ +( ((x) == PWC_LVD_CMP_ON) || \ + ((x) == PWC_LVD_CMP_OFF)) + +/* Parameter validity check for PWC LVD exception type. */ +#define IS_PWC_LVD_EXP_TYPE(x) \ +( ((x) == PWC_LVD_EXP_TYPE_NONE) || \ + ((x) == PWC_LVD_EXP_TYPE_INT) || \ + ((x) == PWC_LVD_EXP_TYPE_NMI) || \ + ((x) == PWC_LVD_EXP_TYPE_RST)) + +/* Parameter validity check for LVD digital noise filter function setting. */ +#define IS_PWC_LVD_FILTER_EN(x) \ +( ((x) == PWC_LVD_FILTER_ON) || \ + ((x) == PWC_LVD_FILTER_OFF)) + +/* Parameter validity check for LVD digital noise filter clock setting. */ +#define IS_PWC_LVD_FILTER_CLK(x) \ +( ((x) == PWC_LVD_FILTER_LRC_DIV1) || \ + ((x) == PWC_LVD_FILTER_LRC_DIV2) || \ + ((x) == PWC_LVD_FILTER_LRC_DIV4) || \ + ((x) == PWC_LVD_FILTER_LRC_MUL2)) + +/* Parameter validity check for LVD detect voltage setting. */ +#define IS_PWC_LVD_THRESHOLD_VOLTAGE(x) \ +( ((x) == PWC_LVD_THRESHOLD_LVL0) || \ + ((x) == PWC_LVD_THRESHOLD_LVL1) || \ + ((x) == PWC_LVD_THRESHOLD_LVL2) || \ + ((x) == PWC_LVD_THRESHOLD_LVL3) || \ + ((x) == PWC_LVD_THRESHOLD_LVL4) || \ + ((x) == PWC_LVD_THRESHOLD_LVL5) || \ + ((x) == PWC_LVD_THRESHOLD_LVL6) || \ + ((x) == PWC_LVD_THRESHOLD_LVL7)) + +/* Parameter validity check for LVD NMI function setting. */ +#define IS_PWC_LVD_NMI(x) \ +( ((x) == PWC_LVD_INT_MASK) || \ + ((x) == PWC_LVD_INT_NONMASK)) + +/* Parameter validity check for LVD trigger setting. */ +#define IS_PWC_LVD_TRIG_EDGE(x) \ +( ((x) == PWC_LVD_TRIG_FALLING) || \ + ((x) == PWC_LVD_TRIG_RISING) || \ + ((x) == PWC_LVD_TRIG_BOTH)) + +/* Parameter validity check for LVD trigger setting. */ +#define IS_PWC_LVD_CLR_FLAG(x) \ +( ((x) == PWC_LVD1_FLAG_DETECT) || \ + ((x) == PWC_LVD2_FLAG_DETECT)) + +/* Parameter validity check for LVD flag. */ +#define IS_PWC_LVD_GET_FLAG(x) \ +( ((x) != 0x00U) && \ + (((x) | PWC_LVD_FLAG_MASK) == PWC_LVD_FLAG_MASK)) + +/* Parameter validity check for power down mode wake up event with trigger. */ +#define IS_PWC_WAKEUP_TRIG_EVT(x) \ +( ((x) != 0x00U) && \ + (((x) | PWC_PD_WKUP_TRIG_ALL) == PWC_PD_WKUP_TRIG_ALL)) + +/* Parameter validity check for power down mode wake up trigger edge. */ +#define IS_PWC_WAKEUP_TRIG(x) \ +( ((x) == PWC_PD_WKUP_TRIG_FALLING) || \ + ((x) == PWC_PD_WKUP_TRIG_RISING)) + +/* Parameter validity check for wake up flag. */ +#define IS_PWC_WKUP_FLAG(x) \ +( ((x) != 0x00U) && \ + (((x) | PWC_PD_WKUP_FLAG_ALL) == PWC_PD_WKUP_FLAG_ALL)) + +/* Parameter validity check for stop mode drive capacity. */ +#define IS_PWC_STOP_DRV(drv) \ +( ((drv) == PWC_STOP_DRV_HIGH) || \ + ((drv) == PWC_STOP_DRV_LOW)) + +/* Parameter validity check for clock setting after wake-up from stop mode. */ +#define IS_PWC_STOP_CLK(x) \ +( ((x) == PWC_STOP_CLK_KEEP) || \ + ((x) == PWC_STOP_CLK_MRC)) + +/* Parameter validity check for flash wait setting after wake-up from stop mode. */ +#define IS_PWC_STOP_FLASH_WAIT(x) \ +( ((x)== PWC_STOP_FLASH_WAIT_ON) || \ + ((x)== PWC_STOP_FLASH_WAIT_OFF)) + +#define IS_PWC_LDO_SEL(x) \ +( ((x) != 0x00U) && \ + (((x) | PWC_LDO_MASK) == PWC_LDO_MASK)) + +/* Parameter validity check for WKT Clock Source. */ +#define IS_PWC_WKT_CLK_SRC(x) \ +( ((x)== PWC_WKT_CLK_SRC_64HZ) || \ + ((x)== PWC_WKT_CLK_SRC_XTAL32) || \ + ((x)== PWC_WKT_CLK_SRC_LRC)) + +/* Parameter validity check for WKT Comparision Value. */ +#define IS_PWC_WKT_COMPARISION_VALUE(x) ((x) <= 0x0FFFU) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup PWC_Local_Variables PWC Local Variables + * @{ + */ +static uint32_t NVIC_ISER_BAK[5]; +static uint8_t m_u8HrcState = 0U; +static uint8_t m_u8MrcState = 0U; +static uint8_t m_u8WkupIntCount = 0U; +static uint8_t m_u8StopFlag = 0U; +static uint8_t m_u8SysClockSource = 1U; +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup PWC_Local_Functions PWC Local Functions + * @{ + */ + +/** + * @brief Select system clock source. + * @param u8SysSrc The system clock source. + * @retval None + * @note Must close all of the fcg register before switch system clock source. + ** This function only be called in func. PWC_ClockBackup and + ** PWC_ClockRecover. + ** If need to switch system clock please call CLK_SetSysClkSource. + */ +static void PWC_SetSysClk(uint8_t u8SysSrc) +{ + __IO uint32_t fcg0 = CM_PWC->FCG0; + __IO uint32_t fcg1 = CM_PWC->FCG1; + __IO uint32_t fcg2 = CM_PWC->FCG2; + __IO uint32_t fcg3 = CM_PWC->FCG3; + + DDL_ASSERT(IS_PWC_CLK_UNLOCKED()); + + /* Only current system clock source or target system clock source is MPLL + need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source. + We need to backup fcg0~fcg3 before close them. */ + if ((PWC_SYSCLK_SRC_PLL == (CM_CMU->CKSWR & CMU_CKSWR_CKSW)) || (PWC_SYSCLK_SRC_PLL == u8SysSrc)) { + /* Close fcg0~fcg3. */ + CM_PWC->FCG0 = 0xFFFFFAEEUL; + CM_PWC->FCG1 = 0xFFFFFFFFUL; + CM_PWC->FCG2 = 0xFFFFFFFFUL; + CM_PWC->FCG3 = 0xFFFFFFFFUL; + + DDL_DelayUS(1UL); + } + + WRITE_REG8(CM_CMU->CKSWR, u8SysSrc); + + /* update system clock frequency. */ + SystemCoreClockUpdate(); + + DDL_DelayUS(1UL); + + /* Open fcg0~fcg3. */ + CM_PWC->FCG0 = fcg0; + CM_PWC->FCG1 = fcg1; + CM_PWC->FCG2 = fcg2; + CM_PWC->FCG3 = fcg3; + + DDL_DelayUS(1UL); +} + +/** + * @brief Backup HRC/MRC state and system clock , enable HRC/MRC ,set MRC as + * system clock before enter stop mode. + * @param None + * @retval None + */ +static void PWC_ClockBackup(void) +{ + __IO uint32_t timeout = 0UL; + uint8_t u8State; + + DDL_ASSERT(IS_PWC_CLK_UNLOCKED()); + + /* HRC state backup. */ + m_u8HrcState = READ_REG8_BIT(CM_CMU->HRCCR, CMU_HRCCR_HRCSTP); + /* System clock backup*/ + m_u8SysClockSource = CM_CMU->CKSWR & CMU_CKSWR_CKSW; + + /* Enable HRC before enter stop mode. */ + if (0U != m_u8HrcState) { + CM_CMU->HRCCR = 0U; + do { + u8State = READ_REG8_BIT(CM_CMU->OSCSTBSR, CMU_OSCSTBSR_HRCSTBF); + timeout++; + } while ((timeout < 0x1000UL) && (u8State != CMU_OSCSTBSR_HRCSTBF)); + } + + /* When system clock source is HRC or MPLL, set MRC as system clock. . */ + if ((PWC_SYSCLK_SRC_HRC == m_u8SysClockSource) || (PWC_SYSCLK_SRC_PLL == m_u8SysClockSource)) { + if (0U == READ_REG8_BIT(CM_PWC->STPMCR, PWC_STPMCR_CKSMRC)) { + /* MRC state backup. */ + m_u8MrcState = READ_REG(CM_CMU->MRCCR); + if (0x80U != m_u8MrcState) { + CM_CMU->MRCCR = 0x80U; + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + } + } + PWC_SetSysClk(1U); + } +} + +/** + * @brief Recover HRC/MRC state and system clock after wake up stop mode. + * @param None + * @retval None + */ +static void PWC_ClockRecover(void) +{ + DDL_ASSERT(IS_PWC_CLK_UNLOCKED()); + + if (0U == READ_REG8_BIT(CM_PWC->STPMCR, PWC_STPMCR_CKSMRC)) { + if ((PWC_SYSCLK_SRC_HRC == m_u8SysClockSource) || (PWC_SYSCLK_SRC_PLL == m_u8SysClockSource)) { + /* Recover MRC state & system clock source. */ + PWC_SetSysClk(m_u8SysClockSource); + WRITE_REG8(CM_CMU->MRCCR, m_u8MrcState); + } + /* Recover HRC state after wake up stop mode. */ + WRITE_REG8(CM_CMU->HRCCR, m_u8HrcState); + } + /* Update system clock */ + SystemCoreClockUpdate(); +} +/** + * @} + */ + +/** + * @defgroup PWC_Global_Functions PWC Global Functions + * @{ + */ +/** + * @brief Enter power down mode. + * @param None + * @retval None + */ +__RAM_FUNC void PWC_PD_Enter(void) +{ + WRITE_REG16(CM_PWC->FPRC, PWC_UNLOCK_CODE1); + + if (PWC_PWRC0_PDMDS_1 == READ_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_PDMDS_1)) { + SET_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_VVDRSD); + } + + CLR_REG8_BIT(CM_PWC->PVDCR1, PWC_PVDCR1_PVD1IRS | PWC_PVDCR1_PVD2IRS); + SET_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_STOP); + + __disable_irq(); + SET_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_PWDN); + for (uint8_t i = 0U; i < 10U; i++) { + __NOP(); + } + __enable_irq(); + + __WFI(); +} + +/** + * @brief NVIC backup and disable before entry from stop mode + * @param None + * @retval None + */ +void PWC_STOP_NvicBackup(void) +{ + uint8_t u8Count; + __IO uint32_t *INTC_SELx; + uint32_t u32WakeupSrc; + + /* Backup NVIC set enable register for IRQ0~143*/ + for (u8Count = 0U; u8Count < sizeof(NVIC_ISER_BAK) / sizeof(uint32_t); u8Count++) { + NVIC_ISER_BAK[u8Count] = NVIC->ISER[u8Count]; + } + + /* Disable share vector */ + for (u8Count = 128U; u8Count < 144U; u8Count++) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + + for (u8Count = 0U; u8Count < 128U; u8Count++) { + INTC_SELx = (__IO uint32_t *)((uint32_t)(&CM_INTC->SEL0) + (4UL * u8Count)); + /* Disable NVIC if it is the wake up-able source from stop mode */ + u32WakeupSrc = (uint32_t)(*INTC_SELx) & INTC_SEL_INTSEL; + if (IS_PWC_STOP_WKUP_SRC((en_int_src_t)u32WakeupSrc)) { + switch (u32WakeupSrc) { + case INT_SRC_USART1_WUPI: + if (0UL == bCM_INTC->WUPEN_b.RXWUEN) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_TMR0_1_CMP_A: + if (0UL == bCM_INTC->WUPEN_b.TMR0WUEN) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_RTC_ALM: + if (0UL == bCM_INTC->WUPEN_b.RTCALMWUEN) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_RTC_PRD: + if (0UL == bCM_INTC->WUPEN_b.RTCPRDWUEN) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_WKTM_PRD: + if (0UL == bCM_INTC->WUPEN_b.WKTMWUEN) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_CMP1: + if (0UL == bCM_INTC->WUPEN_b.CMPI0WUEN) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_LVD1: + if (0UL == bCM_INTC->WUPEN_b.PVD1WUEN) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_LVD2: + if (0UL == bCM_INTC->WUPEN_b.PVD2WUEN) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_SWDT_REFUDF: + if (0UL == bCM_INTC->WUPEN_b.SWDTWUEN) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ0: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN0) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ1: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN1) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ2: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN2) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ3: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN3) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ4: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN4) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ5: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN5) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ6: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN6) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ7: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN7) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ8: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN8) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ9: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN9) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ10: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN10) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ11: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN11) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ12: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN12) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ13: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN13) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ14: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN14) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ15: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN15) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + default: + break; + } + } else if ((uint32_t)INT_SRC_MAX != u32WakeupSrc) { + /* Disable NVIC for all none-wake up source */ + NVIC_DisableIRQ((IRQn_Type)u8Count); + } else { + ; + } + } +} + +/** + * @brief NVIC recover after wake up from stop mode + * @param None + * @retval None + */ +void PWC_STOP_NvicRecover(void) +{ + uint8_t u8Count; + + for (u8Count = 0U; u8Count < sizeof(NVIC_ISER_BAK) / sizeof(uint32_t); u8Count++) { + NVIC->ISER[u8Count] = NVIC_ISER_BAK[u8Count]; + } +} + +/** + * @brief Clock backup before enter stop mode and mark it. + * @param None + * @retval None + */ +void PWC_STOP_ClockBackup(void) +{ + /* Disable all interrupt to ensure the following operation continued. */ + __disable_irq(); + + /* HRC/MRC backup and switch system clock as MRC before entry from stop mode. */ + PWC_ClockBackup(); + + /* Mark the system clock has been switch as MRC, and will enter the stop mode. */ + m_u8StopFlag = 1U; + + /* Enable all interrupt. */ + __enable_irq(); +} + +/** + * @brief Clock recover after wake up stop mode. + * @param None + * @retval None + */ +void PWC_STOP_ClockRecover(void) +{ + /* Disable all interrupt to ensure the following operation continued. */ + __disable_irq(); + + /* Mark the system clock will be switch as MRC, and has waked_up from stop mode. */ + m_u8StopFlag = 0U; + + /* Recover HRC/MRC state and system clock after wake up stop mode. */ + PWC_ClockRecover(); + + /* Enable all interrupt. */ + __enable_irq(); +} + +/** + * @brief Clock backup before exit wake up interrupt. + * @param None + * @retval None + */ +void PWC_STOP_IrqClockBackup(void) +{ + if ((1UL == m_u8StopFlag) && (1UL == m_u8WkupIntCount)) { + /* HRC/MRC backup and switch system clock as MRC. */ + PWC_ClockBackup(); + } + m_u8WkupIntCount--; +} + +/** + * @brief Clock recover after enter wake up interrupt. + * @param None + * @retval None + */ +void PWC_STOP_IrqClockRecover(void) +{ + /* The variable to display how many waked_up interrupt has been occurred + simultaneously and to decided whether backup clock before exit wake_up + interrupt. */ + m_u8WkupIntCount++; + + if (1UL == m_u8StopFlag) { + /* Recover HRC/MRC state and system clock. */ + PWC_ClockRecover(); + } +} + +/** + * @brief Enter stop mode. + * @param [in] u8StopType specifies the XTAL initial config. + * @arg PWC_STOP_WFI Enter stop mode by WFI, and wake-up by interrupt handle. + * @arg PWC_STOP_WFE_INT Enter stop mode by WFE, and wake-up by interrupt request. + * @arg PWC_STOP_WFE_EVT Enter stop mode by WFE, and wake-up by event. + * @retval None + */ +void PWC_STOP_Enter(uint8_t u8StopType) +{ + + DDL_ASSERT(IS_PWC_UNLOCKED()); + DDL_ASSERT(IS_PWC_STOP_TYPE(u8StopType)); + + /* NVIC backup and disable before entry from stop mode.*/ + PWC_STOP_NvicBackup(); + /* Clock backup and switch system clock as MRC before entry from stop mode. */ + PWC_STOP_ClockBackup(); + + SET_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_STOP); + CLR_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_PWDN); + if (PWC_STOP_WFI == u8StopType) { + __WFI(); + } else { + if (PWC_STOP_WFE_INT == u8StopType) { + SET_REG32_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); + } else { + CLR_REG32_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); + } + __SEV(); + __WFE(); + __WFE(); + } + /* Recover HRC/MRC state and system clock after wake up from stop mode. */ + PWC_STOP_ClockRecover(); + /* NVIC recover after wake up from stop mode. */ + PWC_STOP_NvicRecover(); +} + +/** + * @brief Enter sleep mode. + * @param None + * @retval None + */ +void PWC_SLEEP_Enter(void) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + + CLR_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_STOP); + CLR_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_PWDN); + + __WFI(); +} + +/** + * @brief Configure ram run mode. + * @param [in] u16Mode Specifies the mode to run. + * @arg PWC_RAM_HIGH_SPEED + * @arg PWC_RAM_ULOW_SPEED + * @retval None + */ +void PWC_RamModeConfig(uint16_t u16Mode) +{ + DDL_ASSERT(IS_PWC_RAM_MD(u16Mode)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG16(CM_PWC->RAMOPM, u16Mode); +} + +/** + * @brief Initialize LVD config structure. Fill each pstcLvdInit with default value + * @param [in] pstcLvdInit Pointer to a stc_pwc_lvd_init_t structure that contains configuration information. + * @retval int32_t: + * - LL_OK: LVD structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_LVD_StructInit(stc_pwc_lvd_init_t *pstcLvdInit) +{ + int32_t i32Ret = LL_OK; + /* Check if pointer is NULL */ + if (NULL == pstcLvdInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* RESET LVD init structure parameters values */ + pstcLvdInit->u32State = PWC_LVD_OFF; + pstcLvdInit->u32CompareOutputState = PWC_LVD_CMP_OFF; + pstcLvdInit->u32ExceptionType = PWC_LVD_EXP_TYPE_NONE; + pstcLvdInit->u32Filter = PWC_LVD_FILTER_OFF; + pstcLvdInit->u32FilterClock = PWC_LVD_FILTER_LRC_MUL2; + pstcLvdInit->u32ThresholdVoltage = PWC_LVD_THRESHOLD_LVL0; + } + return i32Ret; +} + +/** + * @brief LVD configuration. + * @param [in] u8Ch LVD channel @ref PWC_LVD_Channel. + * @param [in] pstcLvdInit Pointer to a stc_pwc_lvd_init_t structure that contains configuration information. + * @retval int32_t: + * - LL_OK: LVD initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_LVD_Init(uint8_t u8Ch, const stc_pwc_lvd_init_t *pstcLvdInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcLvdInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_EN(pstcLvdInit->u32State)); + DDL_ASSERT(IS_PWC_LVD_EXP_TYPE(pstcLvdInit->u32ExceptionType)); + DDL_ASSERT(IS_PWC_LVD_CMP_EN(pstcLvdInit->u32CompareOutputState)); + DDL_ASSERT(IS_PWC_LVD_FILTER_EN(pstcLvdInit->u32Filter)); + DDL_ASSERT(IS_PWC_LVD_FILTER_CLK(pstcLvdInit->u32FilterClock)); + DDL_ASSERT(IS_PWC_LVD_THRESHOLD_VOLTAGE(pstcLvdInit->u32ThresholdVoltage)); + + /* disable filter function in advance */ + SET_REG8_BIT(CM_PWC->PVDFCR, (PWC_PVDFCR_PVD1NFDIS << PWC_LVD_BIT_OFFSET(u8Ch))); + MODIFY_REG8(CM_PWC->PVDFCR, (PWC_PVDFCR_PVD1NFDIS | PWC_PVDFCR_PVD1NFCKS) << PWC_LVD_BIT_OFFSET(u8Ch), \ + (pstcLvdInit->u32Filter | pstcLvdInit->u32FilterClock) << PWC_LVD_BIT_OFFSET(u8Ch)); + /* Config LVD threshold voltage */ + MODIFY_REG8(CM_PWC->PVDLCR, PWC_PVDLCR_PVD1LVL << PWC_LVD_BIT_OFFSET(u8Ch), \ + pstcLvdInit->u32ThresholdVoltage << PWC_LVD_BIT_OFFSET(u8Ch)); + /* Enable LVD */ + MODIFY_REG8(CM_PWC->PVDCR0, PWC_PVDCR0_PVD1EN << u8Ch, pstcLvdInit->u32State << u8Ch); + /* Enable compare output */ + MODIFY_REG8(CM_PWC->PVDCR1, PWC_PVDCR1_PVD1CMPOE << PWC_LVD_BIT_OFFSET(u8Ch), \ + pstcLvdInit->u32CompareOutputState << PWC_LVD_BIT_OFFSET(u8Ch)); + /* config PVDIRE & PWC_PVDCR1_PVD1IRS while PVDEN & PVDCMPOE enable */ + MODIFY_REG8(CM_PWC->PVDCR1, (PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS) << PWC_LVD_BIT_OFFSET(u8Ch), \ + (pstcLvdInit->u32ExceptionType & 0xFFU) << PWC_LVD_BIT_OFFSET(u8Ch)); + MODIFY_REG8(CM_PWC->PVDICR, PWC_PVDICR_PVD1NMIS << PWC_LVD_BIT_OFFSET(u8Ch), \ + ((pstcLvdInit->u32ExceptionType >> PWC_LVD_EXP_NMI_POS) & 0xFFU) << PWC_LVD_BIT_OFFSET(u8Ch)); + + } + return i32Ret; +} + +/** + * @brief De-initialize PWC LVD. + * @param [in] u8Ch LVD channel @ref PWC_LVD_Channel. + * @retval None + */ +void PWC_LVD_DeInit(uint8_t u8Ch) +{ + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + /* Disable LVD */ + CLR_REG_BIT(CM_PWC->PVDCR0, PWC_PVDCR0_PVD1EN << u8Ch); + /* Disable Ext-Vcc */ + if (PWC_LVD_CH2 == u8Ch) { + CLR_REG8_BIT(CM_PWC->PVDCR0, PWC_PVDCR0_EXVCCINEN); + } else { + /* rsvd */ + } + /* Reset filter */ + CLR_REG8_BIT(CM_PWC->PVDFCR, (PWC_PVDFCR_PVD1NFDIS | PWC_PVDFCR_PVD1NFCKS) << PWC_LVD_BIT_OFFSET(u8Ch)); + /* Reset configure */ + CLR_REG8_BIT(CM_PWC->PVDCR1, (PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS | PWC_PVDCR1_PVD1CMPOE) << \ + PWC_LVD_BIT_OFFSET(u8Ch)); + CLR_REG8_BIT(CM_PWC->PVDICR, PWC_PVDICR_PVD1NMIS << PWC_LVD_BIT_OFFSET(u8Ch)); + /* Reset threshold voltage */ + CLR_REG8_BIT(CM_PWC->PVDLCR, PWC_PVDLCR_PVD1LVL << PWC_LVD_BIT_OFFSET(u8Ch)); +} + +/** + * @brief Enable or disable LVD. + * @param [in] u8Ch Specifies which channel to operate. @ref PWC_LVD_Channel. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_LVD_Cmd(uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + if (ENABLE == enNewState) { + SET_REG_BIT(PWC_LVD_EN_REG, PWC_LVD_EN_BIT << PWC_LVD_EN_BIT_OFFSET(u8Ch)); + } else { + CLR_REG_BIT(PWC_LVD_EN_REG, PWC_LVD_EN_BIT << PWC_LVD_EN_BIT_OFFSET(u8Ch)); + } +} + +/** + * @brief Enable or disable LVD external input. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note While enable external input, should choose PWC_LVD_CH2 to initialize and threshold voltage must set PWC_LVD_EXTVCC + */ +void PWC_LVD_ExtInputCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + if (ENABLE == enNewState) { + SET_REG_BIT(PWC_LVD_EXT_INPUT_EN_REG, PWC_LVD_EXT_INPUT_EN_BIT); + } else { + CLR_REG_BIT(PWC_LVD_EXT_INPUT_EN_REG, PWC_LVD_EXT_INPUT_EN_BIT); + } +} + +/** + * @brief Enable or disable LVD compare output. + * @param [in] u8Ch Specifies which channel to operate. @ref PWC_LVD_Channel. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_LVD_CompareOutputCmd(uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + if (ENABLE == enNewState) { + SET_REG_BIT(PWC_LVD_CMP_OUTPUT_EN_REG, PWC_LVD_CMP_OUTPUT_EN_BIT << PWC_LVD_BIT_OFFSET(u8Ch)); + } else { + CLR_REG_BIT(PWC_LVD_CMP_OUTPUT_EN_REG, PWC_LVD_CMP_OUTPUT_EN_BIT << PWC_LVD_BIT_OFFSET(u8Ch)); + } +} + +/** + * @brief Enable or disable LVD digital filter. + * @param [in] u8Ch Specifies which channel to operate. @ref PWC_LVD_Channel. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_LVD_DigitalFilterCmd(uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG_BIT(PWC_LVD_FILTER_EN_REG, PWC_LVD_FILTER_EN_BIT << PWC_LVD_BIT_OFFSET(u8Ch)); + } else { + SET_REG_BIT(PWC_LVD_FILTER_EN_REG, PWC_LVD_FILTER_EN_BIT << PWC_LVD_BIT_OFFSET(u8Ch)); + } +} + +/** + * @brief Enable or disable LVD compare output. + * @param [in] u8Ch Specifies which channel to operate. @ref PWC_LVD_Channel. + * @param [in] u32Clock Specifies filter clock. @ref PWC_LVD_DFS_Clk_Sel + * @retval None + */ +void PWC_LVD_SetFilterClock(uint8_t u8Ch, uint32_t u32Clock) +{ + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_FILTER_CLK(u32Clock)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + MODIFY_REG8(CM_PWC->PVDFCR, PWC_PVDFCR_PVD1NFCKS << PWC_LVD_BIT_OFFSET(u8Ch), \ + u32Clock << PWC_LVD_BIT_OFFSET(u8Ch)); +} + +/** + * @brief Set LVD threshold voltage. + * @param [in] u8Ch Specifies which channel to operate. @ref PWC_LVD_Channel. + * @param [in] u32Voltage Specifies threshold voltage. @ref PWC_LVD_Detection_Voltage_Sel + * @retval None + * @note While PWC_LVD_CH2, PWC_LVD_EXTVCC only valid while EXTINPUT enable. + */ +void PWC_LVD_SetThresholdVoltage(uint8_t u8Ch, uint32_t u32Voltage) +{ + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_THRESHOLD_VOLTAGE(u32Voltage)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + MODIFY_REG8(CM_PWC->PVDLCR, (PWC_PVDLCR_PVD1LVL << PWC_LVD_BIT_OFFSET(u8Ch)), \ + u32Voltage << PWC_LVD_BIT_OFFSET(u8Ch)); +} + +/** + * @brief Get LVD flag. + * @param [in] u8Flag LVD flag to be get @ref PWC_LVD_Flag + * @retval An @ref en_flag_status_t enumeration value + * @note PVDxDETFLG is available when PVDCR0.PVDxEN and PVDCR1.PVDxCMPOE are set to '1' + */ +en_flag_status_t PWC_LVD_GetStatus(uint8_t u8Flag) +{ + DDL_ASSERT(IS_PWC_LVD_GET_FLAG(u8Flag)); + return ((0x00U != READ_REG8_BIT(PWC_LVD_STATUS_REG, u8Flag)) ? SET : RESET); +} + +/** + * @brief Clear LVD flag. + * @param [in] u8Flag LVD flag to be get @ref PWC_LVD_Flag + * @arg PWC_LVD1_FLAG_DETECT + * @arg PWC_LVD2_FLAG_DETECT + * @retval None + * @note PWC_LVD2_FLAG_DETECT only valid + */ +void PWC_LVD_ClearStatus(uint8_t u8Flag) +{ + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + DDL_ASSERT(IS_PWC_LVD_CLR_FLAG(u8Flag)); + + u8Flag = u8Flag >> PWC_PVDDSR_PVD1DETFLG_POS; + CLR_REG8_BIT(PWC_LVD_STATUS_REG, u8Flag); +} + +/** + * @brief LDO(HRC & PLL) command. + * @param [in] u16Ldo Specifies the ldo to command. + * @arg PWC_LDO_PLL + * @arg PWC_LDO_HRC + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_LDO_Cmd(uint16_t u16Ldo, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_LDO_SEL(u16Ldo)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG8_BIT(CM_PWC->PWRC1, u16Ldo); + } else { + SET_REG8_BIT(CM_PWC->PWRC1, u16Ldo); + } +} + +/** + * @brief Switch high speed to ultra low speed, set the drive ability. + * @param None + * @retval int32_t: + * - LL_OK: Mode switch successful. + * - LL_ERR: Mode switch failure, check whether EFM was unlocked please. + * @note Before calling this API, please switch system clock to the required + * low speed frequency in advance, and make sure NO any flash program + * or erase operation background. + */ +int32_t PWC_HighSpeedToLowSpeed(void) +{ + uint32_t u32To = PWC_MD_SWITCH_TIMEOUT2; + + DDL_ASSERT(IS_PWC_UNLOCKED()); + DDL_ASSERT(IS_PWC_EFM_UNLOCKED()); + + WRITE_REG32(bCM_EFM->FRMC_b.LVM, ENABLE); + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_ULOW_SPEED); + + while (PWC_RAM_ULOW_SPEED != READ_REG16(CM_PWC->RAMOPM)) { + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_ULOW_SPEED); + if (0UL == u32To--) { + return LL_ERR; + } + } + + u32To = PWC_MD_SWITCH_TIMEOUT2; + while (0UL == READ_REG32(bCM_EFM->FRMC_b.LVM)) { + WRITE_REG32(bCM_EFM->FRMC_b.LVM, ENABLE); + if (0UL == u32To--) { + return LL_ERR; + } + } + + MODIFY_REG8(CM_PWC->PWRC2, PWC_PWRC2_DDAS | PWC_PWRC2_DVS, PWC_PWRC2_DDAS_3 | PWC_PWRC2_DVS_1); + WRITE_REG8(CM_PWC->MDSWCR, PWC_MD_SWITCH_CMD); + + /* Delay 30uS*/ + DDL_DelayUS(PWC_MD_SWITCH_TIMEOUT); + + return LL_OK; +} + +/** + * @brief Switch ultra low speed to high speed, set the drive ability. + * @param None + * @retval int32_t: + * - LL_OK: Mode switch successful. + * - LL_ERR: Mode switch failure, check whether EFM was unlocked please. + * @note After calling this API, the system clock is able to switch high frequency. + */ +/** + * @brief Switch ultra low speed to high speed, set the drive ability. + * @param None + * @retval int32_t: + * - LL_OK: Mode switch successful. + * - LL_ERR: Mode switch failure, check whether EFM was unlocked please. + * @note After calling this API, the system clock is able to switch high frequency. + */ +int32_t PWC_LowSpeedToHighSpeed(void) +{ + uint32_t u32To = PWC_MD_SWITCH_TIMEOUT2; + + DDL_ASSERT(IS_PWC_UNLOCKED()); + DDL_ASSERT(IS_PWC_EFM_UNLOCKED()); + SET_REG8_BIT(CM_PWC->PWRC2, PWC_PWRC2_DDAS | PWC_PWRC2_DVS); + WRITE_REG8(CM_PWC->MDSWCR, PWC_MD_SWITCH_CMD); + + /* Delay 30uS*/ + DDL_DelayUS(PWC_MD_SWITCH_TIMEOUT); + + WRITE_REG32(bCM_EFM->FRMC_b.LVM, DISABLE); + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_HIGH_SPEED); + + while (PWC_RAM_HIGH_SPEED != READ_REG16(CM_PWC->RAMOPM)) { + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_HIGH_SPEED); + if (0UL == u32To--) { + return LL_ERR; + } + } + + u32To = PWC_MD_SWITCH_TIMEOUT2; + while (0UL != READ_REG32(bCM_EFM->FRMC_b.LVM)) { + WRITE_REG32(bCM_EFM->FRMC_b.LVM, DISABLE); + if (0UL == u32To--) { + return LL_ERR; + } + } + + return LL_OK; +} + +/** + * @brief Switch high speed to high performance, set the drive ability. + * @param None + * @retval int32_t: + * - LL_OK: Mode switch successful. + * - LL_ERR: Mode switch failure, check whether EFM was unlocked please. + * @note After calling this API, the system clock is able to switch high frequency.. + */ +int32_t PWC_HighSpeedToHighPerformance(void) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG8(CM_PWC->PWRC2, PWC_PWRC2_DDAS | PWC_PWRC2_DVS, PWC_PWRC2_DDAS); + WRITE_REG8(CM_PWC->MDSWCR, PWC_MD_SWITCH_CMD); + + /* Delay 30uS*/ + DDL_DelayUS(PWC_MD_SWITCH_TIMEOUT); + + return LL_OK; +} + +/** + * @brief Switch high performance to high speed, set the drive ability. + * @param None + * @retval int32_t: + * - LL_OK: Mode switch successful. + * - LL_ERR: Mode switch failure, check whether EFM was unlocked please. + * @note Before calling this API, please switch system clock to the required + * low speed frequency in advance, and make sure NO any flash program + * or erase operation background. + */ +int32_t PWC_HighPerformanceToHighSpeed(void) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG8(CM_PWC->PWRC2, PWC_PWRC2_DDAS | PWC_PWRC2_DVS, PWC_PWRC2_DDAS | PWC_PWRC2_DVS); + WRITE_REG8(CM_PWC->MDSWCR, PWC_MD_SWITCH_CMD); + + /* Delay 30uS*/ + DDL_DelayUS(PWC_MD_SWITCH_TIMEOUT); + + return LL_OK; +} + +/** + * @brief Switch low speed to high performance, set the drive ability. + * @param None + * @retval int32_t: + * - LL_OK: Mode switch successful. + * - LL_ERR: Mode switch failure, check whether EFM was unlocked please. + * @note After calling this API, the system clock is able to switch high frequency.. + */ +int32_t PWC_LowSpeedToHighPerformance(void) +{ + uint32_t u32To; + + DDL_ASSERT(IS_PWC_UNLOCKED()); + DDL_ASSERT(IS_PWC_EFM_UNLOCKED()); + + MODIFY_REG8(CM_PWC->PWRC2, PWC_PWRC2_DDAS | PWC_PWRC2_DVS, PWC_PWRC2_DDAS); + WRITE_REG8(CM_PWC->MDSWCR, PWC_MD_SWITCH_CMD); + + /* Delay 30uS*/ + DDL_DelayUS(PWC_MD_SWITCH_TIMEOUT); + + WRITE_REG32(bCM_EFM->FRMC_b.LVM, DISABLE); + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_HIGH_SPEED); + + u32To = PWC_MD_SWITCH_TIMEOUT2; + while (PWC_RAM_HIGH_SPEED != READ_REG16(CM_PWC->RAMOPM)) { + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_HIGH_SPEED); + if (0UL == u32To--) { + return LL_ERR; + } + } + + u32To = PWC_MD_SWITCH_TIMEOUT2; + while (0UL != READ_REG32(bCM_EFM->FRMC_b.LVM)) { + WRITE_REG32(bCM_EFM->FRMC_b.LVM, DISABLE); + if (0UL == u32To--) { + return LL_ERR; + } + } + + return LL_OK; +} + +/** + * @brief Switch high performance to low speed, set the drive ability. + * @param None + * @retval int32_t: + * - LL_OK: Mode switch successful. + * - LL_ERR: Mode switch failure, check whether EFM was unlocked please. + * @note Before calling this API, please switch system clock to the required + * low speed frequency in advance, and make sure NO any flash program + * or erase operation background.. + */ +int32_t PWC_HighPerformanceToLowSpeed(void) +{ + uint32_t u32To; + + DDL_ASSERT(IS_PWC_UNLOCKED()); + DDL_ASSERT(IS_PWC_EFM_UNLOCKED()); + + WRITE_REG32(bCM_EFM->FRMC_b.LVM, ENABLE); + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_ULOW_SPEED); + + u32To = PWC_MD_SWITCH_TIMEOUT2; + while (PWC_RAM_ULOW_SPEED != READ_REG16(CM_PWC->RAMOPM)) { + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_ULOW_SPEED); + if (0UL == u32To--) { + return LL_ERR; + } + } + + u32To = PWC_MD_SWITCH_TIMEOUT2; + while (0UL == READ_REG32(bCM_EFM->FRMC_b.LVM)) { + WRITE_REG32(bCM_EFM->FRMC_b.LVM, ENABLE); + if (0UL == u32To--) { + return LL_ERR; + } + } + + MODIFY_REG8(CM_PWC->PWRC2, PWC_PWRC2_DDAS | PWC_PWRC2_DVS, PWC_PWRC2_DDAS_3 | PWC_PWRC2_DVS_1); + WRITE_REG8(CM_PWC->MDSWCR, PWC_MD_SWITCH_CMD); + + /* Delay 30uS*/ + DDL_DelayUS(PWC_MD_SWITCH_TIMEOUT); + + return LL_OK; +} + +/** + * @brief VDR area power down command. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Power down mode + * @arg DISABLE: Run mode + * @retval None + */ +void PWC_PD_VdrCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_VVDRSD); + } else { + SET_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_VVDRSD); + } +} + +/** + * @brief Ram area power down command. + * @param [in] u32PeriphRam Specifies which ram to operate. @ref PWC_PD_Periph_Ram + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Power down mode + * @arg DISABLE: Run mode + * @retval None + */ +void PWC_PD_PeriphRamCmd(uint32_t u32PeriphRam, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_PRAM_CONTROL(u32PeriphRam)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + CM_PWC->RAMPC0 |= u32PeriphRam; + } else { + CM_PWC->RAMPC0 &= ~u32PeriphRam; + } +} + +/** + * @brief Initialize Power down mode config structure. Fill each pstcPDModeConfig with default value + * @param [in] pstcPDModeConfig Pointer to a stc_pwc_pd_mode_config_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: Power down mode structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_PD_StructInit(stc_pwc_pd_mode_config_t *pstcPDModeConfig) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcPDModeConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcPDModeConfig->u8IOState = PWC_PD_IO_KEEP1; + pstcPDModeConfig->u8Mode = PWC_PD_MD1; + pstcPDModeConfig->u8VcapCtrl = PWC_PD_VCAP_0P1UF; + } + return i32Ret; +} + +/** + * @brief Power down mode config structure. + * @param [in] pstcPDModeConfig Pointer to a stc_pwc_pd_mode_config_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: Power down mode config successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_PD_Config(const stc_pwc_pd_mode_config_t *pstcPDModeConfig) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcPDModeConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG8(CM_PWC->PWRC0, (PWC_PWRC0_IORTN | PWC_PWRC0_PDMDS), \ + (pstcPDModeConfig->u8IOState | pstcPDModeConfig->u8Mode)); + MODIFY_REG8(CM_PWC->PWRC3, PWC_PWRC3_PDTS, pstcPDModeConfig->u8VcapCtrl << PWC_PWRC3_PDTS_POS); + } + return i32Ret; +} + +/** + * @brief Power down mode wake up event config. + * @param [in] u32Event Wakeup Event. @ref PWC_WKUP_Event_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_PD_WakeupCmd(uint32_t u32Event, en_functional_state_t enNewState) +{ + uint8_t u8Event0 = (uint8_t)u32Event; + uint8_t u8Event1 = (uint8_t)(u32Event >> PWC_PD_WKUP1_POS); + uint8_t u8Event2 = (uint8_t)(u32Event >> PWC_PD_WKUP2_POS); + if (ENABLE == enNewState) { + SET_REG8_BIT(CM_PWC->PDWKE0, u8Event0); + SET_REG8_BIT(CM_PWC->PDWKE1, u8Event1); + SET_REG8_BIT(CM_PWC->PDWKE2, u8Event2); + } else { + CLR_REG8_BIT(CM_PWC->PDWKE0, u8Event0); + CLR_REG8_BIT(CM_PWC->PDWKE1, u8Event1); + CLR_REG8_BIT(CM_PWC->PDWKE2, u8Event2); + } +} + +/** + * @brief Power down mode wake up event trigger config. + * @param [in] u8Event PVD and wake up pin. @ref PWC_WKUP_Trigger_Event_Sel + * @param [in] u8TrigEdge The trigger edge. + * @arg PWC_PD_WKUP_TRIG_FALLING + * @arg PWC_PD_WKUP_TRIG_RISING + * @retval None + */ +void PWC_PD_SetWakeupTriggerEdge(uint8_t u8Event, uint8_t u8TrigEdge) +{ + DDL_ASSERT(IS_PWC_WAKEUP_TRIG_EVT(u8Event)); + DDL_ASSERT(IS_PWC_WAKEUP_TRIG(u8TrigEdge)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (PWC_PD_WKUP_TRIG_RISING == u8TrigEdge) { + SET_REG8_BIT(CM_PWC->PDWKES, u8Event); + } else { + CLR_REG8_BIT(CM_PWC->PDWKES, u8Event); + } +} + +/** + * @brief Get wake up event flag. + * @param [in] u16Flag Wake up event. @ref PWC_WKUP_Event_Flag_Sel + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t PWC_PD_GetWakeupStatus(uint16_t u16Flag) +{ + uint8_t u8Flag0; + uint8_t u8Flag1; + + DDL_ASSERT(IS_PWC_WKUP_FLAG(u16Flag)); + + u8Flag0 = READ_REG8_BIT(CM_PWC->PDWKF0, u16Flag); + u8Flag1 = READ_REG8_BIT(CM_PWC->PDWKF1, (u16Flag >> PWC_PD_WKUP_FLAG1_POS)); + + return (((0U != u8Flag0) || (0U != u8Flag1)) ? SET : RESET); +} + +/** + * @brief Clear wake up event flag. + * @param [in] u16Flag Wake up event. @ref PWC_WKUP_Event_Flag_Sel + * @retval None + */ +void PWC_PD_ClearWakeupStatus(uint16_t u16Flag) +{ + uint8_t u8Flag0; + uint8_t u8Flag1; + + DDL_ASSERT(IS_PWC_WKUP_FLAG(u16Flag)); + + u8Flag0 = (uint8_t)u16Flag; + u8Flag1 = (uint8_t)(u16Flag >> PWC_PD_WKUP_FLAG1_POS); + + CLR_REG8_BIT(CM_PWC->PDWKF0, u8Flag0); + CLR_REG8_BIT(CM_PWC->PDWKF1, u8Flag1); +} + +/** + * @brief Stop mode config. + * @param [in] pstcStopConfig Chip config before entry stop mode. + * @arg u8StopDrv, MCU from which speed mode entry stop mode. + * @arg u16Clock, System clock setting after wake-up from stop mode. + * @arg u16FlashWait, Whether wait flash stable after wake-up from stop mode. + * @arg u16ExBusHold, ExBus status in stop mode. + * @retval int32_t: + * - LL_OK: Stop mode config successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_STOP_Config(const stc_pwc_stop_mode_config_t *pstcStopConfig) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcStopConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + + DDL_ASSERT(IS_PWC_UNLOCKED()); + + DDL_ASSERT(IS_PWC_STOP_CLK(pstcStopConfig->u16Clock)); + DDL_ASSERT(IS_PWC_STOP_DRV(pstcStopConfig->u8StopDrv)); + DDL_ASSERT(IS_PWC_STOP_FLASH_WAIT(pstcStopConfig->u16FlashWait)); + MODIFY_REG8(CM_PWC->PWRC1, PWC_PWRC1_STPDAS, pstcStopConfig->u8StopDrv); + MODIFY_REG16(CM_PWC->STPMCR, (PWC_STPMCR_CKSMRC | PWC_STPMCR_FLNWT), \ + (pstcStopConfig->u16Clock | pstcStopConfig->u16FlashWait)); + + } + return i32Ret; +} + +/** + * @brief Initialize stop mode config structure. Fill each pstcStopConfig with default value + * @param [in] pstcStopConfig Pointer to a stc_pwc_stop_mode_config_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: Stop down mode structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_STOP_StructInit(stc_pwc_stop_mode_config_t *pstcStopConfig) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcStopConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcStopConfig->u16Clock = PWC_STOP_CLK_KEEP; + pstcStopConfig->u8StopDrv = PWC_STOP_DRV_HIGH; + pstcStopConfig->u16FlashWait = PWC_STOP_FLASH_WAIT_ON; + } + return i32Ret; +} + +/** + * @brief Stop mode wake up clock config. + * @param [in] u8Clock System clock setting after wake-up from stop mode. @ref PWC_STOP_CLK_Sel + * @retval None + */ +void PWC_STOP_ClockSelect(uint8_t u8Clock) +{ + DDL_ASSERT(IS_PWC_STOP_CLK(u8Clock)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG16(CM_PWC->STPMCR, PWC_STPMCR_CKSMRC, (uint16_t)u8Clock); + +} + +/** + * @brief Stop mode wake up flash wait config. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_STOP_FlashWaitCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_FLNWT); + } else { + SET_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_FLNWT); + } +} + +/** + * @brief Stop mode driver capacity config. + * @param [in] u8StopDrv Drive capacity while enter stop mode. + * @arg PWC_STOP_DRV_HIGH + * @arg PWC_STOP_DRV_LOW + * @retval None + */ +void PWC_STOP_SetDrv(uint8_t u8StopDrv) +{ + DDL_ASSERT(IS_PWC_STOP_DRV(u8StopDrv)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG8(CM_PWC->PWRC1, PWC_PWRC1_STPDAS, u8StopDrv); +} + +/** + * @brief PWC power monitor command. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note This monitor power is used for ADC and output to REGC pin. + */ +void PWC_PowerMonitorCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + if (ENABLE == enNewState) { + SET_REG8_BIT(CM_PWC->PWCMR, PWC_PWCMR_ADBUFE); + } else { + CLR_REG8_BIT(CM_PWC->PWCMR, PWC_PWCMR_ADBUFE); + } + +} + +/** + * @brief WKT Timer Initialize. + * @param [in] u16ClkSrc Clock source. + * This parameter can be one of the values @ref PWC_WKT_Clock_Source. + * @param [in] u16CmpVal Comparison value of the Counter. + * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 0xFFF. + * @retval None + */ +void PWC_WKT_Config(uint16_t u16ClkSrc, uint16_t u16CmpVal) +{ + /* Check parameters */ + DDL_ASSERT(IS_PWC_WKT_CLK_SRC(u16ClkSrc)); + DDL_ASSERT(IS_PWC_WKT_COMPARISION_VALUE(u16CmpVal)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG16(CM_PWC->WKTCR, (uint16_t)(u16ClkSrc | (u16CmpVal & PWC_WKTCR_WKTMCMP))); +} + +/** + * @brief SET WKT Timer compare value. + * @param [in] u16CmpVal Comparison value of the Counter. + * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 0xFFF. + * @retval None + */ +void PWC_WKT_SetCompareValue(uint16_t u16CmpVal) +{ + /* Check parameters */ + DDL_ASSERT(IS_PWC_WKT_COMPARISION_VALUE(u16CmpVal)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + MODIFY_REG16(CM_PWC->WKTCR, PWC_WKTCR_WKTMCMP, u16CmpVal); +} + +/** + * @brief Get WKT Timer compare value. + * @param None + * @retval uint16_t WKT Compare value + */ +uint16_t PWC_WKT_GetCompareValue(void) +{ + uint16_t u16CmpVal; + + u16CmpVal = READ_REG16_BIT(CM_PWC->WKTCR, PWC_WKTCR_WKTMCMP); + + return u16CmpVal; +} + +/** + * @brief ENABLE or DISABLE WKT Timer. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_WKT_Cmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + MODIFY_REG16(CM_PWC->WKTCR, PWC_WKTCR_WKTCE, PWC_WKT_ON); + } else { + MODIFY_REG16(CM_PWC->WKTCR, PWC_WKTCR_WKTCE, PWC_WKT_OFF); + } + +} + +/** + * @brief Get WKT Timer count match flag. + * @param None + * @retval An @ref en_flag_status_t enumeration type value. enumeration value: + */ +en_flag_status_t PWC_WKT_GetStatus(void) +{ + en_flag_status_t enFlagState; + + enFlagState = (0U != READ_REG16_BIT(CM_PWC->WKTCR, PWC_WKTCR_WKOVF)) ? SET : RESET; + + return enFlagState; +} + +/** + * @brief Clear WKT Timer count match flag. + * @param None + * @retval None + */ +void PWC_WKT_ClearStatus(void) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + CLR_REG16_BIT(CM_PWC->WKTCR, PWC_WKTCR_WKOVF); +} + +/** + * @brief ENABLE or DISABLE XTAL32 power. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Power on + * @arg DISABLE: Power off + * @retval None + */ +void PWC_XTAL32_PowerCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG8_BIT(CM_PWC->XTAL32CS, PWC_XTAL32CS_CSDIS); + } else { + SET_REG_BIT(CM_PWC->XTAL32CS, PWC_XTAL32CS_CSDIS); + } +} + +/** + * @brief Ret_Sram area power command. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Power on + * @arg DISABLE: Power off + * @retval None + */ +void PWC_RetSram_PowerCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_RETRAMSD); + } else { + SET_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_RETRAMSD); + } +} + +/** + * @} + */ + +#endif /* LL_PWC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_qspi.c b/mcu/lib/src/hc32_ll_qspi.c new file mode 100644 index 0000000..11bc37e --- /dev/null +++ b/mcu/lib/src/hc32_ll_qspi.c @@ -0,0 +1,481 @@ +/** + ******************************************************************************* + * @file hc32_ll_qspi.c + * @brief This file provides firmware functions to manage the QSPI. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-01-15 CDT Modify the conditions for entering direct communication mode + 2023-09-30 CDT Optimize QSPI_ClearStatus function + Modify return value type of QSPI_DeInit function + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_qspi.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_QSPI QSPI + * @brief QSPI Driver Library + * @{ + */ + +#if (LL_QSPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup QSPI_Local_Macros QSPI Local Macros + * @{ + */ + +/* QSPI registers Mask */ +#define QSPI_CR_CLR_MASK (QSPI_CR_DIV | QSPI_CR_SPIMD3 | QSPI_CR_PFSAE | \ + QSPI_CR_PFE | QSPI_CR_MDSEL) +#define QSPI_FCR_CLR_MASK (QSPI_FCR_DUTY | QSPI_FCR_DMCYCN | QSPI_FCR_SSNLD | \ + QSPI_FCR_SSNHD | QSPI_FCR_FOUR_BIC | QSPI_FCR_AWSL) +#define QSPI_CUSTOM_MD_CLR_MASK (QSPI_CR_IPRSL | QSPI_CR_APRSL | QSPI_CR_DPRSL) + +/** + * @defgroup QSPI_Check_Parameters_Validity QSPI check parameters validity + * @{ + */ + +#define IS_QSPI_CLK_DIV(x) \ +( ((x) != 0U) && \ + (((x) | QSPI_CLK_DIV64) == QSPI_CLK_DIV64)) + +#define IS_QSPI_SPI_MD(x) \ +( ((x) == QSPI_SPI_MD0) || \ + ((x) == QSPI_SPI_MD3)) + +#define IS_QSPI_PREFETCH_MD(x) \ +( ((x) == QSPI_PREFETCH_MD_INVD) || \ + ((x) == QSPI_PREFETCH_MD_EDGE_STOP) || \ + ((x) == QSPI_PREFETCH_MD_IMMED_STOP)) + +#define IS_QSPI_READ_MD(x) \ +( ((x) == QSPI_RD_MD_STD_RD) || \ + ((x) == QSPI_RD_MD_FAST_RD) || \ + ((x) == QSPI_RD_MD_DUAL_OUTPUT_FAST_RD) || \ + ((x) == QSPI_RD_MD_DUAL_IO_FAST_RD) || \ + ((x) == QSPI_RD_MD_QUAD_OUTPUT_FAST_RD) || \ + ((x) == QSPI_RD_MD_QUAD_IO_FAST_RD) || \ + ((x) == QSPI_RD_MD_CUSTOM_STANDARD_RD) || \ + ((x) == QSPI_RD_MD_CUSTOM_FAST_RD)) + +#define IS_QSPI_DUMMY_CYCLE(x) (((x) | QSPI_DUMMY_CYCLE18) == QSPI_DUMMY_CYCLE18) + +#define IS_QSPI_ADDR_WIDTH(x) \ +( ((x) == QSPI_ADDR_WIDTH_8BIT) || \ + ((x) == QSPI_ADDR_WIDTH_16BIT) || \ + ((x) == QSPI_ADDR_WIDTH_24BIT) || \ + ((x) == QSPI_ADDR_WIDTH_32BIT_INSTR_24BIT) || \ + ((x) == QSPI_ADDR_WIDTH_32BIT_INSTR_32BIT)) + +#define IS_QSPI_QSSN_SETUP_TIME(x) \ +( ((x) == QSPI_QSSN_SETUP_ADVANCE_QSCK0P5) || \ + ((x) == QSPI_QSSN_SETUP_ADVANCE_QSCK1P5)) + +#define IS_QSPI_QSSN_RELEASE_TIME(x) \ +( ((x) == QSPI_QSSN_RELEASE_DELAY_QSCK0P5) || \ + ((x) == QSPI_QSSN_RELEASE_DELAY_QSCK1P5) || \ + ((x) == QSPI_QSSN_RELEASE_DELAY_QSCK32) || \ + ((x) == QSPI_QSSN_RELEASE_DELAY_QSCK128) || \ + ((x) == QSPI_QSSN_RELEASE_DELAY_INFINITE)) + +#define IS_QSPI_QSSN_INTERVAL_TIME(x) ((x) <= QSPI_QSSN_INTERVAL_QSCK16) + +#define IS_QSPI_INSTR_PROTOCOL(x) \ +( ((x) == QSPI_INSTR_PROTOCOL_1LINE) || \ + ((x) == QSPI_INSTR_PROTOCOL_2LINE) || \ + ((x) == QSPI_INSTR_PROTOCOL_4LINE)) + +#define IS_QSPI_ADDR_PROTOCOL(x) \ +( ((x) == QSPI_ADDR_PROTOCOL_1LINE) || \ + ((x) == QSPI_ADDR_PROTOCOL_2LINE) || \ + ((x) == QSPI_ADDR_PROTOCOL_4LINE)) + +#define IS_QSPI_DATA_PROTOCOL(x) \ +( ((x) == QSPI_DATA_PROTOCOL_1LINE) || \ + ((x) == QSPI_DATA_PROTOCOL_2LINE) || \ + ((x) == QSPI_DATA_PROTOCOL_4LINE)) + +#define IS_QSPI_WP_PIN_LVL(x) \ +( ((x) == QSPI_WP_PIN_LOW) || \ + ((x) == QSPI_WP_PIN_HIGH)) + +#define IS_QSPI_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | QSPI_FLAG_ALL) == QSPI_FLAG_ALL)) + +#define IS_QSPI_CLR_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | QSPI_FLAG_CLR_ALL) == QSPI_FLAG_CLR_ALL)) + +#define IS_QSPI_BLOCK_SIZE(x) ((x) <= (QSPI_EXAR_EXADR >> QSPI_EXAR_EXADR_POS)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup QSPI_Local_Variable QSPI Local Variable + * @{ + */ + +/* Current read mode */ +static uint32_t m_u32ReadMode = 0U; + +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup QSPI_Global_Functions QSPI Global Functions + * @{ + */ + +/** + * @brief De-initializes QSPI. + * @param None + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: Works timeout. + */ +int32_t QSPI_DeInit(void) +{ + WRITE_REG32(CM_QSPI->CR, 0x003F0000UL); + WRITE_REG32(CM_QSPI->CSCR, 0x0FUL); + WRITE_REG32(CM_QSPI->FCR, 0x8033UL); + WRITE_REG32(CM_QSPI->CCMD, 0x0UL); + WRITE_REG32(CM_QSPI->XCMD, 0xFFUL); + WRITE_REG32(CM_QSPI->SR2, QSPI_FLAG_ROM_ACCESS_ERR); + WRITE_REG32(CM_QSPI->EXAR, 0UL); + return LL_OK; +} + +/** + * @brief Initialize QSPI. + * @param [in] pstcQspiInit Pointer to a @ref stc_qspi_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t QSPI_Init(const stc_qspi_init_t *pstcQspiInit) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Duty = 0UL; + + if (NULL == pstcQspiInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_QSPI_CLK_DIV(pstcQspiInit->u32ClockDiv)); + DDL_ASSERT(IS_QSPI_SPI_MD(pstcQspiInit->u32SpiMode)); + DDL_ASSERT(IS_QSPI_PREFETCH_MD(pstcQspiInit->u32PrefetchMode)); + DDL_ASSERT(IS_QSPI_READ_MD(pstcQspiInit->u32ReadMode)); + DDL_ASSERT(IS_QSPI_DUMMY_CYCLE(pstcQspiInit->u32DummyCycle)); + DDL_ASSERT(IS_QSPI_ADDR_WIDTH(pstcQspiInit->u32AddrWidth)); + DDL_ASSERT(IS_QSPI_QSSN_SETUP_TIME(pstcQspiInit->u32SetupTime)); + DDL_ASSERT(IS_QSPI_QSSN_RELEASE_TIME(pstcQspiInit->u32ReleaseTime)); + DDL_ASSERT(IS_QSPI_QSSN_INTERVAL_TIME(pstcQspiInit->u32IntervalTime)); + + /* Duty cycle compensation */ + if (0UL == (pstcQspiInit->u32ClockDiv & QSPI_CLK_DIV2)) { + u32Duty = QSPI_FCR_DUTY; + } + MODIFY_REG32(CM_QSPI->CR, QSPI_CR_CLR_MASK, (pstcQspiInit->u32ClockDiv | pstcQspiInit->u32SpiMode | + pstcQspiInit->u32PrefetchMode | pstcQspiInit->u32ReadMode)); + WRITE_REG32(CM_QSPI->CSCR, ((pstcQspiInit->u32ReleaseTime >> 8U) | pstcQspiInit->u32IntervalTime)); + MODIFY_REG32(CM_QSPI->FCR, QSPI_FCR_CLR_MASK, (pstcQspiInit->u32DummyCycle | pstcQspiInit->u32AddrWidth | + pstcQspiInit->u32SetupTime | (pstcQspiInit->u32ReleaseTime & 0xFFU) | u32Duty)); + } + + return i32Ret; +} + +/** + * @brief Fills each stc_qspi_init_t member with default value. + * @param [out] pstcQspiInit Pointer to a @ref stc_qspi_init_t structure + * @retval int32_t: + * - LL_OK: stc_qspi_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t QSPI_StructInit(stc_qspi_init_t *pstcQspiInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcQspiInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcQspiInit->u32ClockDiv = QSPI_CLK_DIV2; + pstcQspiInit->u32SpiMode = QSPI_SPI_MD0; + pstcQspiInit->u32PrefetchMode = QSPI_PREFETCH_MD_INVD; + pstcQspiInit->u32ReadMode = QSPI_RD_MD_STD_RD; + pstcQspiInit->u32DummyCycle = QSPI_DUMMY_CYCLE3; + pstcQspiInit->u32AddrWidth = QSPI_ADDR_WIDTH_24BIT; + pstcQspiInit->u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5; + pstcQspiInit->u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK0P5; + pstcQspiInit->u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1; + } + + return i32Ret; +} + +/** + * @brief Set the level of WP pin. + * @param [in] u32Level The level value. + * This parameter can be one of the following values: + * @arg QSPI_WP_PIN_LOW: WP(QSIO2) pin output low + * @arg QSPI_WP_PIN_HIGH: WP(QSIO2) pin output high + * @retval None + */ +void QSPI_SetWpPinLevel(uint32_t u32Level) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_WP_PIN_LVL(u32Level)); + + MODIFY_REG32(CM_QSPI->FCR, QSPI_FCR_WPOL, u32Level); +} + +/** + * @brief Set the prefetch mode. + * @param [in] u32Mode The prefetch mode. + * This parameter can be one of the following values: + * @arg QSPI_PREFETCH_MD_INVD: Disable prefetch + * @arg QSPI_PREFETCH_MD_EDGE_STOP: Stop prefetch at the edge of byte + * @arg QSPI_PREFETCH_MD_IMMED_STOP: Stop prefetch at current position immediately + * @retval None + */ +void QSPI_SetPrefetchMode(uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_PREFETCH_MD(u32Mode)); + + MODIFY_REG32(CM_QSPI->CR, (QSPI_CR_PFE | QSPI_CR_PFSAE), u32Mode); +} + +/** + * @brief Selects the block to access. + * @param [in] u8Block Memory block number (range is 0 to 63) + * @retval None + */ +void QSPI_SelectMemoryBlock(uint8_t u8Block) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_BLOCK_SIZE(u8Block)); + + WRITE_REG32(CM_QSPI->EXAR, ((uint32_t)u8Block << QSPI_EXAR_EXADR_POS)); +} + +/** + * @brief Set the read mode. + * @param [in] u32Mode Read mode. + * This parameter can be one of the following values: + * @arg QSPI_RD_MD_STD_RD: Standard read mode (no dummy cycles) + * @arg QSPI_RD_MD_FAST_RD: Fast read mode (dummy cycles between address and data) + * @arg QSPI_RD_MD_DUAL_OUTPUT_FAST_RD: Fast read dual output mode (data on 2 lines) + * @arg QSPI_RD_MD_DUAL_IO_FAST_RD: Fast read dual I/O mode (address and data on 2 lines) + * @arg QSPI_RD_MD_QUAD_OUTPUT_FAST_RD: Fast read quad output mode (data on 4 lines) + * @arg QSPI_RD_MD_QUAD_IO_FAST_RD: Fast read quad I/O mode (address and data on 4 lines) + * @arg QSPI_RD_MD_CUSTOM_STANDARD_RD: Custom standard read mode + * @arg QSPI_RD_MD_CUSTOM_FAST_RD: Custom fast read mode + * @retval None + */ +void QSPI_SetReadMode(uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_READ_MD(u32Mode)); + + MODIFY_REG32(CM_QSPI->CR, QSPI_CR_MDSEL, u32Mode); +} + +/** + * @brief Configure the custom read. + * @param [in] pstcCustomMode Pointer to a @ref stc_qspi_custom_mode_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t QSPI_CustomReadConfig(const stc_qspi_custom_mode_t *pstcCustomMode) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcCustomMode) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_QSPI_INSTR_PROTOCOL(pstcCustomMode->u32InstrProtocol)); + DDL_ASSERT(IS_QSPI_ADDR_PROTOCOL(pstcCustomMode->u32AddrProtocol)); + DDL_ASSERT(IS_QSPI_DATA_PROTOCOL(pstcCustomMode->u32DataProtocol)); + + MODIFY_REG32(CM_QSPI->CR, QSPI_CUSTOM_MD_CLR_MASK, (pstcCustomMode->u32InstrProtocol | + pstcCustomMode->u32AddrProtocol | pstcCustomMode->u32DataProtocol)); + WRITE_REG32(CM_QSPI->CCMD, pstcCustomMode->u8InstrCode); + } + + return i32Ret; +} + +/** + * @brief Enable or disable XIP mode. + * @param [in] u8ModeCode Enter or exit XIP mode code + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void QSPI_XipModeCmd(uint8_t u8ModeCode, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(CM_QSPI->XCMD, u8ModeCode); + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_XIPE); + } else { + CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_XIPE); + } +} + +/** + * @brief Enter direct communication mode. + * @param None + * @retval None + */ +void QSPI_EnterDirectCommMode(void) +{ + /* Backup the read mode */ + m_u32ReadMode = READ_REG32_BIT(CM_QSPI->CR, QSPI_CR_MDSEL); + if (m_u32ReadMode <= QSPI_RD_MD_QUAD_IO_FAST_RD) { + /* Set standard read mode */ + CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_MDSEL); + } + /* Enter direct communication mode */ + SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); +} + +/** + * @brief Exit direct communication mode. + * @param None + * @retval None + */ +void QSPI_ExitDirectCommMode(void) +{ + /* Exit direct communication mode */ + CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); + if (m_u32ReadMode <= QSPI_RD_MD_QUAD_IO_FAST_RD) { + /* Recovery the read mode */ + SET_REG32_BIT(CM_QSPI->CR, m_u32ReadMode); + } +} + +/** + * @brief Get the size of prefetched buffer. + * @param None + * @retval uint8_t Prefetched buffer size. + */ +uint8_t QSPI_GetPrefetchBufSize(void) +{ + return (uint8_t)(READ_REG32_BIT(CM_QSPI->SR, QSPI_SR_PFNUM) >> QSPI_SR_PFNUM_POS); +} + +/** + * @brief Get QSPI flag. + * @param [in] u32Flag QSPI flag type + * This parameter can be one or any combination of the following values: + * @arg QSPI_FLAG_DIRECT_COMM_BUSY: Serial transfer being processed + * @arg QSPI_FLAG_XIP_MD: XIP mode + * @arg QSPI_FLAG_ROM_ACCESS_ERR: ROM access detection status in direct communication mode + * @arg QSPI_FLAG_PREFETCH_BUF_FULL: Prefetch buffer is full + * @arg QSPI_FLAG_PREFETCH_STOP: Prefetch function operating + * @arg QSPI_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t QSPI_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_QSPI_FLAG(u32Flag)); + + if (0UL != READ_REG32_BIT(CM_QSPI->SR, u32Flag)) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear QSPI flag. + * @param [in] u32Flag QSPI flag type + * This parameter can be one or any combination of the following values: + * @arg QSPI_FLAG_ROM_ACCESS_ERR: ROM access detection status in direct communication mode + * @arg QSPI_FLAG_CLR_ALL: All of the above + * @retval None + */ +void QSPI_ClearStatus(uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_CLR_FLAG(u32Flag)); + + WRITE_REG32(CM_QSPI->SR2, u32Flag); +} + +/** + * @} + */ + +#endif /* LL_QSPI_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_rmu.c b/mcu/lib/src/hc32_ll_rmu.c new file mode 100644 index 0000000..76e726d --- /dev/null +++ b/mcu/lib/src/hc32_ll_rmu.c @@ -0,0 +1,137 @@ +/** + ******************************************************************************* + * @file hc32_ll_rmu.c + * @brief This file provides firmware functions to manage the Reset Manage Unit + * (RMU). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_rmu.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_RMU RMU + * @brief RMU Driver Library + * @{ + */ + +#if (LL_RMU_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup RMU_Local_Macros RMU Local Macros + * @{ + */ + +/** + * @defgroup RMU_Check_Parameters_Validity RMU Check Parameters Validity + * @{ + */ + +/*! Parameter validity check for RMU reset cause. */ +#define IS_VALID_RMU_RST_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | RMU_FLAG_ALL) == RMU_FLAG_ALL)) + +/** + * @} + */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup RMU_Global_Functions RMU Global Functions + * @{ + */ + +/** + * @brief Get the reset cause. + * @param [in] u32RmuResetCause Reset flags that need to be queried, @ref RMU_ResetCause in details + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t RMU_GetStatus(uint32_t u32RmuResetCause) +{ + en_flag_status_t enStatus; + DDL_ASSERT(IS_VALID_RMU_RST_FLAG(u32RmuResetCause)); + + enStatus = ((0UL == READ_REG32_BIT(CM_RMU->RSTF0, u32RmuResetCause)) ? RESET : SET); + return enStatus; +} + +/** + * @brief Clear reset Status. + * @param None + * @retval NOne + * @note Clear reset flag should be done after read RMU_RSTF0 register. + * Call PWC_Unlock(PWC_UNLOCK_CODE_1) unlock RMU_RSTF0 register first. + */ +void RMU_ClearStatus(void) +{ + SET_REG_BIT(CM_RMU->RSTF0, RMU_RSTF0_CLRF); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); +} + +/** + * @} + */ + +#endif /* LL_RMU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_rtc.c b/mcu/lib/src/hc32_ll_rtc.c new file mode 100644 index 0000000..db8209c --- /dev/null +++ b/mcu/lib/src/hc32_ll_rtc.c @@ -0,0 +1,936 @@ +/** + ******************************************************************************* + * @file hc32_ll_rtc.c + * @brief This file provides firmware functions to manage the Real-Time + * Clock(RTC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_rtc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_RTC RTC + * @brief Real-Time Clock Driver Library + * @{ + */ + +#if (LL_RTC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup RTC_Local_Macros RTC Local Macros + * @{ + */ + +/* RTC software reset timeout(ms) */ +#define RTC_SW_RST_TIMEOUT (100UL) +/* RTC mode switch timeout(ms) */ +#define RTC_MD_SWITCH_TIMEOUT (100UL) + +/** + * @defgroup RTC_Check_Parameters_Validity RTC Check Parameters Validity + * @{ + */ +#define IS_RTC_DATA_FMT(x) \ +( ((x) == RTC_DATA_FMT_DEC) || \ + ((x) == RTC_DATA_FMT_BCD)) + +#define IS_RTC_CLK_SRC(x) \ +( ((x) == RTC_CLK_SRC_XTAL32) || \ + ((x) == RTC_CLK_SRC_LRC)) + +#define IS_RTC_HOUR_FMT(x) \ +( ((x) == RTC_HOUR_FMT_12H) || \ + ((x) == RTC_HOUR_FMT_24H)) + +#define IS_RTC_INT_PERIOD(x) \ +( ((x) == RTC_INT_PERIOD_INVD) || \ + ((x) == RTC_INT_PERIOD_PER_HALF_SEC) || \ + ((x) == RTC_INT_PERIOD_PER_SEC) || \ + ((x) == RTC_INT_PERIOD_PER_MINUTE) || \ + ((x) == RTC_INT_PERIOD_PER_HOUR) || \ + ((x) == RTC_INT_PERIOD_PER_DAY) || \ + ((x) == RTC_INT_PERIOD_PER_MONTH)) + +#define IS_RTC_CLK_COMPEN(x) \ +( ((x) == RTC_CLK_COMPEN_DISABLE) || \ + ((x) == RTC_CLK_COMPEN_ENABLE)) + +#define IS_RTC_CLK_COMPEN_MD(x) \ +( ((x) == RTC_CLK_COMPEN_MD_DISTRIBUTED) || \ + ((x) == RTC_CLK_COMPEN_MD_UNIFORM)) + +#define IS_RTC_HOUR_12H_AM_PM(x) \ +( ((x) == RTC_HOUR_12H_AM) || \ + ((x) == RTC_HOUR_12H_PM)) + +#define IS_RTC_GET_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | RTC_FLAG_ALL) == RTC_FLAG_ALL)) + +#define IS_RTC_CLR_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | RTC_FLAG_CLR_ALL) == RTC_FLAG_CLR_ALL)) + +#define IS_RTC_INT(x) \ +( ((x) != 0U) && \ + (((x) | RTC_INT_ALL) == RTC_INT_ALL)) + +#define IS_RTC_YEAR(x) ((x) <= 99U) + +#define IS_RTC_MONTH(x) (((x) >= 1U) && ((x) <= 12U)) + +#define IS_RTC_DAY(x) (((x) >= 1U) && ((x) <= 31U)) + +#define IS_RTC_HOUR_12H(x) (((x) >= 1U) && ((x) <= 12U)) + +#define IS_RTC_HOUR_24H(x) ((x) <= 23U) + +#define IS_RTC_MINUTE(x) ((x) <= 59U) + +#define IS_RTC_SEC(x) ((x) <= 59U) + +#define IS_RTC_WEEKDAY(x) ((x) <= 6U) + +#define IS_RTC_ALARM_WEEKDAY(x) (((x) >= 0x01U) && ((x) <= 0x7FU)) + +#define IS_RTC_COMPEN_VALUE(x) ((x) <= 0x1FFU) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup RTC_Global_Functions RTC Global Functions + * @{ + */ + +/** + * @brief De-Initialize RTC. + * @param None + * @retval int32_t: + * - LL_OK: De-Initialize success + * - LL_ERR_TIMEOUT: De-Initialize timeout + */ +int32_t RTC_DeInit(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + WRITE_REG32(bCM_RTC->CR0_b.RESET, RESET); + /* Waiting for normal count status or end of RTC software reset */ + u32Count = RTC_SW_RST_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_RTC->CR0_b.RESET)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + if (LL_OK == i32Ret) { + /* Reset all RTC registers */ + WRITE_REG32(bCM_RTC->CR0_b.RESET, SET); + /* Waiting for RTC software reset to complete */ + u32Count = RTC_SW_RST_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_RTC->CR0_b.RESET)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + } + + return i32Ret; +} + +/** + * @brief Initialize RTC. + * @param [in] pstcRtcInit Pointer to a @ref stc_rtc_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_Init(const stc_rtc_init_t *pstcRtcInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_CLK_SRC(pstcRtcInit->u8ClockSrc)); + DDL_ASSERT(IS_RTC_HOUR_FMT(pstcRtcInit->u8HourFormat)); + DDL_ASSERT(IS_RTC_INT_PERIOD(pstcRtcInit->u8IntPeriod)); + DDL_ASSERT(IS_RTC_CLK_COMPEN(pstcRtcInit->u8ClockCompen)); + DDL_ASSERT(IS_RTC_COMPEN_VALUE(pstcRtcInit->u16CompenValue)); + DDL_ASSERT(IS_RTC_CLK_COMPEN_MD(pstcRtcInit->u8CompenMode)); + + /* RTC CR3 Configuration */ + MODIFY_REG8(CM_RTC->CR3, (RTC_CR3_LRCEN | RTC_CR3_RCKSEL), pstcRtcInit->u8ClockSrc); + /* RTC CR1 Configuration */ + MODIFY_REG8(CM_RTC->CR1, (RTC_CR1_PRDS | RTC_CR1_AMPM | RTC_CR1_ONEHZSEL), + (pstcRtcInit->u8IntPeriod | pstcRtcInit->u8HourFormat | pstcRtcInit->u8CompenMode)); + /* RTC Compensation Configuration */ + MODIFY_REG8(CM_RTC->ERRCRH, (RTC_ERRCRH_COMPEN | RTC_ERRCRH_COMP8), + (pstcRtcInit->u8ClockCompen | (uint8_t)((pstcRtcInit->u16CompenValue >> 8U) & 0x01U))); + WRITE_REG8(CM_RTC->ERRCRL, (uint8_t)(pstcRtcInit->u16CompenValue & 0xFFU)); + } + + return i32Ret; +} + +/** + * @brief Fills each stc_rtc_init_t member with default value. + * @param [out] pstcRtcInit Pointer to a @ref stc_rtc_init_t structure + * @retval int32_t: + * - LL_OK: stc_rtc_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_StructInit(stc_rtc_init_t *pstcRtcInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcRtcInit->u8ClockSrc = RTC_CLK_SRC_LRC; + pstcRtcInit->u8HourFormat = RTC_HOUR_FMT_24H; + pstcRtcInit->u8IntPeriod = RTC_INT_PERIOD_INVD; + pstcRtcInit->u8ClockCompen = RTC_CLK_COMPEN_DISABLE; + pstcRtcInit->u8CompenMode = RTC_CLK_COMPEN_MD_DISTRIBUTED; + pstcRtcInit->u16CompenValue = 0U; + } + + return i32Ret; +} + +/** + * @brief Enter RTC read/write mode. + * @param None + * @retval int32_t: + * - LL_OK: Enter mode success + * - LL_ERR_TIMEOUT: Enter mode timeout + */ +int32_t RTC_EnterRwMode(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* Mode switch when RTC is running */ + if (0UL != READ_REG32(bCM_RTC->CR1_b.START)) { + if (1UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + WRITE_REG32(bCM_RTC->CR2_b.RWREQ, SET); + /* Waiting for RWEN bit set */ + u32Count = RTC_MD_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL); + while (1UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + } + } + + return i32Ret; +} + +/** + * @brief Exit RTC read/write mode. + * @param None + * @retval int32_t: + * - LL_OK: Exit mode success + * - LL_ERR_TIMEOUT: Exit mode timeout + */ +int32_t RTC_ExitRwMode(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* Mode switch when RTC is running */ + if (0UL != READ_REG32(bCM_RTC->CR1_b.START)) { + if (0UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + WRITE_REG32(bCM_RTC->CR2_b.RWREQ, RESET); + /* Waiting for RWEN bit reset */ + u32Count = RTC_MD_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + } + } + + return i32Ret; +} + +/** + * @brief Confirm the condition for RTC to enter low power mode. + * @param None + * @retval int32_t: + * - LL_OK: Can enter low power mode + * - LL_ERR_TIMEOUT: Can't enter low power mode + */ +int32_t RTC_ConfirmLPMCond(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* Check RTC work status */ + if (0UL != READ_REG32(bCM_RTC->CR1_b.START)) { + WRITE_REG32(bCM_RTC->CR2_b.RWREQ, SET); + /* Waiting for RTC RWEN bit set */ + u32Count = RTC_MD_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL); + while (1UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + if (LL_OK == i32Ret) { + WRITE_REG32(bCM_RTC->CR2_b.RWREQ, RESET); + /* Waiting for RTC RWEN bit reset */ + u32Count = RTC_MD_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + } + } + + return i32Ret; +} + +/** + * @brief Set the RTC interrupt period. + * @param [in] u8Period Specifies the interrupt period. + * This parameter can be one of the following values: + * @arg RTC_INT_PERIOD_INVD: Period interrupt invalid + * @arg RTC_INT_PERIOD_PER_HALF_SEC: Interrupt per half second + * @arg RTC_INT_PERIOD_PER_SEC: Interrupt per second + * @arg RTC_INT_PERIOD_PER_MINUTE: Interrupt per minute + * @arg RTC_INT_PERIOD_PER_HOUR: Interrupt per hour + * @arg RTC_INT_PERIOD_PER_DAY: Interrupt per day + * @arg RTC_INT_PERIOD_PER_MONTH: Interrupt per month + * @retval None + */ +void RTC_SetIntPeriod(uint8_t u8Period) +{ + uint32_t u32RtcSta; + uint32_t u32IntSta; + + /* Check parameters */ + DDL_ASSERT(IS_RTC_INT_PERIOD(u8Period)); + + u32RtcSta = READ_REG32(bCM_RTC->CR1_b.START); + u32IntSta = READ_REG32(bCM_RTC->CR2_b.PRDIE); + /* Disable period interrupt when START=1 and clear period flag after write */ + if ((0UL != u32IntSta) && (0UL != u32RtcSta)) { + WRITE_REG32(bCM_RTC->CR2_b.PRDIE, RESET); + } + + /* RTC CR1 Configuration */ + MODIFY_REG8(CM_RTC->CR1, RTC_CR1_PRDS, u8Period); + + if ((0UL != u32IntSta) && (0UL != u32RtcSta)) { + WRITE_REG32(bCM_RTC->CR2_b.PRDIE, SET); + } +} + +/** + * @brief Set the RTC clock source. + * @param [in] u8Src Specifies the clock source. + * This parameter can be one of the following values: + * @arg @ref RTC_Clock_Source + * @retval None + */ +void RTC_SetClockSrc(uint8_t u8Src) +{ + /* Check parameters */ + DDL_ASSERT(IS_RTC_CLK_SRC(u8Src)); + + MODIFY_REG8(CM_RTC->CR3, (RTC_CR3_LRCEN | RTC_CR3_RCKSEL), u8Src); +} + +/** + * @brief Set RTC clock compensation value. + * @param [in] u16Value Specifies the clock compensation value of RTC. + * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 0x1FF. + * @retval None + */ +void RTC_SetClockCompenValue(uint16_t u16Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_RTC_COMPEN_VALUE(u16Value)); + + WRITE_REG32(bCM_RTC->ERRCRH_b.COMP8, ((uint32_t)u16Value >> 8U) & 0x01U); + WRITE_REG8(CM_RTC->ERRCRL, (uint8_t)(u16Value & 0x00FFU)); +} + +/** + * @brief Get RTC counter status. + * @param None + * @retval An @ref en_functional_state_t enumeration value. + * - ENABLE: RTC counter started + * - DISABLE: RTC counter stopped + */ +en_functional_state_t RTC_GetCounterState(void) +{ + en_functional_state_t enState = DISABLE; + + if (0UL != READ_REG32(bCM_RTC->CR1_b.START)) { + enState = ENABLE; + } + + return enState; +} + +/** + * @brief Enable or disable RTC count. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_Cmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_RTC->CR1_b.START, enNewState); +} + +/** + * @brief Enable or disable RTC LRC function. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_LrcCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_RTC->CR3_b.LRCEN, enNewState); +} + +/** + * @brief Enable or disable RTC 1HZ output. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_OneHzOutputCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_RTC->CR1_b.ONEHZOE, enNewState); +} + +/** + * @brief Enable or disable clock compensation. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_ClockCompenCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_RTC->ERRCRH_b.COMPEN, enNewState); +} + +/** + * @brief Set RTC current date. + * @param [in] u8Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [in] pstcRtcDate Pointer to a @ref stc_rtc_date_t structure + * @retval int32_t: + * - LL_OK: Set date success + * - LL_ERR: Set date failed + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_SetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcDate) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + if (RTC_DATA_FMT_DEC != u8Format) { + DDL_ASSERT(IS_RTC_YEAR(RTC_BCD2DEC(pstcRtcDate->u8Year))); + DDL_ASSERT(IS_RTC_MONTH(RTC_BCD2DEC(pstcRtcDate->u8Month))); + DDL_ASSERT(IS_RTC_DAY(RTC_BCD2DEC(pstcRtcDate->u8Day))); + } else { + DDL_ASSERT(IS_RTC_YEAR(pstcRtcDate->u8Year)); + DDL_ASSERT(IS_RTC_MONTH(pstcRtcDate->u8Month)); + DDL_ASSERT(IS_RTC_DAY(pstcRtcDate->u8Day)); + } + DDL_ASSERT(IS_RTC_WEEKDAY(pstcRtcDate->u8Weekday)); + + /* Enter read/write mode */ + if (LL_OK != RTC_EnterRwMode()) { + i32Ret = LL_ERR; + } else { + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcDate->u8Year = RTC_DEC2BCD(pstcRtcDate->u8Year); + pstcRtcDate->u8Month = RTC_DEC2BCD(pstcRtcDate->u8Month); + pstcRtcDate->u8Day = RTC_DEC2BCD(pstcRtcDate->u8Day); + } + + WRITE_REG8(CM_RTC->YEAR, pstcRtcDate->u8Year); + WRITE_REG8(CM_RTC->MON, pstcRtcDate->u8Month); + WRITE_REG8(CM_RTC->DAY, pstcRtcDate->u8Day); + WRITE_REG8(CM_RTC->WEEK, pstcRtcDate->u8Weekday); + + /* Exit read/write mode */ + if (LL_OK != RTC_ExitRwMode()) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/** + * @brief Get RTC current date. + * @param [in] u8Format Specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [out] pstcRtcDate Pointer to a @ref stc_rtc_date_t structure + * @retval int32_t: + * - LL_OK: Get date success + * - LL_ERR: Get date failed + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_GetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcDate) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + /* Enter read/write mode */ + if (LL_OK != RTC_EnterRwMode()) { + i32Ret = LL_ERR; + } else { + /* Get RTC date registers */ + pstcRtcDate->u8Year = READ_REG8(CM_RTC->YEAR); + pstcRtcDate->u8Month = READ_REG8(CM_RTC->MON); + pstcRtcDate->u8Day = READ_REG8(CM_RTC->DAY); + pstcRtcDate->u8Weekday = READ_REG8(CM_RTC->WEEK); + + /* Check decimal format*/ + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcDate->u8Year = RTC_BCD2DEC(pstcRtcDate->u8Year); + pstcRtcDate->u8Month = RTC_BCD2DEC(pstcRtcDate->u8Month); + pstcRtcDate->u8Day = RTC_BCD2DEC(pstcRtcDate->u8Day); + } + + /* exit read/write mode */ + if (LL_OK != RTC_ExitRwMode()) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/** + * @brief Set RTC current time. + * @param [in] u8Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [in] pstcRtcTime Pointer to a @ref stc_rtc_time_t structure + * @retval int32_t: + * - LL_OK: Set time success + * - LL_ERR: Set time failed + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_SetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcTime) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + if (RTC_DATA_FMT_DEC != u8Format) { + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + DDL_ASSERT(IS_RTC_HOUR_12H(RTC_BCD2DEC(pstcRtcTime->u8Hour))); + DDL_ASSERT(IS_RTC_HOUR_12H_AM_PM(pstcRtcTime->u8AmPm)); + } else { + DDL_ASSERT(IS_RTC_HOUR_24H(RTC_BCD2DEC(pstcRtcTime->u8Hour))); + } + DDL_ASSERT(IS_RTC_MINUTE(RTC_BCD2DEC(pstcRtcTime->u8Minute))); + DDL_ASSERT(IS_RTC_SEC(RTC_BCD2DEC(pstcRtcTime->u8Second))); + } else { + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + DDL_ASSERT(IS_RTC_HOUR_12H(pstcRtcTime->u8Hour)); + DDL_ASSERT(IS_RTC_HOUR_12H_AM_PM(pstcRtcTime->u8AmPm)); + } else { + DDL_ASSERT(IS_RTC_HOUR_24H(pstcRtcTime->u8Hour)); + } + DDL_ASSERT(IS_RTC_MINUTE(pstcRtcTime->u8Minute)); + DDL_ASSERT(IS_RTC_SEC(pstcRtcTime->u8Second)); + } + + /* Enter read/write mode */ + if (LL_OK != RTC_EnterRwMode()) { + i32Ret = LL_ERR; + } else { + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcTime->u8Hour = RTC_DEC2BCD(pstcRtcTime->u8Hour); + pstcRtcTime->u8Minute = RTC_DEC2BCD(pstcRtcTime->u8Minute); + pstcRtcTime->u8Second = RTC_DEC2BCD(pstcRtcTime->u8Second); + } + if ((RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) && + (RTC_HOUR_12H_PM == pstcRtcTime->u8AmPm)) { + SET_REG8_BIT(pstcRtcTime->u8Hour, RTC_HOUR_12H_PM); + } + + WRITE_REG8(CM_RTC->HOUR, pstcRtcTime->u8Hour); + WRITE_REG8(CM_RTC->MIN, pstcRtcTime->u8Minute); + WRITE_REG8(CM_RTC->SEC, pstcRtcTime->u8Second); + + /* Exit read/write mode */ + if (LL_OK != RTC_ExitRwMode()) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/** + * @brief Get RTC current time. + * @param [in] u8Format Specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [out] pstcRtcTime Pointer to a @ref stc_rtc_time_t structure + * @retval int32_t: + * - LL_OK: Get time success + * - LL_ERR: Get time failed + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_GetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcTime) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + /* Enter read/write mode */ + if (LL_OK != RTC_EnterRwMode()) { + i32Ret = LL_ERR; + } else { + /* Get RTC time registers */ + pstcRtcTime->u8Hour = READ_REG8(CM_RTC->HOUR); + pstcRtcTime->u8Minute = READ_REG8(CM_RTC->MIN); + pstcRtcTime->u8Second = READ_REG8(CM_RTC->SEC); + + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + if (RTC_HOUR_12H_PM == (pstcRtcTime->u8Hour & RTC_HOUR_12H_PM)) { + CLR_REG8_BIT(pstcRtcTime->u8Hour, RTC_HOUR_12H_PM); + pstcRtcTime->u8AmPm = RTC_HOUR_12H_PM; + } else { + pstcRtcTime->u8AmPm = RTC_HOUR_12H_AM; + } + } else { + pstcRtcTime->u8AmPm = RTC_HOUR_24H; + } + + /* Check decimal format*/ + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcTime->u8Hour = RTC_BCD2DEC(pstcRtcTime->u8Hour); + pstcRtcTime->u8Minute = RTC_BCD2DEC(pstcRtcTime->u8Minute); + pstcRtcTime->u8Second = RTC_BCD2DEC(pstcRtcTime->u8Second); + } + + /* exit read/write mode */ + if (LL_OK != RTC_ExitRwMode()) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/** + * @brief Set RTC alarm time. + * @param [in] u8Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [in] pstcRtcAlarm Pointer to a @ref stc_rtc_alarm_t structure + * @retval int32_t: + * - LL_OK: Set RTC alarm time success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_SetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcAlarm) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + if (RTC_DATA_FMT_DEC != u8Format) { + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + DDL_ASSERT(IS_RTC_HOUR_12H(RTC_BCD2DEC(pstcRtcAlarm->u8AlarmHour))); + DDL_ASSERT(IS_RTC_HOUR_12H_AM_PM(pstcRtcAlarm->u8AlarmAmPm)); + } else { + DDL_ASSERT(IS_RTC_HOUR_24H(RTC_BCD2DEC(pstcRtcAlarm->u8AlarmHour))); + } + DDL_ASSERT(IS_RTC_MINUTE(RTC_BCD2DEC(pstcRtcAlarm->u8AlarmMinute))); + } else { + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + DDL_ASSERT(IS_RTC_HOUR_12H(pstcRtcAlarm->u8AlarmHour)); + DDL_ASSERT(IS_RTC_HOUR_12H_AM_PM(pstcRtcAlarm->u8AlarmAmPm)); + } else { + DDL_ASSERT(IS_RTC_HOUR_24H(pstcRtcAlarm->u8AlarmHour)); + } + DDL_ASSERT(IS_RTC_MINUTE(pstcRtcAlarm->u8AlarmMinute)); + } + DDL_ASSERT(IS_RTC_ALARM_WEEKDAY(pstcRtcAlarm->u8AlarmWeekday)); + + /* Configure alarm registers */ + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcAlarm->u8AlarmHour = RTC_DEC2BCD(pstcRtcAlarm->u8AlarmHour); + pstcRtcAlarm->u8AlarmMinute = RTC_DEC2BCD(pstcRtcAlarm->u8AlarmMinute); + } + if ((RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) && + (RTC_HOUR_12H_PM == pstcRtcAlarm->u8AlarmAmPm)) { + SET_REG8_BIT(pstcRtcAlarm->u8AlarmHour, RTC_HOUR_12H_PM); + } + + WRITE_REG8(CM_RTC->ALMHOUR, pstcRtcAlarm->u8AlarmHour); + WRITE_REG8(CM_RTC->ALMMIN, pstcRtcAlarm->u8AlarmMinute); + WRITE_REG8(CM_RTC->ALMWEEK, pstcRtcAlarm->u8AlarmWeekday); + } + + return i32Ret; +} + +/** + * @brief Get RTC alarm time. + * @param [in] u8Format Specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [out] pstcRtcAlarm Pointer to a @ref stc_rtc_alarm_t structure + * @retval int32_t: + * - LL_OK: Get RTC alarm time success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_GetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcAlarm) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + + /* Get RTC date and time register */ + pstcRtcAlarm->u8AlarmWeekday = READ_REG8(CM_RTC->ALMWEEK); + pstcRtcAlarm->u8AlarmMinute = READ_REG8(CM_RTC->ALMMIN); + pstcRtcAlarm->u8AlarmHour = READ_REG8(CM_RTC->ALMHOUR); + + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + if (RTC_HOUR_12H_PM == (pstcRtcAlarm->u8AlarmHour & RTC_HOUR_12H_PM)) { + CLR_REG8_BIT(pstcRtcAlarm->u8AlarmHour, RTC_HOUR_12H_PM); + pstcRtcAlarm->u8AlarmAmPm = RTC_HOUR_12H_PM; + } else { + pstcRtcAlarm->u8AlarmAmPm = RTC_HOUR_12H_AM; + } + } else { + pstcRtcAlarm->u8AlarmAmPm = RTC_HOUR_24H; + } + + /* Check decimal format*/ + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcAlarm->u8AlarmHour = RTC_BCD2DEC(pstcRtcAlarm->u8AlarmHour); + pstcRtcAlarm->u8AlarmMinute = RTC_BCD2DEC(pstcRtcAlarm->u8AlarmMinute); + } + } + + return i32Ret; +} + +/** + * @brief Enable or disable RTC alarm. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_AlarmCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_RTC->CR2_b.ALME, enNewState); +} + +/** + * @brief Enable or disable specified RTC interrupt. + * @param [in] u32IntType Specifies the RTC interrupt source. + * This parameter can be one or any combination of the following values: + * @arg @ref RTC_Interrupt + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint32_t u32IntTemp; + + /* Check parameters */ + DDL_ASSERT(IS_RTC_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32IntTemp = u32IntType & 0x0000FFUL; + if (0UL != u32IntTemp) { + if (DISABLE != enNewState) { + SET_REG8_BIT(CM_RTC->CR2, u32IntTemp); + } else { + CLR_REG8_BIT(CM_RTC->CR2, u32IntTemp); + } + } + +} + +/** + * @brief Get RTC flag status. + * @param [in] u32Flag Specifies the RTC flag type. + * This parameter can be one or any combination of the following values: + * @arg @ref RTC_Flag + * @arg RTC_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t RTC_GetStatus(uint32_t u32Flag) +{ + uint8_t u8FlagTemp; + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_RTC_GET_FLAG(u32Flag)); + + u8FlagTemp = (uint8_t)(u32Flag & 0xFFU); + if (0U != u8FlagTemp) { + if (0U != (READ_REG8_BIT(CM_RTC->CR2, u8FlagTemp))) { + enFlagSta = SET; + } + } + + return enFlagSta; +} + +/** + * @brief Clear RTC flag. + * @param [in] u32Flag Specifies the RTC flag type. + * This parameter can be one or any combination of the following values: + * @arg @ref RTC_Flag + * @arg RTC_FLAG_CLR_ALL: All of the above + * @retval None + */ +void RTC_ClearStatus(uint32_t u32Flag) +{ + uint8_t u8FlagTemp; + + /* Check parameters */ + DDL_ASSERT(IS_RTC_CLR_FLAG(u32Flag)); + + u8FlagTemp = (uint8_t)(u32Flag & 0xFFU); + if (0U != u8FlagTemp) { + CLR_REG8_BIT(CM_RTC->CR1, RTC_CR1_ALMFCLR); + } + +} + +/** + * @} + */ + +#endif /* LL_RTC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_sdioc.c b/mcu/lib/src/hc32_ll_sdioc.c new file mode 100644 index 0000000..6184de4 --- /dev/null +++ b/mcu/lib/src/hc32_ll_sdioc.c @@ -0,0 +1,2874 @@ +/** + ******************************************************************************* + * @file hc32_ll_sdioc.c + * @brief This file provides firmware functions to manage the Secure Digital + * Input and Output Controller(SDIOC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-09-30 CDT Modify response type of MMC CMD3 + Rename function SDMMC_ACMD41_SendOperatCond to SDMMC_ACMD41_SendOperateCond + Rename function SDMMC_CMD1_SendOperatCond to SDMMC_CMD1_SendOperateCond + Optimize SDIOC_GetMode function + Support CMD5/CMD52/CMD53 + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_sdioc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_SDIOC SDIOC + * @brief SDIOC Driver Library + * @{ + */ + +#if (LL_SDIOC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SDIOC_Local_Macros SDIOC Local Macros + * @{ + */ + +/* CMD52 arguments field shift */ +#define SDIO_CMD52_ARG_REG_ADDR_SHIFT (9U) +#define SDIO_CMD52_ARG_FUNC_SHIFT (28U) + +/* CMD53 arguments field shift */ +#define SDIO_CMD53_ARG_REG_ADDR_SHIFT (9U) +#define SDIO_CMD53_ARG_FUNC_SHIFT (28U) + +/* Masks for R6 Response */ +#define SDMMC_R6_GEN_UNKNOWN_ERR (0x00002000UL) +#define SDMMC_R6_ILLEGAL_CMD (0x00004000UL) +#define SDMMC_R6_COM_CRC_FAIL (0x00008000UL) + +/* SDMMC command parameters */ +#define SDMMC_CMD8_CHECK_PATTERN (0x000001AAUL) +/* 3.2V-3.3V */ +#define SDMMC_ACMD41_VOLT_WIN (0x80100000UL) + +/* Command send and response timeout(ms) */ +#define SDMMC_CMD_TIMEOUT (5000UL) +/* Max erase Timeout 60s */ +#define SDMMC_MAX_ERASE_TIMEOUT (60000UL) +/* SDIOC software reset timeout(ms) */ +#define SDIOC_SW_RST_TIMEOUT (50UL) + +/* SDIOC NORINTSGEN register Mask */ +#define SDIOC_NORINTSGEN_CLR_MASK (0x01F7U) +/* SDIOC ERRINTSGEN register Mask */ +#define SDIOC_ERRINTSGEN_CLR_MASK (0x017FU) + +/*!< Get the specified register address of the specified SDIOC unit */ +#define SDIOC_ARG_ADDR(__UNIT__) (__IO uint32_t*)((uint32_t)(&((__UNIT__)->ARG0))) +#define SDIOC_BUF_ADDR(__UNIT__) (__IO uint32_t*)((uint32_t)(&((__UNIT__)->BUF0))) +#define SDIOC_RESP_ADDR(__UNIT__, __RESP__) (__IO uint32_t*)((uint32_t)(&((__UNIT__)->RESP0)) + (__RESP__)) + +/** + * @defgroup SDIOC_Check_Parameters_Validity SDIOC Check Parameters Validity + * @{ + */ +#define IS_SDIOC_UNIT(x) \ +( ((x) == CM_SDIOC1) || \ + ((x) == CM_SDIOC2)) + +#define IS_SDIOC_MD(x) \ +( ((x) == SDIOC_MD_SD) || \ + ((x) == SDIOC_MD_MMC)) + +#define IS_SDIOC_CARD_DETECT_WAY(x) \ +( ((x) == SDIOC_CARD_DETECT_CD_PIN_LVL) || \ + ((x) == SDIOC_CARD_DETECT_TEST_SIGNAL)) + +#define IS_SDIOC_CARD_DETECT_TEST_LEVEL(x) \ +( ((x) == SDIOC_CARD_DETECT_TEST_LVL_LOW) || \ + ((x) == SDIOC_CARD_DETECT_TEST_LVL_HIGH)) + +#define IS_SDIOC_SPEED_MD(x) \ +( ((x) == SDIOC_SPEED_MD_NORMAL) || \ + ((x) == SDIOC_SPEED_MD_HIGH)) + +#define IS_SDIOC_BUS_WIDTH(x) \ +( ((x) == SDIOC_BUS_WIDTH_1BIT) || \ + ((x) == SDIOC_BUS_WIDTH_4BIT) || \ + ((x) == SDIOC_BUS_WIDTH_8BIT)) + +#define IS_SDIOC_CLK_DIV(x) \ +( ((x) == SDIOC_CLK_DIV1) || \ + ((x) == SDIOC_CLK_DIV2) || \ + ((x) == SDIOC_CLK_DIV4) || \ + ((x) == SDIOC_CLK_DIV8) || \ + ((x) == SDIOC_CLK_DIV16) || \ + ((x) == SDIOC_CLK_DIV32) || \ + ((x) == SDIOC_CLK_DIV64) || \ + ((x) == SDIOC_CLK_DIV128) || \ + ((x) == SDIOC_CLK_DIV256)) + +#define IS_SDIOC_CMD_TYPE(x) \ +( ((x) == SDIOC_CMD_TYPE_NORMAL) || \ + ((x) == SDIOC_CMD_TYPE_SUSPEND) || \ + ((x) == SDIOC_CMD_TYPE_RESUME) || \ + ((x) == SDIOC_CMD_TYPE_ABORT)) + +#define IS_SDIOC_DATA_LINE(x) \ +( ((x) == SDIOC_DATA_LINE_DISABLE) || \ + ((x) == SDIOC_DATA_LINE_ENABLE)) + +#define IS_SDIOC_TRANS_DIR(x) \ +( ((x) == SDIOC_TRANS_DIR_TO_CARD) || \ + ((x) == SDIOC_TRANS_DIR_TO_HOST)) + +#define IS_SDIOC_AUTO_SEND_CMD12(x) \ +( ((x) == SDIOC_AUTO_SEND_CMD12_DISABLE) || \ + ((x) == SDIOC_AUTO_SEND_CMD12_ENABLE)) + +#define IS_SDIOC_TRANS_MD(x) \ +( ((x) == SDIOC_TRANS_MD_SINGLE) || \ + ((x) == SDIOC_TRANS_MD_INFINITE) || \ + ((x) == SDIOC_TRANS_MD_MULTI) || \ + ((x) == SDIOC_TRANS_MD_STOP_MULTI)) + +#define IS_SDIOC_DATA_TIMEOUT_TIME(x) ((x) <= SDIOC_DATA_TIMEOUT_CLK_2E27) + +#define IS_SDIOC_RESP_REG(x) \ +( ((x) == SDIOC_RESP_REG_BIT0_31) || \ + ((x) == SDIOC_RESP_REG_BIT32_63) || \ + ((x) == SDIOC_RESP_REG_BIT64_95) || \ + ((x) == SDIOC_RESP_REG_BIT96_127)) + +#define IS_SDIOC_SW_RST_TYPE(x) \ +( ((x) == SDIOC_SW_RST_DATA_LINE) || \ + ((x) == SDIOC_SW_RST_CMD_LINE) || \ + ((x) == SDIOC_SW_RST_ALL)) + +#define IS_SDIOC_OUTPUT_CLK_FREQ(x) \ +( ((x) == SDIOC_OUTPUT_CLK_FREQ_400K) || \ + ((x) == SDIOC_OUTPUT_CLK_FREQ_25M) || \ + ((x) == SDIOC_OUTPUT_CLK_FREQ_26M) || \ + ((x) == SDIOC_OUTPUT_CLK_FREQ_50M) || \ + ((x) == SDIOC_OUTPUT_CLK_FREQ_52M)) + +#define IS_SDIOC_GET_HOST_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_HOST_FLAG_ALL) == SDIOC_HOST_FLAG_ALL)) + +#define IS_SDIOC_GET_INT_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_INT_FLAG_ALL) == SDIOC_INT_FLAG_ALL)) + +#define IS_SDIOC_CLR_INT_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_INT_FLAG_CLR_ALL) == SDIOC_INT_FLAG_CLR_ALL)) + +#define IS_SDIOC_INT(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_INT_ALL) == SDIOC_INT_ALL)) + +#define IS_SDIOC_AUTO_CMD_ERR_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_AUTO_CMD_ERR_FLAG_ALL) == SDIOC_AUTO_CMD_ERR_FLAG_ALL)) + +#define IS_SDIOC_FORCE_AUTO_CMD_ERR(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_FORCE_AUTO_CMD_ERR_ALL) == SDIOC_FORCE_AUTO_CMD_ERR_ALL)) + +#define IS_SDIOC_FORCE_ERR_INT(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_FORCE_ERR_INT_ALL) == SDIOC_FORCE_ERR_INT_ALL)) + +#define IS_SDIOC_RESP_TYPE(x) \ +( ((x) == SDIOC_RESP_TYPE_NO) || \ + ((x) == SDIOC_RESP_TYPE_R2) || \ + ((x) == SDIOC_RESP_TYPE_R3_R4) || \ + ((x) == SDIOC_RESP_TYPE_R1_R5_R6_R7) || \ + ((x) == SDIOC_RESP_TYPE_R1B_R5B)) + +#define IS_SDIOC_CMD_INDEX(x) ((x) < 0x40U) + +#define IS_SDIOC_BLOCK_SIZE(x) (((x) >= 1U) && ((x) <= 512U)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup SDIOC_Global_Functions SDIOC Global Functions + * @{ + */ + +/** + * @brief Wait for command response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32CheckFlag Check flags + * This parameter can be one or any combination the following values: + * @arg SDIOC_INT_FLAG_CC: Command Complete status + * @arg SDIOC_INT_FLAG_CIE: Command Index error status + * @arg SDIOC_INT_FLAG_CEBE: Command End Bit error status + * @arg SDIOC_INT_FLAG_CCE: Command CRC error status + * @arg SDIOC_INT_FLAG_CTOE: Command Timeout error status + * @param [in] u32Timeout Timeout time(ms) for waiting SDIOC + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_WaitResponse(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32CheckFlag, + uint32_t u32Timeout, uint32_t *pu32ErrStatus) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + uint32_t u32Temp; + + *pu32ErrStatus = 0UL; + /* The u32Timeout is expressed in ms */ + u32Count = u32Timeout * (HCLK_VALUE / 20000UL); + while (RESET == SDIOC_GetIntStatus(SDIOCx, u32CheckFlag)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + if (LL_OK == i32Ret) { + i32Ret = LL_ERR; + u32Temp = CLR_REG32_BIT(u32CheckFlag, SDIOC_INT_FLAG_CC); + if (RESET == SDIOC_GetIntStatus(SDIOCx, u32Temp)) { + /* No error flag set */ + *pu32ErrStatus = SDMMC_ERR_NONE; + SDIOC_ClearIntStatus(SDIOCx, SDIOC_INT_STATIC_FLAGS); + i32Ret = LL_OK; + } else if ((RESET != SDIOC_GetIntStatus(SDIOCx, SDIOC_INT_FLAG_CIE)) && + (SDIOC_INT_FLAG_CIE == (u32CheckFlag & SDIOC_INT_FLAG_CIE))) { + *pu32ErrStatus = SDMMC_ERR_CMD_INDEX; + SDIOC_ClearIntStatus(SDIOCx, SDIOC_INT_FLAG_CIE); + } else if ((RESET != SDIOC_GetIntStatus(SDIOCx, SDIOC_INT_FLAG_CEBE)) && + (SDIOC_INT_FLAG_CEBE == (u32CheckFlag & SDIOC_INT_FLAG_CEBE))) { + *pu32ErrStatus = SDMMC_ERR_CMD_STOP_BIT; + SDIOC_ClearIntStatus(SDIOCx, SDIOC_INT_FLAG_CEBE); + } else if ((RESET != SDIOC_GetIntStatus(SDIOCx, SDIOC_INT_FLAG_CCE)) && + (SDIOC_INT_FLAG_CCE == (u32CheckFlag & SDIOC_INT_FLAG_CCE))) { + *pu32ErrStatus = SDMMC_ERR_CMD_CRC_FAIL; + SDIOC_ClearIntStatus(SDIOCx, SDIOC_INT_FLAG_CCE); + } else { + *pu32ErrStatus = SDMMC_ERR_CMD_TIMEOUT; + SDIOC_ClearIntStatus(SDIOCx, SDIOC_INT_FLAG_CTOE); + } + } + + return i32Ret; +} + +/** + * @brief Checks for error conditions for no response command. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdError(CM_SDIOC_TypeDef *SDIOCx) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* The SDMMC_CMD_TIMEOUT is expressed in ms */ + u32Count = SDMMC_CMD_TIMEOUT * (HCLK_VALUE / 20000UL); + while (RESET == SDIOC_GetIntStatus(SDIOCx, SDIOC_INT_FLAG_CC)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + if (LL_OK == i32Ret) { + SDIOC_ClearIntStatus(SDIOCx, SDIOC_INT_STATIC_FLAGS); + } + + return i32Ret; +} + +/** + * @brief Checks for error conditions for R1 response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Timeout Timeout time(ms) for waiting SDIOC + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdResp1(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Timeout, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + uint32_t u32RespVal; + + i32Ret = SDMMC_WaitResponse(SDIOCx, (SDIOC_INT_FLAG_CC | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | + SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE), u32Timeout, pu32ErrStatus); + if (LL_OK == i32Ret) { + /* Fetch has received a response. */ + (void)SDIOC_GetResponse(SDIOCx, SDIOC_RESP_REG_BIT0_31, &u32RespVal); + if (0UL != (u32RespVal & SDMMC_ERR_BITS_MASK)) { + *pu32ErrStatus = u32RespVal & SDMMC_ERR_BITS_MASK; + i32Ret = LL_ERR; + } + } + + return i32Ret; +} + +/** + * @brief Checks for error conditions for R1 response with busy. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Timeout Timeout time(ms) for waiting SDIOC + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdResp1Busy(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Timeout, uint32_t *pu32ErrStatus) +{ + __IO uint32_t u32Count; + int32_t i32Ret; + uint32_t u32RespVal; + + i32Ret = SDMMC_WaitResponse(SDIOCx, (SDIOC_INT_FLAG_CC | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | + SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE), u32Timeout, pu32ErrStatus); + if (LL_OK == i32Ret) { + /* Fetch has received a response. */ + (void)SDIOC_GetResponse(SDIOCx, SDIOC_RESP_REG_BIT0_31, &u32RespVal); + if (0UL != (u32RespVal & SDMMC_ERR_BITS_MASK)) { + *pu32ErrStatus = u32RespVal & SDMMC_ERR_BITS_MASK; + i32Ret = LL_ERR; + } else { + /* Wait for busy status to release */ + u32Count = u32Timeout * (HCLK_VALUE / 20000UL); + while (RESET == SDIOC_GetHostStatus(SDIOCx, SDIOC_HOST_FLAG_DATL_D0)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + } + } + + return i32Ret; +} + +/** + * @brief Checks for error conditions for R2(CID or CSD) response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdResp2(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + return SDMMC_WaitResponse(SDIOCx, (SDIOC_INT_FLAG_CC | SDIOC_INT_FLAG_CEBE | SDIOC_INT_FLAG_CCE | + SDIOC_INT_FLAG_CTOE), SDMMC_CMD_TIMEOUT, pu32ErrStatus); +} + +/** + * @brief Checks for error conditions for R3(OCR) response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdResp3(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + return SDMMC_WaitResponse(SDIOCx, (SDIOC_INT_FLAG_CC | SDIOC_INT_FLAG_CEBE | SDIOC_INT_FLAG_CTOE), + SDMMC_CMD_TIMEOUT, pu32ErrStatus); +} + +/** + * @brief Checks for error conditions for R4 response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdResp4(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + return SDMMC_WaitResponse(SDIOCx, (SDIOC_INT_FLAG_CC | SDIOC_INT_FLAG_CEBE | SDIOC_INT_FLAG_CCE | + SDIOC_INT_FLAG_CTOE), SDMMC_CMD_TIMEOUT, pu32ErrStatus); +} + +/** + * @brief Checks for error conditions for R5 response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdResp5(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + return SDMMC_WaitResponse(SDIOCx, (SDIOC_INT_FLAG_CC | SDIOC_INT_FLAG_CEBE | SDIOC_INT_FLAG_CCE | + SDIOC_INT_FLAG_CTOE), SDMMC_CMD_TIMEOUT, pu32ErrStatus); +} + +/** + * @brief Checks for error conditions for R6(RCA) response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu16RCA Pointer to a value of device RCA + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdResp6(CM_SDIOC_TypeDef *SDIOCx, uint16_t *pu16RCA, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + uint32_t u32RespVal; + + i32Ret = SDMMC_WaitResponse(SDIOCx, (SDIOC_INT_FLAG_CC | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | + SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE), SDMMC_CMD_TIMEOUT, pu32ErrStatus); + if (LL_OK == i32Ret) { + i32Ret = LL_ERR; + /* Fetch has received a response. */ + (void)SDIOC_GetResponse(SDIOCx, SDIOC_RESP_REG_BIT0_31, &u32RespVal); + if (0UL == (u32RespVal & (SDMMC_R6_GEN_UNKNOWN_ERR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAIL))) { + i32Ret = LL_OK; + *pu16RCA = (uint16_t)(u32RespVal >> 16U); + } else if (SDMMC_R6_GEN_UNKNOWN_ERR == (u32RespVal & SDMMC_R6_GEN_UNKNOWN_ERR)) { + *pu32ErrStatus = SDMMC_ERR_GENERAL_UNKNOWN_ERR; + } else if (SDMMC_R6_ILLEGAL_CMD == (u32RespVal & SDMMC_R6_ILLEGAL_CMD)) { + *pu32ErrStatus = SDMMC_ERR_ILLEGAL_CMD; + } else { + *pu32ErrStatus = SDMMC_ERR_COM_CRC_FAILED; + } + } + + return i32Ret; +} + +/** + * @brief Checks for error conditions for R7 response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdResp7(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + return SDMMC_WaitResponse(SDIOCx, (SDIOC_INT_FLAG_CC | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | + SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE), SDMMC_CMD_TIMEOUT, pu32ErrStatus); +} + +/** + * @brief De-Initialize SDIOC. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @retval int32_t: + * - LL_OK: SDIOC De-Initialize success + * - LL_ERR_TIMEOUT: Software reset timeout + */ +int32_t SDIOC_DeInit(CM_SDIOC_TypeDef *SDIOCx) +{ + return SDIOC_SWReset(SDIOCx, SDIOC_SW_RST_ALL); +} + +/** + * @brief Initialize SDIOC. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] pstcSdiocInit Pointer to a @ref stc_sdioc_init_t structure + * @retval int32_t: + * - LL_OK: SDIOC Initialize success + * - LL_ERR_INVD_PARAM: pstcSdiocInit == NULL + */ +int32_t SDIOC_Init(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_init_t *pstcSdiocInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcSdiocInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_MD(pstcSdiocInit->u32Mode)); + DDL_ASSERT(IS_SDIOC_CARD_DETECT_WAY(pstcSdiocInit->u8CardDetect)); + DDL_ASSERT(IS_SDIOC_SPEED_MD(pstcSdiocInit->u8SpeedMode)); + DDL_ASSERT(IS_SDIOC_BUS_WIDTH(pstcSdiocInit->u8BusWidth)); + DDL_ASSERT(IS_SDIOC_CLK_DIV(pstcSdiocInit->u16ClockDiv)); + + /* Set the SDIOC mode */ + if (CM_SDIOC1 == SDIOCx) { + WRITE_REG32(bCM_PERIC->SDIOC_SYCTLREG_b.SELMMC1, pstcSdiocInit->u32Mode); + } else { + WRITE_REG32(bCM_PERIC->SDIOC_SYCTLREG_b.SELMMC2, pstcSdiocInit->u32Mode); + } + /* Set the SDIOC clock control value */ + WRITE_REG16(SDIOCx->CLKCON, (pstcSdiocInit->u16ClockDiv | SDIOC_CLKCON_ICE | SDIOC_CLKCON_CE)); + /* Set the SDIOC host control value */ + WRITE_REG8(SDIOCx->HOSTCON, (pstcSdiocInit->u8CardDetect | pstcSdiocInit->u8BusWidth | + pstcSdiocInit->u8SpeedMode)); + /* Enable normal interrupt status */ + WRITE_REG16(SDIOCx->NORINTSTEN, SDIOC_NORINTSGEN_CLR_MASK); + /* Enable error interrupt status */ + WRITE_REG16(SDIOCx->ERRINTSTEN, SDIOC_ERRINTSGEN_CLR_MASK); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_sdioc_init_t to default values. + * @param [out] pstcSdiocInit Pointer to a @ref stc_sdioc_init_t structure + * @retval int32_t: + * - LL_OK: Structure Initialize success + * - LL_ERR_INVD_PARAM: pstcSdiocInit == NULL + */ +int32_t SDIOC_StructInit(stc_sdioc_init_t *pstcSdiocInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcSdiocInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcSdiocInit->u32Mode = SDIOC_MD_SD; + pstcSdiocInit->u8CardDetect = SDIOC_CARD_DETECT_CD_PIN_LVL; + pstcSdiocInit->u8SpeedMode = SDIOC_SPEED_MD_NORMAL; + pstcSdiocInit->u8BusWidth = SDIOC_BUS_WIDTH_1BIT; + pstcSdiocInit->u16ClockDiv = SDIOC_CLK_DIV1; + } + + return i32Ret; +} + +/** + * @brief Set software reset. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u8Type Software reset type + * This parameter can be one of the following values: + * @arg SDIOC_SW_RST_DATA_LINE: Only part of data circuit is reset + * @arg SDIOC_SW_RST_CMD_LINE: Only part of command circuit is reset + * @arg SDIOC_SW_RST_ALL: Reset the entire Host Controller except for the card detection circuit + * @retval int32_t: + * - LL_OK: Software reset success + * - LL_ERR_TIMEOUT: Software reset timeout + */ +int32_t SDIOC_SWReset(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Type) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32Count; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_SW_RST_TYPE(u8Type)); + + WRITE_REG8(SDIOCx->SFTRST, u8Type); + /* Wait for reset finish */ + u32Count = SDIOC_SW_RST_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0U != READ_REG8_BIT(SDIOCx->SFTRST, u8Type)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + return i32Ret; +} + +/** + * @brief Enable or disable power. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_PowerCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG8_BIT(SDIOCx->PWRCON, SDIOC_PWRCON_PWON); + } else { + CLR_REG8_BIT(SDIOCx->PWRCON, SDIOC_PWRCON_PWON); + } +} + +/** + * @brief Get power state. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @retval An @ref en_functional_state_t enumeration value. + * - DISABLE: Power off or SDIOCx == NULL + * - ENABLE: Power on + */ +en_functional_state_t SDIOC_GetPowerState(const CM_SDIOC_TypeDef *SDIOCx) +{ + en_functional_state_t enPowerSta = DISABLE; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + if (0U != (READ_REG8_BIT(SDIOCx->PWRCON, SDIOC_PWRCON_PWON))) { + enPowerSta = ENABLE; + } + + return enPowerSta; +} + +/** + * @brief Get SDIOC work mode. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @retval uint32_t value: + * - SDIOC_MD_SD: SDIOCx selects SD mode + * - SDIOC_MD_MMC: SDIOCx selects MMC mode + */ +uint32_t SDIOC_GetMode(const CM_SDIOC_TypeDef *SDIOCx) +{ + uint32_t u32SdMode; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + if (CM_SDIOC1 == SDIOCx) { + u32Temp = PERIC_SDIOC_SYCTLREG_SELMMC1; + } else { + u32Temp = PERIC_SDIOC_SYCTLREG_SELMMC2; + } + u32SdMode = READ_REG32_BIT(CM_PERIC->SDIOC_SYCTLREG, u32Temp); + if (0UL != u32SdMode) { /* MMC mode */ + u32SdMode = SDIOC_MD_MMC; + } else { + u32SdMode = SDIOC_MD_SD; + } + + return u32SdMode; +} + +/** + * @brief Enable or disable clock output. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_ClockCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG8_BIT(SDIOCx->CLKCON, SDIOC_CLKCON_CE); + } else { + CLR_REG8_BIT(SDIOCx->CLKCON, SDIOC_CLKCON_CE); + } +} + +/** + * @brief Set clock division. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u16Div Clock division + * This parameter can be one of the following values: + * @arg SDIOC_CLK_DIV1: CLK1/1 + * @arg SDIOC_CLK_DIV2: CLK1/2 + * @arg SDIOC_CLK_DIV4: CLK1/4 + * @arg SDIOC_CLK_DIV8: CLK1/8 + * @arg SDIOC_CLK_DIV16: CLK1/16 + * @arg SDIOC_CLK_DIV32: CLK1/32 + * @arg SDIOC_CLK_DIV64: CLK1/64 + * @arg SDIOC_CLK_DIV128: CLK1/128 + * @arg SDIOC_CLK_DIV256: CLK1/256 + * @retval None + */ +void SDIOC_SetClockDiv(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Div) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_CLK_DIV(u16Div)); + + MODIFY_REG16(SDIOCx->CLKCON, SDIOC_CLKCON_FS, u16Div); +} + +/** + * @brief Find the most suitable clock division for the set clock frequency. + * @note More clock values can be set as needed, but the maximum cannot exceed 50MHz. + * @param [in] u32ClockFreq SDIOCx_CK clock frequency + * This parameter can be one of the following values: + * @arg SDIOC_OUTPUT_CLK_FREQ_400K: SDIOC clock: 400KHz + * @arg SDIOC_OUTPUT_CLK_FREQ_25M: SDIOC clock: 25MHz + * @arg SDIOC_OUTPUT_CLK_FREQ_26M: SDIOC clock: 26MHz + * @arg SDIOC_OUTPUT_CLK_FREQ_50M: SDIOC clock: 50MHz + * @arg SDIOC_OUTPUT_CLK_FREQ_52M: SDIOC clock: 52MHz + * @arg Any other value + * @param [out] pu16Div Pointer to a value of clock division + * @retval int32_t: + * - LL_OK: SDIOC Initialize success + * - LL_ERR: The Bus clock frequency is too high + * - LL_ERR_INVD_PARAM: pu16Div == NULL or 0UL == u32ClockFreq + */ +int32_t SDIOC_GetOptimumClockDiv(uint32_t u32ClockFreq, uint16_t *pu16Div) +{ + int32_t i32Ret = LL_OK; + uint32_t u32BusClock; + uint32_t u32ClockDiv; + uint32_t u32Temp; + + if ((NULL == pu16Div) || (0UL == u32ClockFreq)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Get BUS frequency */ + u32BusClock = SystemCoreClock / (0x01UL << (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_EXCKS) >> CMU_SCFGR_EXCKS_POS)); + u32ClockDiv = u32BusClock / u32ClockFreq; + if (0UL != (u32BusClock % u32ClockFreq)) { + u32ClockDiv++; + } + /* Check the effectiveness of clock division */ + if (u32ClockDiv > 256U) { /* Maximum division is 256 */ + i32Ret = LL_ERR; + } else { + if (1U == u32ClockDiv) { + *pu16Div = SDIOC_CLK_DIV1; + } else { + for (u32Temp = SDIOC_CLK_DIV2; u32Temp <= SDIOC_CLK_DIV256; u32Temp <<= 1U) { + if (u32ClockDiv <= (u32Temp >> (SDIOC_CLKCON_FS_POS - 1U))) { + break; + } + } + *pu16Div = (uint16_t)u32Temp; + } + } + } + + return i32Ret; +} + +/** + * @brief Verify the validity of the clock division. + * @param [in] u32Mode SDIOC work mode + * This parameter can be one of the following values: + * @arg SDIOC_MD_SD: SDIOCx selects SD mode + * @arg SDIOC_MD_MMC: SDIOCx selects MMC mode + * @param [in] u8SpeedMode Speed mode + * This parameter can be one of the following values: + * @arg SDIOC_SPEED_MD_NORMAL: Normal speed mode + * @arg SDIOC_SPEED_MD_HIGH: High speed mode + * @param [in] u16ClockDiv Clock division + * This parameter can be one of the following values: + * @arg SDIOC_CLK_DIV1: CLK1/1 + * @arg SDIOC_CLK_DIV2: CLK1/2 + * @arg SDIOC_CLK_DIV4: CLK1/4 + * @arg SDIOC_CLK_DIV8: CLK1/8 + * @arg SDIOC_CLK_DIV16: CLK1/16 + * @arg SDIOC_CLK_DIV32: CLK1/32 + * @arg SDIOC_CLK_DIV64: CLK1/64 + * @arg SDIOC_CLK_DIV128: CLK1/128 + * @arg SDIOC_CLK_DIV256: CLK1/256 + * @retval int32_t: + * - LL_OK: The clock division is valid + * - LL_ERR: The Bus clock frequency is too high + */ +int32_t SDIOC_VerifyClockDiv(uint32_t u32Mode, uint8_t u8SpeedMode, uint16_t u16ClockDiv) +{ + int32_t i32Ret = LL_OK; + uint32_t u32BusClock; + uint32_t u32ClockFreq; + uint32_t u32MaxFreq; + uint32_t u32DivValue; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_MD(u32Mode)); + DDL_ASSERT(IS_SDIOC_SPEED_MD(u8SpeedMode)); + DDL_ASSERT(IS_SDIOC_CLK_DIV(u16ClockDiv)); + + /* Get Bus frequency */ + u32BusClock = SystemCoreClock / (0x01UL << (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_EXCKS) >> CMU_SCFGR_EXCKS_POS)); + u32DivValue = ((uint32_t)u16ClockDiv >> (SDIOC_CLKCON_FS_POS - 1U)); + if (0UL == u32DivValue) { + u32ClockFreq = u32BusClock; + } else { + u32ClockFreq = u32BusClock / u32DivValue; + } + + if (SDIOC_SPEED_MD_NORMAL == u8SpeedMode) { + if (SDIOC_MD_SD != u32Mode) { /* MMC mode */ + u32MaxFreq = SDIOC_OUTPUT_CLK_FREQ_26M; + } else { + u32MaxFreq = SDIOC_OUTPUT_CLK_FREQ_25M; + } + } else { + if (SDIOC_MD_SD != u32Mode) { /* MMC mode */ + u32MaxFreq = SDIOC_OUTPUT_CLK_FREQ_52M; + } else { + u32MaxFreq = SDIOC_OUTPUT_CLK_FREQ_50M; + } + } + if (u32ClockFreq > u32MaxFreq) { + i32Ret = LL_ERR; + } + + return i32Ret; +} + +/** + * @brief Get device insert status. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SDIOC_GetInsertStatus(const CM_SDIOC_TypeDef *SDIOCx) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + if (0UL != (READ_REG32_BIT(SDIOCx->PSTAT, SDIOC_PSTAT_CSS))) { + if (0UL != (READ_REG32_BIT(SDIOCx->PSTAT, SDIOC_PSTAT_CIN))) { + enFlagSta = SET; + } + } + + return enFlagSta; +} + +/** + * @brief Set speed mode. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u8SpeedMode Speed mode + * This parameter can be one of the following values: + * @arg SDIOC_SPEED_MD_NORMAL: Normal speed mode + * @arg SDIOC_SPEED_MD_HIGH: High speed mode + * @retval None + */ +void SDIOC_SetSpeedMode(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8SpeedMode) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_SPEED_MD(u8SpeedMode)); + + if (SDIOC_SPEED_MD_NORMAL != u8SpeedMode) { + SET_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_HSEN); + } else { + CLR_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_HSEN); + } +} + +/** + * @brief Set bus width. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u8BusWidth Bus width + * This parameter can be one of the following values: + * @arg SDIOC_BUS_WIDTH_1BIT: The Bus width is 1 bit + * @arg SDIOC_BUS_WIDTH_4BIT: The Bus width is 4 bit + * @arg SDIOC_BUS_WIDTH_8BIT: The Bus width is 8 bit + * @retval None + */ +void SDIOC_SetBusWidth(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8BusWidth) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_BUS_WIDTH(u8BusWidth)); + + MODIFY_REG8(SDIOCx->HOSTCON, (SDIOC_HOSTCON_DW | SDIOC_HOSTCON_EXDW), u8BusWidth); +} + +/** + * @brief Set card detect line select. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u8Src Card detect source + * This parameter can be one of the following values: + * @arg SDIOC_CARD_DETECT_CD_PIN_LVL: SDIOCx_CD(x=1~2) line is selected (for normal use) + * @arg SDIOC_CARD_DETECT_TEST_SIGNAL: The Card Detect Test Level is selected(for test purpose) + * @retval None + */ +void SDIOC_SetCardDetectSrc(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Src) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_CARD_DETECT_WAY(u8Src)); + + if (SDIOC_CARD_DETECT_CD_PIN_LVL != u8Src) { + SET_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_CDSS); + } else { + CLR_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_CDSS); + } +} + +/** + * @brief Set card detect test level. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u8Level Card test level + * This parameter can be one of the following values: + * @arg SDIOC_CARD_DETECT_TEST_LVL_LOW: Card identification test signal is low level (with device insertion) + * @arg SDIOC_CARD_DETECT_TEST_LVL_HIGH: Card identification test signal is high level (no device insertion) + * @retval None + */ +void SDIOC_SetCardDetectTestLevel(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Level) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_CARD_DETECT_TEST_LEVEL(u8Level)); + + if (SDIOC_CARD_DETECT_TEST_LVL_LOW != u8Level) { + SET_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_CDTL); + } else { + CLR_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_CDTL); + } +} + +/** + * @brief Configure the SDIOCx command parameters. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] pstcCmdConfig Pointer to a @ref stc_sdioc_cmd_config_t structure + * @retval int32_t: + * - LL_OK: Configure SDIOCx command parameters success + * - LL_ERR_INVD_PARAM: pstcCmdConfig == NULL + */ +int32_t SDIOC_SendCommand(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_cmd_config_t *pstcCmdConfig) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *pu32Temp; + + if (NULL == pstcCmdConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_CMD_INDEX(pstcCmdConfig->u16CmdIndex)); + DDL_ASSERT(IS_SDIOC_CMD_TYPE(pstcCmdConfig->u16CmdType)); + DDL_ASSERT(IS_SDIOC_DATA_LINE(pstcCmdConfig->u16DataLine)); + DDL_ASSERT(IS_SDIOC_RESP_TYPE(pstcCmdConfig->u16ResponseType)); + + /* Set the SDIOC Command parameters value */ + pu32Temp = SDIOC_ARG_ADDR(SDIOCx); + WRITE_REG32(*pu32Temp, pstcCmdConfig->u32Argument); + /* Set the SDIOC Command controller value */ + WRITE_REG16(SDIOCx->CMD, ((uint16_t)(pstcCmdConfig->u16CmdIndex << SDIOC_CMD_IDX_POS) | + pstcCmdConfig->u16CmdType | pstcCmdConfig->u16DataLine | + pstcCmdConfig->u16ResponseType)); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_sdioc_cmd_config_t to default values. + * @param [out] pstcCmdConfig Pointer to a @ref stc_sdioc_cmd_config_t structure + * @retval int32_t: + * - LL_OK: Structure Initialize success + * - LL_ERR_INVD_PARAM: pstcDataConfig == NULL + */ +int32_t SDIOC_CommandStructInit(stc_sdioc_cmd_config_t *pstcCmdConfig) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcCmdConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcCmdConfig->u32Argument = 0U; + pstcCmdConfig->u16CmdIndex = 0U; + pstcCmdConfig->u16CmdType = SDIOC_CMD_TYPE_NORMAL; + pstcCmdConfig->u16DataLine = SDIOC_DATA_LINE_DISABLE; + pstcCmdConfig->u16ResponseType = SDIOC_RESP_TYPE_NO; + } + + return i32Ret; +} + +/** + * @brief Get the response received from the card for the last command + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u8Reg SDIOC response register + * This parameter can be one of the following values: + * @arg SDIOC_RESP_REG_BIT0_31: Command Response Register 0-31bit + * @arg SDIOC_RESP_REG_BIT32_63: Command Response Register 32-63bit + * @arg SDIOC_RESP_REG_BIT64_95: Command Response Register 64-95bit + * @arg SDIOC_RESP_REG_BIT96_127: Command Response Register 96-127bit + * @param [out] pu32Value Pointer to a Response value + * @retval int32_t: + * - LL_OK: Get response success + * - LL_ERR_INVD_PARAM: pu32Value == NULL + */ +int32_t SDIOC_GetResponse(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Reg, uint32_t *pu32Value) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pu32Value) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_RESP_REG(u8Reg)); + + *pu32Value = READ_REG32(*SDIOC_RESP_ADDR(SDIOCx, u8Reg)); + } + + return i32Ret; +} + +/** + * @brief Configure the SDIOCx data parameters. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] pstcDataConfig Pointer to a @ref stc_sdioc_data_config_t structure + * @retval int32_t: + * - LL_OK: Configure SDIOCx data parameters success + * - LL_ERR_INVD_PARAM: pstcDataConfig == NULL + */ +int32_t SDIOC_ConfigData(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_data_config_t *pstcDataConfig) +{ + int32_t i32Ret = LL_OK; + uint16_t u16BlkCnt; + + if (NULL == pstcDataConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_BLOCK_SIZE(pstcDataConfig->u16BlockSize)); + DDL_ASSERT(IS_SDIOC_TRANS_DIR(pstcDataConfig->u16TransDir)); + DDL_ASSERT(IS_SDIOC_AUTO_SEND_CMD12(pstcDataConfig->u16AutoCmd12)); + DDL_ASSERT(IS_SDIOC_TRANS_MD(pstcDataConfig->u16TransMode)); + DDL_ASSERT(IS_SDIOC_DATA_TIMEOUT_TIME(pstcDataConfig->u16DataTimeout)); + + if (SDIOC_TRANS_MD_STOP_MULTI == pstcDataConfig->u16TransMode) { + u16BlkCnt = 0U; + } else { + u16BlkCnt = pstcDataConfig->u16BlockCount; + } + /* Set the SDIOC Data Transfer Timeout value */ + WRITE_REG8(SDIOCx->TOUTCON, pstcDataConfig->u16DataTimeout); + /* Set the SDIOC Block Count value */ + WRITE_REG16(SDIOCx->BLKSIZE, pstcDataConfig->u16BlockSize); + /* Set the SDIOC Block Size value */ + WRITE_REG16(SDIOCx->BLKCNT, u16BlkCnt); + /* Set the SDIOC Data Transfer Mode */ + WRITE_REG16(SDIOCx->TRANSMODE, ((pstcDataConfig->u16TransDir | pstcDataConfig->u16AutoCmd12 | + pstcDataConfig->u16TransMode) & 0xFFU)); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_sdioc_data_config_t to default values. + * @param [out] pstcDataConfig Pointer to a @ref stc_sdioc_data_config_t structure + * @retval int32_t: + * - LL_OK: Structure Initialize success + * - LL_ERR_INVD_PARAM: pstcDataConfig == NULL + */ +int32_t SDIOC_DataStructInit(stc_sdioc_data_config_t *pstcDataConfig) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDataConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDataConfig->u16BlockSize = 512U; + pstcDataConfig->u16BlockCount = 0U; + pstcDataConfig->u16TransDir = SDIOC_TRANS_DIR_TO_CARD; + pstcDataConfig->u16AutoCmd12 = SDIOC_AUTO_SEND_CMD12_DISABLE; + pstcDataConfig->u16TransMode = SDIOC_TRANS_MD_SINGLE; + pstcDataConfig->u16DataTimeout = SDIOC_DATA_TIMEOUT_CLK_2E13; + } + + return i32Ret; +} + +/** + * @brief Read data from SDIOC FIFO. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] au8Data Pointer to the buffer + * @param [in] u32Len Data length + * @retval int32_t: + * - LL_OK: Read data success + * - LL_ERR_INVD_PARAM: NULL == au8Data or (u32Len % 4U) != 0 + */ +int32_t SDIOC_ReadBuffer(CM_SDIOC_TypeDef *SDIOCx, uint8_t au8Data[], uint32_t u32Len) +{ + int32_t i32Ret = LL_OK; + uint32_t i; + uint32_t u32Temp; + __IO uint32_t *BUF_REG; + + if ((NULL == au8Data) || (0U != (u32Len % 4U))) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + BUF_REG = SDIOC_BUF_ADDR(SDIOCx); + for (i = 0U; i < u32Len; i += 4U) { + u32Temp = READ_REG32(*BUF_REG); + au8Data[i] = (uint8_t)(u32Temp & 0xFFUL); + au8Data[i + 1U] = (uint8_t)((u32Temp >> 8U) & 0xFFUL); + au8Data[i + 2U] = (uint8_t)((u32Temp >> 16U) & 0xFFUL); + au8Data[i + 3U] = (uint8_t)((u32Temp >> 24U) & 0xFFUL); + } + } + + return i32Ret; +} + +/** + * @brief Write data to SDIOC FIFO. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] au8Data Pointer to the buffer + * @param [in] u32Len Data length + * @retval int32_t: + * - LL_OK: Write data success + * - LL_ERR_INVD_PARAM: NULL == au8Data or (u32Len % 4U) != 0 + */ +int32_t SDIOC_WriteBuffer(CM_SDIOC_TypeDef *SDIOCx, const uint8_t au8Data[], uint32_t u32Len) +{ + int32_t i32Ret = LL_OK; + uint32_t i; + uint32_t u32Temp; + __IO uint32_t *BUF_REG; + + if ((NULL == au8Data) || (0U != (u32Len % 4U))) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + BUF_REG = SDIOC_BUF_ADDR(SDIOCx); + for (i = 0U; i < u32Len; i += 4U) { + u32Temp = ((uint32_t)au8Data[i + 3U] << 24U) | ((uint32_t)au8Data[i + 2U] << 16U) | + ((uint32_t)au8Data[i + 1U] << 8U) | au8Data[i]; + WRITE_REG32(*BUF_REG, u32Temp); + } + } + + return i32Ret; +} + +/** + * @brief Enable or disable block gap stop. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_BlockGapStopCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_SABGR); + } else { + CLR_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_SABGR); + } +} + +/** + * @brief Restart data transfer. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @retval None + */ +void SDIOC_RestartTrans(CM_SDIOC_TypeDef *SDIOCx) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + SET_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_CR); +} + +/** + * @brief Enable or disable read wait. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_ReadWaitCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_RWC); + } else { + CLR_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_RWC); + } +} + +/** + * @brief Enable or disable data block gap interrupt. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_BlockGapIntCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_IABG); + } else { + CLR_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_IABG); + } +} + +/** + * @brief Enable or disable interrupt. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32IntType Normal and error interrupts source + * This parameter can be one or any combination of the following values: + * @arg SDIOC_INT_CINTSEN: Card interrupt + * @arg SDIOC_INT_CRMSEN: Card Removal interrupt + * @arg SDIOC_INT_CISTSEN: Card Insertion interrupt + * @arg SDIOC_INT_BRRSEN: Buffer Read Ready interrupt + * @arg SDIOC_INT_BWRSEN: Buffer Write Ready interrupt + * @arg SDIOC_INT_BGESEN: Block Gap Event interrupt + * @arg SDIOC_INT_TCSEN: Transfer Complete interrupt + * @arg SDIOC_INT_CCSEN: Command Complete interrupt + * @arg SDIOC_INT_ACESEN: Auto CMD12 error interrupt + * @arg SDIOC_INT_DEBESEN: Data End Bit error interrupt + * @arg SDIOC_INT_DCESEN: Data CRC error interrupt + * @arg SDIOC_INT_DTOESEN: Data Timeout error interrupt + * @arg SDIOC_INT_CIESEN: Command Index error interrupt + * @arg SDIOC_INT_CEBESEN: Command End Bit error interrupt + * @arg SDIOC_INT_CCESEN: Command CRC error interrupt + * @arg SDIOC_INT_CTOESEN: Command Timeout error interrupt + * @arg SDIOC_INT_ALL: All of the above + * @arg SDIOC_NORMAL_INT_ALL: All of the normal interrupt + * @arg SDIOC_ERR_INT_ALL: All of the error interrupt + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_IntCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint16_t u16NormalInt; + uint16_t u16ErrorInt; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u16NormalInt = (uint16_t)(u32IntType & 0xFFFFU); + u16ErrorInt = (uint16_t)(u32IntType >> 16U); + if (DISABLE != enNewState) { + if (0U != u16NormalInt) { + SET_REG16_BIT(SDIOCx->NORINTSGEN, u16NormalInt); + } + if (0U != u16ErrorInt) { + SET_REG16_BIT(SDIOCx->ERRINTSGEN, u16ErrorInt); + } + } else { + if (0U != u16NormalInt) { + CLR_REG16_BIT(SDIOCx->NORINTSGEN, u16NormalInt); + } + if (0U != u16ErrorInt) { + CLR_REG16_BIT(SDIOCx->ERRINTSGEN, u16ErrorInt); + } + } +} + +/** + * @brief Get interrupt enable state. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32IntType Normal and error interrupts source + * This parameter can be one or any combination of the following values: + * @arg SDIOC_INT_CINTSEN: Card interrupt + * @arg SDIOC_INT_CRMSEN: Card Removal interrupt + * @arg SDIOC_INT_CISTSEN: Card Insertion interrupt + * @arg SDIOC_INT_BRRSEN: Buffer Read Ready interrupt + * @arg SDIOC_INT_BWRSEN: Buffer Write Ready interrupt + * @arg SDIOC_INT_BGESEN: Block Gap Event interrupt + * @arg SDIOC_INT_TCSEN: Transfer Complete interrupt + * @arg SDIOC_INT_CCSEN: Command Complete interrupt + * @arg SDIOC_INT_ACESEN: Auto CMD12 error interrupt + * @arg SDIOC_INT_DEBESEN: Data End Bit error interrupt + * @arg SDIOC_INT_DCESEN: Data CRC error interrupt + * @arg SDIOC_INT_DTOESEN: Data Timeout error interrupt + * @arg SDIOC_INT_CIESEN: Command Index error interrupt + * @arg SDIOC_INT_CEBESEN: Command End Bit error interrupt + * @arg SDIOC_INT_CCESEN: Command CRC error interrupt + * @arg SDIOC_INT_CTOESEN: Command Timeout error interrupt + * @arg SDIOC_INT_ALL: All of the above + * @arg SDIOC_NORMAL_INT_ALL: All of the normal interrupt + * @arg SDIOC_ERR_INT_ALL: All of the error interrupt + * @retval An @ref en_functional_state_t enumeration value. + * - ENABLE: The interrupt is enable + * - DISABLE: The interrupt is disable + */ +en_functional_state_t SDIOC_GetIntEnableState(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType) +{ + uint16_t u16NormalInt; + uint16_t u16ErrorInt; + en_functional_state_t enIntSta = DISABLE; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_INT(u32IntType)); + + u16NormalInt = (uint16_t)(u32IntType & 0xFFFFU); + u16ErrorInt = (uint16_t)(u32IntType >> 16U); + if (0U != u16NormalInt) { + if (0U != (READ_REG16_BIT(SDIOCx->NORINTSGEN, u16NormalInt))) { + enIntSta = ENABLE; + } + } + if ((0U != u16ErrorInt) && (enIntSta != ENABLE)) { + if (0U != (READ_REG16_BIT(SDIOCx->ERRINTSGEN, u16ErrorInt))) { + enIntSta = ENABLE; + } + } + + return enIntSta; +} + +/** + * @brief Get interrupt flag status. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Flag Normal and error interrupts flag + * This parameter can be one or any combination the following values: + * @arg SDIOC_INT_FLAG_EI: Error interrupt flag + * @arg SDIOC_INT_FLAG_CINT: Card interrupt flag + * @arg SDIOC_INT_FLAG_CRM: Card Removal flag + * @arg SDIOC_INT_FLAG_CIST: Card Insertion flag + * @arg SDIOC_INT_FLAG_BRR: Buffer Read Ready flag + * @arg SDIOC_INT_FLAG_BWR: Buffer Write Ready flag + * @arg SDIOC_INT_FLAG_BGE: Block Gap Event flag + * @arg SDIOC_INT_FLAG_TC: Transfer Complete flag + * @arg SDIOC_INT_FLAG_CC: Command Complete flag + * @arg SDIOC_INT_FLAG_ACE: Auto CMD12 error flag + * @arg SDIOC_INT_FLAG_DEBE: Data End Bit error flag + * @arg SDIOC_INT_FLAG_DCE: Data CRC error flag + * @arg SDIOC_INT_FLAG_DTOE: Data Timeout error flag + * @arg SDIOC_INT_FLAG_CIE: Command Index error flag + * @arg SDIOC_INT_FLAG_CEBE: Command End Bit error flag + * @arg SDIOC_INT_FLAG_CCE: Command CRC error flag + * @arg SDIOC_INT_FLAG_CTOE: Command Timeout error flag + * @arg SDIOC_INT_FLAG_ALL: All of the above + * @arg SDIOC_NORMAL_INT_FLAG_ALL: All of the normal interrupt flag + * @arg SDIOC_ERR_INT_FLAG_ALL: All of the error interrupt flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SDIOC_GetIntStatus(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + uint16_t u16NormalFlag; + uint16_t u16ErrorFlag; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_GET_INT_FLAG(u32Flag)); + + u16NormalFlag = (uint16_t)(u32Flag & 0xFFFFU); + u16ErrorFlag = (uint16_t)(u32Flag >> 16U); + if (0U != u16NormalFlag) { + if (0U != (READ_REG16_BIT(SDIOCx->NORINTST, u16NormalFlag))) { + enFlagSta = SET; + } + } + if ((0U != u16ErrorFlag) && (enFlagSta != SET)) { + if (0U != (READ_REG16_BIT(SDIOCx->ERRINTST, u16ErrorFlag))) { + enFlagSta = SET; + } + } + + return enFlagSta; +} + +/** + * @brief Clear interrupt flag status. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Flag Normal and error interrupts flag + * This parameter can be one or any combination of the following values: + * @arg SDIOC_INT_FLAG_CRM: Card Removal flag + * @arg SDIOC_INT_FLAG_CIST: Card Insertion flag + * @arg SDIOC_INT_FLAG_BRR: Buffer Read Ready flag + * @arg SDIOC_INT_FLAG_BWR: Buffer Write Ready flag + * @arg SDIOC_INT_FLAG_BGE: Block Gap Event flag + * @arg SDIOC_INT_FLAG_TC: Transfer Complete flag + * @arg SDIOC_INT_FLAG_CC: Command Complete flag + * @arg SDIOC_INT_FLAG_ACE: Auto CMD12 error flag + * @arg SDIOC_INT_FLAG_DEBE: Data End Bit error flag + * @arg SDIOC_INT_FLAG_DCE: Data CRC error flag + * @arg SDIOC_INT_FLAG_DTOE: Data Timeout error flag + * @arg SDIOC_INT_FLAG_CIE: Command Index error flag + * @arg SDIOC_INT_FLAG_CEBE: Command End Bit error flag + * @arg SDIOC_INT_FLAG_CCE: Command CRC error flag + * @arg SDIOC_INT_FLAG_CTOE: Command Timeout error flag + * @arg SDIOC_INT_FLAG_CLR_ALL: All of the above + * @retval None + */ +void SDIOC_ClearIntStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag) +{ + uint16_t u16NormalFlag; + uint16_t u16ErrorFlag; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_CLR_INT_FLAG(u32Flag)); + + u16NormalFlag = (uint16_t)(u32Flag & 0xFFFFU); + u16ErrorFlag = (uint16_t)(u32Flag >> 16U); + if (0U != u16NormalFlag) { + WRITE_REG16(SDIOCx->NORINTST, u16NormalFlag); + } + if (0U != u16ErrorFlag) { + WRITE_REG16(SDIOCx->ERRINTST, u16ErrorFlag); + } +} + +/** + * @brief Enable or disable interrupt status. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32IntType Normal and error interrupts source + * This parameter can be one or any combination of the following values: + * @arg SDIOC_INT_CINTSEN: Card interrupt + * @arg SDIOC_INT_CRMSEN: Card Removal interrupt + * @arg SDIOC_INT_CISTSEN: Card Insertion interrupt + * @arg SDIOC_INT_BRRSEN: Buffer Read Ready interrupt + * @arg SDIOC_INT_BWRSEN: Buffer Write Ready interrupt + * @arg SDIOC_INT_BGESEN: Block Gap Event interrupt + * @arg SDIOC_INT_TCSEN: Transfer Complete interrupt + * @arg SDIOC_INT_CCSEN: Command Complete interrupt + * @arg SDIOC_INT_ACESEN: Auto CMD12 error interrupt + * @arg SDIOC_INT_DEBESEN: Data End Bit error interrupt + * @arg SDIOC_INT_DCESEN: Data CRC error interrupt + * @arg SDIOC_INT_DTOESEN: Data Timeout error interrupt + * @arg SDIOC_INT_CIESEN: Command Index error interrupt + * @arg SDIOC_INT_CEBESEN: Command End Bit error interrupt + * @arg SDIOC_INT_CCESEN: Command CRC error interrupt + * @arg SDIOC_INT_CTOESEN: Command Timeout error interrupt + * @arg SDIOC_INT_ALL: All of the above + * @arg SDIOC_NORMAL_INT_ALL: All of the normal interrupt + * @arg SDIOC_ERR_INT_ALL: All of the error interrupt + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_IntStatusCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint16_t u16NormalInt; + uint16_t u16ErrorInt; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u16NormalInt = (uint16_t)(u32IntType & 0xFFFFU); + u16ErrorInt = (uint16_t)(u32IntType >> 16U); + if (DISABLE != enNewState) { + if (0U != u16NormalInt) { + SET_REG16_BIT(SDIOCx->NORINTSTEN, u16NormalInt); + } + if (0U != u16ErrorInt) { + SET_REG16_BIT(SDIOCx->ERRINTSTEN, u16ErrorInt); + } + } else { + if (0U != u16NormalInt) { + CLR_REG16_BIT(SDIOCx->NORINTSTEN, u16NormalInt); + } + if (0U != u16ErrorInt) { + CLR_REG16_BIT(SDIOCx->ERRINTSTEN, u16ErrorInt); + } + } +} + +/** + * @brief Get Host status. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Flag Host flag + * This parameter can be one or any combination the following values: + * @arg SDIOC_HOST_FLAG_CMDL: CMD Line Level flag + * @arg SDIOC_HOST_FLAG_DATL: DAT[3:0] Line Level flag + * @arg SDIOC_HOST_FLAG_DATL_D0: DAT[0] Line Level flag + * @arg SDIOC_HOST_FLAG_DATL_D1: DAT[1] Line Level flag + * @arg SDIOC_HOST_FLAG_DATL_D2: DAT[2] Line Level flag + * @arg SDIOC_HOST_FLAG_DATL_D3: DAT[3] Line Level flag + * @arg SDIOC_HOST_FLAG_WPL: Write Protect Line Level flag + * @arg SDIOC_HOST_FLAG_CDL: Card Detect Line Level flag + * @arg SDIOC_HOST_FLAG_CSS: Device Stable flag + * @arg SDIOC_HOST_FLAG_CIN: Device Inserted flag + * @arg SDIOC_HOST_FLAG_BRE: Data buffer full flag + * @arg SDIOC_HOST_FLAG_BWE: Data buffer empty flag + * @arg SDIOC_HOST_FLAG_RTA: Read operation flag + * @arg SDIOC_HOST_FLAG_WTA: Write operation flag + * @arg SDIOC_HOST_FLAG_DA: DAT Line transfer flag + * @arg SDIOC_HOST_FLAG_CID: Command Inhibit with data flag + * @arg SDIOC_HOST_FLAG_CIC: Command Inhibit flag + * @arg SDIOC_HOST_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SDIOC_GetHostStatus(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_GET_HOST_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(SDIOCx->PSTAT, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Get auto CMD12 error status. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u16Flag Auto CMD12 error flag + * This parameter can be one or any combination the following values: + * @arg SDIOC_AUTO_CMD_ERR_FLAG_CMDE: Command Not Issued By Auto CMD12 error flag + * @arg SDIOC_AUTO_CMD_ERR_FLAG_IE: Auto CMD12 Index error flag + * @arg SDIOC_AUTO_CMD_ERR_FLAG_EBE: Auto CMD12 End Bit error flag + * @arg SDIOC_AUTO_CMD_ERR_FLAG_CE: Auto CMD12 CRC error flag + * @arg SDIOC_AUTO_CMD_ERR_FLAG_TOE: Auto CMD12 Timeout error flag + * @arg SDIOC_AUTO_CMD_ERR_FLAG_NE: Auto CMD12 Not Executed flag + * @arg SDIOC_AUTO_CMD_ERR_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SDIOC_GetAutoCmdErrorStatus(const CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_AUTO_CMD_ERR_FLAG(u16Flag)); + + if (0U != (READ_REG16_BIT(SDIOCx->ATCERRST, u16Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Force the specified auto CMD12 error event. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u16Event Auto CMD12 error event + * This parameter can be one or any combination the following values: + * @arg SDIOC_FORCE_AUTO_CMD_ERR_FCMDE: Force Event for Command Not Issued By Auto CMD12 error + * @arg SDIOC_FORCE_AUTO_CMD_ERR_FIE: Force Event for Auto CMD12 Index error + * @arg SDIOC_FORCE_AUTO_CMD_ERR_FEBE: Force Event for Auto CMD12 End Bit error + * @arg SDIOC_FORCE_AUTO_CMD_ERR_FCE: Force Event for Auto CMD12 CRC error + * @arg SDIOC_FORCE_AUTO_CMD_ERR_FTOE: Force Event for Auto CMD12 Timeout error + * @arg SDIOC_FORCE_AUTO_CMD_ERR_FNE: Force Event for Auto CMD12 Not Executed + * @arg SDIOC_FORCE_AUTO_CMD_ERR_ALL: All of the above + * @retval None + */ +void SDIOC_ForceAutoCmdErrorEvent(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Event) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_FORCE_AUTO_CMD_ERR(u16Event)); + + WRITE_REG16(SDIOCx->FEA, u16Event); +} + +/** + * @brief Force the specified error interrupt event. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u16Event Error interrupt event + * This parameter can be one or any combination the following values: + * @arg SDIOC_FORCE_ERR_INT_FACE: Force Event for Auto CMD12 error + * @arg SDIOC_FORCE_ERR_INT_FDEBE: Force Event for Data End Bit error + * @arg SDIOC_FORCE_ERR_INT_FDCE: Force Event for Data CRC error + * @arg SDIOC_FORCE_ERR_INT_FDTOE: Force Event for Data Timeout error + * @arg SDIOC_FORCE_ERR_INT_FCIE: Force Event for Command Index error + * @arg SDIOC_FORCE_ERR_INT_FCEBE: Force Event for Command End Bit error + * @arg SDIOC_FORCE_ERR_INT_FCCE: Force Event for Command CRC error + * @arg SDIOC_FORCE_ERR_INT_FCTOE: Force Event for Command Timeout error + * @arg SDIOC_FORCE_ERR_INT_ALL: All of the above + * @retval None + */ +void SDIOC_ForceErrorIntEvent(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Event) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_FORCE_ERR_INT(u16Event)); + + WRITE_REG16(SDIOCx->FEE, u16Event); +} + +/** + * @brief Send the Go Idle State command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD0_GoIdleState(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + *pu32ErrStatus = SDMMC_ERR_NONE; + stcCmdConfig.u32Argument = 0UL; + stcCmdConfig.u16CmdIndex = SDIOC_CMD0_GO_IDLE_STATE; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_NO; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdError(SDIOCx); + } + } + + return i32Ret; +} + +/** + * @brief Send the Send CID command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD2_AllSendCID(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = 0UL; + stcCmdConfig.u16CmdIndex = SDIOC_CMD2_ALL_SEND_CID; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R2; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp2(SDIOCx, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the command for asking the card to publish a new relative address(RCA). + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu16RCA Pointer to the new RCA value + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu16RCA == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD3_SendRelativeAddr(CM_SDIOC_TypeDef *SDIOCx, uint16_t *pu16RCA, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + uint32_t u32SdMode; + + if ((NULL == pu16RCA) || (NULL == pu32ErrStatus)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = (uint32_t)(*pu16RCA) << 16U; + stcCmdConfig.u16CmdIndex = SDIOC_CMD3_SEND_RELATIVE_ADDR; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + u32SdMode = SDIOC_GetMode(SDIOCx); + if (SDIOC_MD_SD != u32SdMode) { /* MMC mode */ + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } else { + i32Ret = SDMMC_GetCmdResp6(SDIOCx, pu16RCA, pu32ErrStatus); + } + } + } + + return i32Ret; +} + +/** + * @brief Checks switchable function and switch card function. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Argument Argument used for the command. + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD6_SwitchFunc(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + uint32_t u32SdMode; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32Argument; + stcCmdConfig.u16CmdIndex = SDIOC_CMD6_SWITCH_FUNC; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + u32SdMode = SDIOC_GetMode(SDIOCx); + if (SDIOC_MD_SD != u32SdMode) { /* MMC mode */ + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1B_R5B; + } else { + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + } + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + if (SDIOC_MD_SD != u32SdMode) { /* MMC mode */ + i32Ret = SDMMC_GetCmdResp1Busy(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } else { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + } + + return i32Ret; +} + +/** + * @brief Send the Select Deselect command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32RCA Relative Card Address(RCA) + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD7_SelectDeselectCard(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32RCA; + stcCmdConfig.u16CmdIndex = SDIOC_CMD7_SELECT_DESELECT_CARD; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1B_R5B; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1Busy(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Interface Condition command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD8_SendInterfaceCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + uint32_t u32SdMode; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Argument: - [31:12]: Reserved (shall be set to '0') + - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) + - [7:0]: Check Pattern (recommended 0xAA) */ + stcCmdConfig.u32Argument = SDMMC_CMD8_CHECK_PATTERN; + stcCmdConfig.u16CmdIndex = SDIOC_CMD8_SEND_IF_COND; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + u32SdMode = SDIOC_GetMode(SDIOCx); + if (SDIOC_MD_SD != u32SdMode) { /* MMC mode */ + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + } else { + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + } + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + if (SDIOC_MD_SD != u32SdMode) { /* MMC mode */ + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } else { + i32Ret = SDMMC_GetCmdResp7(SDIOCx, pu32ErrStatus); + } + } + } + + return i32Ret; +} + +/** + * @brief Send the Send CSD command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32RCA Relative Card Address(RCA) + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD9_SendCSD(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32RCA; + stcCmdConfig.u16CmdIndex = SDIOC_CMD9_SEND_CSD; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R2; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp2(SDIOCx, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Stop Transfer command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD12_StopTrans(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = 0UL; + stcCmdConfig.u16CmdIndex = SDIOC_CMD12_STOP_TRANSMISSION; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1B_R5B; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1Busy(SDIOCx, SDMMC_CMD_TIMEOUT * 1000UL, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Status command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32RCA Relative Card Address(RCA) + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD13_SendStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32RCA; + stcCmdConfig.u16CmdIndex = SDIOC_CMD13_SEND_STATUS; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Data Block Length command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32BlockLen Block length + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD16_SetBlockLength(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32BlockLen, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32BlockLen; + stcCmdConfig.u16CmdIndex = SDIOC_CMD16_SET_BLOCKLEN; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Read Single Block command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32ReadAddr Data address + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD17_ReadSingleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32ReadAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD17_READ_SINGLE_BLOCK; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Read Multi Block command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32ReadAddr Data address + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD18_ReadMultipleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32ReadAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD18_READ_MULTI_BLOCK; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Write Single Block command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32WriteAddr Data address + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD24_WriteSingleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32WriteAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD24_WRITE_SINGLE_BLOCK; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Write Multi Block command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32WriteAddr Data address + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD25_WriteMultipleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32WriteAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD25_WRITE_MULTI_BLOCK; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Start Address Erase command for SD and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32StartAddr The start address will be erased + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD32_EraseBlockStartAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32StartAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD32_ERASE_WR_BLK_START; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the End Address Erase command for SD and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32EndAddr The end address will be erased + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD33_EraseBlockEndAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32EndAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD33_ERASE_WR_BLK_END; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Erase command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD38_Erase(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = 0UL; + stcCmdConfig.u16CmdIndex = SDIOC_CMD38_ERASE; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1B_R5B; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1Busy(SDIOCx, SDMMC_MAX_ERASE_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Application command to verify that that the next command + * is an application specific command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Argument Argument used for the command. + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD55_AppCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32Argument; + stcCmdConfig.u16CmdIndex = SDIOC_CMD55_APP_CMD; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Bus Width command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32BusWidth The data bus width + * This parameter can be one of the following values: + * @arg SDMMC_SCR_BUS_WIDTH_1BIT: 1 bit bus + * @arg SDMMC_SCR_BUS_WIDTH_4BIT: 4 bits bus + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_ACMD6_SetBusWidth(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32BusWidth, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32BusWidth; + stcCmdConfig.u16CmdIndex = SDIOC_ACMD6_SET_BUS_WIDTH; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Status register command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_ACMD13_SendStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = 0UL; + stcCmdConfig.u16CmdIndex = SDIOC_ACMD13_SD_STATUS; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the command asking the accessed card to send its operating condition register(OCR). + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Argument Argument used for the command. + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_ACMD41_SendOperateCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32Argument | SDMMC_ACMD41_VOLT_WIN; + stcCmdConfig.u16CmdIndex = SDIOC_ACMD41_SD_APP_OP_COND; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R3_R4; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp3(SDIOCx, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Send SCR command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_ACMD51_SendSCR(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = 0UL; + stcCmdConfig.u16CmdIndex = SDIOC_ACMD51_SEND_SCR; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Sends host capacity support information command. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Argument Argument used for the command. + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD1_SendOperateCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32Argument; + stcCmdConfig.u16CmdIndex = SDIOC_CMD1_SEND_OP_COND; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R3_R4; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp3(SDIOCx, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Start Address Erase command and check the response + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32StartAddr The start address will be erased + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD35_EraseGroupStartAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32StartAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD35_ERASE_GROUP_START; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the End Address Erase command and check the response + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32EndAddr The end address will be erased + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD36_EraseGroupEndAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32EndAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD36_ERASE_GROUP_END; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the IO_SEND_OP_COND command for inquiring about the voltage range needed by the I/O card. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Argument Argument used for the command. + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD5_IOSendOperateCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32Argument; + stcCmdConfig.u16CmdIndex = SDIOC_CMD5_IO_SEND_OP_COND; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R3_R4; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp4(SDIOCx, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the IO_RW_DIRECT command to access a single I/O register. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] pstcCmdArg Pointer to a @ref stc_sdio_cmd52_arg_t structure + * @param [in] u8In Data to write + * @param [out] pu8Out Pointer to buffer to store command response + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error or response(R5) indicate error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pstcCmdArg == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD52_IORwDirect(CM_SDIOC_TypeDef *SDIOCx, const stc_sdio_cmd52_arg_t *pstcCmdArg, + uint8_t u8In, uint8_t *pu8Out, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + uint32_t u32Arg; + uint32_t u32R5; + stc_sdioc_cmd_config_t stcCmdConfig; + + if ((NULL == pstcCmdArg) || (NULL == pu32ErrStatus)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Command arguments */ + u32Arg = 0UL; + u32Arg |= pstcCmdArg->u32RwFlag; + u32Arg |= ((uint32_t)pstcCmdArg->u8FuncNum << SDIO_CMD52_ARG_FUNC_SHIFT); + u32Arg |= (pstcCmdArg->u32RegAddr << SDIO_CMD52_ARG_REG_ADDR_SHIFT); + u32Arg |= pstcCmdArg->u32RawFlag; + u32Arg |= u8In; + + stcCmdConfig.u32Argument = u32Arg; + stcCmdConfig.u16CmdIndex = SDIOC_CMD52_IO_RW_DIRECT; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp5(SDIOCx, pu32ErrStatus); + if (LL_OK == i32Ret) { + (void)SDIOC_GetResponse(SDIOCx, SDIOC_RESP_REG_BIT0_31, &u32R5); + if (NULL != pu8Out) { + *pu8Out = (uint8_t)(u32R5 & 0x000000FFUL); + } + } + } + } + + return i32Ret; +} + +/** + * @brief Send the IO_RW_EXTENDED command to access a large number of I/O registers. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] pstcCmdArg Pointer to a @ref stc_sdio_cmd53_arg_t structure + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error or response(R5) indicate error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pstcCmdArg == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD53_IORwExtended(CM_SDIOC_TypeDef *SDIOCx, const stc_sdio_cmd53_arg_t *pstcCmdArg, + uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + uint32_t u32Arg; + stc_sdioc_cmd_config_t stcCmdConfig; + + if ((NULL == pstcCmdArg) || (NULL == pu32ErrStatus)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Command arguments */ + u32Arg = 0UL; + u32Arg |= pstcCmdArg->u32RwFlag; + u32Arg |= ((uint32_t)pstcCmdArg->u8FuncNum << SDIO_CMD53_ARG_FUNC_SHIFT); + u32Arg |= pstcCmdArg->u32BlockMode; + u32Arg |= pstcCmdArg->u32OperateCode; + u32Arg |= (pstcCmdArg->u32RegAddr << SDIO_CMD53_ARG_REG_ADDR_SHIFT); + + stcCmdConfig.u32Argument = u32Arg; + stcCmdConfig.u16CmdIndex = SDIOC_CMD53_IO_RW_EXTENDED; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp5(SDIOCx, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_SDIOC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_spi.c b/mcu/lib/src/hc32_ll_spi.c new file mode 100644 index 0000000..35c63e4 --- /dev/null +++ b/mcu/lib/src/hc32_ll_spi.c @@ -0,0 +1,994 @@ +/** + ******************************************************************************* + * @file hc32_ll_spi.c + * @brief This file provides firmware functions to manage the Serial Peripheral + * Interface(SPI). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-01-15 CDT Add frame level processing for API SPI_TxRx(),SPI_Tx() + 2023-06-30 CDT Modify SPI_GetStatus,SPI_TxRx,SPI_Tx function + Add SPI_SetSckPolarity,SPI_SetSckPhase functions + Modify return type of fuction SPI_DeInit + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_spi.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_SPI SPI + * @brief Serial Peripheral Interface Driver Library + * @{ + */ + +#if (LL_SPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SPI_Local_Macros SPI Local Macros + * @{ + */ + +#define SPI_CFG1_DEFAULT (0x00000010UL) +#define SPI_CFG2_DEFAULT (0x00000F1DUL) + +#define SPI_SS0_VALID_CFG (0UL) +#define SPI_SS1_VALID_CFG (SPI_CFG2_SSA_0) +#define SPI_SS2_VALID_CFG (SPI_CFG2_SSA_1) +#define SPI_SS3_VALID_CFG (SPI_CFG2_SSA_0 | SPI_CFG2_SSA_1) + +#define SPI_SR_DEFAULT (0x00000020UL) + +/** + * @defgroup SPI_Check_Parameters_Validity SPI Check Parameters Validity + * @{ + */ + +/*! Parameter valid check for SPI peripheral */ +#define IS_VALID_SPI_UNIT(x) \ +( (CM_SPI1 == (x)) || \ + (CM_SPI2 == (x)) || \ + (CM_SPI3 == (x)) || \ + (CM_SPI4 == (x))) + +/*! Parameter valid check for SPI wire mode */ +#define IS_SPI_WIRE_MD(x) \ +( ((x) == SPI_4_WIRE) || \ + ((x) == SPI_3_WIRE)) + +/*! Parameter valid check for SPI transfer mode */ +#define IS_SPI_TRANS_MD(x) \ +( ((x) == SPI_FULL_DUPLEX) || \ + ((x) == SPI_SEND_ONLY)) + +/*! Parameter valid check for SPI master slave mode */ +#define IS_SPI_MASTER_SLAVE(x) \ +( ((x) == SPI_SLAVE) || \ + ((x) == SPI_MASTER)) + +/*! Parameter valid check for SPI loopback mode */ +#define IS_SPI_SPLPBK(x) \ +( ((x) == SPI_LOOPBACK_INVD) || \ + ((x) == SPI_LOOPBACK_MOSI_INVT) || \ + ((x) == SPI_LOOPBACK_MOSI)) + +/*! Parameter valid check for SPI communication suspend function status */ +#define IS_SPI_SUSPD_MD_STD(x) \ +( ((x) == SPI_COM_SUSP_FUNC_OFF) || \ + ((x) == SPI_COM_SUSP_FUNC_ON)) + +/*! Parameter valid check for SPI data frame level */ +#define IS_SPI_DATA_FRAME(x) \ +( ((x) == SPI_1_FRAME) || \ + ((x) == SPI_2_FRAME) || \ + ((x) == SPI_3_FRAME) || \ + ((x) == SPI_4_FRAME)) + +/*! Parameter valid check for SPI fault detect function status */ +#define IS_SPI_MD_FAULT_DETECT_CMD(x) \ +( ((x) == SPI_MD_FAULT_DETECT_DISABLE) || \ + ((x) == SPI_MD_FAULT_DETECT_ENABLE)) + +/*! Parameter valid check for SPI parity check mode */ +#define IS_SPI_PARITY_CHECK(x) \ +( ((x) == SPI_PARITY_INVD) || \ + ((x) == SPI_PARITY_EVEN) || \ + ((x) == SPI_PARITY_ODD)) + +/*! Parameter valid check for SPI interval time delay */ +#define IS_SPI_INTERVAL_DELAY(x) \ +( ((x) == SPI_INTERVAL_TIME_1SCK) || \ + ((x) == SPI_INTERVAL_TIME_2SCK) || \ + ((x) == SPI_INTERVAL_TIME_3SCK) || \ + ((x) == SPI_INTERVAL_TIME_4SCK) || \ + ((x) == SPI_INTERVAL_TIME_5SCK) || \ + ((x) == SPI_INTERVAL_TIME_6SCK) || \ + ((x) == SPI_INTERVAL_TIME_7SCK) || \ + ((x) == SPI_INTERVAL_TIME_8SCK)) + +/*! Parameter valid check for SPI release time delay */ +#define IS_SPI_RELEASE_DELAY(x) \ +( ((x) == SPI_RELEASE_TIME_1SCK) || \ + ((x) == SPI_RELEASE_TIME_2SCK) || \ + ((x) == SPI_RELEASE_TIME_3SCK) || \ + ((x) == SPI_RELEASE_TIME_4SCK) || \ + ((x) == SPI_RELEASE_TIME_5SCK) || \ + ((x) == SPI_RELEASE_TIME_6SCK) || \ + ((x) == SPI_RELEASE_TIME_7SCK) || \ + ((x) == SPI_RELEASE_TIME_8SCK)) + +/*! Parameter valid check for SPI Setup time delay delay */ +#define IS_SPI_SETUP_DELAY(x) \ +( ((x) == SPI_SETUP_TIME_1SCK) || \ + ((x) == SPI_SETUP_TIME_2SCK) || \ + ((x) == SPI_SETUP_TIME_3SCK) || \ + ((x) == SPI_SETUP_TIME_4SCK) || \ + ((x) == SPI_SETUP_TIME_5SCK) || \ + ((x) == SPI_SETUP_TIME_6SCK) || \ + ((x) == SPI_SETUP_TIME_7SCK) || \ + ((x) == SPI_SETUP_TIME_8SCK)) + +/*! Parameter valid check for SPI read data register target buffer */ +#define IS_SPI_RD_TARGET_BUFF(x) \ +( ((x) == SPI_RD_TARGET_RD_BUF) || \ + ((x) == SPI_RD_TARGET_WR_BUF)) + +/*! Parameter valid check for SPI mode */ +#define IS_SPI_SPI_MD(x) \ +( ((x) == SPI_MD_0) || \ + ((x) == SPI_MD_1) || \ + ((x) == SPI_MD_2) || \ + ((x) == SPI_MD_3)) + +/*! Parameter valid check for SPI SCK Polarity */ +#define IS_SPI_SCK_POLARITY(x) \ +( ((x) == SPI_SCK_POLARITY_LOW) || \ + ((x) == SPI_SCK_POLARITY_HIGH)) + +/*! Parameter valid check for SPI SCK Phase */ +#define IS_SPI_SCK_PHASE(x) \ +( ((x) == SPI_SCK_PHASE_ODD_EDGE_SAMPLE) || \ + ((x) == SPI_SCK_PHASE_EVEN_EDGE_SAMPLE)) + +/*! Parameter valid check for SPI SS signal */ +#define IS_SPI_SS_PIN(x) \ +( ((x) == SPI_PIN_SS0) || \ + ((x) == SPI_PIN_SS1) || \ + ((x) == SPI_PIN_SS2) || \ + ((x) == SPI_PIN_SS3)) + +/*! Parameter valid check for SPI baudrate prescaler */ +#define IS_SPI_BIT_RATE_DIV(x) \ +( ((x) == SPI_BR_CLK_DIV2) || \ + ((x) == SPI_BR_CLK_DIV4) || \ + ((x) == SPI_BR_CLK_DIV8) || \ + ((x) == SPI_BR_CLK_DIV16) || \ + ((x) == SPI_BR_CLK_DIV32) || \ + ((x) == SPI_BR_CLK_DIV64) || \ + ((x) == SPI_BR_CLK_DIV128) || \ + ((x) == SPI_BR_CLK_DIV256)) + +/*! Parameter valid check for SPI data bits */ +#define IS_SPI_DATA_SIZE(x) \ +( ((x) == SPI_DATA_SIZE_4BIT) || \ + ((x) == SPI_DATA_SIZE_5BIT) || \ + ((x) == SPI_DATA_SIZE_6BIT) || \ + ((x) == SPI_DATA_SIZE_7BIT) || \ + ((x) == SPI_DATA_SIZE_8BIT) || \ + ((x) == SPI_DATA_SIZE_9BIT) || \ + ((x) == SPI_DATA_SIZE_10BIT) || \ + ((x) == SPI_DATA_SIZE_11BIT) || \ + ((x) == SPI_DATA_SIZE_12BIT) || \ + ((x) == SPI_DATA_SIZE_13BIT) || \ + ((x) == SPI_DATA_SIZE_14BIT) || \ + ((x) == SPI_DATA_SIZE_15BIT) || \ + ((x) == SPI_DATA_SIZE_16BIT) || \ + ((x) == SPI_DATA_SIZE_20BIT) || \ + ((x) == SPI_DATA_SIZE_24BIT) || \ + ((x) == SPI_DATA_SIZE_32BIT)) + +/*! Parameter valid check for SPI LSB MSB mode */ +#define IS_SPI_FIRST_BIT(x) \ +( ((x) == SPI_FIRST_MSB) || \ + ((x) == SPI_FIRST_LSB)) + +/*! Parameter valid check for SPI Communication mode */ +#define IS_SPI_COMM_MD(x) \ +( ((x) == SPI_COMM_MD_NORMAL) || \ + ((x) == SPI_COMM_MD_CONTINUE)) + +/*! Parameter valid check for interrupt flag */ +#define IS_SPI_INT(x) \ +( ((x) != 0UL) && \ + (((x) | SPI_IRQ_ALL) == SPI_IRQ_ALL)) + +/*! Parameter valid check for SPI status flag */ +#define IS_SPI_STD_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SPI_FLAG_ALL) == SPI_FLAG_ALL)) + +/*! Parameter valid check for SPI status flag for clear */ +#define IS_SPI_CLR_STD_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SPI_FLAG_CLR_ALL) == SPI_FLAG_CLR_ALL)) + +/*! Parameter valid check for SPI command*/ +#define IS_SPI_CMD_ALLOWED(x) \ +( (READ_REG32_BIT(SPIx->SR, SPI_FLAG_MD_FAULT) == 0UL) || \ + ((x) == DISABLE)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup SPI_Local_Func SPI Local Functions + * @{ + */ + +/** + * @brief SPI check status. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32FlagMask Bit mask of status flag. + * @param [in] u32Value Valid value of the status. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: SPI transmit timeout. + */ +static int32_t SPI_WaitStatus(const CM_SPI_TypeDef *SPIx, uint32_t u32FlagMask, uint32_t u32Value, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + + while (READ_REG32_BIT(SPIx->SR, u32FlagMask) != u32Value) { + if (u32Timeout == 0UL) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Timeout--; + } + return i32Ret; +} + +/** + * @brief SPI transmit and receive data in full duplex mode. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * @param [out] pvRxBuf The pointer to the buffer which the received data will be stored. + * @param [in] u32Len The length of the data in byte or half word. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: SPI transmit and receive timeout. + */ +static int32_t SPI_TxRx(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t u32BitSize; + __IO uint32_t u32TxCnt = 0U, u32RxCnt = 0U; + __IO uint32_t u32Count = 0U; + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + __UNUSED __IO uint32_t u32Read; + __IO uint32_t u32FrameCnt; + uint32_t u32FrameNum = READ_REG32_BIT(SPIx->CFG1, SPI_CFG1_FTHLV) + 1UL; + DDL_ASSERT(0UL == (u32Len % u32FrameNum)); + + /* Get data bit size, SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_32BIT */ + u32BitSize = READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_DSIZE); + while (u32RxCnt < u32Len) { + /* Tx data */ + if (u32TxCnt < u32Len) { + /* Wait TX buffer empty. */ + i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_TX_BUF_EMPTY, SPI_FLAG_TX_BUF_EMPTY, 0U); + if (i32Ret == LL_OK) { + if (pvTxBuf != NULL) { + u32FrameCnt = 0UL; + while (u32FrameCnt < u32FrameNum) { + if (u32BitSize <= SPI_DATA_SIZE_8BIT) { + /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */ + WRITE_REG32(SPIx->DR, ((const uint8_t *)pvTxBuf)[u32TxCnt]); + } else if (u32BitSize <= SPI_DATA_SIZE_16BIT) { + /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */ + WRITE_REG32(SPIx->DR, ((const uint16_t *)pvTxBuf)[u32TxCnt]); + } else { + /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */ + WRITE_REG32(SPIx->DR, ((const uint32_t *)pvTxBuf)[u32TxCnt]); + } + u32FrameCnt++; + u32TxCnt++; + } + } else { + u32FrameCnt = 0UL; + while (u32FrameCnt < u32FrameNum) { + WRITE_REG32(SPIx->DR, 0xFFFFFFFFUL); + u32FrameCnt++; + u32TxCnt++; + } + } + } + } + + /* RX data */ + i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_RX_BUF_FULL, SPI_FLAG_RX_BUF_FULL, 0U); + if (i32Ret == LL_OK) { + if (pvRxBuf != NULL) { + u32FrameCnt = 0UL; + while (u32FrameCnt < u32FrameNum) { + u32Tmp = READ_REG32(SPIx->DR); + if (u32BitSize <= SPI_DATA_SIZE_8BIT) { + /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */ + ((uint8_t *)pvRxBuf)[u32RxCnt] = (uint8_t)u32Tmp; + } else if (u32BitSize <= SPI_DATA_SIZE_16BIT) { + /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */ + ((uint16_t *)pvRxBuf)[u32RxCnt] = (uint16_t)u32Tmp; + } else { + /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */ + ((uint32_t *)pvRxBuf)[u32RxCnt] = (uint32_t)u32Tmp; + } + u32FrameCnt++; + u32RxCnt++; + } + } else { + /* Dummy read */ + u32FrameCnt = 0UL; + while (u32FrameCnt < u32FrameNum) { + u32Read = READ_REG32(SPIx->DR); + u32FrameCnt++; + u32RxCnt++; + } + } + } + + /* check timeout */ + if (u32Count > u32Timeout) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count++; + } + + if ((SPI_CR1_MSTR == READ_REG32_BIT(SPIx->CR1, SPI_CR1_MSTR)) && (i32Ret == LL_OK)) { + i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_IDLE, 0UL, u32Timeout); + } + + return i32Ret; +} + +/** + * @brief SPI send data only. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * @param [in] u32Len The length of the data in byte or half word or word. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: SPI transmit timeout. + */ +static int32_t SPI_Tx(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + __IO uint32_t u32TxCnt = 0U; + uint32_t u32BitSize; + int32_t i32Ret = LL_OK; + __IO uint32_t u32FrameCnt; + uint32_t u32FrameNum = READ_REG32_BIT(SPIx->CFG1, SPI_CFG1_FTHLV) + 1UL; + DDL_ASSERT(0UL == (u32Len % u32FrameNum)); + + /* Get data bit size, SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_32BIT */ + u32BitSize = READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_DSIZE); + while (u32TxCnt < u32Len) { + u32FrameCnt = 0UL; + while (u32FrameCnt < u32FrameNum) { + if (u32BitSize <= SPI_DATA_SIZE_8BIT) { + /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */ + WRITE_REG32(SPIx->DR, ((const uint8_t *)pvTxBuf)[u32TxCnt]); + } else if (u32BitSize <= SPI_DATA_SIZE_16BIT) { + /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */ + WRITE_REG32(SPIx->DR, ((const uint16_t *)pvTxBuf)[u32TxCnt]); + } else { + /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */ + WRITE_REG32(SPIx->DR, ((const uint32_t *)pvTxBuf)[u32TxCnt]); + } + u32FrameCnt++; + u32TxCnt++; + } + /* Wait TX buffer empty. */ + i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_TX_BUF_EMPTY, SPI_FLAG_TX_BUF_EMPTY, u32Timeout); + if (i32Ret != LL_OK) { + break; + } + } + + if ((SPI_CR1_MSTR == READ_REG32_BIT(SPIx->CR1, SPI_CR1_MSTR)) && (i32Ret == LL_OK)) { + i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_IDLE, 0UL, u32Timeout); + } + + return i32Ret; +} + +/** + * @} + */ + +/** + * @defgroup SPI_Global_Functions SPI Global Functions + * @{ + */ + +/** + * @brief Initializes the SPI peripheral according to the specified parameters + * in the structure stc_spi_init. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pstcSpiInit Pointer to a stc_spi_init_t structure that contains + * the configuration information for the SPI. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_INVD_PARAM: pstcSpiInit == NULL or configuration parameter error. + */ +int32_t SPI_Init(CM_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + if (NULL != pstcSpiInit) { + DDL_ASSERT(IS_SPI_WIRE_MD(pstcSpiInit->u32WireMode)); + DDL_ASSERT(IS_SPI_TRANS_MD(pstcSpiInit->u32TransMode)); + DDL_ASSERT(IS_SPI_MASTER_SLAVE(pstcSpiInit->u32MasterSlave)); + DDL_ASSERT(IS_SPI_MD_FAULT_DETECT_CMD(pstcSpiInit->u32ModeFaultDetect)); + DDL_ASSERT(IS_SPI_PARITY_CHECK(pstcSpiInit->u32Parity)); + DDL_ASSERT(IS_SPI_SPI_MD(pstcSpiInit->u32SpiMode)); + DDL_ASSERT(IS_SPI_BIT_RATE_DIV(pstcSpiInit->u32BaudRatePrescaler)); + DDL_ASSERT(IS_SPI_DATA_SIZE(pstcSpiInit->u32DataBits)); + DDL_ASSERT(IS_SPI_FIRST_BIT(pstcSpiInit->u32FirstBit)); + DDL_ASSERT(IS_SPI_SUSPD_MD_STD(pstcSpiInit->u32SuspendMode)); + DDL_ASSERT(IS_SPI_DATA_FRAME(pstcSpiInit->u32FrameLevel)); + + /* Configuration parameter check */ + if ((SPI_MASTER == pstcSpiInit->u32MasterSlave) && (SPI_MD_FAULT_DETECT_ENABLE == pstcSpiInit->u32ModeFaultDetect)) { + /* pstcSpiInit->u32ModeFaultDetect can not be SPI_MD_FAULT_DETECT_ENABLE in master mode */ + } else if ((SPI_3_WIRE == pstcSpiInit->u32WireMode) && (SPI_SLAVE == pstcSpiInit->u32MasterSlave) + && ((SPI_MD_0 == pstcSpiInit->u32SpiMode) || (SPI_MD_2 == pstcSpiInit->u32SpiMode))) { + /* SPI_3_WIRE can not support SPI_MD_0 and SPI_MD_2 */ + } else { + WRITE_REG32(SPIx->CR1, pstcSpiInit->u32WireMode | pstcSpiInit->u32TransMode | pstcSpiInit->u32MasterSlave + | pstcSpiInit->u32SuspendMode | pstcSpiInit->u32ModeFaultDetect | pstcSpiInit->u32Parity); + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_FTHLV, pstcSpiInit->u32FrameLevel); + WRITE_REG32(SPIx->CFG2, pstcSpiInit->u32SpiMode | pstcSpiInit->u32BaudRatePrescaler | pstcSpiInit->u32DataBits + | pstcSpiInit->u32FirstBit); + i32Ret = LL_OK; + } + } + return i32Ret; +} + +/** + * @brief De-initializes the SPI peripheral. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @retval int32_t: + * - LL_OK: No error occurred. + */ +int32_t SPI_DeInit(CM_SPI_TypeDef *SPIx) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + WRITE_REG32(SPIx->CR1, 0UL); + WRITE_REG32(SPIx->CFG1, SPI_CFG1_DEFAULT); + WRITE_REG32(SPIx->CFG2, SPI_CFG2_DEFAULT); + CLR_REG32_BIT(SPIx->SR, SPI_FLAG_CLR_ALL); + + return LL_OK; +} + +/** + * @brief Set a default value for the SPI initialization structure. + * @param [in] pstcSpiInit Pointer to a stc_spi_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcSpiInit == NULL. + */ +int32_t SPI_StructInit(stc_spi_init_t *pstcSpiInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcSpiInit) { + pstcSpiInit->u32WireMode = SPI_4_WIRE; + pstcSpiInit->u32TransMode = SPI_FULL_DUPLEX; + pstcSpiInit->u32MasterSlave = SPI_MASTER; + pstcSpiInit->u32ModeFaultDetect = SPI_MD_FAULT_DETECT_DISABLE; + pstcSpiInit->u32Parity = SPI_PARITY_INVD; + pstcSpiInit->u32SpiMode = SPI_MD_0; + pstcSpiInit->u32BaudRatePrescaler = SPI_BR_CLK_DIV8; + pstcSpiInit->u32DataBits = SPI_DATA_SIZE_8BIT; + pstcSpiInit->u32FirstBit = SPI_FIRST_MSB; + pstcSpiInit->u32SuspendMode = SPI_COM_SUSP_FUNC_OFF; + pstcSpiInit->u32FrameLevel = SPI_1_FRAME; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Enable or disable SPI interrupt. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32IntType SPI interrupt type. Can be one or any + * combination of the parameter @ref SPI_Int_Type_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SPI_IntCmd(CM_SPI_TypeDef *SPIx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_SPI_INT(u32IntType)); + + if (enNewState == ENABLE) { + SET_REG32_BIT(SPIx->CR1, u32IntType); + } else { + CLR_REG32_BIT(SPIx->CR1, u32IntType); + } +} + +/** + * @brief SPI function enable or disable. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SPI_Cmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_SPI_CMD_ALLOWED(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(SPIx->CR1, SPI_CR1_SPE); + } else { + CLR_REG32_BIT(SPIx->CR1, SPI_CR1_SPE); + } +} + +/** + * @brief Write SPI data register. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Data The data will be written to the data register. + * @retval None. + */ +void SPI_WriteData(CM_SPI_TypeDef *SPIx, uint32_t u32Data) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + WRITE_REG32(SPIx->DR, u32Data); +} + +/** + * @brief Read SPI data register. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @retval uint32_t A 32-bit data of SPI data register. + */ +uint32_t SPI_ReadData(const CM_SPI_TypeDef *SPIx) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + return READ_REG32(SPIx->DR); +} + +/** + * @brief SPI get status flag. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Flag SPI state flag. Can be one or any + * combination of the parameter of @ref SPI_State_Flag_Define + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SPI_GetStatus(const CM_SPI_TypeDef *SPIx, uint32_t u32Flag) +{ + en_flag_status_t enFlag = RESET; + uint32_t u32Status; + + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_STD_FLAG(u32Flag)); + + u32Status = READ_REG32(SPIx->SR); + if (SPI_FLAG_IDLE == (SPI_FLAG_IDLE & u32Flag)) { + CLR_REG32_BIT(u32Flag, SPI_FLAG_IDLE); + if (0U == (u32Status & SPI_FLAG_IDLE)) { + enFlag = SET; + } + } + if (0U != READ_REG32_BIT(u32Status, u32Flag)) { + enFlag = SET; + } + + return enFlag; +} + +/** + * @brief SPI clear state flag. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Flag SPI state flag. Can be one or any combination of the parameter below + * @arg SPI_FLAG_OVERLOAD + * @arg SPI_FLAG_MD_FAULT + * @arg SPI_FLAG_PARITY_ERR + * @arg SPI_FLAG_UNDERLOAD + * @retval None + */ +void SPI_ClearStatus(CM_SPI_TypeDef *SPIx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_CLR_STD_FLAG(u32Flag)); + + CLR_REG32_BIT(SPIx->SR, u32Flag); +} + +/** + * @brief SPI loopback function configuration. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Mode Loopback mode. Can be one parameter @ref SPI_Loopback_Selection_Define + * @retval None + */ +void SPI_LoopbackModeConfig(CM_SPI_TypeDef *SPIx, uint32_t u32Mode) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SPLPBK(u32Mode)); + + MODIFY_REG32(SPIx->CR1, SPI_CR1_SPLPBK | SPI_CR1_SPLPBK2, u32Mode); +} + +/** + * @brief SPI parity check error self diagnosis function enable or disable. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ + +void SPI_ParityCheckCmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(SPIx->CR1, SPI_CR1_PATE); + } else { + CLR_REG32_BIT(SPIx->CR1, SPI_CR1_PATE); + } +} + +/** + * @brief SPI signals delay time configuration + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pstcDelayConfig Pointer to a stc_spi_delay_t structure that contains + * the configuration information for the SPI delay time. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_INVD_PARAM: pstcDelayConfig == NULL + */ +int32_t SPI_DelayTimeConfig(CM_SPI_TypeDef *SPIx, const stc_spi_delay_t *pstcDelayConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + if (NULL != pstcDelayConfig) { + DDL_ASSERT(IS_SPI_INTERVAL_DELAY(pstcDelayConfig->u32IntervalDelay)); + DDL_ASSERT(IS_SPI_RELEASE_DELAY(pstcDelayConfig->u32ReleaseDelay)); + DDL_ASSERT(IS_SPI_SETUP_DELAY(pstcDelayConfig->u32SetupDelay)); + + /* Interval delay */ + if (SPI_INTERVAL_TIME_1SCK == pstcDelayConfig->u32IntervalDelay) { + CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MIDIE); + CLR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MIDI); + } else { + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MIDI, pstcDelayConfig->u32IntervalDelay); + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MIDIE); + } + + /* SCK release delay */ + if (SPI_RELEASE_TIME_1SCK == pstcDelayConfig->u32ReleaseDelay) { + CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSDLE); + CLR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MSSDL); + } else { + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSDLE); + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MSSDL, pstcDelayConfig->u32ReleaseDelay); + } + + /* Setup delay */ + if (SPI_SETUP_TIME_1SCK == pstcDelayConfig->u32SetupDelay) { + CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSIE); + CLR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MSSI); + } else { + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSIE); + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MSSI, pstcDelayConfig->u32SetupDelay); + } + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set a default value for the SPI delay time configuration structure. + * @param [in] pstcDelayConfig Pointer to a stc_spi_delay_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcDelayConfig == NULL. + */ +int32_t SPI_DelayStructInit(stc_spi_delay_t *pstcDelayConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcDelayConfig) { + pstcDelayConfig->u32IntervalDelay = SPI_INTERVAL_TIME_1SCK; + pstcDelayConfig->u32ReleaseDelay = SPI_RELEASE_TIME_1SCK; + pstcDelayConfig->u32SetupDelay = SPI_SETUP_TIME_1SCK; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief SPI SS signal valid level configuration + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32SSPin Specify the SS pin @ref SPI_SS_Pin_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SPI_SSValidLevelConfig(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SS_PIN(u32SSPin)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(SPIx->CFG1, u32SSPin); + } else { + CLR_REG32_BIT(SPIx->CFG1, u32SSPin); + } +} + +/** + * @brief Set the SPI SCK polarity. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Polarity Specify the SPI SCK polarity @ref SPI_SCK_Polarity_Define + * @retval None + */ +void SPI_SetSckPolarity(CM_SPI_TypeDef *SPIx, uint32_t u32Polarity) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SCK_POLARITY(u32Polarity)); + + if (SPI_SCK_POLARITY_LOW == u32Polarity) { + CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_CPOL); + } else { + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_CPOL); + } +} + +/** + * @brief Set the SPI SCK phase. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Phase Specify the SPI SCK phase @ref SPI_SCK_Phase_Define + * @retval None + */ +void SPI_SetSckPhase(CM_SPI_TypeDef *SPIx, uint32_t u32Phase) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SCK_PHASE(u32Phase)); + + if (SPI_SCK_PHASE_ODD_EDGE_SAMPLE == u32Phase) { + CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_CPHA); + } else { + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_CPHA); + } +} + +/** + * @brief SPI valid SS signal configuration + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32SSPin Specify the SS pin @ref SPI_SS_Pin_Define + * @retval None + */ +void SPI_SSPinSelect(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin) +{ + uint32_t u32RegConfig; + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SS_PIN(u32SSPin)); + + switch (u32SSPin) { + case SPI_PIN_SS0: + u32RegConfig = SPI_SS0_VALID_CFG; + break; + case SPI_PIN_SS1: + u32RegConfig = SPI_SS1_VALID_CFG; + break; + case SPI_PIN_SS2: + u32RegConfig = SPI_SS2_VALID_CFG; + break; + case SPI_PIN_SS3: + u32RegConfig = SPI_SS3_VALID_CFG; + break; + + default: + u32RegConfig = SPI_SS0_VALID_CFG; + break; + } + MODIFY_REG32(SPIx->CFG2, SPI_CFG2_SSA, u32RegConfig); +} + +/** + * @brief SPI read buffer configuration + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32ReadBuf Target buffer for read operation @ref SPI_Read_Target_Buf_Define + * @retval None + */ +void SPI_ReadBufConfig(CM_SPI_TypeDef *SPIx, uint32_t u32ReadBuf) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_RD_TARGET_BUFF(u32ReadBuf)); + + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_SPRDTD, u32ReadBuf); +} + +/** + * @brief SPI transmit data. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * @param [in] u32TxLen The length of the data to be sent. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: SPI transmit timeout. + * - LL_ERR_INVD_PARAM: pvTxBuf == NULL or u32TxLen == 0U + * @note -No SS pin active and inactive operation in 3-wire mode. Add operations of SS pin depending on your application. + * -In the send only slave mode, the function needs to increase an appropriate delay after calling to ensure the + * integrity of data transmission. + */ +int32_t SPI_Trans(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32TxLen, uint32_t u32Timeout) +{ + uint32_t u32Flags; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pvTxBuf != NULL) && (u32TxLen != 0U)) { + u32Flags = READ_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS); + if (u32Flags == SPI_SEND_ONLY) { + /* Transmit data in send only mode. */ + i32Ret = SPI_Tx(SPIx, pvTxBuf, u32TxLen, u32Timeout); + } else { + /* Transmit data in full duplex mode. */ + i32Ret = SPI_TxRx(SPIx, pvTxBuf, NULL, u32TxLen, u32Timeout); + } + } + return i32Ret; +} + +/** + * @brief SPI receive data. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pvRxBuf The pointer to the buffer which the received data to be stored. + * @param [in] u32RxLen The length of the data to be received. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: SPI receive timeout. + * - LL_ERR_INVD_PARAM: pvRxBuf == NULL or u32RxLen == 0U + * @note -No SS pin active and inactive operation in 3-wire mode. Add operations of SS pin depending on your application. + */ +int32_t SPI_Receive(CM_SPI_TypeDef *SPIx, void *pvRxBuf, uint32_t u32RxLen, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pvRxBuf != NULL) && (u32RxLen != 0U)) { + /* Receives data in full duplex master mode. */ + i32Ret = SPI_TxRx(SPIx, NULL, pvRxBuf, u32RxLen, u32Timeout); + } + return i32Ret; +} + +/** + * @brief SPI transmit and receive data. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * If this pointer is NULL and the pvRxBuf is NOT NULL, the MOSI output high + * and the the received data will be stored in the buffer pointed by pvRxBuf. + * @param [out] pvRxBuf The pointer to the buffer which the received data will be stored. + * This for full duplex transfer. + * @param [in] u32Len The length of the data(in byte or half word) to be sent and received. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: SPI transmit and receive timeout. + * - LL_ERR_INVD_PARAM: pvRxBuf == NULL or pvRxBuf == NULL or u32Len == 0U + * @note SPI receives data while sending data. + */ +int32_t SPI_TransReceive(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pvTxBuf != NULL) && (pvRxBuf != NULL) && (u32Len != 0U)) { + /* Transmit and receive data in full duplex master mode. */ + i32Ret = SPI_TxRx(SPIx, pvTxBuf, pvRxBuf, u32Len, u32Timeout); + } + return i32Ret; +} +/** + * @} + */ + +#endif /* LL_SPI_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_sram.c b/mcu/lib/src/hc32_ll_sram.c new file mode 100644 index 0000000..c041b6e --- /dev/null +++ b/mcu/lib/src/hc32_ll_sram.c @@ -0,0 +1,302 @@ +/** + ******************************************************************************* + * @file hc32_ll_sram.c + * @brief This file provides firmware functions to manage the SRAM. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-10-31 CDT Deleted redundant comments + 2023-06-30 CDT API fixed: SRAM_ClearStatus() + 2023-09-30 CDT API fixed: SRAM_SetWaitCycle() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_sram.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_SRAM SRAM + * @brief SRAM Driver Library + * @{ + */ + +#if (LL_SRAM_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SRAM_Local_Macros SRAM Local Macros + * @{ + */ + +/** + * @defgroup SRAM_Configuration_Bits_Mask SRAM Configuration Bits Mask + * @{ + */ +#define SRAM_ECC_MD_MASK (SRAMC_CKCR_ECCMOD) +#define SRAM_CYCLE_MASK (0x00000007UL) +/** + * @} + */ + +/** + * @defgroup SRAM_Check_Parameters_Validity SRAM check parameters validity + * @{ + */ +#define IS_SRAM_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask))) + +#define IS_SRAM_ERR_MD(x) (((x) == SRAM_ERR_MD_NMI) || ((x) == SRAM_ERR_MD_RST)) + +#define IS_SRAM_WAIT_CYCLE(x) ((x) <= SRAM_WAIT_CYCLE7) + +#define IS_SRAM_SEL(x) IS_SRAM_BIT_MASK(x, SRAM_SRAM_ALL) + +#define IS_SRAM_ECC_SRAM(x) ((x) == SRAM_ECC_SRAM3) + +#define IS_SRAM_FLAG(x) IS_SRAM_BIT_MASK(x, SRAM_FLAG_ALL) + +#define IS_SRAM_WTPR_UNLOCK() (CM_SRAMC->WTPR == SRAM_REG_UNLOCK_KEY) + +#define IS_SRAM_CKPR_UNLOCK() (CM_SRAMC->CKPR == SRAM_REG_UNLOCK_KEY) + +#define IS_SRAM_ECC_MD(x) \ +( ((x) == SRAM_ECC_MD_INVD) || \ + ((x) == SRAM_ECC_MD1) || \ + ((x) == SRAM_ECC_MD2) || \ + ((x) == SRAM_ECC_MD3)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup SRAM_Global_Functions SRAM Global Functions + * @{ + */ + +/** + * @brief Initializes SRAM. + * @param None + * @retval None + */ +void SRAM_Init(void) +{ + SET_REG32_BIT(CM_SRAMC->CKSR, SRAM_FLAG_ALL); +} + +/** + * @brief De-initializes SRAM. RESET the registers of SRAM. + * @param None + * @retval None + * @note Call SRAM_REG_Unlock to unlock registers WTCR and CKCR first. + */ +void SRAM_DeInit(void) +{ + /* Call SRAM_REG_Unlock to unlock register WTCR and CKCR. */ + DDL_ASSERT(IS_SRAM_WTPR_UNLOCK()); + DDL_ASSERT(IS_SRAM_CKPR_UNLOCK()); + + WRITE_REG32(CM_SRAMC->WTCR, 0U); + WRITE_REG32(CM_SRAMC->CKCR, 0U); + SET_REG32_BIT(CM_SRAMC->CKSR, SRAM_FLAG_ALL); +} + +/** + * @brief Specifies access wait cycle for SRAM. + * @param [in] u32SramSel The SRAM selection. + * This parameter can be values of @ref SRAM_Sel + * @param [in] u32WriteCycle The write access wait cycle for the specified SRAM + * This parameter can be a value of @ref SRAM_Access_Wait_Cycle + * @param [in] u32ReadCycle The read access wait cycle for the specified SRAM. + * This parameter can be a value of @ref SRAM_Access_Wait_Cycle + * @arg SRAM_WAIT_CYCLE0: Wait 0 CPU cycle. + * @arg SRAM_WAIT_CYCLE1: Wait 1 CPU cycle. + * @arg SRAM_WAIT_CYCLE2: Wait 2 CPU cycles. + * @arg SRAM_WAIT_CYCLE3: Wait 3 CPU cycles. + * @arg SRAM_WAIT_CYCLE4: Wait 4 CPU cycles. + * @arg SRAM_WAIT_CYCLE5: Wait 5 CPU cycles. + * @arg SRAM_WAIT_CYCLE6: Wait 6 CPU cycles. + * @arg SRAM_WAIT_CYCLE7: Wait 7 CPU cycles. + * @retval None + * @note Call SRAM_REG_Unlock to unlock register WTCR first. + */ +void SRAM_SetWaitCycle(uint32_t u32SramSel, uint32_t u32WriteCycle, uint32_t u32ReadCycle) +{ + uint8_t i = 0U; + uint8_t u8OfsWt; + uint8_t u8OfsRd; + + DDL_ASSERT(IS_SRAM_SEL(u32SramSel)); + DDL_ASSERT(IS_SRAM_WAIT_CYCLE(u32WriteCycle)); + DDL_ASSERT(IS_SRAM_WAIT_CYCLE(u32ReadCycle)); + DDL_ASSERT(IS_SRAM_WTPR_UNLOCK()); + + while (u32SramSel != 0UL) { + if ((u32SramSel & 0x1UL) != 0UL) { + u8OfsRd = i * 8U; + u8OfsWt = u8OfsRd + 4U; + MODIFY_REG32(CM_SRAMC->WTCR, + ((SRAM_CYCLE_MASK << u8OfsWt) | (SRAM_CYCLE_MASK << u8OfsRd)), + ((u32WriteCycle << u8OfsWt) | (u32ReadCycle << u8OfsRd))); + } + u32SramSel >>= 1U; + i++; + } +} + +/** + * @brief Specifies ECC mode. + * @param [in] u32SramSel The SRAM selection. This function is used to specify the + * ECC mode for members SRAM_ECC_XXXX of @ref SRAM_Sel + * @param [in] u32EccMode The ECC mode. + * This parameter can be a value of @ref SRAM_ECC_Mode + * @arg SRAM_ECC_MD_INVD: The ECC mode is invalid. + * @arg SRAM_ECC_MD1: When 1-bit error occurred: + * ECC error corrects. + * No 1-bit-error status flag setting, no interrupt or reset. + * When 2-bit error occurred: + * ECC error detects. + * 2-bit-error status flag sets and interrupt or reset occurred. + * @arg SRAM_ECC_MD2: When 1-bit error occurred: + * ECC error corrects. + * 1-bit-error status flag sets, no interrupt or reset. + * When 2-bit error occurred: + * ECC error detects. + * 2-bit-error status flag sets and interrupt or reset occurred. + * @arg SRAM_ECC_MD3: When 1-bit error occurred: + * ECC error corrects. + * 1-bit-error status flag sets and interrupt or reset occurred. + * When 2-bit error occurred: + * ECC error detects. + * 2-bit-error status flag sets and interrupt or reset occurred. + * @retval None + * @note Call SRAM_REG_Unlock to unlock register CKCR first. + */ +void SRAM_SetEccMode(uint32_t u32SramSel, uint32_t u32EccMode) +{ + DDL_ASSERT(IS_SRAM_ECC_SRAM(u32SramSel)); + DDL_ASSERT(IS_SRAM_ECC_MD(u32EccMode)); + DDL_ASSERT(IS_SRAM_CKPR_UNLOCK()); + + if ((u32SramSel & SRAM_SRAM3) != 0U) { + MODIFY_REG32(CM_SRAMC->CKCR, SRAM_ECC_MD_MASK, u32EccMode); + } + +} + +/** + * @brief Specifies the operation which is operated after check error occurred. + * @param [in] u32SramSel The SRAM selection. + * This parameter can be values of @ref SRAM_Sel + * @param [out] u32ErrMode The operation after check error occurred. + * This parameter can be a value of @ref SRAM_Err_Mode + * @arg SRAM_ERR_MD_NMI: Check error generates NMI(non-maskable interrupt). + * @arg SRAM_ERR_MD_RST: Check error generates system reset. + * @retval None + * @note Call SRAM_REG_Unlock to unlock register CKCR first. + */ +void SRAM_SetErrorMode(uint32_t u32SramSel, uint32_t u32ErrMode) +{ + DDL_ASSERT(IS_SRAM_SEL(u32SramSel)); + DDL_ASSERT(IS_SRAM_ERR_MD(u32ErrMode)); + DDL_ASSERT(IS_SRAM_CKPR_UNLOCK()); + + if ((u32SramSel & (SRAM_SRAM12 | SRAM_SRAMR | SRAM_SRAMH)) != 0U) { + WRITE_REG32(bCM_SRAMC->CKCR_b.PYOAD, u32ErrMode); + } + + if ((u32SramSel & SRAM_SRAM3) != 0U) { + WRITE_REG32(bCM_SRAMC->CKCR_b.ECCOAD, u32ErrMode); + } + +} + +/** + * @brief Get the status of the specified flag of SRAM. + * @param [in] u32Flag The flag of SRAM. + * This parameter can be a value of @ref SRAM_Err_Status_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SRAM_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_SRAM_FLAG(u32Flag)); + if (READ_REG32_BIT(CM_SRAMC->CKSR, u32Flag) != 0U) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of the specified flag of SRAM. + * @param [in] u32Flag The flag of SRAM. + * This parameter can be values of @ref SRAM_Err_Status_Flag + * @retval None + */ +void SRAM_ClearStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_SRAM_FLAG(u32Flag)); + WRITE_REG32(CM_SRAMC->CKSR, u32Flag); +} + +/** + * @} + */ + +#endif /* LL_SRAM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_swdt.c b/mcu/lib/src/hc32_ll_swdt.c new file mode 100644 index 0000000..f2952e8 --- /dev/null +++ b/mcu/lib/src/hc32_ll_swdt.c @@ -0,0 +1,182 @@ +/** + ******************************************************************************* + * @file hc32_ll_swdt.c + * @brief This file provides firmware functions to manage the Specialized Watch + * Dog Timer(SWDT). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-09-30 CDT Optimize SWDT_ClearStatus function timeout + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_swdt.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_SWDT SWDT + * @brief Specialized Watch Dog Timer + * @{ + */ + +#if (LL_SWDT_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SWDT_Local_Macros SWDT Local Macros + * @{ + */ + +/* SWDT Refresh Key */ +#define SWDT_REFRESH_KEY_START (0x0123UL) +#define SWDT_REFRESH_KEY_END (0x3210UL) + +/* SWDT clear flag timeout(ms) */ +#define SWDT_CLR_FLAG_TIMEOUT (400UL) + +/** + * @defgroup SWDT_Check_Parameters_Validity SWDT Check Parameters Validity + * @{ + */ + +#define IS_SWDT_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SWDT_FLAG_ALL) == SWDT_FLAG_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @addtogroup SWDT_Global_Functions + * @{ + */ + +/** + * @brief SWDT feed dog. + * @note In software startup mode, Start counter when refreshing for the first time. + * @param None + * @retval None + */ +void SWDT_FeedDog(void) +{ + WRITE_REG32(CM_SWDT->RR, SWDT_REFRESH_KEY_START); + WRITE_REG32(CM_SWDT->RR, SWDT_REFRESH_KEY_END); +} + +/** + * @brief Get SWDT flag status. + * @param [in] u32Flag SWDT flag type + * This parameter can be one or any combination of the following values: + * @arg SWDT_FLAG_UDF: Count underflow flag + * @arg SWDT_FLAG_REFRESH: Refresh error flag + * @arg SWDT_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SWDT_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_SWDT_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(CM_SWDT->SR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear SWDT flag. + * @param [in] u32Flag SWDT flag type + * This parameter can be one or any combination of the following values: + * @arg SWDT_FLAG_UDF: Count underflow flag + * @arg SWDT_FLAG_REFRESH: Refresh error flag + * @arg SWDT_FLAG_ALL: All of the above + * @retval int32_t: + * - LL_OK: Clear flag success + * - LL_ERR_TIMEOUT: Clear flag timeout + */ +int32_t SWDT_ClearStatus(uint32_t u32Flag) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* Check parameters */ + DDL_ASSERT(IS_SWDT_FLAG(u32Flag)); + + /* Waiting for FLAG bit clear */ + u32Count = SWDT_CLR_FLAG_TIMEOUT * (HCLK_VALUE / 25000UL); + while (0UL != READ_REG32_BIT(CM_SWDT->SR, u32Flag)) { + CLR_REG32_BIT(CM_SWDT->SR, u32Flag); + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_SWDT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_tmr0.c b/mcu/lib/src/hc32_ll_tmr0.c new file mode 100644 index 0000000..8b4f245 --- /dev/null +++ b/mcu/lib/src/hc32_ll_tmr0.c @@ -0,0 +1,625 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr0.c + * @brief This file provides firmware functions to manage the TMR0 + * (TMR0). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_tmr0.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TMR0 TMR0 + * @brief TMR0 Driver Library + * @{ + */ + +#if (LL_TMR0_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR0_Local_Macros TMR0 Local Macros + * @{ + */ +/* Max channel number */ +#define TMR0_CH_MAX (2UL) + +#define TMR0_CLK_SRC_MASK (TMR0_BCONR_SYNSA | TMR0_BCONR_SYNCLKA | TMR0_BCONR_ASYNCLKA) +#define TMR0_BCONR_CLR_MASK (TMR0_BCONR_CAPMDA | TMR0_BCONR_CKDIVA | TMR0_BCONR_HICPA | TMR0_CLK_SRC_MASK) + +/** + * @defgroup TMR0_Register_Address TMR0 Register Address + * @{ + */ +#define TMR0_CNTR_ADDR(__UNIT__, __CH__) (__IO uint32_t*)((uint32_t)(&((__UNIT__)->CNTAR)) + ((__CH__) << 2UL)) +#define TMR0_CMPR_ADDR(__UNIT__, __CH__) (__IO uint32_t*)((uint32_t)(&((__UNIT__)->CMPAR)) + ((__CH__) << 2UL)) +/** + * @} + */ +#define TMR0_CH_OFFSET(__CH__) ((__CH__) << 4U) + +/** + * @defgroup TMR0_Check_Parameters_Validity TMR0 Check Parameters Validity + * @{ + */ +#define IS_TMR0_UNIT(x) \ +( ((x) == CM_TMR0_1) || \ + ((x) == CM_TMR0_2)) + +#define IS_TMR0_CH(x) \ +( ((x) == TMR0_CH_A) || \ + ((x) == TMR0_CH_B)) + +#define IS_TMR0_CLK_SRC(x) \ +( ((x) == TMR0_CLK_SRC_INTERN_CLK) || \ + ((x) == TMR0_CLK_SRC_SPEC_EVT) || \ + ((x) == TMR0_CLK_SRC_LRC) || \ + ((x) == TMR0_CLK_SRC_XTAL32)) + +#define IS_TMR0_CLK_DIV(x) \ +( ((x) == TMR0_CLK_DIV1) || \ + ((x) == TMR0_CLK_DIV2) || \ + ((x) == TMR0_CLK_DIV4) || \ + ((x) == TMR0_CLK_DIV8) || \ + ((x) == TMR0_CLK_DIV16) || \ + ((x) == TMR0_CLK_DIV32) || \ + ((x) == TMR0_CLK_DIV64) || \ + ((x) == TMR0_CLK_DIV128) || \ + ((x) == TMR0_CLK_DIV256) || \ + ((x) == TMR0_CLK_DIV512) || \ + ((x) == TMR0_CLK_DIV1024)) + +#define IS_TMR0_FUNC(x) \ +( ((x) == TMR0_FUNC_CMP) || \ + ((x) == TMR0_FUNC_CAPT)) + +#define IS_TMR0_INT(x) \ +( ((x) != 0U) && \ + (((x) | TMR0_INT_ALL) == TMR0_INT_ALL)) + +#define IS_TMR0_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | TMR0_FLAG_ALL) == TMR0_FLAG_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup TMR0_Global_Functions TMR0 Global Functions + * @{ + */ + +/** + * @brief De-Initialize TMR0 function + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @retval None + */ +void TMR0_DeInit(CM_TMR0_TypeDef *TMR0x) +{ + uint32_t u32Ch; + __IO uint32_t *CNTR; + __IO uint32_t *CMPR; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + + WRITE_REG32(TMR0x->BCONR, 0UL); + WRITE_REG32(TMR0x->STFLR, 0UL); + for (u32Ch = 0UL; u32Ch < TMR0_CH_MAX; u32Ch++) { + CNTR = TMR0_CNTR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CNTR, 0UL); + CMPR = TMR0_CMPR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CMPR, 0x0000FFFFUL); + } +} + +/** + * @brief Initialize TMR0 function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] pstcTmr0Init Pointer to a @ref stc_tmr0_init_t. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: pstcTmr0Init is NULL + */ +int32_t TMR0_Init(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, const stc_tmr0_init_t *pstcTmr0Init) +{ + __IO uint32_t *CNTR; + __IO uint32_t *CMPR; + int32_t i32Ret = LL_OK; + + if (NULL == pstcTmr0Init) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_TMR0_CLK_SRC(pstcTmr0Init->u32ClockSrc)); + DDL_ASSERT(IS_TMR0_CLK_DIV(pstcTmr0Init->u32ClockDiv)); + DDL_ASSERT(IS_TMR0_FUNC(pstcTmr0Init->u32Func)); + + CNTR = TMR0_CNTR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CNTR, 0UL); + CMPR = TMR0_CMPR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CMPR, pstcTmr0Init->u16CompareValue); + MODIFY_REG32(TMR0x->BCONR, (TMR0_BCONR_CLR_MASK << TMR0_CH_OFFSET(u32Ch)), + ((pstcTmr0Init->u32ClockSrc | pstcTmr0Init->u32ClockDiv | + pstcTmr0Init->u32Func) << TMR0_CH_OFFSET(u32Ch))); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr0_init_t to default values. + * @param [out] pstcTmr0Init Pointer to a @ref stc_tmr0_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: pstcTmr0Init is NULL + */ +int32_t TMR0_StructInit(stc_tmr0_init_t *pstcTmr0Init) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcTmr0Init) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcTmr0Init->u32ClockSrc = TMR0_CLK_SRC_INTERN_CLK; + pstcTmr0Init->u32ClockDiv = TMR0_CLK_DIV1; + pstcTmr0Init->u32Func = TMR0_FUNC_CMP; + pstcTmr0Init->u16CompareValue = 0xFFFFU; + } + return i32Ret; +} + +/** + * @brief Start TMR0. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @retval None + */ +void TMR0_Start(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_CSTA << TMR0_CH_OFFSET(u32Ch))); +} + +/** + * @brief Stop TMR0. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @retval None + */ +void TMR0_Stop(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_CSTA << TMR0_CH_OFFSET(u32Ch))); +} + +/** + * @brief Set Tmr0 counter value. + * @note Setting the count requires stop tmr0. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] u16Value The data to write to the counter register + * @retval None + */ +void TMR0_SetCountValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value) +{ + __IO uint32_t *CNTR; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + CNTR = TMR0_CNTR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CNTR, u16Value); +} + +/** + * @brief Get Tmr0 counter value. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @retval uint16_t The counter register data + */ +uint16_t TMR0_GetCountValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch) +{ + __IO uint32_t *CNTR; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + CNTR = TMR0_CNTR_ADDR(TMR0x, u32Ch); + return (uint16_t)READ_REG32(*CNTR); +} + +/** + * @brief Set Tmr0 compare value. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] u16Value The data to write to the compare register + * @retval None + */ +void TMR0_SetCompareValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value) +{ + __IO uint32_t *CMPR; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + CMPR = TMR0_CMPR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CMPR, u16Value); +} + +/** + * @brief Get Tmr0 compare value. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @retval The compare register data + */ +uint16_t TMR0_GetCompareValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch) +{ + __IO uint32_t *CMPR; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + CMPR = TMR0_CMPR_ADDR(TMR0x, u32Ch); + return (uint16_t)READ_REG32(*CMPR); +} + +/** + * @brief Set clock source. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] u32Src Specifies the clock source + * This parameter can be a value of the following: + * @arg @ref TMR0_Clock_Source + * @retval None + */ +void TMR0_SetClockSrc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Src) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_TMR0_CLK_SRC(u32Src)); + + MODIFY_REG32(TMR0x->BCONR, (TMR0_CLK_SRC_MASK << TMR0_CH_OFFSET(u32Ch)), (u32Src << TMR0_CH_OFFSET(u32Ch))); +} + +/** + * @brief Set the division of clock. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] u32Div Specifies the clock source division + * This parameter can be a value of the following: + * @arg TMR0_CLK_DIV1: Clock source / 1 + * @arg TMR0_CLK_DIV2: Clock source / 2 + * @arg TMR0_CLK_DIV4: Clock source / 4 + * @arg TMR0_CLK_DIV8: Clock source / 8 + * @arg TMR0_CLK_DIV16: Clock source / 16 + * @arg TMR0_CLK_DIV32: Clock source / 32 + * @arg TMR0_CLK_DIV64: Clock source / 64 + * @arg TMR0_CLK_DIV128: Clock source / 128 + * @arg TMR0_CLK_DIV256: Clock source / 256 + * @arg TMR0_CLK_DIV512: Clock source / 512 + * @arg TMR0_CLK_DIV1024: Clock source / 1024 + * @retval None. + */ +void TMR0_SetClockDiv(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Div) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_TMR0_CLK_DIV(u32Div)); + + MODIFY_REG32(TMR0x->BCONR, (TMR0_BCONR_CKDIVA << TMR0_CH_OFFSET(u32Ch)), (u32Div << TMR0_CH_OFFSET(u32Ch))); +} + +/** + * @brief Set Tmr0 Function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] u32Func Select TMR0 function + * This parameter can be a value of the following: + * @arg TMR0_FUNC_CMP: Select the Compare function + * @arg TMR0_FUNC_CAPT: Select the Capture function + * @retval None + */ +void TMR0_SetFunc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Func) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_TMR0_FUNC(u32Func)); + + MODIFY_REG32(TMR0x->BCONR, ((TMR0_BCONR_CAPMDA | TMR0_BCONR_HICPA) << TMR0_CH_OFFSET(u32Ch)), + (u32Func << TMR0_CH_OFFSET(u32Ch))); +} + +/** + * @brief Enable or disable HardWare trigger capture function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR0_HWCaptureCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HICPA << TMR0_CH_OFFSET(u32Ch))); + } else { + CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HICPA << TMR0_CH_OFFSET(u32Ch))); + } +} + +/** + * @brief Enable or disable HardWare trigger start function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR0_HWStartCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HSTAA << TMR0_CH_OFFSET(u32Ch))); + } else { + CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HSTAA << TMR0_CH_OFFSET(u32Ch))); + } +} + +/** + * @brief Enable or disable HardWare trigger stop function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR0_HWStopCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HSTPA << TMR0_CH_OFFSET(u32Ch))); + } else { + CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HSTPA << TMR0_CH_OFFSET(u32Ch))); + } +} + +/** + * @brief Enable or disable HardWare trigger clear function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR0_HWClearCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HCLEA << TMR0_CH_OFFSET(u32Ch))); + } else { + CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HCLEA << TMR0_CH_OFFSET(u32Ch))); + } +} + +/** + * @brief Enable or disable specified Tmr0 interrupt. + * @note The comparison matching interrupt of channel 'TMR0_INT_CMP_A' in unit 'CM_TMR0_1' is only available in asynchronous counting mode. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32IntType TMR0 interrupt type + * This parameter can be any combination value of the following values: + * @arg @ref TMR0_Interrupt. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR0_IntCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32IntType, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG32_BIT(TMR0x->BCONR, u32IntType); + } else { + CLR_REG32_BIT(TMR0x->BCONR, u32IntType); + } +} + +/** + * @brief Get Tmr0 status. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Flag TMR0 flag type + * This parameter can be any combination value of the following values: + * @arg @ref TMR0_FLAG + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t TMR0_GetStatus(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(TMR0x->STFLR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear Tmr0 status. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Flag TMR0 flag type + * This parameter can be any combination value of the following values: + * @arg @ref TMR0_FLAG + * @retval None + */ +void TMR0_ClearStatus(CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_FLAG(u32Flag)); + + CLR_REG32_BIT(TMR0x->STFLR, u32Flag); +} + +/** + * @} + */ + +#endif /* LL_TMR0_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_tmr4.c b/mcu/lib/src/hc32_ll_tmr4.c new file mode 100644 index 0000000..fad6578 --- /dev/null +++ b/mcu/lib/src/hc32_ll_tmr4.c @@ -0,0 +1,2253 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr4.c + * @brief This file provides firmware functions to manage the TMR4(Timer4). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-10-31 CDT Modify macro-define: TMR4_OCSR_MASK + Re-name parameter u16IntType to u32IntType + 2023-01-15 CDT Add RCSR register data type + 2023-06-30 CDT Add function comments: macros group @ref TMR4_OC_Channel + Modify function return value comments: TMR4_OC_GetPolarity + Modify function parameter comments: TMR4_PWM_SetPolarity + Modify typo + Modify function: TMR4_DeInit, TMR4_OC_DeInit, TMR4_PWM_DeInit, TMR4_EVT_DeInit + Modify macro-definition: IS_TMR4_OC_BUF_OBJECT + Fix magic number of function: TMR4_OC_StructInit + 2023-09-30 CDT Fix spell error about "response" that in function name + Modify fuction:TMR4_PWM_Init + Modify comment + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_tmr4.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TMR4 TMR4 + * @brief TMR4 Driver Library + * @{ + */ + +#if (LL_TMR4_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR4_Local_Macros TMR4 Local Macros + * @{ + */ + +/** + * @defgroup TMR4_Check_Parameters_Validity TMR4 Check Parameters Validity + * @{ + */ +#define IS_TMR4_UNIT(x) \ +( ((x) == CM_TMR4_1) || \ + ((x) == CM_TMR4_2) || \ + ((x) == CM_TMR4_3)) + +#define IS_TMR4_CLK_DIV(x) \ +( ((x) == TMR4_CLK_DIV1) || \ + ((x) == TMR4_CLK_DIV2) || \ + ((x) == TMR4_CLK_DIV4) || \ + ((x) == TMR4_CLK_DIV8) || \ + ((x) == TMR4_CLK_DIV16) || \ + ((x) == TMR4_CLK_DIV32) || \ + ((x) == TMR4_CLK_DIV64) || \ + ((x) == TMR4_CLK_DIV128) || \ + ((x) == TMR4_CLK_DIV256) || \ + ((x) == TMR4_CLK_DIV512) || \ + ((x) == TMR4_CLK_DIV1024)) + +#define IS_TMR4_MD(x) \ +( ((x) == TMR4_MD_SAWTOOTH) || \ + ((x) == TMR4_MD_TRIANGLE)) + +#define IS_TMR4_CLK_SRC(x) \ +( ((x) == TMR4_CLK_SRC_INTERNCLK) || \ + ((x) == TMR4_CLK_SRC_EXTCLK)) + +#define IS_TMR4_INT_CNT_MASKTIME(x) ((x) <= TMR4_INT_CNT_MASK15) + +#define IS_TMR4_INT_CNT(x) \ +( ((x) != 0UL) && \ + (((x) | TMR4_INT_CNT_MASK) == TMR4_INT_CNT_MASK)) + +#define IS_TMR4_INT(x) \ +( ((x) != 0UL) && \ + (((x) | TMR4_INT_ALL) == TMR4_INT_ALL)) + +#define IS_TMR4_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | TMR4_FLAG_ALL) == TMR4_FLAG_ALL)) + +#define IS_TMR4_OC_HIGH_CH(x) (((x) & 0x1UL) == 0UL) +#define IS_TMR4_OC_LOW_CH(x) (((x) & 0x1UL) == 1UL) + +#define IS_TMR4_OC_BUF_OBJECT(x) \ +( (((x) | TMR4_OC_BUF_OBJECT_MASK) == TMR4_OC_BUF_OBJECT_MASK)) + +#define IS_TMR4_OC_BUF_COND(x) \ +( ((x) == TMR4_OC_BUF_COND_IMMED) || \ + ((x) == TMR4_OC_BUF_COND_PEAK) || \ + ((x) == TMR4_OC_BUF_COND_VALLEY) || \ + ((x) == TMR4_OC_BUF_COND_PEAK_VALLEY)) + +#define IS_TMR4_OC_INVD_POLARITY(x) \ +( ((x) == TMR4_OC_INVD_LOW) || \ + ((x) == TMR4_OC_INVD_HIGH)) + +#define IS_TMR4_PWM_MD(x) \ +( ((x) == TMR4_PWM_MD_THROUGH) || \ + ((x) == TMR4_PWM_MD_DEAD_TMR) || \ + ((x) == TMR4_PWM_MD_DEAD_TMR_FILTER)) + +#define IS_TMR4_PWM_POLARITY(x) \ +( ((x) == TMR4_PWM_OXH_HOLD_OXL_HOLD) || \ + ((x) == TMR4_PWM_OXH_INVT_OXL_HOLD) || \ + ((x) == TMR4_PWM_OXH_HOLD_OXL_INVT) || \ + ((x) == TMR4_PWM_OXH_INVT_OXL_INVT)) + +#define IS_TMR4_PWM_CLK_DIV(x) (((x) | TMR4_PWM_CLK_DIV128) == TMR4_PWM_CLK_DIV128) + +#define IS_TMR4_PWM_DEADTIME_REG_IDX(x) \ +( ((x) == TMR4_PWM_PDAR_IDX) || \ + ((x) == TMR4_PWM_PDBR_IDX)) + +#define IS_TMR4_PWM_OE_EFFECT(x) \ +( ((x) == TMR4_PWM_OE_EFFECT_IMMED) || \ + ((x) == TMR4_PWM_OE_EFFECT_COUNT_PEAK) || \ + ((x) == TMR4_PWM_OE_EFFECT_COUNT_VALLEY)) + +#define IS_TMR4_PWM_PIN_MD(x) \ +( ((x) == TMR4_PWM_PIN_OUTPUT_OS) || \ + ((x) == TMR4_PWM_PIN_OUTPUT_NORMAL)) + +#define IS_TMR4_EVT_MATCH_COND(x) (((x) | TMR4_EVT_MATCH_CNT_ALL) == TMR4_EVT_MATCH_CNT_ALL) + +#define IS_TMR4_EVT_MASK_TYPE(x) \ +( ((x) != 0U) || \ + (((x) | TMR4_EVT_MASK_TYPE_ALL) == TMR4_EVT_MASK_TYPE_ALL)) + +#define IS_TMR4_EVT_DELAY_OBJECT(x) \ +( ((x) == TMR4_EVT_DELAY_OCCRXH) || \ + ((x) == TMR4_EVT_DELAY_OCCRXL)) + +#define IS_TMR4_EVT_MD(x) \ +( ((x) == TMR4_EVT_MD_DELAY) || \ + ((x) == TMR4_EVT_MD_CMP)) + +#define IS_TMR4_EVT_MASK(x) (((x) | TMR4_EVT_MASK15) == TMR4_EVT_MASK15) + +#define IS_TMR4_EVT_BUF_COND(x) \ +( ((x) == TMR4_EVT_BUF_COND_IMMED) || \ + ((x) == TMR4_EVT_BUF_COND_PEAK) || \ + ((x) == TMR4_EVT_BUF_COND_VALLEY) || \ + ((x) == TMR4_EVT_BUF_COND_PEAK_VALLEY)) + +#define IS_TMR4_OC_CH(x) ((x) <= TMR4_OC_CH_WL) +#define IS_TMR4_PWM_CH(x) ((x) <= TMR4_PWM_CH_W) +#define IS_TMR4_PWM_PIN(x) ((x) <= TMR4_PWM_PIN_OWL) +#define IS_TMR4_EVT_CH(x) ((x) <= TMR4_EVT_CH_WL) +#define IS_TMR4_EVT_OUTPUT_EVT(x) \ +( ((x) >> TMR4_SCSR_EVTOS_POS) <= (TMR4_EVT_OUTPUT_EVT5 >> TMR4_SCSR_EVTOS_POS)) +#define IS_TMR4_EVT_OUTPUT_SIGNAL(x) ((x) <= TMR4_EVT_OUTPUT_EVT5_SIGNAL) + +#define IS_TMR4_PWM_ABNORMAL_PIN_STAT(x) ((x) <= TMR4_PWM_ABNORMAL_PIN_HOLD) +/** + * @} + */ + +/** + * @defgroup TMR4_Channel_Max TMR4 Channel Max + * @{ + */ +#define TMR4_OC_CH_MAX (TMR4_OC_CH_WL) +#define TMR4_PWM_CH_MAX (TMR4_PWM_CH_W) +#define TMR4_EVT_CH_MAX (TMR4_EVT_CH_WL) +/** + * @} + */ + +/** + * @defgroup TMR4_Flag_Interrupt_Mask TMR4 Flag and Interrupt Mask + * @{ + */ +#define TMR4_FLAG_CNT_MASK (TMR4_FLAG_CNT_PEAK | TMR4_FLAG_CNT_VALLEY) +#define TMR4_INT_CNT_MASK (TMR4_INT_CNT_PEAK | TMR4_INT_CNT_VALLEY) + +#define TMR4_FLAG_OC_MASK (TMR4_FLAG_OC_CMP_UH | TMR4_FLAG_OC_CMP_UL | TMR4_FLAG_OC_CMP_VH | \ + TMR4_FLAG_OC_CMP_VL | TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL) +#define TMR4_INT_OC_MASK (TMR4_INT_OC_CMP_UH | TMR4_INT_OC_CMP_UL | TMR4_INT_OC_CMP_VH | \ + TMR4_INT_OC_CMP_VL | TMR4_INT_OC_CMP_WH | TMR4_INT_OC_CMP_WL) + +#define TMR4_FLAG_RELOAD_TMR_MASK (TMR4_FLAG_RELOAD_TMR_U | TMR4_FLAG_RELOAD_TMR_V | TMR4_FLAG_RELOAD_TMR_W) +#define TMR4_INT_RELOAD_TMR_MASK (TMR4_INT_RELOAD_TMR_U | TMR4_INT_RELOAD_TMR_V | TMR4_INT_RELOAD_TMR_W) + +/** + * @} + */ + +#define RCSR_REG_TYPE uint16_t + +/** + * @defgroup TMR4_Registers_Reset_Value TMR4 Registers Reset Value + * @{ + */ +#define TMR4_CCSR_RST_VALUE (0x0040U) +#define TMR4_SCER_RST_VALUE (0xFF00U) +#define TMR4_SCMR_RST_VALUE (0xFF00U) +#define TMR4_POCR_RST_VALUE (0xFF00U) +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Buffer_Object_Mask TMR4 OC Buffer Object Mask + * @{ + */ +#define TMR4_OC_BUF_OBJECT_MASK (TMR4_OC_BUF_CMP_VALUE | TMR4_OC_BUF_CMP_MD) +/** + * @} + */ + +/** + * @defgroup TMR4_OCSR_Bit_Mask TMR4_OCSR Bit Mask + * @brief Get the specified TMR4_OCSR register bis value of the specified TMR4 OC channel + * @{ + */ +#define TMR4_OCSR_OCEx_MASK(CH) (((uint16_t)TMR4_OCSR_OCEH) << ((CH) % 2UL)) +#define TMR4_OCSR_OCPx_MASK(CH) (((uint16_t)TMR4_OCSR_OCPH) << ((CH) % 2UL)) +#define TMR4_OCSR_OCIE_MASK (TMR4_OCSR_OCIEH | TMR4_OCSR_OCIEL) +#define TMR4_OCSR_OCF_MASK (TMR4_OCSR_OCFH | TMR4_OCSR_OCFL) +#define TMR4_OCSR_MASK(CH) \ +( ((uint16_t)(TMR4_OCSR_OCEH | TMR4_OCSR_OCPH | TMR4_OCSR_OCIEH | TMR4_OCSR_OCFH)) << (((CH) % 2UL))) +/** + * @} + */ + +/** + * @defgroup TMR4_OCSR_Bit TMR4_OCSR Bit + * @brief Get the specified TMR4_OCSR register bis value of the specified TMR4 OC channel + * @{ + */ +#define TMR4_OCSR_OCEx(CH, OCEx) (((uint16_t)OCEx) << (((uint16_t)((CH) % 2UL)) + TMR4_OCSR_OCEH_POS)) +#define TMR4_OCSR_OCPx(CH, OCPx) (((uint16_t)OCPx) << ((CH) % 2UL)) +#define TMR4_OCSR_OCIEx(CH, OCIEx) (((uint16_t)OCIEx) << ((CH) % 2UL)) +#define TMR4_OCSR_OCFx(CH, OCFx) (((uint16_t)OCFx) << ((CH) % 2UL)) +/** + * @} + */ + +/** + * @defgroup TMR4_OCER_Bit_Mask TMR4_OCER Bit Mask + * @brief Get the specified TMR4_OCER register bis value of the specified TMR4 OC channel + * @{ + */ +#define TMR4_OCER_CxBUFEN_MASK(CH) (((uint16_t)TMR4_OCER_CHBUFEN) << (((CH) % 2UL) << 1U)) +#define TMR4_OCER_MxBUFEN_MASK(CH) (((uint16_t)TMR4_OCER_MHBUFEN) << (((CH) % 2UL) << 1U)) +#define TMR4_OCER_LMCx_MASK(CH) (((uint16_t)TMR4_OCER_LMCH) << ((CH) % 2UL)) +#define TMR4_OCER_LMMx_MASK(CH) (((uint16_t)TMR4_OCER_LMMH) << ((CH) % 2UL)) +#define TMR4_OCER_MCECx_MASK(CH) (((uint16_t)TMR4_OCER_MCECH) << ((CH) % 2UL)) +#define TMR4_OCER_MASK(CH) \ +( (((uint16_t)(TMR4_OCER_CHBUFEN | TMR4_OCER_MHBUFEN)) << (((CH) % 2UL) << 1U)) | \ + (((uint16_t)(TMR4_OCER_LMCH | TMR4_OCER_LMMH | TMR4_OCER_MCECH)) << ((CH) % 2UL))) +/** + * @} + */ + +/** + * @defgroup TMR4_OCER_Bit TMR4_OCER Bit + * @brief Get the specified TMR4_OCER register bis value of the specified TMR4 OC channel + * @{ + */ +#define TMR4_OCER_CxBUFEN(CH, CxBUFEN) ((uint16_t)((uint16_t)(CxBUFEN) << ((((CH) % 2UL) << 1U) + TMR4_OCER_CHBUFEN_POS))) +#define TMR4_OCER_MxBUFEN(CH, MxBUFEN) ((uint16_t)((uint16_t)(MxBUFEN) << ((((CH) % 2UL) << 1U) + TMR4_OCER_MHBUFEN_POS))) +#define TMR4_OCER_LMCx(CH, LMCx) ((uint16_t)(LMCx) << ((((CH) % 2UL)) + TMR4_OCER_LMCH_POS)) +#define TMR4_OCER_LMMx(CH, LMMx) ((uint16_t)(LMMx) << ((((CH) % 2UL)) + TMR4_OCER_LMMH_POS)) +#define TMR4_OCER_MCECx(CH, MCECx) ((uint16_t)(MCECx) << ((((CH) % 2UL)) + TMR4_OCER_MCECH_POS)) +/** + * @} + */ + +/** + * @defgroup TMR4_RCSR_Bit_Mask TMR4_RCSR Bit Mask + * @brief Get the specified TMR4_RCSR register bis value of the specified TMR4 PWM channel + * @{ + */ +#define TMR4_RCSR_RTIDx_MASK(CH) ((RCSR_REG_TYPE)(((RCSR_REG_TYPE)TMR4_RCSR_RTIDU) << (CH))) +#define TMR4_RCSR_RTIFx_MASK(CH) ((RCSR_REG_TYPE)(((RCSR_REG_TYPE)TMR4_RCSR_RTIFU) << ((CH) << 2U))) +#define TMR4_RCSR_RTICx_MASK(CH) ((RCSR_REG_TYPE)(((RCSR_REG_TYPE)TMR4_RCSR_RTICU) << ((CH) << 2U))) +#define TMR4_RCSR_RTEx_MASK(CH) ((RCSR_REG_TYPE)(((RCSR_REG_TYPE)TMR4_RCSR_RTEU) << ((CH) << 2U))) +#define TMR4_RCSR_RTSx_MASK(CH) ((RCSR_REG_TYPE)(((RCSR_REG_TYPE)TMR4_RCSR_RTSU) << ((CH) << 2U))) +#define TMR4_RCSR_MASK(CH) (TMR4_RCSR_RTIDx_MASK(CH) | TMR4_RCSR_RTIFx_MASK(CH) | TMR4_RCSR_RTICx_MASK(CH) | \ + TMR4_RCSR_RTEx_MASK(CH) | TMR4_RCSR_RTSx_MASK(CH)) +/** + * @} + */ + +/** + * @defgroup TMR4_Register TMR4 Register + * @{ + */ +#define TMR4_REG_ADDR(_REG_) ((uint32_t)(&(_REG_))) +#define TMR4_REG16(_ADDR_) ((__IO uint16_t *)(_ADDR_)) +#define TMR4_REG32(_ADDR_) ((__IO uint32_t *)(_ADDR_)) +#define TMR4_RCSR_REG(_ADDR_) ((__IO RCSR_REG_TYPE *)(_ADDR_)) + +/** + * @defgroup TMR4_OC_Register_UVW TMR4 OC Register + * @brief Get the specified OC register address of the specified TMR4 unit + * @{ + */ +#define _TMR4_OCCR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->OCCRUH) + ((CH) << 2U)) +#define _TMR4_OCMR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->OCMRHUH) + ((CH) << 2U)) +#define _TMR4_OCER(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->OCERU) + (((CH) & 0x06UL) << 1U)) +#define _TMR4_OCSR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->OCSRU) + (((CH) & 0x06UL) << 1U)) +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Register_UVW TMR4 PWM Register + * @brief Get the specified PWM register address of the specified TMR4 unit + * @{ + */ +#define _TMR4_RCSR(UNIT) TMR4_RCSR_REG(TMR4_REG_ADDR((UNIT)->RCSR)) +#define _TMR4_POCR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->POCRU) + ((CH) << 2U)) +#define _TMR4_PFSR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->PFSRU) + ((CH) << 3U)) +#define _TMR4_PDR(UNIT, CH, IDX) TMR4_REG16(TMR4_REG_ADDR((UNIT)->PDARU) + ((CH) << 3U) + ((IDX) << 1U)) +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Register_UVW TMR4 Event Register + * @brief Get the specified event register address of the specified TMR4 unit + * @{ + */ +#define _TMR4_SCCR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->SCCRUH) + ((CH) << 2U)) +#define _TMR4_SCSR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->SCSRUH) + ((CH) << 2U)) +#define _TMR4_SCMR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->SCMRUH) + ((CH) << 2U)) +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Register TMR4 OC Register + * @{ + */ +#define TMR4_OCCR(UNIT, CH) _TMR4_OCCR(UNIT, CH) +#define TMR4_OCMR(UNIT, CH) _TMR4_OCMR(UNIT, CH) +#define TMR4_OCER(UNIT, CH) _TMR4_OCER(UNIT, CH) +#define TMR4_OCSR(UNIT, CH) _TMR4_OCSR(UNIT, CH) +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Register TMR4 PWM Register + * @{ + */ +#define TMR4_RCSR(UNIT) _TMR4_RCSR(UNIT) +#define TMR4_POCR(UNIT, CH) _TMR4_POCR(UNIT, CH) +#define TMR4_PFSR(UNIT, CH) _TMR4_PFSR(UNIT, CH) +#define TMR4_PDR(UNIT, CH, IDX) _TMR4_PDR(UNIT, CH, IDX) +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Register TMR4 Event Register + * @{ + */ +#define TMR4_SCCR(UNIT, CH) _TMR4_SCCR(UNIT, CH) +#define TMR4_SCSR(UNIT, CH) _TMR4_SCSR(UNIT, CH) +#define TMR4_SCMR(UNIT, CH) _TMR4_SCMR(UNIT, CH) +/** + * @} + */ + +/** + * @defgroup TMR4_ECER_Register EMB Expand Control Register + * @brief Get the specified EVT register address of the specified TMR4 unit + * @{ + */ +#define TMR4_ECER(UNITx) \ +( ((UNITx) == CM_TMR4_1) ? (&CM_TMR4CR->ECER1) : \ + (((UNITx) == CM_TMR4_2) ? (&CM_TMR4CR->ECER2) : (&CM_TMR4CR->ECER3))) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup TMR4_Global_Functions TMR4 Global Functions + * @{ + */ + +/** + * @defgroup TMR4_Counter_Global_Functions TMR4 Counter Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_tmr4_init_t to default values + * @param [out] pstcTmr4Init Pointer to a @ref stc_tmr4_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcCntInit value is NULL. + */ +int32_t TMR4_StructInit(stc_tmr4_init_t *pstcTmr4Init) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4Init) { + pstcTmr4Init->u16PeriodValue = 0xFFFFU; + pstcTmr4Init->u16CountMode = TMR4_MD_SAWTOOTH; + pstcTmr4Init->u16ClockSrc = TMR4_CLK_SRC_INTERNCLK; + pstcTmr4Init->u16ClockDiv = TMR4_CLK_DIV1; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] pstcTmr4Init Pointer to a @ref stc_tmr4_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcCntInit value is NULL. + */ +int32_t TMR4_Init(CM_TMR4_TypeDef *TMR4x, const stc_tmr4_init_t *pstcTmr4Init) +{ + uint16_t u16Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4Init) { + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_CLK_SRC(pstcTmr4Init->u16ClockSrc)); + DDL_ASSERT(IS_TMR4_CLK_DIV(pstcTmr4Init->u16ClockDiv)); + DDL_ASSERT(IS_TMR4_MD(pstcTmr4Init->u16CountMode)); + + /* Set TMR4_CCSR */ + u16Value = (pstcTmr4Init->u16ClockDiv | pstcTmr4Init->u16ClockSrc | \ + pstcTmr4Init->u16CountMode | TMR4_CCSR_CLEAR | TMR4_CCSR_STOP); + WRITE_REG16(TMR4x->CCSR, u16Value); + + /* Set TMR4_CVPR: default value */ + WRITE_REG16(TMR4x->CVPR, 0x0000U); + + /* Set TMR4 period */ + WRITE_REG16(TMR4x->CPSR, pstcTmr4Init->u16PeriodValue); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-Initialize TMR4 counter function + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval int32_t: + * - LL_OK: Reset success. + */ +int32_t TMR4_DeInit(CM_TMR4_TypeDef *TMR4x) +{ + uint32_t u32Ch; + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + /* Configures the registers to reset value. */ + WRITE_REG16(TMR4x->CCSR, TMR4_CCSR_RST_VALUE); + WRITE_REG16(TMR4x->CPSR, 0xFFFFU); + WRITE_REG16(TMR4x->CVPR, 0x0000U); + WRITE_REG16(TMR4x->CNTR, 0x0000U); + + /* De-initialize OC */ + for (u32Ch = 0UL; u32Ch <= TMR4_OC_CH_MAX; u32Ch++) { + TMR4_OC_DeInit(TMR4x, u32Ch); + } + + /* De-initialize PWM */ + for (u32Ch = 0UL; u32Ch <= TMR4_PWM_CH_MAX; u32Ch++) { + TMR4_PWM_DeInit(TMR4x, u32Ch); + } + + /* De-initialize special event */ + for (u32Ch = 0UL; u32Ch <= TMR4_OC_CH_MAX; u32Ch++) { + TMR4_EVT_DeInit(TMR4x, u32Ch); + } + + return i32Ret; +} + +/** + * @brief Set TMR4 counter clock source + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Src TMR4 counter clock source + * This parameter can be one of the macros group @ref TMR4_Count_Clock_Source + * @arg TMR4_CLK_SRC_INTERNCLK: Uses the internal clock as counter's count clock + * @arg TMR4_CLK_SRC_EXTCLK: Uses an external input clock as counter's count clock + * @retval None + * @note The clock division function is valid when clock source is internal clock. + */ +void TMR4_SetClockSrc(CM_TMR4_TypeDef *TMR4x, uint16_t u16Src) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_CLK_SRC(u16Src)); + + MODIFY_REG16(TMR4x->CCSR, TMR4_CCSR_ECKEN, u16Src); +} + +/** + * @brief Set TMR4 counter clock division + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Div TMR4 clock division + * This parameter can be one of the macros group @ref TMR4_Count_Clock_Division + * @arg TMR4_CLK_DIV1: CLK + * @arg TMR4_CLK_DIV2: CLK/2 + * @arg TMR4_CLK_DIV4: CLK/4 + * @arg TMR4_CLK_DIV8: CLK/8 + * @arg TMR4_CLK_DIV16: CLK/16 + * @arg TMR4_CLK_DIV32: CLK/32 + * @arg TMR4_CLK_DIV64: CLK/64 + * @arg TMR4_CLK_DIV128: CLK/128 + * @arg TMR4_CLK_DIV256: CLK/256 + * @arg TMR4_CLK_DIV512: CLK/512 + * @arg TMR4_CLK_DIV1024: CLK/1024 + * @retval None + * @note The clock division function is valid when clock source is the internal clock. + */ +void TMR4_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint16_t u16Div) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_CLK_DIV(u16Div)); + + MODIFY_REG16(TMR4x->CCSR, TMR4_CCSR_CKDIV, u16Div); +} + +/** + * @brief Set TMR4 counter count mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Mode TMR4 counter count mode + * This parameter can be one of the macros group @ref TMR4_Count_Mode + * @arg TMR4_MD_SAWTOOTH: TMR4 count mode sawtooth wave + * @arg TMR4_MD_TRIANGLE: TMR4 count mode triangular + * @retval None + */ +void TMR4_SetCountMode(CM_TMR4_TypeDef *TMR4x, uint16_t u16Mode) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_MD(u16Mode)); + + MODIFY_REG16(TMR4x->CCSR, TMR4_CCSR_MODE, u16Mode); +} + +/** + * @brief Get the period value of the TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval The period value of the TMR4 counter + */ +uint16_t TMR4_GetPeriodValue(const CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + return READ_REG16(TMR4x->CPSR); +} + +/** + * @brief Set the period value of the TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Value The period value of the TMR4 counter + * @arg number of 16bit + * @retval None + */ +void TMR4_SetPeriodValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + WRITE_REG16(TMR4x->CPSR, u16Value); +} + +/** + * @brief Get the count value of the TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval The count value of the TMR4 counter + */ +uint16_t TMR4_GetCountValue(const CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + return READ_REG16(TMR4x->CNTR); +} + +/** + * @brief Set the count value of the TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Value The count value of the TMR4 counter + * @arg number of 16bit + * @retval None + */ +void TMR4_SetCountValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + WRITE_REG16(TMR4x->CNTR, u16Value); +} + +/** + * @brief Clear TMR4 counter count value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval None + */ +void TMR4_ClearCountValue(CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + SET_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_CLEAR); +} + +/** + * @brief Start TMR4 counter + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval None + */ +void TMR4_Start(CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + CLR_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_STOP); +} + +/** + * @brief Stop TMR4 counter + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval None + */ +void TMR4_Stop(CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + SET_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_STOP); +} + +/** + * @brief Clear TMR4 flag + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Flag TMR4 flag + * This parameter can be any composed value of the macros group @ref TMR4_Flag + * @retval None + */ +void TMR4_ClearStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag) +{ + uint32_t u32ClearFlag; + __IO uint16_t *OCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_FLAG(u32Flag)); + + /* Counter flag */ + if ((u32Flag & TMR4_FLAG_CNT_MASK) > 0UL) { + CLR_REG16_BIT(TMR4x->CCSR, (u32Flag & TMR4_FLAG_CNT_MASK)); + } + + /* Output-compare flag */ + u32ClearFlag = (u32Flag & TMR4_FLAG_OC_MASK); + if (u32ClearFlag > 0UL) { + /* TMR4_OCSRU */ + u32ClearFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_UH | TMR4_FLAG_OC_CMP_UL)) >> 10U); + if (u32ClearFlag > 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_UH); + CLR_REG16_BIT(*OCSR, u32ClearFlag); + } + + /* TMR4_OCSRV */ + u32ClearFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_VH | TMR4_FLAG_OC_CMP_VL)) >> 12U); + if (u32ClearFlag > 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_VH); + CLR_REG16_BIT(*OCSR, u32ClearFlag); + } + + /* TMR4_OCSRW */ + u32ClearFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL)) >> 14U); + if (u32ClearFlag > 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_WH); + CLR_REG16_BIT(*OCSR, u32ClearFlag); + } + } + + /* PWM reload timer flag */ + u32ClearFlag = ((u32Flag & TMR4_FLAG_RELOAD_TMR_MASK) << 5U); + if (u32ClearFlag > 0UL) { + SET_REG_BIT(TMR4x->RCSR, (RCSR_REG_TYPE)u32ClearFlag); + } +} + +/** + * @brief Get TMR4 flag + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Flag TMR4 flag + * This parameter can be any composed value of the macros group @ref TMR4_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t TMR4_GetStatus(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag) +{ + uint32_t u32ReadFlag; + uint8_t u8FlagSetCount = 0; + __IO uint16_t *OCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_FLAG(u32Flag)); + + /* Counter flag status */ + if (READ_REG16_BIT(TMR4x->CCSR, (u32Flag & TMR4_FLAG_CNT_MASK)) > 0U) { + u8FlagSetCount++; + } + + /* Output-compare interrupt */ + u32ReadFlag = (u32Flag & TMR4_FLAG_OC_MASK); + if (u32ReadFlag > 0UL) { + /* TMR4_OCSRU */ + u32ReadFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_UH | TMR4_FLAG_OC_CMP_UL)) >> 10U); + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_UH); + if (READ_REG16_BIT(*OCSR, u32ReadFlag) > 0U) { + u8FlagSetCount++; + } + + /* TMR4_OCSRV */ + u32ReadFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_VH | TMR4_FLAG_OC_CMP_VL)) >> 12U); + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_VH); + if (READ_REG16_BIT(*OCSR, u32ReadFlag) > 0U) { + u8FlagSetCount++; + } + + /* TMR4_OCSRW */ + u32ReadFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL)) >> 14U); + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_WH); + if (READ_REG16_BIT(*OCSR, u32ReadFlag) > 0U) { + u8FlagSetCount++; + } + } + + /* PWM reload timer flag status */ + u32ReadFlag = ((u32Flag & (TMR4_FLAG_RELOAD_TMR_MASK)) << 4U); + if (READ_REG_BIT(TMR4x->RCSR, (RCSR_REG_TYPE)u32ReadFlag) > 0U) { + u8FlagSetCount++; + } + + return (u8FlagSetCount == 0U) ? RESET : SET; +} + +/** + * @brief Enable or disable the specified TMR4 interrupt + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32IntType TMR4 interrupt source + * This parameter can be any composed value of the macros group @ref TMR4_Interrupt + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_IntCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint32_t u32Type; + __IO uint16_t *OCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Counter interrupt */ + u32Type = (u32IntType & TMR4_INT_CNT_MASK); + if (u32Type > 0UL) { + (ENABLE == enNewState) ? SET_REG16_BIT(TMR4x->CCSR, u32Type) : CLR_REG16_BIT(TMR4x->CCSR, u32Type); + } + + /* Output-compare interrupt */ + u32Type = (u32IntType & TMR4_INT_OC_MASK); + if (u32Type > 0UL) { + /* TMR4_OCSRU */ + u32Type = ((u32IntType & (TMR4_INT_OC_CMP_UH | TMR4_INT_OC_CMP_UL)) >> 12U); + if (u32Type != 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_UH); + (ENABLE == enNewState) ? SET_REG16_BIT(*OCSR, u32Type) : CLR_REG16_BIT(*OCSR, u32Type); + } + + /* TMR4_OCSRV */ + u32Type = ((u32IntType & (TMR4_INT_OC_CMP_VH | TMR4_INT_OC_CMP_VL)) >> 14U); + if (u32Type != 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_VH); + (ENABLE == enNewState) ? SET_REG16_BIT(*OCSR, u32Type) : CLR_REG16_BIT(*OCSR, u32Type); + } + + /* TMR4_OCSRW */ + u32Type = ((u32IntType & (TMR4_INT_OC_CMP_WH | TMR4_INT_OC_CMP_WL)) >> 16U); + if (u32Type != 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_WH); + (ENABLE == enNewState) ? SET_REG16_BIT(*OCSR, u32Type) : CLR_REG16_BIT(*OCSR, u32Type); + } + } + + /* PWM reload timer interrupt */ + u32Type = (u32IntType & TMR4_INT_RELOAD_TMR_MASK); + if (u32Type > 0UL) { + (ENABLE == enNewState) ? CLR_REG_BIT(TMR4x->RCSR, (RCSR_REG_TYPE)u32Type) : SET_REG_BIT(TMR4x->RCSR, (RCSR_REG_TYPE)u32Type); + } +} + +/** + * @brief Enable or disable the TMR4 counter period buffer function. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_PeriodBufCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_BUFEN); + } else { + CLR_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_BUFEN); + } +} + +/** + * @brief Get TMR4 count interrupt mask times + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32IntType TMR4 interrupt source + * This parameter can be one of the following values: + * @arg TMR4_INT_CNT_PEAK: Count peak interrupt + * @arg TMR4_INT_CNT_VALLEY : Count valley interrupt + * @retval Returned value can be one of the macros group @ref TMR4_Count_Interrupt_Mask_Time + * - TMR4_INT_CNT_MASK0: Counter interrupt flag is always set(not masked) for counter count every time at "0x0000" or peak + * - TMR4_INT_CNT_MASK1: Counter interrupt flag is set once when counter counts 2 times at "0x0000" or peak (skipping 1 count) + * - TMR4_INT_CNT_MASK2: Counter interrupt flag is set once when counter counts 3 times at "0x0000" or peak (skipping 2 count) + * - TMR4_INT_CNT_MASK3: Counter interrupt flag is set once when counter counts 4 times at "0x0000" or peak (skipping 3 count) + * - TMR4_INT_CNT_MASK4: Counter interrupt flag is set once when counter counts 5 times at "0x0000" or peak (skipping 4 count) + * - TMR4_INT_CNT_MASK5: Counter interrupt flag is set once when counter counts 6 times at "0x0000" or peak (skipping 5 count) + * - TMR4_INT_CNT_MASK6: Counter interrupt flag is set once when counter counts 7 times at "0x0000" or peak (skipping 6 count) + * - TMR4_INT_CNT_MASK7: Counter interrupt flag is set once when counter counts 8 times at "0x0000" or peak (skipping 7 count) + * - TMR4_INT_CNT_MASK8: Counter interrupt flag is set once when counter counts 9 times at "0x0000" or peak (skipping 8 count) + * - TMR4_INT_CNT_MASK9: Counter interrupt flag is set once when counter counts 10 times at "0x0000" or peak (skipping 9 count) + * - TMR4_INT_CNT_MASK10: Counter interrupt flag is set once when counter counts 11 times at "0x0000" or peak (skipping 10 count) + * - TMR4_INT_CNT_MASK11: Counter interrupt flag is set once when counter counts 12 times at "0x0000" or peak (skipping 11 count) + * - TMR4_INT_CNT_MASK12: Counter interrupt flag is set once when counter counts 13 times at "0x0000" or peak (skipping 12 count) + * - TMR4_INT_CNT_MASK13: Counter interrupt flag is set once when counter counts 14 times at "0x0000" or peak (skipping 13 count) + * - TMR4_INT_CNT_MASK14: Counter interrupt flag is set once when counter counts 15 times at "0x0000" or peak (skipping 14 count) + * - TMR4_INT_CNT_MASK15: Counter interrupt flag is set once when counter counts 16 times at "0x0000" or peak (skipping 15 count) + */ +uint16_t TMR4_GetCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType) +{ + uint16_t u16MaskTimes; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_INT_CNT(u32IntType)); + + if (TMR4_INT_CNT_VALLEY == u32IntType) { + u16MaskTimes = (READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_ZIM) >> TMR4_CVPR_ZIM_POS); + } else { + u16MaskTimes = (READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_PIM) >> TMR4_CVPR_PIM_POS); + } + + return u16MaskTimes; +} + +/** + * @brief Set TMR4 counter interrupt mask times + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32IntType TMR4 interrupt source + * This parameter can be one of the following values: + * @arg TMR4_INT_CNT_PEAK: Count peak interrupt + * @arg TMR4_INT_CNT_VALLEY : Count valley interrupt + * @param [in] u16MaskTime TMR4 counter interrupt mask times + * This parameter can be one of the macros group @ref TMR4_Count_Interrupt_Mask_Time + * @arg TMR4_INT_CNT_MASK0: Counter interrupt flag is always set(not masked) for counter count every time at "0x0000" or peak + * @arg TMR4_INT_CNT_MASK1: Counter interrupt flag is set once when counter counts 2 times at "0x0000" or peak (skipping 1 count) + * @arg TMR4_INT_CNT_MASK2: Counter interrupt flag is set once when counter counts 3 times at "0x0000" or peak (skipping 2 count) + * @arg TMR4_INT_CNT_MASK3: Counter interrupt flag is set once when counter counts 4 times at "0x0000" or peak (skipping 3 count) + * @arg TMR4_INT_CNT_MASK4: Counter interrupt flag is set once when counter counts 5 times at "0x0000" or peak (skipping 4 count) + * @arg TMR4_INT_CNT_MASK5: Counter interrupt flag is set once when counter counts 6 times at "0x0000" or peak (skipping 5 count) + * @arg TMR4_INT_CNT_MASK6: Counter interrupt flag is set once when counter counts 7 times at "0x0000" or peak (skipping 6 count) + * @arg TMR4_INT_CNT_MASK7: Counter interrupt flag is set once when counter counts 8 times at "0x0000" or peak (skipping 7 count) + * @arg TMR4_INT_CNT_MASK8: Counter interrupt flag is set once when counter counts 9 times at "0x0000" or peak (skipping 8 count) + * @arg TMR4_INT_CNT_MASK9: Counter interrupt flag is set once when counter counts 10 times at "0x0000" or peak (skipping 9 count) + * @arg TMR4_INT_CNT_MASK10: Counter interrupt flag is set once when counter counts 11 times at "0x0000" or peak (skipping 10 count) + * @arg TMR4_INT_CNT_MASK11: Counter interrupt flag is set once when counter counts 12 times at "0x0000" or peak (skipping 11 count) + * @arg TMR4_INT_CNT_MASK12: Counter interrupt flag is set once when counter counts 13 times at "0x0000" or peak (skipping 12 count) + * @arg TMR4_INT_CNT_MASK13: Counter interrupt flag is set once when counter counts 14 times at "0x0000" or peak (skipping 13 count) + * @arg TMR4_INT_CNT_MASK14: Counter interrupt flag is set once when counter counts 15 times at "0x0000" or peak (skipping 14 count) + * @arg TMR4_INT_CNT_MASK15: Counter interrupt flag is set once when counter counts 16 times at "0x0000" or peak (skipping 15 count) + * @retval None + */ +void TMR4_SetCountIntMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, uint16_t u16MaskTime) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_INT_CNT(u32IntType)); + DDL_ASSERT(IS_TMR4_INT_CNT_MASKTIME(u16MaskTime)); + + if (TMR4_INT_CNT_VALLEY == (u32IntType & TMR4_INT_CNT_VALLEY)) { + MODIFY_REG16(TMR4x->CVPR, TMR4_CVPR_ZIM, (u16MaskTime << TMR4_CVPR_ZIM_POS)); + } + + if (TMR4_INT_CNT_PEAK == (u32IntType & TMR4_INT_CNT_PEAK)) { + MODIFY_REG16(TMR4x->CVPR, TMR4_CVPR_PIM, (u16MaskTime << TMR4_CVPR_PIM_POS)); + } +} + +/** + * @brief Get TMR4 counter current interrupt mask times + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32IntType TMR4 interrupt source + * This parameter can be one of the macros group @ref TMR4_Interrupt + * @arg TMR4_INT_CNT_PEAK: Count peak interrupt + * @arg TMR4_INT_CNT_VALLEY : Count valley interrupt + * @retval Returned value can be one of the macros group @ref TMR4_Count_Interrupt_Mask_Time + * - TMR4_INT_CNT_MASK0: Counter interrupt flag is always set(not masked) for every counter count at "0x0000" or peak + * - TMR4_INT_CNT_MASK1: Counter interrupt flag is set once for 2 every counter counts at "0x0000" or peak (skipping 1 count) + * - TMR4_INT_CNT_MASK2: Counter interrupt flag is set once for 3 every counter counts at "0x0000" or peak (skipping 2 count) + * - TMR4_INT_CNT_MASK3: Counter interrupt flag is set once for 4 every counter counts at "0x0000" or peak (skipping 3 count) + * - TMR4_INT_CNT_MASK4: Counter interrupt flag is set once for 5 every counter counts at "0x0000" or peak (skipping 4 count) + * - TMR4_INT_CNT_MASK5: Counter interrupt flag is set once for 6 every counter counts at "0x0000" or peak (skipping 5 count) + * - TMR4_INT_CNT_MASK6: Counter interrupt flag is set once for 7 every counter counts at "0x0000" or peak (skipping 6 count) + * - TMR4_INT_CNT_MASK7: Counter interrupt flag is set once for 8 every counter counts at "0x0000" or peak (skipping 7 count) + * - TMR4_INT_CNT_MASK8: Counter interrupt flag is set once for 9 every counter counts at "0x0000" or peak (skipping 8 count) + * - TMR4_INT_CNT_MASK9: Counter interrupt flag is set once for 10 every counter counts at "0x0000" or peak (skipping 9 count) + * - TMR4_INT_CNT_MASK10: Counter interrupt flag is set once for 11 every counter counts at "0x0000" or peak (skipping 10 count) + * - TMR4_INT_CNT_MASK11: Counter interrupt flag is set once for 12 every counter counts at "0x0000" or peak (skipping 11 count) + * - TMR4_INT_CNT_MASK12: Counter interrupt flag is set once for 13 every counter counts at "0x0000" or peak (skipping 12 count) + * - TMR4_INT_CNT_MASK13: Counter interrupt flag is set once for 14 every counter counts at "0x0000" or peak (skipping 13 count) + * - TMR4_INT_CNT_MASK14: Counter interrupt flag is set once for 15 every counter counts at "0x0000" or peak (skipping 14 count) + * - TMR4_INT_CNT_MASK15: Counter interrupt flag is set once for 16 every counter counts at "0x0000" or peak (skipping 15 count) + */ +uint16_t TMR4_GetCurrentCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType) +{ + uint16_t u16MaskTimes; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_INT_CNT(u32IntType)); + + if (TMR4_INT_CNT_VALLEY == u32IntType) { + u16MaskTimes = (READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_ZIC) >> TMR4_CVPR_ZIC_POS); + } else { + u16MaskTimes = (READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_PIC) >> TMR4_CVPR_PIC_POS); + } + + return u16MaskTimes; +} + +/** + * @} + */ + +/** + * @defgroup TMR4_Output_Compare_Global_Functions TMR4 Output-Compare Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_tmr4_oc_init_t to default values + * @param [out] pstcTmr4OcInit Pointer to a @ref stc_tmr4_oc_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4OcInit value is NULL. + */ +int32_t TMR4_OC_StructInit(stc_tmr4_oc_init_t *pstcTmr4OcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4OcInit) { + pstcTmr4OcInit->u16CompareValue = 0U; + pstcTmr4OcInit->u16OcInvalidPolarity = TMR4_OC_INVD_LOW; + pstcTmr4OcInit->u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED; + pstcTmr4OcInit->u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED; + pstcTmr4OcInit->u16BufLinkTransObject = TMR4_OC_BUF_NONE; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize TMR4 OC + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] pstcTmr4OcInit Pointer to a @ref stc_tmr4_oc_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4OcInit value is NULL. + */ +int32_t TMR4_OC_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_oc_init_t *pstcTmr4OcInit) +{ + uint16_t u16Value; + __IO uint16_t *OCER; + __IO uint16_t *OCSR; + __IO uint16_t *OCCR; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4OcInit) { + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_OC_INVD_POLARITY(pstcTmr4OcInit->u16OcInvalidPolarity)); + DDL_ASSERT(IS_TMR4_OC_BUF_COND(pstcTmr4OcInit->u16CompareModeBufCond)); + DDL_ASSERT(IS_TMR4_OC_BUF_COND(pstcTmr4OcInit->u16CompareValueBufCond)); + DDL_ASSERT(IS_TMR4_OC_BUF_OBJECT(pstcTmr4OcInit->u16BufLinkTransObject)); + + /* Get pointer of current channel OC register address */ + OCSR = TMR4_OCSR(TMR4x, u32Ch); + OCER = TMR4_OCER(TMR4x, u32Ch); + OCCR = TMR4_OCCR(TMR4x, u32Ch); + + /* Set output polarity when OC is disabled. */ + MODIFY_REG16(*OCSR, TMR4_OCSR_MASK(u32Ch), TMR4_OCSR_OCPx(u32Ch, pstcTmr4OcInit->u16OcInvalidPolarity)); + + /* Set OCMR&&OCCR buffer function */ + u16Value = (TMR4_OCER_MxBUFEN(u32Ch, pstcTmr4OcInit->u16CompareModeBufCond) | \ + TMR4_OCER_CxBUFEN(u32Ch, pstcTmr4OcInit->u16CompareValueBufCond)); + if (TMR4_OC_BUF_CMP_VALUE == (pstcTmr4OcInit->u16BufLinkTransObject & TMR4_OC_BUF_CMP_VALUE)) { + u16Value |= TMR4_OCER_LMCx_MASK(u32Ch); + } + + if (TMR4_OC_BUF_CMP_MD == (pstcTmr4OcInit->u16BufLinkTransObject & TMR4_OC_BUF_CMP_MD)) { + u16Value |= TMR4_OCER_LMMx_MASK(u32Ch); + } + + MODIFY_REG16(*OCER, TMR4_OCER_MASK(u32Ch), u16Value); + + /* Set OC compare value */ + WRITE_REG16(*OCCR, pstcTmr4OcInit->u16CompareValue); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-initialize TMR4 OC + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @retval None + */ +void TMR4_OC_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __IO uint16_t *OCER; + __IO uint16_t *OCSR; + __IO uint16_t *OCCR; + __IO uint16_t *OCMRxH; + __IO uint32_t *OCMRxL; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCSR = TMR4_OCSR(TMR4x, u32Ch); + OCER = TMR4_OCER(TMR4x, u32Ch); + OCCR = TMR4_OCCR(TMR4x, u32Ch); + + /* Clear bits: port output valid && OP level && interrupt */ + CLR_REG16_BIT(*OCSR, TMR4_OCSR_MASK(u32Ch)); + + /* Clear bits: OCMR&&OCCR buffer */ + CLR_REG16_BIT(*OCER, TMR4_OCER_MASK(u32Ch)); + + /* Set OC compare match value */ + WRITE_REG16(*OCCR, 0x0000U); + + /* Set OCMR value */ + if ((u32Ch & 0x01UL) == 0UL) { + OCMRxH = TMR4_OCMR(TMR4x, u32Ch); + WRITE_REG16(*OCMRxH, 0x0000U); + } else { + OCMRxL = (__IO uint32_t *)((uint32_t)TMR4_OCMR(TMR4x, u32Ch)); + WRITE_REG32(*OCMRxL, 0x00000000UL); + } +} + +/** + * @brief Get TMR4 OC OCCR compare value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @retval The compare value of the TMR4 OC OCCR register + */ +uint16_t TMR4_OC_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint16_t *OCCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCCR = TMR4_OCCR(TMR4x, u32Ch); + + return READ_REG16(*OCCR); +} + +/** + * @brief Set TMR4 OC compare value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] u16Value The compare value of the TMR4 OC OCCR register + * @arg number of 16bit + * @retval None + */ +void TMR4_OC_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value) +{ + __IO uint16_t *OCCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCCR = TMR4_OCCR(TMR4x, u32Ch); + + WRITE_REG16(*OCCR, u16Value); +} + +/** + * @brief Enable or disable the TMR4 OC of the specified channel. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_OC_Cmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + __IO uint16_t *OCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get pointer of current channel OC register address */ + OCSR = TMR4_OCSR(TMR4x, u32Ch); + + /* Set OCSR port output compare */ + MODIFY_REG16(*OCSR, TMR4_OCSR_OCEx_MASK(u32Ch), TMR4_OCSR_OCEx(u32Ch, enNewState)); +} + +/** + * @brief Extend the matching conditions of TMR4 OC channel + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_OC_ExtendControlCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + __IO uint16_t *OCER; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get pointer of current channel OC register address */ + OCER = TMR4_OCER(TMR4x, u32Ch); + + /* Set OCER register: Extend match function */ + MODIFY_REG16(*OCER, TMR4_OCER_MCECx_MASK(u32Ch), TMR4_OCER_MCECx(u32Ch, enNewState)); +} + +/** + * @brief Set TMR4 OC OCCR/OCMR buffer interval response function + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] u16Object TMR4 OC register buffer: OCCR/OCMR + * This parameter can be any composed value of the macros group @ref TMR4_OC_Buffer_Object + * @arg TMR4_OC_BUF_CMP_VALUE: The register OCCR buffer function + * @arg TMR4_OC_BUF_CMP_MD: The register OCMR buffer function + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Enable the OCMR/OCMR register buffer function. + * @arg DISABLE: Disable the OCMR/OCMR register buffer function. + * @retval None + */ +void TMR4_OC_BufIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, + uint16_t u16Object, en_functional_state_t enNewState) +{ + __IO uint16_t *OCER; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_OC_BUF_OBJECT(u16Object)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get pointer of current channel OC register address */ + OCER = TMR4_OCER(TMR4x, u32Ch); + + if (TMR4_OC_BUF_CMP_VALUE == (u16Object & TMR4_OC_BUF_CMP_VALUE)) { + /* Set OCER register: OCCR link transfer function */ + MODIFY_REG16(*OCER, TMR4_OCER_LMCx_MASK(u32Ch), TMR4_OCER_LMCx(u32Ch, enNewState)); + } + + if (TMR4_OC_BUF_CMP_MD == (u16Object & TMR4_OC_BUF_CMP_MD)) { + /* Set OCER register: OCMR link transfer function */ + MODIFY_REG16(*OCER, TMR4_OCER_LMMx_MASK(u32Ch), TMR4_OCER_LMMx(u32Ch, enNewState)); + } +} + +/** + * @brief Get TMR4 OC output current polarity + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @retval Returned value can be one of the macros group @ref TMR4_OC_Output_Polarity + * - TMR4_OC_PORT_LOW: TMR4 OC output low level + * - TMR4_OC_PORT_HIGH: TMR4 OC output high level + */ +uint16_t TMR4_OC_GetPolarity(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint16_t *OCSR; + uint16_t u16Polarity; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCSR = TMR4_OCSR(TMR4x, u32Ch); + + /* Get OCSR register: OC output polarity */ + u16Polarity = READ_REG16_BIT(*OCSR, TMR4_OCSR_OCPx_MASK(u32Ch)); + return (u16Polarity >> (u32Ch % 2UL)); +} + +/** + * @brief Set TMR4 OC invalid output polarity + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] u16Polarity TMR4 OC invalid output polarity. + * This parameter can be one of the macros group @ref TMR4_OC_Invalid_Output_Polarity + * @arg TMR4_OC_INVD_LOW: TMR4 OC output low level when OC is invalid + * @arg TMR4_OC_INVD_HIGH: TMR4 OC output high level when OC is invalid + * @retval None + */ +void TMR4_OC_SetOcInvalidPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity) +{ + __IO uint16_t *OCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_OC_INVD_POLARITY(u16Polarity)); + + /* Get pointer of current channel OC register address */ + OCSR = TMR4_OCSR(TMR4x, u32Ch); + + /* Set OCSR register: OC invalid output polarity */ + MODIFY_REG16(*OCSR, TMR4_OCSR_OCPx_MASK(u32Ch), TMR4_OCSR_OCPx(u32Ch, u16Polarity)); +} + +/** + * @brief Set TMR4 OC OCCR/OCMR buffer transfer condition + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] u16Object TMR4 OC register buffer type: OCCR/OCMR + * This parameter can be any composed value of the macros group @ref TMR4_OC_Buffer_Object + * @arg TMR4_OC_BUF_CMP_VALUE: The register OCCR buffer function + * @arg TMR4_OC_BUF_CMP_MD: The register OCMR buffer function + * @param [in] u16BufCond TMR4 OC OCCR/OCMR buffer transfer condition + * This parameter can be one of the macros group @ref TMR4_OC_Buffer_Transfer_Condition + * @arg TMR4_OC_BUF_COND_IMMED: Buffer transfer is made when writing to the OCCR/OCMR register. + * @arg TMR4_OC_BUF_COND_VALLEY: Buffer transfer is made when counter count valley. + * @arg TMR4_OC_BUF_COND_PEAK: Buffer transfer is made when counter count peak. + * @arg TMR4_OC_BUF_COND_PEAK_VALLEY: Buffer transfer is made when counter count peak or valley. + * @retval None + */ +void TMR4_OC_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object, uint16_t u16BufCond) +{ + __IO uint16_t *OCER; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_OC_BUF_OBJECT(u16Object)); + DDL_ASSERT(IS_TMR4_OC_BUF_COND(u16BufCond)); + + /* Get pointer of current channel OC register address */ + OCER = TMR4_OCER(TMR4x, u32Ch); + + if (TMR4_OC_BUF_CMP_VALUE == (u16Object & TMR4_OC_BUF_CMP_VALUE)) { + /* Set OCER register: OCCR buffer mode */ + MODIFY_REG16(*OCER, TMR4_OCER_CxBUFEN_MASK(u32Ch), TMR4_OCER_CxBUFEN(u32Ch, u16BufCond)); + } + + if (TMR4_OC_BUF_CMP_MD == (u16Object & TMR4_OC_BUF_CMP_MD)) { + /* Set OCER register: OCMR buffer mode */ + MODIFY_REG16(*OCER, TMR4_OCER_MxBUFEN_MASK(u32Ch), TMR4_OCER_MxBUFEN(u32Ch, u16BufCond)); + } +} + +/** + * @brief Get the TMR4 OC high channel mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel. + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @retval The TMR4 OC high channel mode + * @note The function only can get high channel mode:TMR4_OC_CH_xH(x = U/V/W) + */ +uint16_t TMR4_OC_GetHighChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint16_t *OCMRxH; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_HIGH_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCMRxH = TMR4_OCMR(TMR4x, u32Ch); + return READ_REG16(*OCMRxH); +} + +/** + * @brief Set the TMR4 OC high channel mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel. + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] unTmr4Ocmrh The TMR4 OC high channel mode @ref un_tmr4_oc_ocmrh_t + * @retval None + * @note The function only can set high channel mode:TMR4_OC_CH_xH(x = U/V/W) + */ +void TMR4_OC_SetHighChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrh_t unTmr4Ocmrh) +{ + __IO uint16_t *OCMRxH; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_HIGH_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCMRxH = TMR4_OCMR(TMR4x, u32Ch); + WRITE_REG16(*OCMRxH, unTmr4Ocmrh.OCMRx); +} + +/** + * @brief Get the TMR4 OC low channel mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel. + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @retval The TMR4 OC low channel mode + * @note The function only can get low channel mode:TMR4_OC_CH_xL(x = U/V/W) + */ +uint32_t TMR4_OC_GetLowChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint32_t *OCMRxL; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_LOW_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCMRxL = (__IO uint32_t *)((uint32_t)TMR4_OCMR(TMR4x, u32Ch)); + return READ_REG32(*OCMRxL); +} + +/** + * @brief Set the TMR4 OC low channel mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel. + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] unTmr4Ocmrl The TMR4 OC low channel mode @ref un_tmr4_oc_ocmrl_t + * @retval None + * @note The function only can set low channel mode:TMR4_OC_CH_xL(x = U/V/W) + */ +void TMR4_OC_SetLowChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrl_t unTmr4Ocmrl) +{ + __IO uint32_t *OCMRxL; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_LOW_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCMRxL = (__IO uint32_t *)((uint32_t)TMR4_OCMR(TMR4x, u32Ch)); + WRITE_REG32(*OCMRxL, unTmr4Ocmrl.OCMRx); +} + +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Global_Functions TMR4 PWM Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_tmr4_pwm_init_t to default values + * @param [out] pstcTmr4PwmInit Pointer to a @ref stc_tmr4_pwm_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4PwmInit value is NULL. + */ +int32_t TMR4_PWM_StructInit(stc_tmr4_pwm_init_t *pstcTmr4PwmInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4PwmInit) { + pstcTmr4PwmInit->u16Mode = TMR4_PWM_MD_THROUGH; + pstcTmr4PwmInit->u16ClockDiv = TMR4_PWM_CLK_DIV1; + pstcTmr4PwmInit->u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize TMR4 PWM + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] pstcTmr4PwmInit Pointer to a @ref stc_tmr4_pwm_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4PwmInit value is NULL. + */ +int32_t TMR4_PWM_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_pwm_init_t *pstcTmr4PwmInit) +{ + uint16_t POCRValue; + __IO uint16_t *POCR; + RCSR_REG_TYPE RCSRValue; + __IO RCSR_REG_TYPE *RCSR; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4PwmInit) { + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_PWM_MD(pstcTmr4PwmInit->u16Mode)); + DDL_ASSERT(IS_TMR4_PWM_CLK_DIV(pstcTmr4PwmInit->u16ClockDiv)); + DDL_ASSERT(IS_TMR4_PWM_POLARITY(pstcTmr4PwmInit->u16Polarity)); + + /* Get pointer of current channel PWM register address */ + POCR = TMR4_POCR(TMR4x, u32Ch); + RCSR = TMR4_RCSR(TMR4x); + + /* Set POCR register */ + POCRValue = (pstcTmr4PwmInit->u16Mode | pstcTmr4PwmInit->u16ClockDiv | pstcTmr4PwmInit->u16Polarity); + WRITE_REG16(*POCR, POCRValue); + + /* Set RCSR register */ + RCSRValue = (TMR4_RCSR_RTSx_MASK(u32Ch) | TMR4_RCSR_RTIDx_MASK(u32Ch) | TMR4_RCSR_RTICx_MASK(u32Ch)); + MODIFY_REG(*RCSR, TMR4_RCSR_MASK(u32Ch), RCSRValue); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-initialize TMR4 PWM + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @retval None + */ +void TMR4_PWM_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __IO uint16_t *POCR; + __IO RCSR_REG_TYPE *RCSR; + RCSR_REG_TYPE RCSRValue; + __IO uint16_t *PDAR; + __IO uint16_t *PDBR; + __IO uint16_t *PFSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + + /* Get pointer of current channel PWM register address */ + POCR = TMR4_POCR(TMR4x, u32Ch); + RCSR = TMR4_RCSR(TMR4x); + PDAR = TMR4_PDR(TMR4x, u32Ch, TMR4_PWM_PDAR_IDX); + PDBR = TMR4_PDR(TMR4x, u32Ch, TMR4_PWM_PDBR_IDX); + PFSR = TMR4_PFSR(TMR4x, u32Ch); + + /* Set POCR register to reset value */ + WRITE_REG16(*POCR, TMR4_POCR_RST_VALUE); + + /* Set RCSR register */ + RCSRValue = (TMR4_RCSR_RTSx_MASK(u32Ch) | TMR4_RCSR_RTICx_MASK(u32Ch)); + MODIFY_REG(*RCSR, TMR4_RCSR_MASK(u32Ch), RCSRValue); + + /* Set PDAR/PDBR register to reset value */ + WRITE_REG16(*PDAR, 0U); + WRITE_REG16(*PDBR, 0U); + + /* Set POCR register to reset value */ + WRITE_REG16(*PFSR, 0U); + + /* Set abnormal pin status to reset value */ + TMR4_PWM_SetAbnormalPinStatus(TMR4x, ((u32Ch << 1) + 0UL), TMR4_PWM_ABNORMAL_PIN_HIZ); + TMR4_PWM_SetAbnormalPinStatus(TMR4x, ((u32Ch << 1) + 1UL), TMR4_PWM_ABNORMAL_PIN_HIZ); + +} + +/** + * @brief Set TMR4 PWM clock division + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] u16Div TMR4 PWM internal clock division + * This parameter can be one of the macros group @ref TMR4_PWM_Clock_Division + * @arg TMR4_PWM_CLK_DIV1: CLK + * @arg TMR4_PWM_CLK_DIV2: CLK/2 + * @arg TMR4_PWM_CLK_DIV4: CLK/4 + * @arg TMR4_PWM_CLK_DIV8: CLK/8 + * @arg TMR4_PWM_CLK_DIV16: CLK/16 + * @arg TMR4_PWM_CLK_DIV32: CLK/32 + * @arg TMR4_PWM_CLK_DIV64: CLK/64 + * @arg TMR4_PWM_CLK_DIV128: CLK/128 + * @retval None + */ +void TMR4_PWM_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Div) +{ + __IO uint16_t *POCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_PWM_CLK_DIV(u16Div)); + + /* Get pointer of current channel PWM register address */ + POCR = TMR4_POCR(TMR4x, u32Ch); + + MODIFY_REG16(*POCR, TMR4_POCR_DIVCK, u16Div); +} + +/** + * @brief Set TMR4 PWM output polarity. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] u16Polarity TMR4 PWM output polarity + * This parameter can be one of the macros group @ref TMR4_PWM_Polarity + * @arg TMR4_PWM_OXH_HOLD_OXL_HOLD: Output PWML and PWMH signals without changing the level + * @arg TMR4_PWM_OXH_INVT_OXL_INVT: Output both PWML and PWMH signals reversed + * @arg TMR4_PWM_OXH_INVT_OXL_HOLD: Output the PWMH signal reversed, outputs the PWML signal without changing the level + * @arg TMR4_PWM_OXH_HOLD_OXL_INVT: Output the PWMH signal without changing the level, Outputs the PWML signal reversed + * @retval None + */ +void TMR4_PWM_SetPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity) +{ + __IO uint16_t *POCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_PWM_POLARITY(u16Polarity)); + + /* Get pointer of current channel PWM register address */ + POCR = TMR4_POCR(TMR4x, u32Ch); + + MODIFY_REG16(*POCR, TMR4_POCR_LVLS, u16Polarity); +} + +/** + * @brief Start TMR4 PWM reload-timer + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @retval None + */ +void TMR4_PWM_StartReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + + SET_REG_BIT(TMR4x->RCSR, TMR4_RCSR_RTEx_MASK(u32Ch)); +} + +/** + * @brief Stop TMR4 PWM reload-timer + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @retval None + */ +void TMR4_PWM_StopReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + + SET_REG_BIT(TMR4x->RCSR, TMR4_RCSR_RTSx_MASK(u32Ch)); +} + +/** + * @brief Set TMR4 PWM filter count value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] u16Value TMR4 PWM filter count value + * @arg number of 16bit + * @retval None + */ +void TMR4_PWM_SetFilterCountValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value) +{ + __IO uint16_t *PFSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + + /* Get pointer of current channel PWM register address */ + PFSR = TMR4_PFSR(TMR4x, u32Ch); + + WRITE_REG16(*PFSR, u16Value); +} + +/** + * @brief Set TMR4 PWM dead time count + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] u32DeadTimeIndex TMR4 PWM dead time register index + * This parameter can be one of the macros group @ref TMR4_PWM_Dead_Time_Register_Index + * @arg TMR4_PWM_PDAR_IDX: TMR4_PDARn + * @arg TMR4_PWM_PDBR_IDX: TMR4_PDBRn + * @param [in] u16Value TMR4 PWM dead time register value + * @arg number of 16bit + * @retval None + */ +void TMR4_PWM_SetDeadTimeValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex, uint16_t u16Value) +{ + __IO uint16_t *PDR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_PWM_DEADTIME_REG_IDX(u32DeadTimeIndex)); + + /* Get pointer of current channel PWM register address */ + PDR = TMR4_PDR(TMR4x, u32Ch, u32DeadTimeIndex); + + WRITE_REG16(*PDR, u16Value); +} + +/** + * @brief Get TMR4 PWM dead time count + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] u32DeadTimeIndex TMR4 PWM dead time register index + * This parameter can be one of the macros group @ref TMR4_PWM_Dead_Time_Register_Index + * @arg TMR4_PWM_PDAR_IDX: TMR4_PDARn + * @arg TMR4_PWM_PDBR_IDX: TMR4_PDBRn + * @retval TMR4 PWM dead time register value + */ +uint16_t TMR4_PWM_GetDeadTimeValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex) +{ + __I uint16_t *PDR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_PWM_DEADTIME_REG_IDX(u32DeadTimeIndex)); + + /* Get pointer of current channel PWM register address */ + PDR = TMR4_PDR(TMR4x, u32Ch, u32DeadTimeIndex); + + return READ_REG16(*PDR); +} + +/** + * @brief Set TMR4 PWM pin status when below conditions occur:1.EMB 2.MOE=0 3.MOE=1&OExy=0 + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32PwmPin TMR4 PWM pin + * This parameter can be one of the macros group @ref TMR4_PWM_Pin + * @param [in] u32PinStatus TMR4 PWM pin status + * This parameter can be one of the macros group @ref TMR4_PWM_Abnormal_Pin_Status. + * @retval None + */ +void TMR4_PWM_SetAbnormalPinStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32PwmPin, uint32_t u32PinStatus) +{ + __IO uint32_t *ECER; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_ABNORMAL_PIN_STAT(u32PinStatus)); + + (void)(u32PwmPin); + ECER = TMR4_ECER(TMR4x); + + if ((TMR4_PWM_ABNORMAL_PIN_HIZ == u32PinStatus) || \ + (TMR4_PWM_ABNORMAL_PIN_LOW == u32PinStatus) || \ + (TMR4_PWM_ABNORMAL_PIN_HIGH == u32PinStatus)) { + WRITE_REG32(*ECER, u32PinStatus); + } else { + if (TMR4_PWM_ABNORMAL_PIN_HOLD == u32PinStatus) { + SET_REG16_BIT(TMR4x->ECSR, TMR4_ECSR_HOLD); + } else { + CLR_REG16_BIT(TMR4x->ECSR, TMR4_ECSR_HOLD); + } + + WRITE_REG32(*ECER, 0UL); + } +} + +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Global_Functions TMR4 Event Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_tmr4_evt_init_t to default values + * @param [in] pstcTmr4EventInit Pointer to a @ref stc_tmr4_evt_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4EventInit value is NULL. + */ +int32_t TMR4_EVT_StructInit(stc_tmr4_evt_init_t *pstcTmr4EventInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4EventInit) { + pstcTmr4EventInit->u16Mode = TMR4_EVT_MD_CMP; + pstcTmr4EventInit->u16CompareValue = 0U; + pstcTmr4EventInit->u16OutputEvent = TMR4_EVT_OUTPUT_EVT0; + pstcTmr4EventInit->u16MatchCond = 0U; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize TMR4 event + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] pstcTmr4EventInit Pointer to a @ref stc_tmr4_evt_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4EventInit value is NULL. + */ +int32_t TMR4_EVT_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_evt_init_t *pstcTmr4EventInit) +{ + uint16_t u16Value; + __IO uint16_t *SCCR; + __IO uint16_t *SCSR; + __IO uint16_t *SCMR; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4EventInit) { + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_MD(pstcTmr4EventInit->u16Mode)); + DDL_ASSERT(IS_TMR4_EVT_OUTPUT_EVT(pstcTmr4EventInit->u16OutputEvent)); + DDL_ASSERT(IS_TMR4_EVT_MATCH_COND(pstcTmr4EventInit->u16MatchCond)); + + /* Get actual address of register list of current channel */ + SCCR = TMR4_SCCR(TMR4x, u32Ch); + SCSR = TMR4_SCSR(TMR4x, u32Ch); + SCMR = TMR4_SCMR(TMR4x, u32Ch); + + /* Set SCSR register */ + u16Value = (pstcTmr4EventInit->u16Mode | pstcTmr4EventInit->u16OutputEvent | pstcTmr4EventInit->u16MatchCond); + WRITE_REG16(*SCSR, u16Value); + + /* Set SCMR register */ + WRITE_REG16(*SCMR, 0xFF00U); + + /* Set SCCR register: compare value */ + WRITE_REG16(*SCCR, pstcTmr4EventInit->u16CompareValue); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-initialize TMR4 PWM + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @retval None + */ +void TMR4_EVT_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __IO uint16_t *SCCR; + __IO uint16_t *SCSR; + __IO uint16_t *SCMR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + SCCR = TMR4_SCCR(TMR4x, u32Ch); + SCSR = TMR4_SCSR(TMR4x, u32Ch); + SCMR = TMR4_SCMR(TMR4x, u32Ch); + + /* Configure default parameter */ + WRITE_REG16(*SCCR, 0x0U); + WRITE_REG16(*SCSR, 0x0000U); + WRITE_REG16(*SCMR, TMR4_SCMR_RST_VALUE); +} + +/** + * @brief Set TMR4 event delay object + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16Object TMR4 event delay object + * This parameter can be one of the macros group @ref TMR4_Event_Delay_Object + * @arg TMR4_EVT_DELAY_OCCRXH: TMR4 event delay object - OCCRxh + * @arg TMR4_EVT_DELAY_OCCRXL: TMR4 event delay object - OCCRxl + * @retval None + */ +void TMR4_EVT_SetDelayObject(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object) +{ + __IO uint16_t *SCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_DELAY_OBJECT(u16Object)); + + /* Get actual address of register list of current channel */ + SCSR = TMR4_SCSR(TMR4x, u32Ch); + + /* Set SCSR register */ + MODIFY_REG16(*SCSR, TMR4_SCSR_EVTDS, u16Object); +} + +/** + * @brief Set TMR4 event trigger event. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16MaskTime Mask times + * This parameter can be one of the macros group @ref TMR4_Event_Mask_Times + * @arg TMR4_EVT_MASK0: Mask 0 times + * @arg TMR4_EVT_MASK1: Mask 1 times + * @arg TMR4_EVT_MASK2: Mask 2 times + * @arg TMR4_EVT_MASK3: Mask 3 times + * @arg TMR4_EVT_MASK4: Mask 4 times + * @arg TMR4_EVT_MASK5: Mask 5 times + * @arg TMR4_EVT_MASK6: Mask 6 times + * @arg TMR4_EVT_MASK7: Mask 7 times + * @arg TMR4_EVT_MASK8: Mask 8 times + * @arg TMR4_EVT_MASK9: Mask 9 times + * @arg TMR4_EVT_MASK10: Mask 10 times + * @arg TMR4_EVT_MASK11: Mask 11 times + * @arg TMR4_EVT_MASK12: Mask 12 times + * @arg TMR4_EVT_MASK13: Mask 13 times + * @arg TMR4_EVT_MASK14: Mask 14 times + * @arg TMR4_EVT_MASK15: Mask 15 times + * @retval None + */ +void TMR4_EVT_SetMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16MaskTime) +{ + __IO uint16_t *SCMR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_MASK(u16MaskTime)); + + /* Get actual address of register list of current channel */ + SCMR = TMR4_SCMR(TMR4x, u32Ch); + + /* Set SCMR register */ + MODIFY_REG16(*SCMR, TMR4_SCMR_AMC, u16MaskTime); +} + +/** + * @brief Get TMR4 event SCCR register value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @retval Returned value can be one of the macros group @ref TMR4_Event_Mask_Times + * - TMR4_EVT_MASK0: Mask 0 times + * - TMR4_EVT_MASK1: Mask 1 times + * - TMR4_EVT_MASK2: Mask 2 times + * - TMR4_EVT_MASK3: Mask 3 times + * - TMR4_EVT_MASK4: Mask 4 times + * - TMR4_EVT_MASK5: Mask 5 times + * - TMR4_EVT_MASK6: Mask 6 times + * - TMR4_EVT_MASK7: Mask 7 times + * - TMR4_EVT_MASK8: Mask 8 times + * - TMR4_EVT_MASK9: Mask 9 times + * - TMR4_EVT_MASK10: Mask 10 times + * - TMR4_EVT_MASK11: Mask 11 times + * - TMR4_EVT_MASK12: Mask 12 times + * - TMR4_EVT_MASK13: Mask 13 times + * - TMR4_EVT_MASK14: Mask 14 times + * - TMR4_EVT_MASK15: Mask 15 times + */ +uint16_t TMR4_EVT_GetMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint16_t *SCMR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + SCMR = TMR4_SCMR(TMR4x, u32Ch); + + return READ_REG16_BIT(*SCMR, TMR4_SCMR_AMC); +} + +/** + * @brief Set TMR4 event compare value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16Value SCCR register value + * @arg number of 16bit + * @retval None + */ +void TMR4_EVT_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value) +{ + __IO uint16_t *SCCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + SCCR = TMR4_SCCR(TMR4x, u32Ch); + + /* Set SCCR register */ + WRITE_REG16(*SCCR, u16Value); +} + +/** + * @brief Get TMR4 event compare value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @retval SCCR register value + */ +uint16_t TMR4_EVT_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint16_t *SCCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + SCCR = TMR4_SCCR(TMR4x, u32Ch); + + return READ_REG16(*SCCR); +} + +/** + * @brief Set TMR4 output event + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16Event TMR4 event output event + * This parameter can be one of the macros group @ref TMR4_Event_Output_Event + * @retval None + */ +void TMR4_EVT_SetOutputEvent(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Event) +{ + __IO uint16_t *SCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_OUTPUT_EVT(u16Event)); + + /* Get actual address of register list of current channel */ + SCSR = TMR4_SCSR(TMR4x, u32Ch); + + /* Set SCSR register */ + MODIFY_REG16(*SCSR, TMR4_SCSR_EVTOS, u16Event); +} + +/** + * @brief Set the SCCR&SCMR buffer transfer condition + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16BufCond The buffer transfer condition + * This parameter can be one of the macros group @ref TMR4_Event_Buffer_Transfer_Condition + * @arg TMR4_EVT_BUF_COND_IMMED: Register SCCR&SCMR buffer transfer when writing to the SCCR&SCMR register + * @arg TMR4_EVT_BUF_COND_VALLEY: Register SCCR&SCMR buffer transfer when counter count valley + * @arg TMR4_EVT_BUF_COND_PEAK: Register SCCR&SCMR buffer transfer when counter count peak + * @arg TMR4_EVT_BUF_COND_PEAK_VALLEY: Register SCCR&SCMR buffer transfer when counter count peak or valley + * @retval None + */ +void TMR4_EVT_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16BufCond) +{ + __IO uint16_t *SCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_BUF_COND(u16BufCond)); + + /* Get actual address of register list of current channel */ + SCSR = TMR4_SCSR(TMR4x, u32Ch); + + MODIFY_REG16(*SCSR, TMR4_SCSR_BUFEN, u16BufCond); +} + +/** + * @brief Enable or disable the buffer interval response function of TMR4 event. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_EVT_BufIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + __IO uint16_t *SCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get actual address of register list of current channel */ + SCSR = TMR4_SCSR(TMR4x, u32Ch); + + if (ENABLE == enNewState) { + SET_REG16_BIT(*SCSR, TMR4_SCSR_LMC); + } else { + CLR_REG16_BIT(*SCSR, TMR4_SCSR_LMC); + } +} + +/** + * @brief Enable or disable the specified interval response of TMR4 event. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16MaskType The specified mask compare type of TMR4 event + * This parameter can be any composed value of the macros group @ref TMR4_Event_Mask + * @arg TMR4_EVT_MASK_VALLEY: Compare with the counter valley interrupt mask counter + * @arg TMR4_EVT_MASK_PEAK: Compare with the counter peak interrupt mask counter + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_EVT_EventIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, + uint16_t u16MaskType, en_functional_state_t enNewState) +{ + __IO uint16_t *SCMR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_MASK_TYPE(u16MaskType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get actual address of register list of current channel */ + SCMR = TMR4_SCMR(TMR4x, u32Ch); + + if (ENABLE == enNewState) { + SET_REG16_BIT(*SCMR, u16MaskType); + } else { + CLR_REG16_BIT(*SCMR, u16MaskType); + } +} + +/** + * @brief Enable or disable the specified count compare type of TMR4 event + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16Cond The specified count compare type of TMR4 event + * This parameter can be any composed value of the macros group @ref TMR4_Event_Match_Condition + * @arg TMR4_EVT_MATCH_CNT_UP: Start event operate when match with SCCR&SCMR and TMR4 counter count up + * @arg TMR4_EVT_MATCH_CNT_DOWN: Start event operate when match with SCCR&SCMR and TMR4 counter count down + * @arg TMR4_EVT_MATCH_CNT_VALLEY: Start event operate when match with SCCR&SCMR and TMR4 counter count valley + * @arg TMR4_EVT_MATCH_CNT_PEAK: Start event operate when match with SCCR&SCMR and TMR4 counter count peak + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_EVT_MatchCondCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState) +{ + __IO uint16_t *SCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_MATCH_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get actual address of register list of current channel */ + SCSR = TMR4_SCSR(TMR4x, u32Ch); + + if (ENABLE == enNewState) { + SET_REG16_BIT(*SCSR, u16Cond); + } else { + CLR_REG16_BIT(*SCSR, u16Cond); + } +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LL_TMR4_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_tmr6.c b/mcu/lib/src/hc32_ll_tmr6.c new file mode 100644 index 0000000..5ec5cc8 --- /dev/null +++ b/mcu/lib/src/hc32_ll_tmr6.c @@ -0,0 +1,1683 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr6.c + * @brief This file provides firmware functions to manage the TMR6(TMR6). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Define variable in the beginning of the function + 2023-01-15 CDT Modify structure stc_timer6_init_t to stc_tmr6_init_t + Modify API TMR6_SetFilterClockDiv() + 2023-06-30 CDT Modify typo + Delete union in stc_tmr6_init_t structure + Modify API TMR6_GetCountDir() + 2023-09-30 CDT Modify API TMR6_Init() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_tmr6.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TMR6 TMR6 + * @brief TMR6 Driver Library + * @{ + */ + +#if (LL_TMR6_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR6_Local_Macros TMR6 Local Macros + * @{ + */ + +/* Timer6 registers reset value */ +#define TMR6_REG_RST_VALUE_U32 (0xFFFFFFFFUL) +#define TMR6_REG_RST_VALUE_U16 (0xFFFFU) +#define TMR6_REG_GCONR_RST_VALUE (0x00000100UL) + +/* Define for BCONR register configuration */ +#define BCONR_FUNC_CMD_MASK (0x01UL) +#define BCONR_GEN_CFG_MASK (0x00000002UL) +#define BCONR_GEN_CFG_CHB_OFS (0x02UL) +#define BCONR_PERIOD_CFG_MASK (0x00000002UL) +#define BCONR_PERIOD_CFG_OFS (0x08UL) +#define BCONR_SPECIAL_CFG_MASK (0x00000032UL) +#define BCONR_SPECIAL_CFG_CHA_OFS (0x10UL) +#define BCONR_SPECIAL_CFG_TRIG_CHA_OFS (0x12UL) +#define BCONR_SPECIAL_CFG_CHB_OFS (0x18UL) +#define BCONR_SPECIAL_CFG_TRIG_CHB_OFS (0x1AUL) + +/* Define mask value for PWM output configuration for register */ +#define PCONR_REG_CHB_SHIFT (16U) +#define PCONR_REG_CHA_OUTPUT_CFG_MASK (0x000000FFUL) +#define PCONR_REG_CHB_OUTPUT_CFG_MASK (PCONR_REG_CHA_OUTPUT_CFG_MASK << PCONR_REG_CHB_SHIFT) +#define PCONR_REG_POLARITY_START_STOP_MASK (0x01UL) +#define PCONR_REG_POLARITY_MASK (0x03UL) + +/* Define mask value for GCONR register */ +#define TMR6_INIT_MASK (TMR6_GCONR_DIR | TMR6_GCONR_MODE | TMR6_GCONR_CKDIV) +#define TMR6_ZMASK_CFG_MASK (TMR6_GCONR_ZMSKVAL | TMR6_GCONR_ZMSKPOS | TMR6_GCONR_ZMSKREV) + +/** + * @defgroup TMR6_Check_Param_Validity TMR6 Check Parameters Validity + * @{ + */ + +/*! Parameter valid check for normal timer6 unit */ +#define IS_VALID_TMR6_UNIT(x) \ +( ((x) == CM_TMR6_1) || \ + ((x) == CM_TMR6_2) || \ + ((x) == CM_TMR6_3)) + +/*! Parameter valid check for timer6 count source */ +#define IS_TMR6_CNT_SRC(x) \ +( ((x) == TMR6_CNT_SRC_SW) || \ + ((x) == TMR6_CNT_SRC_HW)) + +/*! Parameter valid check for interrupt source configuration */ +#define IS_VALID_IRQ(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_INT_ALL) == TMR6_INT_ALL)) + +/*! Parameter valid check for status bit read */ +#define IS_VALID_GET_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_FLAG_ALL) == TMR6_FLAG_ALL)) + +/*! Parameter valid check for status bit clear */ +#define IS_VALID_CLR_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_FLAG_CLR_ALL) == TMR6_FLAG_CLR_ALL)) + +/*! Parameter valid check for period register */ +#define IS_VALID_PERIOD_REG(x) \ +( (x) <= TMR6_PERIOD_REG_C) + +/*! Parameter valid check for general compare register */ +#define IS_VALID_CMP_REG(x) \ +( (x) <= TMR6_CMP_REG_F) + +/*! Parameter valid check for general/special compare channel */ +#define IS_VALID_CNT_CH(x) \ +( ((x) == TMR6_CH_A) || \ + ((x) == TMR6_CH_B)) + +/*! Parameter valid check for buffer function number */ +#define IS_VALID_BUF_NUM(x) \ +( ((x) == TMR6_BUF_SINGLE) || \ + ((x) == TMR6_BUF_DUAL)) + +/*! Parameter valid check for buffer transfer timer configuration */ +#define IS_VALID_BUF_TRANS_TRIG(x) \ +( ((x) == TMR6_BUF_TRANS_INVD) || \ + ((x) == TMR6_BUF_TRANS_OVF) || \ + ((x) == TMR6_BUF_TRANS_UDF) || \ + ((x) == TMR6_BUF_TRANS_OVF_UDF)) + +/*! Parameter valid check for count condition for valid period function */ +#define IS_VALID_PERIOD_CNT_COND(x) \ +( ((x) == TMR6_VALID_PERIOD_INVD) || \ + ((x) == TMR6_VALID_PERIOD_CNT_COND_VALLEY) || \ + ((x) == TMR6_VALID_PERIOD_CNT_COND_PEAK) || \ + ((x) == TMR6_VALID_PERIOD_CNT_COND_VALLEY_PEAK)) + +/*! Parameter valid check for count condition for valid period count */ +#define IS_VALID_PERIOD_CNT(x) \ +( ((x) == TMR6_VALID_PERIOD_CNT_INVD) || \ + ((x) == TMR6_VALID_PERIOD_CNT1) || \ + ((x) == TMR6_VALID_PERIOD_CNT2) || \ + ((x) == TMR6_VALID_PERIOD_CNT3) || \ + ((x) == TMR6_VALID_PERIOD_CNT4) || \ + ((x) == TMR6_VALID_PERIOD_CNT5) || \ + ((x) == TMR6_VALID_PERIOD_CNT6) || \ + ((x) == TMR6_VALID_PERIOD_CNT7)) + +/*! Parameter valid check for count register data range */ +#define IS_VALID_REG_RANGE_U16(x) ((x) <= 0xFFFFUL) + +/*! Parameter valid check for dead time register */ +#define IS_VALID_DEADTIME_REG(x) \ +( ((x) == TMR6_DEADTIME_REG_UP_A) || \ + ((x) == TMR6_DEADTIME_REG_DOWN_A) || \ + ((x) == TMR6_DEADTIME_REG_UP_B) || \ + ((x) == TMR6_DEADTIME_REG_DOWN_B)) + +/*! Parameter valid check for pin */ +#define IS_VALID_PIN(x) \ +( ((x) == TMR6_IO_PWMA) || \ + ((x) == TMR6_IO_PWMB) || \ + ((x) == TMR6_INPUT_TRIGA) || \ + ((x) == TMR6_INPUT_TRIGB)) + +/*! Parameter valid check for input pin filter clock */ +#define IS_VALID_FILTER_CLK(x) \ +( ((x) == TMR6_FILTER_CLK_DIV1) || \ + ((x) == TMR6_FILTER_CLK_DIV4) || \ + ((x) == TMR6_FILTER_CLK_DIV16) || \ + ((x) == TMR6_FILTER_CLK_DIV64)) + +/*! Parameter valid check for PWM pin status */ +#define IS_VALID_PWM_POLARITY(x) \ +( ((x) == TMR6_PWM_LOW) || \ + ((x) == TMR6_PWM_HIGH) || \ + ((x) == TMR6_PWM_HOLD) || \ + ((x) == TMR6_PWM_INVT)) + +/*! Parameter valid check for start stop hold for PWM output pin */ +#define IS_VALID_PWM_START_STOP_HOLD(x) \ +( ((x) == TMR6_PWM_START_STOP_HOLD) || \ + ((x) == TMR6_PWM_START_STOP_CHANGE)) + +/*! Parameter valid check for force PWM output pin */ + +/*! Parameter valid check for PWM pin status for count start and stop */ +#define IS_VALID_PWM_POLARITY_START_STOP(x) \ +( ((x) == TMR6_PWM_LOW) || \ + ((x) == TMR6_PWM_HIGH)) + +#define IS_VALID_CNT_STAT(x) \ +( ((x) == TMR6_STAT_START) || \ + ((x) == TMR6_STAT_STOP) || \ + ((x) == TMR6_STAT_MATCH_CMP) || \ + ((x) == TMR6_STAT_MATCH_PERIOD)) + +/*! Parameter valid check for pin mode */ +#define IS_VALID_PIN_MD(x) \ +( ((x) == TMR6_PIN_CMP_OUTPUT) || \ + ((x) == TMR6_PIN_CAPT_INPUT)) + +/*! Parameter valid check for pin output status when EMB event valid */ +#define IS_VALID_EMB_VALID_PIN_POLARITY(x) \ +( ((x) == TMR6_EMB_PIN_NORMAL) || \ + ((x) == TMR6_EMB_PIN_HIZ) || \ + ((x) == TMR6_EMB_PIN_LOW) || \ + ((x) == TMR6_EMB_PIN_HIGH)) + +/*! Parameter valid check for dead time buffer function for DTUAR and DTUBR register */ +#define IS_VALID_DEADTIME_BUF_FUNC_DTUAR_REG(x) \ +( ((x) == TMR6_DEADTIME_CNT_UP_BUF_OFF) || \ + ((x) == TMR6_DEADTIME_CNT_UP_BUF_ON)) + +/*! Parameter valid check for dead time buffer function for DTDAR and DTDBR register */ +#define IS_VALID_DEADTIME_BUF_FUNC_DTDAR_REG(x) \ +( ((x) == TMR6_DEADTIME_CNT_DOWN_BUF_OFF) || \ + ((x) == TMR6_DEADTIME_CNT_DOWN_BUF_ON)) + +/*! Parameter valid check for dead time equal function for DTUAR and DTDAR register */ +#define IS_VALID_DEADTIME_EQUAL_FUNC_REG(x) \ +( ((x) == TMR6_DEADTIME_EQUAL_OFF) || \ + ((x) == TMR6_DEADTIME_EQUAL_ON)) + +/*! Parameter valid check for start condition */ +#define IS_VALID_START_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_START_COND_ALL) == TMR6_START_COND_ALL)) + +/*! Parameter valid check for stop condition */ +#define IS_VALID_STOP_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_STOP_COND_ALL) == TMR6_STOP_COND_ALL)) + +/*! Parameter valid check for clear condition */ +#define IS_VALID_CLR_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_CLR_COND_ALL) == TMR6_CLR_COND_ALL)) + +/*! Parameter valid check for capture condition */ +#define IS_VALID_CAPT_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_CAPT_COND_ALL) == TMR6_CAPT_COND_ALL)) + +/*! Parameter valid check for hardware count up condition */ +#define IS_VALID_CNT_UP_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_CNT_UP_COND_ALL) == TMR6_CNT_UP_COND_ALL)) + +/*! Parameter valid check for hardware count down condition */ +#define IS_VALID_CNT_DOWN_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_CNT_DOWN_COND_ALL) == TMR6_CNT_DOWN_COND_ALL)) + +/*! Parameter valid check for count Mode */ +#define IS_VALID_CNT_MD(x) \ +( ((x) == TMR6_MD_SAWTOOTH) || \ + ((x) == TMR6_MD_TRIANGLE_A) || \ + ((x) == TMR6_MD_TRIANGLE_B)) + +/*! Parameter valid check for count direction */ +#define IS_VALID_CNT_DIR(x) \ +( ((x) == TMR6_CNT_UP) || \ + ((x) == TMR6_CNT_DOWN)) + +/*! Parameter valid check for count clock division */ +#define IS_VALID_CNT_CLK_DIV(x) \ +( ((x) == TMR6_CLK_DIV1) || \ + ((x) == TMR6_CLK_DIV2) || \ + ((x) == TMR6_CLK_DIV4) || \ + ((x) == TMR6_CLK_DIV8) || \ + ((x) == TMR6_CLK_DIV16) || \ + ((x) == TMR6_CLK_DIV64) || \ + ((x) == TMR6_CLK_DIV256) || \ + ((x) == TMR6_CLK_DIV1024)) + +/*! Parameter valid check for Z Mask input function mask cycles number */ +#define IS_VALID_ZMASK_CYCLES(x) \ +( ((x) == TMR6_ZMASK_FUNC_INVD) || \ + ((x) == TMR6_ZMASK_CYCLE_4) || \ + ((x) == TMR6_ZMASK_CYCLE_8) || \ + ((x) == TMR6_ZMASK_CYCLE_16)) + +/*! Parameter valid check for Z Mask function of timer6 position unit */ +#define IS_VALID_POS_UNIT_ZMASK_FUNC(x) \ +( ((x) == TMR6_POS_CLR_ZMASK_FUNC_OFF) || \ + ((x) == TMR6_POS_CLR_ZMASK_FUNC_ON)) + +/*! Parameter valid check for Z Mask function of timer6 revolution unit */ +#define IS_VALID_REVO_UNIT_ZMASK_FUNC(x) \ +( ((x) == TMR6_REVO_CNT_ZMASK_FUNC_OFF) || \ + ((x) == TMR6_REVO_CNT_ZMASK_FUNC_ON)) + +/*! Parameter valid check for software sync control unit */ +#define IS_VALID_SW_UNIT(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_SW_SYNC_ALL) == TMR6_SW_SYNC_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup TMR6_Global_Functions TMR6 Global Functions + * @{ + */ + +/** + * @brief Initialize the timer6 count function + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] pstcTmr6Init Pointer of configuration structure @ref stc_tmr6_init_t + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_Init(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_init_t *pstcTmr6Init) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if (NULL != pstcTmr6Init) { + /* Check parameters */ + DDL_ASSERT(IS_TMR6_CNT_SRC(pstcTmr6Init->u8CountSrc)); + + if (pstcTmr6Init->u8CountSrc == TMR6_CNT_SRC_SW) { + /* Normal count */ + DDL_ASSERT(IS_VALID_CNT_MD(pstcTmr6Init->sw_count.u32CountMode)); + DDL_ASSERT(IS_VALID_CNT_DIR(pstcTmr6Init->sw_count.u32CountDir)); + DDL_ASSERT(IS_VALID_CNT_CLK_DIV(pstcTmr6Init->sw_count.u32ClockDiv)); + + MODIFY_REG32(TMR6x->GCONR, TMR6_INIT_MASK, (pstcTmr6Init->sw_count.u32CountMode | pstcTmr6Init->sw_count.u32CountDir | \ + pstcTmr6Init->sw_count.u32ClockDiv)); + } else { + /* Hardware count */ + DDL_ASSERT(IS_VALID_CNT_UP_COND(pstcTmr6Init->hw_count.u32CountUpCond) || + (pstcTmr6Init->hw_count.u32CountUpCond == TMR6_CNT_UP_COND_INVD)); + DDL_ASSERT(IS_VALID_CNT_DOWN_COND(pstcTmr6Init->hw_count.u32CountDownCond) || + (pstcTmr6Init->hw_count.u32CountDownCond == TMR6_CNT_DOWN_COND_INVD)); + + WRITE_REG32(TMR6x->HCUPR, pstcTmr6Init->hw_count.u32CountUpCond); + WRITE_REG32(TMR6x->HCDOR, pstcTmr6Init->hw_count.u32CountDownCond); + } + + DDL_ASSERT(IS_VALID_REG_RANGE_U16(pstcTmr6Init->u32PeriodValue)); + WRITE_REG32(TMR6x->PERAR, pstcTmr6Init->u32PeriodValue); + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set timer6 base count mode + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Mode @ref TMR6_Count_Mode_Define + * @retval None + */ +void TMR6_SetCountMode(CM_TMR6_TypeDef *TMR6x, uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_MD(u32Mode)); + MODIFY_REG32(TMR6x->GCONR, TMR6_GCONR_MODE, u32Mode); +} + +/** + * @brief Set timer6 base count direction + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Dir @ref TMR6_Count_Dir_Define + * @retval None + */ +void TMR6_SetCountDir(CM_TMR6_TypeDef *TMR6x, uint32_t u32Dir) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_DIR(u32Dir)); + MODIFY_REG32(TMR6x->GCONR, TMR6_GCONR_DIR, u32Dir); +} + +/** + * @brief Set timer6 base count direction + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval uint32_t Count direction @ref TMR6_Count_Dir_Status_Define + */ +uint32_t TMR6_GetCountDir(CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + return READ_REG32_BIT(TMR6x->STFLR, TMR6_STFLR_DIRF); +} + +/** + * @brief Set timer6 clock division + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Div @ref TMR6_Count_Clock_Define + * @retval None + */ +void TMR6_SetClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Div) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CLK_DIV(u32Div)); + + MODIFY_REG32(TMR6x->GCONR, TMR6_GCONR_CKDIV, u32Div); +} + +/** + * @brief Hardware increase condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware count, maybe one or any combination of the parameter + * @ref TMR6_HW_Count_Up_Cond_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWCountUpCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_UP_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HCUPR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HCUPR, u32Cond); + } +} + +/** + * @brief Hardware decrease condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware count, maybe one or any combination of the parameter + * @ref TMR6_HW_Count_Down_Cond_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWCountDownCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_DOWN_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HCDOR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HCDOR, u32Cond); + } +} + +/** + * @brief Initialize the timer6 hardware count function + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch @ref TMR6_Count_Ch_Define + * @param [in] pstcPwmInit Pointer of initialize structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_PWM_Init(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_pwm_init_t *pstcPwmInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + __IO uint32_t *TMR6_GCMxR; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + + TMR6_GCMxR = (__IO uint32_t *)((uint32_t)&TMR6x->GCMAR + 4UL * u32Ch); + + if (NULL != pstcPwmInit) { + DDL_ASSERT(IS_VALID_PWM_POLARITY_START_STOP(pstcPwmInit->u32StartPolarity)); + DDL_ASSERT(IS_VALID_PWM_POLARITY_START_STOP(pstcPwmInit->u32StopPolarity)); + DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32CompareMatchPolarity)); + DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32PeriodMatchPolarity)); + DDL_ASSERT(IS_VALID_PWM_START_STOP_HOLD(pstcPwmInit->u32StartStopHold)); + DDL_ASSERT(IS_VALID_REG_RANGE_U16(pstcPwmInit->u32CompareValue)); + WRITE_REG32(*TMR6_GCMxR, pstcPwmInit->u32CompareValue); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->PCONR, PCONR_REG_CHA_OUTPUT_CFG_MASK, \ + pstcPwmInit->u32CompareMatchPolarity << TMR6_PCONR_CMPCA_POS \ + | pstcPwmInit->u32PeriodMatchPolarity << TMR6_PCONR_PERCA_POS \ + | pstcPwmInit->u32StopPolarity << TMR6_PCONR_STPCA_POS \ + | pstcPwmInit->u32StartPolarity << TMR6_PCONR_STACA_POS \ + | pstcPwmInit->u32StartStopHold); + } else { + MODIFY_REG32(TMR6x->PCONR, PCONR_REG_CHB_OUTPUT_CFG_MASK, \ + pstcPwmInit->u32CompareMatchPolarity << TMR6_PCONR_CMPCB_POS \ + | pstcPwmInit->u32PeriodMatchPolarity << TMR6_PCONR_PERCB_POS \ + | pstcPwmInit->u32StopPolarity << TMR6_PCONR_STPCB_POS \ + | pstcPwmInit->u32StartPolarity << TMR6_PCONR_STACB_POS \ + | pstcPwmInit->u32StartStopHold); + } + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Timer6 PWM output command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch @ref TMR6_Count_Ch_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_PWM_OutputCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + uint32_t u32Tmp; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + u32Tmp = 0xFFFFFFFFUL; + } else { + u32Tmp = 0UL; + } + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->PCONR, TMR6_PCONR_OUTENA, u32Tmp); + } else { + MODIFY_REG32(TMR6x->PCONR, TMR6_PCONR_OUTENB, u32Tmp); + } +} + +/** + * @brief Timer6 set pin polarity + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch @ref TMR6_Count_Ch_Define + * @param [in] u32CountState Polarity set for @ref TMR6_Count_State_Define + * @param [in] u32Polarity @ref TMR6_Pin_Polarity_Define + * @retval None + */ +void TMR6_PWM_SetPolarity(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32CountState, uint32_t u32Polarity) +{ + uint32_t u32PolarityMask = PCONR_REG_POLARITY_MASK; + + uint8_t au8Pos[4] = {TMR6_PCONR_STACA_POS, TMR6_PCONR_STPCA_POS, TMR6_PCONR_CMPCA_POS, TMR6_PCONR_PERCA_POS }; + DDL_ASSERT(IS_VALID_CNT_STAT(u32CountState)); + if ((TMR6_STAT_START == u32CountState) || (TMR6_STAT_STOP == u32CountState)) { + DDL_ASSERT(IS_VALID_PWM_POLARITY_START_STOP(u32Polarity)); + u32PolarityMask = PCONR_REG_POLARITY_START_STOP_MASK; + } else { + DDL_ASSERT(IS_VALID_PWM_POLARITY(u32Polarity)); + } + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + + u32Polarity <<= au8Pos[u32CountState]; + u32PolarityMask <<= au8Pos[u32CountState]; + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->PCONR, u32PolarityMask, u32Polarity); + } else { + MODIFY_REG32(TMR6x->PCONR, u32PolarityMask << PCONR_REG_CHB_SHIFT, u32Polarity << PCONR_REG_CHB_SHIFT); + } +} + +/** + * @brief Timer6 set force polarity when next period + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch @ref TMR6_Count_Ch_Define + * @param [in] u32HoldStatus @ref TMR6_Output_StaStp_Hold_Define + * @retval None + */ +void TMR6_PWM_SetStartStopHold(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32HoldStatus) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_PWM_START_STOP_HOLD(u32HoldStatus)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->PCONR, TMR6_PCONR_STASTPSA, u32HoldStatus); + } else { + MODIFY_REG32(TMR6x->PCONR, TMR6_PCONR_STASTPSB, u32HoldStatus << PCONR_REG_CHB_SHIFT); + } +} + +/** + * @brief Hardware capture condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch Input pin select @ref TMR6_Count_Ch_Define + * @param [in] u32Cond Events source for hardware capture, maybe one or any combination of the parameter + * @ref TMR6_hardware_capture_condition_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWCaptureCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState) +{ + __IO uint32_t *HCPxR; + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_CAPT_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + HCPxR = (__IO uint32_t *)((uint32_t)&TMR6x->HCPAR + (u32Ch * 4UL)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(*HCPxR, u32Cond); + } else { + CLR_REG32_BIT(*HCPxR, u32Cond); + } +} + +/** + * @brief Port input filter function configuration(Trig) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Pin Pin to be configured @ref TMR6_Pin_Define + * @param [in] u32Div Filter clock @ref TMR6_Input_Filter_Clock + * @retval None + */ +void TMR6_SetFilterClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, uint32_t u32Div) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PIN(u32Pin)); + DDL_ASSERT(IS_VALID_FILTER_CLK(u32Div)); + + switch (u32Pin) { + case TMR6_IO_PWMA: + MODIFY_REG32(TMR6x->FCONR, TMR6_FCONR_NOFICKGA, u32Div << TMR6_FCONR_NOFICKGA_POS); + break; + case TMR6_IO_PWMB: + MODIFY_REG32(TMR6x->FCONR, TMR6_FCONR_NOFICKGB, u32Div << TMR6_FCONR_NOFICKGB_POS); + break; + case TMR6_INPUT_TRIGA: + MODIFY_REG32(CM_TMR6_1->FCONR, TMR6_FCONR_NOFICKTA, u32Div << TMR6_FCONR_NOFICKTA_POS); + break; + case TMR6_INPUT_TRIGB: + MODIFY_REG32(CM_TMR6_1->FCONR, TMR6_FCONR_NOFICKTB, u32Div << TMR6_FCONR_NOFICKTB_POS); + break; + default: + break; + } +} + +/** + * @brief Port input filter function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Pin Input port to be configured @ref TMR6_Pin_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_FilterCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PIN(u32Pin)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + switch (u32Pin) { + case TMR6_IO_PWMA: + MODIFY_REG32(TMR6x->FCONR, TMR6_FCONR_NOFIENGA, ((uint32_t)enNewState) << TMR6_FCONR_NOFIENGA_POS); + break; + case TMR6_IO_PWMB: + MODIFY_REG32(TMR6x->FCONR, TMR6_FCONR_NOFIENGB, ((uint32_t)enNewState) << TMR6_FCONR_NOFIENGB_POS); + break; + case TMR6_INPUT_TRIGA: + MODIFY_REG32(CM_TMR6_1->FCONR, TMR6_FCONR_NOFIENTA, ((uint32_t)enNewState) << TMR6_FCONR_NOFIENTA_POS); + break; + case TMR6_INPUT_TRIGB: + MODIFY_REG32(CM_TMR6_1->FCONR, TMR6_FCONR_NOFIENTB, ((uint32_t)enNewState) << TMR6_FCONR_NOFIENTB_POS); + break; + default: + break; + } +} + +/** + * @brief Set channel function + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch Channel to be configured @ref TMR6_Count_Ch_Define + * @param [in] u32Func IO mode @ref TMR6_Pin_Mode_Define + * @retval None + */ +void TMR6_SetFunc(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Func) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_PIN_MD(u32Func)); + + switch (u32Ch) { + case TMR6_CH_A: + MODIFY_REG32(TMR6x->PCONR, TMR6_PCONR_CAPMDA, u32Func); + break; + case TMR6_CH_B: + MODIFY_REG32(TMR6x->PCONR, TMR6_PCONR_CAPMDB, u32Func << TMR6_PCONR_CAPMDB_POS); + break; + default: + break; + } +} + +/** + * @brief Timer6 interrupt enable or disable + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32IntType Irq flag, Can be one or any combination of the values from + * @ref TMR6_Int_Flag_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_IntCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32IntType, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_IRQ(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->ICONR, u32IntType); + } else { + CLR_REG32_BIT(TMR6x->ICONR, u32IntType); + } +} + +/** + * @brief Get Timer6 status flag + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Flag Status bit to be read, Can be one or any combination of the values from + * @ref TMR6_Stat_Flag_Define + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t TMR6_GetStatus(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag) +{ + en_flag_status_t enStatus = RESET; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_GET_FLAG(u32Flag)); + + if (0UL != READ_REG32_BIT(TMR6x->STFLR, u32Flag)) { + enStatus = SET; + } + return enStatus; +} + +/** + * @brief Clear Timer6 status flag + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Flag Status bit to be read, Can be one or any combination of the values from + * @ref TMR6_Stat_Flag_Define + * @retval None + */ +void TMR6_ClearStatus(CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CLR_FLAG(u32Flag)); + + CLR_REG32_BIT(TMR6x->STFLR, u32Flag); +} + +/** + * @brief Get Timer6 period number when valid period function enable + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval uint32_t Data for periods number + */ +uint32_t TMR6_GetPeriodNum(const CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + return (READ_REG32_BIT(TMR6x->STFLR, TMR6_STFLR_VPERNUM) >> TMR6_STFLR_VPERNUM_POS); +} + +/** + * @brief De-initialize the timer6 unit + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval None + */ +void TMR6_DeInit(CM_TMR6_TypeDef *TMR6x) +{ + uint32_t u32RefRegResetValue; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + u32RefRegResetValue = TMR6_REG_RST_VALUE_U16; + + WRITE_REG32(TMR6x->GCONR, TMR6_REG_GCONR_RST_VALUE); + WRITE_REG32(TMR6x->CNTER, 0UL); + WRITE_REG32(TMR6x->PERAR, u32RefRegResetValue); + WRITE_REG32(TMR6x->PERBR, u32RefRegResetValue); + WRITE_REG32(TMR6x->PERCR, u32RefRegResetValue); + WRITE_REG32(TMR6x->GCMAR, u32RefRegResetValue); + WRITE_REG32(TMR6x->GCMBR, u32RefRegResetValue); + WRITE_REG32(TMR6x->GCMCR, u32RefRegResetValue); + WRITE_REG32(TMR6x->GCMDR, u32RefRegResetValue); + WRITE_REG32(TMR6x->GCMER, u32RefRegResetValue); + WRITE_REG32(TMR6x->GCMFR, u32RefRegResetValue); + WRITE_REG32(TMR6x->SCMAR, u32RefRegResetValue); + WRITE_REG32(TMR6x->SCMBR, u32RefRegResetValue); + WRITE_REG32(TMR6x->SCMCR, u32RefRegResetValue); + WRITE_REG32(TMR6x->SCMDR, u32RefRegResetValue); + WRITE_REG32(TMR6x->SCMER, u32RefRegResetValue); + WRITE_REG32(TMR6x->SCMFR, u32RefRegResetValue); + WRITE_REG32(TMR6x->DTUAR, u32RefRegResetValue); + WRITE_REG32(TMR6x->DTDAR, u32RefRegResetValue); + WRITE_REG32(TMR6x->DTUBR, u32RefRegResetValue); + WRITE_REG32(TMR6x->DTDBR, u32RefRegResetValue); + WRITE_REG32(TMR6x->ICONR, 0UL); + WRITE_REG32(TMR6x->BCONR, 0UL); + WRITE_REG32(TMR6x->DCONR, 0UL); + WRITE_REG32(TMR6x->PCONR, 0UL); + WRITE_REG32(TMR6x->FCONR, 0UL); + WRITE_REG32(TMR6x->VPERR, 0UL); + WRITE_REG32(TMR6x->STFLR, 0UL); + WRITE_REG32(TMR6x->HSTAR, 0UL); + WRITE_REG32(TMR6x->HSTPR, 0UL); + WRITE_REG32(TMR6x->HCLRR, 0UL); + WRITE_REG32(TMR6x->HCPAR, 0UL); + WRITE_REG32(TMR6x->HCPBR, 0UL); + WRITE_REG32(TMR6x->HCUPR, 0UL); + WRITE_REG32(TMR6x->HCDOR, 0UL); + + WRITE_REG32(CM_TMR6CR->SSTAR, 0UL); + WRITE_REG32(CM_TMR6CR->SSTPR, 0UL); + WRITE_REG32(CM_TMR6CR->SCLRR, 0UL); +} + +/** + * @brief Timer6 count start + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval None + */ +void TMR6_Start(CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + SET_REG32_BIT(TMR6x->GCONR, TMR6_GCONR_START); +} + +/** + * @brief Timer6 count stop + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval None + */ +void TMR6_Stop(CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + CLR_REG32_BIT(TMR6x->GCONR, TMR6_GCONR_START); +} + +/** + * @brief Timer6 counter register set + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Value Counter value + * @retval None + */ +void TMR6_SetCountValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG32(TMR6x->CNTER, u32Value); +} + +/** + * @brief Timer6 get counter register value + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval uint32_t Data for the count register value + */ +uint32_t TMR6_GetCountValue(const CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + return READ_REG32(TMR6x->CNTER); +} + +/** + * @brief Timer6 set period register(A~C) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Period register to be write, @ref TMR6_Period_Reg_Index_Define + * @param [in] u32Value Period value for write + * @retval None + */ +void TMR6_SetPeriodValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value) +{ + __IO uint32_t *TMR6_PERxR; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PERIOD_REG(u32Index)); + + TMR6_PERxR = (uint32_t *)((uint32_t)&TMR6x->PERAR + 4UL * u32Index); + + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG32(*TMR6_PERxR, u32Value); +} + +/** + * @brief Timer6 set general compare register(A~F) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index General compare register to be write, @ref TMR6_Compare_Reg_Index_Define + * @param [in] u32Value Value for write + * @retval None + */ +void TMR6_SetCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value) +{ + __IO uint32_t *TMR6_GCMxR; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_REG(u32Index)); + TMR6_GCMxR = (__IO uint32_t *)((uint32_t)&TMR6x->GCMAR + 4UL * u32Index); + + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG32(*TMR6_GCMxR, u32Value); +} + +/** + * @brief Timer6 set special compare register(A~F) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Special compare register to be write, @ref TMR6_Compare_Reg_Index_Define + * @param [in] u32Value Value for write + * @retval None + */ +void TMR6_SetSpecialCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value) +{ + __IO uint32_t *TMR6_SCMxR; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_REG(u32Index)); + TMR6_SCMxR = (uint32_t *)((uint32_t)&TMR6x->SCMAR + 4UL * u32Index); + + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG32(*TMR6_SCMxR, u32Value); +} + +/** + * @brief Timer6 set dead time register + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Special compare register to be write, @ref TMR6_DeadTime_Reg_Define + * @param [in] u32Value Value for write + * @retval None + */ +void TMR6_SetDeadTimeValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value) +{ + __IO uint32_t *TMR6_DTxyR; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_DEADTIME_REG(u32Index)); + TMR6_DTxyR = (uint32_t *)((uint32_t)&TMR6x->DTUAR + 4UL * u32Index); + + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG32(*TMR6_DTxyR, u32Value); +} + +/** + * @brief Timer6 get general compare registers value(A~F) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index General compare register to be read, @ref TMR6_Compare_Reg_Index_Define + * @retval uint32_t Data for value of the register + */ +uint32_t TMR6_GetCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index) +{ + __IO uint32_t *TMR6_GCMxR; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_REG(u32Index)); + TMR6_GCMxR = (uint32_t *)((uint32_t)&TMR6x->GCMAR + 4UL * u32Index); + + return READ_REG32(*TMR6_GCMxR); +} + +/** + * @brief Timer6 get special compare registers value(A~F) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Special compare register to be read, @ref TMR6_Compare_Reg_Index_Define + * @retval uint32_t Data for value of the register + */ +uint32_t TMR6_GetSpecialCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index) +{ + __IO uint32_t *TMR6_SCMxR; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_REG(u32Index)); + TMR6_SCMxR = (uint32_t *)((uint32_t)&TMR6x->SCMAR + 4UL * u32Index); + + return READ_REG32(*TMR6_SCMxR); +} + +/** + * @brief Timer6 Get period register(A~C) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Period register to be write, @ref TMR6_Period_Reg_Index_Define + * @retval uint32_t Data for value of the register + */ +uint32_t TMR6_GetPeriodValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index) +{ + __IO uint32_t *TMR6_PERxR; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PERIOD_REG(u32Index)); + TMR6_PERxR = (uint32_t *)((uint32_t)&TMR6x->PERAR + 4UL * u32Index); + + return READ_REG32(*TMR6_PERxR); +} + +/** + * @brief Timer6 get dead time register + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Dead time register to be write, @ref TMR6_DeadTime_Reg_Define + * @retval uint32_t Data for value of the register + */ +uint32_t TMR6_GetDeadTimeValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index) +{ + __IO uint32_t *TMR6_DTxyR; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_DEADTIME_REG(u32Index)); + TMR6_DTxyR = (uint32_t *)((uint32_t)&TMR6x->DTUAR + 4UL * u32Index); + + return READ_REG32(*TMR6_DTxyR); +} + +/** + * @brief Timer6 general compare buffer function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch General compare buffer chose @ref TMR6_Count_Ch_Define + * @param [in] u32BufNum Buffer number @ref TMR6_Buf_Num_Define + * @retval None + */ +void TMR6_SetGeneralBufNum(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32BufNum) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_BUF_NUM(u32BufNum)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->BCONR, BCONR_GEN_CFG_MASK, u32BufNum); + } else { + MODIFY_REG32(TMR6x->BCONR, BCONR_GEN_CFG_MASK << BCONR_GEN_CFG_CHB_OFS, u32BufNum << BCONR_GEN_CFG_CHB_OFS); + } +} + +/** + * @brief Timer6 general compare buffer function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch General compare buffer chose, @ref TMR6_Count_Ch_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_GeneralBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK, enNewState); + } else { + MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK << BCONR_GEN_CFG_CHB_OFS, \ + ((uint32_t)enNewState) << BCONR_GEN_CFG_CHB_OFS); + } +} + +/** + * @brief Timer6 special compare buffer function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch Special compare buffer chose, @ref TMR6_Count_Ch_Define + * @param [in] pstcBufConfig Pointer of configuration structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_SpecialBufConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_buf_config_t *pstcBufConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + if (NULL != pstcBufConfig) { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_BUF_NUM(pstcBufConfig->u32BufNum)); + DDL_ASSERT(IS_VALID_BUF_TRANS_TRIG(pstcBufConfig->u32BufTransCond)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->BCONR, BCONR_SPECIAL_CFG_MASK << BCONR_SPECIAL_CFG_CHA_OFS, \ + (pstcBufConfig->u32BufNum << BCONR_SPECIAL_CFG_CHA_OFS) \ + | (pstcBufConfig->u32BufTransCond << BCONR_SPECIAL_CFG_TRIG_CHA_OFS)); + } else { + MODIFY_REG32(TMR6x->BCONR, BCONR_SPECIAL_CFG_MASK << BCONR_SPECIAL_CFG_CHB_OFS, \ + (pstcBufConfig->u32BufNum << BCONR_SPECIAL_CFG_CHB_OFS) | \ + (pstcBufConfig->u32BufTransCond << BCONR_SPECIAL_CFG_TRIG_CHB_OFS)); + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Timer6 special compare buffer function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch General compare buffer chose, @ref TMR6_Count_Ch_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_SpecialBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK << BCONR_SPECIAL_CFG_CHA_OFS, \ + ((uint32_t)enNewState) << BCONR_SPECIAL_CFG_CHA_OFS); + } else { + MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK << BCONR_SPECIAL_CFG_CHB_OFS, \ + ((uint32_t)enNewState) << BCONR_SPECIAL_CFG_CHB_OFS); + } +} + +/** + * @brief Timer6 period buffer function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32BufNum Buffer number @ref TMR6_Buf_Num_Define + * @retval None + */ +void TMR6_SetPeriodBufNum(CM_TMR6_TypeDef *TMR6x, uint32_t u32BufNum) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_BUF_NUM(u32BufNum)); + + MODIFY_REG32(TMR6x->BCONR, BCONR_PERIOD_CFG_MASK << BCONR_PERIOD_CFG_OFS, u32BufNum << BCONR_PERIOD_CFG_OFS); +} + +/** + * @brief Timer6 period buffer function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_PeriodBufCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK << BCONR_PERIOD_CFG_OFS, + ((uint32_t)enNewState) << BCONR_PERIOD_CFG_OFS); +} + +/** + * @brief Timer6 valid period function configuration for special compare function + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] pstcValidperiodConfig Pointer of configuration structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_ValidPeriodConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_valid_period_config_t *pstcValidperiodConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + if (NULL != pstcValidperiodConfig) { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PERIOD_CNT_COND(pstcValidperiodConfig->u32CountCond)); + DDL_ASSERT(IS_VALID_PERIOD_CNT(pstcValidperiodConfig->u32PeriodInterval)); + + MODIFY_REG32(TMR6x->VPERR, TMR6_VPERR_PCNTS | TMR6_VPERR_PCNTE, \ + pstcValidperiodConfig->u32CountCond | pstcValidperiodConfig->u32PeriodInterval); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Timer6 valid period function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch General compare buffer chose, @ref TMR6_Count_Ch_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_ValidPeriodCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->VPERR, TMR6_VPERR_SPPERIA, ((uint32_t)enNewState) << TMR6_VPERR_SPPERIA_POS); + } else { + MODIFY_REG32(TMR6x->VPERR, TMR6_VPERR_SPPERIB, ((uint32_t)enNewState) << TMR6_VPERR_SPPERIB_POS); + } +} + +/** + * @brief Timer6 dead time function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_DeadTimeFuncCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->DCONR, TMR6_DCONR_DTCEN); + } else { + CLR_REG32_BIT(TMR6x->DCONR, TMR6_DCONR_DTCEN); + } +} + +/** + * @brief DeadTime function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] pstcDeadTimeConfig Timer6 dead time config pointer + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_DeadTimeConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_deadtime_config_t *pstcDeadTimeConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if (NULL != pstcDeadTimeConfig) { + DDL_ASSERT(IS_VALID_DEADTIME_EQUAL_FUNC_REG(pstcDeadTimeConfig->u32EqualUpDown)); + DDL_ASSERT(IS_VALID_DEADTIME_BUF_FUNC_DTUAR_REG(pstcDeadTimeConfig->u32BufUp)); + DDL_ASSERT(IS_VALID_DEADTIME_BUF_FUNC_DTDAR_REG(pstcDeadTimeConfig->u32BufDown)); + WRITE_REG32(TMR6x->DCONR, pstcDeadTimeConfig->u32EqualUpDown | pstcDeadTimeConfig->u32BufUp \ + | pstcDeadTimeConfig->u32BufDown); + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Timer6 unit Z phase input mask config + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] pstcZMaskConfig Pointer of configuration structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_ZMaskConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_zmask_config_t *pstcZMaskConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if (NULL != pstcZMaskConfig) { + DDL_ASSERT(IS_VALID_ZMASK_CYCLES(pstcZMaskConfig->u32ZMaskCycle)); + DDL_ASSERT(IS_VALID_POS_UNIT_ZMASK_FUNC(pstcZMaskConfig->u32PosCountMaskFunc)); + DDL_ASSERT(IS_VALID_REVO_UNIT_ZMASK_FUNC(pstcZMaskConfig->u32RevoCountMaskFunc)); + + MODIFY_REG32(TMR6x->GCONR, TMR6_ZMASK_CFG_MASK, pstcZMaskConfig->u32ZMaskCycle | \ + pstcZMaskConfig->u32PosCountMaskFunc | pstcZMaskConfig->u32RevoCountMaskFunc); + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief EMB function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch Channel to be configured @ref TMR6_Count_Ch_Define + * @param [in] pstcEmbConfig Point EMB function Config Pointer + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_EMBConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_emb_config_t *pstcEmbConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if (NULL != pstcEmbConfig) { + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_EMB_VALID_PIN_POLARITY(pstcEmbConfig->u32PinStatus)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->PCONR, TMR6_PCONR_EMBVALA, pstcEmbConfig->u32PinStatus); + } else { + MODIFY_REG32(TMR6x->PCONR, TMR6_PCONR_EMBVALB, + pstcEmbConfig->u32PinStatus << (TMR6_PCONR_EMBVALB_POS - TMR6_PCONR_EMBVALA_POS)); + } + + i32Ret = LL_OK; + } + return i32Ret; + +} + +/** + * @brief Software Sync Start + * @param [in] u32Unit Software Sync units, This parameter can be one or any combination of the parameter + * @ref TMR6_SW_Sync_Unit_define + * @retval None + */ +void TMR6_SWSyncStart(uint32_t u32Unit) +{ + DDL_ASSERT(IS_VALID_SW_UNIT(u32Unit)); + WRITE_REG32(CM_TMR6CR->SSTAR, u32Unit); +} + +/** + * @brief Software Sync Stop + * @param [in] u32Unit Software Sync units, This parameter can be one or any combination of the parameter + * @ref TMR6_SW_Sync_Unit_define + * @retval None + */ +void TMR6_SWSyncStop(uint32_t u32Unit) +{ + DDL_ASSERT(IS_VALID_SW_UNIT(u32Unit)); + WRITE_REG32(CM_TMR6CR->SSTPR, u32Unit); +} + +/** + * @brief Software Sync clear + * @param [in] u32Unit Software Sync units, This parameter can be one or any combination of the parameter + * @ref TMR6_SW_Sync_Unit_define + * @retval None + */ +void TMR6_SWSyncClear(uint32_t u32Unit) +{ + DDL_ASSERT(IS_VALID_SW_UNIT(u32Unit)); + WRITE_REG32(CM_TMR6CR->SCLRR, u32Unit); +} + +/** + * @brief Hardware start function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWStartCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->HSTAR, TMR6_HSTAR_STAS, ((uint32_t)enNewState) << TMR6_HSTAR_STAS_POS); +} + +/** + * @brief Hardware stop function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWStopCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->HSTPR, TMR6_HSTPR_STPS, ((uint32_t)enNewState) << TMR6_HSTPR_STPS_POS); +} + +/** + * @brief Hardware clear function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWClearCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->HCLRR, TMR6_HCLRR_CLES, ((uint32_t)enNewState) << TMR6_HCLRR_CLES_POS); +} + +/** + * @brief Hardware start condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware start, maybe one or any combination of the parameter + * @ref TMR6_hardware_start_condition_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWStartCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_START_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HSTAR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HSTAR, u32Cond); + } +} + +/** + * @brief Hardware stop condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware stop, maybe one or any combination of the parameter + * @ref TMR6_hardware_stop_condition_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWStopCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_STOP_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HSTPR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HSTPR, u32Cond); + } +} + +/** + * @brief Hardware clear condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware clear, maybe one or any combination of the parameter + * @ref TMR6_hardware_clear_condition_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWClearCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CLR_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HCLRR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HCLRR, u32Cond); + } +} + +/** + * @brief Set the fields of structure stc_tmr6_init_t to default values + * @param [out] pstcTmr6Init Pointer to a @ref stc_tmr6_init_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_StructInit(stc_tmr6_init_t *pstcTmr6Init) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32RefRegResetValue; + + /* Check structure pointer */ + if (NULL != pstcTmr6Init) { + pstcTmr6Init->u8CountSrc = TMR6_CNT_SRC_SW; + pstcTmr6Init->sw_count.u32ClockDiv = TMR6_CLK_DIV1; + pstcTmr6Init->sw_count.u32CountMode = TMR6_MD_SAWTOOTH; + pstcTmr6Init->sw_count.u32CountDir = TMR6_CNT_UP; + pstcTmr6Init->hw_count.u32CountUpCond = TMR6_CNT_UP_COND_INVD; + pstcTmr6Init->hw_count.u32CountDownCond = TMR6_CNT_DOWN_COND_INVD; + u32RefRegResetValue = TMR6_REG_RST_VALUE_U16; + pstcTmr6Init->u32PeriodValue = u32RefRegResetValue; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_buf_config_t to default values + * @param [out] pstcBufConfig Pointer to a @ref stc_tmr6_buf_config_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_BufFuncStructInit(stc_tmr6_buf_config_t *pstcBufConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check structure pointer */ + if (NULL != pstcBufConfig) { + pstcBufConfig->u32BufNum = TMR6_BUF_SINGLE; + pstcBufConfig->u32BufTransCond = TMR6_BUF_TRANS_INVD; + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_valid_period_config_t to default values + * @param [out] pstcValidperiodConfig Pointer to a @ref stc_tmr6_valid_period_config_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_ValidPeriodStructInit(stc_tmr6_valid_period_config_t *pstcValidperiodConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check structure pointer */ + if (NULL != pstcValidperiodConfig) { + pstcValidperiodConfig->u32CountCond = TMR6_VALID_PERIOD_INVD; + pstcValidperiodConfig->u32PeriodInterval = TMR6_VALID_PERIOD_CNT_INVD; + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_emb_config_t to default values + * @param [out] pstcEmbConfig Pointer to a @ref stc_tmr6_emb_config_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_EMBConfigStructInit(stc_tmr6_emb_config_t *pstcEmbConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check structure pointer */ + if (NULL != pstcEmbConfig) { + pstcEmbConfig->u32PinStatus = TMR6_EMB_PIN_NORMAL; + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_deadtime_config_t to default values + * @param [out] pstcDeadTimeConfig Pointer to a @ref stc_tmr6_deadtime_config_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_DeadTimeStructInit(stc_tmr6_deadtime_config_t *pstcDeadTimeConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check structure pointer */ + if (NULL != pstcDeadTimeConfig) { + pstcDeadTimeConfig->u32EqualUpDown = TMR6_DEADTIME_EQUAL_OFF; + pstcDeadTimeConfig->u32BufUp = TMR6_DEADTIME_CNT_UP_BUF_OFF; + pstcDeadTimeConfig->u32BufDown = TMR6_DEADTIME_CNT_DOWN_BUF_OFF; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_zmask_config_t to default values + * @param [out] pstcZMaskConfig Pointer to a @ref stc_tmr6_zmask_config_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_ZMaskConfigStructInit(stc_tmr6_zmask_config_t *pstcZMaskConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check structure pointer */ + if (NULL != pstcZMaskConfig) { + pstcZMaskConfig->u32ZMaskCycle = TMR6_ZMASK_FUNC_INVD; + pstcZMaskConfig->u32PosCountMaskFunc = TMR6_POS_CLR_ZMASK_FUNC_OFF; + pstcZMaskConfig->u32RevoCountMaskFunc = TMR6_REVO_CNT_ZMASK_FUNC_OFF; + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_pwm_init_t to default values + * @param [out] pstcPwmInit Pointer to a @ref stc_tmr6_pwm_init_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_PWM_StructInit(stc_tmr6_pwm_init_t *pstcPwmInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32RefRegResetValue; + + /* Check structure pointer */ + if (NULL != pstcPwmInit) { + pstcPwmInit->u32StartPolarity = TMR6_PWM_LOW; + pstcPwmInit->u32StopPolarity = TMR6_PWM_LOW; + + u32RefRegResetValue = TMR6_REG_RST_VALUE_U16; + pstcPwmInit->u32CompareMatchPolarity = TMR6_PWM_LOW; + pstcPwmInit->u32PeriodMatchPolarity = TMR6_PWM_LOW; + pstcPwmInit->u32StartStopHold = TMR6_PWM_START_STOP_CHANGE; + pstcPwmInit->u32CompareValue = u32RefRegResetValue; + i32Ret = LL_OK; + } + return i32Ret; +} +/** + * @} + */ + +#endif /* LL_TMR6_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_tmra.c b/mcu/lib/src/hc32_ll_tmra.c new file mode 100644 index 0000000..37c854d --- /dev/null +++ b/mcu/lib/src/hc32_ll_tmra.c @@ -0,0 +1,1144 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmra.c + * @brief This file provides firmware functions to manage the TMRA(TimerA). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-10-31 CDT Comments optimization + 2023-06-30 CDT Modify typo + Update about split 16bit register TMRA_BCSTR into two 8bit registers TMRA_BCSTRH and TMRA_BCSTRL + Delete union in stc_tmra_init_t structure + 2023-09-30 CDT Modify some of member type of struct stc_tmra_init_t and relate fuction about these member + Rename marco definition IS_TMRA_CMPVAL_BUF_COND to IS_TMRA_BUF_TRANS_COND + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_tmra.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TMRA TMRA + * @brief TMRA Driver Library + * @{ + */ + +#if (LL_TMRA_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMRA_Local_Macros TMRA Local Macros + * @{ + */ +/** + * @defgroup TMRA_Registers_Setting_definition TMRA Registers setting definition + * @{ + */ +#define TMRA_REG_TYPE uint16_t +#define TMRA_REG_VALUE_MAX (0xFFFFUL) + +#define SET_VAL_BY_ADDR(addr, v) (*(__IO TMRA_REG_TYPE *)(addr)) = (TMRA_REG_TYPE)(v) +#define GET_VAL_BY_ADDR(addr) (*(__IO TMRA_REG_TYPE *)(addr)) +/** + * @} + */ + +/** + * @defgroup TMRA_Configuration_Bit_Mask TMRA Configuration Bit Mask + * @{ + */ +#define TMRA_BCSTRH_INT_MASK (TMRA_BCSTRH_ITENUDF | TMRA_BCSTRH_ITENOVF) +#define TMRA_BCSTRH_FLAG_MASK (TMRA_BCSTRH_UDFF | TMRA_BCSTRH_OVFF) +#define TMRA_FCONR_FILTER_CLK_MASK (0x3UL) +#define TMRA_CCONR_FILTER_CLK_MASK (TMRA_CCONR_NOFICKCP) +#define TMRA_PWM_POLARITY_MASK (TMRA_PCONR_STAC) +/** + * @} + */ + +/** + * @defgroup TMRA_Filter_Pin_Max TMRA Pin With Filter Max + * @{ + */ +#define TMRA_PIN_MAX (TMRA_PIN_PWM8) +/** + * @} + */ + +/** + * @defgroup TMRA_Check_Parameters_Validity TMRA check parameters validity + * @{ + */ +#define IS_TMRA_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask))) + +#define IS_TMRA_UNIT(x) \ +( ((x) == CM_TMRA_1) || \ + ((x) == CM_TMRA_2) || \ + ((x) == CM_TMRA_3) || \ + ((x) == CM_TMRA_4) || \ + ((x) == CM_TMRA_5) || \ + ((x) == CM_TMRA_6)) + +#define IS_TMRA_SYNC_UNIT(x) \ +( ((x) == CM_TMRA_2) || \ + ((x) == CM_TMRA_3) || \ + ((x) == CM_TMRA_4) || \ + ((x) == CM_TMRA_5) || \ + ((x) == CM_TMRA_6)) + +#define IS_TMRA_CH(x) ((x) <= TMRA_CH8) + +#define IS_TMRA_UNIT_CH(unit, ch) (IS_TMRA_UNIT(unit) && IS_TMRA_CH(ch)) + +#define IS_TMRA_CNT_SRC(x) (((x) == TMRA_CNT_SRC_SW) || ((x) == TMRA_CNT_SRC_HW)) + +#define IS_TMRA_FUNC(x) (((x) == TMRA_FUNC_CMP) || ((x) == TMRA_FUNC_CAPT)) + +#define IS_TMRA_DIR(x) (((x) == TMRA_DIR_DOWN) || ((x) == TMRA_DIR_UP)) + +#define IS_TMRA_MD(x) (((x) == TMRA_MD_SAWTOOTH) || ((x) == TMRA_MD_TRIANGLE)) + +#define IS_TMRA_CMPVAL_BUF_CH(x) \ +( ((x) == TMRA_CH1) || ((x) == TMRA_CH3) || ((x) == TMRA_CH5) || ((x) == TMRA_CH7)) + +#define IS_TMRA_CLK_DIV(x) \ +( ((x) == TMRA_CLK_DIV1) || \ + ((x) == TMRA_CLK_DIV2) || \ + ((x) == TMRA_CLK_DIV4) || \ + ((x) == TMRA_CLK_DIV8) || \ + ((x) == TMRA_CLK_DIV16) || \ + ((x) == TMRA_CLK_DIV32) || \ + ((x) == TMRA_CLK_DIV64) || \ + ((x) == TMRA_CLK_DIV128) || \ + ((x) == TMRA_CLK_DIV256) || \ + ((x) == TMRA_CLK_DIV512) || \ + ((x) == TMRA_CLK_DIV1024)) + +#define IS_TMRA_FILTER_PIN(x) ((x) <= TMRA_PIN_MAX) + +#define IS_TMRA_CNT_UP_COND(x) IS_TMRA_BIT_MASK(x, TMRA_CNT_UP_COND_ALL) + +#define IS_TMRA_CNT_DOWN_COND(x) IS_TMRA_BIT_MASK(x, TMRA_CNT_DOWN_COND_ALL) + +#define IS_TMRA_INT(x) IS_TMRA_BIT_MASK(x, TMRA_INT_ALL) + +#define IS_TMRA_EVT(x) IS_TMRA_BIT_MASK(x, TMRA_EVT_ALL) + +#define IS_TMRA_FLAG(x) IS_TMRA_BIT_MASK(x, TMRA_FLAG_ALL) + +#define IS_TMRA_CAPT_COND(x) IS_TMRA_BIT_MASK(x, TMRA_CAPT_COND_ALL) + +#define IS_TMRA_FILTER_CLK_DIV(x) ((x) <= TMRA_FILTER_CLK_DIV64) + +#define IS_TMRA_UNIT_INT(u, x) (IS_TMRA_UNIT(u) && IS_TMRA_INT(x)) + +#define IS_TMRA_CH_EVT(u, x) (IS_TMRA_UNIT(u) && IS_TMRA_EVT(x)) + +#define IS_TMRA_UNIT_FPIN(u, x) (IS_TMRA_UNIT(u) && IS_TMRA_FILTER_PIN(x)) + +#define IS_TMRA_UNIT_FLAG(u, x) (IS_TMRA_UNIT(u) && IS_TMRA_FLAG(x)) + +#define IS_TMRA_BUF_TRANS_COND(x) \ +( ((x) == TMRA_BUF_TRANS_COND_OVF_UDF_CLR) || \ + ((x) == TMRA_BUF_TRANS_COND_PEAK) || \ + ((x) == TMRA_BUF_TRANS_COND_VALLEY) || \ + ((x) == TMRA_BUF_TRANS_COND_PEAK_VALLEY)) + +#define IS_TMRA_PWM_START_POLARITY(x) \ +( ((x) == TMRA_PWM_LOW) || \ + ((x) == TMRA_PWM_HIGH) || \ + ((x) == TMRA_PWM_HOLD)) + +#define IS_TMRA_PWM_STOP_POLARITY(x) \ +( ((x) == TMRA_PWM_LOW) || \ + ((x) == TMRA_PWM_HIGH) || \ + ((x) == TMRA_PWM_HOLD)) + +#define IS_TMRA_PWM_CMP_POLARITY(x) \ +( ((x) == TMRA_PWM_LOW) || \ + ((x) == TMRA_PWM_HIGH) || \ + ((x) == TMRA_PWM_HOLD) || \ + ((x) == TMRA_PWM_INVT)) + +#define IS_TMRA_PWM_PERIOD_POLARITY(x) \ +( ((x) == TMRA_PWM_LOW) || \ + ((x) == TMRA_PWM_HIGH) || \ + ((x) == TMRA_PWM_HOLD) || \ + ((x) == TMRA_PWM_INVT)) + +#define IS_TMRA_PWM_FORCE_POLARITY(x) \ +( ((x) == TMRA_PWM_FORCE_INVD) || \ + ((x) == TMRA_PWM_FORCE_LOW) || \ + ((x) == TMRA_PWM_FORCE_HIGH)) + +#define IS_TMRA_PWM_POLARITY(st, pol) \ +( (((st) == TMRA_CNT_STAT_START) && IS_TMRA_PWM_START_POLARITY(pol)) || \ + (((st) == TMRA_CNT_STAT_STOP) && IS_TMRA_PWM_STOP_POLARITY(pol)) || \ + (((st) == TMRA_CNT_STAT_MATCH_CMP) && IS_TMRA_PWM_CMP_POLARITY(pol)) || \ + (((st) == TMRA_CNT_STAT_MATCH_PERIOD) && IS_TMRA_PWM_PERIOD_POLARITY(pol))) + +#define IS_TMRA_START_COND(x) IS_TMRA_BIT_MASK((x), TMRA_START_COND_ALL) + +#define IS_TMRA_STOP_COND(x) IS_TMRA_BIT_MASK((x), TMRA_STOP_COND_ALL) + +#define IS_TMRA_CLR_COND(x) IS_TMRA_BIT_MASK((x), TMRA_CLR_COND_ALL) + +/** + * @} + */ + +/** + * @defgroup TMRA_Miscellaneous_Macros TMRA Miscellaneous Macros + * @{ + */ +#define TMRA_PIN_PWM_OFFSET (3U) + +#define TMRA_CH_NUM (8U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup TMRA_Global_Functions TMRA Global Functions + * @{ + */ +/** + * @brief Initializes the specified TMRA peripheral according to the specified parameters + * in the structure stc_tmra_init_t + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] pstcTmraInit Pointer to a stc_tmra_init_t structure value that + * contains the configuration information for the TMRA. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcTmraInit == NULL. + */ +int32_t TMRA_Init(CM_TMRA_TypeDef *TMRAx, const stc_tmra_init_t *pstcTmraInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + if (pstcTmraInit != NULL) { + DDL_ASSERT(IS_TMRA_CNT_SRC(pstcTmraInit->u8CountSrc)); + + if (pstcTmraInit->u8CountSrc == TMRA_CNT_SRC_SW) { + DDL_ASSERT(IS_TMRA_MD(pstcTmraInit->sw_count.u8CountMode)); + DDL_ASSERT(IS_TMRA_DIR(pstcTmraInit->sw_count.u8CountDir)); + DDL_ASSERT(IS_TMRA_CLK_DIV(pstcTmraInit->sw_count.u8ClockDiv)); + + WRITE_REG8(TMRAx->BCSTRL, pstcTmraInit->sw_count.u8CountMode | \ + pstcTmraInit->sw_count.u8CountDir | \ + pstcTmraInit->sw_count.u8ClockDiv); + } else { + DDL_ASSERT(IS_TMRA_CNT_UP_COND(pstcTmraInit->hw_count.u16CountUpCond) || \ + (pstcTmraInit->hw_count.u16CountUpCond == TMRA_CNT_UP_COND_INVD)); + DDL_ASSERT(IS_TMRA_CNT_DOWN_COND(pstcTmraInit->hw_count.u16CountDownCond) || \ + (pstcTmraInit->hw_count.u16CountDownCond == TMRA_CNT_DOWN_COND_INVD)); + WRITE_REG16(TMRAx->HCUPR, pstcTmraInit->hw_count.u16CountUpCond); + WRITE_REG16(TMRAx->HCDOR, pstcTmraInit->hw_count.u16CountDownCond); + } + + /* Specifies period value. */ + TMRA_SetPeriodValue(TMRAx, pstcTmraInit->u32PeriodValue); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set a default value for the TMRA initialization structure. + * @param [out] pstcTmraInit Pointer to a stc_tmra_init_t structure value that + * contains the configuration information for the TMRA. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcTmraInit == NULL. + */ +int32_t TMRA_StructInit(stc_tmra_init_t *pstcTmraInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcTmraInit != NULL) { + pstcTmraInit->u8CountSrc = TMRA_CNT_SRC_SW; + pstcTmraInit->sw_count.u8ClockDiv = TMRA_CLK_DIV1; + pstcTmraInit->sw_count.u8CountMode = TMRA_MD_SAWTOOTH; + pstcTmraInit->sw_count.u8CountDir = TMRA_DIR_UP; + pstcTmraInit->hw_count.u16CountUpCond = TMRA_CNT_UP_COND_INVD; + pstcTmraInit->hw_count.u16CountDownCond = TMRA_CNT_DOWN_COND_INVD; + pstcTmraInit->u32PeriodValue = (TMRA_REG_TYPE)0xFFFFFFFFUL; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Specifies the counting mode for the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u8Mode Count mode. + * This parameter can be a value of @ref TMRA_Count_Mode + * @arg TMRA_MD_SAWTOOTH: Count mode is sawtooth wave. + * @arg TMRA_MD_TRIANGLE: Count mode is triangle wave. + * @retval None + */ +void TMRA_SetCountMode(CM_TMRA_TypeDef *TMRAx, uint8_t u8Mode) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_MD(u8Mode)); + MODIFY_REG8(TMRAx->BCSTRL, TMRA_BCSTRL_MODE, u8Mode); +} + +/** + * @brief Specifies the counting direction for the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u8Dir Count direction. + * This parameter can be a value of @ref TMRA_Count_Dir + * @arg TMRA_DIR_DOWN: TMRA count down. + * @arg TMRA_DIR_UP: TMRA count up. + * @retval None + */ +void TMRA_SetCountDir(CM_TMRA_TypeDef *TMRAx, uint8_t u8Dir) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_DIR(u8Dir)); + MODIFY_REG8(TMRAx->BCSTRL, TMRA_BCSTRL_DIR, u8Dir); +} + +/** + * @brief Specifies the clock divider for the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u8Div Clock divider. + * This parameter can be a value of @ref TMRA_Clock_Divider + * @retval None + */ +void TMRA_SetClockDiv(CM_TMRA_TypeDef *TMRAx, uint8_t u8Div) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CLK_DIV(u8Div)); + MODIFY_REG8(TMRAx->BCSTRL, TMRA_BCSTRL_CKDIV, u8Div); +} + +/** + * @brief Enable or disable the specified hardware count up condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Cond Hardware count up condition. + * This parameter can be values of @ref TMRA_Hard_Count_Up_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWCountUpCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CNT_UP_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->HCUPR, u16Cond); + } else { + CLR_REG16_BIT(TMRAx->HCUPR, u16Cond); + } +} + +/** + * @brief Enable or disable the specified hardware count down condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Cond Hardware count down condition. + * This parameter can be values of @ref TMRA_Hard_Count_Down_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWCountDownCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CNT_DOWN_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->HCDOR, u16Cond); + } else { + CLR_REG16_BIT(TMRAx->HCDOR, u16Cond); + } +} + +/** + * @brief Specifies function mode of TMRA. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Func Function mode of TMRA. + * This parameter can be a value of @ref TMRA_Function_Mode + * @param [in] u32Ch TMRA channel. + * This parameter can be a value of @ref TMRA_Channel + * @retval None + */ +void TMRA_SetFunc(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Func) +{ + uint32_t u32CCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + DDL_ASSERT(IS_TMRA_FUNC(u16Func)); + + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1 + (u32Ch * 4U); + MODIFY_REG16(RW_MEM16(u32CCONRAddr), TMRA_CCONR_CAPMD, u16Func); +} + +/** + * @brief Initializes the PWM according to the specified parameters + * in the structure stc_tmra_pwm_init_t + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] pstcPwmInit Pointer to a stc_tmra_pwm_init_t structure value that + * contains the configuration information for PWM. + * @param [in] u32Ch TMRA channel. + * This parameter can be a value of @ref TMRA_Channel + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcPwmInit == NULL. + */ +int32_t TMRA_PWM_Init(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, const stc_tmra_pwm_init_t *pstcPwmInit) +{ + uint32_t u32CMPARAddr; + uint32_t u32PCONRAddr; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + + if (pstcPwmInit != NULL) { + DDL_ASSERT(IS_TMRA_PWM_START_POLARITY(pstcPwmInit->u16StartPolarity)); + DDL_ASSERT(IS_TMRA_PWM_STOP_POLARITY(pstcPwmInit->u16StopPolarity)); + DDL_ASSERT(IS_TMRA_PWM_CMP_POLARITY(pstcPwmInit->u16CompareMatchPolarity)); + DDL_ASSERT(IS_TMRA_PWM_PERIOD_POLARITY(pstcPwmInit->u16PeriodMatchPolarity)); + + u32Ch *= 4U; + u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1 + u32Ch; + SET_VAL_BY_ADDR(u32CMPARAddr, pstcPwmInit->u32CompareValue); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + u32Ch; + RW_MEM16(u32PCONRAddr) = (uint16_t)((pstcPwmInit->u16StartPolarity << TMRA_PCONR_STAC_POS) | \ + (pstcPwmInit->u16StopPolarity << TMRA_PCONR_STPC_POS) | \ + (pstcPwmInit->u16CompareMatchPolarity << TMRA_PCONR_CMPC_POS) | \ + (pstcPwmInit->u16PeriodMatchPolarity << TMRA_PCONR_PERC_POS)); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set a default value for the PWM initialization structure. + * @param [out] pstcPwmInit Pointer to a stc_tmra_pwm_init_t structure value that + * contains the configuration information for PWM. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcPwmInit == NULL. + */ +int32_t TMRA_PWM_StructInit(stc_tmra_pwm_init_t *pstcPwmInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcPwmInit != NULL) { + pstcPwmInit->u32CompareValue = TMRA_REG_VALUE_MAX; + pstcPwmInit->u16StartPolarity = TMRA_PWM_HIGH; + pstcPwmInit->u16StopPolarity = TMRA_PWM_LOW; + pstcPwmInit->u16CompareMatchPolarity = TMRA_PWM_INVT; + pstcPwmInit->u16PeriodMatchPolarity = TMRA_PWM_INVT; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Enable or disable the PWM ouput of the specified channel. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value of @ref TMRA_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_PWM_OutputCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState) +{ + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (u32Ch * 4U); + WRITE_REG32(PERIPH_BIT_BAND(u32PCONRAddr, TMRA_PCONR_OUTEN_POS), enNewState); +} + +/** + * @brief Specifies the ouput polarity of the PWM at the specified state of counter. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value @ref TMRA_Channel + * @param [in] u8CountState TMRA counter state. + * This parameter can be a value @ref TMRA_Counter_State + * @param [in] u16Polarity The polarity of PWM. + * This parameter can be a value @ref TMRA_PWM_Polarity + * @retval None + * @note The polarity(high or low) when counting start is only valid when the clock is not divided(BCSTRL.CKDIV == 0). + */ +void TMRA_PWM_SetPolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint8_t u8CountState, uint16_t u16Polarity) +{ + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + DDL_ASSERT(IS_TMRA_PWM_POLARITY(u8CountState, u16Polarity)); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (u32Ch * 4U); + MODIFY_REG16(RW_MEM16(u32PCONRAddr), + (uint16_t)TMRA_PWM_POLARITY_MASK << (u8CountState * 2U), + u16Polarity << (u8CountState * 2U)); +} + +/** + * @brief Specifies the force polarity of the PWM. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value @ref TMRA_Channel + * @param [in] u16Polarity The force polarity of PWM. + * This parameter can be a value @ref TMRA_PWM_Force_Polarity + * @retval None + */ +void TMRA_PWM_SetForcePolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Polarity) +{ + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + DDL_ASSERT(IS_TMRA_PWM_FORCE_POLARITY(u16Polarity)); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (u32Ch * 4U); + MODIFY_REG16(RW_MEM16(u32PCONRAddr), TMRA_PCONR_FORC, u16Polarity); +} + +/** + * @brief Enable or disable the specified capture condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value @ref TMRA_Channel + * @param [in] u16Cond The capture condition. + * This parameter can be a value @ref TMRA_Capture_Cond + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWCaptureCondCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState) +{ + uint32_t u32CCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + DDL_ASSERT(IS_TMRA_CAPT_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + +#if defined __DEBUG + if ((u16Cond & (TMRA_CAPT_COND_TRIG_RISING | TMRA_CAPT_COND_TRIG_FALLING)) != 0U) { + DDL_ASSERT(u32Ch == TMRA_CH3); + } +#endif + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1 + (u32Ch * 4U); + if (enNewState == ENABLE) { + SET_REG16_BIT(RW_MEM16(u32CCONRAddr), u16Cond); + } else { + CLR_REG16_BIT(RW_MEM16(u32CCONRAddr), u16Cond); + } +} + +/** + * @brief Enable or disable hardware start condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Cond Hardware start condition. + * This parameter can be a value @ref TMRA_Hardware_Start_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWStartCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_START_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->HCONR, u16Cond); + } else { + CLR_REG16_BIT(TMRAx->HCONR, u16Cond); + } +} + +/** + * @brief Enable or disable hardware stop condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Cond Hardware stop condition. + * This parameter can be a value @ref TMRA_Hardware_Stop_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWStopCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_STOP_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->HCONR, u16Cond); + } else { + CLR_REG16_BIT(TMRAx->HCONR, u16Cond); + } +} + +/** + * @brief Enable or disable hardware clear condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Cond Hardware clear condition. + * This parameter can be a value @ref TMRA_Hardware_Clear_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWClearCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CLR_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->HCONR, u16Cond); + } else { + CLR_REG16_BIT(TMRAx->HCONR, u16Cond); + } +} + +/** + * @brief Specifies the clock divider of filter. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Pin The pin with filter of TMRA. + * This parameter can be a value of @ref TMRA_Filter_Pin + * @param [in] u16Div The clock source divider of the filter. + * This parameter can be a value of @ref TMRA_Filter_Clock_Divider + * @arg TMRA_FILTER_CLK_DIV1: The filter clock is the clock of timerA / 1. + * @arg TMRA_FILTER_CLK_DIV4: The filter clock is the clock of timerA / 4. + * @arg TMRA_FILTER_CLK_DIV16: The filter clock is the clock of timerA / 16. + * @arg TMRA_FILTER_CLK_DIV64: The filter clock is the clock of timerA / 64. + * @retval None + */ +void TMRA_SetFilterClockDiv(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, uint16_t u16Div) +{ + uint32_t u32Ch; + uint32_t u32CCONRAddr; + const uint8_t au8Offset[] = { + TMRA_FCONR_NOFICKTG_POS, TMRA_FCONR_NOFICKCA_POS, TMRA_FCONR_NOFICKCB_POS, + }; + + DDL_ASSERT(IS_TMRA_UNIT_FPIN(TMRAx, u32Pin)); + DDL_ASSERT(IS_TMRA_FILTER_CLK_DIV(u16Div)); + + if (u32Pin < TMRA_PIN_PWM_OFFSET) { + MODIFY_REG16(TMRAx->FCONR, + (TMRA_FCONR_FILTER_CLK_MASK << au8Offset[u32Pin]), + (u16Div << au8Offset[u32Pin])); + } else { + u32Ch = u32Pin - TMRA_PIN_PWM_OFFSET; + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1 + u32Ch * 4U; + MODIFY_REG16(RW_MEM16(u32CCONRAddr), + TMRA_CCONR_FILTER_CLK_MASK, + (u16Div << TMRA_CCONR_NOFICKCP_POS)); + } +} + +/** + * @brief Enable or disable the filter function of the specified TMRA input pin. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Pin The pin with filter of TMRA. + * This parameter can be values of @ref TMRA_Filter_Pin + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_FilterCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, en_functional_state_t enNewState) +{ + uint8_t u8EnPos; + uint32_t u32Ch; + uint32_t u32RegAddr; + const uint8_t au8Offset[] = { + TMRA_FCONR_NOFIENTG_POS, TMRA_FCONR_NOFIENCA_POS, TMRA_FCONR_NOFIENCB_POS, + }; + + DDL_ASSERT(IS_TMRA_UNIT_FPIN(TMRAx, u32Pin)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (u32Pin < TMRA_PIN_PWM_OFFSET) { + u32RegAddr = (uint32_t)&TMRAx->FCONR; + u8EnPos = au8Offset[u32Pin]; + } else { + u32Ch = u32Pin - TMRA_PIN_PWM_OFFSET; + u32RegAddr = (uint32_t)&TMRAx->CCONR1 + u32Ch * 4U; + u8EnPos = TMRA_CCONR_NOFIENCP_POS; + } + WRITE_REG32(PERIPH_BIT_BAND(u32RegAddr, u8EnPos), enNewState); +} + +/** + * @brief De-initializes the TMRA peripheral. Reset all registers of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval None + */ +void TMRA_DeInit(CM_TMRA_TypeDef *TMRAx) +{ + uint32_t i; + uint32_t u32ChNum = TMRA_CH_NUM; + uint32_t u32AddrOffset; + uint32_t u32PERARAddr; + uint32_t u32CNTERAddr; + uint32_t u32CMPARAddr; + uint32_t u32CCONRAddr; + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + + u32PERARAddr = (uint32_t)&TMRAx->PERAR; + u32CNTERAddr = (uint32_t)&TMRAx->CNTER; + u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1; + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1; + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1; + + for (i = 0U; i < u32ChNum; i++) { + u32AddrOffset = i * 4U; + RW_MEM16(u32CMPARAddr + u32AddrOffset) = 0xFFFFU; + RW_MEM16(u32CCONRAddr + u32AddrOffset) = 0x0U; + RW_MEM16(u32PCONRAddr + u32AddrOffset) = 0x0U; + } + + SET_VAL_BY_ADDR(u32PERARAddr, 0xFFFFFFFFUL); + SET_VAL_BY_ADDR(u32CNTERAddr, 0x0U); + WRITE_REG8(TMRAx->BCSTRL, 0x2U); + WRITE_REG8(TMRAx->BCSTRH, 0x0U); + WRITE_REG16(TMRAx->ICONR, 0x0U); + WRITE_REG16(TMRAx->ECONR, 0x0U); + WRITE_REG16(TMRAx->FCONR, 0x0U); + WRITE_REG16(TMRAx->STFLR, 0x0U); + WRITE_REG16(TMRAx->HCONR, 0x0U); + WRITE_REG16(TMRAx->HCUPR, 0x0U); + WRITE_REG16(TMRAx->HCDOR, 0x0U); + WRITE_REG16(TMRAx->BCONR1, 0x0U); + WRITE_REG16(TMRAx->BCONR2, 0x0U); + WRITE_REG16(TMRAx->BCONR3, 0x0U); + WRITE_REG16(TMRAx->BCONR4, 0x0U); +} + +/** + * @brief Get the counting direction of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval An uint8_t type value of counting direction. + * -TMRA_DIR_DOWN: TMRA count down. + * -TMRA_DIR_UP: TMRA count up. + */ +uint8_t TMRA_GetCountDir(const CM_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + return READ_REG8_BIT(TMRAx->BCSTRL, TMRA_BCSTRL_DIR); +} + +/** + * @brief Set period value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Value The period value to be set. + * This parameter can be a number between: + * 0UL and 0xFFFFFFFFUL for 32-bit TimerA units. + * 0UL and 0xFFFFUL for 16-bit TimerA units. + * @retval None + */ +void TMRA_SetPeriodValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value) +{ + uint32_t u32PERARAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + u32PERARAddr = (uint32_t)&TMRAx->PERAR; + SET_VAL_BY_ADDR(u32PERARAddr, u32Value); +} + +/** + * @brief Get period value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval An uint32_t type type value of period value between: + * - 0UL and 0xFFFFFFFFUL for 32-bit TimerA units. + * - 0UL and 0xFFFFUL for 16-bit TimerA units. + */ +uint32_t TMRA_GetPeriodValue(const CM_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + return (TMRAx->PERAR); +} + +/** + * @brief Set general counter value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Value The general counter value to be set. + * This parameter can be a number between: + * 0UL and 0xFFFFFFFFUL for 32-bit TimerA units. + * 0UL and 0xFFFFUL for 16-bit TimerA units. + * @retval None + */ +void TMRA_SetCountValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value) +{ + uint32_t u32CNTERAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + u32CNTERAddr = (uint32_t)&TMRAx->CNTER; + SET_VAL_BY_ADDR(u32CNTERAddr, u32Value); +} + +/** + * @brief Get general counter value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval An uint32_t type type value of counter value between: + * - 0UL and 0xFFFFFFFFUL for 32-bit TimerA units. + * - 0UL and 0xFFFFUL for 16-bit TimerA units. + */ +uint32_t TMRA_GetCountValue(const CM_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + return (TMRAx->CNTER); +} + +/** + * @brief Set comparison value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value of @ref TMRA_Channel + * @param [in] u32Value The comparison value to be set. + * This parameter can be a number between: + * 0UL and 0xFFFFFFFFUL for 32-bit TimerA units. + * 0UL and 0xFFFFUL for 16-bit TimerA units. + * @retval None + */ +void TMRA_SetCompareValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint32_t u32Value) +{ + uint32_t u32CMPARAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + + u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1 + u32Ch * 4U; + SET_VAL_BY_ADDR(u32CMPARAddr, u32Value); +} + +/** + * @brief Get comparison value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value of @ref TMRA_Channel + * @retval An uint32_t type type value of comparison value value between: + * - 0UL and 0xFFFFFFFFUL for 32-bit TimerA units. + * - 0UL and 0xFFFFUL for 16-bit TimerA units. + */ +uint32_t TMRA_GetCompareValue(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch) +{ + uint32_t u32CMPARAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + + u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1 + u32Ch * 4U; + return GET_VAL_BY_ADDR(u32CMPARAddr); +} + +/** + * @brief Enable or disable synchronous-start. When an even unit enables synchronous-start function, + * start the symmetric odd unit can start the even unit at the same time. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x(x is an even number) + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_SyncStartCmd(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_TMRA_SYNC_UNIT(TMRAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Addr = (uint32_t)&TMRAx->BCSTRL; + WRITE_REG32(PERIPH_BIT_BAND(u32Addr, TMRA_BCSTRL_SYNST_POS), enNewState); +} + +/** + * @brief Specifies the condition of compare value buffer transmission. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be one of the odd channels of @ref TMRA_Channel + * @param [in] u16Cond Buffer condition of the specified TMRA unit. + * This parameter can be a value of @ref TMRA_Cmp_Value_Buf_Trans_Cond + * @arg TMRA_BUF_TRANS_COND_OVF_UDF_CLR: This configuration value applies to non-triangular wave counting mode. + * When counting overflow or underflow or counting register was cleared, + * transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). + * @arg TMRA_BUF_TRANS_COND_PEAK: In triangle wave count mode, when count reached peak, + * transfer CMMARm(m=2,4,6,8,...) to CMMARn(n=1,3,5,7,...). + * @arg TMRA_BUF_TRANS_COND_VALLEY: In triangle wave count mode, when count reached valley, + * transfer CMMARm(m=2,4,6,8,...) to CMMARn(n=1,3,5,7,...). + * @arg TMRA_BUF_TRANS_COND_PEAK_VALLEY: In triangle wave count mode, when count reached peak or valley, + * transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). + * @retval None + * @note The specified condition is only valid when TMRA_BCONR.BEN is set. + */ +void TMRA_SetCompareBufCond(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond) +{ + uint32_t u32BCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CMPVAL_BUF_CH(u32Ch)); + DDL_ASSERT(IS_TMRA_BUF_TRANS_COND(u16Cond)); + + u32BCONRAddr = (uint32_t)&TMRAx->BCONR1 + u32Ch * 4U; + MODIFY_REG16(RW_MEM16(u32BCONRAddr), TMRA_BUF_TRANS_COND_PEAK_VALLEY, u16Cond); +} + +/** + * @brief Enable or disable compare value buffer. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be one of the odd channels of @ref TMRA_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note DO NOT set both TMRA_BCONR.BSEN and TMRA_BCONR.BEN to '1'. + */ +void TMRA_CompareBufCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState) +{ + uint32_t u32BCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CMPVAL_BUF_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32BCONRAddr = (uint32_t)&TMRAx->BCONR1 + u32Ch * 4U; + + WRITE_REG32(PERIPH_BIT_BAND(u32BCONRAddr, TMRA_BCONR_BEN_POS), enNewState); +} + +/** + * @brief Get the status of the specified flag. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Flag The status flags of TMRA. + * This parameter can be a value of @ref TMRA_Status_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t TMRA_GetStatus(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag) +{ + uint8_t u8BCSTR; + uint16_t u16STFLR; + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_TMRA_UNIT_FLAG(TMRAx, u32Flag)); + + u8BCSTR = (uint8_t)(u32Flag & TMRA_BCSTRH_FLAG_MASK); + u16STFLR = (uint16_t)(u32Flag >> 16U); + u8BCSTR = READ_REG8_BIT(TMRAx->BCSTRH, u8BCSTR); + u16STFLR = READ_REG16_BIT(TMRAx->STFLR, u16STFLR); + + if ((u8BCSTR != 0U) || (u16STFLR != 0U)) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of the specified flags. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Flag The status flags of TMRA. + * This parameter can be values of @ref TMRA_Status_Flag + * @retval None + */ +void TMRA_ClearStatus(CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_TMRA_UNIT_FLAG(TMRAx, u32Flag)); + + CLR_REG8_BIT(TMRAx->BCSTRH, u32Flag & TMRA_BCSTRH_FLAG_MASK); + CLR_REG16_BIT(TMRAx->STFLR, u32Flag >> 16U); +} + +/** + * @brief Enable of disable the specified interrupts of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32IntType The interrupt type of TMRA. + * This parameter can be values of @ref TMRA_Interrupt_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_IntCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint32_t u32BCSTRH; + uint32_t u32ICONR; + + DDL_ASSERT(IS_TMRA_UNIT_INT(TMRAx, u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32BCSTRH = u32IntType & TMRA_BCSTRH_INT_MASK; + u32ICONR = u32IntType >> 16U; + if (enNewState == ENABLE) { + SET_REG8_BIT(TMRAx->BCSTRH, u32BCSTRH); + SET_REG16_BIT(TMRAx->ICONR, u32ICONR); + } else { + CLR_REG8_BIT(TMRAx->BCSTRH, u32BCSTRH); + CLR_REG16_BIT(TMRAx->ICONR, u32ICONR); + } +} + +/** + * @brief Enable of disable the specified event of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32EventType The event type of TMRA. + * This parameter can be values of @ref TMRA_Event_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_EventCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32EventType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_CH_EVT(TMRAx, u32EventType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->ECONR, u32EventType); + } else { + CLR_REG16_BIT(TMRAx->ECONR, u32EventType); + } +} + +/** + * @brief Start the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval None + */ +void TMRA_Start(CM_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + SET_REG8_BIT(TMRAx->BCSTRL, TMRA_BCSTRL_START); +} + +/** + * @brief Stop the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval None + */ +void TMRA_Stop(CM_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + CLR_REG8_BIT(TMRAx->BCSTRL, TMRA_BCSTRL_START); +} +/** + * @} + */ + +#endif /* LL_TMRA_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_trng.c b/mcu/lib/src/hc32_ll_trng.c new file mode 100644 index 0000000..4be0ee7 --- /dev/null +++ b/mcu/lib/src/hc32_ll_trng.c @@ -0,0 +1,262 @@ +/** + ******************************************************************************* + * @file hc32_ll_trng.c + * @brief This file provides firmware functions to manage the True Random + * Number Generator(TRNG). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-10-31 CDT API fixed: TRNG_Init() + 2023-06-30 CDT API fixed: rewrite TRNG_GenerateRandom() to Support get multiple random data + API optimized for better random numbers: TRNG_GenerateRandom(), TRNG_GetRandom() + Add TRNG_Cmd,TRNG_DeInit functions and optimize TRNG_Start function + 2023-09-30 CDT Optimize the processing of discarded data and enable TRNG in TRNG_Init() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_trng.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TRNG TRNG + * @brief TRNG Driver Library + * @{ + */ + +#if (LL_TRNG_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TRNG_Local_Macros TRNG Local Macros + * @{ + */ +#define TRNG_TIMEOUT (20000UL) + +/** + * @defgroup TRNG_Check_Parameters_Validity TRNG Check Parameters Validity + * @{ + */ +#define IS_TRNG_SHIFT_CNT(x) \ +( ((x) == TRNG_SHIFT_CNT32) || \ + ((x) == TRNG_SHIFT_CNT64) || \ + ((x) == TRNG_SHIFT_CNT128) || \ + ((x) == TRNG_SHIFT_CNT256)) + +#define IS_RNG_RELOAD_INIT_VAL_EN(x) \ +( ((x) == TRNG_RELOAD_INIT_VAL_ENABLE) || \ + ((x) == TRNG_RELOAD_INIT_VAL_DISABLE)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup TRNG_Global_Functions TRNG Global Functions + * @{ + */ + +/** + * @brief De-initializes TRNG. + * @param None + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: Works timeout. + */ +int32_t TRNG_DeInit(void) +{ + int32_t i32Ret = LL_ERR_TIMEOUT; + __IO uint32_t u32TimeCount = TRNG_TIMEOUT; + + /* Wait generating done */ + while (u32TimeCount-- != 0UL) { + if (READ_REG32(bCM_TRNG->CR_b.RUN) == 0U) { + i32Ret = LL_OK; + break; + } + } + if (i32Ret == LL_OK) { + WRITE_REG32(CM_TRNG->CR, 0UL); + WRITE_REG32(CM_TRNG->MR, 0x00000012UL); + } + + return i32Ret; +} + +/** + * @brief Initializes TRNG. + * @param [in] u32ShiftCount TRNG shift control. This parameter can be a value of @ref TRNG_Shift_Ctrl + * @arg TRNG_SHIFT_CNT32: Shift 32 times when capturing random noise. + * @arg TRNG_SHIFT_CNT64: Shift 64 times when capturing random noise. + * @arg TRNG_SHIFT_CNT128: Shift 128 times when capturing random noise. + * @arg TRNG_SHIFT_CNT256: Shift 256 times when capturing random noise. + * @param [in] u32ReloadInitValueEn Enable or disable load new initial value. + * This parameter can be a value of @ref TRNG_Reload_Init_Value + * @arg TRNG_RELOAD_INIT_VAL_ENABLE: Enable load new initial value. + * @arg TRNG_RELOAD_INIT_VAL_DISABLE: Disable load new initial value. + * @retval None + */ +void TRNG_Init(uint32_t u32ShiftCount, uint32_t u32ReloadInitValueEn) +{ + uint32_t au32Random[20U]; + + DDL_ASSERT(IS_TRNG_SHIFT_CNT(u32ShiftCount)); + DDL_ASSERT(IS_RNG_RELOAD_INIT_VAL_EN(u32ReloadInitValueEn)); + WRITE_REG32(CM_TRNG->MR, u32ShiftCount | u32ReloadInitValueEn); + /* Enable TRNG */ + SET_REG32_BIT(CM_TRNG->CR, TRNG_CR_EN); + /* Discard the first 10 generated data (64bit), 20 for 32bit variable storage */ + (void)TRNG_GenerateRandom(au32Random, 20U); +} + +/** + * @brief Start TRNG and get random number. + * @param [out] pu32Random The destination buffer to store the random number. + * @param [in] u32RandomLen The size(in word) of the destination buffer. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: Works timeout. + * - LL_ERR_INVD_PARAM: pu32Random == NULL or u8RandomLen == 0 + */ +int32_t TRNG_GenerateRandom(uint32_t *pu32Random, uint32_t u32RandomLen) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + __IO uint32_t u32TimeCount = TRNG_TIMEOUT; + uint32_t u32Count = 0U; + + if ((pu32Random != NULL) && (u32RandomLen > 0U)) { + while (u32RandomLen != u32Count) { + /* Start TRNG */ + WRITE_REG32(bCM_TRNG->CR_b.RUN, 1U); + /* Wait generating done. */ + i32Ret = LL_ERR_TIMEOUT; + while (u32TimeCount-- != 0UL) { + if (READ_REG32(bCM_TRNG->CR_b.RUN) == 0U) { + i32Ret = LL_OK; + break; + } + } + + if (i32Ret == LL_OK) { + /* Get the random number. */ + /* XOR with 0x55555555 for better random number */ + pu32Random[u32Count++] = READ_REG32(CM_TRNG->DR0) ^ 0x55555555UL; + if (u32Count < u32RandomLen) { + pu32Random[u32Count++] = READ_REG32(CM_TRNG->DR1) ^ 0x55555555UL; + } + } + } + } + + return i32Ret; +} + +/** + * @brief Start TRNG + * @param None + * @retval None + */ +void TRNG_Start(void) +{ + WRITE_REG32(bCM_TRNG->CR_b.RUN, 1U); +} + +/** + * @brief TRNG function enable or disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TRNG_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_TRNG->CR, TRNG_CR_EN); + } else { + CLR_REG32_BIT(CM_TRNG->CR, TRNG_CR_EN); + } +} + +/** + * @brief Get random number. + * @param [out] pu32Random The destination buffer to store the random number. + * @param [in] u8RandomLen The size(in word) of the destination buffer.(MAX = 2U) + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pu32Random == NULL or u8RandomLen == 0 + */ +int32_t TRNG_GetRandom(uint32_t *pu32Random, uint8_t u8RandomLen) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pu32Random != NULL) && (u8RandomLen > 0U)) { + /* Get the random number. */ + /* XOR with 0x55555555 for better random number */ + pu32Random[0U] = READ_REG32(CM_TRNG->DR0) ^ 0x55555555UL; + if (u8RandomLen > 1U) { + pu32Random[1U] = READ_REG32(CM_TRNG->DR1) ^ 0x55555555UL; + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_TRNG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_usart.c b/mcu/lib/src/hc32_ll_usart.c new file mode 100644 index 0000000..52d0675 --- /dev/null +++ b/mcu/lib/src/hc32_ll_usart.c @@ -0,0 +1,1661 @@ +/** + ******************************************************************************* + * @file hc32_ll_usart.c + * @brief This file provides firmware functions to manage the USART(Universal + * Synchronous/Asynchronous Receiver Transmitter). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Optimize UART DIV_Fraction calculation time + 2023-01-15 CDT Fix bug: expressions may cause overflow when calculate UART DIV_Fraction + 2023-06-30 CDT Add function note: USART_FuncCmd + Modify typo + Round off baudrate fraction division + Split register USART_DR to USART_RDR and USART_TDR + Modify USART_SetTransType parameter: u32Type -> u16Type + Delete function: USART_GetUsartClockDiv + Fix MISRAC2012 warning: USART_GetUsartClockFreq + Code Refine + Modify return type of function USART_DeInit() + 2023-09-30 CDT Modify USART_SmartCard_Init() for stc_usart_smartcard_init_t has modified(u32StopBit has removed) + Fix bug: did not enable MP while USART_MultiProcessor_Init() + API refined: USART_SetBaudrate() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_usart.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_USART USART + * @brief USART Driver Library + * @{ + */ + +#if (LL_USART_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/** + * @defgroup USART_Local_Types USART Local Types + * @{ + */ + +/** + * @brief usart BRR division calculate structure definition + */ +typedef struct { + uint32_t u32UsartClock; /*!< USART clock. */ + uint32_t u32Baudrate; /*!< USART baudrate. */ + uint32_t u32Integer; /*!< Pointer to BRR integer division value. */ + uint32_t u32Fraction; /*!< Pointer to BRR fraction division value. */ + float32_t f32Error; /*!< E(%) baudrate error rate. */ +} stc_usart_brr_t; + +/** + * @} + */ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup USART_Local_Macros USART Local Macros + * @{ + */ + +/** + * @defgroup USART_Check_Parameters_Validity USART Check Parameters Validity + * @{ + */ + +/** + * @defgroup USART_Check_Parameters_Validity_Unit USART Check Parameters Validity Unit + * @{ + */ +#define IS_USART_UNIT(x) \ +( ((x) == CM_USART1) || \ + ((x) == CM_USART2) || \ + ((x) == CM_USART3) || \ + ((x) == CM_USART4)) +#define IS_USART_SMARTCARD_UNIT(x) (IS_USART_UNIT(x)) +#define IS_USART_TIMEOUT_UNIT(x) (IS_USART_UNIT(x)) + +/** + * @} + */ + +#define IS_USART_FUNC(x) \ +( ((x) != 0UL) && \ + (((x) | USART_FUNC_ALL) == USART_FUNC_ALL)) + +#define IS_USART_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | USART_FLAG_ALL) == USART_FLAG_ALL)) + +#define IS_USART_TRANS_TYPE(x) \ +( ((x) == USART_TRANS_ID) || \ + ((x) == USART_TRANS_DATA)) + +#define IS_USART_PARITY(x) \ +( ((x) == USART_PARITY_ODD) || \ + ((x) == USART_PARITY_EVEN) || \ + ((x) == USART_PARITY_NONE)) + +#define IS_USART_DATA_WIDTH(x) \ +( ((x) == USART_DATA_WIDTH_8BIT) || \ + ((x) == USART_DATA_WIDTH_9BIT)) + +#define IS_USART_STOPBIT(x) \ +( ((x) == USART_STOPBIT_1BIT) || \ + ((x) == USART_STOPBIT_2BIT)) + +#define IS_USART_FIRST_BIT(x) \ +( ((x) == USART_FIRST_BIT_MSB) || \ + ((x) == USART_FIRST_BIT_LSB)) + +#define IS_USART_OVER_SAMPLE_BIT(x) \ +( ((x) == USART_OVER_SAMPLE_8BIT) || \ + ((x) == USART_OVER_SAMPLE_16BIT)) + +#define IS_USART_START_BIT_POLARITY(x) \ +( ((x) == USART_START_BIT_LOW) || \ + ((x) == USART_START_BIT_FALLING)) + +#define IS_USART_CLK_SRC(x) \ +( ((x) == USART_CLK_SRC_EXTCLK) || \ + ((x) == USART_CLK_SRC_INTERNCLK)) + +#define IS_USART_CK_OUTPUT(x) \ +( ((x) == USART_CK_OUTPUT_ENABLE) || \ + ((x) == USART_CK_OUTPUT_DISABLE)) + +#define IS_USART_CLK_DIV(x) ((x) <= USART_CLK_DIV_MAX) + +#define IS_USART_DATA(x) ((x) <= 0x01FFUL) + +/** + * @defgroup USART_Check_Parameters_Validity_Hardware_Flow_Control USART Check Parameters Validity Hardware Flow Control + * @{ + */ +#define IS_USART_HW_FLOWCTRL(x) \ +( ((x) == USART_HW_FLOWCTRL_CTS) || \ + ((x) == USART_HW_FLOWCTRL_RTS)) +/** + * @} + */ + +/** + * @defgroup USART_Check_Parameters_Validity_Smartcard_Clock USART Check Parameters Validity Smartcard Clock + * @{ + */ +#define IS_USART_SMARTCARD_ETU_CLK(x) \ +( ((x) == USART_SC_ETU_CLK32) || \ + ((x) == USART_SC_ETU_CLK64) || \ + ((x) == USART_SC_ETU_CLK128) || \ + ((x) == USART_SC_ETU_CLK256) || \ + ((x) == USART_SC_ETU_CLK372)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup USART_Flag_Error_Mask USART Flag Error Mask + * @{ + */ +#define USART_FLAG_ERR_MASK (USART_FLAG_OVERRUN | \ + USART_FLAG_FRAME_ERR | \ + USART_FLAG_PARITY_ERR) +/** + * @} + */ + +/** + * @defgroup USART_Registers_Reset_Value_definition USART Registers Reset Value + * @{ + */ +#define USART_CR1_RST_VALUE (0x80000000UL) + +#define USART_CR2_RST_VALUE (0UL) +/** + * @} + */ + +/** + * @defgroup USART_BRR_Division_Max USART BRR Register Division Max + * @{ + */ +#define USART_BRR_DIV_INTEGER_MAX (0xFFUL) +#define USART_BRR_DIV_FRACTION_MAX (0x7FUL) +/** + * @} + */ + +/** + * @defgroup USART_Clock_Division_Max USART Clock Division Max + * @{ + */ +#define USART_CLK_DIV_MAX (USART_CLK_DIV64) +/** + * @} + */ + +/** + * @defgroup USART_Default_Baudrate USART Default Baudrate + * @{ + */ +#define USART_DEFAULT_BAUDRATE (9600UL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup USART_Local_Functions USART Local Functions + * @{ + */ +/** + * @brief Try to wait the expected status of specified flags + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Flag USART flag + * This parameter can be a value of @ref USART_Flag + * @param [in] enStatus Expected status + * This parameter can be one of the following values: + * @arg SET: Wait flag set + * @arg RESET: Wait flag reset + * @param [in] u32Timeout Maximum count(Max value @ref USART_Max_Timeout) of trying to get status + * @retval int32_t: + * - LL_OK: Complete wait the expected status of the specified flags. + * - LL_ERR_TIMEOUT: Wait timeout. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT. + */ +static int32_t USART_WaitStatus(const CM_USART_TypeDef *USARTx, + uint32_t u32Flag, + en_flag_status_t enStatus, + uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32To = 0UL; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_FLAG(u32Flag)); + + while (USART_GetStatus(USARTx, u32Flag) != enStatus) { + /* Block checking flag if timeout value is USART_TIMEOUT_MAX */ + if ((u32To > u32Timeout) && (u32Timeout < USART_MAX_TIMEOUT)) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + + u32To++; + } + + return i32Ret; +} + +/** + * @brief Calculate baudrate division for UART mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcUartBrr Pointer to a stc_usart_brr_t structure. + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR: Set unsuccessfully. + */ +static int32_t UART_CalculateBrr(const CM_USART_TypeDef *USARTx, stc_usart_brr_t *pstcUartBrr) +{ + uint32_t B; + uint32_t C; + uint32_t OVER8; + uint64_t u64Temp; + uint64_t u64Temp0; + uint64_t u64Dividend; + uint32_t DIV_Integer; + uint32_t DIV_IntegerMod; + uint32_t DIV_Fraction; + float32_t f32CalcError; + uint32_t u32FractionFlag = 1UL; + int32_t i32Ret = LL_ERR; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + C = pstcUartBrr->u32UsartClock; + B = pstcUartBrr->u32Baudrate; + if ((C > 0UL) && (B > 0UL)) { + OVER8 = READ_REG32_BIT(USARTx->CR1, USART_CR1_OVER8) >> USART_CR1_OVER8_POS; + + /* UART mode baudrate integer calculation formula: */ + /* B = C / (8 * (2 - OVER8) * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 8 * (2 - OVER8))) - 1 */ + DIV_Integer = (C / (B * 8UL * (2UL - OVER8))) - 1U; + if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) { + pstcUartBrr->u32Integer = DIV_Integer; + DIV_IntegerMod = C % (B * 8UL * (2UL - OVER8)); + if (0UL == DIV_IntegerMod) { + /* Get accurate baudrate without fraction */ + pstcUartBrr->f32Error = (float32_t)0.0F; + i32Ret = LL_OK; + } else { + /* UART mode baudrate fraction calculation formula: */ + /* B = C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = (256 * (8 * (2 - OVER8) * (DIV_Integer + 1) * B) / C) - 128 */ + /* u64Temp = (8 * (2 - OVER8) * (DIV_Integer + 1) * B) */ + u64Temp0 = (uint64_t)((uint64_t)8UL * ((uint64_t)2UL - (uint64_t)OVER8) * \ + ((uint64_t)DIV_Integer + (uint64_t)1UL) * (uint64_t)B); + + /* u64Temp = u64Temp0 *256 + C/2 */ + u64Temp0 = (u64Temp0 << 8UL); + u64Temp = u64Temp0 + ((uint64_t)C >> 1); /* +(C >> 1) for rounding off */ + if (u64Temp > (uint64_t)(UINT32_MAX)) { + DIV_Fraction = (uint32_t)(u64Temp / C) - 128UL; + } else { + DIV_Fraction = ((uint32_t)u64Temp) / C - 128UL; + } + if (DIV_Fraction <= USART_BRR_DIV_FRACTION_MAX) { + pstcUartBrr->u32Fraction = DIV_Fraction; + /* E(%) = C * (128 + DIV_Fraction) / (256 * (8 * (2 - OVER8) * (DIV_Integer + 1) * B)) - 1 */ + u64Temp = u64Temp0; + u64Dividend = (uint64_t)C * ((uint64_t)128UL + (uint64_t)DIV_Fraction); + f32CalcError = (float32_t)((float64_t)(u64Dividend) / (float64_t)(u64Temp)) - 1.0F; + pstcUartBrr->f32Error = f32CalcError; + i32Ret = LL_OK; + } else { + u32FractionFlag = 0UL; + } + } + } + if (0UL == u32FractionFlag) { + /* Integer rounding off */ + DIV_Integer = ((((C * 10UL) / (B * 8UL * (2UL - OVER8))) + 5UL) / 10UL) - 1UL; /* +5UL for rounding off */ + if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) { + pstcUartBrr->u32Integer = DIV_Integer; + /* E(%) = C / (8 * (2 - OVER8) * (DIV_Integer + 1) * B) - 1 */ + /* u64Temp = (8 * (2 - OVER8) * (DIV_Integer + 1) * B) */ + u64Temp = (uint64_t)((uint64_t)8UL * ((uint64_t)2UL - (uint64_t)OVER8) * ((uint64_t)DIV_Integer + \ + (uint64_t)1UL) * (uint64_t)B); + f32CalcError = (float32_t)((float64_t)C / (float64_t)u64Temp) - 1.0F; + pstcUartBrr->f32Error = f32CalcError; + i32Ret = LL_OK; + } + } + } + return i32Ret; +} + +/** + * @brief Calculate baudrate division for UART mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcClockSyncBrr Pointer to a stc_usart_brr_t structure. + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR: Set unsuccessfully. + */ +static int32_t ClockSync_CalculateBrr(const CM_USART_TypeDef *USARTx, stc_usart_brr_t *pstcClockSyncBrr) +{ + uint32_t B; + uint32_t C; + uint64_t u64Temp; + uint64_t u64Dividend; + uint32_t DIV_Integer; + uint32_t DIV_IntegerMod; + uint32_t DIV_Fraction; + float32_t f32CalcError; + uint32_t u32FractionFlag = 1UL; + int32_t i32Ret = LL_ERR; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + C = pstcClockSyncBrr->u32UsartClock; + B = pstcClockSyncBrr->u32Baudrate; + if ((C > 0UL) && (B > 0UL)) { + /* Clock sync mode baudrate integer calculation formula: */ + /* B = C / (4 * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 4)) - 1 */ + DIV_Integer = (C / (B * 4UL)) - 1UL; + if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) { + pstcClockSyncBrr->u32Integer = DIV_Integer; + DIV_IntegerMod = C % (B * 4UL); + if (0UL == DIV_IntegerMod) { + /* Get accurate baudrate without fraction */ + pstcClockSyncBrr->f32Error = (float32_t)0.0F; + i32Ret = LL_OK; + } else { + /* Clock sync mode baudrate fraction calculation formula: */ + /* B = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = 256 * (4 * (DIV_Integer + 1) * B) / C - 128 */ + + /* u64Temp = (4 * (DIV_Integer + 1) * B) */ + u64Temp = (uint64_t)((uint64_t)4U * ((uint64_t)DIV_Integer + (uint64_t)1UL) * (uint64_t)B); + DIV_Fraction = (uint32_t)((256UL * u64Temp + ((uint64_t)C >> 1)) / C - 128UL); /* +(C >> 1) for rounding off */ + if (DIV_Fraction <= USART_BRR_DIV_FRACTION_MAX) { + pstcClockSyncBrr->u32Fraction = DIV_Fraction; + /* E(%) = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * B * 256) - 1 */ + u64Temp *= (uint64_t)256UL; + u64Dividend = (uint64_t)C * ((uint64_t)128UL + (uint64_t)DIV_Fraction); + f32CalcError = (float32_t)((float64_t)(u64Dividend) / (float64_t)(u64Temp)) - 1.0F; + pstcClockSyncBrr->f32Error = f32CalcError; + i32Ret = LL_OK; + } else { + u32FractionFlag = 0UL; + } + } + } + if (0UL == u32FractionFlag) { + /* Integer rounding off */ + DIV_Integer = ((((C * 10UL) / (B * 4UL)) + 5UL) / 10UL) - 1UL; /* +5UL for rounding off */ + if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) { + pstcClockSyncBrr->u32Integer = DIV_Integer; + /* E(%) = C / (4 * (DIV_Integer + 1) * B) - 1 */ + /* u64Temp = 4 * (DIV_Integer + 1) * B */ + u64Temp = (uint64_t)((uint64_t)4U * ((uint64_t)DIV_Integer + (uint64_t)1UL) * (uint64_t)B); + f32CalcError = (float32_t)((float64_t)C / (float64_t)u64Temp) - 1.0F; + pstcClockSyncBrr->f32Error = f32CalcError; + i32Ret = LL_OK; + } + } + } + return i32Ret; +} + +/** + * @brief Calculate baudrate division for UART mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcSmartCardBrr Pointer to a stc_usart_brr_t structure. + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR: Set unsuccessfully. + */ +static int32_t SmartCard_CalculateBrr(const CM_USART_TypeDef *USARTx, stc_usart_brr_t *pstcSmartCardBrr) +{ + uint32_t B; + uint32_t C; + uint32_t BCN; + uint64_t u64Temp; + uint64_t u64Dividend; + uint32_t DIV_Integer; + uint32_t DIV_IntegerMod; + uint32_t DIV_Fraction; + float32_t f32CalcError; + const uint16_t au16EtuClkCnts[] = {32U, 64U, 93U, 128U, 186U, 256U, 372U, 512U}; + int32_t i32Ret = LL_ERR; + + DDL_ASSERT(IS_USART_SMARTCARD_UNIT(USARTx)); + + C = pstcSmartCardBrr->u32UsartClock; + B = pstcSmartCardBrr->u32Baudrate; + if ((C > 0UL) && (B > 0UL)) { + BCN = READ_REG32_BIT(USARTx->CR3, USART_CR3_BCN); + DDL_ASSERT(IS_USART_SMARTCARD_ETU_CLK(BCN)); + BCN = au16EtuClkCnts[BCN >> USART_CR3_BCN_POS]; + /* Smartcard mode baudrate integer calculation formula: */ + /* B = C / (2 * BCN * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 2 * BCN)) - 1 */ + DIV_Integer = (C / (B * BCN * 2UL)) - 1UL; + if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) { + pstcSmartCardBrr->u32Integer = DIV_Integer; + DIV_IntegerMod = C % (B * BCN * 2UL); + if (0UL == DIV_IntegerMod) { + /* Get accurate baudrate without fraction */ + pstcSmartCardBrr->f32Error = (float32_t)0.0F; + i32Ret = LL_OK; + } else { + /* Smartcard mode baudrate fraction calculation formula: */ + /* B = C * (128 + DIV_Fraction) / ((2 * BCN) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = (256 * (2 * BCN * (DIV_Integer + 1) * B) / C) - 128 */ + + /* u64Temp = (2 * BCN * (DIV_Integer + 1) * B) */ + u64Temp = (uint64_t)((uint64_t)2UL * BCN * ((uint64_t)DIV_Integer + (uint64_t)1UL) * B); + DIV_Fraction = (uint32_t)((256UL * u64Temp + ((uint64_t)C >> 1)) / C - 128UL); /* +(C >> 1) for rounding off */ + if (DIV_Fraction <= USART_BRR_DIV_FRACTION_MAX) { + pstcSmartCardBrr->u32Fraction = DIV_Fraction; + /* E(%) = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * B * 256) - 1 */ + u64Temp *= (uint64_t)256UL; + u64Dividend = (uint64_t)C * ((uint64_t)128UL + (uint64_t)DIV_Fraction); + f32CalcError = (float32_t)((float64_t)u64Dividend / (float64_t)(u64Temp)) - 1.0F; + pstcSmartCardBrr->f32Error = f32CalcError; + i32Ret = LL_OK; + } + } + } + if (LL_ERR == i32Ret) { + /* Integer rounding off */ + DIV_Integer = (((C * 10UL) / (B * BCN * 2UL) + 5UL) / 10UL) - 1UL; /* +5UL for rounding off */ + if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) { + pstcSmartCardBrr->u32Integer = DIV_Integer; + /* E(%) = C / (2 * BCN * (DIV_Integer + 1) * B) - 1 */ + /* u64Temp = 4 * (DIV_Integer + 1) * B */ + u64Temp = (uint64_t)((uint64_t)2UL * BCN * ((uint64_t)DIV_Integer + (uint64_t)1UL) * B); + f32CalcError = (float32_t)((float64_t)C / (float64_t)u64Temp) - 1.0F; + pstcSmartCardBrr->f32Error = f32CalcError; + i32Ret = LL_OK; + } + } + } + return i32Ret; +} + +/** + * @brief Get bus(which USART mounts on) clock frequency value. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval USART clock frequency value + */ +static uint32_t USART_GetBusClockFreq(const CM_USART_TypeDef *USARTx) +{ + uint32_t u32BusClock; + + (void)USARTx; + + u32BusClock = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS); + + return u32BusClock; +} + +/** + * @brief Get USART clock frequency value. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval USART clock frequency value + */ +static uint32_t USART_GetUsartClockFreq(const CM_USART_TypeDef *USARTx) +{ + uint32_t u32BusClock; + uint32_t u32UsartClockDiv; + uint32_t u32UsartClock; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + u32BusClock = USART_GetBusClockFreq(USARTx); + + u32UsartClockDiv = (1UL << (READ_REG32_BIT(USARTx->PR, USART_PR_PSC) * 2UL)); + + u32UsartClock = u32BusClock / u32UsartClockDiv; + return u32UsartClock; +} + +/** + * @} + */ + +/** + * @defgroup USART_Global_Functions USART Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_usart_clocksync_init_t to default values. + * @param [out] pstcClockSyncInit Pointer to a @ref stc_usart_clocksync_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcClockSyncInit value is NULL. + */ +int32_t USART_ClockSync_StructInit(stc_usart_clocksync_init_t *pstcClockSyncInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcClockSyncInit) { + pstcClockSyncInit->u32ClockSrc = USART_CLK_SRC_INTERNCLK; + pstcClockSyncInit->u32ClockDiv = USART_CLK_DIV1; + pstcClockSyncInit->u32Baudrate = USART_DEFAULT_BAUDRATE; + pstcClockSyncInit->u32FirstBit = USART_FIRST_BIT_LSB; + pstcClockSyncInit->u32HWFlowControl = USART_HW_FLOWCTRL_RTS; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize clock synchronization function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcClockSyncInit Pointer to a @ref stc_usart_clocksync_init_t structure. + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcClockSyncInit value is NULL or baudrate set unsuccessfully. + */ +int32_t USART_ClockSync_Init(CM_USART_TypeDef *USARTx, + const stc_usart_clocksync_init_t *pstcClockSyncInit, float32_t *pf32Error) +{ + uint32_t u32CR1Value; + uint32_t u32CR2Value; + uint32_t u32CR3Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcClockSyncInit) { + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_SRC(pstcClockSyncInit->u32ClockSrc)); + DDL_ASSERT(IS_USART_FIRST_BIT(pstcClockSyncInit->u32FirstBit)); + DDL_ASSERT(IS_USART_HW_FLOWCTRL(pstcClockSyncInit->u32HWFlowControl)); + + u32CR1Value = (pstcClockSyncInit->u32FirstBit | USART_CR1_MS | USART_CR1_SBS); + u32CR2Value = (pstcClockSyncInit->u32ClockSrc | USART_CR2_RST_VALUE); + if (USART_CLK_SRC_INTERNCLK == pstcClockSyncInit->u32ClockSrc) { + u32CR2Value |= USART_CK_OUTPUT_ENABLE; + } + u32CR3Value = (pstcClockSyncInit->u32HWFlowControl == USART_HW_FLOWCTRL_CTS) ? USART_HW_FLOWCTRL_CTS : 0UL; + + /* Set control register: CR1/CR2/CR3 */ + WRITE_REG32(USARTx->CR1, u32CR1Value); + WRITE_REG32(USARTx->CR2, u32CR2Value); + WRITE_REG32(USARTx->CR3, u32CR3Value); + + if (USART_CLK_SRC_INTERNCLK == pstcClockSyncInit->u32ClockSrc) { + DDL_ASSERT(IS_USART_CLK_DIV(pstcClockSyncInit->u32ClockDiv)); + + /* Set prescaler register register: PR */ + WRITE_REG32(USARTx->PR, pstcClockSyncInit->u32ClockDiv); + + /* Set baudrate */ + i32Ret = USART_SetBaudrate(USARTx, pstcClockSyncInit->u32Baudrate, pf32Error); + } else { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_usart_multiprocessor_init_t to default values. + * @param [out] pstcMultiProcessorInit Pointer to a @ref stc_usart_multiprocessor_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcMultiProcessorInit value is NULL. + */ +int32_t USART_MultiProcessor_StructInit(stc_usart_multiprocessor_init_t *pstcMultiProcessorInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcMultiProcessorInit) { + pstcMultiProcessorInit->u32ClockSrc = USART_CLK_SRC_INTERNCLK; + pstcMultiProcessorInit->u32ClockDiv = USART_CLK_DIV1; + pstcMultiProcessorInit->u32CKOutput = USART_CK_OUTPUT_DISABLE; + pstcMultiProcessorInit->u32Baudrate = USART_DEFAULT_BAUDRATE; + pstcMultiProcessorInit->u32DataWidth = USART_DATA_WIDTH_8BIT; + pstcMultiProcessorInit->u32StopBit = USART_STOPBIT_1BIT; + pstcMultiProcessorInit->u32OverSampleBit = USART_OVER_SAMPLE_16BIT; + pstcMultiProcessorInit->u32FirstBit = USART_FIRST_BIT_LSB; + pstcMultiProcessorInit->u32StartBitPolarity = USART_START_BIT_FALLING; + pstcMultiProcessorInit->u32HWFlowControl = USART_HW_FLOWCTRL_RTS; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize UART multiple processor function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcMultiProcessorInit Pointer to a @ref stc_usart_multiprocessor_init_t structure. + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcMxProcessorInit value is NULL or baudrate set unsuccessfully. + */ +int32_t USART_MultiProcessor_Init(CM_USART_TypeDef *USARTx, + const stc_usart_multiprocessor_init_t *pstcMultiProcessorInit, float32_t *pf32Error) +{ + uint32_t u32CR1Value; + uint32_t u32CR2Value; + uint32_t u32CR3Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcMultiProcessorInit) { + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_SRC(pstcMultiProcessorInit->u32ClockSrc)); + DDL_ASSERT(IS_USART_CK_OUTPUT(pstcMultiProcessorInit->u32CKOutput)); + DDL_ASSERT(IS_USART_DATA_WIDTH(pstcMultiProcessorInit->u32DataWidth)); + DDL_ASSERT(IS_USART_STOPBIT(pstcMultiProcessorInit->u32StopBit)); + DDL_ASSERT(IS_USART_OVER_SAMPLE_BIT(pstcMultiProcessorInit->u32OverSampleBit)); + DDL_ASSERT(IS_USART_FIRST_BIT(pstcMultiProcessorInit->u32FirstBit)); + DDL_ASSERT(IS_USART_START_BIT_POLARITY(pstcMultiProcessorInit->u32StartBitPolarity)); + DDL_ASSERT(IS_USART_HW_FLOWCTRL(pstcMultiProcessorInit->u32HWFlowControl)); + + u32CR1Value = (pstcMultiProcessorInit->u32DataWidth | pstcMultiProcessorInit->u32OverSampleBit | \ + pstcMultiProcessorInit->u32FirstBit | pstcMultiProcessorInit->u32StartBitPolarity); + u32CR2Value = (USART_CR2_RST_VALUE | USART_CR2_MPE | pstcMultiProcessorInit->u32ClockSrc | \ + pstcMultiProcessorInit->u32CKOutput | pstcMultiProcessorInit->u32StopBit); + u32CR3Value = (pstcMultiProcessorInit->u32HWFlowControl == USART_HW_FLOWCTRL_CTS) ? USART_HW_FLOWCTRL_CTS : 0UL; + + /* Set control register: CR1/CR2/CR3 */ + WRITE_REG32(USARTx->CR1, u32CR1Value); + WRITE_REG32(USARTx->CR2, u32CR2Value); + WRITE_REG32(USARTx->CR3, u32CR3Value); + + if (USART_CLK_SRC_INTERNCLK == pstcMultiProcessorInit->u32ClockSrc) { + DDL_ASSERT(IS_USART_CLK_DIV(pstcMultiProcessorInit->u32ClockDiv)); + + /* Set prescaler register register: PR */ + WRITE_REG32(USARTx->PR, pstcMultiProcessorInit->u32ClockDiv); + + /* Set baudrate */ + i32Ret = USART_SetBaudrate(USARTx, pstcMultiProcessorInit->u32Baudrate, pf32Error); + } else { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_usart_uart_init_t to default values. + * @param [out] pstcUartInit Pointer to a @ref stc_usart_uart_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcUartInit value is NULL. + */ +int32_t USART_UART_StructInit(stc_usart_uart_init_t *pstcUartInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcUartInit) { + pstcUartInit->u32ClockSrc = USART_CLK_SRC_INTERNCLK; + pstcUartInit->u32ClockDiv = USART_CLK_DIV1; + pstcUartInit->u32CKOutput = USART_CK_OUTPUT_DISABLE; + pstcUartInit->u32Baudrate = USART_DEFAULT_BAUDRATE; + pstcUartInit->u32DataWidth = USART_DATA_WIDTH_8BIT; + pstcUartInit->u32StopBit = USART_STOPBIT_1BIT; + pstcUartInit->u32Parity = USART_PARITY_NONE; + pstcUartInit->u32OverSampleBit = USART_OVER_SAMPLE_16BIT; + pstcUartInit->u32FirstBit = USART_FIRST_BIT_LSB; + pstcUartInit->u32StartBitPolarity = USART_START_BIT_FALLING; + pstcUartInit->u32HWFlowControl = USART_HW_FLOWCTRL_RTS; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize UART function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcUartInit Pointer to a @ref stc_usart_uart_init_t structure. + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcUartInit value is NULL or baudrate set unsuccessfully. + */ +int32_t USART_UART_Init(CM_USART_TypeDef *USARTx, const stc_usart_uart_init_t *pstcUartInit, float32_t *pf32Error) +{ + uint32_t u32CR1Value; + uint32_t u32CR2Value; + uint32_t u32CR3Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcUartInit) { + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_SRC(pstcUartInit->u32ClockSrc)); + DDL_ASSERT(IS_USART_CK_OUTPUT(pstcUartInit->u32CKOutput)); + DDL_ASSERT(IS_USART_PARITY(pstcUartInit->u32Parity)); + DDL_ASSERT(IS_USART_DATA_WIDTH(pstcUartInit->u32DataWidth)); + DDL_ASSERT(IS_USART_STOPBIT(pstcUartInit->u32StopBit)); + DDL_ASSERT(IS_USART_OVER_SAMPLE_BIT(pstcUartInit->u32OverSampleBit)); + DDL_ASSERT(IS_USART_FIRST_BIT(pstcUartInit->u32FirstBit)); + DDL_ASSERT(IS_USART_START_BIT_POLARITY(pstcUartInit->u32StartBitPolarity)); + DDL_ASSERT(IS_USART_HW_FLOWCTRL(pstcUartInit->u32HWFlowControl)); + + u32CR1Value = (pstcUartInit->u32Parity | pstcUartInit->u32DataWidth | pstcUartInit->u32FirstBit | \ + pstcUartInit->u32OverSampleBit | pstcUartInit->u32StartBitPolarity); + u32CR2Value = (USART_CR2_RST_VALUE | pstcUartInit->u32ClockSrc | \ + pstcUartInit->u32CKOutput | pstcUartInit->u32StopBit); + u32CR3Value = (pstcUartInit->u32HWFlowControl == USART_HW_FLOWCTRL_CTS) ? USART_HW_FLOWCTRL_CTS : 0UL; + + /* Set control register: CR1/CR2/CR3 */ + WRITE_REG32(USARTx->CR1, u32CR1Value); + WRITE_REG32(USARTx->CR2, u32CR2Value); + WRITE_REG32(USARTx->CR3, u32CR3Value); + + if (USART_CLK_SRC_INTERNCLK == pstcUartInit->u32ClockSrc) { + DDL_ASSERT(IS_USART_CLK_DIV(pstcUartInit->u32ClockDiv)); + + /* Set prescaler register register: PR */ + WRITE_REG32(USARTx->PR, pstcUartInit->u32ClockDiv); + + /* Set baudrate */ + i32Ret = USART_SetBaudrate(USARTx, pstcUartInit->u32Baudrate, pf32Error); + } else { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_usart_smartcard_init_t to default values. + * @param [out] pstcSmartCardInit Pointer to a @ref stc_usart_smartcard_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcSmartCardInit value is NULL. + */ +int32_t USART_SmartCard_StructInit(stc_usart_smartcard_init_t *pstcSmartCardInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcSmartCardInit) { + pstcSmartCardInit->u32ClockDiv = USART_CLK_DIV1; + pstcSmartCardInit->u32CKOutput = USART_CK_OUTPUT_DISABLE; + pstcSmartCardInit->u32Baudrate = USART_DEFAULT_BAUDRATE; + pstcSmartCardInit->u32FirstBit = USART_FIRST_BIT_LSB; + i32Ret = LL_OK; + } + + return i32Ret; +} +/** + * @brief Initialize smartcard function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcSmartCardInit Pointer to a @ref stc_usart_smartcard_init_t structure. + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcSmartCardInit value is NULL or baudrate set unsuccessfully. + */ +int32_t USART_SmartCard_Init(CM_USART_TypeDef *USARTx, + const stc_usart_smartcard_init_t *pstcSmartCardInit, float32_t *pf32Error) +{ + uint32_t u32CR1Value; + uint32_t u32CR2Value; + uint32_t u32CR3Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcSmartCardInit) { + DDL_ASSERT(IS_USART_SMARTCARD_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CK_OUTPUT(pstcSmartCardInit->u32CKOutput)); + DDL_ASSERT(IS_USART_CLK_DIV(pstcSmartCardInit->u32ClockDiv)); + DDL_ASSERT(IS_USART_FIRST_BIT(pstcSmartCardInit->u32FirstBit)); + + u32CR1Value = (pstcSmartCardInit->u32FirstBit | USART_CR1_PCE | USART_CR1_SBS); + u32CR2Value = (pstcSmartCardInit->u32CKOutput | USART_CR2_RST_VALUE); + u32CR3Value = USART_CR3_SCEN | USART_SC_ETU_CLK372; + + /* Set control register: CR1/CR2/CR3 */ + WRITE_REG32(USARTx->CR1, u32CR1Value); + WRITE_REG32(USARTx->CR2, u32CR2Value); + WRITE_REG32(USARTx->CR3, u32CR3Value); + + /* Set prescaler register register: PR */ + WRITE_REG32(USARTx->PR, pstcSmartCardInit->u32ClockDiv); + + /* Set baudrate */ + i32Ret = USART_SetBaudrate(USARTx, pstcSmartCardInit->u32Baudrate, pf32Error); + } + + return i32Ret; +} + +/** + * @brief De-Initialize USART function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval int32_t: + * - LL_OK: Reset success. + */ +int32_t USART_DeInit(CM_USART_TypeDef *USARTx) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + /* Configures the registers to reset value. */ + WRITE_REG32(USARTx->CR1, USART_CR1_RST_VALUE); + WRITE_REG32(USARTx->CR2, USART_CR2_RST_VALUE); + WRITE_REG32(USARTx->CR3, 0UL); + WRITE_REG32(USARTx->PR, 0UL); + + return i32Ret; +} + +/** + * @brief Enable/disable USART Transmit/Receive Function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Func USART function type + * This parameter can be any composed value of the macros group @ref USART_Function. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note In clock synchronization mode, the bit TE or RE of register USART_CR can only be + * written to 1 when TE = 0 and RE = 0 (transmit and receive disabled) + */ +void USART_FuncCmd(CM_USART_TypeDef *USARTx, uint32_t u32Func, en_functional_state_t enNewState) +{ + uint32_t u32BaseFunc; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_USART_FUNC(u32Func)); + + u32BaseFunc = (u32Func & 0xFFFFUL); + if (u32BaseFunc > 0UL) { + (ENABLE == enNewState) ? SET_REG32_BIT(USARTx->CR1, u32BaseFunc) : CLR_REG32_BIT(USARTx->CR1, u32BaseFunc); + } + +} + +/** + * @brief Get USART flag. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Flag USART flag type + * This parameter can be any composed value of the macros group @ref USART_Flag. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t USART_GetStatus(const CM_USART_TypeDef *USARTx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_FLAG(u32Flag)); + + return (0UL == (READ_REG32_BIT(USARTx->SR, u32Flag)) ? RESET : SET); +} + +/** + * @brief Clear USART flag. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Flag USART flag type + * This parameter can be any composed value of the macros group @ref USART_Flag. + * @retval None + */ +void USART_ClearStatus(CM_USART_TypeDef *USARTx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_FLAG(u32Flag)); + + if ((u32Flag & USART_FLAG_ERR_MASK) > 0UL) { + SET_REG32_BIT(USARTx->CR1, (u32Flag & USART_FLAG_ERR_MASK) << USART_CR1_CPE_POS); + } + + /* Timeout flag */ + if ((u32Flag & USART_FLAG_RX_TIMEOUT) > 0UL) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_CRTOF); + } +} + +/** + * @brief Set USART parity. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Parity USART parity + * This parameter can be one of the macros group @ref USART_Parity_Control + * @arg USART_PARITY_NONE: Parity control disabled + * @arg USART_PARITY_ODD: Parity control enabled and Odd Parity is selected + * @arg USART_PARITY_EVEN: Parity control enabled and Even Parity is selected + * @retval None + */ +void USART_SetParity(CM_USART_TypeDef *USARTx, uint32_t u32Parity) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_PARITY(u32Parity)); + + MODIFY_REG32(USARTx->CR1, (USART_CR1_PS | USART_CR1_PCE), u32Parity); +} + +/** + * @brief Set USART bit direction. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32FirstBit USART bit direction + * This parameter can be one of the macros group @ref USART_First_Bit + * @arg USART_FIRST_BIT_MSB: MSB(Most Significant Bit) + * @arg USART_FIRST_BIT_LSB: LSB(Least Significant Bit) + * @retval None + */ +void USART_SetFirstBit(CM_USART_TypeDef *USARTx, uint32_t u32FirstBit) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_FIRST_BIT(u32FirstBit)); + + MODIFY_REG32(USARTx->CR1, USART_CR1_ML, u32FirstBit); +} + +/** + * @brief Set USART stop bit. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32StopBit USART stop bits + * This parameter can be one of the macros group @ref USART_Stop_Bit + * @arg USART_STOPBIT_1BIT: 1 stop bit + * @arg USART_STOPBIT_2BIT: 2 stop bit + * @retval None + */ +void USART_SetStopBit(CM_USART_TypeDef *USARTx, uint32_t u32StopBit) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_STOPBIT(u32StopBit)); + + MODIFY_REG32(USARTx->CR2, USART_CR2_STOP, u32StopBit); +} + +/** + * @brief Set USART data width. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32DataWidth USART data width + * This parameter can be one of the macros group @ref USART_Data_Width_Bit + * @arg USART_DATA_WIDTH_8BIT: 8 bits word width + * @arg USART_DATA_WIDTH_9BIT: 9 bits word width + * @retval None + */ +void USART_SetDataWidth(CM_USART_TypeDef *USARTx, uint32_t u32DataWidth) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_DATA_WIDTH(u32DataWidth)); + + MODIFY_REG32(USARTx->CR1, USART_CR1_M, u32DataWidth); +} + +/** + * @brief Set USART oversampling bits. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32OverSampleBit USART over sample bit + * This parameter can be one of the macros group @ref USART_Over_Sample_Bit + * @arg USART_OVER_SAMPLE_8BIT: Oversampling by 8 bit + * @arg USART_OVER_SAMPLE_16BIT: Oversampling by 16 bit + * @retval None + */ +void USART_SetOverSampleBit(CM_USART_TypeDef *USARTx, uint32_t u32OverSampleBit) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_OVER_SAMPLE_BIT(u32OverSampleBit)); + + MODIFY_REG32(USARTx->CR1, USART_CR1_OVER8, u32OverSampleBit); +} + +/** + * @brief Set USART start bit detect polarity. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Polarity USART start bit detect polarity + * This parameter can be one of the macros group @ref USART_Start_Bit_Polarity + * @arg USART_START_BIT_LOW: Detect RX pin low level + * @arg USART_START_BIT_FALLING: Detect RX pin falling edge + * @retval None + */ +void USART_SetStartBitPolarity(CM_USART_TypeDef *USARTx, uint32_t u32Polarity) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_START_BIT_POLARITY(u32Polarity)); + + MODIFY_REG32(USARTx->CR1, USART_CR1_SBS, u32Polarity); +} + +/** + * @brief Set USART transmission type. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u16Type USART transmission content type + * This parameter can be one of the macros group @ref USART_Transmission_Type + * @arg USART_TRANS_ID: USART transmission content type is processor ID + * @arg USART_TRANS_DATA: USART transmission content type is frame data + * @retval None + */ +void USART_SetTransType(CM_USART_TypeDef *USARTx, uint16_t u16Type) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_TRANS_TYPE(u16Type)); + + MODIFY_REG16(USARTx->TDR, USART_TDR_MPID, u16Type); +} + +/** + * @brief Set USART clock prescaler division. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32ClockDiv USART clock prescaler division. + * This parameter can be one of the macros group @ref USART_Clock_Division + * @retval None + * @note The clock division function is valid only when clock source is internal clock. + */ +void USART_SetClockDiv(CM_USART_TypeDef *USARTx, uint32_t u32ClockDiv) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_DIV(u32ClockDiv)); + + MODIFY_REG32(USARTx->PR, USART_PR_PSC, u32ClockDiv); +} + +/** + * @brief Get USART clock prescaler division. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval Returned value can be one of the macros group @ref USART_Clock_Division + * @note The clock division function is valid only when clock source is internal clock. + */ +uint32_t USART_GetClockDiv(const CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + return READ_REG32_BIT(USARTx->PR, USART_PR_PSC); +} + +/** + * @brief Set USART clock source. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32ClockSrc USART clock source + * This parameter can be one of the macros group @ref USART_Clock_Source + * @arg USART_CLK_SRC_EXTCLK: Clock source is external clock(USART_CK). + * @arg USART_CLK_SRC_INTERNCLK: Clock source is internal clock. + * @retval None + */ +void USART_SetClockSrc(CM_USART_TypeDef *USARTx, uint32_t u32ClockSrc) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_SRC(u32ClockSrc)); + + MODIFY_REG32(USARTx->CR2, USART_CR2_CLKC_1, u32ClockSrc); +} + +/** + * @brief Get USART clock source. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval Returned value can be one of the following values: + * - USART_CLK_SRC_EXTCLK: Clock source is external clock(USART_CK). + * - USART_CLK_SRC_INTERNCLK: Clock source is internal clock. + */ +uint32_t USART_GetClockSrc(const CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + return READ_REG32_BIT(USARTx->CR2, USART_CR2_CLKC_1); +} + +/** + * @brief Enable or disable USART noise filter. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void USART_FilterCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_NFE); + } else { + CLR_REG32_BIT(USARTx->CR1, USART_CR1_NFE); + } +} + +/** + * @brief Enable or disable USART silence. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void USART_SilenceCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_SLME); + } else { + CLR_REG32_BIT(USARTx->CR1, USART_CR1_SLME); + } +} + +/** + * @brief Set UART hardware flow control CTS/RTS selection. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32HWFlowControl USART hardware flow control CTS/RTS selection + * This parameter can be one of the macros group @ref USART_Hardware_Flow_Control. + * @retval None + */ +void USART_SetHWFlowControl(CM_USART_TypeDef *USARTx, uint32_t u32HWFlowControl) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_HW_FLOWCTRL(u32HWFlowControl)); + + if (USART_HW_FLOWCTRL_CTS == u32HWFlowControl) { + SET_REG32_BIT(USARTx->CR3, USART_CR3_CTSE); + } else { + CLR_REG32_BIT(USARTx->CR3, USART_CR3_CTSE); + } +} + +/** + * @brief USART receive data. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval Receive data + */ +uint16_t USART_ReadData(const CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + return READ_REG16(USARTx->RDR); +} + +/** + * @brief USART send data. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u16Data Transmit data + * @retval None + */ +void USART_WriteData(CM_USART_TypeDef *USARTx, uint16_t u16Data) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_DATA(u16Data)); + + WRITE_REG16(USARTx->TDR, u16Data); +} + +/** + * @brief USART send processor ID. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + ** @param [in] u16ID Processor ID + * @retval None + */ +void USART_WriteID(CM_USART_TypeDef *USARTx, uint16_t u16ID) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_DATA(u16ID)); + + WRITE_REG16(USARTx->TDR, (USART_TDR_MPID | u16ID)); +} + +/** + * @brief Set USART baudrate. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Baudrate UART baudrate + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR_INVD_PARAM: Set unsuccessfully. + * @note The function uses fraction division to ensure baudrate accuracy if USART unit supports baudrate fraction division. + */ +int32_t USART_SetBaudrate(CM_USART_TypeDef *USARTx, uint32_t u32Baudrate, float32_t *pf32Error) +{ + uint32_t u32Mode; + stc_usart_brr_t stcUsartBrr; + int32_t i32Ret; + + DDL_ASSERT(u32Baudrate > 0UL); + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + /* Get USART clock frequency */ + stcUsartBrr.u32UsartClock = USART_GetUsartClockFreq(USARTx); + stcUsartBrr.u32Baudrate = u32Baudrate; + stcUsartBrr.f32Error = 0.0F; + stcUsartBrr.u32Fraction = 0xFFUL; + + /* Get usart mode */ + u32Mode = READ_REG32_BIT(USARTx->CR1, USART_CR1_MS); + /* Calculate baudrate for BRR */ + if (0UL == u32Mode) { + if (0UL == READ_REG32_BIT(USARTx->CR3, USART_CR3_SCEN)) { + /* uart mode */ + i32Ret = UART_CalculateBrr(USARTx, &stcUsartBrr); + } else { + /* Smart_card function */ + i32Ret = SmartCard_CalculateBrr(USARTx, &stcUsartBrr); + } + } else { + /* Clock sync mode */ + i32Ret = ClockSync_CalculateBrr(USARTx, &stcUsartBrr); + } + + if (LL_OK == i32Ret) { + /* Set BRR value(integer & fraction) */ + MODIFY_REG32(USARTx->BRR, (USART_BRR_DIV_INTEGER | USART_BRR_DIV_FRACTION), \ + (stcUsartBrr.u32Fraction | (stcUsartBrr.u32Integer << USART_BRR_DIV_INTEGER_POS))); + + if (0xFFUL != stcUsartBrr.u32Fraction) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_FBME); + } + } else { + /* rsvd */ + } + if (NULL != pf32Error) { + *pf32Error = stcUsartBrr.f32Error; + } + + return i32Ret; +} + +/** + * @brief Set USART Smartcard ETU Clock. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32EtuClock USART Smartcard ETU Clock. + * This parameter can be one of the macros group @ref USART_Smartcard_ETU_Clock + * @arg USART_SC_ETU_CLK32: 1 etu = 32/f + * @arg USART_SC_ETU_CLK64: 1 etu = 64/f + * @arg USART_SC_ETU_CLK128: 1 etu = 128/f + * @arg USART_SC_ETU_CLK256: 1 etu = 256/f + * @arg USART_SC_ETU_CLK372: 1 etu = 372/f + * @retval None + */ +void USART_SmartCard_SetEtuClock(CM_USART_TypeDef *USARTx, uint32_t u32EtuClock) +{ + DDL_ASSERT(IS_USART_SMARTCARD_UNIT(USARTx)); + DDL_ASSERT(IS_USART_SMARTCARD_ETU_CLK(u32EtuClock)); + + MODIFY_REG32(USARTx->CR3, USART_CR3_BCN, u32EtuClock); +} + +/** + * @brief UART transmit data in polling mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [out] pvBuf The pointer to data transmitted buffer + * @param [in] u32Len Amount of frame to be sent. + * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Communicate timeout. + * - LL_ERR_INVD_PARAM: u32Len value is 0 or pvBuf is NULL. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT + */ +int32_t USART_UART_Trans(CM_USART_TypeDef *USARTx, const void *pvBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t i; + uint32_t u32DataWidth; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + if ((NULL != pvBuf) && (u32Len > 0UL)) { + u32DataWidth = READ_REG32_BIT(USARTx->CR1, USART_CR1_M); + + if ((USART_DATA_WIDTH_8BIT == u32DataWidth) || (USART_DATA_WIDTH_9BIT == u32DataWidth)) { + for (i = 0UL; i < u32Len; i++) { + /* Wait TX buffer empty. */ + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_EMPTY, SET, u32Timeout); + if (LL_OK != i32Ret) { + break; + } + + if (u32DataWidth == USART_DATA_WIDTH_8BIT) { + USART_WriteData(USARTx, ((const uint8_t *)pvBuf)[i]); + } else { + USART_WriteData(USARTx, ((const uint16_t *)pvBuf)[i]); + } + } + + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_CPLT, SET, u32Timeout); + } + } + } + + return i32Ret; +} + +/** + * @brief UART receive data in polling mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [out] pvBuf The pointer to data received buffer + * @param [in] u32Len Amount of frame to be received. + * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Communicate timeout. + * - LL_ERR_INVD_PARAM: u32Len value is 0 or the pointer pvBuf value is NULL. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT + */ +int32_t USART_UART_Receive(const CM_USART_TypeDef *USARTx, void *pvBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t u32Count; + uint32_t u32DataWidth; + uint16_t u16ReceiveData; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + if ((NULL != pvBuf) && (u32Len > 0UL)) { + u32DataWidth = READ_REG32_BIT(USARTx->CR1, USART_CR1_M); + + for (u32Count = 0UL; u32Count < u32Len; u32Count++) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_RX_FULL, SET, u32Timeout); + if (LL_OK == i32Ret) { + u16ReceiveData = USART_ReadData(USARTx); + if (USART_DATA_WIDTH_8BIT == u32DataWidth) { + ((uint8_t *)pvBuf)[u32Count] = (uint8_t)(u16ReceiveData & 0xFFU); + } else { + ((uint16_t *)pvBuf)[u32Count] = (uint16_t)(u16ReceiveData & 0x1FFU); + } + } else { + break; + } + } + } + + return i32Ret; +} + +/** + * @brief Clock sync transmit && receive data in polling mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] au8Buf The pointer to data transmitted buffer + * @param [in] u32Len Amount of data to be transmitted. + * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Communicate timeout. + * - LL_ERR_INVD_PARAM: u32Len value is 0 or the pointer au8Buf value is NULL. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT + */ +int32_t USART_ClockSync_Trans(CM_USART_TypeDef *USARTx, const uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t i; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + if ((NULL != au8Buf) && (u32Len > 0UL)) { + for (i = 0UL; i < u32Len; i++) { + /* Wait TX buffer empty. */ + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_EMPTY, SET, u32Timeout); + if (LL_OK == i32Ret) { + USART_WriteData(USARTx, au8Buf[i]); + if (READ_REG32_BIT(USARTx->CR1, USART_RX) != 0UL) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_RX_FULL, SET, u32Timeout); + if (LL_OK == i32Ret) { + (void)USART_ReadData(USARTx); + } + } + } + + if (LL_OK != i32Ret) { + break; + } + } + + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_CPLT, SET, u32Timeout); + } + } + + return i32Ret; +} + +/** + * @brief Clock sync receive data in polling mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [out] au8Buf The pointer to data received buffer + * @param [in] u32Len Amount of data to be sent and received. + * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Communicate timeout. + * - LL_ERR_INVD_PARAM: u32Len value is 0 or the pointer au8Buf value is NULL. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT. + */ +int32_t USART_ClockSync_Receive(CM_USART_TypeDef *USARTx, uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t i; + en_functional_state_t enTX; + en_functional_state_t enMasterMode; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + if ((NULL != au8Buf) && (u32Len > 0UL)) { + i32Ret = LL_OK; + enTX = (READ_REG32_BIT(USARTx->CR1, USART_TX) == 0UL) ? DISABLE : ENABLE; + enMasterMode = (USART_CLK_SRC_EXTCLK == READ_REG32_BIT(USARTx->CR2, USART_CR2_CLKC)) ? DISABLE : ENABLE; + + for (i = 0UL; i < u32Len; i++) { + if ((ENABLE == enMasterMode) || (ENABLE == enTX)) { + USART_WriteData(USARTx, 0xFFU); + + /* Wait TX buffer empty. */ + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_EMPTY, SET, u32Timeout); + } + + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_RX_FULL, SET, u32Timeout); + if (LL_OK == i32Ret) { + au8Buf[i] = (uint8_t)USART_ReadData(USARTx); + } + } + + if (LL_OK != i32Ret) { + break; + } + } + + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_CPLT, SET, u32Timeout); + } + } + + return i32Ret; +} + +/** + * @brief Clock sync transmit && receive data in polling mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] au8TxBuf The pointer to data transmitted buffer + * @param [out] au8RxBuf The pointer to data received buffer + * @param [in] u32Len Amount of data to be sent and received. + * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Communicate timeout. + * - LL_ERR_INVD_PARAM: u32Len value is 0. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT. + */ +int32_t USART_ClockSync_TransReceive(CM_USART_TypeDef *USARTx, const uint8_t au8TxBuf[], uint8_t au8RxBuf[], + uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t i; + uint8_t u8ReceiveData; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + if (u32Len > 0UL) { + for (i = 0UL; i < u32Len; i++) { + if (NULL != au8TxBuf) { + USART_WriteData(USARTx, au8TxBuf[i]); + } else { + USART_WriteData(USARTx, 0xFFU); + } + + /* Wait TX buffer empty. */ + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_EMPTY, SET, u32Timeout); + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_RX_FULL, SET, u32Timeout); + if (LL_OK == i32Ret) { + u8ReceiveData = (uint8_t)USART_ReadData(USARTx); + if (NULL != au8RxBuf) { + au8RxBuf[i] = u8ReceiveData; + } + } + } + + if (LL_OK != i32Ret) { + break; + } + } + + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_CPLT, SET, u32Timeout); + } + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_USART_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_usb.c b/mcu/lib/src/hc32_ll_usb.c new file mode 100644 index 0000000..bf41adc --- /dev/null +++ b/mcu/lib/src/hc32_ll_usb.c @@ -0,0 +1,1317 @@ +/** + ******************************************************************************* + * @file hc32_ll_usb.c + * @brief USB core driver. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Add USB core ID select function + 2022-10-31 CDT Add USB DMA function + 2023-09-30 CDT Fix bug for function usb_clearepstall() + Modify typo + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_usb.h" +#include "hdl_clk.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_USB USB + * @brief USB Driver Library + * @{ + */ + +#if (LL_USB_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Parameters check */ +#define IS_USB_CORE_ID(x) \ +( ((x) == USBFS_CORE_ID)) + +#define IS_USB_PHY_TYPE(x) \ +( ((x) == USBHS_PHY_EMBED)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup USB_Global_Functions USB Global Functions + * @{ + */ + +/** + * @brief core software reset + * @param [in] USBx usb instance + * @retval None + */ +void usb_coresoftrst(LL_USB_TypeDef *USBx) +{ + __IO uint8_t u8Status = USB_OK;; + __IO uint32_t u32grstctl = 0UL; + __IO uint32_t u32Count = 0UL; + + /* Wait for AHB master to be idle. */ + do { + hdl_delay_us(1UL); + u32grstctl = READ_REG32(USBx->GREGS->GRSTCTL); + if (++u32Count > 100000UL) { + u8Status = USB_ERROR; + } + } while (0UL == (u32grstctl & USBFS_GRSTCTL_AHBIDL)); + + if (USB_OK == u8Status) { + /* Write the Core Soft Reset bit to reset the USB core */ + u32Count = 0UL; + u32grstctl |= USBFS_GRSTCTL_CSRST; + WRITE_REG32(USBx->GREGS->GRSTCTL, u32grstctl); + + /* Wait for the reset finishing */ + do { + u32grstctl = READ_REG32(USBx->GREGS->GRSTCTL); + if (u32Count > 100000UL) { + break; + } + u32Count++; + hdl_delay_us(1UL); + } while (0UL != (u32grstctl & USBFS_GRSTCTL_CSRST)); + /* Wait for at least 3 PHY clocks after the core resets */ + hdl_delay_us(3UL); + } +} + +/** + * @brief Writes a packet whose byte number is len into the Tx FIFO associated + * with the EP + * @param [in] USBx usb instance + * @param [in] src source pointer used to hold the transmitted data + * @param [in] ch_ep_num end point index + * @param [in] len length in bytes + * @param [in] u8DmaEn USB DMA status + * @retval None + */ +void usb_wrpkt(LL_USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t u8DmaEn) +{ + __IO uint32_t u32pAddr; + __IO uint32_t *fifo; + uint32_t u32Count32b; + uint32_t u32Tmp; + if (u8DmaEn == 0U) { + u32Count32b = (len + 3UL); + u32Count32b = u32Count32b >> 2U; + fifo = USBx->DFIFO[ch_ep_num]; + u32Tmp = 0UL; + while (u32Tmp < u32Count32b) { + WRITE_REG32(*fifo, *((uint32_t *)src)); + u32pAddr = (uint32_t)src; + src = (uint8_t *)(u32pAddr + 4U); + u32Tmp++; + } + } +} + +/** + * @brief Reads a packet whose byte number is len from the Rx FIFO + * @param [in] USBx usb instance + * @param [in] dest destination pointer that point to the received data + * @param [in] len number of bytes + * @retval None + */ +void usb_rdpkt(LL_USB_TypeDef *USBx, uint8_t *dest, uint16_t len) +{ + uint32_t u32Tmp; + __IO uint32_t u32Count32b; + __IO uint32_t u32pAddr; + + __IO uint32_t *fifo = USBx->DFIFO[0]; + u32Count32b = (len + 3UL); + u32Count32b = u32Count32b >> 2U; + u32pAddr = 0UL; + u32Tmp = 0UL; + while (u32Tmp < u32Count32b) { + *(uint32_t *)dest = READ_REG32(*fifo); + u32pAddr = (uint32_t)dest; + dest = (uint8_t *)(u32pAddr + 4U); + u32Tmp++; + } +} + +/** + * @brief Initialize the addresses of the core registers. + * @param [in] USBx usb instance + * @param [in] pstcPortIdentify usb core and phy select + * @param [in] basic_cfgs usb core basic cfgs + * @retval None + */ +void usb_setregaddr(LL_USB_TypeDef *USBx, stc_usb_port_identify *pstcPortIdentify, USB_CORE_BASIC_CFGS *basic_cfgs) +{ + uint32_t u32Tmp = 0UL; + uint32_t u32baseAddr = CM_USBFS_BASE; + DDL_ASSERT(IS_USB_CORE_ID(pstcPortIdentify->u8CoreID)); +#if defined (USB_INTERNAL_DMA_ENABLED) + basic_cfgs->dmaen = 1U; +#else + basic_cfgs->dmaen = 0U; +#endif + /* initialize device cfg following its address */ + basic_cfgs->host_chnum = USB_MAX_CH_NUM; + basic_cfgs->dev_epnum = USB_MAX_EP_NUM; + basic_cfgs->core_type = pstcPortIdentify->u8CoreID; + basic_cfgs->phy_type = USBHS_PHY_EMBED; + if (USBFS_CORE_ID == pstcPortIdentify->u8CoreID) { +#ifdef USB_FS_MODE + u32baseAddr = CM_USBFS_BASE; +#endif + } else { +#ifdef USB_HS_MODE + u32baseAddr = CM_USBHS_BASE; +#endif + } + + USBx->GREGS = (USB_CORE_GREGS *)(u32baseAddr + 0UL); + USBx->DREGS = (USB_CORE_DREGS *)(u32baseAddr + 0x800UL); + + while (u32Tmp < basic_cfgs->dev_epnum) { + USBx->INEP_REGS[u32Tmp] = (USB_CORE_INEPREGS *)(u32baseAddr + 0x900UL + (u32Tmp * 0x20UL)); + USBx->OUTEP_REGS[u32Tmp] = (USB_CORE_OUTEPREGS *)(u32baseAddr + 0xb00UL + (u32Tmp * 0x20UL)); + u32Tmp++; + } + u32Tmp = 0UL; + while (u32Tmp < basic_cfgs->dev_epnum) { + USBx->DFIFO[u32Tmp] = (uint32_t *)(u32baseAddr + 0x1000UL + (u32Tmp * 0x1000UL)); + u32Tmp++; + } + USBx->GCCTL = (uint32_t *)(u32baseAddr + 0xe00UL); +#ifdef USE_HOST_MODE /* if the application mode is host */ + USBx->HREGS = (USB_CORE_HREGS *)(u32baseAddr + 0x400UL); + USBx->HPRT = (uint32_t *)(u32baseAddr + 0x440UL); + u32Tmp = 0UL; + while (u32Tmp < basic_cfgs->host_chnum) { + USBx->HC_REGS[u32Tmp] = (USB_CORE_HC_REGS *)(u32baseAddr + 0x500UL + (u32Tmp * 0x20UL)); + u32Tmp++; + } +#endif /* USE_HOST_MODE */ +} + +/** + * @brief Initializes the USB controller registers and prepares the core + * device mode or host mode operation. + * @param [in] USBx usb instance + * @param [in] basic_cfgs usb core basic cfgs + * @retval None + */ +void usb_initusbcore(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs) +{ + /* reset the core through core soft reset */ + usb_coresoftrst(USBx); + + /* Select PHY for USB core*/ + usb_PhySelect(USBx, basic_cfgs->phy_type); + /* reset the core through core soft reset */ + usb_coresoftrst(USBx); + hdl_delay_ms(20UL); + if (basic_cfgs->dmaen == 1U) { + /* burst length/type(HBstLen) 64-words x32-bit, core operates in a DMA mode*/ + usb_BurstLenConfig(USBx, 5U); + usb_DmaCmd(USBx, 1U); + } +} + +/** + * @brief Flush a Tx FIFO whose index is num + * @param [in] USBx usb instance + * @param [in] num txFIFO index + * @retval None + */ +void usb_txfifoflush(LL_USB_TypeDef *USBx, uint32_t num) +{ + __IO uint32_t u32grstctl; + __IO uint32_t u32Tmp = 0UL; + + u32grstctl = USBFS_GRSTCTL_TXFFLSH | ((num & 0x1FUL) << USBFS_GRSTCTL_TXFNUM_POS); + /* set the TxFIFO Flush bit, set TxFIFO Number */ + WRITE_REG32(USBx->GREGS->GRSTCTL, u32grstctl); + + /* wait for the finishing of txFIFO flushing */ + do { + u32grstctl = READ_REG32(USBx->GREGS->GRSTCTL); + if (u32Tmp <= 200000UL) { + u32Tmp++; + } else { + break; + } + hdl_delay_us(1UL); + } while (0UL != (u32grstctl & USBFS_GRSTCTL_TXFFLSH)); + /* Wait for at least 3 PHY clocks after the txfifo has been flushed */ + hdl_delay_us(3UL); +} + +/** + * @brief Flush the whole rxFIFO + * @param [in] USBx usb instance + * @retval None + */ +void usb_rxfifoflush(LL_USB_TypeDef *USBx) +{ + __IO uint32_t u32grstctl; + __IO uint32_t u32Tmp = 0UL; + + u32grstctl = USBFS_GRSTCTL_RXFFLSH; /* set the RxFIFO Flush bit */ + WRITE_REG32(USBx->GREGS->GRSTCTL, u32grstctl); + /* wait for the finishing of rxFIFO flushing */ + do { + u32grstctl = READ_REG32(USBx->GREGS->GRSTCTL); + if (u32Tmp <= 200000UL) { + u32Tmp++; + } else { + break; + } + hdl_delay_us(1UL); + } while (0UL != (u32grstctl & USBFS_GRSTCTL_RXFFLSH)); + /* Wait for at least 3 PHY clocks after the rxfifo has been flushed */ + hdl_delay_us(3UL); +} + +/** + * @brief set the core to be host mode or device mode through the second + * input parameter. + * @param [in] USBx usb instance + * @param [in] mode mode of HOST_MODE or DEVICE_MODE that the core would be + * @retval None + */ +void usb_modeset(LL_USB_TypeDef *USBx, uint8_t mode) +{ + if (mode == HOST_MODE) { + MODIFY_REG32(USBx->GREGS->GUSBCFG, USBFS_GUSBCFG_FHMOD | USBFS_GUSBCFG_FDMOD, USBFS_GUSBCFG_FHMOD); + } else { + MODIFY_REG32(USBx->GREGS->GUSBCFG, USBFS_GUSBCFG_FHMOD | USBFS_GUSBCFG_FDMOD, USBFS_GUSBCFG_FDMOD); + } + /* wate for the change to take effect */ + hdl_delay_ms(50UL); +} + +#ifdef USE_DEVICE_MODE + +/** + * @brief initializes the initial status of all endpoints of the device to be + * disable. + * @param [in] USBx usb instance + * @param [in] u8EpNum EP number + * @retval None + */ +void usb_devepdis(LL_USB_TypeDef *USBx, uint8_t u8EpNum) +{ + uint8_t u8Tmp = 0U; + + while (u8Tmp < u8EpNum) { + if (0UL != READ_REG32_BIT(USBx->INEP_REGS[u8Tmp]->DIEPCTL, USBFS_DIEPCTL_EPENA)) { + WRITE_REG32(USBx->INEP_REGS[u8Tmp]->DIEPCTL, USBFS_DIEPCTL_EPDIS | USBFS_DIEPCTL_SNAK); + } else { + WRITE_REG32(USBx->INEP_REGS[u8Tmp]->DIEPCTL, 0UL); + } + WRITE_REG32(USBx->INEP_REGS[u8Tmp]->DIEPTSIZ, 0UL); + WRITE_REG32(USBx->INEP_REGS[u8Tmp]->DIEPINT, 0xFFUL); + u8Tmp++; + } + + u8Tmp = 0U; + while (u8Tmp < u8EpNum) { + if (0UL != READ_REG32_BIT(USBx->OUTEP_REGS[u8Tmp]->DOEPCTL, USBFS_DOEPCTL_EPENA)) { + WRITE_REG32(USBx->OUTEP_REGS[u8Tmp]->DOEPCTL, USBFS_DOEPCTL_EPDIS | USBFS_DOEPCTL_SNAK); + } else { + WRITE_REG32(USBx->OUTEP_REGS[u8Tmp]->DOEPCTL, 0UL); + } + WRITE_REG32(USBx->OUTEP_REGS[u8Tmp]->DOEPTSIZ, 0UL); + WRITE_REG32(USBx->OUTEP_REGS[u8Tmp]->DOEPINT, 0xFFUL); + u8Tmp++; + } +} + +#ifdef USB_FS_MODE +static void usb_DevFSFifoConfig(LL_USB_TypeDef *USBx) +{ + uint32_t u32StardAddr; + + WRITE_REG32(USBx->GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); + /* set txFIFO and rxFIFO size of EP0 */ + u32StardAddr = RX_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->HNPTXFSIZ, + (RX_FIFO_FS_SIZE << USBFS_HNPTXFSIZ_NPTXFSA_POS) | (TX0_FIFO_FS_SIZE << USBFS_HNPTXFSIZ_NPTXFD_POS)); + /* set txFIFO size of EP1 */ + u32StardAddr += TX0_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[0], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX1_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP2 */ + u32StardAddr += TX1_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[1], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX2_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP3 */ + u32StardAddr += TX2_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[2], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX3_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP4 */ + u32StardAddr += TX3_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[3], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX4_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP5 */ + u32StardAddr += TX4_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[4], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX5_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); +} +#endif + +#ifdef USB_HS_MODE +static void usb_DevHSFifoConfig(LL_USB_TypeDef *USBx) +{ + uint32_t u32StardAddr; + + WRITE_REG32(USBx->GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); + /* set txFIFO and rxFIFO size of EP0 */ + u32StardAddr = RX_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->HNPTXFSIZ, + (RX_FIFO_HS_SIZE << USBFS_HNPTXFSIZ_NPTXFSA_POS) | (TX0_FIFO_HS_SIZE << USBFS_HNPTXFSIZ_NPTXFD_POS)); + /* set txFIFO size of EP1 */ + u32StardAddr += TX0_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[0], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX1_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP2 */ + u32StardAddr += TX1_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[1], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX2_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP3 */ + u32StardAddr += TX2_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[2], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX3_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP4 */ + u32StardAddr += TX3_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[3], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX4_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP5 */ + u32StardAddr += TX4_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[4], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX5_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP6 */ + u32StardAddr += TX5_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[5], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX6_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP7 */ + u32StardAddr += TX6_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[6], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX7_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP8 */ + u32StardAddr += TX7_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[7], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX8_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP9 */ + u32StardAddr += TX8_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[8], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX9_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP10 */ + u32StardAddr += TX9_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[9], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX10_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP11 */ + u32StardAddr += TX10_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[10], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX11_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP12 */ + u32StardAddr += TX11_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[11], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX12_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP13 */ + u32StardAddr += TX12_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[12], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX13_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP14 */ + u32StardAddr += TX13_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[13], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX14_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP15 */ + u32StardAddr += TX14_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[14], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX15_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); +} +#endif + +/** + * @brief initializes the USB controller, include the size of txFIFO, rxFIFO + * status of endpoints, interrupt register etc. Details are shown as + * follows. + * @param [in] USBx usb instance + * @param [in] basic_cfgs usb core basic cfgs + * @retval None + */ +void usb_devmodeinit(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs) +{ + usb_FrameIntervalConfig(USBx, USB_FRAME_INTERVAL_80); + usb_DevPhySelect(USBx, basic_cfgs->phy_type); + + if (basic_cfgs->core_type == 0U) { +#ifdef USB_FS_MODE + usb_DevFSFifoConfig(USBx); +#endif + } else { +#ifdef USB_HS_MODE + usb_DevHSFifoConfig(USBx); +#endif + } + + usb_clrandmskepint(USBx); + usb_devepdis(USBx, basic_cfgs->dev_epnum); + usb_coreconn(USBx); + usb_devinten(USBx, basic_cfgs->dmaen); +} + +/** + * @brief Enable the interrupt setting when in device mode. + * @param [in] USBx usb instance + * @param [in] u8DmaEn USB DMA status + * @retval None + */ +void usb_devinten(LL_USB_TypeDef *USBx, uint8_t u8DmaEn) +{ + uint32_t u32gintmskTmp = 0UL; + + WRITE_REG32(USBx->GREGS->GINTMSK, 0UL); + WRITE_REG32(USBx->GREGS->GINTSTS, 0xBFFFFFFFUL); + /* Enable the normal interrupt setting */ + usb_normalinten(USBx); + if (u8DmaEn == 0U) { + u32gintmskTmp |= USBFS_GINTMSK_RXFNEM; + } + /* Enable interrupts bits corresponding to the Device mode */ + u32gintmskTmp |= (USBFS_GINTMSK_USBSUSPM | USBFS_GINTMSK_USBRSTM | USBFS_GINTMSK_ENUMDNEM + | USBFS_GINTMSK_IEPIM | USBFS_GINTMSK_OEPIM | USBFS_GINTMSK_SOFM + | USBFS_GINTMSK_IISOIXFRM | USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM); +#ifdef VBUS_SENSING_ENABLED + u32gintmskTmp |= USBFS_GINTMSK_VBUSVIM; +#endif + SET_REG32_BIT(USBx->GREGS->GINTMSK, u32gintmskTmp); +} + +/** + * @brief get the working status of endpoint. + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @retval current status of the endpoint + */ +uint32_t usb_epstatusget(LL_USB_TypeDef *USBx, USB_DEV_EP *ep) +{ + __IO uint32_t u32Status = 0UL; + uint32_t u32dxepctl; + + if (ep->ep_dir == 1U) { + u32dxepctl = READ_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL); + + if (0UL != (u32dxepctl & USBFS_DIEPCTL_STALL)) { + u32Status = USB_EP_TX_STALL; + } else if (0UL != (u32dxepctl & USBFS_DIEPCTL_NAKSTS)) { + u32Status = USB_EP_TX_NAK; + } else { + u32Status = USB_EP_TX_VALID; + } + } else { + u32dxepctl = READ_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL); + if (0UL != (u32dxepctl & USBFS_DOEPCTL_STALL)) { + u32Status = USB_EP_RX_STALL; + } else if (0UL != (u32dxepctl & USBFS_DOEPCTL_NAKSTS)) { + u32Status = USB_EP_RX_NAK; + } else { + u32Status = USB_EP_RX_VALID; + } + } + + return u32Status; +} + +/** + * @brief set the working status of endpoint. + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @param [in] Status new Status that the endpoint would be + * @retval None + */ +void usb_epstatusset(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint32_t Status) +{ + uint32_t u32dxepctl; + uint8_t u8RetFlag = 0U; + + if (ep->ep_dir == 1U) { + u32dxepctl = READ_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL); + + switch (Status) { + case USB_EP_TX_STALL: + usb_setepstall(USBx, ep); + u8RetFlag = 1U; + break; + case USB_EP_TX_NAK: + u32dxepctl |= USBFS_DIEPCTL_SNAK; + break; + case USB_EP_TX_VALID: + if (0UL != (u32dxepctl & USBFS_DIEPCTL_STALL)) { + ep->datax_pid = 0U; + usb_clearepstall(USBx, ep); + u8RetFlag = 1U; + } + u32dxepctl |= (USBFS_DIEPCTL_CNAK | USBFS_DIEPCTL_USBAEP | USBFS_DIEPCTL_EPENA); + break; + case USB_EP_TX_DIS: + u32dxepctl &= (~USBFS_DIEPCTL_USBAEP); + break; + default: + break; + } + /* Write register */ + if (1U != u8RetFlag) { + WRITE_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL, u32dxepctl); + } + } else { + u32dxepctl = READ_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL); + + switch (Status) { + case USB_EP_RX_STALL: + u32dxepctl |= USBFS_DOEPCTL_STALL; + break; + case USB_EP_RX_NAK: + u32dxepctl |= USBFS_DOEPCTL_SNAK; + break; + case USB_EP_RX_VALID: + if (0UL != (u32dxepctl & USBFS_DOEPCTL_STALL)) { + ep->datax_pid = 0U; + usb_clearepstall(USBx, ep); + u8RetFlag = 1U; + } + u32dxepctl |= (USBFS_DOEPCTL_CNAK | USBFS_DOEPCTL_USBAEP | USBFS_DOEPCTL_EPENA); + break; + case USB_EP_RX_DIS: + u32dxepctl &= (~USBFS_DOEPCTL_USBAEP); + break; + default: + break; + } + /* Write register */ + if (1U != u8RetFlag) { + WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL, u32dxepctl); + } + } +} + +/** + * @brief enable the EP0 to be actiove + * @param [in] USBx usb instance + * @retval None + */ +void usb_ep0activate(LL_USB_TypeDef *USBx) +{ + uint32_t u32EnumSpeed; + uint32_t u32DiepctlTmp; + + u32EnumSpeed = READ_REG32(USBx->DREGS->DSTS) & USBFS_DSTS_ENUMSPD; + u32DiepctlTmp = READ_REG32(USBx->INEP_REGS[0]->DIEPCTL); + /* Set the MPS of the DIEPCTL0 based on the enumeration speed */ + if ((DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ == u32EnumSpeed) + || (DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ == u32EnumSpeed) + || (DSTS_ENUMSPD_FS_PHY_48MHZ == u32EnumSpeed)) { + u32DiepctlTmp &= (~USBFS_DIEPCTL_MPSIZ); + } else if (DSTS_ENUMSPD_LS_PHY_6MHZ == u32EnumSpeed) { + u32DiepctlTmp &= (~USBFS_DIEPCTL_MPSIZ); + u32DiepctlTmp |= (3UL << USBFS_DIEPCTL_MPSIZ_POS); + } else { + ; + } + WRITE_REG32(USBx->INEP_REGS[0]->DIEPCTL, u32DiepctlTmp); + SET_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_CGINAK); +} + +/** + * @brief enable an EP to be active + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @retval None + */ +void usb_epactive(LL_USB_TypeDef *USBx, USB_DEV_EP *ep) +{ + uint32_t u32Addr; + uint32_t u32dxepctl; + uint32_t u32Daintmsk; + + if (ep->ep_dir == 1U) { + u32Addr = (uint32_t)(&(USBx->INEP_REGS[ep->epidx]->DIEPCTL)); + u32Daintmsk = 1UL << ep->epidx; + } else { + u32Addr = (uint32_t)(&(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL)); + u32Daintmsk = 1UL << (USBFS_DAINTMSK_OEPINTM_POS + ep->epidx); + } + u32dxepctl = READ_REG32(*(__IO uint32_t *)u32Addr); + if (0UL == (u32dxepctl & USBFS_DIEPCTL_USBAEP)) { + u32dxepctl = ((ep->maxpacket << USBFS_DIEPCTL_MPSIZ_POS) + | (((uint32_t)ep->trans_type) << USBFS_DIEPCTL_EPTYP_POS) + | (((uint32_t)ep->tx_fifo_num) << USBFS_DIEPCTL_TXFNUM_POS) + | USBFS_DIEPCTL_SD0PID_SEVNFRM + | USBFS_DIEPCTL_USBAEP); + + WRITE_REG32(*(__IO uint32_t *)u32Addr, u32dxepctl); + } + SET_REG32_BIT(USBx->DREGS->DAINTMSK, u32Daintmsk); +} + +/** + * @brief enable an EP to be deactive state if it is active + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @retval None + */ +void usb_epdeactive(LL_USB_TypeDef *USBx, USB_DEV_EP *ep) +{ + uint32_t u32Daintmsk; + + if (ep->ep_dir == 1U) { + CLR_REG32_BIT(USBx->INEP_REGS[ep->epidx]->DIEPCTL, USBFS_DIEPCTL_USBAEP); + u32Daintmsk = 1UL << ep->epidx; + } else { + CLR_REG32_BIT(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL, USBFS_DOEPCTL_USBAEP); + u32Daintmsk = 1UL << (USBFS_DAINTMSK_OEPINTM_POS + ep->epidx); + } + CLR_REG32_BIT(USBx->DREGS->DAINTMSK, u32Daintmsk); +} + +/** + * @brief Setup the data into the EP and begin to transmit data. + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @param [in] u8DmaEn USB DMA status + * @retval None + */ +void usb_epntransbegin(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint8_t u8DmaEn) +{ + uint32_t u32depctl; + uint32_t u32DeptsizTmp; + uint32_t u32Pktcnt; + uint32_t u32Xfersize; + + if (ep->ep_dir == 1U) { + u32depctl = READ_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL); + /* Zero Length Packet? */ + if (ep->xfer_len == 0UL) { + u32Xfersize = 0UL; + u32Pktcnt = 1UL; + u32DeptsizTmp = (u32Xfersize << USBFS_DIEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DIEPTSIZ_PKTCNT_POS); + } else { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + u32Xfersize = ep->xfer_len; + u32Pktcnt = (ep->xfer_len - 1U + ep->maxpacket) / ep->maxpacket; + u32DeptsizTmp = (u32Xfersize << USBFS_DIEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DIEPTSIZ_PKTCNT_POS); + } + MODIFY_REG32(USBx->INEP_REGS[ep->epidx]->DIEPTSIZ, USBFS_DIEPTSIZ_XFRSIZ | USBFS_DIEPTSIZ_PKTCNT, u32DeptsizTmp); + + if (u8DmaEn == 1U) { + WRITE_REG32(USBx->INEP_REGS[ep->epidx]->DIEPDMA, ep->dma_addr); + } else { + if (ep->trans_type != EP_TYPE_ISOC) { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) { + SET_REG32_BIT(USBx->DREGS->DIEPEMPMSK, 1UL << ep->epidx); + } + } + } + + if (ep->trans_type == EP_TYPE_ISOC) { + if (((READ_REG32(USBx->DREGS->DSTS) >> USBFS_DSTS_FNSOF_POS) & 0x1U) == 0U) { + u32depctl |= USBFS_DIEPCTL_SODDFRM; + } else { + u32depctl |= USBFS_DIEPCTL_SD0PID_SEVNFRM; + } + } + + u32depctl |= (USBFS_DIEPCTL_CNAK | USBFS_DIEPCTL_EPENA); + WRITE_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL, u32depctl); + + if (ep->trans_type == EP_TYPE_ISOC) { + usb_wrpkt(USBx, ep->xfer_buff, ep->epidx, (uint16_t)ep->xfer_len, u8DmaEn); + } + } else { + u32depctl = READ_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL); + /* Program the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + if (ep->xfer_len == 0U) { + u32Xfersize = ep->maxpacket; + u32Pktcnt = 1UL; + u32DeptsizTmp = (u32Xfersize << USBFS_DOEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DOEPTSIZ_PKTCNT_POS); + } else { + u32Pktcnt = (ep->xfer_len + (ep->maxpacket - 1U)) / ep->maxpacket; + u32Xfersize = u32Pktcnt * ep->maxpacket; + u32DeptsizTmp = (u32Xfersize << USBFS_DOEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DOEPTSIZ_PKTCNT_POS); + ep->xfer_len = u32Xfersize; + } + MODIFY_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPTSIZ, USBFS_DOEPTSIZ_XFRSIZ | USBFS_DOEPTSIZ_PKTCNT, u32DeptsizTmp); + + if (u8DmaEn == 1U) { + WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPDMA, ep->dma_addr); + } + + if (ep->trans_type == EP_TYPE_ISOC) { + if (0U != ep->datax_pid) { + u32depctl |= USBFS_DOEPCTL_SD1PID; + } else { + u32depctl |= USBFS_DOEPCTL_SD0PID; + } + } + u32depctl |= (USBFS_DOEPCTL_CNAK | USBFS_DOEPCTL_EPENA); + WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL, u32depctl); + } +} + +/** + * @brief Setup the data into the EP0 and begin to transmit data. + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @param [in] u8DmaEn USB DMA status + * @retval None + */ +void usb_ep0transbegin(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint8_t u8DmaEn) +{ + uint32_t u32depctl; + uint32_t u32DeptsizTmp; + uint32_t u32Pktcnt; + uint32_t u32Xfersize; + + if (ep->ep_dir == 1U) { + u32depctl = READ_REG32(USBx->INEP_REGS[0]->DIEPCTL); + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) { + u32Xfersize = 0UL; + u32Pktcnt = 1UL; + u32DeptsizTmp = (u32Xfersize << USBFS_DIEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DIEPTSIZ_PKTCNT_POS); + } else { + if (ep->xfer_len > ep->maxpacket) { + ep->xfer_len = ep->maxpacket; + u32Xfersize = ep->maxpacket; + } else { + u32Xfersize = ep->xfer_len; + } + u32Pktcnt = 1UL; + u32DeptsizTmp = (u32Xfersize << USBFS_DIEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DIEPTSIZ_PKTCNT_POS); + } + MODIFY_REG32(USBx->INEP_REGS[0]->DIEPTSIZ, USBFS_DIEPTSIZ_XFRSIZ | USBFS_DIEPTSIZ_PKTCNT, u32DeptsizTmp); + + if (u8DmaEn == 1U) { + WRITE_REG32(USBx->INEP_REGS[ep->epidx]->DIEPDMA, ep->dma_addr); + } + + u32depctl |= (USBFS_DIEPCTL_CNAK | USBFS_DIEPCTL_EPENA); + WRITE_REG32(USBx->INEP_REGS[0]->DIEPCTL, u32depctl); + + if (u8DmaEn == 0U) { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) { + SET_REG32_BIT(USBx->DREGS->DIEPEMPMSK, 1UL << ep->epidx); + } + } + } else { + u32depctl = READ_REG32(USBx->OUTEP_REGS[0]->DOEPCTL); + /* Program the transfer size and packet count as follows: + * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) + * pktcnt = N */ + if (ep->xfer_len == 0U) { + u32Xfersize = 0UL; + u32Pktcnt = 1UL; + } else { + ep->xfer_len = LL_MIN(ep->rem_data_len, ep->maxpacket); + u32Xfersize = ep->xfer_len; + u32Pktcnt = 1UL; + } + u32DeptsizTmp = (u32Xfersize << USBFS_DOEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DOEPTSIZ_PKTCNT_POS); + MODIFY_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPTSIZ, USBFS_DOEPTSIZ_XFRSIZ | USBFS_DOEPTSIZ_PKTCNT, u32DeptsizTmp); + + if (u8DmaEn == 1U) { + WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPDMA, ep->dma_addr); + } + u32depctl |= (USBFS_DOEPCTL_CNAK | USBFS_DOEPCTL_EPENA); + WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL, u32depctl); + } +} + +/** + * @brief Set the EP to be stall status + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @retval None + */ +void usb_setepstall(LL_USB_TypeDef *USBx, USB_DEV_EP *ep) +{ + uint32_t u32depctl; + + if (ep->ep_dir == 1U) { + u32depctl = READ_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL); + if (0UL != (u32depctl & USBFS_DIEPCTL_EPENA)) { + u32depctl |= USBFS_DIEPCTL_EPDIS; + } + u32depctl |= USBFS_DIEPCTL_STALL; + WRITE_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL, u32depctl); + } else { + u32depctl = READ_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL); + u32depctl |= USBFS_DOEPCTL_STALL; + WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL, u32depctl); + } +} + +/** + * @brief clear the stall status of a EP + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @retval None + */ +void usb_clearepstall(LL_USB_TypeDef *USBx, USB_DEV_EP *ep) +{ + uint32_t tmp_depctl_addr; + uint32_t u32depctl; + if (ep->ep_dir == 1U) { + tmp_depctl_addr = (uint32_t)(&(USBx->INEP_REGS[ep->epidx]->DIEPCTL)); + } else { + tmp_depctl_addr = (uint32_t)(&(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL)); + } + u32depctl = READ_REG32(*(__IO uint32_t *)tmp_depctl_addr); + + u32depctl &= (~USBFS_DIEPCTL_STALL); + if ((ep->trans_type == EP_TYPE_INTR) || (ep->trans_type == EP_TYPE_BULK)) { + u32depctl |= USBFS_DIEPCTL_SD0PID_SEVNFRM; + } + + WRITE_REG32(*(__IO uint32_t *)tmp_depctl_addr, u32depctl); +} + +/** + * @brief configure the EPO to receive data packets + * @param [in] USBx usb instance + * @param [in] u8DmaEn USB DMA status + * @retval None + */ +void usb_ep0revcfg(LL_USB_TypeDef *USBx, uint8_t u8DmaEn, uint8_t *u8RevBuf) +{ + uint32_t u32deptsize; + uint32_t u32doepctl; + + u32deptsize = (3UL << USBFS_DOEPTSIZ0_STUPCNT_POS) + | (1UL << USBFS_DOEPTSIZ0_PKTCNT_POS) + | (64UL << USBFS_DOEPTSIZ0_XFRSIZ_POS); + + WRITE_REG32(USBx->OUTEP_REGS[0]->DOEPTSIZ, u32deptsize); + + if (u8DmaEn == 1U) { + WRITE_REG32(USBx->OUTEP_REGS[0]->DOEPDMA, (uint32_t)&u8RevBuf[0]); + u32doepctl = READ_REG32(USBx->OUTEP_REGS[0]->DOEPCTL); + u32doepctl |= (USBFS_DOEPCTL_EPENA | USBFS_DOEPCTL_USBAEP); + WRITE_REG32(USBx->OUTEP_REGS[0]->DOEPCTL, u32doepctl); + } +} + +/** + * @brief enable remote wakeup active + * @param [in] USBx usb instance + * @retval None + */ +void usb_remotewakeupen(LL_USB_TypeDef *USBx) +{ + uint32_t u32dsts; + + u32dsts = READ_REG32(USBx->DREGS->DSTS); + if (0UL != (u32dsts & USBFS_DSTS_SUSPSTS)) { + /* un-gate USB Core clock */ + CLR_REG32_BIT(*USBx->GCCTL, USBFS_GCCTL_GATEHCLK | USBFS_GCCTL_STPPCLK); + } + + SET_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_RWUSIG); + hdl_delay_ms(5UL); + CLR_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_RWUSIG); +} + +/** + * @brief control the device to connect or disconnect + * @param [in] USBx usb instance + * @param [in] link 0(conn) or 1(disconn) + * @retval None + */ +void usb_ctrldevconnect(LL_USB_TypeDef *USBx, uint8_t link) +{ + if (0U == link) { + CLR_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_SDIS); + } else { + SET_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_SDIS); + } + hdl_delay_ms(3UL); +} +#endif + +#ifdef USE_HOST_MODE +/** + * @brief Initializes the USB controller when it is host mode + * @param [in] USBx usb instance + * @param [in] basic_cfgs usb core basic cfgs + * @retval None + */ +void usb_hostmodeinit(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs) +{ + __IO uint8_t u8Tmp = 0U; + WRITE_REG32(*USBx->GCCTL, 0UL); /* reset the register-GCCTL */ + if (USBHS_PHY_EMBED == basic_cfgs->phy_type) { + usb_fslspclkselset(USBx, HCFG_6_MHZ); /* PHY clock is running at 6MHz */ + } else { + usb_fslspclkselset(USBx, HCFG_30_60_MHZ); /* PHY clock is running at 6MHz */ + } + usb_hprtrst(USBx); /* reset the port */ + usb_enumspeed(USBx); /* FS or LS bases on the maximum speed supported by the connected device */ + usb_sethostfifo(USBx, basic_cfgs->core_type); + /* Flush all the txFIFO and the whole rxFIFO */ + usb_txfifoflush(USBx, 0x10UL); + usb_rxfifoflush(USBx); + /* Clear all HC Interrupt bits that are pending */ + while (u8Tmp < basic_cfgs->host_chnum) { + WRITE_REG32(USBx->HC_REGS[u8Tmp]->HCINT, 0xFFFFFFFFUL); + WRITE_REG32(USBx->HC_REGS[u8Tmp]->HCINTMSK, 0UL); + u8Tmp++; + } + usb_hostinten(USBx, basic_cfgs->dmaen); +} + +/** + * @brief set the vbus if state is 1 or reset the vbus if state is 0. + * @param [in] USBx usb instance + * @param [in] u8State the vbus state it would be. + * @retval None + */ +void usb_vbusctrl(LL_USB_TypeDef *USBx, uint8_t u8State) +{ + uint32_t u32hprt; + + u32hprt = usb_rdhprt(USBx); + if ((0UL == (u32hprt & USBFS_HPRT_PWPR)) && (1U == u8State)) { + u32hprt |= USBFS_HPRT_PWPR; + WRITE_REG32(*USBx->HPRT, u32hprt); + } + if ((0UL != (u32hprt & USBFS_HPRT_PWPR)) && (0U == u8State)) { + u32hprt &= (~USBFS_HPRT_PWPR); + WRITE_REG32(*USBx->HPRT, u32hprt); + } +} + +/** + * @brief Enables the related interrupts when the core is host mode + * @param [in] USBx usb instance + * @param [in] u8DmaEn USB DMA status + * @retval None + */ +void usb_hostinten(LL_USB_TypeDef *USBx, uint8_t u8DmaEn) +{ + uint32_t u32gIntmsk = 0UL; + WRITE_REG32(USBx->GREGS->GINTMSK, 0UL); + /* Clear the pending interrupt bits */ + WRITE_REG32(USBx->GREGS->GINTSTS, 0xFFFFFFFFUL); + + /* Enable the normal interrupt bits */ + usb_normalinten(USBx); + + if (u8DmaEn == 0U) { + u32gIntmsk |= USBFS_GINTMSK_RXFNEM; + } + u32gIntmsk |= (USBFS_GINTMSK_HPRTIM + | USBFS_GINTMSK_HCIM + | USBFS_GINTMSK_DISCIM + | USBFS_GINTMSK_SOFM + | USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM); + SET_REG32_BIT(USBx->GREGS->GINTMSK, u32gIntmsk); +} + +/** + * @brief Reset the port, the 1'b0 state must last at lease 10ms. + * @param [in] USBx usb instance + * @retval None + */ +void usb_hprtrst(LL_USB_TypeDef *USBx) +{ + uint32_t u32hprt; + u32hprt = usb_rdhprt(USBx); + u32hprt |= USBFS_HPRT_PRST; + WRITE_REG32(*USBx->HPRT, u32hprt); + hdl_delay_ms(10UL); + u32hprt &= ~USBFS_HPRT_PRST; + WRITE_REG32(*USBx->HPRT, u32hprt); + hdl_delay_ms(20UL); +} + +/** + * @brief Prepares transferring packets on a host channel + * @param [in] USBx usb instance + * @param [in] hc_num channel index + * @param [in] pCh channel structure + * @param [in] u8DmaEn USB DMA status + * @retval status in byte + */ +uint8_t usb_inithch(LL_USB_TypeDef *USBx, uint8_t hc_num, USB_HOST_CH *pCh, uint8_t u8DmaEn) +{ + uint32_t u32hcintmsk = 0UL; + uint32_t u32hcchar = 0UL; + + WRITE_REG32(USBx->HC_REGS[hc_num]->HCINT, 0xFFFFFFFFUL); + switch (pCh->ep_type) { + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + u32hcintmsk |= (USBFS_HCINTMSK_XFRCM + | USBFS_HCINTMSK_STALLM + | USBFS_HCINTMSK_TXERRM + | USBFS_HCINTMSK_DTERRM + | USBFS_HCINTMSK_NAKM); + if (0U != pCh->is_epin) { + u32hcintmsk |= USBFS_HCINTMSK_BBERRM; + } else { + if (0U != pCh->do_ping) { + u32hcintmsk |= USBFS_HCINTMSK_ACKM; + } + } + break; + case EP_TYPE_INTR: + u32hcintmsk |= (USBFS_HCINTMSK_XFRCM + | USBFS_HCINTMSK_NAKM + | USBFS_HCINTMSK_STALLM + | USBFS_HCINTMSK_TXERRM + | USBFS_HCINTMSK_DTERRM + | USBFS_HCINTMSK_FRMORM); + if (0U != pCh->is_epin) { + u32hcintmsk |= USBFS_HCINTMSK_BBERRM; + } + break; + case EP_TYPE_ISOC: + u32hcintmsk |= (USBFS_HCINTMSK_XFRCM + | USBFS_HCINTMSK_FRMORM + | USBFS_HCINTMSK_ACKM); + + if (0U != pCh->is_epin) { + u32hcintmsk |= (USBFS_HCINTMSK_TXERRM | USBFS_HCINTMSK_BBERRM); + } + break; + default: + break; + } + + WRITE_REG32(USBx->HC_REGS[hc_num]->HCINTMSK, u32hcintmsk); + SET_REG32_BIT(USBx->HREGS->HAINTMSK, 1UL << hc_num); + + /* enable the host channel interrupts */ + SET_REG32_BIT(USBx->GREGS->GINTMSK, USBFS_GINTMSK_HCIM); + + /* modify HCCHAR */ + u32hcchar |= (((uint32_t)pCh->dev_addr) << USBFS_HCCHAR_DAD_POS); + u32hcchar |= (((uint32_t)pCh->ep_idx) << USBFS_HCCHAR_EPNUM_POS); + u32hcchar |= (((uint32_t)pCh->is_epin) << USBFS_HCCHAR_EPDIR_POS); + u32hcchar |= (((uint32_t)pCh->ep_type) << USBFS_HCCHAR_EPTYP_POS); + u32hcchar |= (((uint32_t)pCh->max_packet) << USBFS_HCCHAR_MPSIZ_POS); + if (PRTSPD_LOW_SPEED == pCh->ch_speed) { + u32hcchar |= USBFS_HCCHAR_LSDEV; + } else { + u32hcchar &= ~USBFS_HCCHAR_LSDEV; + } + + if (pCh->ep_type == EP_TYPE_INTR) { + u32hcchar |= USBFS_HCCHAR_ODDFRM; + } + WRITE_REG32(USBx->HC_REGS[hc_num]->HCCHAR, u32hcchar); + return USB_OK; +} + +/** + * @brief Start transfer on the channel whose index is hc_num. + * @param [in] USBx usb instance + * @param [in] hc_num channel index + * @param [in] pCh channel structure + * @param [in] u8DmaEn USB DMA status + * @retval status in 8 bits + */ +uint8_t usb_hchtransbegin(LL_USB_TypeDef *USBx, uint8_t hc_num, USB_HOST_CH *pCh, uint8_t u8DmaEn) +{ + uint32_t u32hcchar; + uint32_t u32hctsiz = 0UL; + uint32_t u32hnptxsts; + uint32_t u32hptxsts; + uint16_t u16LenWords; + uint16_t u16NumPacket; + uint16_t u16MaxHcPktCount = 256U; + + /* Compute the expected number of packets associated to the transfer */ + if (pCh->xfer_len > 0U) { + u16NumPacket = (uint16_t)((pCh->xfer_len + + (uint32_t)pCh->max_packet - 1UL) / (uint32_t)pCh->max_packet); + + if (u16NumPacket > u16MaxHcPktCount) { + u16NumPacket = u16MaxHcPktCount; + pCh->xfer_len = (uint32_t)u16NumPacket * (uint32_t)pCh->max_packet; + } + } else { + u16NumPacket = 1U; + } + if (0U != pCh->is_epin) { + pCh->xfer_len = (uint32_t)u16NumPacket * (uint32_t)pCh->max_packet; + } + + u32hctsiz |= (((uint32_t)pCh->xfer_len) << USBFS_HCTSIZ_XFRSIZ_POS); + u32hctsiz |= (((uint32_t)u16NumPacket) << USBFS_HCTSIZ_PKTCNT_POS); + u32hctsiz |= (((uint32_t)pCh->pid_type) << USBFS_HCTSIZ_DPID_POS); + WRITE_REG32(USBx->HC_REGS[hc_num]->HCTSIZ, u32hctsiz); + + if (u8DmaEn == 1U) { + WRITE_REG32(USBx->HC_REGS[hc_num]->HCDMA, pCh->xfer_buff); + } + + u32hcchar = READ_REG32(USBx->HC_REGS[hc_num]->HCCHAR); + u32hcchar &= ~USBFS_HCCHAR_ODDFRM; + u32hcchar |= (usb_ifevenframe(USBx) << USBFS_HCCHAR_ODDFRM_POS); + + /* enable this host channel whose number is hc_num */ + u32hcchar |= USBFS_HCCHAR_CHENA; + u32hcchar &= ~USBFS_HCCHAR_CHDIS; + WRITE_REG32(USBx->HC_REGS[hc_num]->HCCHAR, u32hcchar); + + if (u8DmaEn == 0U) { + if ((pCh->is_epin == 0U) && (pCh->xfer_len > 0U)) { + switch (pCh->ep_type) { + /* Non-periodic transmit */ + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + u32hnptxsts = READ_REG32(USBx->GREGS->HNPTXSTS); + u16LenWords = (uint16_t)((pCh->xfer_len + 3UL) / 4UL); + /* check if the amount of free space available in the non-periodic txFIFO is enough */ + if (u16LenWords > ((u32hnptxsts & USBFS_HNPTXSTS_NPTXFSAV) >> USBFS_HNPTXSTS_NPTXFSAV_POS)) { + /* enable interrrupt of nptxfempty of GINTMSK*/ + SET_REG32_BIT(USBx->GREGS->GINTMSK, USBFS_GINTMSK_NPTXFEM); + } + break; + /* Periodic trnsmit */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + u32hptxsts = READ_REG32(USBx->HREGS->HPTXSTS); + u16LenWords = (uint16_t)((pCh->xfer_len + 3UL) / 4UL); + /* check if the space of periodic TxFIFO is enough */ + if (u16LenWords > ((u32hptxsts & USBFS_HPTXSTS_PTXFSAVL) >> USBFS_HPTXSTS_PTXFSAVL_POS)) { + /* enable interrrupt of ptxfempty of GINTMSK */ + SET_REG32_BIT(USBx->GREGS->GINTMSK, USBFS_GINTMSK_PTXFEM); + } + break; + default: + break; + } + + usb_wrpkt(USBx, pCh->xfer_buff, hc_num, (uint16_t)pCh->xfer_len, u8DmaEn); + } + } + return USB_OK; +} + +/** + * @brief Stop the host and flush all the txFIFOs and the whole rxFIFO. + * @param [in] USBx usb instance + * @param [in] u8ChNum Host channel number + * @retval None + */ +void usb_hoststop(LL_USB_TypeDef *USBx, uint8_t u8ChNum) +{ + __IO uint32_t u32Tmp = 0UL; + + WRITE_REG32(USBx->HREGS->HAINTMSK, 0UL); + WRITE_REG32(USBx->HREGS->HAINT, 0xFFFFFFFFUL); + + do { + usb_chrst(USBx, (uint8_t)u32Tmp); + u32Tmp++; + } while (u32Tmp < u8ChNum); + /* flush all the txFIFOs and the whole rxFIFO */ + usb_rxfifoflush(USBx); + usb_txfifoflush(USBx, 0x10UL); +} + +/** + * @brief make the channel to halt + * @param [in] USBx usb instance + * @param [in] hc_num channel index + * @retval None + */ +void usb_hchstop(LL_USB_TypeDef *USBx, uint8_t hc_num) +{ + uint32_t u32hcchar; + + u32hcchar = READ_REG32(USBx->HC_REGS[hc_num]->HCCHAR); + u32hcchar |= USBFS_HCCHAR_CHDIS; + /* Check for space in the request queue to issue the halt. */ + if ((EP_TYPE_CTRL == ((u32hcchar & USBFS_HCCHAR_EPTYP) >> USBFS_HCCHAR_EPTYP_POS)) + || (EP_TYPE_BULK == ((u32hcchar & USBFS_HCCHAR_EPTYP) >> USBFS_HCCHAR_EPTYP_POS))) { + if (0UL == (READ_REG32(USBx->GREGS->HNPTXSTS) & USBFS_HNPTXSTS_NPTQXSAV)) { + u32hcchar &= (~USBFS_HCCHAR_CHENA); + WRITE_REG32(USBx->HC_REGS[hc_num]->HCCHAR, u32hcchar); + } + } else { + if (0UL == (READ_REG32(USBx->HREGS->HPTXSTS) & USBFS_HPTXSTS_PTXQSAV)) { + u32hcchar &= (~USBFS_HCCHAR_CHENA); + WRITE_REG32(USBx->HC_REGS[hc_num]->HCCHAR, u32hcchar); + } + } + u32hcchar |= USBFS_HCCHAR_CHENA; + WRITE_REG32(USBx->HC_REGS[hc_num]->HCCHAR, u32hcchar); +} + +#endif + +/** + * @} +*/ + +#endif /* LL_USB_ENABLE */ + +/** + * @} +*/ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_utility.c b/mcu/lib/src/hc32_ll_utility.c new file mode 100644 index 0000000..371c453 --- /dev/null +++ b/mcu/lib/src/hc32_ll_utility.c @@ -0,0 +1,440 @@ +/** + ******************************************************************************* + * @file hc32_ll_utility.c + * @brief This file provides utility functions for DDL. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Support re-target printf for IAR EW version 9 or later + 2023-06-30 CDT Modify register USART DR to USART TDR + Prohibit DDL_DelayMS and DDL_DelayUS functions from being optimized + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_UTILITY UTILITY + * @brief DDL Utility Driver + * @{ + */ + +#if (LL_UTILITY_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup UTILITY_Local_Variables UTILITY Local Variables + * @{ + */ + +static uint32_t m_u32TickStep = 0UL; +static __IO uint32_t m_u32TickCount = 0UL; + +#if (LL_PRINT_ENABLE == DDL_ON) +static void *m_pvPrintDevice = NULL; +static uint32_t m_u32PrintTimeout = 0UL; +#endif + +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup UTILITY_Local_Functions UTILITY Local Functions + * @{ + */ +#if (LL_PRINT_ENABLE == DDL_ON) + +/** + * @brief Set print device. + * @param [in] pvPrintDevice Pointer to print device + * @retval None + */ +__STATIC_INLINE void LL_SetPrintDevice(void *pvPrintDevice) +{ + m_pvPrintDevice = pvPrintDevice; +} + +/** + * @brief Get print device. + * @param None + * @retval Pointer to print device + */ +__STATIC_INLINE void *LL_GetPrintDevice(void) +{ + return m_pvPrintDevice; +} + +/** + * @brief Set print timeout. + * @param [in] u32Timeout Print timeout value + * @retval None + */ +__STATIC_INLINE void LL_SetPrintTimeout(uint32_t u32Timeout) +{ + m_u32PrintTimeout = u32Timeout; +} + +/** + * @brief Get print timeout. + * @param None + * @retval Print timeout value + */ +__STATIC_INLINE uint32_t LL_GetPrintTimeout(void) +{ + return m_u32PrintTimeout; +} +#endif /* LL_PRINT_ENABLE */ + +/** + * @} + */ + +/** + * @defgroup UTILITY_Global_Functions UTILITY Global Functions + * @{ + */ + +/** + * @brief Delay function, delay ms approximately + * @param [in] u32Count ms + * @retval None + */ +#if defined (__CC_ARM) /*!< ARM Compiler */ +#pragma push +#pragma O0 +#endif +__NO_OPTIMIZE void DDL_DelayMS(uint32_t u32Count) +{ + __IO uint32_t i; + const uint32_t u32Cyc = (HCLK_VALUE + 10000UL - 1UL) / 10000UL; + + while (u32Count-- > 0UL) { + i = u32Cyc; + while (i-- > 0UL) { + } + } +} + +/** + * @brief Delay function, delay us approximately + * @param [in] u32Count us + * @retval None + */ +__NO_OPTIMIZE void DDL_DelayUS(uint32_t u32Count) +{ + __IO uint32_t i; + const uint32_t u32Cyc = (HCLK_VALUE + 10000000UL - 1UL) / 10000000UL; + + while (u32Count-- > 0UL) { + i = u32Cyc; + while (i-- > 0UL) { + } + } +} +#if defined (__CC_ARM) /*!< ARM Compiler */ +#pragma pop +#endif + +/** + * @brief This function Initializes the interrupt frequency of the SysTick. + * @param [in] u32Freq SysTick interrupt frequency (1 to 1000). + * @retval int32_t: + * - LL_OK: SysTick Initializes succeed + * - LL_ERR: SysTick Initializes failed + */ +__WEAKDEF int32_t SysTick_Init(uint32_t u32Freq) +{ + int32_t i32Ret = LL_ERR; + + if ((0UL != u32Freq) && (u32Freq <= 1000UL)) { + m_u32TickStep = 1000UL / u32Freq; + /* Configure the SysTick interrupt */ + if (0UL == SysTick_Config(HCLK_VALUE / u32Freq)) { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief This function provides minimum delay (in milliseconds). + * @param [in] u32Delay Delay specifies the delay time. + * @retval None + */ +__WEAKDEF void SysTick_Delay(uint32_t u32Delay) +{ + const uint32_t tickStart = SysTick_GetTick(); + uint32_t tickEnd = u32Delay; + uint32_t tickMax; + + if (m_u32TickStep != 0UL) { + tickMax = 0xFFFFFFFFUL / m_u32TickStep * m_u32TickStep; + /* Add a freq to guarantee minimum wait */ + if ((u32Delay >= tickMax) || ((tickMax - u32Delay) < m_u32TickStep)) { + tickEnd = tickMax; + } + while ((SysTick_GetTick() - tickStart) < tickEnd) { + } + } +} + +/** + * @brief This function is called to increment a global variable "u32TickCount". + * @note This variable is incremented in SysTick ISR. + * @param None + * @retval None + */ +__WEAKDEF void SysTick_IncTick(void) +{ + m_u32TickCount += m_u32TickStep; +} + +/** + * @brief Provides a tick value in millisecond. + * @param None + * @retval Tick value + */ +__WEAKDEF uint32_t SysTick_GetTick(void) +{ + return m_u32TickCount; +} + +/** + * @brief Suspend SysTick increment. + * @param None + * @retval None + */ +__WEAKDEF void SysTick_Suspend(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Resume SysTick increment. + * @param None + * @retval None + */ +__WEAKDEF void SysTick_Resume(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +#ifdef __DEBUG +/** + * @brief DDL assert error handle function + * @param [in] file Point to the current assert the wrong file. + * @param [in] line Point line assert the wrong file in the current. + * @retval None + */ +__WEAKDEF void DDL_AssertHandler(const char *file, int line) +{ + /* Users can re-implement this function to print information */ + DDL_Printf("Wrong parameters value: file %s on line %d\r\n", file, line); + + for (;;) { + } +} +#endif /* __DEBUG */ + +#if (LL_PRINT_ENABLE == DDL_ON) + +#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \ + (defined (__ICCARM__) && (__VER__ < 9000000)) || (defined (__CC_ARM)) +/** + * @brief Re-target fputc function. + * @param [in] ch + * @param [in] f + * @retval int32_t + */ +int32_t fputc(int32_t ch, FILE *f) +{ + (void)f; /* Prevent unused argument compilation warning */ + + return (LL_OK == DDL_ConsoleOutputChar((char)ch)) ? ch : -1; +} + +#elif (defined (__ICCARM__) && (__VER__ >= 9000000)) +#include +#pragma module_name = "?__write" +size_t __dwrite(int handle, const unsigned char *buffer, size_t size) +{ + size_t nChars = 0; + size_t i; + + if (buffer == NULL) { + /* + * This means that we should flush internal buffers. Since we + * don't we just return. (Remember, "handle" == -1 means that all + * handles should be flushed.) + */ + return 0; + } + + /* This template only writes to "standard out" and "standard err", + * for all other file handles it returns failure. */ + if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) { + return _LLIO_ERROR; + } + + for (i = 0; i < size; i++) { + if (DDL_ConsoleOutputChar((char)buffer[i]) < 0) { + return _LLIO_ERROR; + } + + ++nChars; + } + + return nChars; +} + +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) +/** + * @brief Re-target _write function. + * @param [in] fd + * @param [in] data + * @param [in] size + * @retval int32_t + */ +int32_t _write(int fd, char data[], int32_t size) +{ + int32_t i = -1; + + if (NULL != data) { + (void)fd; /* Prevent unused argument compilation warning */ + + for (i = 0; i < size; i++) { + if (LL_OK != DDL_ConsoleOutputChar(data[i])) { + break; + } + } + } + + return i ? i : -1; +} +#endif + +/** + * @brief Initialize printf function + * @param [in] vpDevice Pointer to print device + * @param [in] u32Param Print device parameter + * @param [in] pfnPreinit The function pointer for initializing clock, port, print device etc. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR: The callback function pfnPreinit occurs error. + * - LL_ERR_INVD_PARAM: The pointer pfnPreinit is NULL. + */ +int32_t LL_PrintfInit(void *vpDevice, uint32_t u32Param, int32_t (*pfnPreinit)(void *vpDevice, uint32_t u32Param)) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pfnPreinit) { + i32Ret = pfnPreinit(vpDevice, u32Param); /* The callback function initialize clock, port, print device etc */ + if (LL_OK == i32Ret) { + LL_SetPrintDevice(vpDevice); + LL_SetPrintTimeout((u32Param == 0UL) ? 0UL : (HCLK_VALUE / u32Param)); + } else { + i32Ret = LL_ERR; + DDL_ASSERT(i32Ret == LL_OK); /* Initialize unsuccessfully */ + } + } + + return i32Ret; +} + +/** + * @brief Transmit character. + * @param [in] cData The character for transmitting + * @retval int32_t: + * - LL_OK: Transmit successfully. + * - LL_ERR_TIMEOUT: Transmit timeout. + * - LL_ERR_INVD_PARAM: The print device is invalid. + */ +__WEAKDEF int32_t DDL_ConsoleOutputChar(char cData) +{ + uint32_t u32TxEmpty = 0UL; + __IO uint32_t u32TmpCount = 0UL; + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32Timeout = LL_GetPrintTimeout(); + CM_USART_TypeDef *USARTx = (CM_USART_TypeDef *)LL_GetPrintDevice(); + + if (NULL != USARTx) { + /* Wait TX data register empty */ + while ((u32TmpCount <= u32Timeout) && (0UL == u32TxEmpty)) { + u32TxEmpty = READ_REG32_BIT(USARTx->SR, USART_SR_TXE); + u32TmpCount++; + } + + if (0UL != u32TxEmpty) { + WRITE_REG16(USARTx->TDR, (uint16_t)cData); + i32Ret = LL_OK; + } else { + i32Ret = LL_ERR_TIMEOUT; + } + } + + return i32Ret; +} + +#endif /* LL_PRINT_ENABLE */ + +/** + * @} + */ + +#endif /* LL_UTILITY_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/mcu/lib/src/hc32_ll_wdt.c b/mcu/lib/src/hc32_ll_wdt.c new file mode 100644 index 0000000..0103022 --- /dev/null +++ b/mcu/lib/src/hc32_ll_wdt.c @@ -0,0 +1,257 @@ +/** + ******************************************************************************* + * @file hc32_ll_wdt.c + * @brief This file provides firmware functions to manage the General Watch Dog + * Timer(WDT). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-09-30 CDT Optimize WDT_ClearStatus function timeout + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_wdt.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_WDT WDT + * @brief General Watch Dog Timer + * @{ + */ + +#if (LL_WDT_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup WDT_Local_Macros WDT Local Macros + * @{ + */ + +/* WDT Refresh Key */ +#define WDT_REFRESH_KEY_START (0x0123UL) +#define WDT_REFRESH_KEY_END (0x3210UL) + +/* WDT clear flag timeout(ms) */ +#define WDT_CLR_FLAG_TIMEOUT (60000UL) + +/* WDT Registers Clear Mask */ +#define WDT_CR_CLR_MASK (WDT_CR_PERI | WDT_CR_CKS | WDT_CR_WDPT | \ + WDT_CR_SLPOFF | WDT_CR_ITS) + +/** + * @defgroup WDT_Check_Parameters_Validity WDT Check Parameters Validity + * @{ + */ +#define IS_WDT_CNT_PERIOD(x) \ +( ((x) == WDT_CNT_PERIOD256) || \ + ((x) == WDT_CNT_PERIOD4096) || \ + ((x) == WDT_CNT_PERIOD16384) || \ + ((x) == WDT_CNT_PERIOD65536)) + +#define IS_WDT_CLK_DIV(x) \ +( ((x) == WDT_CLK_DIV4) || \ + ((x) == WDT_CLK_DIV64) || \ + ((x) == WDT_CLK_DIV128) || \ + ((x) == WDT_CLK_DIV256) || \ + ((x) == WDT_CLK_DIV512) || \ + ((x) == WDT_CLK_DIV1024) || \ + ((x) == WDT_CLK_DIV2048) || \ + ((x) == WDT_CLK_DIV8192)) + +#define IS_WDT_REFRESH_RANGE(x) \ +( ((x) == WDT_RANGE_0TO100PCT) || \ + ((x) == WDT_RANGE_0TO25PCT) || \ + ((x) == WDT_RANGE_25TO50PCT) || \ + ((x) == WDT_RANGE_0TO50PCT) || \ + ((x) == WDT_RANGE_50TO75PCT) || \ + ((x) == WDT_RANGE_0TO25PCT_50TO75PCT) || \ + ((x) == WDT_RANGE_25TO75PCT) || \ + ((x) == WDT_RANGE_0TO75PCT) || \ + ((x) == WDT_RANGE_75TO100PCT) || \ + ((x) == WDT_RANGE_0TO25PCT_75TO100PCT) || \ + ((x) == WDT_RANGE_25TO50PCT_75TO100PCT) || \ + ((x) == WDT_RANGE_0TO50PCT_75TO100PCT) || \ + ((x) == WDT_RANGE_50TO100PCT) || \ + ((x) == WDT_RANGE_0TO25PCT_50TO100PCT) || \ + ((x) == WDT_RANGE_25TO100PCT)) + +#define IS_WDT_LPM_CNT(x) \ +( ((x) == WDT_LPM_CNT_CONTINUE) || \ + ((x) == WDT_LPM_CNT_STOP)) + +#define IS_WDT_EXP_TYPE(x) \ +( ((x) == WDT_EXP_TYPE_INT) || \ + ((x) == WDT_EXP_TYPE_RST)) + +#define IS_WDT_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | WDT_FLAG_ALL) == WDT_FLAG_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup WDT_Global_Functions WDT Global Functions + * @{ + */ + +/** + * @brief Initializes WDT. + * @param [in] pstcWdtInit Pointer to a @ref stc_wdt_init_t structure + * @retval int32_t: + * - LL_OK: Initializes success + * - LL_ERR_INVD_PARAM: pstcWdtInit == NULL + */ +int32_t WDT_Init(const stc_wdt_init_t *pstcWdtInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcWdtInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_WDT_CNT_PERIOD(pstcWdtInit->u32CountPeriod)); + DDL_ASSERT(IS_WDT_CLK_DIV(pstcWdtInit->u32ClockDiv)); + DDL_ASSERT(IS_WDT_REFRESH_RANGE(pstcWdtInit->u32RefreshRange)); + DDL_ASSERT(IS_WDT_LPM_CNT(pstcWdtInit->u32LPMCount)); + DDL_ASSERT(IS_WDT_EXP_TYPE(pstcWdtInit->u32ExceptionType)); + + /* WDT CR Configuration(Software Start Mode) */ + MODIFY_REG32(CM_WDT->CR, WDT_CR_CLR_MASK, + (pstcWdtInit->u32CountPeriod | pstcWdtInit->u32ClockDiv | + pstcWdtInit->u32RefreshRange | pstcWdtInit->u32LPMCount | + pstcWdtInit->u32ExceptionType)); + } + + return i32Ret; +} + +/** + * @brief WDT feed dog. + * @note In software startup mode, Start counter when refreshing for the first time. + * @param None + * @retval None + */ +void WDT_FeedDog(void) +{ + WRITE_REG32(CM_WDT->RR, WDT_REFRESH_KEY_START); + WRITE_REG32(CM_WDT->RR, WDT_REFRESH_KEY_END); +} + +/** + * @brief Get WDT flag status. + * @param [in] u32Flag WDT flag type + * This parameter can be one or any combination of the following values: + * @arg WDT_FLAG_UDF: Count underflow flag + * @arg WDT_FLAG_REFRESH: Refresh error flag + * @arg WDT_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t WDT_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_WDT_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(CM_WDT->SR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear WDT flag. + * @param [in] u32Flag WDT flag type + * This parameter can be one or any combination of the following values: + * @arg WDT_FLAG_UDF: Count underflow flag + * @arg WDT_FLAG_REFRESH: Refresh error flag + * @arg WDT_FLAG_ALL: All of the above + * @retval int32_t: + * - LL_OK: Clear flag success + * - LL_ERR_TIMEOUT: Clear flag timeout + */ +int32_t WDT_ClearStatus(uint32_t u32Flag) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* Check parameters */ + DDL_ASSERT(IS_WDT_FLAG(u32Flag)); + + /* Waiting for FLAG bit clear */ + u32Count = WDT_CLR_FLAG_TIMEOUT * (HCLK_VALUE / 25000UL); + while (0UL != READ_REG32_BIT(CM_WDT->SR, u32Flag)) { + CLR_REG32_BIT(CM_WDT->SR, u32Flag); + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_WDT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/lib/src/hc32f460_ll_interrupts_share.c b/mcu/lib/src/hc32f460_ll_interrupts_share.c new file mode 100644 index 0000000..b05daec --- /dev/null +++ b/mcu/lib/src/hc32f460_ll_interrupts_share.c @@ -0,0 +1,2260 @@ +/** + ******************************************************************************* + * @file hc32f460_ll_interrupts_share.c + * @brief This file provides firmware functions to manage the Share Interrupt + * Controller (SHARE_INTERRUPTS). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-01-15 CDT Bug fix of TMRA CMP DCU and USART, refine IRQ143 + Rename I2Cx_Error_IrqHandler as I2Cx_EE_IrqHandler + 2023-09-30 CDT IRQxxx_Handler add __DSB for Arm Errata 838869 + The BCSTR register of TimerA is split into BCSTRH and BCSTRL + Modify for head file update: EIRQFR -> EIFR + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_ll_interrupts_share.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_HC32F460_SHARE_INTERRUPTS SHARE_INTERRUPTS + * @brief Share Interrupts Driver Library + * @{ + */ + +#if (LL_INTERRUPTS_SHARE_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup Share_Interrupts_Global_Functions Share Interrupts Global Functions + * @{ + */ +/** + * @brief Share IRQ configure + * @param [in] enIntSrc: Peripheral interrupt source @ref en_int_src_t + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: Share IRQ configure successfully + */ +int32_t INTC_ShareIrqCmd(en_int_src_t enIntSrc, en_functional_state_t enNewState) +{ + __IO uint32_t *INTC_VSSELx; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + INTC_VSSELx = (__IO uint32_t *)(((uint32_t)&CM_INTC->VSSEL128) + (4U * ((uint32_t)enIntSrc / 0x20U))); + if (ENABLE == enNewState) { + SET_REG32_BIT(*INTC_VSSELx, (1UL << ((uint32_t)enIntSrc & 0x1FUL))); + } else { + CLR_REG32_BIT(*INTC_VSSELx, (1UL << ((uint32_t)enIntSrc & 0x1FUL))); + } + return LL_OK; +} + +/** + * @brief Interrupt No.128 share IRQ handler + * @param None + * @retval None + */ +void IRQ128_Handler(void) +{ + const uint32_t VSSEL128 = CM_INTC->VSSEL128; + + /* external interrupt 00 */ + if ((1UL == bCM_INTC->EIFR_b.EIFR0) && (0UL != (VSSEL128 & BIT_MASK_00))) { + EXTINT00_IrqHandler(); + } + /* external interrupt 01 */ + if ((1UL == bCM_INTC->EIFR_b.EIFR1) && (0UL != (VSSEL128 & BIT_MASK_01))) { + EXTINT01_IrqHandler(); + } + /* external interrupt 02 */ + if ((1UL == bCM_INTC->EIFR_b.EIFR2) && (0UL != (VSSEL128 & BIT_MASK_02))) { + EXTINT02_IrqHandler(); + } + /* external interrupt 03 */ + if ((1UL == bCM_INTC->EIFR_b.EIFR3) && (0UL != (VSSEL128 & BIT_MASK_03))) { + EXTINT03_IrqHandler(); + } + /* external interrupt 04 */ + if ((1UL == bCM_INTC->EIFR_b.EIFR4) && (0UL != (VSSEL128 & BIT_MASK_04))) { + EXTINT04_IrqHandler(); + } + /* external interrupt 05 */ + if ((1UL == bCM_INTC->EIFR_b.EIFR5) && (0UL != (VSSEL128 & BIT_MASK_05))) { + EXTINT05_IrqHandler(); + } + /* external interrupt 06 */ + if ((1UL == bCM_INTC->EIFR_b.EIFR6) && (0UL != (VSSEL128 & BIT_MASK_06))) { + EXTINT06_IrqHandler(); + } + /* external interrupt 07 */ + if ((1UL == bCM_INTC->EIFR_b.EIFR7) && (0UL != (VSSEL128 & BIT_MASK_07))) { + EXTINT07_IrqHandler(); + } + /* external interrupt 08 */ + if ((1UL == bCM_INTC->EIFR_b.EIFR8) && (0UL != (VSSEL128 & BIT_MASK_08))) { + EXTINT08_IrqHandler(); + } + /* external interrupt 09 */ + if ((1UL == bCM_INTC->EIFR_b.EIFR9) && (0UL != (VSSEL128 & BIT_MASK_09))) { + EXTINT09_IrqHandler(); + } + /* external interrupt 10 */ + if ((1UL == bCM_INTC->EIFR_b.EIFR10) && (0UL != (VSSEL128 & BIT_MASK_10))) { + EXTINT10_IrqHandler(); + } + /* external interrupt 11 */ + if ((1UL == bCM_INTC->EIFR_b.EIFR11) && (0UL != (VSSEL128 & BIT_MASK_11))) { + EXTINT11_IrqHandler(); + } + /* external interrupt 12 */ + if ((1UL == bCM_INTC->EIFR_b.EIFR12) && (0UL != (VSSEL128 & BIT_MASK_12))) { + EXTINT12_IrqHandler(); + } + /* external interrupt 13 */ + if ((1UL == bCM_INTC->EIFR_b.EIFR13) && (0UL != (VSSEL128 & BIT_MASK_13))) { + EXTINT13_IrqHandler(); + } + /* external interrupt 14 */ + if ((1UL == bCM_INTC->EIFR_b.EIFR14) && (0UL != (VSSEL128 & BIT_MASK_14))) { + EXTINT14_IrqHandler(); + } + /* external interrupt 15 */ + if ((1UL == bCM_INTC->EIFR_b.EIFR15) && (0UL != (VSSEL128 & BIT_MASK_15))) { + EXTINT15_IrqHandler(); + } + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.129 share IRQ handler + * @param None + * @retval None + */ +void IRQ129_Handler(void) +{ + const uint32_t VSSEL129 = CM_INTC->VSSEL129; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + + /* DMA1 Ch.0 interrupt enabled */ + if (1UL == bCM_DMA1->CHCTL0_b.IE) { + /* DMA1 Ch.0 Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKTC0) { + if ((1UL == bCM_DMA1->INTSTAT1_b.TC0) && (0UL != (VSSEL129 & BIT_MASK_00))) { + DMA1_TC0_IrqHandler(); + } + } + /* DMA1 ch.0 Block Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKBTC0) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC0) && (0UL != (VSSEL129 & BIT_MASK_08))) { + DMA1_BTC0_IrqHandler(); + } + } + /* DMA1 ch.0 Transfer/Request Error */ + u32Tmp1 = CM_DMA1->INTSTAT0 & (BIT_MASK_00 | BIT_MASK_16); + u32Tmp2 = (uint32_t)(~(CM_DMA1->INTMASK0) & (BIT_MASK_00 | BIT_MASK_16)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) { + DMA1_Error0_IrqHandler(); + } + } + /* DMA1 Ch.1 interrupt enabled */ + if (1UL == bCM_DMA1->CHCTL1_b.IE) { + /* DMA1 Ch.1 Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKTC1) { + if ((1UL == bCM_DMA1->INTSTAT1_b.TC1) && (0UL != (VSSEL129 & BIT_MASK_01))) { + DMA1_TC1_IrqHandler(); + } + } + /* DMA1 ch.1 Block Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKBTC1) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC1) && (0UL != (VSSEL129 & BIT_MASK_09))) { + DMA1_BTC1_IrqHandler(); + } + } + /* DMA1 ch.1 Transfer/Request Error */ + u32Tmp1 = CM_DMA1->INTSTAT0 & (BIT_MASK_01 | BIT_MASK_17); + u32Tmp2 = (uint32_t)(~(CM_DMA1->INTMASK0) & (BIT_MASK_01 | BIT_MASK_17)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) { + DMA1_Error1_IrqHandler(); + } + } + /* DMA1 Ch.2 interrupt enabled */ + if (1UL == bCM_DMA1->CHCTL2_b.IE) { + /* DMA1 Ch.2 Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKTC2) { + if ((1UL == bCM_DMA1->INTSTAT1_b.TC2) && (0UL != (VSSEL129 & BIT_MASK_02))) { + DMA1_TC2_IrqHandler(); + } + } + /* DMA1 ch.2 Block Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKBTC2) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC2) && (0UL != (VSSEL129 & BIT_MASK_10))) { + DMA1_BTC2_IrqHandler(); + } + } + /* DMA1 ch.2 Transfer/Request Error */ + u32Tmp1 = CM_DMA1->INTSTAT0 & (BIT_MASK_02 | BIT_MASK_18); + u32Tmp2 = (uint32_t)(~(CM_DMA1->INTMASK0) & (BIT_MASK_02 | BIT_MASK_18)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) { + DMA1_Error2_IrqHandler(); + } + } + /* DMA1 Ch.3 interrupt enabled */ + if (1UL == bCM_DMA1->CHCTL3_b.IE) { + /* DMA1 Ch.3 Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKTC3) { + if ((1UL == bCM_DMA1->INTSTAT1_b.TC3) && (0UL != (VSSEL129 & BIT_MASK_03))) { + DMA1_TC3_IrqHandler(); + } + } + /* DMA1 ch.3 Block Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKBTC3) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC3) && (0UL != (VSSEL129 & BIT_MASK_11))) { + DMA1_BTC3_IrqHandler(); + } + } + /* DMA1 ch.3 Transfer/Request Error */ + u32Tmp1 = CM_DMA1->INTSTAT0 & (BIT_MASK_03 | BIT_MASK_19); + u32Tmp2 = (uint32_t)(~(CM_DMA1->INTMASK0) & (BIT_MASK_03 | BIT_MASK_19)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) { + DMA1_Error3_IrqHandler(); + } + } + /* DMA2 Ch.0 interrupt enabled */ + if (1UL == bCM_DMA2->CHCTL0_b.IE) { + /* DMA2 ch.0 Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKTC0) { + if ((1UL == bCM_DMA2->INTSTAT1_b.TC0) && (0UL != (VSSEL129 & BIT_MASK_04))) { + DMA2_TC0_IrqHandler(); + } + } + /* DMA2 ch.0 Block Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKBTC0) { + if ((1UL == bCM_DMA2->INTSTAT1_b.BTC0) && (0UL != (VSSEL129 & BIT_MASK_12))) { + DMA2_BTC0_IrqHandler(); + } + } + /* DMA2 Ch.0 Transfer/Request Error */ + u32Tmp1 = CM_DMA2->INTSTAT0 & (BIT_MASK_00 | BIT_MASK_16); + u32Tmp2 = (uint32_t)(~(CM_DMA2->INTMASK0) & (BIT_MASK_00 | BIT_MASK_16)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_17))) { + DMA2_Error0_IrqHandler(); + } + } + if (1UL == bCM_DMA2->CHCTL1_b.IE) { + /* DMA2 ch.1 Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKTC1) { + if ((1UL == bCM_DMA2->INTSTAT1_b.TC1) && (0UL != (VSSEL129 & BIT_MASK_05))) { + DMA2_TC1_IrqHandler(); + } + } + /* DMA2 ch.1 Block Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKBTC1) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC1) && (0UL != (VSSEL129 & BIT_MASK_13))) { + DMA2_BTC1_IrqHandler(); + } + } + /* DMA2 Ch.1 Transfer/Request Error */ + u32Tmp1 = CM_DMA2->INTSTAT0 & (BIT_MASK_01 | BIT_MASK_17); + u32Tmp2 = (uint32_t)(~(CM_DMA2->INTMASK0) & (BIT_MASK_01 | BIT_MASK_17)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_17))) { + DMA2_Error1_IrqHandler(); + } + } + if (1UL == bCM_DMA2->CHCTL2_b.IE) { + /* DMA2 ch.2 Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKTC2) { + if ((1UL == bCM_DMA2->INTSTAT1_b.TC2) && (0UL != (VSSEL129 & BIT_MASK_06))) { + DMA2_TC2_IrqHandler(); + } + } + /* DMA2 ch.2 Block Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKBTC2) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC2) && (0UL != (VSSEL129 & BIT_MASK_14))) { + DMA2_BTC2_IrqHandler(); + } + } + /* DMA2 Ch.2 Transfer/Request Error */ + u32Tmp1 = CM_DMA2->INTSTAT0 & (BIT_MASK_02 | BIT_MASK_18); + u32Tmp2 = (uint32_t)(~(CM_DMA2->INTMASK0) & (BIT_MASK_02 | BIT_MASK_18)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_17))) { + DMA2_Error2_IrqHandler(); + } + } + if (1UL == bCM_DMA2->CHCTL3_b.IE) { + /* DMA2 ch.3 Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKTC3) { + if ((1UL == bCM_DMA2->INTSTAT1_b.TC3) && (0UL != (VSSEL129 & BIT_MASK_07))) { + DMA2_TC3_IrqHandler(); + } + } + /* DMA2 ch.3 Block Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKBTC3) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC3) && (0UL != (VSSEL129 & BIT_MASK_15))) { + DMA2_BTC3_IrqHandler(); + } + } + /* DMA2 Ch.3 Transfer/Request Error */ + u32Tmp1 = CM_DMA2->INTSTAT0 & (BIT_MASK_03 | BIT_MASK_19); + u32Tmp2 = (uint32_t)(~(CM_DMA2->INTMASK0) & (BIT_MASK_03 | BIT_MASK_19)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_17))) { + DMA2_Error3_IrqHandler(); + } + } + /* EFM program/erase Error */ + if (1UL == bCM_EFM->FITE_b.PEERRITE) { + if ((0UL != (CM_EFM->FSR & 0x0FU)) && (0UL != (VSSEL129 & BIT_MASK_18))) { + EFM_ProgramEraseError_IrqHandler(); + } + } + /* EFM read collision error*/ + if (1UL == bCM_EFM->FITE_b.COLERRITE) { + /* EFM read collision */ + if ((1UL == bCM_EFM->FSR_b.COLERR) && (0UL != (VSSEL129 & BIT_MASK_19))) { + EFM_ColError_IrqHandler(); + } + } + /* EFM operate end */ + if (1UL == bCM_EFM->FITE_b.OPTENDITE) { + /* EFM operate end */ + if ((1UL == bCM_EFM->FSR_b.OPTEND) && (0UL != (VSSEL129 & BIT_MASK_20))) { + EFM_OpEnd_IrqHandler(); + } + } + /* QSPI access error */ + if ((0UL != (CM_QSPI->SR & QSPI_SR_RAER)) && (0UL != (VSSEL129 & BIT_MASK_22))) { + QSPI_Error_IrqHandler(); + } + /*DCU1 */ + if (1UL == bCM_DCU1->CTL_b.INTEN) { + u32Tmp1 = CM_DCU1->INTEVTSEL; + u32Tmp2 = CM_DCU1->FLAG; + if ((0UL != (u32Tmp1 & u32Tmp2 & 0x7FUL)) && (0UL != (VSSEL129 & BIT_MASK_23))) { + DCU1_IrqHandler(); + } + } + /*DCU2 */ + if (1UL == bCM_DCU2->CTL_b.INTEN) { + u32Tmp1 = CM_DCU2->INTEVTSEL; + u32Tmp2 = CM_DCU2->FLAG; + if ((0UL != (u32Tmp1 & u32Tmp2 & 0x7FUL)) && (0UL != (VSSEL129 & BIT_MASK_24))) { + DCU2_IrqHandler(); + } + } + /*DCU3 */ + if (1UL == bCM_DCU3->CTL_b.INTEN) { + u32Tmp1 = CM_DCU3->INTEVTSEL; + u32Tmp2 = CM_DCU3->FLAG; + if ((0UL != (u32Tmp1 & u32Tmp2 & 0x7FUL)) && (0UL != (VSSEL129 & BIT_MASK_25))) { + DCU3_IrqHandler(); + } + } + /*DCU4 */ + if (1UL == bCM_DCU4->CTL_b.INTEN) { + u32Tmp1 = CM_DCU4->INTEVTSEL; + u32Tmp2 = CM_DCU4->FLAG; + if ((0UL != (u32Tmp1 & u32Tmp2 & 0x7FUL)) && (0UL != (VSSEL129 & BIT_MASK_26))) { + DCU4_IrqHandler(); + } + } + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.130 share IRQ handler + * @param None + * @retval None + */ +void IRQ130_Handler(void) +{ + const uint32_t VSSEL130 = CM_INTC->VSSEL130; + /* Timer0 Ch. 1 A compare match */ + if (1UL == bCM_TMR0_1->BCONR_b.INTENA) { + if ((1UL == bCM_TMR0_1->STFLR_b.CMFA) && (0UL != (VSSEL130 & BIT_MASK_00))) { + TMR0_1_CmpA_IrqHandler(); + } + } + /* Timer0 Ch. 1 B compare match */ + if (1UL == bCM_TMR0_1->BCONR_b.INTENB) { + if ((1UL == bCM_TMR0_1->STFLR_b.CMFB) && (0UL != (VSSEL130 & BIT_MASK_01))) { + TMR0_1_CmpB_IrqHandler(); + } + } + /* Timer0 Ch. 2 A compare match */ + if (1UL == bCM_TMR0_2->BCONR_b.INTENA) { + if ((1UL == bCM_TMR0_2->STFLR_b.CMFA) && (0UL != (VSSEL130 & BIT_MASK_02))) { + TMR0_2_CmpA_IrqHandler(); + } + } + /* Timer0 Ch. 2 B compare match */ + if (1UL == bCM_TMR0_2->BCONR_b.INTENB) { + if ((1UL == bCM_TMR0_2->STFLR_b.CMFB) && (0UL != (VSSEL130 & BIT_MASK_03))) { + TMR0_2_CmpB_IrqHandler(); + } + } + /* Main-OSC stop */ + if (CMU_XTALSTDCR_XTALSTDIE == READ_REG8_BIT(CM_CMU->XTALSTDCR, CMU_XTALSTDCR_XTALSTDIE)) { + if ((CMU_XTALSTDSR_XTALSTDF == READ_REG8_BIT(CM_CMU->XTALSTDSR, CMU_XTALSTDSR_XTALSTDF)) && \ + (0UL != (VSSEL130 & BIT_MASK_21))) { + CLK_XtalStop_IrqHandler(); + } + } + /* Wakeup timer */ + if ((PWC_WKTCR_WKOVF == READ_REG16_BIT(CM_PWC->WKTCR, PWC_WKTCR_WKOVF)) && (0UL != (VSSEL130 & BIT_MASK_22))) { + PWC_WakeupTimer_IrqHandler(); + } + /* SWDT */ + if ((0UL != (CM_SWDT->SR & (BIT_MASK_16 | BIT_MASK_17))) && (0UL != (VSSEL130 & BIT_MASK_23))) { + SWDT_IrqHandler(); + } + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.131 share IRQ handler + * @param None + * @retval None + */ +void IRQ131_Handler(void) +{ + const uint32_t VSSEL131 = CM_INTC->VSSEL131; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + /* Timer6 Unit.1 A compare match */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENA) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMAF) && (0UL != (VSSEL131 & BIT_MASK_00))) { + TMR6_1_GCmpA_IrqHandler(); + } + } + /* Timer6 Unit.1 B compare match */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENB) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMBF) && (0UL != (VSSEL131 & BIT_MASK_01))) { + TMR6_1_GCmpB_IrqHandler(); + } + } + /* Timer6 Unit.1 C compare match */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENC) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMCF) && (0UL != (VSSEL131 & BIT_MASK_02))) { + TMR6_1_GCmpC_IrqHandler(); + } + } + /* Timer6 Unit.1 D compare match */ + if (1UL == bCM_TMR6_1->ICONR_b.INTEND) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMDF) && (0UL != (VSSEL131 & BIT_MASK_03))) { + TMR6_1_GCmpD_IrqHandler(); + } + } + /* Timer6 Unit.1 E compare match */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENE) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMEF) && (0UL != (VSSEL131 & BIT_MASK_04))) { + TMR6_1_GCmpE_IrqHandler(); + } + } + /* Timer6 Unit.1 F compare match */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENF) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMFF) && (0UL != (VSSEL131 & BIT_MASK_05))) { + TMR6_1_GCmpF_IrqHandler(); + } + } + /* Timer6 Unit.1 overflow */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENOVF) { + if ((1UL == bCM_TMR6_1->STFLR_b.OVFF) && (0UL != (VSSEL131 & BIT_MASK_06))) { + TMR6_1_GOvf_IrqHandler(); + } + } + /* Timer6 Unit.1 underflow */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENUDF) { + if ((1UL == bCM_TMR6_1->STFLR_b.UDFF) && (0UL != (VSSEL131 & BIT_MASK_07))) { + TMR6_1_GUdf_IrqHandler(); + } + } + /* Timer6 Unit.1 dead time */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENDTE) { + if (((1UL == bCM_TMR6_1->STFLR_b.DTEF)) && (0UL != (VSSEL131 & BIT_MASK_08))) { + TMR6_1_GDte_IrqHandler(); + } + } + /* Timer6 Unit.1 A up-down compare match */ + u32Tmp1 = (CM_TMR6_1->ICONR & (BIT_MASK_16 | BIT_MASK_17)) >> 7U; + u32Tmp2 = CM_TMR6_1->STFLR & (BIT_MASK_09 | BIT_MASK_10); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL131 & BIT_MASK_11))) { + TMR6_1_SCmpA_IrqHandler(); + } + /* Timer6 Unit.1 B up-down compare match */ + u32Tmp1 = (CM_TMR6_1->ICONR & (BIT_MASK_18 | BIT_MASK_19)) >> 7U; + u32Tmp2 = CM_TMR6_1->STFLR & (BIT_MASK_11 | BIT_MASK_12); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL131 & BIT_MASK_12))) { + TMR6_1_SCmpB_IrqHandler(); + } + /* Timer6 Unit.2 A compare match */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENA) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMAF) && (0UL != (VSSEL131 & BIT_MASK_16))) { + TMR6_2_GCmpA_IrqHandler(); + } + } + /* Timer6 Unit.2 B compare match */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENB) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMBF) && (0UL != (VSSEL131 & BIT_MASK_17))) { + TMR6_2_GCmpB_IrqHandler(); + } + } + /* Timer6 Unit.2 C compare match */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENC) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMCF) && (0UL != (VSSEL131 & BIT_MASK_18))) { + TMR6_2_GCmpC_IrqHandler(); + } + } + /* Timer6 Unit.2 D compare match */ + if (1UL == bCM_TMR6_2->ICONR_b.INTEND) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMDF) && (0UL != (VSSEL131 & BIT_MASK_19))) { + TMR6_2_GCmpD_IrqHandler(); + } + } + /* Timer6 Unit.2 E compare match */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENE) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMEF) && (0UL != (VSSEL131 & BIT_MASK_20))) { + TMR6_2_GCmpE_IrqHandler(); + } + } + /* Timer6 Unit.2 F compare match */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENF) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMFF) && (0UL != (VSSEL131 & BIT_MASK_21))) { + TMR6_2_GCmpF_IrqHandler(); + } + } + /* Timer6 Unit.2 overflow */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENOVF) { + if ((1UL == bCM_TMR6_2->STFLR_b.OVFF) && (0UL != (VSSEL131 & BIT_MASK_22))) { + TMR6_2_GOvf_IrqHandler(); + } + } + /* Timer6 Unit.2 underflow */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENUDF) { + if ((1UL == bCM_TMR6_2->STFLR_b.UDFF) && (0UL != (VSSEL131 & BIT_MASK_23))) { + TMR6_2_GUdf_IrqHandler(); + } + } + /* Timer6 Unit.2 dead time */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENDTE) { + if ((1UL == bCM_TMR6_2->STFLR_b.DTEF) && (0UL != (VSSEL131 & BIT_MASK_24))) { + TMR6_2_GDte_IrqHandler(); + } + } + /* Timer6 Unit.2 A up-down compare match */ + u32Tmp1 = (CM_TMR6_2->ICONR & (BIT_MASK_16 | BIT_MASK_17)) >> 7U; + u32Tmp2 = CM_TMR6_2->STFLR & (BIT_MASK_09 | BIT_MASK_10); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL131 & BIT_MASK_27))) { + TMR6_2_SCmpA_IrqHandler(); + } + /* Timer6 Unit.2 B up-down compare match */ + u32Tmp1 = (CM_TMR6_2->ICONR & (BIT_MASK_18 | BIT_MASK_19)) >> 7U; + u32Tmp2 = CM_TMR6_2->STFLR & (BIT_MASK_11 | BIT_MASK_12); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL131 & BIT_MASK_28))) { + TMR6_2_SCmpB_IrqHandler(); + } + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.132 share IRQ handler + * @param None + * @retval None + */ +void IRQ132_Handler(void) +{ + const uint32_t VSSEL132 = CM_INTC->VSSEL132; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + /* Timer6 Unit.3 A compare match */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENA) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMAF) && (0UL != (VSSEL132 & BIT_MASK_00))) { + TMR6_3_GCmpA_IrqHandler(); + } + } + /* Timer6 Unit.3 B compare match */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENB) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMBF) && (0UL != (VSSEL132 & BIT_MASK_01))) { + TMR6_3_GCmpB_IrqHandler(); + } + } + /* Timer6 Unit.3 C compare match */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENC) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMCF) && (0UL != (VSSEL132 & BIT_MASK_02))) { + TMR6_3_GCmpC_IrqHandler(); + } + } + /* Timer6 Unit.3 D compare match */ + if (1UL == bCM_TMR6_3->ICONR_b.INTEND) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMDF) && (0UL != (VSSEL132 & BIT_MASK_03))) { + TMR6_3_GCmpD_IrqHandler(); + } + } + /* Timer6 Unit.3 E compare match */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENE) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMEF) && (0UL != (VSSEL132 & BIT_MASK_04))) { + TMR6_3_GCmpE_IrqHandler(); + } + } + /* Timer6 Unit.3 F compare match */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENF) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMFF) && (0UL != (VSSEL132 & BIT_MASK_05))) { + TMR6_3_GCmpF_IrqHandler(); + } + } + /* Timer6 Unit.3 overflow */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENOVF) { + if ((1UL == bCM_TMR6_3->STFLR_b.OVFF) && (0UL != (VSSEL132 & BIT_MASK_06))) { + TMR6_3_GOvf_IrqHandler(); + } + } + /* Timer6 Unit.3 underflow */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENUDF) { + if ((1UL == bCM_TMR6_3->STFLR_b.UDFF) && (0UL != (VSSEL132 & BIT_MASK_07))) { + TMR6_3_GUdf_IrqHandler(); + } + } + /* Timer6 Unit.3 dead time */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENDTE) { + if ((1UL == bCM_TMR6_3->STFLR_b.DTEF) && (0UL != (VSSEL132 & BIT_MASK_08))) { + TMR6_3_GDte_IrqHandler(); + } + } + /* Timer6 Unit.3 A up-down compare match */ + u32Tmp1 = (CM_TMR6_3->ICONR & (BIT_MASK_16 | BIT_MASK_17)) >> 7U; + u32Tmp2 = CM_TMR6_3->STFLR & (BIT_MASK_09 | BIT_MASK_10); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (0UL != (VSSEL132 & BIT_MASK_11)))) { + TMR6_3_SCmpA_IrqHandler(); + } + /* Timer6 Unit.3 B up-down compare match */ + u32Tmp1 = (CM_TMR6_3->ICONR & (BIT_MASK_18 | BIT_MASK_19)) >> 7U; + u32Tmp2 = CM_TMR6_3->STFLR & (BIT_MASK_11 | BIT_MASK_12); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (0UL != (VSSEL132 & BIT_MASK_12)))) { + TMR6_3_SCmpB_IrqHandler(); + } + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.136 share IRQ handler + * @param None + * @retval None + */ +void IRQ136_Handler(void) +{ + uint32_t u32Tmp1; + uint32_t u32Tmp2; + const uint32_t VSSEL136 = CM_INTC->VSSEL136; + + /* TimerA Unit.1 overflow */ + if (1UL == bCM_TMRA_1->BCSTRH_b.ITENOVF) { + if ((1UL == bCM_TMRA_1->BCSTRH_b.OVFF) && (0UL != (VSSEL136 & BIT_MASK_00))) { + TMRA_1_Ovf_IrqHandler(); + } + } + /* TimerA Unit.1 underflow */ + if (1UL == bCM_TMRA_1->BCSTRH_b.ITENUDF) { + if ((1UL == bCM_TMRA_1->BCSTRH_b.UDFF) && (0UL != (VSSEL136 & BIT_MASK_01))) { + TMRA_1_Udf_IrqHandler(); + } + } + u32Tmp1 = CM_TMRA_1->ICONR; + u32Tmp2 = CM_TMRA_1->STFLR; + /* TimerA Unit.1 compare match */ + if ((0UL != (u32Tmp1 & u32Tmp2 & 0xFFUL)) && (0UL != (VSSEL136 & BIT_MASK_02))) { + TMRA_1_Cmp_IrqHandler(); + } + + /* TimerA Unit.2 overflow */ + if (1UL == bCM_TMRA_2->BCSTRH_b.ITENOVF) { + if ((1UL == bCM_TMRA_2->BCSTRH_b.OVFF) && (0UL != (VSSEL136 & BIT_MASK_03))) { + TMRA_2_Ovf_IrqHandler(); + } + } + /* TimerA Unit.2 underflow */ + if (1UL == bCM_TMRA_2->BCSTRH_b.ITENUDF) { + if ((1UL == bCM_TMRA_2->BCSTRH_b.UDFF) && (0UL != (VSSEL136 & BIT_MASK_04))) { + TMRA_2_Udf_IrqHandler(); + } + } + u32Tmp1 = CM_TMRA_2->ICONR; + u32Tmp2 = CM_TMRA_2->STFLR; + /* TimerA Unit.2 compare match */ + if ((0UL != (u32Tmp1 & u32Tmp2 & 0xFFUL)) && (0UL != (VSSEL136 & BIT_MASK_05))) { + TMRA_2_Cmp_IrqHandler(); + } + + /* TimerA Unit.3 overflow */ + if (1UL == bCM_TMRA_3->BCSTRH_b.ITENOVF) { + if ((1UL == bCM_TMRA_3->BCSTRH_b.OVFF) && (0UL != (VSSEL136 & BIT_MASK_06))) { + TMRA_3_Ovf_IrqHandler(); + } + } + /* TimerA Unit.3 underflow */ + if (1UL == bCM_TMRA_3->BCSTRH_b.ITENUDF) { + if ((1UL == bCM_TMRA_3->BCSTRH_b.UDFF) && (0UL != (VSSEL136 & BIT_MASK_07))) { + TMRA_3_Udf_IrqHandler(); + } + } + u32Tmp1 = CM_TMRA_3->ICONR; + u32Tmp2 = CM_TMRA_3->STFLR; + /* TimerA Unit.3 compare match */ + if ((0UL != (u32Tmp1 & u32Tmp2 & 0xFFUL)) && (0UL != (VSSEL136 & BIT_MASK_08))) { + TMRA_3_Cmp_IrqHandler(); + } + + /* TimerA Unit.4 overflow */ + if (1UL == bCM_TMRA_4->BCSTRH_b.ITENOVF) { + if ((1UL == bCM_TMRA_4->BCSTRH_b.OVFF) && (0UL != (VSSEL136 & BIT_MASK_09))) { + TMRA_4_Ovf_IrqHandler(); + } + } + /* TimerA Unit.4 underflow */ + if (1UL == bCM_TMRA_4->BCSTRH_b.ITENUDF) { + if ((1UL == bCM_TMRA_4->BCSTRH_b.UDFF) && (0UL != (VSSEL136 & BIT_MASK_10))) { + TMRA_4_Udf_IrqHandler(); + } + } + u32Tmp1 = CM_TMRA_4->ICONR; + u32Tmp2 = CM_TMRA_4->STFLR; + /* TimerA Unit.4 compare match */ + if ((0UL != (u32Tmp1 & u32Tmp2 & 0xFFUL)) && (0UL != (VSSEL136 & BIT_MASK_11))) { + TMRA_4_Cmp_IrqHandler(); + } + + /* TimerA Unit.5 overflow */ + if (1UL == bCM_TMRA_5->BCSTRH_b.ITENOVF) { + if ((1UL == bCM_TMRA_5->BCSTRH_b.OVFF) && (0UL != (VSSEL136 & BIT_MASK_12))) { + TMRA_5_Ovf_IrqHandler(); + } + } + /* TimerA Unit.5 underflow */ + if (1UL == bCM_TMRA_5->BCSTRH_b.ITENUDF) { + if ((1UL == bCM_TMRA_5->BCSTRH_b.UDFF) && (0UL != (VSSEL136 & BIT_MASK_13))) { + TMRA_5_Udf_IrqHandler(); + } + } + u32Tmp1 = CM_TMRA_5->ICONR; + u32Tmp2 = CM_TMRA_5->STFLR; + /* TimerA Unit.5 compare match */ + if ((0UL != (u32Tmp1 & u32Tmp2 & 0xFFUL)) && (0UL != (VSSEL136 & BIT_MASK_14))) { + TMRA_5_Cmp_IrqHandler(); + } + + /* TimerA Unit.6 overflow */ + if (1UL == bCM_TMRA_6->BCSTRH_b.ITENOVF) { + if ((1UL == bCM_TMRA_6->BCSTRH_b.OVFF) && (0UL != (VSSEL136 & BIT_MASK_16))) { + TMRA_6_Ovf_IrqHandler(); + } + } + /* TimerA Unit.6 underflow */ + if (1UL == bCM_TMRA_6->BCSTRH_b.ITENUDF) { + if ((1UL == bCM_TMRA_6->BCSTRH_b.UDFF) && (0UL != (VSSEL136 & BIT_MASK_17))) { + TMRA_6_Udf_IrqHandler(); + } + } + u32Tmp1 = CM_TMRA_6->ICONR; + u32Tmp2 = CM_TMRA_6->STFLR; + /* TimerA Unit.6 compare match */ + if ((0UL != (u32Tmp1 & u32Tmp2 & 0xFFUL)) && (0UL != (VSSEL136 & BIT_MASK_18))) { + TMRA_6_Cmp_IrqHandler(); + } + + /* USBFS global interrupt */ + if (1UL == bCM_USBFS->GAHBCFG_b.GINTMSK) { + u32Tmp1 = CM_USBFS->GINTMSK & 0xF77CFCFBUL; + u32Tmp2 = CM_USBFS->GINTSTS & 0xF77CFCFBUL; + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL136 & BIT_MASK_19))) { + USBFS_Global_IrqHandler(); + } + } + + u32Tmp1 = CM_USART1->SR; + u32Tmp2 = CM_USART1->CR1; + /* USART Ch.1 Receive error */ + if ((0UL != (u32Tmp2 & BIT_MASK_05)) && (0UL != (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03))) && \ + (0UL != (VSSEL136 & BIT_MASK_22))) { + USART1_RxError_IrqHandler(); + } + /* USART Ch.1 Receive completed */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_05)) && (0UL != (BIT_MASK_23 & VSSEL136))) { + USART1_RxFull_IrqHandler(); + } + /* USART Ch.1 Transmit data empty */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_07)) && (0UL != (BIT_MASK_24 & VSSEL136))) { + USART1_TxEmpty_IrqHandler(); + } + /* USART Ch.1 Transmit completed */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_06)) && (0UL != (BIT_MASK_25 & VSSEL136))) { + USART1_TxComplete_IrqHandler(); + } + /* USART Ch.1 Receive timeout */ + if ((0UL != (u32Tmp2 & BIT_MASK_01)) && (0UL != (u32Tmp1 & BIT_MASK_08)) && (0UL != (VSSEL136 & BIT_MASK_26))) { + USART1_RxTO_IrqHandler(); + } + + u32Tmp1 = CM_USART2->SR; + u32Tmp2 = CM_USART2->CR1; + /* USART Ch.2 Receive error */ + if ((0UL != (u32Tmp2 & BIT_MASK_05)) && (0UL != (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03))) && \ + (0UL != (VSSEL136 & BIT_MASK_27))) { + USART2_RxError_IrqHandler(); + } + /* USART Ch.2 Receive completed */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_05)) && (0UL != (BIT_MASK_28 & VSSEL136))) { + USART2_RxFull_IrqHandler(); + } + /* USART Ch.2 Transmit data empty */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_07)) && (0UL != (BIT_MASK_29 & VSSEL136))) { + USART2_TxEmpty_IrqHandler(); + } + /* USART Ch.2 Transmit completed */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_06)) && (0UL != (BIT_MASK_30 & VSSEL136))) { + USART2_TxComplete_IrqHandler(); + } + /* USART Ch.2 Receive timeout */ + if ((0UL != (u32Tmp2 & BIT_MASK_01)) && (0UL != (u32Tmp1 & BIT_MASK_08)) && (0UL != (VSSEL136 & BIT_MASK_31))) { + USART2_RxTO_IrqHandler(); + } + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.137 share IRQ handler + * @param None + * @retval None + */ +void IRQ137_Handler(void) +{ + uint32_t u32Tmp1; + uint32_t u32Tmp2; + const uint32_t VSSEL137 = CM_INTC->VSSEL137; + + u32Tmp1 = CM_USART3->SR; + u32Tmp2 = CM_USART3->CR1; + /* USART Ch.3 Receive error */ + if ((0UL != (u32Tmp2 & BIT_MASK_05)) && (0UL != (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03))) && \ + (0UL != (VSSEL137 & BIT_MASK_00))) { + USART3_RxError_IrqHandler(); + } + /* USART Ch.3 Receive completed */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_05)) && (0UL != (BIT_MASK_01 & VSSEL137))) { + USART3_RxFull_IrqHandler(); + } + /* USART Ch.3 Transmit data empty */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_07)) && (0UL != (BIT_MASK_02 & VSSEL137))) { + USART3_TxEmpty_IrqHandler(); + } + /* USART Ch.3 Transmit completed */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_06)) && (0UL != (BIT_MASK_03 & VSSEL137))) { + USART3_TxComplete_IrqHandler(); + } + /* USART Ch.3 Receive timeout */ + if ((0UL != (u32Tmp2 & BIT_MASK_01)) && (0UL != (u32Tmp1 & BIT_MASK_08)) && (0UL != (VSSEL137 & BIT_MASK_04))) { + USART3_RxTO_IrqHandler(); + } + + u32Tmp1 = CM_USART4->SR; + u32Tmp2 = CM_USART4->CR1; + /* USART Ch.4 Receive error */ + if ((0UL != (u32Tmp2 & BIT_MASK_05)) && (0UL != (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03))) && \ + (0UL != (VSSEL137 & BIT_MASK_05))) { + USART4_RxError_IrqHandler(); + } + /* USART Ch.4 Receive completed */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_05)) && (0UL != (BIT_MASK_06 & VSSEL137))) { + USART4_RxFull_IrqHandler(); + } + /* USART Ch.4 Transmit data empty */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_07)) && (0UL != (BIT_MASK_07 & VSSEL137))) { + USART4_TxEmpty_IrqHandler(); + } + /* USART Ch.4 Transmit completed */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_06)) && (0UL != (BIT_MASK_08 & VSSEL137))) { + USART4_TxComplete_IrqHandler(); + } + /* USART Ch.4 Receive timeout */ + if ((0UL != (u32Tmp2 & BIT_MASK_01)) && (0UL != (u32Tmp1 & BIT_MASK_08)) && (0UL != (VSSEL137 & BIT_MASK_09))) { + USART4_RxTO_IrqHandler(); + } + + u32Tmp1 = CM_SPI1->CR1; + u32Tmp2 = CM_SPI1->SR; + /* SPI Ch.1 Receive completed */ + if ((0UL != (u32Tmp1 & BIT_MASK_10)) && (0UL != (u32Tmp2 & BIT_MASK_07)) && (0UL != (VSSEL137 & BIT_MASK_11))) { + SPI1_RxFull_IrqHandler(); + } + /* SPI Ch.1 Transmit buf empty */ + if ((0UL != (u32Tmp1 & BIT_MASK_09)) && (0UL != (u32Tmp2 & BIT_MASK_05)) && (0UL != (VSSEL137 & BIT_MASK_12))) { + SPI1_TxEmpty_IrqHandler(); + } + /* SPI Ch.1 bus idle */ + if ((0UL != (u32Tmp1 & BIT_MASK_11)) && (0UL == (u32Tmp2 & BIT_MASK_01)) && (0UL != (VSSEL137 & BIT_MASK_13))) { + SPI1_Idle_IrqHandler(); + } + /* SPI Ch.1 parity/overflow/underflow/mode error */ + if ((0UL != (u32Tmp1 & BIT_MASK_08)) && \ + (0UL != ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04)))) && \ + (0UL != (VSSEL137 & BIT_MASK_14))) { + SPI1_Error_IrqHandler(); + } + + u32Tmp1 = CM_SPI2->CR1; + u32Tmp2 = CM_SPI2->SR; + /* SPI Ch.2 Receive completed */ + if ((0UL != (u32Tmp1 & BIT_MASK_10)) && (0UL != (u32Tmp2 & BIT_MASK_07)) && (0UL != (VSSEL137 & BIT_MASK_16))) { + SPI2_RxFull_IrqHandler(); + } + /* SPI Ch.2 Transmit buf empty */ + if ((0UL != (u32Tmp1 & BIT_MASK_09)) && (0UL != (u32Tmp2 & BIT_MASK_05)) && (0UL != (VSSEL137 & BIT_MASK_17))) { + SPI2_TxEmpty_IrqHandler(); + } + /* SPI Ch.2 bus idle */ + if ((0UL != (u32Tmp1 & BIT_MASK_11)) && (0UL == (u32Tmp2 & BIT_MASK_01)) && (0UL != (VSSEL137 & BIT_MASK_18))) { + SPI2_Idle_IrqHandler(); + } + /* SPI Ch.2 parity/overflow/underflow/mode error */ + if ((0UL != (u32Tmp1 & BIT_MASK_08)) && \ + (0UL != ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04)))) && \ + (0UL != (VSSEL137 & BIT_MASK_19))) { + SPI2_Error_IrqHandler(); + } + + u32Tmp1 = CM_SPI3->CR1; + u32Tmp2 = CM_SPI3->SR; + /* SPI Ch.3 Receive completed */ + if ((0UL != (u32Tmp1 & BIT_MASK_10)) && (0UL != (u32Tmp2 & BIT_MASK_07)) && (0UL != (VSSEL137 & BIT_MASK_21))) { + SPI3_RxFull_IrqHandler(); + } + /* SPI Ch.3 Transmit buf empty */ + if ((0UL != (u32Tmp1 & BIT_MASK_09)) && (0UL != (u32Tmp2 & BIT_MASK_05)) && (0UL != (VSSEL137 & BIT_MASK_22))) { + SPI3_TxEmpty_IrqHandler(); + } + /* SPI Ch.3 bus idle */ + if ((0UL != (u32Tmp1 & BIT_MASK_11)) && (0UL == (u32Tmp2 & BIT_MASK_01)) && (0UL != (VSSEL137 & BIT_MASK_23))) { + SPI3_Idle_IrqHandler(); + } + /* SPI Ch.3 parity/overflow/underflow/mode error */ + if ((0UL != (u32Tmp1 & BIT_MASK_08)) && \ + (0UL != ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04)))) && \ + (0UL != (VSSEL137 & BIT_MASK_24))) { + SPI3_Error_IrqHandler(); + } + + u32Tmp1 = CM_SPI4->CR1; + u32Tmp2 = CM_SPI4->SR; + /* SPI Ch.4 Receive completed */ + if ((0UL != (u32Tmp1 & BIT_MASK_10)) && (0UL != (u32Tmp2 & BIT_MASK_07)) && (0UL != (VSSEL137 & BIT_MASK_26))) { + SPI4_RxFull_IrqHandler(); + } + /* SPI Ch.4 Transmit buf empty */ + if ((0UL != (u32Tmp1 & BIT_MASK_09)) && (0UL != (u32Tmp2 & BIT_MASK_05)) && (0UL != (VSSEL137 & BIT_MASK_27))) { + SPI4_TxEmpty_IrqHandler(); + } + /* SPI Ch.4 bus idle */ + if ((0UL != (u32Tmp1 & BIT_MASK_11)) && (0UL == (u32Tmp2 & BIT_MASK_01)) && (0UL != (VSSEL137 & BIT_MASK_28))) { + SPI4_Idle_IrqHandler(); + } + /* SPI Ch.4 parity/overflow/underflow/mode error */ + if ((0UL != (u32Tmp1 & BIT_MASK_08)) && \ + (0UL != ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04)))) && \ + (0UL != (VSSEL137 & BIT_MASK_29))) { + SPI4_Error_IrqHandler(); + } + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.138 share IRQ handler + * @param None + * @retval None + */ +void IRQ138_Handler(void) +{ + const uint32_t VSSEL138 = CM_INTC->VSSEL138; + uint32_t u32Tmp1; + + u32Tmp1 = CM_TMR4_1->OCSRU; + /* Timer4 Unit.1 U phase higher compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_00)) && (0UL != (u32Tmp1 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_06))) { + TMR4_1_GCmpUH_IrqHandler(); + } + /* Timer4 Unit.1 U phase lower compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_01)) && (0UL != (u32Tmp1 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_07))) { + TMR4_1_GCmpUL_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_1->OCSRV; + /* Timer4 Unit.1 V phase higher compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_02)) && (0UL != (u32Tmp1 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_06))) { + TMR4_1_GCmpVH_IrqHandler(); + } + /* Timer4 Unit.1 V phase lower compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_03)) && (0UL != (u32Tmp1 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_07))) { + TMR4_1_GCmpVL_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_1->OCSRW; + /* Timer4 Unit.1 W phase higher compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_06))) { + TMR4_1_GCmpWH_IrqHandler(); + } + /* Timer4 Unit.1 W phase lower compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_07))) { + TMR4_1_GCmpWL_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_1->CCSR; + /* Timer4 Unit.1 overflow */ + if ((0UL != (VSSEL138 & BIT_MASK_06)) && (0UL != (u32Tmp1 & BIT_MASK_08)) && (0UL != (u32Tmp1 & BIT_MASK_09))) { + TMR4_1_GOvf_IrqHandler(); + } + /* Timer4 Unit.1 underflow */ + if ((0UL != (VSSEL138 & BIT_MASK_07)) && (0UL != (u32Tmp1 & BIT_MASK_13)) && (0UL != (u32Tmp1 & BIT_MASK_14))) { + TMR4_1_GUdf_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_1->RCSR; + /* Timer4 Unit.1 U phase reload */ + if ((0UL != (VSSEL138 & BIT_MASK_08)) && (0UL == (u32Tmp1 & BIT_MASK_00)) && (0UL != (u32Tmp1 & BIT_MASK_04))) { + TMR4_1_ReloadU_IrqHandler(); + } + /* Timer4 Unit.1 V phase reload */ + if ((0UL != (VSSEL138 & BIT_MASK_09)) && (0UL == (u32Tmp1 & BIT_MASK_01)) && (0UL != (u32Tmp1 & BIT_MASK_08))) { + TMR4_1_ReloadV_IrqHandler(); + } + /* Timer4 Unit.1 W phase reload */ + if ((0UL != (VSSEL138 & BIT_MASK_10)) && (0UL == (u32Tmp1 & BIT_MASK_02)) && (0UL != (u32Tmp1 & BIT_MASK_12))) { + TMR4_1_ReloadW_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_2->OCSRU; + /* Timer4 Unit.2 U phase higher compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_16)) && (0UL != (u32Tmp1 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_06))) { + TMR4_1_GCmpUH_IrqHandler(); + } + /* Timer4 Unit.2 U phase lower compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_17)) && (0UL != (u32Tmp1 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_07))) { + TMR4_1_GCmpUL_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_2->OCSRV; + /* Timer4 Unit.2 V phase higher compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_18)) && (0UL != (u32Tmp1 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_06))) { + TMR4_2_GCmpVH_IrqHandler(); + } + /* Timer4 Unit.2 V phase lower compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_19)) && (0UL != (u32Tmp1 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_07))) { + TMR4_2_GCmpVL_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_2->OCSRW; + /* Timer4 Unit.2 W phase higher compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_20)) && (0UL != (u32Tmp1 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_06))) { + TMR4_2_GCmpWH_IrqHandler(); + } + /* Timer4 Unit.2 W phase lower compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_21)) && (0UL != (u32Tmp1 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_07))) { + TMR4_2_GCmpWL_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_2->CCSR; + /* Timer4 Unit.2 overflow */ + if ((0UL != (VSSEL138 & BIT_MASK_22)) && (0UL != (u32Tmp1 & BIT_MASK_08)) && (0UL != (u32Tmp1 & BIT_MASK_09))) { + TMR4_2_GOvf_IrqHandler(); + } + /* Timer4 Unit.2 underflow */ + if ((0UL != (VSSEL138 & BIT_MASK_23)) && (0UL != (u32Tmp1 & BIT_MASK_13)) && (0UL != (u32Tmp1 & BIT_MASK_14))) { + TMR4_2_GUdf_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_2->RCSR; + /* Timer4 Unit.2 U phase reload */ + if ((0UL != (VSSEL138 & BIT_MASK_24)) && (0UL == (u32Tmp1 & BIT_MASK_00)) && (0UL != (u32Tmp1 & BIT_MASK_04))) { + TMR4_2_ReloadU_IrqHandler(); + } + /* Timer4 Unit.2 V phase reload */ + if ((0UL != (VSSEL138 & BIT_MASK_25)) && (0UL == (u32Tmp1 & BIT_MASK_01)) && (0UL != (u32Tmp1 & BIT_MASK_08))) { + TMR4_2_ReloadV_IrqHandler(); + } + /* Timer4 Unit.2 W phase reload */ + if ((0UL != (VSSEL138 & BIT_MASK_26)) && (0UL == (u32Tmp1 & BIT_MASK_02)) && (0UL != (u32Tmp1 & BIT_MASK_12))) { + TMR4_2_ReloadW_IrqHandler(); + } + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.139 share IRQ handler + * @param None + * @retval None + */ +void IRQ139_Handler(void) +{ + uint32_t u32Tmp1; + const uint32_t VSSEL139 = CM_INTC->VSSEL139; + + u32Tmp1 = CM_TMR4_3->OCSRU; + /* Timer4 Unit.3 U phase higher compare match */ + if ((0UL != (VSSEL139 & BIT_MASK_00)) && (0UL != (u32Tmp1 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_06))) { + TMR4_3_GCmpUH_IrqHandler(); + } + /* Timer4 Unit.3 U phase lower compare match */ + if ((0UL != (VSSEL139 & BIT_MASK_01)) && (0UL != (u32Tmp1 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_07))) { + TMR4_3_GCmpUL_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_3->OCSRV; + /* Timer4 Unit.3 V phase higher compare match */ + if ((0UL != (VSSEL139 & BIT_MASK_02)) && (0UL != (u32Tmp1 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_06))) { + TMR4_3_GCmpVH_IrqHandler(); + } + /* Timer4 Unit.3 V phase lower compare match */ + if ((0UL != (VSSEL139 & BIT_MASK_03)) && (0UL != (u32Tmp1 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_07))) { + TMR4_3_GCmpVL_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_3->OCSRW; + /* Timer4 Unit.3 W phase higher compare match */ + if ((0UL != (VSSEL139 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_06))) { + TMR4_3_GCmpWH_IrqHandler(); + } + /* Timer4 Unit.3 W phase lower compare match */ + if ((0UL != (VSSEL139 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_07))) { + TMR4_3_GCmpWL_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_3->CCSR; + /* Timer4 Unit.3 overflow */ + if ((0UL != (VSSEL139 & BIT_MASK_06)) && (0UL != (u32Tmp1 & BIT_MASK_08)) && (0UL != (u32Tmp1 & BIT_MASK_09))) { + TMR4_3_GOvf_IrqHandler(); + } + /* Timer4 Unit.3 underflow */ + if ((0UL != (VSSEL139 & BIT_MASK_07)) && (0UL != (u32Tmp1 & BIT_MASK_13)) && (0UL != (u32Tmp1 & BIT_MASK_14))) { + TMR4_3_GUdf_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_3->RCSR; + /* Timer4 Unit.3 U phase reload */ + if ((0UL != (VSSEL139 & BIT_MASK_08)) && (0UL == (u32Tmp1 & BIT_MASK_00)) && (0UL != (u32Tmp1 & BIT_MASK_04))) { + TMR4_1_ReloadU_IrqHandler(); + } + /* Timer4 Unit.3 V phase reload */ + if ((0UL != (VSSEL139 & BIT_MASK_09)) && (0UL == (u32Tmp1 & BIT_MASK_01)) && (0UL != (u32Tmp1 & BIT_MASK_08))) { + TMR4_3_ReloadV_IrqHandler(); + } + /* Timer4 Unit.3 W phase reload */ + if ((0UL != (VSSEL139 & BIT_MASK_10)) && (0UL == (u32Tmp1 & BIT_MASK_02)) && (0UL != (u32Tmp1 & BIT_MASK_12))) { + TMR4_3_ReloadW_IrqHandler(); + } + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.140 share IRQ handler + * @param None + * @retval None + */ +void IRQ140_Handler(void) +{ + const uint32_t VSSEL140 = CM_INTC->VSSEL140; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + /* EMB0 */ + u32Tmp1 = CM_EMB0->STAT & 0x0000000FUL; + u32Tmp2 = CM_EMB0->INTEN & 0x0000000FUL; + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL140 & BIT_MASK_06))) { + EMB_GR0_IrqHandler(); + } + /* EMB1 */ + u32Tmp1 = CM_EMB1->STAT & 0x0000000FUL; + u32Tmp2 = CM_EMB1->INTEN & 0x0000000FUL; + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL140 & BIT_MASK_07))) { + EMB_GR1_IrqHandler(); + } + /* EMB2 */ + u32Tmp1 = CM_EMB2->STAT & 0x0000000FUL; + u32Tmp2 = CM_EMB2->INTEN & 0x0000000FUL; + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL140 & BIT_MASK_08))) { + EMB_GR2_IrqHandler(); + } + /* EMB3 */ + u32Tmp1 = CM_EMB3->STAT & 0x0000000FUL; + u32Tmp2 = CM_EMB3->INTEN & 0x0000000FUL; + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL140 & BIT_MASK_09))) { + EMB_GR3_IrqHandler(); + } + + /* I2S Ch.1 Transmit */ + if (1UL == bCM_I2S1->CTRL_b.TXIE) { + if ((1UL == bCM_I2S1->SR_b.TXBA) && (0UL != (VSSEL140 & BIT_MASK_16))) { + I2S1_Tx_IrqHandler(); + } + } + /* I2S Ch.1 Receive */ + if (1UL == bCM_I2S1->CTRL_b.RXIE) { + if ((1UL == bCM_I2S1->SR_b.RXBA) && (0UL != (VSSEL140 & BIT_MASK_17))) { + I2S1_Rx_IrqHandler(); + } + } + /* I2S Ch.1 Error */ + if (1UL == bCM_I2S1->CTRL_b.EIE) { + if (0UL != ((CM_I2S1->ER & (BIT_MASK_00 | BIT_MASK_01))) && (0UL != (VSSEL140 & BIT_MASK_18))) { + I2S1_Error_IrqHandler(); + } + } + /* I2S Ch.2 Transmit */ + if (1UL == bCM_I2S2->CTRL_b.TXIE) { + if ((1UL == bCM_I2S2->SR_b.TXBA) && (0UL != (VSSEL140 & BIT_MASK_19))) { + I2S2_Tx_IrqHandler(); + } + } + /* I2S Ch.2 Receive */ + if (1UL == bCM_I2S2->CTRL_b.RXIE) { + if ((1UL == bCM_I2S2->SR_b.RXBA) && (0UL != (VSSEL140 & BIT_MASK_20))) { + I2S2_Rx_IrqHandler(); + } + } + /* I2S Ch.2 Error */ + if (1UL == bCM_I2S2->CTRL_b.EIE) { + if (0UL != ((CM_I2S2->ER & (BIT_MASK_00 | BIT_MASK_01))) && (0UL != (VSSEL140 & BIT_MASK_21))) { + I2S2_Error_IrqHandler(); + } + } + /* I2S Ch.3 Transmit */ + if (1UL == bCM_I2S3->CTRL_b.TXIE) { + if ((1UL == bCM_I2S3->SR_b.TXBA) && (0UL != (VSSEL140 & BIT_MASK_22))) { + I2S3_Tx_IrqHandler(); + } + } + /* I2S Ch.3 Receive */ + if (1UL == bCM_I2S3->CTRL_b.RXIE) { + if ((1UL == bCM_I2S3->SR_b.RXBA) && (0UL != (VSSEL140 & BIT_MASK_23))) { + I2S3_Rx_IrqHandler(); + } + } + /* I2S Ch.3 Error */ + if (1UL == bCM_I2S3->CTRL_b.EIE) { + if (0UL != ((CM_I2S3->ER & (BIT_MASK_00 | BIT_MASK_01))) && (0UL != (VSSEL140 & BIT_MASK_24))) { + I2S3_Error_IrqHandler(); + } + } + /* I2S Ch.4 Transmit */ + if (1UL == bCM_I2S4->CTRL_b.TXIE) { + if ((1UL == bCM_I2S4->SR_b.TXBA) && (0UL != (VSSEL140 & BIT_MASK_25))) { + I2S4_Tx_IrqHandler(); + } + } + /* I2S Ch.4 Receive */ + if (1UL == bCM_I2S4->CTRL_b.RXIE) { + if ((1UL == bCM_I2S4->SR_b.RXBA) && (0UL != (VSSEL140 & BIT_MASK_26))) { + I2S4_Rx_IrqHandler(); + } + } + /* I2S Ch.4 Error */ + if (1UL == bCM_I2S4->CTRL_b.EIE) { + if (0UL != ((CM_I2S4->ER & (BIT_MASK_00 | BIT_MASK_01))) && (0UL != (VSSEL140 & BIT_MASK_27))) { + I2S4_Error_IrqHandler(); + } + } + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.141 share IRQ handler + * @param None + * @retval None + */ +void IRQ141_Handler(void) +{ + uint32_t VSSEL141 = CM_INTC->VSSEL141; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + /* I2C Ch.1 Receive completed */ + if (1UL == bCM_I2C1->CR2_b.RFULLIE) { + if ((1UL == bCM_I2C1->SR_b.RFULLF) && (0UL != (VSSEL141 & BIT_MASK_04))) { + I2C1_RxFull_IrqHandler(); + } + } + /* I2C Ch.1 Transmit data empty */ + if (1UL == bCM_I2C1->CR2_b.TEMPTYIE) { + if ((1UL == bCM_I2C1->SR_b.TEMPTYF) && (0UL != (VSSEL141 & BIT_MASK_05))) { + I2C1_TxEmpty_IrqHandler(); + } + } + /* I2C Ch.1 Transmit completed */ + if (1UL == bCM_I2C1->CR2_b.TENDIE) { + if ((1UL == bCM_I2C1->SR_b.TENDF) && (0UL != (VSSEL141 & BIT_MASK_06))) { + I2C1_TxComplete_IrqHandler(); + } + } + /* I2C Ch.1 Error */ + u32Tmp1 = CM_I2C1->CR2 & 0x00F05217UL; + u32Tmp2 = CM_I2C1->SR & 0x00F05217UL; + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL141 & BIT_MASK_07))) { + I2C1_EE_IrqHandler(); + } + /* I2C Ch.2 Receive completed */ + if (1UL == bCM_I2C2->CR2_b.RFULLIE) { + if ((1UL == bCM_I2C2->SR_b.RFULLF) && (0UL != (VSSEL141 & BIT_MASK_08))) { + I2C2_RxFull_IrqHandler(); + } + } + /* I2C Ch.2 Transmit data empty */ + if (1UL == bCM_I2C2->CR2_b.TEMPTYIE) { + if ((1UL == bCM_I2C2->SR_b.TEMPTYF) && (0UL != (VSSEL141 & BIT_MASK_09))) { + I2C2_TxEmpty_IrqHandler(); + } + } + /* I2C Ch.2 Transmit completed */ + if (1UL == bCM_I2C2->CR2_b.TENDIE) { + if ((1UL == bCM_I2C2->SR_b.TENDF) && (0UL != (VSSEL141 & BIT_MASK_10))) { + I2C2_TxComplete_IrqHandler(); + } + } + /* I2C Ch.2 Error */ + u32Tmp1 = CM_I2C2->CR2 & 0x00F05217UL; + u32Tmp2 = CM_I2C2->SR & 0x00F05217UL; + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL141 & BIT_MASK_11))) { + I2C2_EE_IrqHandler(); + } + /* I2C Ch.3 Receive completed */ + if (1UL == bCM_I2C3->CR2_b.RFULLIE) { + if ((1UL == bCM_I2C3->SR_b.RFULLF) && (0UL != (VSSEL141 & BIT_MASK_12))) { + I2C3_RxFull_IrqHandler(); + } + } + /* I2C Ch.3 Transmit data empty */ + if (1UL == bCM_I2C3->CR2_b.TEMPTYIE) { + if ((1UL == bCM_I2C3->SR_b.TEMPTYF) && (0UL != (VSSEL141 & BIT_MASK_13))) { + I2C3_TxEmpty_IrqHandler(); + } + } + /* I2C Ch.3 Transmit completed */ + if (1UL == bCM_I2C3->CR2_b.TENDIE) { + if ((1UL == bCM_I2C3->SR_b.TENDF) && (0UL != (VSSEL141 & BIT_MASK_14))) { + I2C3_TxComplete_IrqHandler(); + } + } + /* I2C Ch.3 Error */ + u32Tmp1 = CM_I2C3->CR2 & 0x00F05217UL; + u32Tmp2 = CM_I2C3->SR & 0x00F05217UL; + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL141 & BIT_MASK_15))) { + I2C3_EE_IrqHandler(); + } + /* LVD Ch.1 detected */ + if (PWC_PVDCR1_PVD1IRE == READ_REG8_BIT(CM_PWC->PVDCR1, PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS)) { + if ((PWC_PVDDSR_PVD1DETFLG == READ_REG8_BIT(CM_PWC->PVDDSR, PWC_PVDDSR_PVD1DETFLG)) && \ + (0UL != (VSSEL141 & BIT_MASK_17))) { + PWC_LVD1_IrqHandler(); + } + } + if (PWC_PVDCR1_PVD2IRE == READ_REG8_BIT(CM_PWC->PVDCR1, PWC_PVDCR1_PVD2IRE | PWC_PVDCR1_PVD2IRS)) { + /* LVD Ch.2 detected */ + if ((PWC_PVDDSR_PVD2DETFLG == READ_REG8_BIT(CM_PWC->PVDDSR, PWC_PVDDSR_PVD2DETFLG)) && \ + (0UL != (VSSEL141 & BIT_MASK_18))) { + PWC_LVD2_IrqHandler(); + } + } + /* Freq. calculate error detected */ + if (1UL == bCM_FCM->RIER_b.ERRIE) { + if ((1UL == bCM_FCM->SR_b.ERRF) && (0UL != (VSSEL141 & BIT_MASK_20))) { + FCM_Error_IrqHandler(); + } + } + /* Freq. calculate completed */ + if (1UL == bCM_FCM->RIER_b.MENDIE) { + if ((1UL == bCM_FCM->SR_b.MENDF) && (0UL != (VSSEL141 & BIT_MASK_21))) { + FCM_End_IrqHandler(); + } + } + /* Freq. calculate overflow */ + if (1UL == bCM_FCM->RIER_b.OVFIE) { + if ((1UL == bCM_FCM->SR_b.OVF) && (0UL != (VSSEL141 & BIT_MASK_22))) { + FCM_Ovf_IrqHandler(); + } + } + + /* WDT */ + if ((0UL != (CM_WDT->SR & (BIT_MASK_16 | BIT_MASK_17))) && (0UL != (VSSEL141 & BIT_MASK_23))) { + WDT_IrqHandler(); + } + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.142 share IRQ handler + * @param None + * @retval None + */ +void IRQ142_Handler(void) +{ + uint32_t u32VSSEL142 = CM_INTC->VSSEL142; + /* ADC unit.1 seq. A */ + if (1UL == bCM_ADC1->ICR_b.EOCAIEN) { + if ((1UL == bCM_ADC1->ISR_b.EOCAF) && (0UL != (u32VSSEL142 & BIT_MASK_00))) { + ADC1_SeqA_IrqHandler(); + } + } + /* ADC unit.1 seq. B */ + if (1UL == bCM_ADC1->ICR_b.EOCBIEN) { + if ((1UL == bCM_ADC1->ISR_b.EOCBF) && (0UL != (u32VSSEL142 & BIT_MASK_01))) { + ADC1_SeqB_IrqHandler(); + } + } + /* ADC unit.1 ADW channel compare */ + if (1UL == bCM_ADC1->AWDCR_b.AWDIEN) { + if ((0UL != (CM_ADC1->AWDSR & 0x1FFFFU)) && (0UL != (u32VSSEL142 & BIT_MASK_02))) { + ADC1_ChCmp_IrqHandler(); + } + } + /* ADC unit.1 AWD Seq. compare */ + if (1UL == bCM_ADC1->AWDCR_b.AWDIEN) { + if ((0UL != (CM_ADC1->AWDSR & 0x1FFFFU)) && (0UL != (u32VSSEL142 & BIT_MASK_03))) { + ADC1_SeqCmp_IrqHandler(); + } + } + + /* ADC unit.2 seq. A */ + if (1UL == bCM_ADC2->ICR_b.EOCAIEN) { + if ((1UL == bCM_ADC2->ISR_b.EOCAF) && (0UL != (u32VSSEL142 & BIT_MASK_04))) { + ADC2_SeqA_IrqHandler(); + } + } + /* ADC unit.2 seq. B */ + if (1UL == bCM_ADC2->ICR_b.EOCBIEN) { + if ((1UL == bCM_ADC2->ISR_b.EOCBF) && (0UL != (u32VSSEL142 & BIT_MASK_05))) { + ADC2_SeqB_IrqHandler(); + } + } + /* ADC unit.2 ADW channel compare */ + if (1UL == bCM_ADC2->AWDCR_b.AWDIEN) { + if ((0UL != (CM_ADC2->AWDSR & 0x1FFU)) && (0UL != (u32VSSEL142 & BIT_MASK_06))) { + ADC2_ChCmp_IrqHandler(); + } + } + /* ADC unit.2 AWD Seq. compare */ + if (1UL == bCM_ADC2->AWDCR_b.AWDIEN) { + if ((0UL != (CM_ADC2->AWDSR & 0x1FFU)) && (0UL != (u32VSSEL142 & BIT_MASK_07))) { + ADC2_SeqCmp_IrqHandler(); + } + } + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.143 share IRQ handler + * @param None + * @retval None + */ +void IRQ143_Handler(void) +{ + uint8_t RTIF; + uint8_t RTIE; + uint8_t ERRINT; + uint8_t TTCFG; + uint16_t NORINTST; + uint16_t NORINTSGEN; + uint16_t ERRINTST; + uint16_t ERRINTSGEN; + uint32_t u32VSSEL143 = CM_INTC->VSSEL143; + + /* SDIO Ch.1 */ + if (0UL != (u32VSSEL143 & BIT_MASK_02)) { + NORINTST = CM_SDIOC1->NORINTST; + NORINTSGEN = CM_SDIOC1->NORINTSGEN; + ERRINTST = CM_SDIOC1->ERRINTST; + ERRINTSGEN = CM_SDIOC1->ERRINTSGEN; + + if ((0U != (NORINTST & NORINTSGEN & 0x01F7U)) || (0U != (ERRINTST & ERRINTSGEN & 0x017FU))) { + SDIOC1_IrqHandler(); + } + } + + /* SDIO Ch.2 */ + if (0UL != (u32VSSEL143 & BIT_MASK_05)) { + NORINTST = CM_SDIOC2->NORINTST; + NORINTSGEN = CM_SDIOC2->NORINTSGEN; + ERRINTST = CM_SDIOC2->ERRINTST; + ERRINTSGEN = CM_SDIOC2->ERRINTSGEN; + + if ((0U != (NORINTST & NORINTSGEN & 0x01F7U)) || (0U != (ERRINTST & ERRINTSGEN & 0x017FU))) { + SDIOC2_IrqHandler(); + } + } + + /* CAN */ + if (0UL != (u32VSSEL143 & BIT_MASK_06)) { + RTIF = CM_CAN->RTIF; + RTIE = CM_CAN->RTIE; + ERRINT = CM_CAN->ERRINT; + TTCFG = CM_CAN->TTCFG; + if (((0U != (TTCFG & BIT_MASK_05)) || \ + (0U != (RTIF & BIT_MASK_00)) || \ + (0U != (RTIF & RTIE & 0xFEU)) || \ + ((0U != (ERRINT & BIT_MASK_00)) && (0U != (ERRINT & BIT_MASK_01))) || \ + ((0U != (ERRINT & BIT_MASK_02)) && (0U != (ERRINT & BIT_MASK_03))) || \ + ((0U != (ERRINT & BIT_MASK_04)) && (0U != (ERRINT & BIT_MASK_05))) || \ + ((0U != (TTCFG & BIT_MASK_03)) && (0U != (TTCFG & BIT_MASK_04))) || \ + ((0U != (TTCFG & BIT_MASK_06)) && (0U != (TTCFG & BIT_MASK_07)))) != 0U) { + CAN_IrqHandler(); + } + } + + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} +/** + * @} + */ + +/** + * @defgroup Share_Interrupts_Weakdef_Prototypes Share Interrupts weak function prototypes + * @{ + */ +__WEAKDEF void EXTINT00_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT01_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT02_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT03_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT04_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT05_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT06_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT07_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT08_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT09_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT10_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT11_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT12_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT13_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT14_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT15_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_TC0_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_TC1_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_TC2_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_TC3_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_TC0_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_TC1_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_TC2_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_TC3_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_BTC0_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_BTC1_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_BTC2_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_BTC3_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_BTC0_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_BTC1_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_BTC2_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_BTC3_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_Error0_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_Error1_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_Error2_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_Error3_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_Error0_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_Error1_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_Error2_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_Error3_IrqHandler(void) +{ +} +__WEAKDEF void EFM_ProgramEraseError_IrqHandler(void) +{ +} +__WEAKDEF void EFM_ColError_IrqHandler(void) +{ +} +__WEAKDEF void EFM_OpEnd_IrqHandler(void) +{ +} +__WEAKDEF void QSPI_Error_IrqHandler(void) +{ +} +__WEAKDEF void DCU1_IrqHandler(void) +{ +} +__WEAKDEF void DCU2_IrqHandler(void) +{ +} +__WEAKDEF void DCU3_IrqHandler(void) +{ +} +__WEAKDEF void DCU4_IrqHandler(void) +{ +} +__WEAKDEF void TMR0_1_CmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR0_1_CmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR0_2_CmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR0_2_CmpB_IrqHandler(void) +{ +} +__WEAKDEF void CLK_XtalStop_IrqHandler(void) +{ +} +__WEAKDEF void PWC_WakeupTimer_IrqHandler(void) +{ +} +__WEAKDEF void SWDT_IrqHandler(void) +{ +} +__WEAKDEF void WDT_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GDte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_SCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_SCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GDte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_SCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_SCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GDte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_SCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_SCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_1_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_1_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_1_Cmp_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_2_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_2_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_2_Cmp_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_3_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_3_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_3_Cmp_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_4_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_4_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_4_Cmp_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_5_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_5_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_5_Cmp_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_6_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_6_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_6_Cmp_IrqHandler(void) +{ +} +__WEAKDEF void USBFS_Global_IrqHandler(void) +{ +} +__WEAKDEF void USART1_RxError_IrqHandler(void) +{ +} +__WEAKDEF void USART1_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void USART1_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART1_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void USART1_RxTO_IrqHandler(void) +{ +} +__WEAKDEF void USART2_RxError_IrqHandler(void) +{ +} +__WEAKDEF void USART2_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void USART2_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART2_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void USART2_RxTO_IrqHandler(void) +{ +} +__WEAKDEF void USART3_RxError_IrqHandler(void) +{ +} +__WEAKDEF void USART3_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void USART3_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART3_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void USART3_RxTO_IrqHandler(void) +{ +} +__WEAKDEF void USART4_RxError_IrqHandler(void) +{ +} +__WEAKDEF void USART4_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void USART4_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART4_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void USART4_RxTO_IrqHandler(void) +{ +} +__WEAKDEF void SPI1_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void SPI1_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void SPI1_Error_IrqHandler(void) +{ +} +__WEAKDEF void SPI1_Idle_IrqHandler(void) +{ +} +__WEAKDEF void SPI2_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void SPI2_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void SPI2_Error_IrqHandler(void) +{ +} +__WEAKDEF void SPI2_Idle_IrqHandler(void) +{ +} +__WEAKDEF void SPI3_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void SPI3_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void SPI3_Error_IrqHandler(void) +{ +} +__WEAKDEF void SPI3_Idle_IrqHandler(void) +{ +} +__WEAKDEF void SPI4_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void SPI4_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void SPI4_Error_IrqHandler(void) +{ +} +__WEAKDEF void SPI4_Idle_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpUH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpUL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpVH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpVL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpWH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpWL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_ReloadU_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_ReloadV_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_ReloadW_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpUH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpUL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpVH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpVL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpWH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpWL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_ReloadU_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_ReloadV_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_ReloadW_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpUH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpUL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpVH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpVL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpWH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpWL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_ReloadU_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_ReloadV_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_ReloadW_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR0_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR1_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR2_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR3_IrqHandler(void) +{ +} +__WEAKDEF void I2S1_Tx_IrqHandler(void) +{ +} +__WEAKDEF void I2S1_Rx_IrqHandler(void) +{ +} +__WEAKDEF void I2S1_Error_IrqHandler(void) +{ +} +__WEAKDEF void I2S2_Tx_IrqHandler(void) +{ +} +__WEAKDEF void I2S2_Rx_IrqHandler(void) +{ +} +__WEAKDEF void I2S2_Error_IrqHandler(void) +{ +} +__WEAKDEF void I2S3_Tx_IrqHandler(void) +{ +} +__WEAKDEF void I2S3_Rx_IrqHandler(void) +{ +} +__WEAKDEF void I2S3_Error_IrqHandler(void) +{ +} +__WEAKDEF void I2S4_Tx_IrqHandler(void) +{ +} +__WEAKDEF void I2S4_Rx_IrqHandler(void) +{ +} +__WEAKDEF void I2S4_Error_IrqHandler(void) +{ +} +__WEAKDEF void I2C1_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void I2C1_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void I2C1_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void I2C1_EE_IrqHandler(void) +{ +} +__WEAKDEF void I2C2_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void I2C2_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void I2C2_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void I2C2_EE_IrqHandler(void) +{ +} +__WEAKDEF void I2C3_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void I2C3_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void I2C3_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void I2C3_EE_IrqHandler(void) +{ +} +__WEAKDEF void PWC_LVD1_IrqHandler(void) +{ +} +__WEAKDEF void PWC_LVD2_IrqHandler(void) +{ +} +__WEAKDEF void FCM_Error_IrqHandler(void) +{ +} +__WEAKDEF void FCM_End_IrqHandler(void) +{ +} +__WEAKDEF void FCM_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void ADC1_SeqA_IrqHandler(void) +{ +} +__WEAKDEF void ADC1_SeqB_IrqHandler(void) +{ +} +__WEAKDEF void ADC1_ChCmp_IrqHandler(void) +{ +} +__WEAKDEF void ADC1_SeqCmp_IrqHandler(void) +{ +} +__WEAKDEF void ADC2_SeqA_IrqHandler(void) +{ +} +__WEAKDEF void ADC2_SeqB_IrqHandler(void) +{ +} +__WEAKDEF void ADC2_ChCmp_IrqHandler(void) +{ +} +__WEAKDEF void ADC2_SeqCmp_IrqHandler(void) +{ +} +__WEAKDEF void SDIOC1_IrqHandler(void) +{ +} +__WEAKDEF void SDIOC2_IrqHandler(void) +{ +} +__WEAKDEF void CAN_IrqHandler(void) +{ +} +/** + * @} + */ + +#endif /* LL_INTERRUPTS_SHARE_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/mcu/startup/startup_hc32f460.s b/mcu/startup/startup_hc32f460.s new file mode 100644 index 0000000..560b273 --- /dev/null +++ b/mcu/startup/startup_hc32f460.s @@ -0,0 +1,618 @@ +;/** +; ****************************************************************************** +; @file startup_hc32f460.s +; @brief Startup for MDK. +; verbatim +; Change Logs: +; Date Author Notes +; 2022-03-31 CDT First version +; endverbatim +; ***************************************************************************** +; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; ****************************************************************************** +; */ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Stack_Size EQU 0x00000C00 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Peripheral Interrupts + DCD IRQ000_Handler + DCD IRQ001_Handler + DCD IRQ002_Handler + DCD IRQ003_Handler + DCD IRQ004_Handler + DCD IRQ005_Handler + DCD IRQ006_Handler + DCD IRQ007_Handler + DCD IRQ008_Handler + DCD IRQ009_Handler + DCD IRQ010_Handler + DCD IRQ011_Handler + DCD IRQ012_Handler + DCD IRQ013_Handler + DCD IRQ014_Handler + DCD IRQ015_Handler + DCD IRQ016_Handler + DCD IRQ017_Handler + DCD IRQ018_Handler + DCD IRQ019_Handler + DCD IRQ020_Handler + DCD IRQ021_Handler + DCD IRQ022_Handler + DCD IRQ023_Handler + DCD IRQ024_Handler + DCD IRQ025_Handler + DCD IRQ026_Handler + DCD IRQ027_Handler + DCD IRQ028_Handler + DCD IRQ029_Handler + DCD IRQ030_Handler + DCD IRQ031_Handler + DCD IRQ032_Handler + DCD IRQ033_Handler + DCD IRQ034_Handler + DCD IRQ035_Handler + DCD IRQ036_Handler + DCD IRQ037_Handler + DCD IRQ038_Handler + DCD IRQ039_Handler + DCD IRQ040_Handler + DCD IRQ041_Handler + DCD IRQ042_Handler + DCD IRQ043_Handler + DCD IRQ044_Handler + DCD IRQ045_Handler + DCD IRQ046_Handler + DCD IRQ047_Handler + DCD IRQ048_Handler + DCD IRQ049_Handler + DCD IRQ050_Handler + DCD IRQ051_Handler + DCD IRQ052_Handler + DCD IRQ053_Handler + DCD IRQ054_Handler + DCD IRQ055_Handler + DCD IRQ056_Handler + DCD IRQ057_Handler + DCD IRQ058_Handler + DCD IRQ059_Handler + DCD IRQ060_Handler + DCD IRQ061_Handler + DCD IRQ062_Handler + DCD IRQ063_Handler + DCD IRQ064_Handler + DCD IRQ065_Handler + DCD IRQ066_Handler + DCD IRQ067_Handler + DCD IRQ068_Handler + DCD IRQ069_Handler + DCD IRQ070_Handler + DCD IRQ071_Handler + DCD IRQ072_Handler + DCD IRQ073_Handler + DCD IRQ074_Handler + DCD IRQ075_Handler + DCD IRQ076_Handler + DCD IRQ077_Handler + DCD IRQ078_Handler + DCD IRQ079_Handler + DCD IRQ080_Handler + DCD IRQ081_Handler + DCD IRQ082_Handler + DCD IRQ083_Handler + DCD IRQ084_Handler + DCD IRQ085_Handler + DCD IRQ086_Handler + DCD IRQ087_Handler + DCD IRQ088_Handler + DCD IRQ089_Handler + DCD IRQ090_Handler + DCD IRQ091_Handler + DCD IRQ092_Handler + DCD IRQ093_Handler + DCD IRQ094_Handler + DCD IRQ095_Handler + DCD IRQ096_Handler + DCD IRQ097_Handler + DCD IRQ098_Handler + DCD IRQ099_Handler + DCD IRQ100_Handler + DCD IRQ101_Handler + DCD IRQ102_Handler + DCD IRQ103_Handler + DCD IRQ104_Handler + DCD IRQ105_Handler + DCD IRQ106_Handler + DCD IRQ107_Handler + DCD IRQ108_Handler + DCD IRQ109_Handler + DCD IRQ110_Handler + DCD IRQ111_Handler + DCD IRQ112_Handler + DCD IRQ113_Handler + DCD IRQ114_Handler + DCD IRQ115_Handler + DCD IRQ116_Handler + DCD IRQ117_Handler + DCD IRQ118_Handler + DCD IRQ119_Handler + DCD IRQ120_Handler + DCD IRQ121_Handler + DCD IRQ122_Handler + DCD IRQ123_Handler + DCD IRQ124_Handler + DCD IRQ125_Handler + DCD IRQ126_Handler + DCD IRQ127_Handler + DCD IRQ128_Handler + DCD IRQ129_Handler + DCD IRQ130_Handler + DCD IRQ131_Handler + DCD IRQ132_Handler + DCD IRQ133_Handler + DCD IRQ134_Handler + DCD IRQ135_Handler + DCD IRQ136_Handler + DCD IRQ137_Handler + DCD IRQ138_Handler + DCD IRQ139_Handler + DCD IRQ140_Handler + DCD IRQ141_Handler + DCD IRQ142_Handler + DCD IRQ143_Handler + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main +SET_SRAM3_WAIT + LDR R0, =0x40050804 + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x40050800 + MOV R1, #0x1100 + STR R1, [R0] + + LDR R0, =0x40050804 + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT IRQ000_Handler [WEAK] + EXPORT IRQ001_Handler [WEAK] + EXPORT IRQ002_Handler [WEAK] + EXPORT IRQ003_Handler [WEAK] + EXPORT IRQ004_Handler [WEAK] + EXPORT IRQ005_Handler [WEAK] + EXPORT IRQ006_Handler [WEAK] + EXPORT IRQ007_Handler [WEAK] + EXPORT IRQ008_Handler [WEAK] + EXPORT IRQ009_Handler [WEAK] + EXPORT IRQ010_Handler [WEAK] + EXPORT IRQ011_Handler [WEAK] + EXPORT IRQ012_Handler [WEAK] + EXPORT IRQ013_Handler [WEAK] + EXPORT IRQ014_Handler [WEAK] + EXPORT IRQ015_Handler [WEAK] + EXPORT IRQ016_Handler [WEAK] + EXPORT IRQ017_Handler [WEAK] + EXPORT IRQ018_Handler [WEAK] + EXPORT IRQ019_Handler [WEAK] + EXPORT IRQ020_Handler [WEAK] + EXPORT IRQ021_Handler [WEAK] + EXPORT IRQ022_Handler [WEAK] + EXPORT IRQ023_Handler [WEAK] + EXPORT IRQ024_Handler [WEAK] + EXPORT IRQ025_Handler [WEAK] + EXPORT IRQ026_Handler [WEAK] + EXPORT IRQ027_Handler [WEAK] + EXPORT IRQ028_Handler [WEAK] + EXPORT IRQ029_Handler [WEAK] + EXPORT IRQ030_Handler [WEAK] + EXPORT IRQ031_Handler [WEAK] + EXPORT IRQ032_Handler [WEAK] + EXPORT IRQ033_Handler [WEAK] + EXPORT IRQ034_Handler [WEAK] + EXPORT IRQ035_Handler [WEAK] + EXPORT IRQ036_Handler [WEAK] + EXPORT IRQ037_Handler [WEAK] + EXPORT IRQ038_Handler [WEAK] + EXPORT IRQ039_Handler [WEAK] + EXPORT IRQ040_Handler [WEAK] + EXPORT IRQ041_Handler [WEAK] + EXPORT IRQ042_Handler [WEAK] + EXPORT IRQ043_Handler [WEAK] + EXPORT IRQ044_Handler [WEAK] + EXPORT IRQ045_Handler [WEAK] + EXPORT IRQ046_Handler [WEAK] + EXPORT IRQ047_Handler [WEAK] + EXPORT IRQ048_Handler [WEAK] + EXPORT IRQ049_Handler [WEAK] + EXPORT IRQ050_Handler [WEAK] + EXPORT IRQ051_Handler [WEAK] + EXPORT IRQ052_Handler [WEAK] + EXPORT IRQ053_Handler [WEAK] + EXPORT IRQ054_Handler [WEAK] + EXPORT IRQ055_Handler [WEAK] + EXPORT IRQ056_Handler [WEAK] + EXPORT IRQ057_Handler [WEAK] + EXPORT IRQ058_Handler [WEAK] + EXPORT IRQ059_Handler [WEAK] + EXPORT IRQ060_Handler [WEAK] + EXPORT IRQ061_Handler [WEAK] + EXPORT IRQ062_Handler [WEAK] + EXPORT IRQ063_Handler [WEAK] + EXPORT IRQ064_Handler [WEAK] + EXPORT IRQ065_Handler [WEAK] + EXPORT IRQ066_Handler [WEAK] + EXPORT IRQ067_Handler [WEAK] + EXPORT IRQ068_Handler [WEAK] + EXPORT IRQ069_Handler [WEAK] + EXPORT IRQ070_Handler [WEAK] + EXPORT IRQ071_Handler [WEAK] + EXPORT IRQ072_Handler [WEAK] + EXPORT IRQ073_Handler [WEAK] + EXPORT IRQ074_Handler [WEAK] + EXPORT IRQ075_Handler [WEAK] + EXPORT IRQ076_Handler [WEAK] + EXPORT IRQ077_Handler [WEAK] + EXPORT IRQ078_Handler [WEAK] + EXPORT IRQ079_Handler [WEAK] + EXPORT IRQ080_Handler [WEAK] + EXPORT IRQ081_Handler [WEAK] + EXPORT IRQ082_Handler [WEAK] + EXPORT IRQ083_Handler [WEAK] + EXPORT IRQ084_Handler [WEAK] + EXPORT IRQ085_Handler [WEAK] + EXPORT IRQ086_Handler [WEAK] + EXPORT IRQ087_Handler [WEAK] + EXPORT IRQ088_Handler [WEAK] + EXPORT IRQ089_Handler [WEAK] + EXPORT IRQ090_Handler [WEAK] + EXPORT IRQ091_Handler [WEAK] + EXPORT IRQ092_Handler [WEAK] + EXPORT IRQ093_Handler [WEAK] + EXPORT IRQ094_Handler [WEAK] + EXPORT IRQ095_Handler [WEAK] + EXPORT IRQ096_Handler [WEAK] + EXPORT IRQ097_Handler [WEAK] + EXPORT IRQ098_Handler [WEAK] + EXPORT IRQ099_Handler [WEAK] + EXPORT IRQ100_Handler [WEAK] + EXPORT IRQ101_Handler [WEAK] + EXPORT IRQ102_Handler [WEAK] + EXPORT IRQ103_Handler [WEAK] + EXPORT IRQ104_Handler [WEAK] + EXPORT IRQ105_Handler [WEAK] + EXPORT IRQ106_Handler [WEAK] + EXPORT IRQ107_Handler [WEAK] + EXPORT IRQ108_Handler [WEAK] + EXPORT IRQ109_Handler [WEAK] + EXPORT IRQ110_Handler [WEAK] + EXPORT IRQ111_Handler [WEAK] + EXPORT IRQ112_Handler [WEAK] + EXPORT IRQ113_Handler [WEAK] + EXPORT IRQ114_Handler [WEAK] + EXPORT IRQ115_Handler [WEAK] + EXPORT IRQ116_Handler [WEAK] + EXPORT IRQ117_Handler [WEAK] + EXPORT IRQ118_Handler [WEAK] + EXPORT IRQ119_Handler [WEAK] + EXPORT IRQ120_Handler [WEAK] + EXPORT IRQ121_Handler [WEAK] + EXPORT IRQ122_Handler [WEAK] + EXPORT IRQ123_Handler [WEAK] + EXPORT IRQ124_Handler [WEAK] + EXPORT IRQ125_Handler [WEAK] + EXPORT IRQ126_Handler [WEAK] + EXPORT IRQ127_Handler [WEAK] + EXPORT IRQ128_Handler [WEAK] + EXPORT IRQ129_Handler [WEAK] + EXPORT IRQ130_Handler [WEAK] + EXPORT IRQ131_Handler [WEAK] + EXPORT IRQ132_Handler [WEAK] + EXPORT IRQ133_Handler [WEAK] + EXPORT IRQ134_Handler [WEAK] + EXPORT IRQ135_Handler [WEAK] + EXPORT IRQ136_Handler [WEAK] + EXPORT IRQ137_Handler [WEAK] + EXPORT IRQ138_Handler [WEAK] + EXPORT IRQ139_Handler [WEAK] + EXPORT IRQ140_Handler [WEAK] + EXPORT IRQ141_Handler [WEAK] + EXPORT IRQ142_Handler [WEAK] + EXPORT IRQ143_Handler [WEAK] + +IRQ000_Handler +IRQ001_Handler +IRQ002_Handler +IRQ003_Handler +IRQ004_Handler +IRQ005_Handler +IRQ006_Handler +IRQ007_Handler +IRQ008_Handler +IRQ009_Handler +IRQ010_Handler +IRQ011_Handler +IRQ012_Handler +IRQ013_Handler +IRQ014_Handler +IRQ015_Handler +IRQ016_Handler +IRQ017_Handler +IRQ018_Handler +IRQ019_Handler +IRQ020_Handler +IRQ021_Handler +IRQ022_Handler +IRQ023_Handler +IRQ024_Handler +IRQ025_Handler +IRQ026_Handler +IRQ027_Handler +IRQ028_Handler +IRQ029_Handler +IRQ030_Handler +IRQ031_Handler +IRQ032_Handler +IRQ033_Handler +IRQ034_Handler +IRQ035_Handler +IRQ036_Handler +IRQ037_Handler +IRQ038_Handler +IRQ039_Handler +IRQ040_Handler +IRQ041_Handler +IRQ042_Handler +IRQ043_Handler +IRQ044_Handler +IRQ045_Handler +IRQ046_Handler +IRQ047_Handler +IRQ048_Handler +IRQ049_Handler +IRQ050_Handler +IRQ051_Handler +IRQ052_Handler +IRQ053_Handler +IRQ054_Handler +IRQ055_Handler +IRQ056_Handler +IRQ057_Handler +IRQ058_Handler +IRQ059_Handler +IRQ060_Handler +IRQ061_Handler +IRQ062_Handler +IRQ063_Handler +IRQ064_Handler +IRQ065_Handler +IRQ066_Handler +IRQ067_Handler +IRQ068_Handler +IRQ069_Handler +IRQ070_Handler +IRQ071_Handler +IRQ072_Handler +IRQ073_Handler +IRQ074_Handler +IRQ075_Handler +IRQ076_Handler +IRQ077_Handler +IRQ078_Handler +IRQ079_Handler +IRQ080_Handler +IRQ081_Handler +IRQ082_Handler +IRQ083_Handler +IRQ084_Handler +IRQ085_Handler +IRQ086_Handler +IRQ087_Handler +IRQ088_Handler +IRQ089_Handler +IRQ090_Handler +IRQ091_Handler +IRQ092_Handler +IRQ093_Handler +IRQ094_Handler +IRQ095_Handler +IRQ096_Handler +IRQ097_Handler +IRQ098_Handler +IRQ099_Handler +IRQ100_Handler +IRQ101_Handler +IRQ102_Handler +IRQ103_Handler +IRQ104_Handler +IRQ105_Handler +IRQ106_Handler +IRQ107_Handler +IRQ108_Handler +IRQ109_Handler +IRQ110_Handler +IRQ111_Handler +IRQ112_Handler +IRQ113_Handler +IRQ114_Handler +IRQ115_Handler +IRQ116_Handler +IRQ117_Handler +IRQ118_Handler +IRQ119_Handler +IRQ120_Handler +IRQ121_Handler +IRQ122_Handler +IRQ123_Handler +IRQ124_Handler +IRQ125_Handler +IRQ126_Handler +IRQ127_Handler +IRQ128_Handler +IRQ129_Handler +IRQ130_Handler +IRQ131_Handler +IRQ132_Handler +IRQ133_Handler +IRQ134_Handler +IRQ135_Handler +IRQ136_Handler +IRQ137_Handler +IRQ138_Handler +IRQ139_Handler +IRQ140_Handler +IRQ141_Handler +IRQ142_Handler +IRQ143_Handler + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/pthreads/Makefile b/pthreads/Makefile new file mode 100644 index 0000000..ff573ef --- /dev/null +++ b/pthreads/Makefile @@ -0,0 +1,9 @@ +CFLAGS=-O -Wuninitialized -Werror + +all: example-codelock example-buffer example-small + +example-codelock: example-codelock.c pt.h lc.h + +example-buffer: example-buffer.c pt.h lc.h + +example-small: example-small.c pt.h lc.h diff --git a/pthreads/README b/pthreads/README new file mode 100644 index 0000000..eeace5d --- /dev/null +++ b/pthreads/README @@ -0,0 +1,51 @@ +Protothreads are extremely lightweight stackless threads designed for +severely memory constrained systems such as small embedded systems or +sensor network nodes. Protothreads can be used with or without an +underlying operating system. + +Protothreads provides a blocking context on top of an event-driven +system, without the overhead of per-thread stacks. The purpose of +protothreads is to implement sequential flow of control without +complex state machines or full multi-threading. + +Main features: + + * No machine specific code - the protothreads library is pure C + * Does not use error-prone functions such as longjmp() + * Very small RAM overhead - only two bytes per protothread + * Can be used with or without an OS + * Provides blocking wait without full multi-threading or + stack-switching + * Freely available under a BSD-like open source license + +Example applications: + + * Memory constrained systems + * Event-driven protocol stacks + * Small embedded systems + * Sensor network nodes + +The protothreads library is released under an open source BSD-style +license that allows for both non-commercial and commercial usage. The +only requirement is that credit is given. + +The protothreads library was written by Adam Dunkels +with support from Oliver Schmidt . + +More information and new versions can be found at the protothreads +homepage: + http://www.sics.se/~adam/pt/ + +Documentation can be found in the doc/ subdirectory. + +Two example programs illustrating the use of protothreads can be found +in this directory: + + example-small.c A small example showing how to use protothreads + example-buffer.c The bounded buffer problem with protothreads + example-codelock.c A code lock with simulated key input + +To compile the examples, simply run "make". + + +Adam Dunkels, 3 June 2006 diff --git a/pthreads/README-VISUAL-C++.txt b/pthreads/README-VISUAL-C++.txt new file mode 100644 index 0000000..3b09a69 --- /dev/null +++ b/pthreads/README-VISUAL-C++.txt @@ -0,0 +1,5 @@ +Protothreads can in some cases fail to compile under Visual C++ +version 6.0 due to a bug in the compiler. See the following page for a +solution to the problem: + +http://support.microsoft.com/default.aspx?scid=kb;en-us;199057 diff --git a/pthreads/doc/Doxyfile b/pthreads/doc/Doxyfile new file mode 100644 index 0000000..cecf583 --- /dev/null +++ b/pthreads/doc/Doxyfile @@ -0,0 +1,229 @@ +# Doxyfile 1.4.6 + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- +PROJECT_NAME = "The Protothreads Library 1.4" +PROJECT_NUMBER = +OUTPUT_DIRECTORY = . +CREATE_SUBDIRS = NO +OUTPUT_LANGUAGE = English +USE_WINDOWS_ENCODING = NO +BRIEF_MEMBER_DESC = YES +REPEAT_BRIEF = YES +ABBREVIATE_BRIEF = +ALWAYS_DETAILED_SEC = NO +INLINE_INHERITED_MEMB = NO +FULL_PATH_NAMES = YES +STRIP_FROM_PATH = ../ +STRIP_FROM_INC_PATH = +SHORT_NAMES = YES +JAVADOC_AUTOBRIEF = YES +MULTILINE_CPP_IS_BRIEF = NO +DETAILS_AT_TOP = YES +INHERIT_DOCS = YES +SEPARATE_MEMBER_PAGES = NO +TAB_SIZE = 8 +ALIASES = +OPTIMIZE_OUTPUT_FOR_C = YES +OPTIMIZE_OUTPUT_JAVA = NO +BUILTIN_STL_SUPPORT = NO +DISTRIBUTE_GROUP_DOC = NO +SUBGROUPING = YES +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- +EXTRACT_ALL = NO +EXTRACT_PRIVATE = NO +EXTRACT_STATIC = NO +EXTRACT_LOCAL_CLASSES = NO +EXTRACT_LOCAL_METHODS = NO +HIDE_UNDOC_MEMBERS = YES +HIDE_UNDOC_CLASSES = YES +HIDE_FRIEND_COMPOUNDS = NO +HIDE_IN_BODY_DOCS = NO +INTERNAL_DOCS = NO +CASE_SENSE_NAMES = YES +HIDE_SCOPE_NAMES = NO +SHOW_INCLUDE_FILES = YES +INLINE_INFO = YES +SORT_MEMBER_DOCS = YES +SORT_BRIEF_DOCS = NO +SORT_BY_SCOPE_NAME = NO +GENERATE_TODOLIST = YES +GENERATE_TESTLIST = YES +GENERATE_BUGLIST = NO +GENERATE_DEPRECATEDLIST= NO +ENABLED_SECTIONS = +MAX_INITIALIZER_LINES = 30 +SHOW_USED_FILES = NO +SHOW_DIRECTORIES = NO +FILE_VERSION_FILTER = +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- +QUIET = NO +WARNINGS = YES +WARN_IF_UNDOCUMENTED = YES +WARN_IF_DOC_ERROR = YES +WARN_NO_PARAMDOC = NO +WARN_FORMAT = "$file:$line: $text" +WARN_LOGFILE = +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- +INPUT = pt-mainpage.txt \ + pt-doc.txt \ + ../pt.h \ + ../pt-sem.h \ + ../lc.h \ + ../lc-switch.h \ + ../lc-addrlabels.h +FILE_PATTERNS = +RECURSIVE = NO +EXCLUDE = +EXCLUDE_SYMLINKS = NO +EXCLUDE_PATTERNS = +EXAMPLE_PATH = .. +EXAMPLE_PATTERNS = +EXAMPLE_RECURSIVE = NO +IMAGE_PATH = +INPUT_FILTER = +FILTER_PATTERNS = +FILTER_SOURCE_FILES = NO +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- +SOURCE_BROWSER = YES +INLINE_SOURCES = YES +STRIP_CODE_COMMENTS = NO +REFERENCED_BY_RELATION = YES +REFERENCES_RELATION = YES +USE_HTAGS = NO +VERBATIM_HEADERS = YES +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- +ALPHABETICAL_INDEX = NO +COLS_IN_ALPHA_INDEX = 5 +IGNORE_PREFIX = +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- +GENERATE_HTML = YES +HTML_OUTPUT = html +HTML_FILE_EXTENSION = .html +HTML_HEADER = +HTML_FOOTER = +HTML_STYLESHEET = +HTML_ALIGN_MEMBERS = YES +GENERATE_HTMLHELP = YES +CHM_FILE = +HHC_LOCATION = +GENERATE_CHI = NO +BINARY_TOC = NO +TOC_EXPAND = NO +DISABLE_INDEX = NO +ENUM_VALUES_PER_LINE = 4 +GENERATE_TREEVIEW = YES +TREEVIEW_WIDTH = 250 +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- +GENERATE_LATEX = YES +LATEX_OUTPUT = latex +LATEX_CMD_NAME = latex +MAKEINDEX_CMD_NAME = makeindex +COMPACT_LATEX = YES +PAPER_TYPE = a4 +EXTRA_PACKAGES = +LATEX_HEADER = header.tex +PDF_HYPERLINKS = YES +USE_PDFLATEX = YES +LATEX_BATCHMODE = NO +LATEX_HIDE_INDICES = NO +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- +GENERATE_RTF = NO +RTF_OUTPUT = rtf +COMPACT_RTF = NO +RTF_HYPERLINKS = NO +RTF_STYLESHEET_FILE = +RTF_EXTENSIONS_FILE = +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- +GENERATE_MAN = NO +MAN_OUTPUT = man +MAN_EXTENSION = .3 +MAN_LINKS = NO +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- +GENERATE_XML = NO +XML_OUTPUT = xml +XML_SCHEMA = +XML_DTD = +XML_PROGRAMLISTING = YES +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- +GENERATE_AUTOGEN_DEF = NO +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- +GENERATE_PERLMOD = NO +PERLMOD_LATEX = NO +PERLMOD_PRETTY = YES +PERLMOD_MAKEVAR_PREFIX = +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- +ENABLE_PREPROCESSING = YES +MACRO_EXPANSION = NO +EXPAND_ONLY_PREDEF = NO +SEARCH_INCLUDES = YES +INCLUDE_PATH = +INCLUDE_FILE_PATTERNS = +PREDEFINED = DOXYGEN +EXPAND_AS_DEFINED = +SKIP_FUNCTION_MACROS = YES +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- +TAGFILES = +GENERATE_TAGFILE = +ALLEXTERNALS = NO +EXTERNAL_GROUPS = YES +PERL_PATH = /usr/bin/perl +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- +CLASS_DIAGRAMS = NO +HIDE_UNDOC_RELATIONS = NO +HAVE_DOT = NO +CLASS_GRAPH = NO +COLLABORATION_GRAPH = YES +GROUP_GRAPHS = YES +UML_LOOK = NO +TEMPLATE_RELATIONS = NO +INCLUDE_GRAPH = NO +INCLUDED_BY_GRAPH = YES +CALL_GRAPH = YES +GRAPHICAL_HIERARCHY = YES +DIRECTORY_GRAPH = YES +DOT_IMAGE_FORMAT = png +DOT_PATH = +DOTFILE_DIRS = +MAX_DOT_GRAPH_WIDTH = 1024 +MAX_DOT_GRAPH_HEIGHT = 1024 +MAX_DOT_GRAPH_DEPTH = 0 +DOT_TRANSPARENT = NO +DOT_MULTI_TARGETS = NO +GENERATE_LEGEND = YES +DOT_CLEANUP = YES +#--------------------------------------------------------------------------- +# Configuration::additions related to the search engine +#--------------------------------------------------------------------------- +SEARCHENGINE = NO diff --git a/pthreads/doc/Makefile b/pthreads/doc/Makefile new file mode 100644 index 0000000..fd0c7d1 --- /dev/null +++ b/pthreads/doc/Makefile @@ -0,0 +1,7 @@ +dox: + doxygen Doxyfile + + +pdf: dox + (cd latex; $(MAKE) refman.pdf) + mv latex/refman.pdf pt-refman.pdf \ No newline at end of file diff --git a/pthreads/doc/header.tex b/pthreads/doc/header.tex new file mode 100644 index 0000000..5899653 --- /dev/null +++ b/pthreads/doc/header.tex @@ -0,0 +1,52 @@ +\documentclass[a4paper]{article} +\usepackage{a4wide} +\usepackage{makeidx} +\usepackage{fancyhdr} +\usepackage{graphicx} +\usepackage{multicol} +\usepackage{float} +\usepackage{textcomp} +\usepackage{alltt} +\usepackage{times} +\usepackage{epsfig} +\ifx\pdfoutput\undefined +\usepackage[ps2pdf, + pagebackref=true, + colorlinks=true, + linkcolor=blue + ]{hyperref} +\usepackage{pspicture} +\else +\usepackage[pdftex, + pagebackref=true, + colorlinks=true, + linkcolor=blue + ]{hyperref} +\fi +\usepackage{doxygen} +\makeindex +\setcounter{tocdepth}{1} +\renewcommand{\footrulewidth}{0.4pt} +\begin{document} +\begin{titlepage} +\vspace*{5cm} +\begin{center} +{\Huge Protothreads}\\ +\vspace*{1cm} +{\LARGE The Protothreads Library 1.3 Reference Manual}\\ +\vspace*{3cm} +{\Large June 2006}\\ +\vspace*{2cm} +\includegraphics[width=6cm]{../sicslogo.pdf}\\ +\vspace*{1cm} +{\Large Adam Dunkels}\\ +{\Large \texttt{adam@sics.se}}\\ +\vspace*{1cm} +{\LARGE Swedish Institute of Computer Science}\\ +\vspace*{0.5cm} + +\end{center} +\end{titlepage} +\pagenumbering{roman} +\tableofcontents +\pagenumbering{arabic} diff --git a/pthreads/doc/html/doxygen.css b/pthreads/doc/html/doxygen.css new file mode 100644 index 0000000..05615b2 --- /dev/null +++ b/pthreads/doc/html/doxygen.css @@ -0,0 +1,310 @@ +BODY,H1,H2,H3,H4,H5,H6,P,CENTER,TD,TH,UL,DL,DIV { + font-family: Geneva, Arial, Helvetica, sans-serif; +} +BODY,TD { + font-size: 90%; +} +H1 { + text-align: center; + font-size: 160%; +} +H2 { + font-size: 120%; +} +H3 { + font-size: 100%; +} +CAPTION { font-weight: bold } +DIV.qindex { + width: 100%; + background-color: #e8eef2; + border: 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This file in turn +includes the actual implementation of local continuations, which +typically also is contained in a single header file. + +*/ + +/** @} */ + +/** +\defgroup examples Examples +@{ + +\section example-small A small example + +This first example shows a very simple program: two protothreads +waiting for each other to toggle two flags. The code illustrates how +to write protothreads code, how to initialize protothreads, and how to +schedule them. + +\include example-small.c + + +\section example-code-lock A code-lock +This example shows how to implement a simple code lock - the kind of +device that is placed next to doors and that you have to push a four +digit number into in order to unlock the door. + +The code lock waits for key presses from a numeric keyboard and if the +correct code is entered, the lock is unlocked. There is a maximum time +of one second between each key press, and after the correct code has +been entered, no more keys must be pressed for 0.5 seconds before the +lock is opened. + +\include example-codelock.c + +\section example-buffer The bounded buffer with protothread semaphores + +The following example shows how to implement the bounded buffer +problem using the protothreads semaphore library. The example uses +three protothreads: one producer() protothread that produces items, +one consumer() protothread that consumes items, and one +driver_thread() that schedules the producer and consumer protothreads. + +Note that there is no need for a mutex to guard the add_to_buffer() +and get_from_buffer() functions because of the implicit locking +semantics of protothreads - a protothread will never be preempted and +will never block except in an explicit PT_WAIT statement. + +\include example-buffer.c + +*/ + + +/** @} */ diff --git a/pthreads/doc/pt-mainpage.txt b/pthreads/doc/pt-mainpage.txt new file mode 100644 index 0000000..60eb016 --- /dev/null +++ b/pthreads/doc/pt-mainpage.txt @@ -0,0 +1,156 @@ +/** + +\mainpage The Protothreads Library + +\author Adam Dunkels + +Protothreads are a type of lightweight stackless threads designed for +severly memory constrained systems such as deeply embedded systems or +sensor network nodes. Protothreads provides linear code execution for +event-driven systems implemented in C. Protothreads can be used with +or without an RTOS. + +Protothreads are a extremely lightweight, stackless type of threads +that provides a blocking context on top of an event-driven system, +without the overhead of per-thread stacks. The purpose of protothreads +is to implement sequential flow of control without complex state +machines or full multi-threading. Protothreads provides conditional +blocking inside C functions. + +Main features: + + - No machine specific code - the protothreads library is pure C + + - Does not use error-prone functions such as longjmp() + + - Very small RAM overhead - only two bytes per protothread + + - Can be used with or without an OS + + - Provides blocking wait without full multi-threading or + stack-switching + +Examples applications: + + - Memory constrained systems + + - Event-driven protocol stacks + + - Deeply embedded systems + + - Sensor network nodes + + +\sa \ref examples "Example programs" +\sa \ref pt "Protothreads API documentation" + +The protothreads library is released under a BSD-style license that +allows for both non-commercial and commercial usage. The only +requirement is that credit is given. + +More information and new version of the code can be found at the +Protothreads homepage: + + http://www.sics.se/~adam/pt/ + +\section authors Authors + +The protothreads library was written by Adam Dunkels +with support from Oliver Schmidt . + +\section using Using protothreads + +Using protothreads in a project is easy: simply copy the files pt.h, +lc.h and lc-switch.h into the include files directory of the project, +and \#include "pt.h" in all files that should use protothreads. + +\section pt-desc Protothreads + +Protothreads are a extremely lightweight, stackless threads that +provides a blocking context on top of an event-driven system, without +the overhead of per-thread stacks. The purpose of protothreads is to +implement sequential flow of control without using complex state +machines or full multi-threading. Protothreads provides conditional +blocking inside a C function. + +In memory constrained systems, such as deeply embedded systems, +traditional multi-threading may have a too large memory overhead. In +traditional multi-threading, each thread requires its own stack, that +typically is over-provisioned. The stacks may use large parts of the +available memory. + +The main advantage of protothreads over ordinary threads is that +protothreads are very lightweight: a protothread does not require its +own stack. Rather, all protothreads run on the same stack and context +switching is done by stack rewinding. This is advantageous in memory +constrained systems, where a stack for a thread might use a large part +of the available memory. A protothread only requires only two bytes of +memory per protothread. Moreover, protothreads are implemented in pure +C and do not require any machine-specific assembler code. + +A protothread runs within a single C function and cannot span over +other functions. A protothread may call normal C functions, but cannot +block inside a called function. Blocking inside nested function calls +is instead made by spawning a separate protothread for each +potentially blocking function. The advantage of this approach is that +blocking is explicit: the programmer knows exactly which functions +that block that which functions the never blocks. + +Protothreads are similar to asymmetric co-routines. The main +difference is that co-routines uses a separate stack for each +co-routine, whereas protothreads are stackless. The most similar +mechanism to protothreads are Python generators. These are also +stackless constructs, but have a different purpose. Protothreads +provides blocking contexts inside a C function, whereas Python +generators provide multiple exit points from a generator function. + +\section pt-autovars Local variables + +\note +Because protothreads do not save the stack context across a blocking +call, local variables are not preserved when the protothread +blocks. This means that local variables should be used with utmost +care - if in doubt, do not use local variables inside a protothread! + +\section pt-scheduling Scheduling + +A protothread is driven by repeated calls to the function in which the +protothread is running. Each time the function is called, the +protothread will run until it blocks or exits. Thus the scheduling of +protothreads is done by the application that uses protothreads. + +\section pt-impl Implementation + +Protothreads are implemented using local continuations. A local +continuation represents the current state of execution at a particular +place in the program, but does not provide any call history or local +variables. A local continuation can be set in a specific function to +capture the state of the function. After a local continuation has been +set can be resumed in order to restore the state of the function at +the point where the local continuation was set. + + +Local continuations can be implemented in a variety of ways: + + -# by using machine specific assembler code, + -# by using standard C constructs, or + -# by using compiler extensions. + +The first way works by saving and restoring the processor state, +except for stack pointers, and requires between 16 and 32 bytes of +memory per protothread. The exact amount of memory required depends on +the architecture. + +The standard C implementation requires only two bytes of state per +protothread and utilizes the C switch() statement in a non-obvious way +that is similar to Duff's device. This implementation does, however, +impose a slight restriction to the code that uses protothreads: a +protothread cannot perform a blocking wait (PT_WAIT_UNTIL() or +PT_YIELD()) inside a switch() statement. + +Certain compilers has C extensions that can be used to implement +protothreads. GCC supports label pointers that can be used for this +purpose. With this implementation, protothreads require 4 bytes of RAM +per protothread. + +*/ diff --git a/pthreads/doc/pt-refman.pdf b/pthreads/doc/pt-refman.pdf new file mode 100644 index 0000000..2ee4db0 Binary files /dev/null and b/pthreads/doc/pt-refman.pdf differ diff --git a/pthreads/doc/sicslogo.pdf b/pthreads/doc/sicslogo.pdf new file mode 100644 index 0000000..239a1bf Binary files /dev/null and b/pthreads/doc/sicslogo.pdf differ diff --git a/pthreads/example-buffer.c b/pthreads/example-buffer.c new file mode 100644 index 0000000..44fa4a7 --- /dev/null +++ b/pthreads/example-buffer.c @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2004-2005, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the protothreads library. + * + * Author: Adam Dunkels + * + * $Id: example-buffer.c,v 1.5 2005/10/07 05:21:33 adam Exp $ + */ + +#ifdef _WIN32 +#include +#else +#include +#endif +#include + +#include "pt-sem.h" + +#define NUM_ITEMS 32 +#define BUFSIZE 8 + +static int buffer[BUFSIZE]; +static int bufptr; + +static void +add_to_buffer(int item) +{ + printf("Item %d added to buffer at place %d\n", item, bufptr); + buffer[bufptr] = item; + bufptr = (bufptr + 1) % BUFSIZE; +} +static int +get_from_buffer(void) +{ + int item; + item = buffer[bufptr]; + printf("Item %d retrieved from buffer at place %d\n", + item, bufptr); + bufptr = (bufptr + 1) % BUFSIZE; + return item; +} + +static int +produce_item(void) +{ + static int item = 0; + printf("Item %d produced\n", item); + return item++; +} + +static void +consume_item(int item) +{ + printf("Item %d consumed\n", item); +} + +static struct pt_sem full, empty; + +static +PT_THREAD(producer(struct pt *pt)) +{ + static int produced; + + PT_BEGIN(pt); + + for(produced = 0; produced < NUM_ITEMS; ++produced) { + + PT_SEM_WAIT(pt, &full); + + add_to_buffer(produce_item()); + + PT_SEM_SIGNAL(pt, &empty); + } + + PT_END(pt); +} + +static +PT_THREAD(consumer(struct pt *pt)) +{ + static int consumed; + + PT_BEGIN(pt); + + for(consumed = 0; consumed < NUM_ITEMS; ++consumed) { + + PT_SEM_WAIT(pt, &empty); + + consume_item(get_from_buffer()); + + PT_SEM_SIGNAL(pt, &full); + } + + PT_END(pt); +} + +static +PT_THREAD(driver_thread(struct pt *pt)) +{ + static struct pt pt_producer, pt_consumer; + + PT_BEGIN(pt); + + PT_SEM_INIT(&empty, 0); + PT_SEM_INIT(&full, BUFSIZE); + + PT_INIT(&pt_producer); + PT_INIT(&pt_consumer); + + PT_WAIT_THREAD(pt, producer(&pt_producer) & + consumer(&pt_consumer)); + + PT_END(pt); +} + + +int +main(void) +{ + struct pt driver_pt; + + PT_INIT(&driver_pt); + + while(PT_SCHEDULE(driver_thread(&driver_pt))) { + + /* + * When running this example on a multitasking system, we must + * give other processes a chance to run too and therefore we call + * usleep() resp. Sleep() here. On a dedicated embedded system, + * we usually do not need to do this. + */ +#ifdef _WIN32 + Sleep(0); +#else + usleep(10); +#endif + } + return 0; +} diff --git a/pthreads/example-codelock.c b/pthreads/example-codelock.c new file mode 100644 index 0000000..cbeeb96 --- /dev/null +++ b/pthreads/example-codelock.c @@ -0,0 +1,414 @@ +/* + * Copyright (c) 2004-2005, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the protothreads library. + * + * Author: Adam Dunkels + * + * $Id: example-codelock.c,v 1.5 2005/10/06 07:57:08 adam Exp $ + */ + +/* + * + * This example shows how to implement a simple code lock. The code + * lock waits for key presses from a numeric keyboard and if the + * correct code is entered, the lock is unlocked. There is a maximum + * time of one second between each key press, and after the correct + * code has been entered, no more keys must be pressed for 0.5 seconds + * before the lock is opened. + * + * This is an example that shows two things: + * - how to implement a code lock key input mechanism, and + * - how to implement a sequential timed routine. + * + * The program consists of two protothreads, one that implements the + * code lock reader and one that implements simulated keyboard input. + * + * + */ + +#ifdef _WIN32 +#include +#else +#include +#include +#endif +#include + +#include "pt.h" + +/*---------------------------------------------------------------------------*/ +/* + * The following definitions are just for the simple timer library + * used in this example. The actual implementation of the functions + * can be found at the end of this file. + */ +struct timer { int start, interval; }; +static int timer_expired(struct timer *t); +static void timer_set(struct timer *t, int usecs); +/*---------------------------------------------------------------------------*/ +/* + * This example uses two timers: one for the code lock protothread and + * one for the simulated key input protothread. + */ +static struct timer codelock_timer, input_timer; +/*---------------------------------------------------------------------------*/ +/* + * This is the code that has to be entered. + */ +static const char code[4] = {'1', '4', '2', '3'}; +/*---------------------------------------------------------------------------*/ +/* + * This example has two protothread and therefor has two protothread + * control structures of type struct pt. These are initialized with + * PT_INIT() in the main() function below. + */ +static struct pt codelock_pt, input_pt; +/*---------------------------------------------------------------------------*/ +/* + * The following code implements a simple key input. Input is made + * with the press_key() function, and the function key_pressed() + * checks if a key has been pressed. The variable "key" holds the + * latest key that was pressed. The variable "key_pressed_flag" is set + * when a key is pressed and cleared when a key press is checked. + */ +static char key, key_pressed_flag; + +static void +press_key(char k) +{ + printf("--- Key '%c' pressed\n", k); + key = k; + key_pressed_flag = 1; +} + +static int +key_pressed(void) +{ + if(key_pressed_flag != 0) { + key_pressed_flag = 0; + return 1; + } + return 0; +} +/*---------------------------------------------------------------------------*/ +/* + * Declaration of the protothread function implementing the code lock + * logic. The protothread function is declared using the PT_THREAD() + * macro. The function is declared with the "static" keyword since it + * is local to this file. The name of the function is codelock_thread + * and it takes one argument, pt, of the type struct pt. + * + */ +static +PT_THREAD(codelock_thread(struct pt *pt)) +{ + /* This is a local variable that holds the number of keys that have + * been pressed. Note that it is declared with the "static" keyword + * to make sure that the variable is *not* allocated on the stack. + */ + static int keys; + + /* + * Declare the beginning of the protothread. + */ + PT_BEGIN(pt); + + /* + * We'll let the protothread loop until the protothread is + * expliticly exited with PT_EXIT(). + */ + while(1) { + + /* + * We'll be reading key presses until we get the right amount of + * correct keys. + */ + for(keys = 0; keys < sizeof(code); ++keys) { + + /* + * If we haven't gotten any keypresses, we'll simply wait for one. + */ + if(keys == 0) { + + /* + * The PT_WAIT_UNTIL() function will block until the condition + * key_pressed() is true. + */ + PT_WAIT_UNTIL(pt, key_pressed()); + } else { + + /* + * If the "key" variable was larger than zero, we have already + * gotten at least one correct key press. If so, we'll not + * only wait for the next key, but we'll also set a timer that + * expires in one second. This gives the person pressing the + * keys one second to press the next key in the code. + */ + timer_set(&codelock_timer, 1000); + + /* + * The following statement shows how complex blocking + * conditions can be easily expressed with protothreads and + * the PT_WAIT_UNTIL() function. + */ + PT_WAIT_UNTIL(pt, key_pressed() || timer_expired(&codelock_timer)); + + /* + * If the timer expired, we should break out of the for() loop + * and start reading keys from the beginning of the while(1) + * loop instead. + */ + if(timer_expired(&codelock_timer)) { + printf("Code lock timer expired.\n"); + + /* + * Break out from the for() loop and start from the + * beginning of the while(1) loop. + */ + break; + } + } + + /* + * Check if the pressed key was correct. + */ + if(key != code[keys]) { + printf("Incorrect key '%c' found\n", key); + /* + * Break out of the for() loop since the key was incorrect. + */ + break; + } else { + printf("Correct key '%c' found\n", key); + } + } + + /* + * Check if we have gotten all keys. + */ + if(keys == sizeof(code)) { + printf("Correct code entered, waiting for 500 ms before unlocking.\n"); + + /* + * Ok, we got the correct code. But to make sure that the code + * was not just a fluke of luck by an intruder, but the correct + * code entered by a person that knows the correct code, we'll + * wait for half a second before opening the lock. If another + * key is pressed during this time, we'll assume that it was a + * fluke of luck that the correct code was entered the first + * time. + */ + timer_set(&codelock_timer, 500); + PT_WAIT_UNTIL(pt, key_pressed() || timer_expired(&codelock_timer)); + + /* + * If we continued from the PT_WAIT_UNTIL() statement without + * the timer expired, we don't open the lock. + */ + if(!timer_expired(&codelock_timer)) { + printf("Key pressed during final wait, code lock locked again.\n"); + } else { + + /* + * If the timer expired, we'll open the lock and exit from the + * protothread. + */ + printf("Code lock unlocked.\n"); + PT_EXIT(pt); + } + } + } + + /* + * Finally, we'll mark the end of the protothread. + */ + PT_END(pt); +} +/*---------------------------------------------------------------------------*/ +/* + * This is the second protothread in this example. It implements a + * simulated user pressing the keys. This illustrates how a linear + * sequence of timed instructions can be implemented with + * protothreads. + */ +static +PT_THREAD(input_thread(struct pt *pt)) +{ + PT_BEGIN(pt); + + printf("Waiting 1 second before entering first key.\n"); + + timer_set(&input_timer, 1000); + PT_WAIT_UNTIL(pt, timer_expired(&input_timer)); + + press_key('1'); + + timer_set(&input_timer, 100); + PT_WAIT_UNTIL(pt, timer_expired(&input_timer)); + + press_key('2'); + + timer_set(&input_timer, 100); + PT_WAIT_UNTIL(pt, timer_expired(&input_timer)); + + press_key('3'); + + timer_set(&input_timer, 2000); + PT_WAIT_UNTIL(pt, timer_expired(&input_timer)); + + press_key('1'); + + timer_set(&input_timer, 200); + PT_WAIT_UNTIL(pt, timer_expired(&input_timer)); + + press_key('4'); + + timer_set(&input_timer, 200); + PT_WAIT_UNTIL(pt, timer_expired(&input_timer)); + + press_key('2'); + + timer_set(&input_timer, 2000); + PT_WAIT_UNTIL(pt, timer_expired(&input_timer)); + + press_key('3'); + + timer_set(&input_timer, 200); + PT_WAIT_UNTIL(pt, timer_expired(&input_timer)); + + press_key('1'); + + timer_set(&input_timer, 200); + PT_WAIT_UNTIL(pt, timer_expired(&input_timer)); + + press_key('4'); + + timer_set(&input_timer, 200); + PT_WAIT_UNTIL(pt, timer_expired(&input_timer)); + + press_key('2'); + + timer_set(&input_timer, 100); + PT_WAIT_UNTIL(pt, timer_expired(&input_timer)); + + press_key('3'); + + timer_set(&input_timer, 100); + PT_WAIT_UNTIL(pt, timer_expired(&input_timer)); + + press_key('4'); + + timer_set(&input_timer, 1500); + PT_WAIT_UNTIL(pt, timer_expired(&input_timer)); + + press_key('1'); + + timer_set(&input_timer, 300); + PT_WAIT_UNTIL(pt, timer_expired(&input_timer)); + + press_key('4'); + + timer_set(&input_timer, 400); + PT_WAIT_UNTIL(pt, timer_expired(&input_timer)); + + press_key('2'); + + timer_set(&input_timer, 500); + PT_WAIT_UNTIL(pt, timer_expired(&input_timer)); + + press_key('3'); + + timer_set(&input_timer, 2000); + PT_WAIT_UNTIL(pt, timer_expired(&input_timer)); + + PT_END(pt); +} +/*---------------------------------------------------------------------------*/ +/* + * This is the main function. It initializes the two protothread + * control structures and schedules the two protothreads. The main + * function returns when the protothread the runs the code lock exits. + */ +int +main(void) +{ + /* + * Initialize the two protothread control structures. + */ + PT_INIT(&input_pt); + PT_INIT(&codelock_pt); + + /* + * Schedule the two protothreads until the codelock_thread() exits. + */ + while(PT_SCHEDULE(codelock_thread(&codelock_pt))) { + PT_SCHEDULE(input_thread(&input_pt)); + + /* + * When running this example on a multitasking system, we must + * give other processes a chance to run too and therefore we call + * usleep() resp. Sleep() here. On a dedicated embedded system, + * we usually do not need to do this. + */ +#ifdef _WIN32 + Sleep(0); +#else + usleep(10); +#endif + } + + return 0; +} +/*---------------------------------------------------------------------------*/ +/* + * Finally, the implementation of the simple timer library follows. + */ +#ifdef _WIN32 + +static int clock_time(void) +{ return (int)GetTickCount(); } + +#else /* _WIN32 */ + +static int clock_time(void) +{ + struct timeval tv; + struct timezone tz; + gettimeofday(&tv, &tz); + return tv.tv_sec * 1000 + tv.tv_usec / 1000; +} + +#endif /* _WIN32 */ + +static int timer_expired(struct timer *t) +{ return (int)(clock_time() - t->start) >= (int)t->interval; } + +static void timer_set(struct timer *t, int interval) +{ t->interval = interval; t->start = clock_time(); } +/*---------------------------------------------------------------------------*/ diff --git a/pthreads/example-small.c b/pthreads/example-small.c new file mode 100644 index 0000000..37c1716 --- /dev/null +++ b/pthreads/example-small.c @@ -0,0 +1,97 @@ +/** + * This is a very small example that shows how to use + * protothreads. The program consists of two protothreads that wait + * for each other to toggle a variable. + */ + +/* We must always include pt.h in our protothreads code. */ +#include "pt.h" + +#include /* For printf(). */ + +/* Two flags that the two protothread functions use. */ +static int protothread1_flag, protothread2_flag; + +/** + * The first protothread function. A protothread function must always + * return an integer, but must never explicitly return - returning is + * performed inside the protothread statements. + * + * The protothread function is driven by the main loop further down in + * the code. + */ +static int +protothread1(struct pt *pt) +{ + /* A protothread function must begin with PT_BEGIN() which takes a + pointer to a struct pt. */ + PT_BEGIN(pt); + + /* We loop forever here. */ + while(1) { + /* Wait until the other protothread has set its flag. */ + PT_WAIT_UNTIL(pt, protothread2_flag != 0); + printf("Protothread 1 running\n"); + + /* We then reset the other protothread's flag, and set our own + flag so that the other protothread can run. */ + protothread2_flag = 0; + protothread1_flag = 1; + + /* And we loop. */ + } + + /* All protothread functions must end with PT_END() which takes a + pointer to a struct pt. */ + PT_END(pt); +} + +/** + * The second protothread function. This is almost the same as the + * first one. + */ +static int +protothread2(struct pt *pt) +{ + PT_BEGIN(pt); + + while(1) { + /* Let the other protothread run. */ + protothread2_flag = 1; + + /* Wait until the other protothread has set its flag. */ + PT_WAIT_UNTIL(pt, protothread1_flag != 0); + printf("Protothread 2 running\n"); + + /* We then reset the other protothread's flag. */ + protothread1_flag = 0; + + /* And we loop. */ + } + PT_END(pt); +} + +/** + * Finally, we have the main loop. Here is where the protothreads are + * initialized and scheduled. First, however, we define the + * protothread state variables pt1 and pt2, which hold the state of + * the two protothreads. + */ +static struct pt pt1, pt2; +int +main(void) +{ + /* Initialize the protothread state variables with PT_INIT(). */ + PT_INIT(&pt1); + PT_INIT(&pt2); + + /* + * Then we schedule the two protothreads by repeatedly calling their + * protothread functions and passing a pointer to the protothread + * state variables as arguments. + */ + while(1) { + protothread1(&pt1); + protothread2(&pt2); + } +} diff --git a/pthreads/lc-addrlabels.h b/pthreads/lc-addrlabels.h new file mode 100644 index 0000000..3e6474e --- /dev/null +++ b/pthreads/lc-addrlabels.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2004-2005, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the Contiki operating system. + * + * Author: Adam Dunkels + * + * $Id: lc-addrlabels.h,v 1.4 2006/06/03 11:29:43 adam Exp $ + */ + +/** + * \addtogroup lc + * @{ + */ + +/** + * \file + * Implementation of local continuations based on the "Labels as + * values" feature of gcc + * \author + * Adam Dunkels + * + * This implementation of local continuations is based on a special + * feature of the GCC C compiler called "labels as values". This + * feature allows assigning pointers with the address of the code + * corresponding to a particular C label. + * + * For more information, see the GCC documentation: + * http://gcc.gnu.org/onlinedocs/gcc/Labels-as-Values.html + * + */ + +#ifndef __LC_ADDRLABELS_H__ +#define __LC_ADDRLABELS_H__ + +/** \hideinitializer */ +typedef void * lc_t; + +#define LC_INIT(s) s = NULL + +#define LC_RESUME(s) \ + do { \ + if(s != NULL) { \ + goto *s; \ + } \ + } while(0) + +#define LC_CONCAT2(s1, s2) s1##s2 +#define LC_CONCAT(s1, s2) LC_CONCAT2(s1, s2) + +#define LC_SET(s) \ + do { \ + LC_CONCAT(LC_LABEL, __LINE__): \ + (s) = &&LC_CONCAT(LC_LABEL, __LINE__); \ + } while(0) + +#define LC_END(s) + +#endif /* __LC_ADDRLABELS_H__ */ +/** @} */ diff --git a/pthreads/lc-switch.h b/pthreads/lc-switch.h new file mode 100644 index 0000000..dbdde01 --- /dev/null +++ b/pthreads/lc-switch.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2004-2005, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the Contiki operating system. + * + * Author: Adam Dunkels + * + * $Id: lc-switch.h,v 1.4 2006/06/03 11:29:43 adam Exp $ + */ + +/** + * \addtogroup lc + * @{ + */ + +/** + * \file + * Implementation of local continuations based on switch() statment + * \author Adam Dunkels + * + * This implementation of local continuations uses the C switch() + * statement to resume execution of a function somewhere inside the + * function's body. The implementation is based on the fact that + * switch() statements are able to jump directly into the bodies of + * control structures such as if() or while() statmenets. + * + * This implementation borrows heavily from Simon Tatham's coroutines + * implementation in C: + * http://www.chiark.greenend.org.uk/~sgtatham/coroutines.html + */ + +#ifndef __LC_SWITCH_H__ +#define __LC_SWITCH_H__ + +/* WARNING! lc implementation using switch() does not work if an + LC_SET() is done within another switch() statement! */ + +/** \hideinitializer */ +typedef unsigned short lc_t; + +#define LC_INIT(s) s = 0; + +#define LC_RESUME(s) switch(s) { case 0: + +#define LC_SET(s) s = __LINE__; case __LINE__: + +#define LC_END(s) } + +#endif /* __LC_SWITCH_H__ */ + +/** @} */ diff --git a/pthreads/lc.h b/pthreads/lc.h new file mode 100644 index 0000000..a965956 --- /dev/null +++ b/pthreads/lc.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2004-2005, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the protothreads library. + * + * Author: Adam Dunkels + * + * $Id: lc.h,v 1.2 2005/02/24 10:36:59 adam Exp $ + */ + +/** + * \addtogroup pt + * @{ + */ + +/** + * \defgroup lc Local continuations + * @{ + * + * Local continuations form the basis for implementing protothreads. A + * local continuation can be set in a specific function to + * capture the state of the function. After a local continuation has + * been set can be resumed in order to restore the state of the + * function at the point where the local continuation was set. + * + * + */ + +/** + * \file lc.h + * Local continuations + * \author + * Adam Dunkels + * + */ + +#ifdef DOXYGEN +/** + * Initialize a local continuation. + * + * This operation initializes the local continuation, thereby + * unsetting any previously set continuation state. + * + * \hideinitializer + */ +#define LC_INIT(lc) + +/** + * Set a local continuation. + * + * The set operation saves the state of the function at the point + * where the operation is executed. As far as the set operation is + * concerned, the state of the function does not include the + * call-stack or local (automatic) variables, but only the program + * counter and such CPU registers that needs to be saved. + * + * \hideinitializer + */ +#define LC_SET(lc) + +/** + * Resume a local continuation. + * + * The resume operation resumes a previously set local continuation, thus + * restoring the state in which the function was when the local + * continuation was set. If the local continuation has not been + * previously set, the resume operation does nothing. + * + * \hideinitializer + */ +#define LC_RESUME(lc) + +/** + * Mark the end of local continuation usage. + * + * The end operation signifies that local continuations should not be + * used any more in the function. This operation is not needed for + * most implementations of local continuation, but is required by a + * few implementations. + * + * \hideinitializer + */ +#define LC_END(lc) + +/** + * \var typedef lc_t; + * + * The local continuation type. + * + * \hideinitializer + */ +#endif /* DOXYGEN */ + +#ifndef __LC_H__ +#define __LC_H__ + + +#ifdef LC_INCLUDE +#include LC_INCLUDE +#else +#include "lc-switch.h" +#endif /* LC_INCLUDE */ + +#endif /* __LC_H__ */ + +/** @} */ +/** @} */ diff --git a/pthreads/pt-sem.h b/pthreads/pt-sem.h new file mode 100644 index 0000000..98ae25d --- /dev/null +++ b/pthreads/pt-sem.h @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the protothreads library. + * + * Author: Adam Dunkels + * + * $Id: pt-sem.h,v 1.2 2005/02/24 10:36:59 adam Exp $ + */ + +/** + * \addtogroup pt + * @{ + */ + +/** + * \defgroup ptsem Protothread semaphores + * @{ + * + * This module implements counting semaphores on top of + * protothreads. Semaphores are a synchronization primitive that + * provide two operations: "wait" and "signal". The "wait" operation + * checks the semaphore counter and blocks the thread if the counter + * is zero. The "signal" operation increases the semaphore counter but + * does not block. If another thread has blocked waiting for the + * semaphore that is signalled, the blocked thread will become + * runnable again. + * + * Semaphores can be used to implement other, more structured, + * synchronization primitives such as monitors and message + * queues/bounded buffers (see below). + * + * The following example shows how the producer-consumer problem, also + * known as the bounded buffer problem, can be solved using + * protothreads and semaphores. Notes on the program follow after the + * example. + * + \code +#include "pt-sem.h" + +#define NUM_ITEMS 32 +#define BUFSIZE 8 + +static struct pt_sem mutex, full, empty; + +PT_THREAD(producer(struct pt *pt)) +{ + static int produced; + + PT_BEGIN(pt); + + for(produced = 0; produced < NUM_ITEMS; ++produced) { + + PT_SEM_WAIT(pt, &full); + + PT_SEM_WAIT(pt, &mutex); + add_to_buffer(produce_item()); + PT_SEM_SIGNAL(pt, &mutex); + + PT_SEM_SIGNAL(pt, &empty); + } + + PT_END(pt); +} + +PT_THREAD(consumer(struct pt *pt)) +{ + static int consumed; + + PT_BEGIN(pt); + + for(consumed = 0; consumed < NUM_ITEMS; ++consumed) { + + PT_SEM_WAIT(pt, &empty); + + PT_SEM_WAIT(pt, &mutex); + consume_item(get_from_buffer()); + PT_SEM_SIGNAL(pt, &mutex); + + PT_SEM_SIGNAL(pt, &full); + } + + PT_END(pt); +} + +PT_THREAD(driver_thread(struct pt *pt)) +{ + static struct pt pt_producer, pt_consumer; + + PT_BEGIN(pt); + + PT_SEM_INIT(&empty, 0); + PT_SEM_INIT(&full, BUFSIZE); + PT_SEM_INIT(&mutex, 1); + + PT_INIT(&pt_producer); + PT_INIT(&pt_consumer); + + PT_WAIT_THREAD(pt, producer(&pt_producer) & + consumer(&pt_consumer)); + + PT_END(pt); +} + \endcode + * + * The program uses three protothreads: one protothread that + * implements the consumer, one thread that implements the producer, + * and one protothread that drives the two other protothreads. The + * program uses three semaphores: "full", "empty" and "mutex". The + * "mutex" semaphore is used to provide mutual exclusion for the + * buffer, the "empty" semaphore is used to block the consumer is the + * buffer is empty, and the "full" semaphore is used to block the + * producer is the buffer is full. + * + * The "driver_thread" holds two protothread state variables, + * "pt_producer" and "pt_consumer". It is important to note that both + * these variables are declared as static. If the static + * keyword is not used, both variables are stored on the stack. Since + * protothreads do not store the stack, these variables may be + * overwritten during a protothread wait operation. Similarly, both + * the "consumer" and "producer" protothreads declare their local + * variables as static, to avoid them being stored on the stack. + * + * + */ + +/** + * \file + * Couting semaphores implemented on protothreads + * \author + * Adam Dunkels + * + */ + +#ifndef __PT_SEM_H__ +#define __PT_SEM_H__ + +#include "pt.h" + +struct pt_sem { + unsigned int count; +}; + +/** + * Initialize a semaphore + * + * This macro initializes a semaphore with a value for the + * counter. Internally, the semaphores use an "unsigned int" to + * represent the counter, and therefore the "count" argument should be + * within range of an unsigned int. + * + * \param s (struct pt_sem *) A pointer to the pt_sem struct + * representing the semaphore + * + * \param c (unsigned int) The initial count of the semaphore. + * \hideinitializer + */ +#define PT_SEM_INIT(s, c) (s)->count = c + +/** + * Wait for a semaphore + * + * This macro carries out the "wait" operation on the semaphore. The + * wait operation causes the protothread to block while the counter is + * zero. When the counter reaches a value larger than zero, the + * protothread will continue. + * + * \param pt (struct pt *) A pointer to the protothread (struct pt) in + * which the operation is executed. + * + * \param s (struct pt_sem *) A pointer to the pt_sem struct + * representing the semaphore + * + * \hideinitializer + */ +#define PT_SEM_WAIT(pt, s) \ + do { \ + PT_WAIT_UNTIL(pt, (s)->count > 0); \ + --(s)->count; \ + } while(0) + +/** + * Signal a semaphore + * + * This macro carries out the "signal" operation on the semaphore. The + * signal operation increments the counter inside the semaphore, which + * eventually will cause waiting protothreads to continue executing. + * + * \param pt (struct pt *) A pointer to the protothread (struct pt) in + * which the operation is executed. + * + * \param s (struct pt_sem *) A pointer to the pt_sem struct + * representing the semaphore + * + * \hideinitializer + */ +#define PT_SEM_SIGNAL(pt, s) ++(s)->count + +#endif /* __PT_SEM_H__ */ + +/** @} */ +/** @} */ + diff --git a/pthreads/pt.h b/pthreads/pt.h new file mode 100644 index 0000000..3ce0d18 --- /dev/null +++ b/pthreads/pt.h @@ -0,0 +1,328 @@ +/* + * Copyright (c) 2004-2005, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the Contiki operating system. + * + * Author: Adam Dunkels + * + * $Id: pt.h,v 1.7 2006/10/02 07:52:56 adam Exp $ + */ + +/** + * \addtogroup pt + * @{ + */ + +/** + * \file + * Protothreads implementation. + * \author + * Adam Dunkels + * + */ + +#ifndef __PT_H__ +#define __PT_H__ + +#include "lc.h" +#include "stdint.h" +#include "stdbool.h" + +struct pt { + lc_t lc; + uint8_t status; +}; + +typedef struct pt pt_t; + +#define PT_WAITING 0 +#define PT_YIELDED 1 +#define PT_EXITED 2 +#define PT_ENDED 3 + +/** + * \name Initialization + * @{ + */ + +/** + * Initialize a protothread. + * + * Initializes a protothread. Initialization must be done prior to + * starting to execute the protothread. + * + * \param pt A pointer to the protothread control structure. + * + * \sa PT_SPAWN() + * + * \hideinitializer + */ +#define PT_INIT(pt) LC_INIT((pt)->lc) + +/** @} */ + +/** + * \name Declaration and definition + * @{ + */ + +/** + * Declaration of a protothread. + * + * This macro is used to declare a protothread. All protothreads must + * be declared with this macro. + * + * \param name_args The name and arguments of the C function + * implementing the protothread. + * + * \hideinitializer + */ +#define PT_THREAD(name_args) char name_args + +/** + * Declare the start of a protothread inside the C function + * implementing the protothread. + * + * This macro is used to declare the starting point of a + * protothread. It should be placed at the start of the function in + * which the protothread runs. All C statements above the PT_BEGIN() + * invokation will be executed each time the protothread is scheduled. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_BEGIN(pt) { char PT_YIELD_FLAG = 1; (void)PT_YIELD_FLAG; LC_RESUME((pt)->lc) + +/** + * Declare the end of a protothread. + * + * This macro is used for declaring that a protothread ends. It must + * always be used together with a matching PT_BEGIN() macro. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_END(pt) LC_END((pt)->lc); PT_YIELD_FLAG = 0; \ + PT_INIT(pt); return PT_ENDED; } + +/** @} */ + +/** + * \name Blocked wait + * @{ + */ + +/** + * Block and wait until condition is true. + * + * This macro blocks the protothread until the specified condition is + * true. + * + * \param pt A pointer to the protothread control structure. + * \param condition The condition. + * + * \hideinitializer + */ +#define PT_WAIT_UNTIL(pt, condition) \ + do { \ + LC_SET((pt)->lc); \ + if(!(condition)) { \ + return PT_WAITING; \ + } \ + } while(0) + +/** + * Block and wait while condition is true. + * + * This function blocks and waits while condition is true. See + * PT_WAIT_UNTIL(). + * + * \param pt A pointer to the protothread control structure. + * \param cond The condition. + * + * \hideinitializer + */ +#define PT_WAIT_WHILE(pt, cond) PT_WAIT_UNTIL((pt), !(cond)) + +/** @} */ + +/** + * \name Hierarchical protothreads + * @{ + */ + +/** + * Block and wait until a child protothread completes. + * + * This macro schedules a child protothread. The current protothread + * will block until the child protothread completes. + * + * \note The child protothread must be manually initialized with the + * PT_INIT() function before this function is used. + * + * \param pt A pointer to the protothread control structure. + * \param thread The child protothread with arguments + * + * \sa PT_SPAWN() + * + * \hideinitializer + */ +#define PT_WAIT_THREAD(pt, thread) PT_WAIT_WHILE((pt), PT_SCHEDULE(thread)) + +/** + * Spawn a child protothread and wait until it exits. + * + * This macro spawns a child protothread and waits until it exits. The + * macro can only be used within a protothread. + * + * \param pt A pointer to the protothread control structure. + * \param child A pointer to the child protothread's control structure. + * \param thread The child protothread with arguments + * + * \hideinitializer + */ +#define PT_SPAWN(pt, child, thread) \ + do { \ + PT_INIT((child)); \ + PT_WAIT_THREAD((pt), (thread)); \ + } while(0) + +/** @} */ + +/** + * \name Exiting and restarting + * @{ + */ + +/** + * Restart the protothread. + * + * This macro will block and cause the running protothread to restart + * its execution at the place of the PT_BEGIN() call. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_RESTART(pt) \ + do { \ + PT_INIT(pt); \ + return PT_WAITING; \ + } while(0) + +/** + * Exit the protothread. + * + * This macro causes the protothread to exit. If the protothread was + * spawned by another protothread, the parent protothread will become + * unblocked and can continue to run. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_EXIT(pt) \ + do { \ + PT_INIT(pt); \ + return PT_EXITED; \ + } while(0) + +/** @} */ + +/** + * \name Calling a protothread + * @{ + */ + +/** + * Schedule a protothread. + * + * This function shedules a protothread. The return value of the + * function is non-zero if the protothread is running or zero if the + * protothread has exited. + * + * \param f The call to the C function implementing the protothread to + * be scheduled + * + * \hideinitializer + */ +#define PT_SCHEDULE(f) ((f) < PT_EXITED) + +/** @} */ + +/** + * \name Yielding from a protothread + * @{ + */ + +/** + * Yield from the current protothread. + * + * This function will yield the protothread, thereby allowing other + * processing to take place in the system. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_YIELD(pt) \ + do { \ + PT_YIELD_FLAG = 0; \ + LC_SET((pt)->lc); \ + if(PT_YIELD_FLAG == 0) { \ + return PT_YIELDED; \ + } \ + } while(0) + +/** + * \brief Yield from the protothread until a condition occurs. + * \param pt A pointer to the protothread control structure. + * \param cond The condition. + * + * This function will yield the protothread, until the + * specified condition evaluates to true. + * + * + * \hideinitializer + */ +#define PT_YIELD_UNTIL(pt, cond) \ + do { \ + PT_YIELD_FLAG = 0; \ + LC_SET((pt)->lc); \ + if((PT_YIELD_FLAG == 0) || !(cond)) { \ + return PT_YIELDED; \ + } \ + } while(0) + +/** @} */ + +#endif /* __PT_H__ */ + +/** @} */ diff --git a/pthreads/pt_ext.c b/pthreads/pt_ext.c new file mode 100644 index 0000000..45e033f --- /dev/null +++ b/pthreads/pt_ext.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2025, Your Name. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file implements the extensions to the protothreads library. + * + * Author: Your Name + */ + +#include "pt_ext.h" + +/** + * Global tick counter. + * + * This variable is used to track system ticks. It should be incremented + * by the system tick interrupt or a similar mechanism. + */ +volatile unsigned int pt_ticks = 0; + +/** + * Increment the system tick counter. + */ +void +pt_ticks_inc(void) +{ + pt_ticks++; +} + +/** + * Get the current system tick counter. + * + * \return The current tick count. + */ +unsigned int +pt_ticks_get(void) +{ + return pt_ticks; +} + +/** + * Check if timeout has occurred, handling tick counter overflow. + */ +int +pt_is_timeout(unsigned int start, unsigned int end, unsigned int timeout) +{ + return (end - start) >= timeout || + ((end < start) && (UINT_MAX - start + end + 1) >= timeout); +} + +/** + * Initialize the protothreads extensions. + * + * This function resets the global tick counter to zero. + */ +void +pt_ext_init(void) +{ + pt_ticks = 0; +} diff --git a/pthreads/pt_ext.h b/pthreads/pt_ext.h new file mode 100644 index 0000000..cba9ee7 --- /dev/null +++ b/pthreads/pt_ext.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2025, Your Name. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is an extension to the protothreads library. + * + * Author: Your Name + */ + +#ifndef __PT_EXT_H__ +#define __PT_EXT_H__ + +#include "pt.h" +#include "limits.h" + +#define PT_WAIT_STAT_SUCC (0 ) +#define PT_WAIT_STAT_TIMEOUT (-2) + +/** + * \addtogroup pt + * @{ + */ + +/** + * Increment the system tick counter. + * + * This macro increments the global tick counter. It should be called + * from a system tick interrupt or similar context. + */ + + void pt_ticks_inc(void); + +/** + * Get the current system tick counter. + * + * \return The current tick count. + */ +unsigned int pt_ticks_get(void); + + + +/** + * Delay for a specified number of milliseconds. + * + * This macro blocks the protothread for the specified number of + * milliseconds. The delay is implemented using the global tick counter. + * + * \param pt A pointer to the protothread control structure. + * \param ms The number of milliseconds to delay. + */ +/** + * Check if timeout has occurred, handling tick counter overflow. + * + * \param start The start tick count + * \param end The end tick count + * \param timeout The timeout value in ticks + * \return 1 if timeout occurred, 0 otherwise + */ +int pt_is_timeout(unsigned int start, unsigned int end, unsigned int timeout); + +#define PT_DELAY_MS(pt, ms) \ + do { \ + static unsigned int _pt_delay_start=0; \ + _pt_delay_start = pt_ticks_get(); \ + PT_WAIT_UNTIL((pt), pt_is_timeout(_pt_delay_start, pt_ticks_get(), ms)); \ + } while (0) + +#define PT_WAIT(pt, c, timeout, result) \ + do { \ + static unsigned int _pt_wait_start = 0;\ + _pt_wait_start = pt_ticks_get(); \ + *result = -1; \ + PT_WAIT_UNTIL((pt), (c) || pt_is_timeout(_pt_wait_start, pt_ticks_get(), timeout)); \ + if (c) { *result = 0; };\ + if (pt_is_timeout(_pt_wait_start, pt_ticks_get(), timeout)) { *result = -2;};\ + }while (0) + +/** @} */ +/** @} */ + +#endif /* __PT_EXT_H__ */ diff --git a/pthreads/pt_pm.c b/pthreads/pt_pm.c new file mode 100644 index 0000000..b799e4d --- /dev/null +++ b/pthreads/pt_pm.c @@ -0,0 +1,105 @@ + +#include "pt_task.h" +#include "pt_pm.h" +#include "pt_ext.h" + +#include "stdio.h" + +// 系统空闲æ¡ä»¶ +#define SYSTEM_IS_IDLE() (ALL_TASKS_IDLE()) +#define DEEP_SLEEP_THRESHOLD 5 // 进入深度休眠的空闲计数阈值 + +static struct { + pm_adapter_t default_adapter; + pt_t pt; + pm_mode_t current_mode; // 当å‰åŠŸè€—æ¨¡å¼ + uint32_t ref_count[PM_SLEEP_MODE_MAX]; // 引用计数数组 +} pm; + +static bool system_is_idle(void) +{ + return pt_task_all_idle(); +} + +/* +功耗管ç†ï¼šé历所有任务状æ€ï¼Œç„¶åŽæ ¹æ®ç”¨äºŽè¯·æ±‚的功耗模å¼ï¼Œè°ƒç”¨é€‚é…器接å£ï¼Œè°ƒæ•´MCUçš„è¿è¡Œæ¨¡å¼ +*/ +static void pt_pm_handler(void) { + + if (system_is_idle()) { + + // 切æ¢åˆ°ä¸‹ä¸€ä¸ªå¯ç”¨çš„åŠŸè€—æ¨¡å¼ + pm_mode_t next_mode = PM_SLEEP_MODE_NONE; + for (pm_mode_t m = PM_SLEEP_MODE_NONE; m < PM_SLEEP_MODE_MAX; m++) { + if (pm.ref_count[m] > 0 ) { + next_mode = m; + } + } + + if (next_mode != pm.current_mode && pm.default_adapter.sleep) { + pm.default_adapter.sleep(next_mode); + pm.current_mode = next_mode; + } + + } else { + + pt_pm_release(PM_SLEEP_MODE_NONE); // 唤醒系统 + + if (pm.default_adapter.wakeup) { + pm.default_adapter.wakeup(); + } + pm.current_mode = PM_SLEEP_MODE_NONE; + } +} + + +void pt_pm_adapter_init(pm_adapter_t *adapter) { + if (adapter) { + pm.default_adapter = *adapter; // å¤åˆ¶æ•´ä¸ªç»“构体 + } else { + pm.default_adapter.sleep = 0; + pm.default_adapter.wakeup = 0; + } +} + +void pt_pm_init(void) { + + PT_INIT(&pm.pt); +} + + +int pt_task_pm(void) { + + PT_BEGIN(&pm.pt); + + while (1) { + + pt_pm_handler(); // 处ç†åŠŸè€—çŠ¶æ€ + + PT_DELAY_MS(&pm.pt, system_is_idle() ? 1000 : 100); + } + + PT_END(&pm.pt); +} + +/* +请求功耗模å¼ï¼šå¼•ç”¨è®¡æ•°è‡ªå¢žï¼Œå¦‚果为1，则调用适é…器接å£ï¼Œè°ƒæ•´MCUçš„è¿è¡Œæ¨¡å¼ +*/ +void pt_pm_request(pm_mode_t mode) { + if (mode >= PM_SLEEP_MODE_MAX) { + return; // æ— æ•ˆæ¨¡å¼ + } + pm.ref_count[mode]++; // ä»…æ“作引用计数 +} + +/* +释放功耗模å¼ï¼šå¼•ç”¨è®¡æ•°è‡ªå‡ï¼Œå¦‚果为0，则调用适é…器接å£ï¼Œè°ƒæ•´MCUçš„è¿è¡Œæ¨¡å¼ +*/ +void pt_pm_release(pm_mode_t mode) { + if (mode >= PM_SLEEP_MODE_MAX) { + return; // æ— æ•ˆæ¨¡å¼ + } + if (pm.ref_count[mode] > 0) { + pm.ref_count[mode]--; // ä»…æ“作引用计数 + } +} diff --git a/pthreads/pt_pm.h b/pthreads/pt_pm.h new file mode 100644 index 0000000..2998d36 --- /dev/null +++ b/pthreads/pt_pm.h @@ -0,0 +1,33 @@ +#ifndef PT_PM_H +#define PT_PM_H + +#include "pt_task.h" + +typedef enum { + PM_SLEEP_MODE_NONE, + PM_SLEEP_MODE_IDLE, + PM_SLEEP_MODE_LIGHT, + PM_SLEEP_MODE_DEEP, + PM_SLEEP_MODE_STANDBY, + PM_SLEEP_MODE_POWER_DOWN, + PM_SLEEP_MODE_MAX +} pm_mode_t; + +typedef struct { + void (*sleep)(pm_mode_t mode); + void (*wakeup)(void); +} pm_adapter_t; + +extern void pt_pm_adapter_init(pm_adapter_t *adapter); + +extern void pt_pm_init(void); + +extern void pt_pm_request(pm_mode_t mode); + +extern void pt_pm_release(pm_mode_t mode); + +extern int pt_task_pm(void); + +#endif + + diff --git a/pthreads/pt_sem.h b/pthreads/pt_sem.h new file mode 100644 index 0000000..98ae25d --- /dev/null +++ b/pthreads/pt_sem.h @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the protothreads library. + * + * Author: Adam Dunkels + * + * $Id: pt-sem.h,v 1.2 2005/02/24 10:36:59 adam Exp $ + */ + +/** + * \addtogroup pt + * @{ + */ + +/** + * \defgroup ptsem Protothread semaphores + * @{ + * + * This module implements counting semaphores on top of + * protothreads. Semaphores are a synchronization primitive that + * provide two operations: "wait" and "signal". The "wait" operation + * checks the semaphore counter and blocks the thread if the counter + * is zero. The "signal" operation increases the semaphore counter but + * does not block. If another thread has blocked waiting for the + * semaphore that is signalled, the blocked thread will become + * runnable again. + * + * Semaphores can be used to implement other, more structured, + * synchronization primitives such as monitors and message + * queues/bounded buffers (see below). + * + * The following example shows how the producer-consumer problem, also + * known as the bounded buffer problem, can be solved using + * protothreads and semaphores. Notes on the program follow after the + * example. + * + \code +#include "pt-sem.h" + +#define NUM_ITEMS 32 +#define BUFSIZE 8 + +static struct pt_sem mutex, full, empty; + +PT_THREAD(producer(struct pt *pt)) +{ + static int produced; + + PT_BEGIN(pt); + + for(produced = 0; produced < NUM_ITEMS; ++produced) { + + PT_SEM_WAIT(pt, &full); + + PT_SEM_WAIT(pt, &mutex); + add_to_buffer(produce_item()); + PT_SEM_SIGNAL(pt, &mutex); + + PT_SEM_SIGNAL(pt, &empty); + } + + PT_END(pt); +} + +PT_THREAD(consumer(struct pt *pt)) +{ + static int consumed; + + PT_BEGIN(pt); + + for(consumed = 0; consumed < NUM_ITEMS; ++consumed) { + + PT_SEM_WAIT(pt, &empty); + + PT_SEM_WAIT(pt, &mutex); + consume_item(get_from_buffer()); + PT_SEM_SIGNAL(pt, &mutex); + + PT_SEM_SIGNAL(pt, &full); + } + + PT_END(pt); +} + +PT_THREAD(driver_thread(struct pt *pt)) +{ + static struct pt pt_producer, pt_consumer; + + PT_BEGIN(pt); + + PT_SEM_INIT(&empty, 0); + PT_SEM_INIT(&full, BUFSIZE); + PT_SEM_INIT(&mutex, 1); + + PT_INIT(&pt_producer); + PT_INIT(&pt_consumer); + + PT_WAIT_THREAD(pt, producer(&pt_producer) & + consumer(&pt_consumer)); + + PT_END(pt); +} + \endcode + * + * The program uses three protothreads: one protothread that + * implements the consumer, one thread that implements the producer, + * and one protothread that drives the two other protothreads. The + * program uses three semaphores: "full", "empty" and "mutex". The + * "mutex" semaphore is used to provide mutual exclusion for the + * buffer, the "empty" semaphore is used to block the consumer is the + * buffer is empty, and the "full" semaphore is used to block the + * producer is the buffer is full. + * + * The "driver_thread" holds two protothread state variables, + * "pt_producer" and "pt_consumer". It is important to note that both + * these variables are declared as static. If the static + * keyword is not used, both variables are stored on the stack. Since + * protothreads do not store the stack, these variables may be + * overwritten during a protothread wait operation. Similarly, both + * the "consumer" and "producer" protothreads declare their local + * variables as static, to avoid them being stored on the stack. + * + * + */ + +/** + * \file + * Couting semaphores implemented on protothreads + * \author + * Adam Dunkels + * + */ + +#ifndef __PT_SEM_H__ +#define __PT_SEM_H__ + +#include "pt.h" + +struct pt_sem { + unsigned int count; +}; + +/** + * Initialize a semaphore + * + * This macro initializes a semaphore with a value for the + * counter. Internally, the semaphores use an "unsigned int" to + * represent the counter, and therefore the "count" argument should be + * within range of an unsigned int. + * + * \param s (struct pt_sem *) A pointer to the pt_sem struct + * representing the semaphore + * + * \param c (unsigned int) The initial count of the semaphore. + * \hideinitializer + */ +#define PT_SEM_INIT(s, c) (s)->count = c + +/** + * Wait for a semaphore + * + * This macro carries out the "wait" operation on the semaphore. The + * wait operation causes the protothread to block while the counter is + * zero. When the counter reaches a value larger than zero, the + * protothread will continue. + * + * \param pt (struct pt *) A pointer to the protothread (struct pt) in + * which the operation is executed. + * + * \param s (struct pt_sem *) A pointer to the pt_sem struct + * representing the semaphore + * + * \hideinitializer + */ +#define PT_SEM_WAIT(pt, s) \ + do { \ + PT_WAIT_UNTIL(pt, (s)->count > 0); \ + --(s)->count; \ + } while(0) + +/** + * Signal a semaphore + * + * This macro carries out the "signal" operation on the semaphore. The + * signal operation increments the counter inside the semaphore, which + * eventually will cause waiting protothreads to continue executing. + * + * \param pt (struct pt *) A pointer to the protothread (struct pt) in + * which the operation is executed. + * + * \param s (struct pt_sem *) A pointer to the pt_sem struct + * representing the semaphore + * + * \hideinitializer + */ +#define PT_SEM_SIGNAL(pt, s) ++(s)->count + +#endif /* __PT_SEM_H__ */ + +/** @} */ +/** @} */ + diff --git a/pthreads/pt_task.c b/pthreads/pt_task.c new file mode 100644 index 0000000..ebf530b --- /dev/null +++ b/pthreads/pt_task.c @@ -0,0 +1,71 @@ +/* + * Implementation of automatic protothreads initialization and scheduling + */ + +#include "pt_task.h" +#include "stdio.h" + +static int task_start_sch_entry(pt_t *p) +{ + PT_BEGIN(p); + + PT_END(p); +} +PT_TASK_START(task_start_sch_entry); + + +static int task_end_sch_entry(pt_t *p) +{ + PT_BEGIN(p); + + + + PT_END(p); +} +PT_TASK_END(task_end_sch_entry); + +bool pt_task_is_active(pt_task_t *task) +{ + if( ( task->status < PT_WAITING ) && + (task->status< PT_EXITED) ){ + + return 1; + + }else{ + + return 0; + } +} + +/* + * Schedule all registered task functions + */ +void pt_task_schedule(void) +{ + pt_task_t* start = (pt_task_t*) PT_TASK_OBJ_START; + pt_task_t* end = (pt_task_t*) PT_TASK_OBJ_END; + + for (pt_task_t* task = start; task < end; task++) + { + if (task->fn_entry && task->pt && task->status < PT_ENDED) + { + task->status = task->fn_entry(task->pt); + } + } +} + + +bool pt_task_all_idle(void) +{ + bool is_idle = true; + pt_task_t* start = (pt_task_t*)PT_TASK_OBJ_START; + pt_task_t* end = (pt_task_t*)PT_TASK_OBJ_END; + for (pt_task_t* task = start; task < end; task++) { + if (task->pt && pt_task_is_active(task)) { + is_idle = false; + break; + } + } + return is_idle; +} + diff --git a/pthreads/pt_task.h b/pthreads/pt_task.h new file mode 100644 index 0000000..9ab350d --- /dev/null +++ b/pthreads/pt_task.h @@ -0,0 +1,100 @@ +#ifndef PT_TASK_H +#define PT_TASK_H + +#include "pt.h" + +#include "pt_sem.h" + +#include "pt_ext.h" + +#include "pt_pm.h" + +/* + * Structure for registered entries + * Contains the name, protothread control structure, and function pointers + * for initialization and entry functions. + */ +typedef struct pt pt_t; + +typedef struct +{ + const char name[24]; /* Entry name */ + pt_t* pt; /* Protothread control structure */ + int status; + int (*fn_entry)(pt_t *pt); /* Function pointer */ +} pt_task_t; + + +/* + * Register a scheduling entry function + * \param obj_name Unique identifier for the entry (max 7 chars) + * \param pt_ptr Protothread control structure pointer + * \param entry_func Entry point function (int (*)(pt_t *)) + */ +/* + * Register a scheduling entry function + * @param obj_name Unique identifier for the entry (max 7 chars) + * @param pt_ptr Protothread control structure pointer + * @param init_func Initialization function (int (*)(pt_t *)) + * @param entry_func Entry point function (int (*)(pt_t *)) + */ +#define PT_TASK_OBJ(obj_name) _pt_task_object_##obj_name + +//#define PT_TASK_OBJ_DECL(obj_name) pt_task_t PT_TASK_OBJ(obj_name) + + +/* + * Specific section boundary accessors for PT_SCHEDULE_SECTION + */ +#ifdef __CC_ARM + /* MDK ARM Compiler specific macros for PT_SCHEDULE_SECTION */ + #define PT_TASK_OBJ_START ((uint32_t)&PT_TASK_OBJ(start)) + #define PT_TASK_OBJ_END ((uint32_t)&PT_TASK_OBJ(end)) +#elif defined(__GNUC__) + extern char __start_PT_SCHEDULE[]; + extern char __stop_PT_SCHEDULE[]; + #define PT_SCHEDULE_START (uint32_t)__start_PT_SCHEDULE + #define PT_SCHEDULE_END (uint32_t)__stop_PT_SCHEDULE +#endif + + +#define PT_TASK_DECL(obj_name,level,entry_func) \ + static pt_t _pt_object_##obj_name; \ + static pt_task_t _pt_task_object_##obj_name\ + __attribute__((section("task._pt_obj_"#level), used)) = { \ + .name = #obj_name, \ + .pt = &(_pt_object_##obj_name), \ + .fn_entry =(entry_func) \ + } + + +#define PT_TASK_START(entry_func) PT_TASK_DECL(start,"00",entry_func) + +#define PT_TASK_BOARD_REG(entry_func) PT_TASK_DECL(entry_func,"01",entry_func) + +#define PT_TASK_DRIVER_REG(entry_func) PT_TASK_DECL(entry_func,"02",entry_func) + +#define PT_TASK_DEVICE_REG(entry_func) PT_TASK_DECL(entry_func,"03",entry_func) + +#define PT_TASK_COMPONENT_REG(entry_func) PT_TASK_DECL(entry_func,"04",entry_func) + +#define PT_TASK_THID_REG(entry_func) PT_TASK_DECL(entry_func,"05",entry_func) + +#define PT_TASK_APP_REG(entry_func) PT_TASK_DECL(entry_func,"06",entry_func) + +#define PT_TASK_END(entry_func) PT_TASK_DECL(end,"99",entry_func) + +/* + * Prototypes for auto management functions + */ +void pt_task_init(void); + +void pt_task_schedule(void); + +bool pt_task_is_active(pt_task_t *task); + +bool pt_task_all_idle(void); + +#endif + + diff --git a/version.txt b/version.txt new file mode 100644 index 0000000..3aad5d3 --- /dev/null +++ b/version.txt @@ -0,0 +1,267 @@ +version date comment +2.0.0 + Apr 16, 2021 1. Support new hardware: EV_F460_LQ100_V2; + 2. add USB lib and example. + +1.3.1 Apr 09, 2021 1. Add usb example usb_host_hid_msc. + +1.3.0 + Feb 04, 2021 1. Fixed a bug of API HASH_Start(). + 2. Bug Fixed for example clk_switch_sysclk.#PWC_HS2HP should be called before clock is ready. + 3. Add note for API(PWC_HP2LS etc) in pwc.c. + 4. Modified TBDs as 30us base 200Mhz in clk.c. + + Jan 25, 2021 1. Fix bug for usbd_hid_custom example(about windows 10). + + Jan 18, 2021 1. Modified function ADC_ChannleRemap(), from ADC_ChannleRemap() to ADC_ChannelRemap(). + 2. Fixed a bug of function ADC_PollingSa(). + +1.2.0 + Dec 16, 2020 1. Add API XXX_ComTriggerCmd() and modify XXX_SetTriggerSrc() (XXX=ADC/DCU/OTS/TimerA/Timer0/Timer6/EventPort/DMA). + + Dec 15, 2020 1. Fix bug for usbh_hid_core.c(The HID report data will not be decoded if the USBH_Process() not process in time). + 2. Add register AOS_COMTRG1/2 + + Dec 11, 2020 1. Modify define for USB_MAX_STR_DESC_SIZ. + 2. Fix bug for USB device USBD_GetDescriptor function. + + Dec 03, 2020 + 1. Fixed SysTick_Delay function overflow handling. + + Dec 02,2020 1. Modified func. CAN_IrqFlgClr() + 2. Add CLKInit() function (Config system clock as 200M) to example lpm_pwerdown_wakeup + + Nov 30,2020 1. Add lmp_lwp(lowest power) example to lpm. + 2. Modify PWC driver. + 3. Add example usbh_msc_mouse_kb and modify USB lib for PHY clock config. + + Nov 16,2020 1. Add communication function for I2C example. + Nov 10,2020 1. Revise I2C TxEmpty & Complete share IRQ handler entry. + 2. Revise SPI idle share IRQ handler flag judgment. + + Oct 30,2020 1. Rename register DMA_CHxCTL bit4 SRTPEN as SRPTEN +1.1.1 + Oct 27,2020 1. Modify I2C driver and I2C example. + Oct 19,2020 1. Modify USART UART/smartcard/clock-sync initialization function. + + Oct 13,2020 1. Modify PWC_WKTM_WKUPFLAG as 0x80. + 2. Remove definition PWC_RXD0_WKUPFLAG. + 3. Write 1 to bit14 in STPMCR. + + Sep 25,2020 1. Rename Interrupt/Event source in hc32f46x.h: INT_I2Cx_EE1 to INT_I2Cx_EEI, EVT_I2Cx_EE1 to EVT_I2Cx_EEI. + 2. Fixed some spelling mistakes. + + Sep 15,2020 1. Modify i2s driver for duplex mode and add example i2s_fullduplex. + 2. Modify i2s clock pclk source from pclk3 to pclk1. + 3. Add systick related function to the utility driver. + 4. Add systick example. + + Aug 28,2020 1. Fix bug for example usbd_mouse. + 2. Modify macro define in usb_conf.h file. + 3. Modify usbd_cdc_Setup() function for USBD CDC class. + 4. Update the drivers and examples based on the header file. + 5. Fix bug for i2c_slave_polling. + 6. Update headfile for i2c DTR and DRR register. + + Jul 31,2020 1. Synchronize driver register with chip manual. + + Jul 20,2020 1. Add wait RDY at begin of func. EFM_SetErasePgmMode(). + 2. Modified en_efm_erase_pgm_md_t as #define + + Jul 7,2020 1. Fixed a bug in spi_write_read_flash example. + 2. Remove register XTAL32CFGR XTAL32SUPDRV bit + 3. Modified func. DMA_ReConfig() function & add func. DMA_ReCfgLlp() + 4. Modified func. PWC_PdWakeupEvtEdgeCfg() & add func. PWC_ClearPvdFlag() + 5. Modified comment & spell error + + May 21,2020 1. unify EFM wait cycle for all examples + 2. KEYSCAN example refine + + Feb 27,2020 1. Driver refine for PWC/CLK + + Feb 14,2020 1. Logic error in timer4 reload share irq + + Jan 08,2020 1. Added GCC compiler support. + 2. Added Eclipse project files for each example project. + 3. Fixed a bug of IS_ADC_TRIG_SRC_EVENT in hc32f46x_adc.c. + 4. Fixed a bug of function AdcChannelConfig in ..\example\adc\adc_10_internal_channel\source\main.c. + + Jan 07,2020 1. Modify usbh_mouse_kb example for GCC compiler. + 2. Modify readme file for usbh_msc example. + + Jan 06,2020 1. Fixed a bug in example adc_10_internal_channel. + Turn on the clock of CMP while ADC input source is internal VREF. + + Jan 06,2020 1. Fix bug for CMP CMP_ADC_SetRefVoltPath function. + + Dec 30,2019 1. Set FPU function in system initialization stage. + + Dec 24,2019 1. Add USB host example -> HID mouse and Keyboard. + 2. Refine ext int example. + + Dec 13,2019 1. Modify media data for i2s_play_wm8731_44k and i2s_play_wm8731_exck_8k example. + + Dec 12,2019 1. Add AsyncDelay for timer0 driver. + 2. Check operation result when switch speed for SD midware. + 3. Remove limit of 4 bytes align for SD write/read buffer. + 4. Dmac.c typo + 5. Delete some duplicate files + + Dec 11,2019 1. Fix bug for TIMERA_OrthogonalCodingInit function. + + Dec 10,2019 1. Modify USBLIB for GCC compiler. + 2. Add Timeout function for timer0 driver. + + Dec 6,2019 1. Modify the wrong word of QSPI example. + + Dec 4,2019 1. Fix bug for TIMERA_HwTriggerInit and TIMERA_HwClearConfig Function. + + Nov 22,2019 1. Fix bug for I2C slave example: Clear STOP and NACK flag after address flag detected. + + Nov 19,2019 1. add hid_msc composite device demo + 2. MISRAC2004 for some source files + + Nov 11,2019 1. modify for USBLIB: Add IAD descriptor for VCP device. + + Nov 8,2019 1. Added support for GCC. + + Nov 5,2019 1. modify for USBLIB: re-open usb clock in DCD_SessionRequest_ISR function + 2. Fix bug for example i2c_slave_irq + + Nov 1,2019 1. Fix bug for mem_cmp function in ff.c. + 2. Correct access width from u32 to u16 of GPIO regs: PODR, POER, POSR, PORR, POTR + + Oct 30,2019 1. Fix bug for QSPI_PrefetchCmd Function. + + Oct 21,2019 1. Add function CLK_ClearXtalStdFlg to clk.c + 2. Modified function PWC_EnterPowerDownMd #add 30 clock cycle after set PWDN + 3. Fix bug for I2S_ClrErrFlag function + + Oct 10,2019 1. Move PWC_EnterPowerDownMd func to ran for IAR + + Oct 9, 2019 1. Modified Set function(transfer count, block size, src/dest address etc.) in dma.c + + Sept 27,2019 1. Fixed bug for function CLK_SysClkConfig # CMU_SCFGR register reserved bits 31~28 should be equal with bits 27~24 + + Sept 25,2019 1. Add examples of Timer6 module. + 2. Add Trigger source config API of Timer6 + +1.1.0 + Sept 16,2019 1. Modify startup file for KEIL project. + 2. Fix bug when using KEIL compiler.(USBFS Register GRXSTSP is read for multiple times.) + + Aug 29, 2019 1. modify DDL code for C-STAT and MISRA-2004 warning. + 2. add RAM3 wait-time in startup_hc32f46x.s + +1.0.4 + July 31, 2019 1. Fix bug for i2c_at24c02 example. + + July 29, 2019 1. modify for timer0 driver: timer0 UNIT1 channelA can't configured as synchronous mode. + 2. modify the port configuration for USB example. + + July 25, 2019 1. Modify usb_core.c, Configuration FIFO for each IN ENDPOINT. + 2. Add device class hid_custom. + Add device class composite device(HID + CDC) + 3. modify device class name from "hid" to "hid_mouse". + modify device class name from "vcp" to "cdc_vcp" + 4. Add example hid_custom. + Add example composite device cdc_hid + + July 16, 2019 1. modified CMP driver enumeration en_cmp_inp4_sel_t + 2. modify spelling mistake for "position" + 3. modify macro UART_DEBUG_PRINTF to hc32f46x_utility.h file + + July 2, 2019 1. modified SRAM_Init + 2. add SRAM_Init to clk_switch_sysclk sample, mainly setting sram + read/write cycle + + July 1, 2019 1. Fix bug for I2S_FuncCmd() function. + 2. Modify headfile hc32f46x.h for keyscan. + + June 19, 2019 1. dma.c & dma.h + add readback to ensure write correct to DMA DMA_SetXx fun. + add wait running channel disable before DMA_ChannelCmd. + modified the functions DMA_SetXx & DMA_ChannelCmd void as en_result_t + + Jun 6, 2019 1. add USB CDC VCP + 2. comment assert() in usart baudrate failure case + + Jun 3, 2019 1. modify MPU protection regions write/read permission functions + + May 29, 2019 1. Add comment to func CLK_GetI2sClkSource in hc32f46x_clk.c + 2. interrupt.c + SPI_SPEI and SPI_SPII bit position in share IRQ register of SPI.1~4 + + May 28, 2019 1. Fix bug for i2c_master_polling example. + 2. modifid PIDRH register + 3. delete setupxx at .mac file + + May 24, 2019 1. convert encoding to UTF-8 for readme.txt + 2. add clock division interface of SPI + 3. add clock division and WP_Pin level interface of QSPI + 4. modify some words to be misspelled + 5. add USB MSC device card reader + 6. add MW_W25QXX_ENABLE in all ddl_config.h + 7. modify comment for usb lib and example + 8. modify device PID and VID + 9. add CLK_GetPllClockFreq function + 10.add CLK_GetI2sClkSource function + 11.modify Timer4 pwm: POCR register channel offset + 12.fix bug for i2s slave mode + 13.add DAM MON_xx register + 14.modified ICG.HRCFREQSEL as 1 bit + 15.add RTC CR1.ALMFCLR, CR2.ALMF + 16.add EFM FRMC.LVM + 17.add alarm flag to RTC + 18.set USB 1st DeviceDescriptor len to 8 + 19.synchronize hc32f46x_ddl.chm version to 1.0.4 and update above + + 1.0.3 May 15, 2019 1. add EFM_ClearFlag at ahead of program & erase + 2. comment valid check in EFM_ClearFlag + + May 8, 2019 1. usb driver + use SPACE instead of TAB + 2. interrupt + typo + delete RTC interrupt ISR in share IRQ handler + EfmPageEraseErr_IrqHandler --> EfmPgmEraseErr_IrqHandler + 3. exint_nmi_swi + delete callback function pointer in exint init structure + + Apr 26, 2019 1. modified CMU_ClrResetFlag func. comment + + Apr 22, 2019 1. word spelling error + 2. upll setting for adc/usb/trng + + Apr 18, 2019 1. modify comments about OVER8 = 1 + 2. modify baudrate calculate + 3. delete duplicated semicolon + + Apr 9, 2019 1. modified IS_XTAL_STOP_VALID & IS_HRC_STOP_VALID + 2. add judge before IS_XXX_STOP_VALID + + Apr 4, 2019 1. recover IS_PLLQ_DIV_VALID, recover CLK_PLLM_MIN as 1u + 2. add IS_UPLLM_VALID because of upllm 2~24 and pllm 1~24 + 3. modified func CLK_UpllConfig , IS_PLLM_VALID as + IS_UPLLM_VALID and comment pllm between 1M and 24M + 4. modified CLK_PLLM_MIN as 2u, CLK_PLLN_MAX as 480u + 5. use IS_PLL_DIV_VALID instead of IS_PLLQ_DIV_VALID + 6. modified func CLK_MpllConfig comment, pllsource/pllm + is between 1MHz and 24MHz. + + Apr 1, 2019 1. add EP2 OUT function for HID device + + Mar 18, 2019 1. update chm file according to src updating + + Mar 15, 2019 1. add CRC driver & sample + 2. bug fix + ICG/PWC/CLK/I2C + + Mar 11, 2019 1. modify efm/rtc/clk/ driver & sample + 2. update SFR & SVD for IDE + 3. add 'ram.ini' for MDK RAM function + 4. add CRC pre-process + + Mar 7, 2019 1. first release on github.com + +EOF diff --git a/串å£å‡çº§åè®®.xlsx b/串å£å‡çº§åè®®.xlsx new file mode 100644 index 0000000..bf95684 Binary files /dev/null and b/串å£å‡çº§åè®®.xlsx differ