226 lines
8.0 KiB
C
226 lines
8.0 KiB
C
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/**
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*******************************************************************************
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* @file hc32_ll_tmr0.h
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* @brief This file contains all the functions prototypes of the TMR0 driver
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* library.
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@verbatim
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Change Logs:
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Date Author Notes
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2022-03-31 CDT First version
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2023-06-30 CDT Modify typo
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@endverbatim
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*******************************************************************************
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* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by XHSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#ifndef __HC32_LL_TMR0_H__
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#define __HC32_LL_TMR0_H__
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_ll_def.h"
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#include "hc32f4xx.h"
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#include "hc32f4xx_conf.h"
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/**
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* @addtogroup LL_Driver
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* @{
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*/
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/**
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* @addtogroup LL_TMR0
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* @{
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*/
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#if (LL_TMR0_ENABLE == DDL_ON)
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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* @defgroup TMR0_Global_Types TMR0 Global Types
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* @{
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*/
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/**
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* @brief TMR0 initialization structure definition
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* @note The 'u32ClockDiv' is invalid when the value of 'u32ClockSrc' is "TMR0_CLK_SRC_SPEC_EVT".
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*/
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typedef struct {
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uint32_t u32ClockSrc; /*!< Specifies the clock source of TMR0 channel.
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This parameter can be a value of @ref TMR0_Clock_Source */
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uint32_t u32ClockDiv; /*!< Specifies the clock division of TMR0 channel.
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This parameter can be a value of @ref TMR0_Clock_Division */
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uint32_t u32Func; /*!< Specifies the function of TMR0 channel.
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This parameter can be a value of @ref TMR0_Function */
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uint16_t u16CompareValue; /*!< Specifies the compare value of TMR0 channel.
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This parameter can be a value of half-word */
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} stc_tmr0_init_t;
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/**
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* @}
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*/
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/**
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* @defgroup TMR0_Global_Macros TMR0 Global Macros
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* @{
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*/
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/**
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* @defgroup TMR0_Channel TMR0 Channel
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* @{
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*/
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#define TMR0_CH_A (0UL)
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#define TMR0_CH_B (1UL)
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/**
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* @}
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*/
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/**
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* @defgroup TMR0_Clock_Source TMR0 Clock Source
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* @note In asynchronous clock, continuous operation of the BCONR register requires waiting for 3 asynchronous clocks.
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* @{
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*/
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#define TMR0_CLK_SRC_INTERN_CLK (0UL) /*!< Internal clock (Synchronous clock) */
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#define TMR0_CLK_SRC_SPEC_EVT (TMR0_BCONR_SYNCLKA) /*!< Specified event (Synchronous clock) */
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#define TMR0_CLK_SRC_LRC (TMR0_BCONR_SYNSA) /*!< LRC (Asynchronous clock) */
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#define TMR0_CLK_SRC_XTAL32 (TMR0_BCONR_ASYNCLKA | TMR0_BCONR_SYNSA) /*!< XTAL32 (Asynchronous clock) */
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/**
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* @}
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*/
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/**
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* @defgroup TMR0_Clock_Division TMR0 Clock Division
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* @{
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*/
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#define TMR0_CLK_DIV1 (0UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK */
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#define TMR0_CLK_DIV2 (1UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/2 */
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#define TMR0_CLK_DIV4 (2UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/4 */
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#define TMR0_CLK_DIV8 (3UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/8 */
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#define TMR0_CLK_DIV16 (4UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/16 */
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#define TMR0_CLK_DIV32 (5UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/32 */
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#define TMR0_CLK_DIV64 (6UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/64 */
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#define TMR0_CLK_DIV128 (7UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/128 */
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#define TMR0_CLK_DIV256 (8UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/256 */
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#define TMR0_CLK_DIV512 (9UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/512 */
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#define TMR0_CLK_DIV1024 (10UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/1024 */
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/**
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* @}
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*/
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/**
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* @defgroup TMR0_Function TMR0 Function
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* @{
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*/
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#define TMR0_FUNC_CMP (0UL) /*!< Output compare function */
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#define TMR0_FUNC_CAPT (TMR0_BCONR_CAPMDA | TMR0_BCONR_HICPA) /*!< Input capture function */
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/**
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* @}
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*/
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/**
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* @defgroup TMR0_Interrupt TMR0 Interrupt
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* @{
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*/
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#define TMR0_INT_CMP_A (TMR0_BCONR_INTENA)
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#define TMR0_INT_CMP_B (TMR0_BCONR_INTENB)
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#define TMR0_INT_ALL (TMR0_INT_CMP_A | TMR0_INT_CMP_B)
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/**
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* @}
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*/
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/**
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* @defgroup TMR0_FLAG TMR0 Flag
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* @{
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*/
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#define TMR0_FLAG_CMP_A (TMR0_STFLR_CMFA)
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#define TMR0_FLAG_CMP_B (TMR0_STFLR_CMFB)
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#define TMR0_FLAG_ALL (TMR0_FLAG_CMP_A | TMR0_FLAG_CMP_B)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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Global function prototypes (definition in C source)
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******************************************************************************/
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/**
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* @addtogroup TMR0_Global_Functions
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* @{
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*/
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/* Initialization functions */
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void TMR0_DeInit(CM_TMR0_TypeDef *TMR0x);
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int32_t TMR0_Init(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, const stc_tmr0_init_t *pstcTmr0Init);
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int32_t TMR0_StructInit(stc_tmr0_init_t *pstcTmr0Init);
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void TMR0_Start(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch);
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void TMR0_Stop(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch);
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/* Control configuration functions */
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void TMR0_SetCountValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value);
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uint16_t TMR0_GetCountValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch);
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void TMR0_SetCompareValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value);
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uint16_t TMR0_GetCompareValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch);
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void TMR0_SetClockSrc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Src);
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void TMR0_SetClockDiv(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Div);
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void TMR0_SetFunc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Func);
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/* Hardware trigger Functions */
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void TMR0_HWCaptureCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState);
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void TMR0_HWStartCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState);
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void TMR0_HWStopCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState);
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void TMR0_HWClearCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState);
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/* Interrupt and flag management functions */
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void TMR0_IntCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32IntType, en_functional_state_t enNewState);
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en_flag_status_t TMR0_GetStatus(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag);
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void TMR0_ClearStatus(CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag);
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/**
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* @}
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*/
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#endif /* LL_TMR0_ENABLE */
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HC32_LL_TMR0_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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