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YuanHongbin
2026-06-01 18:15:20 +08:00
parent 2786112b83
commit 4758a7f04e
134 changed files with 96670 additions and 0 deletions
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Project/source/Module/CS1237/CS1237_LEFTLOW.c
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#include "CS1237_LEFTLOW.h"
#include "Debug.h"
#include "bsp.h"
#include "main.h"
#include "Algorithm.h"
#define CS1237_DOUT_OUT() PORT_OE(LEFTLOW_CS1237_DOUT_PORTx, LEFTLOW_CS1237_DOUT_PINx, Enable)
#define CS1237_DOUT_IN() PORT_OE(LEFTLOW_CS1237_DOUT_PORTx, LEFTLOW_CS1237_DOUT_PINx, Disable)
#define CS1237_DOUT_H() SET_LEFTLOW_CS1237_DOUT()
#define CS1237_DOUT_L() CLR_LEFTLOW_CS1237_DOUT()
#define CS1237_DOUT_GET() GET_LEFTLOW_CS1237_DOUT()
#define CS1237_SCLK_H() SET_LEFTLOW_CS1237_SCLK()
#define CS1237_SCLK_L() CLR_LEFTLOW_CS1237_SCLK()
#define CS1237_5NS(x) delay_5ns(x) //5ns延时
#define CS1237_1US(x) Ddl_Delay1us(x) //1us延时
#define CS1237_1MS(x) Ddl_Delay1ms(x) //1ms延时
#define CS1237IntEnable() ExtInt01IntEnable()
#define CS1237IntDisable() ExtInt01IntDisable()
LEFTLOW_CS1237Var_t LEFTLOW_CS1237Var;
static bool InitFlag;
static bool CS1237IrqFlag;
static bool BuildDelay;
static uint8_t CS1237Port;
static uint8_t CS1237Hz;
static uint8_t CS1237PGA;
extern void LEFTLOW_CS1237AinADataProcessCallBack(int32_t AD);
/** cs1237 时序时钟*/
static void CS1237_Clock(void)
{
CS1237_SCLK_H();
CS1237_5NS(60);
CS1237_SCLK_L();
CS1237_5NS(60);
}
/** cs1237 休眠*/
static void CS1237_Sleep(void)
{
CS1237_SCLK_H();
CS1237_1US(200);
}
/** cs1237 唤醒*/
static void CS1237_WakeUp(void)
{
CS1237_SCLK_L();
CS1237_1US(20);
}
/**设置CS1237寄存器*/
static void Set_CS1237_Config(uint8_t ad_reg)
{
uint16_t bit_cout = 0;
uint8_t reg_temp = 0x00;
//DOUT由高变低之后开始读取数据
CS1237_DOUT_OUT();
CS1237_DOUT_H();
CS1237_DOUT_IN();
CS1237_SCLK_L(); //时钟拉低
LEFTLOW_CS1237Var.CS1237Delay1mSCnt = 300;
CS1237IrqFlag = false;
while(CS1237IrqFlag == false) //等待芯片准备好
{
if(LEFTLOW_CS1237Var.CS1237Delay1mSCnt <= 0){
//DBG_LOG("LEFTLOW CS1237 Preparation Timeout...\r\n");
return; // 超时退出
}
}
CS1237IntDisable();
CS1237IrqFlag = false;
/* clk1-clk26 写期间不需要操作*/
for (bit_cout = 0; bit_cout < 26; bit_cout++)
{
CS1237_Clock(); //给一周期时钟
}
/* clk27 DOUT输出拉高*/
CS1237_Clock(); //给一周期时钟
CS1237_DOUT_H();
/* clk28 - clk29 发送写寄存器命令字 */
CS1237_Clock(); //给一周期时钟
CS1237_Clock(); //给一周期时钟
/* clk30 - clk36 发送写寄存器命令字 */
CS1237_DOUT_OUT();
reg_temp = WRITE_CONFIG_CMD << 1; //命令长度为 7bits (写0x65)左移1位
for (bit_cout = 0; bit_cout < 7; bit_cout++)
{
if (reg_temp & 0x80) //MSB
{
CS1237_DOUT_H();
}
else
{
CS1237_DOUT_L();
}
reg_temp = reg_temp << 1;
CS1237_Clock();
}
/* clk37写寄存器模式还是输出 */
CS1237_Clock();
/* clk38 ~ clk45 写入寄存器值 */
reg_temp = ad_reg;//要配件的寄存器数值
for (bit_cout = 0; bit_cout < 8; bit_cout++)
{
if (reg_temp & 0x80) //MSB
{
CS1237_DOUT_H();
}
else
{
CS1237_DOUT_L();
}
reg_temp = reg_temp << 1;
CS1237_Clock();
}
/* 8: clk46 */
CS1237_Clock();
CS1237_DOUT_H();
CS1237_DOUT_IN();
CS1237IntEnable();
return ;
}
/**读CS1237寄存器*/
static int32_t Read_CS1237_Config(void)
{
uint16_t bit_cout = 0;
uint8_t reg_temp = 0x00;
//DOUT由高变低之后开始读取数据
CS1237_DOUT_OUT();
CS1237_DOUT_H();
CS1237_DOUT_IN();
CS1237_SCLK_L(); //时钟拉低
LEFTLOW_CS1237Var.CS1237Delay1mSCnt = 300;
CS1237IrqFlag = false;
while(CS1237IrqFlag == false) //等待芯片准备好
{
if(LEFTLOW_CS1237Var.CS1237Delay1mSCnt <= 0){
//DBG_LOG("LEFTLOW CS1237 Preparation Timeout...\r\n");
return 0; // 超时退出
}
}
CS1237IntDisable();
CS1237IrqFlag = false;
/* clk1-clk26 写期间不需要操作*/
for (bit_cout = 0; bit_cout < 26; bit_cout++)
{
CS1237_Clock(); //给一周期时钟
}
/* clk27 DOUT输出拉高*/
CS1237_Clock(); //给一周期时钟
CS1237_DOUT_H();
/* clk28 - clk29 发送写寄存器命令字 */
CS1237_Clock(); //给一周期时钟
CS1237_Clock(); //给一周期时钟
/* clk30 - clk36 发送读寄存器命令字 */
CS1237_DOUT_OUT();
reg_temp = READ_CONFIG_CMD << 1; //命令长度为 7bits (写0x56)左移1位
for (bit_cout = 0; bit_cout < 7; bit_cout++)
{
if (reg_temp & 0x80) //MSB
{
CS1237_DOUT_H();
}
else
{
CS1237_DOUT_L();
}
reg_temp = reg_temp << 1;
CS1237_Clock();
}
/* clk37，读寄存器模式改输入 */
CS1237_Clock();
CS1237_DOUT_IN();
for (bit_cout = 0; bit_cout < 8; bit_cout++)
{
CS1237_SCLK_H();
reg_temp <<= 1; //左移1位准备接受数据 初始默认0
CS1237_5NS(60);//延时300ns
if(CS1237_DOUT_GET() == true) //有数值则累加
reg_temp |= 1;
CS1237_SCLK_L();
CS1237_5NS(60);
}
/* 8: clk46 */
CS1237_Clock();
CS1237_DOUT_IN();
CS1237_DOUT_H();
CS1237IntEnable();
return reg_temp ;
}
/**读取CS1237的AD数*/
static int32_t Read_CS1237_Ad_Data(void)
{
uint16_t bit_cout = 0;
int32_t data_temp = 0;
/* clk1 ~ clk24 ADC数据*/
data_temp = 0;
for (bit_cout = 0; bit_cout < 24; bit_cout++)
{
CS1237_SCLK_H();
data_temp <<= 1; //左移1位准备接受数据 初始默认0
CS1237_5NS(60);//延时300ns
if(CS1237_DOUT_GET() == true) //有数值则累加
data_temp |= 1;
CS1237_SCLK_L();
CS1237_5NS(60);
}
/* clk25 ~ clk27 */
for (bit_cout = 24; bit_cout < 27; bit_cout++)
{
CS1237_Clock(); //给一周期时钟
}
CS1237_DOUT_H();
CS1237_SCLK_L();
if(data_temp > 0x7FFFFF) //取24位
{
data_temp |= 0xFF000000;
}
return data_temp;
}
void LEFTLOW_CS1237_IrqCallBack(void)
{
CS1237IrqFlag = true;
}
void LEFTLOW_CS1237_Init(void)
{
CS1237IrqFlag = false;
BuildDelay = false;
LEFTLOW_CS1237Var.AinA_AD = 0;
LEFTLOW_CS1237Var.Temp_AD = 0;
LEFTLOW_CS1237Var.Jump_AD = 0;
CS1237IntEnable();
CS1237Port = CH_SEL_A;
CS1237Hz = SPEED_SEL_640Hz;
CS1237PGA = PGA_SEL_128;
uint8_t read_reg = 0x00;
uint8_t set_reg = REFO_ON | CS1237Hz | CS1237PGA | CS1237Port;
CS1237_1MS(20);
Set_CS1237_Config(set_reg);
CS1237_1MS(20);
read_reg = Read_CS1237_Config();
CS1237_1MS(20);
if(read_reg != set_reg){
DBG_LOG("LEFTLOW CS1237 Init ERR...\r\n");
//DBG_LOG("set_reg = %02X\tread_reg = %02X\r\n",set_reg,read_reg);
InitFlag = true;
}
else {
DBG_LOG("LEFTLOW CS1237 Init OK...\r\n");
//DBG_LOG("set_reg = %02X\tread_reg = %02X\r\n",set_reg,read_reg);
CS1237Port = read_reg & 0x03;
InitFlag = true;
}
CS1237IntDisable();
}
void LEFTLOW_CS1237DataLoopCollect(void)
{
static int32_t ad_array[PACK_NUM];
static uint8_t adcnt;
static uint8_t TimeOutmagcnt;
switch(LEFTLOW_CS1237Var.Status) {
case LLCS1237_STATUS_IDLE:{
break;}
case LLCS1237_STATUS_START:{
memset(&ad_array, 0x00, sizeof(ad_array));
adcnt = 0;
TimeOutmagcnt = 0;
memset(&LEFTLOW_CS1237Var, NULL, sizeof(LEFTLOW_CS1237Var));
if(BuildDelay == true)
{
BuildDelay = false;
if(CS1237Hz == SPEED_SEL_10Hz){
LEFTLOW_CS1237Var.CS1237Delay1mSCnt = tCon_10Hz;
}
if(CS1237Hz == SPEED_SEL_40Hz){
LEFTLOW_CS1237Var.CS1237Delay1mSCnt = tCon_40Hz;
}
if(CS1237Hz == SPEED_SEL_640Hz){
LEFTLOW_CS1237Var.CS1237Delay1mSCnt = tCon_640Hz;
}
if(CS1237Hz == SPEED_SEL6_1280Hz){
LEFTLOW_CS1237Var.CS1237Delay1mSCnt = tCon_1280Hz;
}
LEFTLOW_CS1237Var.Status = LLCS1237_STATUS_DELAY;
}
else
{
LEFTLOW_CS1237Var.Status = LLCS1237_STATUS_READ;
}
break;}
case LLCS1237_STATUS_DELAY:{
if(LEFTLOW_CS1237Var.CS1237Delay1mSCnt <= 0){
LEFTLOW_CS1237Var.Status = LLCS1237_STATUS_READ;
}
break;}
case LLCS1237_STATUS_READ:{
CS1237IrqFlag = false;
LEFTLOW_CS1237Var.CS1237Delay1mSCnt = 100;
LEFTLOW_CS1237Var.Status = LLCS1237_STATUS_WAIT_READ;
break;}
case LLCS1237_STATUS_WAIT_READ:{
if(LEFTLOW_CS1237Var.CS1237Delay1mSCnt <= 0){
LEFTLOW_CS1237Var.Status = LLCS1237_STATUS_READ;
TimeOutmagcnt++;
}
if(CS1237IrqFlag == true){
CS1237IrqFlag = false;
ad_array[adcnt++] = Read_CS1237_Ad_Data();
LEFTLOW_CS1237Var.Status = LLCS1237_STATUS_READ;
}
if(TimeOutmagcnt >= PACK_NUM){
TimeOutmagcnt = 0;
if(adcnt > 0){
if(CS1237Port == CH_SEL_A){
LEFTLOW_CS1237Var.AinA_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
LEFTLOW_CS1237AinADataProcessCallBack(LEFTLOW_CS1237Var.AinA_AD);
}
if(CS1237Port == CH_SEL_TEMP){
LEFTLOW_CS1237Var.Temp_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
//CS1237TempDataProcessCallBack(LEFTLOW_CS1237Var.Temp_AD);
}
if(CS1237Port == CH_SEL_JUMP){
LEFTLOW_CS1237Var.Jump_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
//CS1237JumpDataProcessCallBack(LEFTLOW_CS1237Var.Jump_AD);
}
LEFTLOW_CS1237Var.Status = LLCS1237_STATUS_CH_SEL;
}
else{
if(CS1237Port == CH_SEL_A){
DBG_LOG("LEFTLOW CS1237 CHA TimeOut...\r\n");
}
if(CS1237Port == CH_SEL_TEMP){
DBG_LOG("LEFTLOW CS1237 Temp TimeOut...\r\n");
}
if(CS1237Port == CH_SEL_JUMP){
DBG_LOG("LEFTLOW CS1237 Jump TimeOut...\r\n");
}
LEFTLOW_CS1237Var.Status = LLCS1237_STATUS_CH_SEL;
}
}
if(adcnt >= PACK_NUM){
if(CS1237Port == CH_SEL_A){
LEFTLOW_CS1237Var.AinA_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
LEFTLOW_CS1237AinADataProcessCallBack(LEFTLOW_CS1237Var.AinA_AD);
}
if(CS1237Port == CH_SEL_TEMP){
LEFTLOW_CS1237Var.Temp_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
//CS1237TempDataProcessCallBack(LEFTLOW_CS1237Var.Temp_AD);
}
if(CS1237Port == CH_SEL_JUMP){
LEFTLOW_CS1237Var.Jump_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
//CS1237JumpDataProcessCallBack(LEFTLOW_CS1237Var.Jump_AD);
}
LEFTLOW_CS1237Var.Status = LLCS1237_STATUS_CH_SEL;
}
break;}
case LLCS1237_STATUS_CH_SEL:{
LEFTLOW_CS1237Var.Status = LLCS1237_STATUS_STOP;
BuildDelay = false;
uint8_t read_reg;
if(CS1237Port == CH_SEL_A){
#if(PORT_TEMP == 1)
read_reg = Read_CS1237_Config();
Set_CS1237_Config((read_reg & 0xFC) | CH_SEL_TEMP);
CS1237Port = CH_SEL_TEMP;
BuildDelay = true;
break;
#endif
#if(PORT_JUMP == 1)
read_reg = Read_CS1237_Config();
Set_CS1237_Config((read_reg & 0xFC) | CH_SEL_JUMP);
CS1237Port = CH_SEL_JUMP;
BuildDelay = true;
break;
#endif
}
if(CS1237Port == CH_SEL_TEMP){
#if(PORT_JUMP == 1)
read_reg = Read_CS1238_Config();
Set_CS1238_Config((read_reg & 0xFC) | CH_SEL_JUMP);
CS1238Port = CH_SEL_JUMP;
BuildDelay = true;
break;
#endif
#if(PORT_A == 1)
read_reg = Read_CS1237_Config();
Set_CS1237_Config((read_reg & 0xFC) | CH_SEL_A);
CS1237Port = CH_SEL_A;
BuildDelay = true;
break;
#endif
}
if(CS1237Port == CH_SEL_JUMP){
#if(PORT_A == 1)
read_reg = Read_CS1237_Config();
Set_CS1237_Config((read_reg & 0xFC) | CH_SEL_A);
CS1237Port = CH_SEL_A;
BuildDelay = true;
break;
#endif
#if(PORT_TEMP == 1)
read_reg = Read_CS1237_Config();
Set_CS1237_Config((read_reg & 0xFC) | CH_SEL_TEMP);
CS1237Port = CH_SEL_TEMP;
BuildDelay = true;
break;
#endif
}
break;}
case LLCS1237_STATUS_STOP:{
LEFTLOW_CS1237Stop();
LEFTLOW_CS1237Var.Status = LLCS1237_STATUS_IDLE;
//LEFTLOW_CS1237Var.Status = LLCS1237_STATUS_START;//持续工作
break;}
}
}
void LEFTLOW_CS12371mSRoutine(void)
{
if(LEFTLOW_CS1237Var.CS1237Delay1mSCnt > 0)
LEFTLOW_CS1237Var.CS1237Delay1mSCnt--;
}
void LEFTLOW_CS1237Start(void)
{
CS1237_WakeUp();
CS1237_1MS(2);
BuildDelay = true;
CS1237IntEnable();
if(!InitFlag){
LEFTLOW_CS1237_Init();
return;
}
LEFTLOW_CS1237Var.Status = LLCS1237_STATUS_START;
}
void LEFTLOW_CS1237Stop(void)
{
CS1237IntDisable();
//CS1237_Sleep();
}
Project/source/Module/CS1237/CS1237_LEFTLOW.h
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#include "bsp.h"
#ifndef _CS1237_LEFTLOW_H_
#define _CS1237_LEFTLOW_H_
#define READ_CONFIG_CMD 0x56
#define WRITE_CONFIG_CMD 0x65
#define CONFIG_RST 0x0C
#define REFO_OFF 0x40
#define REFO_ON 0x00
#define SPEED_SEL_10Hz 0x00
#define SPEED_SEL_40Hz 0x10
#define SPEED_SEL_640Hz 0x20
#define SPEED_SEL6_1280Hz 0x30
#define PGA_SEL_1 0x00
#define PGA_SEL_2 0x04
#define PGA_SEL_64 0x08
#define PGA_SEL_128 0x0C
#define CH_SEL_A 0x00
//#define CH_SEL_B 0x01
#define CH_SEL_TEMP 0x02
#define CH_SEL_JUMP 0x03
/*Definition of conversion time corresponding to repeatability setting*/
/*
10Hz //建立时间300ms
40Hz //建立时间75ms
640Hz //建立时间6.25ms
1280Hz //建立时间3.125ms
*/
#define tCon_10Hz 300 /* ms. */
#define tCon_40Hz 75 /* ms. */
#define tCon_640Hz 7 /* ms. */
#define tCon_1280Hz 4 /* ms. */
#define PORT_A 1 //采集通道A
//#define PORT_B 1 //采集通道B
#define PORT_TEMP 0 //采集温度
#define PORT_JUMP 0 //内短采集
#define PACK_NUM 1 //一次采集的数据包数量
#define FILTER_NUM 0 //滤波数
typedef enum{
LLCS1237_STATUS_IDLE,
LLCS1237_STATUS_START,
LLCS1237_STATUS_DELAY,
LLCS1237_STATUS_READ,
LLCS1237_STATUS_WAIT_READ,
LLCS1237_STATUS_CH_SEL,
LLCS1237_STATUS_STOP,
}LeftLowCS1237Status_m;
typedef struct{
LeftLowCS1237Status_m Status;
uint32_t CS1237Delay1mSCnt;
int32_t AinA_AD;//AINAad数据
//int32_t AinB_AD;//AINBad数据
int32_t Temp_AD;//温度ad数据
int32_t Jump_AD;//内短ad数据
}
LEFTLOW_CS1237Var_t;
void LEFTLOW_CS1237_Init(void);
void LEFTLOW_CS1237_IrqCallBack(void);
void LEFTLOW_CS1237DataLoopCollect(void);
void LEFTLOW_CS12371mSRoutine(void);
void LEFTLOW_CS1237Start(void);
void LEFTLOW_CS1237Stop(void);
#endif
Project/source/Module/CS1237/CS1237_LEFTUP.c
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#include "CS1237_LEFTUP.h"
#include "Debug.h"
#include "bsp.h"
#include "main.h"
#include "Algorithm.h"
#define CS1237_DOUT_OUT() PORT_OE(LEFTUP_CS1237_DOUT_PORTx, LEFTUP_CS1237_DOUT_PINx, Enable)
#define CS1237_DOUT_IN() PORT_OE(LEFTUP_CS1237_DOUT_PORTx, LEFTUP_CS1237_DOUT_PINx, Disable)
#define CS1237_DOUT_H() SET_LEFTUP_CS1237_DOUT()
#define CS1237_DOUT_L() CLR_LEFTUP_CS1237_DOUT()
#define CS1237_DOUT_GET() GET_LEFTUP_CS1237_DOUT()
#define CS1237_SCLK_H() SET_LEFTUP_CS1237_SCLK()
#define CS1237_SCLK_L() CLR_LEFTUP_CS1237_SCLK()
#define CS1237_5NS(x) delay_5ns(x) //5ns延时
#define CS1237_1US(x) Ddl_Delay1us(x) //1us延时
#define CS1237_1MS(x) Ddl_Delay1ms(x) //1ms延时
#define CS1237IntEnable() ExtInt10IntEnable()
#define CS1237IntDisable() ExtInt10IntDisable()
LEFTUP_CS1237Var_t LEFTUP_CS1237Var;
static bool InitFlag;
static bool CS1237IrqFlag;
static bool BuildDelay;
static uint8_t CS1237Port;
static uint8_t CS1237Hz;
static uint8_t CS1237PGA;
extern void LEFTUP_CS1237AinADataProcessCallBack(int32_t AD);
/** cs1237 时序时钟*/
static void CS1237_Clock(void)
{
CS1237_SCLK_H();
CS1237_5NS(60);
CS1237_SCLK_L();
CS1237_5NS(60);
}
/** cs1237 休眠*/
static void CS1237_Sleep(void)
{
CS1237_SCLK_H();
CS1237_1US(200);
}
/** cs1237 唤醒*/
static void CS1237_WakeUp(void)
{
CS1237_SCLK_L();
CS1237_1US(20);
}
/**设置CS1237寄存器*/
static void Set_CS1237_Config(uint8_t ad_reg)
{
uint16_t bit_cout = 0;
uint8_t reg_temp = 0x00;
//DOUT由高变低之后开始读取数据
CS1237_DOUT_OUT();
CS1237_DOUT_H();
CS1237_DOUT_IN();
CS1237_SCLK_L(); //时钟拉低
LEFTUP_CS1237Var.CS1237Delay1mSCnt = 300;
CS1237IrqFlag = false;
while(CS1237IrqFlag == false) //等待芯片准备好
{
if(LEFTUP_CS1237Var.CS1237Delay1mSCnt <= 0){
//DBG_LOG("LEFTUP CS1237 Preparation Timeout...\r\n");
return; // 超时退出
}
}
CS1237IntDisable();
CS1237IrqFlag = false;
/* clk1-clk26 写期间不需要操作*/
for (bit_cout = 0; bit_cout < 26; bit_cout++)
{
CS1237_Clock(); //给一周期时钟
}
/* clk27 DOUT输出拉高*/
CS1237_Clock(); //给一周期时钟
CS1237_DOUT_H();
/* clk28 - clk29 发送写寄存器命令字 */
CS1237_Clock(); //给一周期时钟
CS1237_Clock(); //给一周期时钟
/* clk30 - clk36 发送写寄存器命令字 */
CS1237_DOUT_OUT();
reg_temp = WRITE_CONFIG_CMD << 1; //命令长度为 7bits (写0x65)左移1位
for (bit_cout = 0; bit_cout < 7; bit_cout++)
{
if (reg_temp & 0x80) //MSB
{
CS1237_DOUT_H();
}
else
{
CS1237_DOUT_L();
}
reg_temp = reg_temp << 1;
CS1237_Clock();
}
/* clk37写寄存器模式还是输出 */
CS1237_Clock();
/* clk38 ~ clk45 写入寄存器值 */
reg_temp = ad_reg;//要配件的寄存器数值
for (bit_cout = 0; bit_cout < 8; bit_cout++)
{
if (reg_temp & 0x80) //MSB
{
CS1237_DOUT_H();
}
else
{
CS1237_DOUT_L();
}
reg_temp = reg_temp << 1;
CS1237_Clock();
}
/* 8: clk46 */
CS1237_Clock();
CS1237_DOUT_H();
CS1237_DOUT_IN();
CS1237IntEnable();
return ;
}
/**读CS1237寄存器*/
static int32_t Read_CS1237_Config(void)
{
uint16_t bit_cout = 0;
uint8_t reg_temp = 0x00;
//DOUT由高变低之后开始读取数据
CS1237_DOUT_OUT();
CS1237_DOUT_H();
CS1237_DOUT_IN();
CS1237_SCLK_L(); //时钟拉低
LEFTUP_CS1237Var.CS1237Delay1mSCnt = 300;
CS1237IrqFlag = false;
while(CS1237IrqFlag == false) //等待芯片准备好
{
if(LEFTUP_CS1237Var.CS1237Delay1mSCnt <= 0){
//DBG_LOG("LEFTUP CS1237 Preparation Timeout...\r\n");
return 0; // 超时退出
}
}
CS1237IntDisable();
CS1237IrqFlag = false;
/* clk1-clk26 写期间不需要操作*/
for (bit_cout = 0; bit_cout < 26; bit_cout++)
{
CS1237_Clock(); //给一周期时钟
}
/* clk27 DOUT输出拉高*/
CS1237_Clock(); //给一周期时钟
CS1237_DOUT_H();
/* clk28 - clk29 发送写寄存器命令字 */
CS1237_Clock(); //给一周期时钟
CS1237_Clock(); //给一周期时钟
/* clk30 - clk36 发送读寄存器命令字 */
CS1237_DOUT_OUT();
reg_temp = READ_CONFIG_CMD << 1; //命令长度为 7bits (写0x56)左移1位
for (bit_cout = 0; bit_cout < 7; bit_cout++)
{
if (reg_temp & 0x80) //MSB
{
CS1237_DOUT_H();
}
else
{
CS1237_DOUT_L();
}
reg_temp = reg_temp << 1;
CS1237_Clock();
}
/* clk37，读寄存器模式改输入 */
CS1237_Clock();
CS1237_DOUT_IN();
for (bit_cout = 0; bit_cout < 8; bit_cout++)
{
CS1237_SCLK_H();
reg_temp <<= 1; //左移1位准备接受数据 初始默认0
CS1237_5NS(60);//延时300ns
if(CS1237_DOUT_GET() == true) //有数值则累加
reg_temp |= 1;
CS1237_SCLK_L();
CS1237_5NS(60);
}
/* 8: clk46 */
CS1237_Clock();
CS1237_DOUT_IN();
CS1237_DOUT_H();
CS1237IntEnable();
return reg_temp ;
}
/**读取CS1237的AD数*/
static int32_t Read_CS1237_Ad_Data(void)
{
uint16_t bit_cout = 0;
int32_t data_temp = 0;
/* clk1 ~ clk24 ADC数据*/
data_temp = 0;
for (bit_cout = 0; bit_cout < 24; bit_cout++)
{
CS1237_SCLK_H();
data_temp <<= 1; //左移1位准备接受数据 初始默认0
CS1237_5NS(60);//延时300ns
if(CS1237_DOUT_GET() == true) //有数值则累加
data_temp |= 1;
CS1237_SCLK_L();
CS1237_5NS(60);
}
/* clk25 ~ clk27 */
for (bit_cout = 24; bit_cout < 27; bit_cout++)
{
CS1237_Clock(); //给一周期时钟
}
CS1237_DOUT_H();
CS1237_SCLK_L();
if(data_temp > 0x7FFFFF) //取24位
{
data_temp |= 0xFF000000;
}
return data_temp;
}
void LEFTUP_CS1237_IrqCallBack(void)
{
CS1237IrqFlag = true;
}
void LEFTUP_CS1237_Init(void)
{
CS1237IrqFlag = false;
BuildDelay = false;
LEFTUP_CS1237Var.AinA_AD = 0;
LEFTUP_CS1237Var.Temp_AD = 0;
LEFTUP_CS1237Var.Jump_AD = 0;
CS1237IntEnable();
CS1237Port = CH_SEL_A;
CS1237Hz = SPEED_SEL_640Hz;
CS1237PGA = PGA_SEL_128;
uint8_t read_reg = 0x00;
uint8_t set_reg = REFO_ON | CS1237Hz | CS1237PGA | CS1237Port;
CS1237_1MS(20);
Set_CS1237_Config(set_reg);
CS1237_1MS(20);
read_reg = Read_CS1237_Config();
CS1237_1MS(20);
if(read_reg != set_reg){
DBG_LOG("LEFTUP CS1237 Init ERR...\r\n");
//DBG_LOG("set_reg = %02X\tread_reg = %02X\r\n",set_reg,read_reg);
InitFlag = true;
}
else {
DBG_LOG("LEFTUP CS1237 Init OK...\r\n");
//DBG_LOG("set_reg = %02X\tread_reg = %02X\r\n",set_reg,read_reg);
CS1237Port = read_reg & 0x03;
InitFlag = true;
}
CS1237IntDisable();
}
void LEFTUP_CS1237DataLoopCollect(void)
{
static int32_t ad_array[PACK_NUM];
static uint8_t adcnt;
static uint8_t TimeOutmagcnt;
switch(LEFTUP_CS1237Var.Status) {
case LUCS1237_STATUS_IDLE:{
break;}
case LUCS1237_STATUS_START:{
memset(&ad_array, 0x00, sizeof(ad_array));
adcnt = 0;
TimeOutmagcnt = 0;
memset(&LEFTUP_CS1237Var, NULL, sizeof(LEFTUP_CS1237Var));
if(BuildDelay == true)
{
BuildDelay = false;
if(CS1237Hz == SPEED_SEL_10Hz){
LEFTUP_CS1237Var.CS1237Delay1mSCnt = tCon_10Hz;
}
if(CS1237Hz == SPEED_SEL_40Hz){
LEFTUP_CS1237Var.CS1237Delay1mSCnt = tCon_40Hz;
}
if(CS1237Hz == SPEED_SEL_640Hz){
LEFTUP_CS1237Var.CS1237Delay1mSCnt = tCon_640Hz;
}
if(CS1237Hz == SPEED_SEL6_1280Hz){
LEFTUP_CS1237Var.CS1237Delay1mSCnt = tCon_1280Hz;
}
LEFTUP_CS1237Var.Status = LUCS1237_STATUS_DELAY;
}
else
{
LEFTUP_CS1237Var.Status = LUCS1237_STATUS_READ;
}
break;}
case LUCS1237_STATUS_DELAY:{
if(LEFTUP_CS1237Var.CS1237Delay1mSCnt <= 0){
LEFTUP_CS1237Var.Status = LUCS1237_STATUS_READ;
}
break;}
case LUCS1237_STATUS_READ:{
CS1237IrqFlag = false;
LEFTUP_CS1237Var.CS1237Delay1mSCnt = 100;
LEFTUP_CS1237Var.Status = LUCS1237_STATUS_WAIT_READ;
break;}
case LUCS1237_STATUS_WAIT_READ:{
if(LEFTUP_CS1237Var.CS1237Delay1mSCnt <= 0){
LEFTUP_CS1237Var.Status = LUCS1237_STATUS_READ;
TimeOutmagcnt++;
}
if(CS1237IrqFlag == true){
CS1237IrqFlag = false;
ad_array[adcnt++] = Read_CS1237_Ad_Data();
LEFTUP_CS1237Var.Status = LUCS1237_STATUS_READ;
}
if(TimeOutmagcnt >= PACK_NUM){
TimeOutmagcnt = 0;
if(adcnt > 0){
if(CS1237Port == CH_SEL_A){
LEFTUP_CS1237Var.AinA_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
LEFTUP_CS1237AinADataProcessCallBack(LEFTUP_CS1237Var.AinA_AD);
}
if(CS1237Port == CH_SEL_TEMP){
LEFTUP_CS1237Var.Temp_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
//CS1237TempDataProcessCallBack(LEFTLOW_CS1237Var.Temp_AD);
}
if(CS1237Port == CH_SEL_JUMP){
LEFTUP_CS1237Var.Jump_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
//CS1237JumpDataProcessCallBack(LEFTLOW_CS1237Var.Jump_AD);
}
LEFTUP_CS1237Var.Status = LUCS1237_STATUS_CH_SEL;
}
else{
if(CS1237Port == CH_SEL_A){
DBG_LOG("LEFTUPs CS1237 CHA TimeOut...\r\n");
}
if(CS1237Port == CH_SEL_TEMP){
DBG_LOG("LEFTUP CS1237 Temp TimeOut...\r\n");
}
if(CS1237Port == CH_SEL_JUMP){
DBG_LOG("LEFTUP CS1237 Jump TimeOut...\r\n");
}
LEFTUP_CS1237Var.Status = LUCS1237_STATUS_CH_SEL;
}
}
if(adcnt >= PACK_NUM){
if(CS1237Port == CH_SEL_A){
LEFTUP_CS1237Var.AinA_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
LEFTUP_CS1237AinADataProcessCallBack(LEFTUP_CS1237Var.AinA_AD);
}
if(CS1237Port == CH_SEL_TEMP){
LEFTUP_CS1237Var.Temp_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
//CS1237TempDataProcessCallBack(LEFTLOW_CS1237Var.Temp_AD);
}
if(CS1237Port == CH_SEL_JUMP){
LEFTUP_CS1237Var.Jump_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
//CS1237JumpDataProcessCallBack(LEFTLOW_CS1237Var.Jump_AD);
}
LEFTUP_CS1237Var.Status = LUCS1237_STATUS_CH_SEL;
}
break;}
case LUCS1237_STATUS_CH_SEL:{
LEFTUP_CS1237Var.Status = LUCS1237_STATUS_STOP;
BuildDelay = false;
uint8_t read_reg;
if(CS1237Port == CH_SEL_A){
#if(PORT_TEMP == 1)
read_reg = Read_CS1237_Config();
Set_CS1237_Config((read_reg & 0xFC) | CH_SEL_TEMP);
CS1237Port = CH_SEL_TEMP;
BuildDelay = true;
break;
#endif
#if(PORT_JUMP == 1)
read_reg = Read_CS1237_Config();
Set_CS1237_Config((read_reg & 0xFC) | CH_SEL_JUMP);
CS1237Port = CH_SEL_JUMP;
BuildDelay = true;
break;
#endif
}
if(CS1237Port == CH_SEL_TEMP){
#if(PORT_JUMP == 1)
read_reg = Read_CS1238_Config();
Set_CS1238_Config((read_reg & 0xFC) | CH_SEL_JUMP);
CS1238Port = CH_SEL_JUMP;
BuildDelay = true;
break;
#endif
#if(PORT_A == 1)
read_reg = Read_CS1237_Config();
Set_CS1237_Config((read_reg & 0xFC) | CH_SEL_A);
CS1237Port = CH_SEL_A;
BuildDelay = true;
break;
#endif
}
if(CS1237Port == CH_SEL_JUMP){
#if(PORT_A == 1)
read_reg = Read_CS1237_Config();
Set_CS1237_Config((read_reg & 0xFC) | CH_SEL_A);
CS1237Port = CH_SEL_A;
BuildDelay = true;
break;
#endif
#if(PORT_TEMP == 1)
read_reg = Read_CS1237_Config();
Set_CS1237_Config((read_reg & 0xFC) | CH_SEL_TEMP);
CS1237Port = CH_SEL_TEMP;
BuildDelay = true;
break;
#endif
}
break;}
case LUCS1237_STATUS_STOP:{
LEFTUP_CS1237Stop();
LEFTUP_CS1237Var.Status = LUCS1237_STATUS_IDLE;
//LEFTUP_CS1237Var.Status = LUCS1237_STATUS_START;//持续工作
break;}
}
}
void LEFTUP_CS12371mSRoutine(void)
{
if(LEFTUP_CS1237Var.CS1237Delay1mSCnt > 0)
LEFTUP_CS1237Var.CS1237Delay1mSCnt--;
}
void LEFTUP_CS1237Start(void)
{
CS1237_WakeUp();
CS1237_1MS(2);
BuildDelay = true;
CS1237IntEnable();
if(!InitFlag){
LEFTUP_CS1237_Init();
return;
}
LEFTUP_CS1237Var.Status = LUCS1237_STATUS_START;
}
void LEFTUP_CS1237Stop(void)
{
CS1237IntDisable();
//CS1237_Sleep();
}
Project/source/Module/CS1237/CS1237_LEFTUP.h
+80
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#include "bsp.h"
#ifndef _CS1237_LEFTUP_H_
#define _CS1237_LEFTUP_H_
#define READ_CONFIG_CMD 0x56
#define WRITE_CONFIG_CMD 0x65
#define CONFIG_RST 0x0C
#define REFO_OFF 0x40
#define REFO_ON 0x00
#define SPEED_SEL_10Hz 0x00
#define SPEED_SEL_40Hz 0x10
#define SPEED_SEL_640Hz 0x20
#define SPEED_SEL6_1280Hz 0x30
#define PGA_SEL_1 0x00
#define PGA_SEL_2 0x04
#define PGA_SEL_64 0x08
#define PGA_SEL_128 0x0C
#define CH_SEL_A 0x00
//#define CH_SEL_B 0x01
#define CH_SEL_TEMP 0x02
#define CH_SEL_JUMP 0x03
/*Definition of conversion time corresponding to repeatability setting*/
/*
10Hz //建立时间300ms
40Hz //建立时间75ms
640Hz //建立时间6.25ms
1280Hz //建立时间3.125ms
*/
#define tCon_10Hz 300 /* ms. */
#define tCon_40Hz 75 /* ms. */
#define tCon_640Hz 7 /* ms. */
#define tCon_1280Hz 4 /* ms. */
#define PORT_A 1 //采集通道A
//#define PORT_B 1 //采集通道B
#define PORT_TEMP 0 //采集温度
#define PORT_JUMP 0 //内短采集
#define PACK_NUM 1 //一次采集的数据包数量
#define FILTER_NUM 0 //滤波数
typedef enum{
LUCS1237_STATUS_IDLE,
LUCS1237_STATUS_START,
LUCS1237_STATUS_DELAY,
LUCS1237_STATUS_READ,
LUCS1237_STATUS_WAIT_READ,
LUCS1237_STATUS_CH_SEL,
LUCS1237_STATUS_STOP,
}LeftUpCS1237Status_m;
typedef struct{
LeftUpCS1237Status_m Status;
uint32_t CS1237Delay1mSCnt;
int32_t AinA_AD;//AINAad数据
//int32_t AinB_AD;//AINBad数据
int32_t Temp_AD;//温度ad数据
int32_t Jump_AD;//内短ad数据
}
LEFTUP_CS1237Var_t;
void LEFTUP_CS1237_Init(void);
void LEFTUP_CS1237_IrqCallBack(void);
void LEFTUP_CS1237DataLoopCollect(void);
void LEFTUP_CS12371mSRoutine(void);
void LEFTUP_CS1237Start(void);
void LEFTUP_CS1237Stop(void);
#endif
Project/source/Module/CS1237/CS1237_RIGHTLOW.c
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#include "CS1237_RIGHTLOW.h"
#include "Debug.h"
#include "bsp.h"
#include "main.h"
#include "Algorithm.h"
#define CS1237_DOUT_OUT() PORT_OE(RIGHTLOW_CS1237_DOUT_PORTx, RIGHTLOW_CS1237_DOUT_PINx, Enable)
#define CS1237_DOUT_IN() PORT_OE(RIGHTLOW_CS1237_DOUT_PORTx, RIGHTLOW_CS1237_DOUT_PINx, Disable)
#define CS1237_DOUT_H() SET_RIGHTLOW_CS1237_DOUT()
#define CS1237_DOUT_L() CLR_RIGHTLOW_CS1237_DOUT()
#define CS1237_DOUT_GET() GET_RIGHTLOW_CS1237_DOUT()
#define CS1237_SCLK_H() SET_RIGHTLOW_CS1237_SCLK()
#define CS1237_SCLK_L() CLR_RIGHTLOW_CS1237_SCLK()
#define CS1237_5NS(x) delay_5ns(x) //5ns延时
#define CS1237_1US(x) Ddl_Delay1us(x) //1us延时
#define CS1237_1MS(x) Ddl_Delay1ms(x) //1ms延时
#define CS1237IntEnable() ExtInt06IntEnable()
#define CS1237IntDisable() ExtInt06IntDisable()
RIGHTLOW_CS1237Var_t RIGHTLOW_CS1237Var;
static bool InitFlag;
static bool CS1237IrqFlag;
static bool BuildDelay;
static uint8_t CS1237Port;
static uint8_t CS1237Hz;
static uint8_t CS1237PGA;
extern void RIGHTLOW_CS1237AinADataProcessCallBack(int32_t AD);
/** cs1237 时序时钟*/
static void CS1237_Clock(void)
{
CS1237_SCLK_H();
CS1237_5NS(60);
CS1237_SCLK_L();
CS1237_5NS(60);
}
/** cs1237 休眠*/
static void CS1237_Sleep(void)
{
CS1237_SCLK_H();
CS1237_1US(200);
}
/** cs1237 唤醒*/
static void CS1237_WakeUp(void)
{
CS1237_SCLK_L();
CS1237_1US(20);
}
/**设置CS1237寄存器*/
static void Set_CS1237_Config(uint8_t ad_reg)
{
uint16_t bit_cout = 0;
uint8_t reg_temp = 0x00;
//DOUT由高变低之后开始读取数据
CS1237_DOUT_OUT();
CS1237_DOUT_H();
CS1237_DOUT_IN();
CS1237_SCLK_L(); //时钟拉低
RIGHTLOW_CS1237Var.CS1237Delay1mSCnt = 300;
CS1237IrqFlag = false;
while(CS1237IrqFlag == false) //等待芯片准备好
{
if(RIGHTLOW_CS1237Var.CS1237Delay1mSCnt <= 0){
//DBG_LOG("RIGHTLOW CS1237 Preparation Timeout...\r\n");
return; // 超时退出
}
}
CS1237IntDisable();
CS1237IrqFlag = false;
/* clk1-clk26 写期间不需要操作*/
for (bit_cout = 0; bit_cout < 26; bit_cout++)
{
CS1237_Clock(); //给一周期时钟
}
/* clk27 DOUT输出拉高*/
CS1237_Clock(); //给一周期时钟
CS1237_DOUT_H();
/* clk28 - clk29 发送写寄存器命令字 */
CS1237_Clock(); //给一周期时钟
CS1237_Clock(); //给一周期时钟
/* clk30 - clk36 发送写寄存器命令字 */
CS1237_DOUT_OUT();
reg_temp = WRITE_CONFIG_CMD << 1; //命令长度为 7bits (写0x65)左移1位
for (bit_cout = 0; bit_cout < 7; bit_cout++)
{
if (reg_temp & 0x80) //MSB
{
CS1237_DOUT_H();
}
else
{
CS1237_DOUT_L();
}
reg_temp = reg_temp << 1;
CS1237_Clock();
}
/* clk37写寄存器模式还是输出 */
CS1237_Clock();
/* clk38 ~ clk45 写入寄存器值 */
reg_temp = ad_reg;//要配件的寄存器数值
for (bit_cout = 0; bit_cout < 8; bit_cout++)
{
if (reg_temp & 0x80) //MSB
{
CS1237_DOUT_H();
}
else
{
CS1237_DOUT_L();
}
reg_temp = reg_temp << 1;
CS1237_Clock();
}
/* 8: clk46 */
CS1237_Clock();
CS1237_DOUT_H();
CS1237_DOUT_IN();
CS1237IntEnable();
return ;
}
/**读CS1237寄存器*/
static int32_t Read_CS1237_Config(void)
{
uint16_t bit_cout = 0;
uint8_t reg_temp = 0x00;
//DOUT由高变低之后开始读取数据
CS1237_DOUT_OUT();
CS1237_DOUT_H();
CS1237_DOUT_IN();
CS1237_SCLK_L(); //时钟拉低
RIGHTLOW_CS1237Var.CS1237Delay1mSCnt = 300;
CS1237IrqFlag = false;
while(CS1237IrqFlag == false) //等待芯片准备好
{
if(RIGHTLOW_CS1237Var.CS1237Delay1mSCnt <= 0){
//DBG_LOG("RIGHTLOW CS1237 Preparation Timeout...\r\n");
return 0; // 超时退出
}
}
CS1237IntDisable();
CS1237IrqFlag = false;
/* clk1-clk26 写期间不需要操作*/
for (bit_cout = 0; bit_cout < 26; bit_cout++)
{
CS1237_Clock(); //给一周期时钟
}
/* clk27 DOUT输出拉高*/
CS1237_Clock(); //给一周期时钟
CS1237_DOUT_H();
/* clk28 - clk29 发送写寄存器命令字 */
CS1237_Clock(); //给一周期时钟
CS1237_Clock(); //给一周期时钟
/* clk30 - clk36 发送读寄存器命令字 */
CS1237_DOUT_OUT();
reg_temp = READ_CONFIG_CMD << 1; //命令长度为 7bits (写0x56)左移1位
for (bit_cout = 0; bit_cout < 7; bit_cout++)
{
if (reg_temp & 0x80) //MSB
{
CS1237_DOUT_H();
}
else
{
CS1237_DOUT_L();
}
reg_temp = reg_temp << 1;
CS1237_Clock();
}
/* clk37，读寄存器模式改输入 */
CS1237_Clock();
CS1237_DOUT_IN();
for (bit_cout = 0; bit_cout < 8; bit_cout++)
{
CS1237_SCLK_H();
reg_temp <<= 1; //左移1位准备接受数据 初始默认0
CS1237_5NS(60);//延时300ns
if(CS1237_DOUT_GET() == true) //有数值则累加
reg_temp |= 1;
CS1237_SCLK_L();
CS1237_5NS(60);
}
/* 8: clk46 */
CS1237_Clock();
CS1237_DOUT_IN();
CS1237_DOUT_H();
CS1237IntEnable();
return reg_temp ;
}
/**读取CS1237的AD数*/
static int32_t Read_CS1237_Ad_Data(void)
{
uint16_t bit_cout = 0;
int32_t data_temp = 0;
/* clk1 ~ clk24 ADC数据*/
data_temp = 0;
for (bit_cout = 0; bit_cout < 24; bit_cout++)
{
CS1237_SCLK_H();
data_temp <<= 1; //左移1位准备接受数据 初始默认0
CS1237_5NS(60);//延时300ns
if(CS1237_DOUT_GET() == true) //有数值则累加
data_temp |= 1;
CS1237_SCLK_L();
CS1237_5NS(60);
}
/* clk25 ~ clk27 */
for (bit_cout = 24; bit_cout < 27; bit_cout++)
{
CS1237_Clock(); //给一周期时钟
}
CS1237_DOUT_H();
CS1237_SCLK_L();
if(data_temp > 0x7FFFFF) //取24位
{
data_temp |= 0xFF000000;
}
return data_temp;
}
void RIGHTLOW_CS1237_IrqCallBack(void)
{
CS1237IrqFlag = true;
}
void RIGHTLOW_CS1237_Init(void)
{
CS1237IrqFlag = false;
BuildDelay = false;
RIGHTLOW_CS1237Var.AinA_AD = 0;
RIGHTLOW_CS1237Var.Temp_AD = 0;
RIGHTLOW_CS1237Var.Jump_AD = 0;
CS1237IntEnable();
CS1237Port = CH_SEL_A;
CS1237Hz = SPEED_SEL_640Hz;
CS1237PGA = PGA_SEL_128;
uint8_t read_reg = 0x00;
uint8_t set_reg = REFO_ON | CS1237Hz | CS1237PGA | CS1237Port;
CS1237_1MS(20);
Set_CS1237_Config(set_reg);
CS1237_1MS(20);
read_reg = Read_CS1237_Config();
CS1237_1MS(20);
if(read_reg != set_reg){
DBG_LOG("RIGHTLOW CS1237 Init ERR...\r\n");
//DBG_LOG("set_reg = %02X\tread_reg = %02X\r\n",set_reg,read_reg);
InitFlag = true;
}
else {
DBG_LOG("RIGHTLOW CS1237 Init OK...\r\n");
//DBG_LOG("set_reg = %02X\tread_reg = %02X\r\n",set_reg,read_reg);
CS1237Port = read_reg & 0x03;
InitFlag = true;
}
CS1237IntDisable();
}
void RIGHTLOW_CS1237DataLoopCollect(void)
{
static int32_t ad_array[PACK_NUM];
static uint8_t adcnt;
static uint8_t TimeOutmagcnt;
switch(RIGHTLOW_CS1237Var.Status) {
case RLCS1237_STATUS_IDLE:{
break;}
case RLCS1237_STATUS_START:{
memset(&ad_array, 0x00, sizeof(ad_array));
adcnt = 0;
TimeOutmagcnt = 0;
memset(&RIGHTLOW_CS1237Var, NULL, sizeof(RIGHTLOW_CS1237Var));
if(BuildDelay == true)
{
BuildDelay = false;
if(CS1237Hz == SPEED_SEL_10Hz){
RIGHTLOW_CS1237Var.CS1237Delay1mSCnt = tCon_10Hz;
}
if(CS1237Hz == SPEED_SEL_40Hz){
RIGHTLOW_CS1237Var.CS1237Delay1mSCnt = tCon_40Hz;
}
if(CS1237Hz == SPEED_SEL_640Hz){
RIGHTLOW_CS1237Var.CS1237Delay1mSCnt = tCon_640Hz;
}
if(CS1237Hz == SPEED_SEL6_1280Hz){
RIGHTLOW_CS1237Var.CS1237Delay1mSCnt = tCon_1280Hz;
}
RIGHTLOW_CS1237Var.Status = RLCS1237_STATUS_DELAY;
}
else
{
RIGHTLOW_CS1237Var.Status = RLCS1237_STATUS_READ;
}
break;}
case RLCS1237_STATUS_DELAY:{
if(RIGHTLOW_CS1237Var.CS1237Delay1mSCnt <= 0){
RIGHTLOW_CS1237Var.Status = RLCS1237_STATUS_READ;
}
break;}
case RLCS1237_STATUS_READ:{
CS1237IrqFlag = false;
RIGHTLOW_CS1237Var.CS1237Delay1mSCnt = 100;
RIGHTLOW_CS1237Var.Status = RLCS1237_STATUS_WAIT_READ;
break;}
case RLCS1237_STATUS_WAIT_READ:{
if(RIGHTLOW_CS1237Var.CS1237Delay1mSCnt <= 0){
RIGHTLOW_CS1237Var.Status = RLCS1237_STATUS_READ;
TimeOutmagcnt++;
}
if(CS1237IrqFlag == true){
CS1237IrqFlag = false;
ad_array[adcnt++] = Read_CS1237_Ad_Data();
RIGHTLOW_CS1237Var.Status = RLCS1237_STATUS_READ;
}
if(TimeOutmagcnt >= PACK_NUM){
TimeOutmagcnt = 0;
if(adcnt > 0){
if(CS1237Port == CH_SEL_A){
RIGHTLOW_CS1237Var.AinA_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
RIGHTLOW_CS1237AinADataProcessCallBack(RIGHTLOW_CS1237Var.AinA_AD);
}
if(CS1237Port == CH_SEL_TEMP){
RIGHTLOW_CS1237Var.Temp_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
//CS1237TempDataProcessCallBack(LEFTLOW_CS1237Var.Temp_AD);
}
if(CS1237Port == CH_SEL_JUMP){
RIGHTLOW_CS1237Var.Jump_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
//CS1237JumpDataProcessCallBack(LEFTLOW_CS1237Var.Jump_AD);
}
RIGHTLOW_CS1237Var.Status = RLCS1237_STATUS_CH_SEL;
}
else{
if(CS1237Port == CH_SEL_A){
DBG_LOG("RIGHTLOW CS1237 CHA TimeOut...\r\n");
}
if(CS1237Port == CH_SEL_TEMP){
DBG_LOG("RIGHTLOW CS1237 Temp TimeOut...\r\n");
}
if(CS1237Port == CH_SEL_JUMP){
DBG_LOG("RIGHTLOW CS1237 Jump TimeOut...\r\n");
}
RIGHTLOW_CS1237Var.Status = RLCS1237_STATUS_CH_SEL;
}
}
if(adcnt >= PACK_NUM){
if(CS1237Port == CH_SEL_A){
RIGHTLOW_CS1237Var.AinA_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
RIGHTLOW_CS1237AinADataProcessCallBack(RIGHTLOW_CS1237Var.AinA_AD);
}
if(CS1237Port == CH_SEL_TEMP){
RIGHTLOW_CS1237Var.Temp_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
//CS1237TempDataProcessCallBack(LEFTLOW_CS1237Var.Temp_AD);
}
if(CS1237Port == CH_SEL_JUMP){
RIGHTLOW_CS1237Var.Jump_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
//CS1237JumpDataProcessCallBack(LEFTLOW_CS1237Var.Jump_AD);
}
RIGHTLOW_CS1237Var.Status = RLCS1237_STATUS_CH_SEL;
}
break;}
case RLCS1237_STATUS_CH_SEL:{
RIGHTLOW_CS1237Var.Status = RLCS1237_STATUS_STOP;
BuildDelay = false;
uint8_t read_reg;
if(CS1237Port == CH_SEL_A){
#if(PORT_TEMP == 1)
read_reg = Read_CS1237_Config();
Set_CS1237_Config((read_reg & 0xFC) | CH_SEL_TEMP);
CS1237Port = CH_SEL_TEMP;
BuildDelay = true;
break;
#endif
#if(PORT_JUMP == 1)
read_reg = Read_CS1237_Config();
Set_CS1237_Config((read_reg & 0xFC) | CH_SEL_JUMP);
CS1237Port = CH_SEL_JUMP;
BuildDelay = true;
break;
#endif
}
if(CS1237Port == CH_SEL_TEMP){
#if(PORT_JUMP == 1)
read_reg = Read_CS1238_Config();
Set_CS1238_Config((read_reg & 0xFC) | CH_SEL_JUMP);
CS1238Port = CH_SEL_JUMP;
BuildDelay = true;
break;
#endif
#if(PORT_A == 1)
read_reg = Read_CS1237_Config();
Set_CS1237_Config((read_reg & 0xFC) | CH_SEL_A);
CS1237Port = CH_SEL_A;
BuildDelay = true;
break;
#endif
}
if(CS1237Port == CH_SEL_JUMP){
#if(PORT_A == 1)
read_reg = Read_CS1237_Config();
Set_CS1237_Config((read_reg & 0xFC) | CH_SEL_A);
CS1237Port = CH_SEL_A;
BuildDelay = true;
break;
#endif
#if(PORT_TEMP == 1)
read_reg = Read_CS1237_Config();
Set_CS1237_Config((read_reg & 0xFC) | CH_SEL_TEMP);
CS1237Port = CH_SEL_TEMP;
BuildDelay = true;
break;
#endif
}
break;}
case RLCS1237_STATUS_STOP:{
RIGHTLOW_CS1237Stop();
RIGHTLOW_CS1237Var.Status = RLCS1237_STATUS_IDLE;
//RIGHTLOW_CS1237Var.Status = RLCS1237_STATUS_START;//持续工作
break;}
}
}
void RIGHTLOW_CS12371mSRoutine(void)
{
if(RIGHTLOW_CS1237Var.CS1237Delay1mSCnt > 0)
RIGHTLOW_CS1237Var.CS1237Delay1mSCnt--;
}
void RIGHTLOW_CS1237Start(void)
{
CS1237_WakeUp();
CS1237_1MS(2);
BuildDelay = true;
CS1237IntEnable();
if(!InitFlag){
RIGHTLOW_CS1237_Init();
return;
}
RIGHTLOW_CS1237Var.Status = RLCS1237_STATUS_START;
}
void RIGHTLOW_CS1237Stop(void)
{
CS1237IntDisable();
//CS1237_Sleep();
}
Project/source/Module/CS1237/CS1237_RIGHTLOW.h
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#include "bsp.h"
#ifndef _CS1237_RIGHTLOW_H_
#define _CS1237_RIGHTLOW_H_
#define READ_CONFIG_CMD 0x56
#define WRITE_CONFIG_CMD 0x65
#define CONFIG_RST 0x0C
#define REFO_OFF 0x40
#define REFO_ON 0x00
#define SPEED_SEL_10Hz 0x00
#define SPEED_SEL_40Hz 0x10
#define SPEED_SEL_640Hz 0x20
#define SPEED_SEL6_1280Hz 0x30
#define PGA_SEL_1 0x00
#define PGA_SEL_2 0x04
#define PGA_SEL_64 0x08
#define PGA_SEL_128 0x0C
#define CH_SEL_A 0x00
//#define CH_SEL_B 0x01
#define CH_SEL_TEMP 0x02
#define CH_SEL_JUMP 0x03
/*Definition of conversion time corresponding to repeatability setting*/
/*
10Hz //建立时间300ms
40Hz //建立时间75ms
640Hz //建立时间6.25ms
1280Hz //建立时间3.125ms
*/
#define tCon_10Hz 300 /* ms. */
#define tCon_40Hz 75 /* ms. */
#define tCon_640Hz 7 /* ms. */
#define tCon_1280Hz 4 /* ms. */
#define PORT_A 1 //采集通道A
//#define PORT_B 1 //采集通道B
#define PORT_TEMP 0 //采集温度
#define PORT_JUMP 0 //内短采集
#define PACK_NUM 1 //一次采集的数据包数量
#define FILTER_NUM 0 //滤波数
typedef enum{
RLCS1237_STATUS_IDLE,
RLCS1237_STATUS_START,
RLCS1237_STATUS_DELAY,
RLCS1237_STATUS_READ,
RLCS1237_STATUS_WAIT_READ,
RLCS1237_STATUS_CH_SEL,
RLCS1237_STATUS_STOP,
}RightLowCS1237Status_m;
typedef struct{
RightLowCS1237Status_m Status;
uint32_t CS1237Delay1mSCnt;
int32_t AinA_AD;//AINAad数据
//int32_t AinB_AD;//AINBad数据
int32_t Temp_AD;//温度ad数据
int32_t Jump_AD;//内短ad数据
}
RIGHTLOW_CS1237Var_t;
void RIGHTLOW_CS1237_Init(void);
void RIGHTLOW_CS1237_IrqCallBack(void);
void RIGHTLOW_CS1237DataLoopCollect(void);
void RIGHTLOW_CS12371mSRoutine(void);
void RIGHTLOW_CS1237Start(void);
void RIGHTLOW_CS1237Stop(void);
#endif
Project/source/Module/CS1237/CS1237_RIGHTUP.c
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#include "CS1237_RIGHTUP.h"
#include "Debug.h"
#include "bsp.h"
#include "main.h"
#include "Algorithm.h"
#define CS1237_DOUT_OUT() PORT_OE(RIGHTUP_CS1237_DOUT_PORTx, RIGHTUP_CS1237_DOUT_PINx, Enable)
#define CS1237_DOUT_IN() PORT_OE(RIGHTUP_CS1237_DOUT_PORTx, RIGHTUP_CS1237_DOUT_PINx, Disable)
#define CS1237_DOUT_H() SET_RIGHTUP_CS1237_DOUT()
#define CS1237_DOUT_L() CLR_RIGHTUP_CS1237_DOUT()
#define CS1237_DOUT_GET() GET_RIGHTUP_CS1237_DOUT()
#define CS1237_SCLK_H() SET_RIGHTUP_CS1237_SCLK()
#define CS1237_SCLK_L() CLR_RIGHTUP_CS1237_SCLK()
#define CS1237_5NS(x) delay_5ns(x) //5ns延时
#define CS1237_1US(x) Ddl_Delay1us(x) //1us延时
#define CS1237_1MS(x) Ddl_Delay1ms(x) //1ms延时
#define CS1237IntEnable() ExtInt04IntEnable()
#define CS1237IntDisable() ExtInt04IntDisable()
RIGHTUP_CS1237Var_t RIGHTUP_CS1237Var;
static bool InitFlag;
static bool CS1237IrqFlag;
static bool BuildDelay;
static uint8_t CS1237Port;
static uint8_t CS1237Hz;
static uint8_t CS1237PGA;
extern void RIGHTUP_CS1237AinADataProcessCallBack(int32_t AD);
/** cs1237 时序时钟*/
static void CS1237_Clock(void)
{
CS1237_SCLK_H();
CS1237_5NS(60);
CS1237_SCLK_L();
CS1237_5NS(60);
}
/** cs1237 休眠*/
static void CS1237_Sleep(void)
{
CS1237_SCLK_H();
CS1237_1US(200);
}
/** cs1237 唤醒*/
static void CS1237_WakeUp(void)
{
CS1237_SCLK_L();
CS1237_1US(20);
}
/**设置CS1237寄存器*/
static void Set_CS1237_Config(uint8_t ad_reg)
{
uint16_t bit_cout = 0;
uint8_t reg_temp = 0x00;
//DOUT由高变低之后开始读取数据
CS1237_DOUT_OUT();
CS1237_DOUT_H();
CS1237_DOUT_IN();
CS1237_SCLK_L(); //时钟拉低
RIGHTUP_CS1237Var.CS1237Delay1mSCnt = 300;
CS1237IrqFlag = false;
while(CS1237IrqFlag == false) //等待芯片准备好
{
if(RIGHTUP_CS1237Var.CS1237Delay1mSCnt <= 0){
//DBG_LOG("RIGHTUP CS1237 Preparation Timeout...\r\n");
return; // 超时退出
}
}
CS1237IntDisable();
CS1237IrqFlag = false;
/* clk1-clk26 写期间不需要操作*/
for (bit_cout = 0; bit_cout < 26; bit_cout++)
{
CS1237_Clock(); //给一周期时钟
}
/* clk27 DOUT输出拉高*/
CS1237_Clock(); //给一周期时钟
CS1237_DOUT_H();
/* clk28 - clk29 发送写寄存器命令字 */
CS1237_Clock(); //给一周期时钟
CS1237_Clock(); //给一周期时钟
/* clk30 - clk36 发送写寄存器命令字 */
CS1237_DOUT_OUT();
reg_temp = WRITE_CONFIG_CMD << 1; //命令长度为 7bits (写0x65)左移1位
for (bit_cout = 0; bit_cout < 7; bit_cout++)
{
if (reg_temp & 0x80) //MSB
{
CS1237_DOUT_H();
}
else
{
CS1237_DOUT_L();
}
reg_temp = reg_temp << 1;
CS1237_Clock();
}
/* clk37写寄存器模式还是输出 */
CS1237_Clock();
/* clk38 ~ clk45 写入寄存器值 */
reg_temp = ad_reg;//要配件的寄存器数值
for (bit_cout = 0; bit_cout < 8; bit_cout++)
{
if (reg_temp & 0x80) //MSB
{
CS1237_DOUT_H();
}
else
{
CS1237_DOUT_L();
}
reg_temp = reg_temp << 1;
CS1237_Clock();
}
/* 8: clk46 */
CS1237_Clock();
CS1237_DOUT_H();
CS1237_DOUT_IN();
CS1237IntEnable();
return ;
}
/**读CS1237寄存器*/
static int32_t Read_CS1237_Config(void)
{
uint16_t bit_cout = 0;
uint8_t reg_temp = 0x00;
//DOUT由高变低之后开始读取数据
CS1237_DOUT_OUT();
CS1237_DOUT_H();
CS1237_DOUT_IN();
CS1237_SCLK_L(); //时钟拉低
RIGHTUP_CS1237Var.CS1237Delay1mSCnt = 300;
CS1237IrqFlag = false;
while(CS1237IrqFlag == false) //等待芯片准备好
{
if(RIGHTUP_CS1237Var.CS1237Delay1mSCnt <= 0){
//DBG_LOG("RIGHTUP CS1237 Preparation Timeout...\r\n");
return 0; // 超时退出
}
}
CS1237IntDisable();
CS1237IrqFlag = false;
/* clk1-clk26 写期间不需要操作*/
for (bit_cout = 0; bit_cout < 26; bit_cout++)
{
CS1237_Clock(); //给一周期时钟
}
/* clk27 DOUT输出拉高*/
CS1237_Clock(); //给一周期时钟
CS1237_DOUT_H();
/* clk28 - clk29 发送写寄存器命令字 */
CS1237_Clock(); //给一周期时钟
CS1237_Clock(); //给一周期时钟
/* clk30 - clk36 发送读寄存器命令字 */
CS1237_DOUT_OUT();
reg_temp = READ_CONFIG_CMD << 1; //命令长度为 7bits (写0x56)左移1位
for (bit_cout = 0; bit_cout < 7; bit_cout++)
{
if (reg_temp & 0x80) //MSB
{
CS1237_DOUT_H();
}
else
{
CS1237_DOUT_L();
}
reg_temp = reg_temp << 1;
CS1237_Clock();
}
/* clk37，读寄存器模式改输入 */
CS1237_Clock();
CS1237_DOUT_IN();
for (bit_cout = 0; bit_cout < 8; bit_cout++)
{
CS1237_SCLK_H();
reg_temp <<= 1; //左移1位准备接受数据 初始默认0
CS1237_5NS(60);//延时300ns
if(CS1237_DOUT_GET() == true) //有数值则累加
reg_temp |= 1;
CS1237_SCLK_L();
CS1237_5NS(60);
}
/* 8: clk46 */
CS1237_Clock();
CS1237_DOUT_IN();
CS1237_DOUT_H();
CS1237IntEnable();
return reg_temp ;
}
/**读取CS1237的AD数*/
static int32_t Read_CS1237_Ad_Data(void)
{
uint16_t bit_cout = 0;
int32_t data_temp = 0;
/* clk1 ~ clk24 ADC数据*/
data_temp = 0;
for (bit_cout = 0; bit_cout < 24; bit_cout++)
{
CS1237_SCLK_H();
data_temp <<= 1; //左移1位准备接受数据 初始默认0
CS1237_5NS(60);//延时300ns
if(CS1237_DOUT_GET() == true) //有数值则累加
data_temp |= 1;
CS1237_SCLK_L();
CS1237_5NS(60);
}
/* clk25 ~ clk27 */
for (bit_cout = 24; bit_cout < 27; bit_cout++)
{
CS1237_Clock(); //给一周期时钟
}
CS1237_DOUT_H();
CS1237_SCLK_L();
if(data_temp > 0x7FFFFF) //取24位
{
data_temp |= 0xFF000000;
}
return data_temp;
}
void RIGHTUP_CS1237_IrqCallBack(void)
{
CS1237IrqFlag = true;
}
void RIGHTUP_CS1237_Init(void)
{
CS1237IrqFlag = false;
BuildDelay = false;
RIGHTUP_CS1237Var.AinA_AD = 0;
RIGHTUP_CS1237Var.Temp_AD = 0;
RIGHTUP_CS1237Var.Jump_AD = 0;
CS1237IntEnable();
CS1237Port = CH_SEL_A;
CS1237Hz = SPEED_SEL_640Hz;
CS1237PGA = PGA_SEL_128;
uint8_t read_reg = 0x00;
uint8_t set_reg = REFO_ON | CS1237Hz | CS1237PGA | CS1237Port;
CS1237_1MS(20);
Set_CS1237_Config(set_reg);
CS1237_1MS(20);
read_reg = Read_CS1237_Config();
CS1237_1MS(20);
if(read_reg != set_reg){
DBG_LOG("RIGHTUP CS1237 Init ERR...\r\n");
//DBG_LOG("set_reg = %02X\tread_reg = %02X\r\n",set_reg,read_reg);
InitFlag = true;
}
else {
DBG_LOG("RIGHTUP CS1237 Init OK...\r\n");
//DBG_LOG("set_reg = %02X\tread_reg = %02X\r\n",set_reg,read_reg);
CS1237Port = read_reg & 0x03;
InitFlag = true;
}
CS1237IntDisable();
}
void RIGHTUP_CS1237DataLoopCollect(void)
{
static int32_t ad_array[PACK_NUM];
static uint8_t adcnt;
static uint8_t TimeOutmagcnt;
switch(RIGHTUP_CS1237Var.Status) {
case RUCS1237_STATUS_IDLE:{
break;}
case RUCS1237_STATUS_START:{
memset(&ad_array, 0x00, sizeof(ad_array));
adcnt = 0;
TimeOutmagcnt = 0;
memset(&RIGHTUP_CS1237Var, NULL, sizeof(RIGHTUP_CS1237Var));
if(BuildDelay == true)
{
BuildDelay = false;
if(CS1237Hz == SPEED_SEL_10Hz){
RIGHTUP_CS1237Var.CS1237Delay1mSCnt = tCon_10Hz;
}
if(CS1237Hz == SPEED_SEL_40Hz){
RIGHTUP_CS1237Var.CS1237Delay1mSCnt = tCon_40Hz;
}
if(CS1237Hz == SPEED_SEL_640Hz){
RIGHTUP_CS1237Var.CS1237Delay1mSCnt = tCon_640Hz;
}
if(CS1237Hz == SPEED_SEL6_1280Hz){
RIGHTUP_CS1237Var.CS1237Delay1mSCnt = tCon_1280Hz;
}
RIGHTUP_CS1237Var.Status = RUCS1237_STATUS_DELAY;
}
else
{
RIGHTUP_CS1237Var.Status = RUCS1237_STATUS_READ;
}
break;}
case RUCS1237_STATUS_DELAY:{
if(RIGHTUP_CS1237Var.CS1237Delay1mSCnt <= 0){
RIGHTUP_CS1237Var.Status = RUCS1237_STATUS_READ;
}
break;}
case RUCS1237_STATUS_READ:{
CS1237IrqFlag = false;
RIGHTUP_CS1237Var.CS1237Delay1mSCnt = 100;
RIGHTUP_CS1237Var.Status = RUCS1237_STATUS_WAIT_READ;
break;}
case RUCS1237_STATUS_WAIT_READ:{
if(RIGHTUP_CS1237Var.CS1237Delay1mSCnt <= 0){
RIGHTUP_CS1237Var.Status = RUCS1237_STATUS_READ;
TimeOutmagcnt++;
}
if(CS1237IrqFlag == true){
CS1237IrqFlag = false;
ad_array[adcnt++] = Read_CS1237_Ad_Data();
RIGHTUP_CS1237Var.Status = RUCS1237_STATUS_READ;
}
if(TimeOutmagcnt >= PACK_NUM){
TimeOutmagcnt = 0;
if(adcnt > 0){
if(CS1237Port == CH_SEL_A){
RIGHTUP_CS1237Var.AinA_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
RIGHTUP_CS1237AinADataProcessCallBack(RIGHTUP_CS1237Var.AinA_AD);
}
if(CS1237Port == CH_SEL_TEMP){
RIGHTUP_CS1237Var.Temp_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
//CS1237TempDataProcessCallBack(LEFTLOW_CS1237Var.Temp_AD);
}
if(CS1237Port == CH_SEL_JUMP){
RIGHTUP_CS1237Var.Jump_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
//CS1237JumpDataProcessCallBack(LEFTLOW_CS1237Var.Jump_AD);
}
RIGHTUP_CS1237Var.Status = RUCS1237_STATUS_CH_SEL;
}
else{
if(CS1237Port == CH_SEL_A){
DBG_LOG("RIGHTUP CS1237 CHA TimeOut...\r\n");
}
if(CS1237Port == CH_SEL_TEMP){
DBG_LOG("RIGHTUP CS1237 Temp TimeOut...\r\n");
}
if(CS1237Port == CH_SEL_JUMP){
DBG_LOG("RIGHTUP CS1237 Jump TimeOut...\r\n");
}
RIGHTUP_CS1237Var.Status = RUCS1237_STATUS_CH_SEL;
}
}
if(adcnt >= PACK_NUM){
if(CS1237Port == CH_SEL_A){
RIGHTUP_CS1237Var.AinA_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
RIGHTUP_CS1237AinADataProcessCallBack(RIGHTUP_CS1237Var.AinA_AD);
}
if(CS1237Port == CH_SEL_TEMP){
RIGHTUP_CS1237Var.Temp_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
//CS1237TempDataProcessCallBack(LEFTLOW_CS1237Var.Temp_AD);
}
if(CS1237Port == CH_SEL_JUMP){
RIGHTUP_CS1237Var.Jump_AD = IntFilter_32t(ad_array, adcnt, FILTER_NUM);
//CS1237JumpDataProcessCallBack(LEFTLOW_CS1237Var.Jump_AD);
}
RIGHTUP_CS1237Var.Status = RUCS1237_STATUS_CH_SEL;
}
break;}
case RUCS1237_STATUS_CH_SEL:{
RIGHTUP_CS1237Var.Status = RUCS1237_STATUS_STOP;
BuildDelay = false;
uint8_t read_reg;
if(CS1237Port == CH_SEL_A){
#if(PORT_TEMP == 1)
read_reg = Read_CS1237_Config();
Set_CS1237_Config((read_reg & 0xFC) | CH_SEL_TEMP);
CS1237Port = CH_SEL_TEMP;
BuildDelay = true;
break;
#endif
#if(PORT_JUMP == 1)
read_reg = Read_CS1237_Config();
Set_CS1237_Config((read_reg & 0xFC) | CH_SEL_JUMP);
CS1237Port = CH_SEL_JUMP;
BuildDelay = true;
break;
#endif
}
if(CS1237Port == CH_SEL_TEMP){
#if(PORT_JUMP == 1)
read_reg = Read_CS1238_Config();
Set_CS1238_Config((read_reg & 0xFC) | CH_SEL_JUMP);
CS1238Port = CH_SEL_JUMP;
BuildDelay = true;
break;
#endif
#if(PORT_A == 1)
read_reg = Read_CS1237_Config();
Set_CS1237_Config((read_reg & 0xFC) | CH_SEL_A);
CS1237Port = CH_SEL_A;
BuildDelay = true;
break;
#endif
}
if(CS1237Port == CH_SEL_JUMP){
#if(PORT_A == 1)
read_reg = Read_CS1237_Config();
Set_CS1237_Config((read_reg & 0xFC) | CH_SEL_A);
CS1237Port = CH_SEL_A;
BuildDelay = true;
break;
#endif
#if(PORT_TEMP == 1)
read_reg = Read_CS1237_Config();
Set_CS1237_Config((read_reg & 0xFC) | CH_SEL_TEMP);
CS1237Port = CH_SEL_TEMP;
BuildDelay = true;
break;
#endif
}
break;}
case RUCS1237_STATUS_STOP:{
RIGHTUP_CS1237Stop();
RIGHTUP_CS1237Var.Status = RUCS1237_STATUS_IDLE;
//RIGHTUP_CS1237Var.Status = RUCS1237_STATUS_START;//持续工作
break;}
}
}
void RIGHTUP_CS12371mSRoutine(void)
{
if(RIGHTUP_CS1237Var.CS1237Delay1mSCnt > 0)
RIGHTUP_CS1237Var.CS1237Delay1mSCnt--;
}
void RIGHTUP_CS1237Start(void)
{
CS1237_WakeUp();
CS1237_1MS(2);
BuildDelay = true;
CS1237IntEnable();
if(!InitFlag){
RIGHTUP_CS1237_Init();
return;
}
RIGHTUP_CS1237Var.Status = RUCS1237_STATUS_START;
}
void RIGHTUP_CS1237Stop(void)
{
CS1237IntDisable();
//CS1237_Sleep();
}
Project/source/Module/CS1237/CS1237_RIGHTUP.h
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#include "bsp.h"
#ifndef _CS1237_RIGHTUP_H_
#define _CS1237_RIGHTUP_H_
#define READ_CONFIG_CMD 0x56
#define WRITE_CONFIG_CMD 0x65
#define CONFIG_RST 0x0C
#define REFO_OFF 0x40
#define REFO_ON 0x00
#define SPEED_SEL_10Hz 0x00
#define SPEED_SEL_40Hz 0x10
#define SPEED_SEL_640Hz 0x20
#define SPEED_SEL6_1280Hz 0x30
#define PGA_SEL_1 0x00
#define PGA_SEL_2 0x04
#define PGA_SEL_64 0x08
#define PGA_SEL_128 0x0C
#define CH_SEL_A 0x00
//#define CH_SEL_B 0x01
#define CH_SEL_TEMP 0x02
#define CH_SEL_JUMP 0x03
/*Definition of conversion time corresponding to repeatability setting*/
/*
10Hz //建立时间300ms
40Hz //建立时间75ms
640Hz //建立时间6.25ms
1280Hz //建立时间3.125ms
*/
#define tCon_10Hz 300 /* ms. */
#define tCon_40Hz 75 /* ms. */
#define tCon_640Hz 7 /* ms. */
#define tCon_1280Hz 4 /* ms. */
#define PORT_A 1 //采集通道A
//#define PORT_B 1 //采集通道B
#define PORT_TEMP 0 //采集温度
#define PORT_JUMP 0 //内短采集
#define PACK_NUM 1 //一次采集的数据包数量
#define FILTER_NUM 0 //滤波数
typedef enum{
RUCS1237_STATUS_IDLE,
RUCS1237_STATUS_START,
RUCS1237_STATUS_DELAY,
RUCS1237_STATUS_READ,
RUCS1237_STATUS_WAIT_READ,
RUCS1237_STATUS_CH_SEL,
RUCS1237_STATUS_STOP,
}RightUpCS1237Status_m;
typedef struct{
RightUpCS1237Status_m Status;
uint32_t CS1237Delay1mSCnt;
int32_t AinA_AD;//AINAad数据
//int32_t AinB_AD;//AINBad数据
int32_t Temp_AD;//温度ad数据
int32_t Jump_AD;//内短ad数据
}
RIGHTUP_CS1237Var_t;
void RIGHTUP_CS1237_Init(void);
void RIGHTUP_CS1237_IrqCallBack(void);
void RIGHTUP_CS1237DataLoopCollect(void);
void RIGHTUP_CS12371mSRoutine(void);
void RIGHTUP_CS1237Start(void);
void RIGHTUP_CS1237Stop(void);
#endif
Project/source/Module/SX127x/sx127x.c
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#include "sx127x.h"
#include "Debug.h"
#if (LORA_MODULE == SX1278W1)
Sx1276Type_t LoRaPara = {
.ucChannel = 0,
.dwFreqHz = FREQ_CENT,
.ucPower = 20,
.SignalBw = SX1276_BW_250K,
.SpreadFactor = SX1276_SF_512,
.ErrorCoding = SX1276_EC_4_6,
.RegPreamble = 10,
.ucOpModePrev = RFLR_OPMODE_STANDBY,
.bAntSwPrev = RF_ANT_RECEIVER,
.RegBuff = 0,
.State = SX1276_IDLE,
.ucRxPacketSize = 0,
.ucTxPacketSize = 0,
.RxCallBack = NULL,
};
void LoraReset(void)
{
LORA_RESET_CLR();
Ddl_Delay1ms(1);
LORA_RESET_SET();
}
/////////////////////////////////////////////////
void SX1276SetAntSw(Sx1276AntStatus_m Status)
{
switch(Status){
case RF_ANT_TRANSMITTER:
LORA_ANTTXEN();
break;
case RF_ANT_RECEIVER:
LORA_ANTRXEN();
break;
case RF_ANT_CLOSE:
LORA_ANTCLOSE();
break;
}
}
void SX1276ReadBuffer(uint8_t ucAddr, uint8_t *pucBuff, uint8_t ucLen)
{
uint8_t ucCnt;
LORA_SPI_NSS_CLR();
LORA_SPI_READ_WRITE(ucAddr & 0x7F);
for( ucCnt = 0; ucCnt < ucLen; ucCnt++ ){
pucBuff[ucCnt] = LORA_SPI_READ_WRITE(0);
}
LORA_SPI_NSS_SET();
}
void SX1276WriteBuffer(uint8_t ucAddr, uint8_t *pucBuff, uint8_t ucLen)
{
uint8_t ucCnt;
LORA_SPI_NSS_CLR();
LORA_SPI_READ_WRITE(ucAddr | 0x80);
for( ucCnt = 0; ucCnt < ucLen; ucCnt++ ){
LORA_SPI_READ_WRITE(pucBuff[ucCnt]);
}
LORA_SPI_NSS_SET();
}
void SX1276Write(uint8_t ucAddr, uint8_t ucData)
{
SX1276WriteBuffer(ucAddr, &ucData, 1);
}
void SX1276Read(uint8_t ucAddr, uint8_t * pucData)
{
SX1276ReadBuffer(ucAddr, pucData, 1);
}
void SX1276WriteFifo(uint8_t *pucBuff, uint8_t ucLen)
{
SX1276WriteBuffer(0, pucBuff, ucLen);
}
void SX1276ReadFifo(uint8_t *pucBuff, uint8_t ucLen)
{
SX1276ReadBuffer(0, pucBuff, ucLen);
}
/////////////////////////////////////////////////
void SX1276LoRaSetNbTrigPeaks(uint8_t ucValue)
{
SX1276Read(0x31, &(LoRaPara.RegBuff.RegTestReserved31));
LoRaPara.RegBuff.RegTestReserved31 = (LoRaPara.RegBuff.RegTestReserved31 & 0xF8) | ucValue;
SX1276Write(0x31, LoRaPara.RegBuff.RegTestReserved31 );
}
void SX1276LoRaSetSignalBandwidth(Sx1276BwType Bw)
{
SX1276Read(REG_LR_MODEMCONFIG1, &(LoRaPara.RegBuff.RegModemConfig1));
LoRaPara.RegBuff.RegModemConfig1 = (LoRaPara.RegBuff.RegModemConfig1 & RFLR_MODEMCONFIG1_BW_MASK) | Bw;
SX1276Write(REG_LR_MODEMCONFIG1, LoRaPara.RegBuff.RegModemConfig1);
LoRaPara.SignalBw = Bw;
}
void SX1276LoRaSetSpreadingFactor(Sx1276SpreadFactorType Factor)
{
if (Factor > SX1276_SF_4096){
Factor = SX1276_SF_4096;
}
else if (Factor < SX1276_SF_64){
Factor = SX1276_SF_64;
}
if (Factor == SX1276_SF_64){
SX1276LoRaSetNbTrigPeaks(5);
}
else{
SX1276LoRaSetNbTrigPeaks(3);
}
SX1276Read(REG_LR_MODEMCONFIG2, &(LoRaPara.RegBuff.RegModemConfig2));
LoRaPara.RegBuff.RegModemConfig2 = (LoRaPara.RegBuff.RegModemConfig2 & RFLR_MODEMCONFIG2_SF_MASK ) | Factor;
SX1276Write(REG_LR_MODEMCONFIG2, LoRaPara.RegBuff.RegModemConfig2);
LoRaPara.SpreadFactor = Factor;
}
void SX1276LoRaSetErrorCoding(Sx1276ErrorCodingType Value){
SX1276Read(REG_LR_MODEMCONFIG1, &(LoRaPara.RegBuff.RegModemConfig1));
LoRaPara.RegBuff.RegModemConfig1 = (LoRaPara.RegBuff.RegModemConfig1 & RFLR_MODEMCONFIG1_CODINGRATE_MASK ) | Value;
SX1276Write(REG_LR_MODEMCONFIG1, LoRaPara.RegBuff.RegModemConfig1 );
LoRaPara.ErrorCoding = Value;
}
void SX1276LoRaSetFreqHz(uint32_t dwFreqHz)
{
LoRaPara.dwFreqHz = dwFreqHz;
dwFreqHz = ( uint32_t )( ( double )dwFreqHz / ( double )FREQ_STEP );
LoRaPara.RegBuff.RegFrfMsb = ( uint8_t )( ( dwFreqHz >> 16 ) & 0xFF );
LoRaPara.RegBuff.RegFrfMid = ( uint8_t )( ( dwFreqHz >> 8 ) & 0xFF );
LoRaPara.RegBuff.RegFrfLsb = ( uint8_t )( dwFreqHz & 0xFF );
SX1276WriteBuffer(REG_LR_FRFMSB, &(LoRaPara.RegBuff.RegFrfMsb), 3);
}
void SX1276LoRaSetSymbTimeout(uint16_t ucValue)
{
SX1276ReadBuffer(REG_LR_MODEMCONFIG2, &(LoRaPara.RegBuff.RegModemConfig2), 2);
LoRaPara.RegBuff.RegModemConfig2 = (LoRaPara.RegBuff.RegModemConfig2 & RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK) | (( ucValue >> 8) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK );
LoRaPara.RegBuff.RegSymbTimeoutLsb = ucValue & 0xFF;
SX1276WriteBuffer(REG_LR_MODEMCONFIG2, &(LoRaPara.RegBuff.RegModemConfig2), 2);
}
void SX1276LoRaSetLowDatarateOptimize(bool bEnable)
{
SX1276Read(REG_LR_MODEMCONFIG3, &(LoRaPara.RegBuff.RegModemConfig3));
LoRaPara.RegBuff.RegModemConfig3 = (LoRaPara.RegBuff.RegModemConfig3 & RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) | ( bEnable << 3 );
SX1276Write(REG_LR_MODEMCONFIG3, LoRaPara.RegBuff.RegModemConfig3);
}
void SX1276LoRaSetPAOutput(uint8_t ucOutputPin)
{
SX1276Read(REG_LR_PACONFIG, &(LoRaPara.RegBuff.RegPaConfig));
LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_PASELECT_MASK ) | ucOutputPin;
SX1276Write(REG_LR_PACONFIG, LoRaPara.RegBuff.RegPaConfig );
}
void SX1276LoRaSetPa20dBm(bool bEnable)
{
SX1276Read(REG_LR_PADAC, &(LoRaPara.RegBuff.RegPaDac));
SX1276Read(REG_LR_PACONFIG, &(LoRaPara.RegBuff.RegPaConfig));
if ((LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_PASELECT_PABOOST ) == RFLR_PACONFIG_PASELECT_PABOOST ) {
if( bEnable == true ){
LoRaPara.RegBuff.RegPaDac = 0x87;
}
}
else{
LoRaPara.RegBuff.RegPaDac = 0x84;
}
SX1276Write(REG_LR_PADAC, LoRaPara.RegBuff.RegPaDac );
}
void SX1276LoRaSetRfPower(int8_t sbPower)
{
SX1276Read(REG_LR_PACONFIG, &(LoRaPara.RegBuff.RegPaConfig));
SX1276Read(REG_LR_PADAC, &(LoRaPara.RegBuff.RegPaDac));
if ((LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_PASELECT_PABOOST ) == RFLR_PACONFIG_PASELECT_PABOOST ) {
if ((LoRaPara.RegBuff.RegPaDac & 0x87) == 0x87){
if( sbPower < 5 ){
sbPower = 5;
}
if( sbPower > 20){
sbPower = 20;
}
LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70;
LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) |
( uint8_t )( ( uint16_t )( sbPower - 5 ) & 0x0F );
}
else{
if( sbPower < 2){
sbPower = 2;
}
if( sbPower > 17){
sbPower = 17;
}
LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70;
LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) |
( uint8_t )( ( uint16_t )( sbPower - 2 ) & 0x0F );
}
}
else{
if( sbPower < -1){
sbPower = -1;
}
if( sbPower > 14){
sbPower = 14;
}
LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70;
LoRaPara.RegBuff.RegPaConfig = (LoRaPara.RegBuff.RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) |
( uint8_t )( ( uint16_t )( sbPower + 1 ) & 0x0F );
}
SX1276Write(REG_LR_PACONFIG, LoRaPara.RegBuff.RegPaConfig);
LoRaPara.ucPower = sbPower;
}
void SX1276LoRaSetOpMode(Sx1276OpModeType ucOpMode)
{
Sx1276AntStatus_m bAntSwStatus = RF_ANT_RECEIVER;
LoRaPara.ucOpModePrev = LoRaPara.RegBuff.RegOpMode & ~RFLR_OPMODE_MASK;
if( ucOpMode != LoRaPara.ucOpModePrev){
if(ucOpMode == RFLR_OPMODE_TRANSMITTER){
bAntSwStatus = RF_ANT_TRANSMITTER;
}
else if(ucOpMode == RFLR_OPMODE_RECEIVER){
bAntSwStatus = RF_ANT_RECEIVER;
}
else {
bAntSwStatus = RF_ANT_CLOSE;
}
if( bAntSwStatus != LoRaPara.bAntSwPrev ){
LoRaPara.bAntSwPrev = bAntSwStatus;
SX1276SetAntSw(bAntSwStatus);
}
LoRaPara.RegBuff.RegOpMode = (LoRaPara.RegBuff.RegOpMode & RFLR_OPMODE_MASK ) | ucOpMode;
SX1276Write( REG_LR_OPMODE, LoRaPara.RegBuff.RegOpMode);
}
}
////////////////////////////////////////////////////////////////
void Sx1276LoRaEnterRx(void)
{
uint8_t ucCnt;
SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY);
LoRaPara.RegBuff.RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT | RFLR_IRQFLAGS_VALIDHEADER | RFLR_IRQFLAGS_TXDONE;
SX1276Write(REG_LR_IRQFLAGSMASK, LoRaPara.RegBuff.RegIrqFlagsMask);
LoRaPara.RegBuff.RegHopPeriod = 255;
SX1276Write(REG_LR_HOPPERIOD, LoRaPara.RegBuff.RegHopPeriod );
// RxDone RxTimeout FhssChangeChannel ValidHeader
LoRaPara.RegBuff.RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_01 | RFLR_DIOMAPPING1_DIO3_01;
// CadDetected ModeReady
LoRaPara.RegBuff.RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_00 | RFLR_DIOMAPPING2_DIO5_00;
SX1276WriteBuffer(REG_LR_DIOMAPPING1, &(LoRaPara.RegBuff.RegDioMapping1), 2);
LoRaPara.RegBuff.RegFifoAddrPtr = LoRaPara.RegBuff.RegFifoRxBaseAddr;
SX1276Write(REG_LR_FIFOADDRPTR, LoRaPara.RegBuff.RegFifoAddrPtr);
SX1276LoRaSetOpMode(RFLR_OPMODE_RECEIVER);
for (ucCnt=0; ucCnt< LORA_BUFF_SIZE; ucCnt++){
LoRaPara.RxTxBuff[ucCnt] = 0;
}
LoRaPara.State = SX1276_IDLE;//COMST_RX
uint8_t temp;
SX1276Read(REG_LR_IRQFLAGS, &temp);
}
/////////////////////////////////////////////////
void Sx1276LoRaInit(void (*RxCallBack)(uint8_t *rBuff, uint8_t rlen))
{
if(RxCallBack != NULL) {
LoRaPara.RxCallBack = RxCallBack;
}
LoraReset();
SX1276LoRaSetOpMode(RFLR_OPMODE_SLEEP);
LoRaPara.RegBuff.RegOpMode = (LoRaPara.RegBuff.RegOpMode & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON;
SX1276Write(REG_LR_OPMODE, LoRaPara.RegBuff.RegOpMode );
SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY);
// RxDone RxTimeout FhssChangeChannel ValidHeader
LoRaPara.RegBuff.RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_00 | RFLR_DIOMAPPING1_DIO3_01;
// CadDetected ModeReady
LoRaPara.RegBuff.RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_00 | RFLR_DIOMAPPING2_DIO5_00;
SX1276WriteBuffer(REG_LR_DIOMAPPING1, &(LoRaPara.RegBuff.RegDioMapping1), 2 );
SX1276ReadBuffer(REG_LR_OPMODE, (uint8_t*)&(LoRaPara.RegBuff) + 1, SIZE_OF_REGISTERS);
LoRaPara.State = SX1276_BUSY;
SX1276Read(REG_LR_VERSION, &(LoRaPara.RegBuff.RegVersion));
SX1276ReadBuffer(REG_LR_OPMODE, (uint8_t*)&(LoRaPara.RegBuff) + 1, SIZE_OF_REGISTERS);
LoRaPara.RegBuff.RegLna = RFLR_LNA_GAIN_G1;
SX1276WriteBuffer(REG_LR_OPMODE, (uint8_t*)&(LoRaPara.RegBuff) + 1, SIZE_OF_REGISTERS);
// set the RF settings
SX1276LoRaSetFreqHz(LoRaPara.dwFreqHz);
//REG_LR_MODEMCONFIG1
SX1276Read(REG_LR_MODEMCONFIG1, &(LoRaPara.RegBuff.RegModemConfig1));
//SignalBandwidth
LoRaPara.RegBuff.RegModemConfig1 = (LoRaPara.RegBuff.RegModemConfig1 & RFLR_MODEMCONFIG1_BW_MASK ) | LoRaPara.SignalBw;
//ErrorCoding
LoRaPara.RegBuff.RegModemConfig1 = (LoRaPara.RegBuff.RegModemConfig1 & RFLR_MODEMCONFIG1_CODINGRATE_MASK ) | LoRaPara.ErrorCoding;
//IMPLICITHEADER
LoRaPara.RegBuff.RegModemConfig1 = LoRaPara.RegBuff.RegModemConfig1 | RFLR_MODEMCONFIG1_IMPLICITHEADER_ON;
SX1276Write(REG_LR_MODEMCONFIG1, LoRaPara.RegBuff.RegModemConfig1);
//REG_LR_MODEMCONFIG2
SX1276Read(REG_LR_MODEMCONFIG2, &(LoRaPara.RegBuff.RegModemConfig2));
//SpreadingFactor
if( LoRaPara.SpreadFactor == SX1276_SF_64){
SX1276LoRaSetNbTrigPeaks(5);
SX1276LoRaSetLowDatarateOptimize(true); //低数据速率设置
}
else{
SX1276LoRaSetNbTrigPeaks(3);
SX1276LoRaSetLowDatarateOptimize(false); //低数据速率设置
}
LoRaPara.RegBuff.RegModemConfig2 = (LoRaPara.RegBuff.RegModemConfig2 & RFLR_MODEMCONFIG2_SF_MASK ) | LoRaPara.SpreadFactor;
//PacketCrcOn
LoRaPara.RegBuff.RegModemConfig2 = (LoRaPara.RegBuff.RegModemConfig2 & RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) | SX1276_CRC_ON; //SX1276_CRC_OFF
SX1276Write(REG_LR_MODEMCONFIG2, LoRaPara.RegBuff.RegModemConfig2);
LoRaPara.RegBuff.RegModemConfig2 = 0;
SX1276Read(REG_LR_MODEMCONFIG2, &(LoRaPara.RegBuff.RegModemConfig2));
SX1276LoRaSetSymbTimeout(0x3FF);
LoRaPara.RegBuff.RegPreambleMsb= (LoRaPara.RegPreamble >> 8) & 0x00ff;
LoRaPara.RegBuff.RegPreambleLsb= LoRaPara.RegPreamble & 0x00ff;
SX1276Write(REG_LR_PREAMBLEMSB, LoRaPara.RegBuff.RegPreambleMsb);
SX1276Write(REG_LR_PREAMBLELSB, LoRaPara.RegBuff.RegPreambleLsb);
SX1276Write(REG_LR_PAYLOADLENGTH, LORA_BUFF_SIZE);
SX1276Write(REG_LR_PAYLOADMAXLENGTH, LORA_BUFF_SIZE);
LoRaPara.RegBuff.RegPayloadLength = LORA_BUFF_SIZE;
#ifndef USE_LORA_860_PA
if(LoRaPara.dwFreqHz > 860000000 ){
SX1276LoRaSetPAOutput(RFLR_PACONFIG_PASELECT_RFO);
SX1276LoRaSetPa20dBm(false);
LoRaPara.ucPower = 14;
}
else
#endif
{
SX1276LoRaSetPAOutput(RFLR_PACONFIG_PASELECT_PABOOST);
SX1276LoRaSetPa20dBm(true);
LoRaPara.ucPower = 20;
}
SX1276LoRaSetRfPower(LoRaPara.ucPower);
SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY);
Sx1276LoRaEnterRx();
}
void IsrSx1276LoRaTxRx(void){
switch (LoRaPara.State){
case SX1276_IDLE:
case SX1276_RX:
// Clear Irq
SET_LORA_RX_LED();
do {
SX1276Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE);
SX1276Read(REG_LR_IRQFLAGS, &(LoRaPara.RegBuff.RegIrqFlags));
if((LoRaPara.RegBuff.RegIrqFlags & RFLR_IRQFLAGS_RXDONE) != RFLR_IRQFLAGS_RXDONE)
break;
}while(1);
if((LoRaPara.RegBuff.RegIrqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR ) == RFLR_IRQFLAGS_PAYLOADCRCERROR) {
// Clear Irq
SX1276Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR);
LoRaPara.State = SX1276_IDLE;
break;
}
SX1276Read(REG_LR_PKTSNRVALUE, &(LoRaPara.RegBuff.RegPktSnrValue));
SX1276Read(REG_LR_RSSIVALUE, &(LoRaPara.RegBuff.RegRssiValue));
SX1276Read(REG_LR_PKTRSSIVALUE, &(LoRaPara.RegBuff.RegPktRssiValue));
SX1276Read(REG_LR_FIFORXCURRENTADDR, &(LoRaPara.RegBuff.RegFifoRxCurrentAddr));
SX1276Read(REG_LR_NBRXBYTES, &(LoRaPara.RegBuff.RegNbRxBytes));
LoRaPara.ucRxPacketSize = LoRaPara.RegBuff.RegNbRxBytes;
LoRaPara.RegBuff.RegFifoAddrPtr = LoRaPara.RegBuff.RegFifoRxCurrentAddr;
SX1276Write(REG_LR_FIFOADDRPTR, LoRaPara.RegBuff.RegFifoAddrPtr);
SX1276ReadFifo(LoRaPara.RxTxBuff, (LoRaPara.ucRxPacketSize > LORA_BUFF_SIZE) ? LORA_BUFF_SIZE : LoRaPara.ucRxPacketSize);
uint8_t ucLen;
if(LoRaPara.ucRxPacketSize < LORA_BUFF_SIZE) {
ucLen= LoRaPara.ucRxPacketSize;
}
else {
ucLen= LORA_BUFF_SIZE;
}
LoRaPara.RxTxBuff[ucLen] = 0;
if(LoRaPara.RxCallBack != NULL)
LoRaPara.RxCallBack(LoRaPara.RxTxBuff, ucLen);
LoRaPara.ucRxPacketSize = 0;
LoRaPara.State = SX1276_IDLE;
CLR_LORA_RX_LED();
break;
case SX1276_TX:
// Clear Irq
SX1276Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE);
LORA_TXLED_OFF();
Sx1276LoRaEnterRx();
break;
default:
break;
}
}
void Sx1276LoRaLoopHandler(void)
{
if(LORA_GETDIO0() > 0){ // RxDone or TxDone
IsrSx1276LoRaTxRx();
}
}
void Sx1276LoRaSendBuffer(uint8_t* pucBuff, uint8_t ucLen)
{
LoRaPara.State = SX1276_BUSY;
if (ucLen > LORA_BUFF_SIZE){
ucLen = LORA_BUFF_SIZE;
}
LoRaPara.ucTxPacketSize = ucLen;
while(ucLen--){
LoRaPara.RxTxBuff[ucLen] = pucBuff[ucLen];
};
SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY);
LoRaPara.RegBuff.RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT | RFLR_IRQFLAGS_RXDONE | RFLR_IRQFLAGS_PAYLOADCRCERROR | RFLR_IRQFLAGS_VALIDHEADER;
//LoRaPara.RegBuff.RegHopPeriod = 0;
//SX1276Write(REG_LR_HOPPERIOD, LoRaPara.RegBuff.RegHopPeriod);
SX1276Write(REG_LR_IRQFLAGSMASK, LoRaPara.RegBuff.RegIrqFlagsMask);
// Initializes the payload size
LoRaPara.RegBuff.RegPayloadLength = LoRaPara.ucTxPacketSize;
SX1276Write(REG_LR_PAYLOADLENGTH, LoRaPara.RegBuff.RegPayloadLength);
LoRaPara.RegBuff.RegFifoTxBaseAddr = 0x00; // Full buffer used for Tx
SX1276Write(REG_LR_FIFOTXBASEADDR, LoRaPara.RegBuff.RegFifoTxBaseAddr);
LoRaPara.RegBuff.RegFifoAddrPtr = LoRaPara.RegBuff.RegFifoTxBaseAddr;
SX1276Write(REG_LR_FIFOADDRPTR, LoRaPara.RegBuff.RegFifoAddrPtr);
// Write payload buffer to LORA modem
SX1276WriteFifo(LoRaPara.RxTxBuff, LoRaPara.RegBuff.RegPayloadLength);
// TxDone RxTimeout FhssChangeChannel ValidHeader
LoRaPara.RegBuff.RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_00 | RFLR_DIOMAPPING1_DIO3_01;
// PllLock Mode Ready
LoRaPara.RegBuff.RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_01 | RFLR_DIOMAPPING2_DIO5_00;
SX1276WriteBuffer(REG_LR_DIOMAPPING1, &(LoRaPara.RegBuff.RegDioMapping1), 2);
SX1276LoRaSetOpMode(RFLR_OPMODE_TRANSMITTER);
uint8_t temp;
SX1276Read(REG_LR_IRQFLAGS, &temp);
LORA_TXLED_ON();
LoRaPara.State = SX1276_TX;
}
void Sx1276LoRaSleep(void)
{
SX1276LoRaSetOpMode(RFLR_OPMODE_SLEEP);//RFLR_OPMODE_STANDBY
}
void Sx1276LoRaWakeup(void)
{
Sx1276LoRaEnterRx();
}
////////////////////////////////////////
//配置本层参数的函数
//频道表
const uint32_t gdwSx1276ChannelTbl[SX1276_CHANNEL_MAX]={
FREQ_CENT-FREQ_DEV*8, FREQ_CENT-FREQ_DEV*7, FREQ_CENT-FREQ_DEV*6, FREQ_CENT-FREQ_DEV*5,
FREQ_CENT-FREQ_DEV*4, FREQ_CENT-FREQ_DEV*3, FREQ_CENT-FREQ_DEV*2, FREQ_CENT-FREQ_DEV*1,
FREQ_CENT+FREQ_DEV*0, FREQ_CENT+FREQ_DEV*1, FREQ_CENT+FREQ_DEV*2, FREQ_CENT+FREQ_DEV*3,
FREQ_CENT+FREQ_DEV*4, FREQ_CENT+FREQ_DEV*5, FREQ_CENT+FREQ_DEV*6, FREQ_CENT+FREQ_DEV*7,
FREQ_CENT+FREQ_DEV*8
};
//LORAPT_CHANNEL
uint8_t SX1276LoRaReadChannel(void)
{
return LoRaPara.ucChannel;
}
bool SX1276LoRaWriteChannel(uint8_t Channel)
{
if(Channel > SX1276_CHANNEL_MAX) {
return false;
}
LoRaPara.dwFreqHz = gdwSx1276ChannelTbl[Channel];
SX1276LoRaSetFreqHz(LoRaPara.dwFreqHz);
return true;
}
//LORAPT_FREQ,
uint32_t SX1276LoRaReadFreq(void)
{
return LoRaPara.dwFreqHz;
}
void SX1276LoRaWriteFreq(uint32_t Freq)
{
SX1276LoRaSetFreqHz(Freq);
}
//LORAPT_BW,
uint32_t SX1276LoRaReadBw(void)
{
return LoRaPara.SignalBw;
}
void SX1276LoRaWriteBw(Sx1276BwType SignalBw)
{
LoRaPara.SignalBw = SignalBw;
SX1276LoRaSetSignalBandwidth(SignalBw);
}
//LORAPT_SF,
uint8_t SX1276LoRaReadSf(void)
{
return LoRaPara.SpreadFactor;
}
void SX1276LoRaWriteSf(Sx1276SpreadFactorType SpreadFactor)
{
LoRaPara.SpreadFactor = SpreadFactor;
SX1276LoRaSetSpreadingFactor(LoRaPara.SpreadFactor);
}
//LORAPT_EC,
uint8_t SX1276LoRaReadEc(void)
{
return LoRaPara.ErrorCoding;
}
void SX1276LoRaWriteEc(Sx1276ErrorCodingType ErrorCoding)
{
LoRaPara.ErrorCoding = ErrorCoding;
SX1276LoRaSetErrorCoding(ErrorCoding);
}
//LORAPT_RSSI,
uint32_t SX1276LoRaParaReadRssi(void)
{
uint32_t rssi;
SX1276Read(REG_LR_PKTRSSIVALUE, &(LoRaPara.RegBuff.RegPktRssiValue));
SX1276Read(REG_LR_RSSIVALUE, &(LoRaPara.RegBuff.RegRssiValue));
rssi = (uint16_t)(LoRaPara.RegBuff.RegPktSnrValue)<<16;
rssi |= (uint16_t)(LoRaPara.RegBuff.RegRssiValue)<<8;
rssi |= LoRaPara.RegBuff.RegPktRssiValue;
return rssi;
}
uint8_t SX1276LoRaReadRssiPkt(void)
{
uint8_t RssiPkt;
SX1276Read(REG_LR_PKTRSSIVALUE, &LoRaPara.RegBuff.RegPktRssiValue);
RssiPkt = LoRaPara.RegBuff.RegPktRssiValue;
return RssiPkt;
}
//LORAPT_POWER,
void SX1276LoRaWritePwr(int8_t Pwr)
{
SX1276LoRaSetRfPower(Pwr);
}
//LORAPT_SET_RX,
void SX1276LoRaWriteRx(void)
{
Sx1276LoRaEnterRx();
}
//LORAPT_SET_SLEEP,true-Sleep, false-Wakeup
void SX1276LoRaWriteSleep(bool Sleep)
{
if(Sleep){
Sx1276LoRaSleep();
}
else {
Sx1276LoRaWakeup();
}
}
Sx1276StateType_t SX1276LoRaReadStatus(void)
{
return LoRaPara.State;
}
///////////////RSSI Calc///////////////
void SX1276LoCalcRssiSnr(int16_t *pswRssi, int8_t *psbSnr)
{
int8_t sbSnr= LoRaPara.RegBuff.RegPktSnrValue & 0x80 ? (-1)*((int8_t)(((~LoRaPara.RegBuff.RegPktSnrValue+ 1)& 0xFF)/4)): (~LoRaPara.RegBuff.RegPktSnrValue& 0xFF)/4;
if (*psbSnr > 0) {
*pswRssi= RSSI_OFFSET_LF+ LoRaPara.RegBuff.RegPktRssiValue;
}
else {
*pswRssi= NOISE_ABSOLUTE_ZERO + 10 + SIGNAL_BW_LOG_125KHZ + NOISE_FIGURE_LF + sbSnr;
}
*psbSnr= sbSnr;
}
#endif
Project/source/Module/SX127x/sx127x.h
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@@ -0,0 +1,789 @@
#ifndef __SX127X_H
#define __SX127X_H
#include "bsp.h"
//Constant values need to compute the RSSI value
#define RSSI_OFFSET_LF -155
#define RSSI_OFFSET_HF -150
#define NOISE_ABSOLUTE_ZERO -174
#define NOISE_FIGURE_LF 4
#define NOISE_FIGURE_HF 6
#define SIGNAL_BW_LOG_125KHZ 5
//SX1276 definitions
#define XTAL_FREQ 32000000
#define FREQ_STEP 61.03515625
//SX1276 Internal registers Address
#define REG_LR_FIFO 0x00
// Common settings
#define REG_LR_OPMODE 0x01
#define REG_LR_BANDSETTING 0x04
#define REG_LR_FRFMSB 0x06
#define REG_LR_FRFMID 0x07
#define REG_LR_FRFLSB 0x08
// Tx settings
#define REG_LR_PACONFIG 0x09
#define REG_LR_PARAMP 0x0A
#define REG_LR_OCP 0x0B
// Rx settings
#define REG_LR_LNA 0x0C
// LoRa registers
#define REG_LR_FIFOADDRPTR 0x0D
#define REG_LR_FIFOTXBASEADDR 0x0E
#define REG_LR_FIFORXBASEADDR 0x0F
#define REG_LR_FIFORXCURRENTADDR 0x10
#define REG_LR_IRQFLAGSMASK 0x11
#define REG_LR_IRQFLAGS 0x12
#define REG_LR_NBRXBYTES 0x13
#define REG_LR_RXHEADERCNTVALUEMSB 0x14
#define REG_LR_RXHEADERCNTVALUELSB 0x15
#define REG_LR_RXPACKETCNTVALUEMSB 0x16
#define REG_LR_RXPACKETCNTVALUELSB 0x17
#define REG_LR_MODEMSTAT 0x18
#define REG_LR_PKTSNRVALUE 0x19
#define REG_LR_PKTRSSIVALUE 0x1A
#define REG_LR_RSSIVALUE 0x1B
#define REG_LR_HOPCHANNEL 0x1C
#define REG_LR_MODEMCONFIG1 0x1D
#define REG_LR_MODEMCONFIG2 0x1E
#define REG_LR_SYMBTIMEOUTLSB 0x1F
#define REG_LR_PREAMBLEMSB 0x20
#define REG_LR_PREAMBLELSB 0x21
#define REG_LR_PAYLOADLENGTH 0x22
#define REG_LR_PAYLOADMAXLENGTH 0x23
#define REG_LR_HOPPERIOD 0x24
#define REG_LR_FIFORXBYTEADDR 0x25
#define REG_LR_MODEMCONFIG3 0x26
// end of documented register in datasheet
// I/O settings
#define REG_LR_DIOMAPPING1 0x40
#define REG_LR_DIOMAPPING2 0x41
// Version
#define REG_LR_VERSION 0x42
// Additional settings
#define REG_LR_PLLHOP 0x44
#define REG_LR_TCXO 0x4B
#define REG_LR_PADAC 0x4D
#define REG_LR_FORMERTEMP 0x5B
#define REG_LR_BITRATEFRAC 0x5D
#define REG_LR_AGCREF 0x61
#define REG_LR_AGCTHRESH1 0x62
#define REG_LR_AGCTHRESH2 0x63
#define REG_LR_AGCTHRESH3 0x64
//RegOpMode
typedef enum{
RFLR_OPMODE_LONGRANGEMODE_MASK =0x7F,
RFLR_OPMODE_LONGRANGEMODE_OFF =0x00, // Default
RFLR_OPMODE_LONGRANGEMODE_ON =0x80,
RFLR_OPMODE_ACCESSSHAREDREG_MASK =0xBF,
RFLR_OPMODE_ACCESSSHAREDREG_ENABLE =0x40,
RFLR_OPMODE_ACCESSSHAREDREG_DISABLE =0x00, // Default
RFLR_OPMODE_FREQMODE_ACCESS_MASK =0xF7,
RFLR_OPMODE_FREQMODE_ACCESS_LF =0x08, // Default
RFLR_OPMODE_FREQMODE_ACCESS_HF =0x00,
RFLR_OPMODE_MASK =0xF8,
RFLR_OPMODE_SLEEP =0x00,
RFLR_OPMODE_STANDBY =0x01, // Default
RFLR_OPMODE_SYNTHESIZER_TX =0x02,
RFLR_OPMODE_TRANSMITTER =0x03,
RFLR_OPMODE_SYNTHESIZER_RX =0x04,
RFLR_OPMODE_RECEIVER =0x05,
// LoRa specific modes
RFLR_OPMODE_RECEIVER_SINGLE =0x06,
RFLR_OPMODE_CAD =0x07
}Sx1276OpModeType;
//RegBandSetting
#define RFLR_BANDSETTING_MASK 0x3F
#define RFLR_BANDSETTING_AUTO 0x00 // Default
#define RFLR_BANDSETTING_DIV_BY_1 0x40
#define RFLR_BANDSETTING_DIV_BY_2 0x80
#define RFLR_BANDSETTING_DIV_BY_6 0xC0
//RegFrf (MHz)
#define RFLR_FRFMSB_434_MHZ 0x6C // Default
#define RFLR_FRFMID_434_MHZ 0x80 // Default
#define RFLR_FRFLSB_434_MHZ 0x00 // Default
#define RFLR_FRFMSB_863_MHZ 0xD7
#define RFLR_FRFMID_863_MHZ 0xC0
#define RFLR_FRFLSB_863_MHZ 0x00
#define RFLR_FRFMSB_864_MHZ 0xD8
#define RFLR_FRFMID_864_MHZ 0x00
#define RFLR_FRFLSB_864_MHZ 0x00
#define RFLR_FRFMSB_865_MHZ 0xD8
#define RFLR_FRFMID_865_MHZ 0x40
#define RFLR_FRFLSB_865_MHZ 0x00
#define RFLR_FRFMSB_866_MHZ 0xD8
#define RFLR_FRFMID_866_MHZ 0x80
#define RFLR_FRFLSB_866_MHZ 0x00
#define RFLR_FRFMSB_867_MHZ 0xD8
#define RFLR_FRFMID_867_MHZ 0xC0
#define RFLR_FRFLSB_867_MHZ 0x00
#define RFLR_FRFMSB_868_MHZ 0xD9
#define RFLR_FRFMID_868_MHZ 0x00
#define RFLR_FRFLSB_868_MHZ 0x00
#define RFLR_FRFMSB_869_MHZ 0xD9
#define RFLR_FRFMID_869_MHZ 0x40
#define RFLR_FRFLSB_869_MHZ 0x00
#define RFLR_FRFMSB_870_MHZ 0xD9
#define RFLR_FRFMID_870_MHZ 0x80
#define RFLR_FRFLSB_870_MHZ 0x00
#define RFLR_FRFMSB_902_MHZ 0xE1
#define RFLR_FRFMID_902_MHZ 0x80
#define RFLR_FRFLSB_902_MHZ 0x00
#define RFLR_FRFMSB_903_MHZ 0xE1
#define RFLR_FRFMID_903_MHZ 0xC0
#define RFLR_FRFLSB_903_MHZ 0x00
#define RFLR_FRFMSB_904_MHZ 0xE2
#define RFLR_FRFMID_904_MHZ 0x00
#define RFLR_FRFLSB_904_MHZ 0x00
#define RFLR_FRFMSB_905_MHZ 0xE2
#define RFLR_FRFMID_905_MHZ 0x40
#define RFLR_FRFLSB_905_MHZ 0x00
#define RFLR_FRFMSB_906_MHZ 0xE2
#define RFLR_FRFMID_906_MHZ 0x80
#define RFLR_FRFLSB_906_MHZ 0x00
#define RFLR_FRFMSB_907_MHZ 0xE2
#define RFLR_FRFMID_907_MHZ 0xC0
#define RFLR_FRFLSB_907_MHZ 0x00
#define RFLR_FRFMSB_908_MHZ 0xE3
#define RFLR_FRFMID_908_MHZ 0x00
#define RFLR_FRFLSB_908_MHZ 0x00
#define RFLR_FRFMSB_909_MHZ 0xE3
#define RFLR_FRFMID_909_MHZ 0x40
#define RFLR_FRFLSB_909_MHZ 0x00
#define RFLR_FRFMSB_910_MHZ 0xE3
#define RFLR_FRFMID_910_MHZ 0x80
#define RFLR_FRFLSB_910_MHZ 0x00
#define RFLR_FRFMSB_911_MHZ 0xE3
#define RFLR_FRFMID_911_MHZ 0xC0
#define RFLR_FRFLSB_911_MHZ 0x00
#define RFLR_FRFMSB_912_MHZ 0xE4
#define RFLR_FRFMID_912_MHZ 0x00
#define RFLR_FRFLSB_912_MHZ 0x00
#define RFLR_FRFMSB_913_MHZ 0xE4
#define RFLR_FRFMID_913_MHZ 0x40
#define RFLR_FRFLSB_913_MHZ 0x00
#define RFLR_FRFMSB_914_MHZ 0xE4
#define RFLR_FRFMID_914_MHZ 0x80
#define RFLR_FRFLSB_914_MHZ 0x00
#define RFLR_FRFMSB_915_MHZ 0xE4 // Default
#define RFLR_FRFMID_915_MHZ 0xC0 // Default
#define RFLR_FRFLSB_915_MHZ 0x00 // Default
#define RFLR_FRFMSB_916_MHZ 0xE5
#define RFLR_FRFMID_916_MHZ 0x00
#define RFLR_FRFLSB_916_MHZ 0x00
#define RFLR_FRFMSB_917_MHZ 0xE5
#define RFLR_FRFMID_917_MHZ 0x40
#define RFLR_FRFLSB_917_MHZ 0x00
#define RFLR_FRFMSB_918_MHZ 0xE5
#define RFLR_FRFMID_918_MHZ 0x80
#define RFLR_FRFLSB_918_MHZ 0x00
#define RFLR_FRFMSB_919_MHZ 0xE5
#define RFLR_FRFMID_919_MHZ 0xC0
#define RFLR_FRFLSB_919_MHZ 0x00
#define RFLR_FRFMSB_920_MHZ 0xE6
#define RFLR_FRFMID_920_MHZ 0x00
#define RFLR_FRFLSB_920_MHZ 0x00
#define RFLR_FRFMSB_921_MHZ 0xE6
#define RFLR_FRFMID_921_MHZ 0x40
#define RFLR_FRFLSB_921_MHZ 0x00
#define RFLR_FRFMSB_922_MHZ 0xE6
#define RFLR_FRFMID_922_MHZ 0x80
#define RFLR_FRFLSB_922_MHZ 0x00
#define RFLR_FRFMSB_923_MHZ 0xE6
#define RFLR_FRFMID_923_MHZ 0xC0
#define RFLR_FRFLSB_923_MHZ 0x00
#define RFLR_FRFMSB_924_MHZ 0xE7
#define RFLR_FRFMID_924_MHZ 0x00
#define RFLR_FRFLSB_924_MHZ 0x00
#define RFLR_FRFMSB_925_MHZ 0xE7
#define RFLR_FRFMID_925_MHZ 0x40
#define RFLR_FRFLSB_925_MHZ 0x00
#define RFLR_FRFMSB_926_MHZ 0xE7
#define RFLR_FRFMID_926_MHZ 0x80
#define RFLR_FRFLSB_926_MHZ 0x00
#define RFLR_FRFMSB_927_MHZ 0xE7
#define RFLR_FRFMID_927_MHZ 0xC0
#define RFLR_FRFLSB_927_MHZ 0x00
#define RFLR_FRFMSB_928_MHZ 0xE8
#define RFLR_FRFMID_928_MHZ 0x00
#define RFLR_FRFLSB_928_MHZ 0x00
//RegPaConfig
#define RFLR_PACONFIG_PASELECT_MASK 0x7F
#define RFLR_PACONFIG_PASELECT_PABOOST 0x80
#define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default
#define RFLR_PACONFIG_MAX_POWER_MASK 0x8F
#define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0
//RegPaRamp
#define RFLR_PARAMP_TXBANDFORCE_MASK 0xEF
#define RFLR_PARAMP_TXBANDFORCE_BAND_SEL 0x10
#define RFLR_PARAMP_TXBANDFORCE_AUTO 0x00 // Default
#define RFLR_PARAMP_MASK 0xF0
#define RFLR_PARAMP_3400_US 0x00
#define RFLR_PARAMP_2000_US 0x01
#define RFLR_PARAMP_1000_US 0x02
#define RFLR_PARAMP_0500_US 0x03
#define RFLR_PARAMP_0250_US 0x04
#define RFLR_PARAMP_0125_US 0x05
#define RFLR_PARAMP_0100_US 0x06
#define RFLR_PARAMP_0062_US 0x07
#define RFLR_PARAMP_0050_US 0x08
#define RFLR_PARAMP_0040_US 0x09 // Default
#define RFLR_PARAMP_0031_US 0x0A
#define RFLR_PARAMP_0025_US 0x0B
#define RFLR_PARAMP_0020_US 0x0C
#define RFLR_PARAMP_0015_US 0x0D
#define RFLR_PARAMP_0012_US 0x0E
#define RFLR_PARAMP_0010_US 0x0F
//RegOcp
#define RFLR_OCP_MASK 0xDF
#define RFLR_OCP_ON 0x20 // Default
#define RFLR_OCP_OFF 0x00
#define RFLR_OCP_TRIM_MASK 0xE0
#define RFLR_OCP_TRIM_045_MA 0x00
#define RFLR_OCP_TRIM_050_MA 0x01
#define RFLR_OCP_TRIM_055_MA 0x02
#define RFLR_OCP_TRIM_060_MA 0x03
#define RFLR_OCP_TRIM_065_MA 0x04
#define RFLR_OCP_TRIM_070_MA 0x05
#define RFLR_OCP_TRIM_075_MA 0x06
#define RFLR_OCP_TRIM_080_MA 0x07
#define RFLR_OCP_TRIM_085_MA 0x08
#define RFLR_OCP_TRIM_090_MA 0x09
#define RFLR_OCP_TRIM_095_MA 0x0A
#define RFLR_OCP_TRIM_100_MA 0x0B // Default
#define RFLR_OCP_TRIM_105_MA 0x0C
#define RFLR_OCP_TRIM_110_MA 0x0D
#define RFLR_OCP_TRIM_115_MA 0x0E
#define RFLR_OCP_TRIM_120_MA 0x0F
#define RFLR_OCP_TRIM_130_MA 0x10
#define RFLR_OCP_TRIM_140_MA 0x11
#define RFLR_OCP_TRIM_150_MA 0x12
#define RFLR_OCP_TRIM_160_MA 0x13
#define RFLR_OCP_TRIM_170_MA 0x14
#define RFLR_OCP_TRIM_180_MA 0x15
#define RFLR_OCP_TRIM_190_MA 0x16
#define RFLR_OCP_TRIM_200_MA 0x17
#define RFLR_OCP_TRIM_210_MA 0x18
#define RFLR_OCP_TRIM_220_MA 0x19
#define RFLR_OCP_TRIM_230_MA 0x1A
#define RFLR_OCP_TRIM_240_MA 0x1B
//RegLna
#define RFLR_LNA_GAIN_MASK 0x1F
#define RFLR_LNA_GAIN_G1 0x20 // Default
#define RFLR_LNA_GAIN_G2 0x40
#define RFLR_LNA_GAIN_G3 0x60
#define RFLR_LNA_GAIN_G4 0x80
#define RFLR_LNA_GAIN_G5 0xA0
#define RFLR_LNA_GAIN_G6 0xC0
#define RFLR_LNA_BOOST_LF_MASK 0xE7
#define RFLR_LNA_BOOST_LF_DEFAULT 0x00 // Default
#define RFLR_LNA_BOOST_LF_GAIN 0x08
#define RFLR_LNA_BOOST_LF_IP3 0x10
#define RFLR_LNA_BOOST_LF_BOOST 0x18
#define RFLR_LNA_RXBANDFORCE_MASK 0xFB
#define RFLR_LNA_RXBANDFORCE_BAND_SEL 0x04
#define RFLR_LNA_RXBANDFORCE_AUTO 0x00 // Default
#define RFLR_LNA_BOOST_HF_MASK 0xFC
#define RFLR_LNA_BOOST_HF_OFF 0x00 // Default
#define RFLR_LNA_BOOST_HF_ON 0x03
//RegFifoAddrPtr
#define RFLR_FIFOADDRPTR 0x00 // Default
//RegFifoTxBaseAddr
#define RFLR_FIFOTXBASEADDR 0x80 // Default
//RegFifoTxBaseAddr
#define RFLR_FIFORXBASEADDR 0x00 // Default
//RegFifoRxCurrentAddr (Read Only)
//RegIrqFlagsMask
#define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80
#define RFLR_IRQFLAGS_RXDONE_MASK 0x40
#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20
#define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10
#define RFLR_IRQFLAGS_TXDONE_MASK 0x08
#define RFLR_IRQFLAGS_CADDONE_MASK 0x04
#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02
#define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01
//RegIrqFlags
#define RFLR_IRQFLAGS_RXTIMEOUT 0x80
#define RFLR_IRQFLAGS_RXDONE 0x40
#define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20
#define RFLR_IRQFLAGS_VALIDHEADER 0x10
#define RFLR_IRQFLAGS_TXDONE 0x08
#define RFLR_IRQFLAGS_CADDONE 0x04
#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02
#define RFLR_IRQFLAGS_CADDETECTED 0x01
//RegModemStat (Read Only)
#define RFLR_MODEMSTAT_RX_CR_MASK 0x1F
#define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0
//RegModemConfig1
#define RFLR_MODEMCONFIG1_BW_MASK 0x0F
#define RFLR_MODEMCONFIG1_BW_7_81_KHZ 0x00
#define RFLR_MODEMCONFIG1_BW_10_41_KHZ 0x10
#define RFLR_MODEMCONFIG1_BW_15_62_KHZ 0x20
#define RFLR_MODEMCONFIG1_BW_20_83_KHZ 0x30
#define RFLR_MODEMCONFIG1_BW_31_25_KHZ 0x40
#define RFLR_MODEMCONFIG1_BW_41_66_KHZ 0x50
#define RFLR_MODEMCONFIG1_BW_62_50_KHZ 0x60
#define RFLR_MODEMCONFIG1_BW_125_KHZ 0x70 // Default
#define RFLR_MODEMCONFIG1_BW_250_KHZ 0x80
#define RFLR_MODEMCONFIG1_BW_500_KHZ 0x90
#define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xF1
#define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x02
#define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x04 // Default
#define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x06
#define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x08
#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFE
#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x00
#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x01 // Default
//RegModemConfig2
#define RFLR_MODEMCONFIG2_SF_MASK 0x0F
#define RFLR_MODEMCONFIG2_SF_6 0x60
#define RFLR_MODEMCONFIG2_SF_7 0x70 // Default
#define RFLR_MODEMCONFIG2_SF_8 0x80
#define RFLR_MODEMCONFIG2_SF_9 0x90
#define RFLR_MODEMCONFIG2_SF_10 0xA0
#define RFLR_MODEMCONFIG2_SF_11 0xB0
#define RFLR_MODEMCONFIG2_SF_12 0xC0
#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7
#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08
#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00
#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 0xFB
#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON 0x04
#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF 0x00 // Default
#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC
#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default
//RegHopChannel (Read Only)
#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F
#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80
#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default
#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_MASK 0xBF
#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_ON 0x40
#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_OFF 0x00 // Default
#define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F
//RegSymbTimeoutLsb
#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default
//RegPreambleLengthMsb
#define RFLR_PREAMBLELENGTHMSB 0x00 // Default
//RegPreambleLengthLsb
#define RFLR_PREAMBLELENGTHLSB 0x08 // Default
//RegPayloadLength
#define RFLR_PAYLOADLENGTH 0x0E // Default
//RegPayloadMaxLength
#define RFLR_PAYLOADMAXLENGTH 0xFF // Default
//RegHopPeriod
#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default
//RegDioMapping1
//DIO0
#define RFLR_DIOMAPPING1_DIO0_MASK 0x3F
#define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default
#define RFLR_DIOMAPPING1_DIO0_01 0x40
#define RFLR_DIOMAPPING1_DIO0_10 0x80
#define RFLR_DIOMAPPING1_DIO0_11 0xC0
//DIO1
#define RFLR_DIOMAPPING1_DIO1_MASK 0xCF
#define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default
#define RFLR_DIOMAPPING1_DIO1_01 0x10
#define RFLR_DIOMAPPING1_DIO1_10 0x20
#define RFLR_DIOMAPPING1_DIO1_11 0x30
//DIO2
#define RFLR_DIOMAPPING1_DIO2_MASK 0xF3
#define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default
#define RFLR_DIOMAPPING1_DIO2_01 0x04
#define RFLR_DIOMAPPING1_DIO2_10 0x08
#define RFLR_DIOMAPPING1_DIO2_11 0x0C
//DIO3
#define RFLR_DIOMAPPING1_DIO3_MASK 0xFC
#define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default
#define RFLR_DIOMAPPING1_DIO3_01 0x01
#define RFLR_DIOMAPPING1_DIO3_10 0x02
#define RFLR_DIOMAPPING1_DIO3_11 0x03
//RegDioMapping2
//DIO4
#define RFLR_DIOMAPPING2_DIO4_MASK 0x3F
#define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default
#define RFLR_DIOMAPPING2_DIO4_01 0x40
#define RFLR_DIOMAPPING2_DIO4_10 0x80
#define RFLR_DIOMAPPING2_DIO4_11 0xC0
//DIO5
#define RFLR_DIOMAPPING2_DIO5_MASK 0xCF
#define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default
#define RFLR_DIOMAPPING2_DIO5_01 0x10
#define RFLR_DIOMAPPING2_DIO5_10 0x20
#define RFLR_DIOMAPPING2_DIO5_11 0x30
//MAP
#define RFLR_DIOMAPPING2_MAP_MASK 0xFE
#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01
#define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default
// RegPllHop
#define RFLR_PLLHOP_FASTHOP_MASK 0x7F
#define RFLR_PLLHOP_FASTHOP_ON 0x80
#define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default
//RegTcxo
#define RFLR_TCXO_TCXOINPUT_MASK 0xEF
#define RFLR_TCXO_TCXOINPUT_ON 0x10
#define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default
//RegPaDac
#define RFLR_PADAC_20DBM_MASK 0xF8
#define RFLR_PADAC_20DBM_ON 0x07
#define RFLR_PADAC_20DBM_OFF 0x04 // Default
//RegPll
#define RFLR_PLL_BANDWIDTH_MASK 0x3F
#define RFLR_PLL_BANDWIDTH_75 0x00
#define RFLR_PLL_BANDWIDTH_150 0x40
#define RFLR_PLL_BANDWIDTH_225 0x80
#define RFLR_PLL_BANDWIDTH_300 0xC0 // Default
//RegPllLowPn
#define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F
#define RFLR_PLLLOWPN_BANDWIDTH_75 0x00
#define RFLR_PLLLOWPN_BANDWIDTH_150 0x40
#define RFLR_PLLLOWPN_BANDWIDTH_225 0x80
#define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default
//RegModemConfig3
#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK 0xF7
#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON 0x08
#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF 0x00 // Default
#define RFLR_MODEMCONFIG3_AGCAUTO_MASK 0xFB
#define RFLR_MODEMCONFIG3_AGCAUTO_ON 0x04 // Default
#define RFLR_MODEMCONFIG3_AGCAUTO_OFF 0x00
//REGISTER
typedef struct _Sx1276RegType{
uint8_t RegFifo; // 0x00
// Common settings
uint8_t RegOpMode; // 0x01
uint8_t RegRes02; // 0x02
uint8_t RegRes03; // 0x03
uint8_t RegBandSetting; // 0x04
uint8_t RegRes05; // 0x05
uint8_t RegFrfMsb; // 0x06
uint8_t RegFrfMid; // 0x07
uint8_t RegFrfLsb; // 0x08
// Tx settings
uint8_t RegPaConfig; // 0x09
uint8_t RegPaRamp; // 0x0A
uint8_t RegOcp; // 0x0B
// Rx settings
uint8_t RegLna; // 0x0C
// LoRa registers
uint8_t RegFifoAddrPtr; // 0x0D
uint8_t RegFifoTxBaseAddr; // 0x0E
uint8_t RegFifoRxBaseAddr; // 0x0F
uint8_t RegFifoRxCurrentAddr; // 0x10
uint8_t RegIrqFlagsMask; // 0x11
uint8_t RegIrqFlags; // 0x12
uint8_t RegNbRxBytes; // 0x13
uint8_t RegRxHeaderCntValueMsb; // 0x14
uint8_t RegRxHeaderCntValueLsb; // 0x15
uint8_t RegRxPacketCntValueMsb; // 0x16
uint8_t RegRxPacketCntValueLsb; // 0x17
uint8_t RegModemStat; // 0x18
uint8_t RegPktSnrValue; // 0x19
uint8_t RegPktRssiValue; // 0x1A
uint8_t RegRssiValue; // 0x1B
uint8_t RegHopChannel; // 0x1C
uint8_t RegModemConfig1; // 0x1D
uint8_t RegModemConfig2; // 0x1E
uint8_t RegSymbTimeoutLsb; // 0x1F
uint8_t RegPreambleMsb; // 0x20
uint8_t RegPreambleLsb; // 0x21
uint8_t RegPayloadLength; // 0x22
uint8_t RegMaxPayloadLength; // 0x23
uint8_t RegHopPeriod; // 0x24
uint8_t RegFifoRxByteAddr; // 0x25
uint8_t RegModemConfig3; // 0x26
uint8_t RegTestReserved27[0x30 - 0x27]; // 0x27-0x30
uint8_t RegTestReserved31; // 0x31
uint8_t RegTestReserved32[0x40 - 0x32]; // 0x32-0x40
// I/O settings
uint8_t RegDioMapping1; // 0x40
uint8_t RegDioMapping2; // 0x41
// Version
uint8_t RegVersion; // 0x42
// Additional settings
uint8_t RegAgcRef; // 0x43
uint8_t RegAgcThresh1; // 0x44
uint8_t RegAgcThresh2; // 0x45
uint8_t RegAgcThresh3; // 0x46
// Test
uint8_t RegTestReserved47[0x4B - 0x47]; // 0x47-0x4A
// Additional settings
uint8_t RegPllHop; // 0x4B
uint8_t RegTestReserved4C; // 0x4C
uint8_t RegPaDac; // 0x4D
// Test
//uint8_t RegTestReserved4E[0x58-0x4E]; // 0x4E-0x57
// Additional settings
//uint8_t RegTcxo; // 0x58
// Test
//uint8_t RegTestReserved59; // 0x59
// Test
//uint8_t RegTestReserved5B; // 0x5B
// Additional settings
//uint8_t RegPll; // 0x5C
// Test
//uint8_t RegTestReserved5D; // 0x5D
// Additional settings
//uint8_t RegPllLowPn; // 0x5E
// Test
//uint8_t RegTestReserved5F[0x6C - 0x5F]; // 0x5F-0x6B
// Additional settings
//uint8_t RegFormerTemp; // 0x6C
// Test
//uint8_t RegTestReserved6D[0x71 - 0x6D]; // 0x6D-0x70
}Sx1276RegType;
#define SIZE_OF_REGISTERS (sizeof(Sx1276RegType))
//RF state machine
typedef enum{
RFLR_STATE_IDLE,
RFLR_STATE_RX_RUNNING,
RFLR_STATE_TX_RUNNING,
}LRStateType;
typedef enum{
RADIO_RESET_OFF,
RADIO_RESET_ON,
}tRadioResetState;
typedef enum{
RF_IDLE,
RF_BUSY,
RF_RX_DONE,
RF_RX_TIMEOUT,
RF_TX_DONE,
RF_TX_TIMEOUT,
RF_LEN_ERROR,
RF_CHANNEL_EMPTY,
RF_CHANNEL_ACTIVITY_DETECTED,
}Sx1276RetType;
typedef enum{
SX1276_BW_7K8= (0),
SX1276_BW_10K4= (1<<4),
SX1276_BW_15K6= (2<<4),
SX1276_BW_20K8= (3<<4),
SX1276_BW_31K2= (4<<4),
SX1276_BW_41K6= (5<<4),
SX1276_BW_62K5= (6<<4),
SX1276_BW_125K= (7<<4),
SX1276_BW_250K= (8<<4),
SX1276_BW_500K= (9<<4)
}Sx1276BwType;
typedef enum{
SX1276_SF_64= (6<<4),
SX1276_SF_128= (7<<4),
SX1276_SF_256= (8<<4),
SX1276_SF_512= (9<<4),
SX1276_SF_1024= (10<<4),
SX1276_SF_2048= (11<<4),
SX1276_SF_4096= (12<<4)
}Sx1276SpreadFactorType;
typedef enum{
SX1276_EC_4_5= (1<<1),
SX1276_EC_4_6= (2<<1),
SX1276_EC_4_7= (3<<1),
SX1276_EC_4_8= (4<<1)
}Sx1276ErrorCodingType;
typedef enum{
SX1276_CRC_OFF= (0),
SX1276_CRC_ON= (1<<2)
}Sx1276CrcOnType;
typedef enum{
SX1276_IH_OFF= (0),
SX1276_IH_ON= (1)
}Sx1276ImplicitHeaderOnType;
//可变速率
typedef struct _AutoSfType{
Sx1276SpreadFactorType Sf;
uint8_t ucRssiMin, ucRssiMax;
uint16_t wTimeout;
}AutoSfType, *PAutoSf;
//Parameter
typedef enum{
LORAPT_STATUS,
LORAPT_CHANNEL,
LORAPT_FREQ,
LORAPT_BW,
LORAPT_SF,
LORAPT_EC,
LORAPT_RSSI,
LORAPT_POWER,
LORAPT_SET_RX,
LORAPT_SET_SLEEP,
LORAPT_MAX
}Sx1276LoraParaType;
#define SX1276_CHANNEL_MAX 17
#define LORA_RESET_SET() SET_LORA_RST()
#define LORA_RESET_CLR() CLR_LORA_RST()
#define LORA_SPI_NSS_SET() SET_LORA_NSS()
#define LORA_SPI_NSS_CLR() CLR_LORA_NSS()
#define LORA_SPI_READ_WRITE(x) SpiSendReceive(x)
#define LORA_GETDIO0() GET_LORA_DIO0()
#define LORA_GETDIO1() GET_LORA_DIO1()
#define USE_RF_SW 0
#define USE_LORA_LED 0
#if USE_RF_SW == 1
#define LORA_ANTTXEN() { \
SET_LORA_TXEN_PIN();\
CLR_LORA_RXEN_PIN();\
}
#define LORA_ANTRXEN() { \
SET_LORA_RXEN_PIN();\
CLR_LORA_TXEN_PIN();\
}
#define LORA_ANTCLOSE() { \
CLR_LORA_RXEN_PIN();\
CLR_LORA_TXEN_PIN();\
}
#else
#define LORA_ANTTXEN()
#define LORA_ANTRXEN()
#define LORA_ANTCLOSE()
#endif
#if USE_LORA_LED == 1
#define LORA_TXLED_ON() SET_LED_PIN()
#define LORA_TXLED_OFF() CLR_LED_PIN()
#else
#define LORA_TXLED_ON() SET_LORA_TX_LED()
#define LORA_TXLED_OFF() CLR_LORA_TX_LED()
#endif
#define LORA_BUFF_SIZE 255
typedef enum {
RF_ANT_TRANSMITTER,
RF_ANT_RECEIVER,
RF_ANT_CLOSE,
}Sx1276AntStatus_m;
typedef enum {
SX1276_SLEEP,
SX1276_IDLE,
SX1276_RX,
SX1276_TX,
SX1276_BUSY,
SX1276_ERROR,
SX1276_MAX
}Sx1276StateType_t;
typedef struct {
uint8_t ucChannel;
uint32_t dwFreqHz;
int8_t ucPower;
Sx1276BwType SignalBw;
Sx1276SpreadFactorType SpreadFactor;
Sx1276ErrorCodingType ErrorCoding;
uint8_t RegPreamble;
uint8_t ucOpModePrev;
Sx1276AntStatus_m bAntSwPrev;
Sx1276RegType RegBuff;
Sx1276StateType_t State;
uint8_t ucRxPacketSize;
uint8_t ucTxPacketSize;
uint8_t RxTxBuff[LORA_BUFF_SIZE];
void (*RxCallBack)(uint8_t *rBuff, uint8_t rlen);
}Sx1276Type_t, *pSx1276Type;
//ISM Freq In China
//Up Link:
//CH0-5: 470.3-471.3MHz
//CH39-44:478.1-479.1MHz
//CH78-95:485.9-489.3MHz
//Down Link:
//CH0-47:500.3-509.7MHz
#define USE_915MHZ 0//=1使用915 =0使用433
#if (USE_915MHZ == 1)
//中心频率，不定义则默认为449000000Hz
#define FREQ_CENT 915000000ul
//860MHz-1GHz使用PA功放，不定义则默认不使用
//SX127x不定义，HOPERF模块需要定义
#define USE_LORA_860_PA
#endif
#if !defined FREQ_CENT
#define FREQ_CENT (433100000ul+ 0)//125000
//#define FREQ_DEV 250000ul
#endif
#if !defined FREQ_DEV
//#define FREQ_CENT (449000000ul+ 0)//125000
#define FREQ_DEV 250000ul
#endif
//////////////////////////////////////////////////////////////////////
void Sx1276LoRaLoopHandler(void);
void Sx1276LoRaInit(void (*RxCallBack)(uint8_t *rBuff, uint8_t rlen));
void Sx1276LoRaSendBuffer(uint8_t* pucBuff, uint8_t ucLen);
uint8_t SX1276LoRaReadChannel(void);
bool SX1276LoRaWriteChannel(uint8_t Channel);
uint32_t SX1276LoRaReadFreq(void);
void SX1276LoRaWriteFreq(uint32_t Freq);
void SX1276LoRaWriteBw(Sx1276BwType SignalBw);
uint32_t SX1276LoRaReadBw(void);
uint8_t SX1276LoRaReadSf(void);
void SX1276LoRaWriteSf(Sx1276SpreadFactorType SpreadFactor);
void SX1276LoRaWriteEc(Sx1276ErrorCodingType ErrorCoding);
uint8_t SX1276LoRaReadEc(void);
uint32_t SX1276LoRaParaReadRssi(void);
uint8_t SX1276LoRaReadRssiPkt(void);
void SX1276LoRaWritePwr(int8_t Pwr);
void SX1276LoRaWriteRx(void);
void SX1276LoRaWriteSleep(bool Sleep);
Sx1276StateType_t SX1276LoRaReadStatus(void);
void SX1276LoCalcRssiSnr(int16_t *pswRssi, int8_t *psbSnr);
void Sx1276LoRaSleep(void);
void Sx1276LoRaWakeup(void);
#endif
Project/source/Module/dc_motor/dc_motor.c
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Project/source/Module/dc_motor/dc_motor.h
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#ifndef __DCMOTOR_H
#define __DCMOTOR_H
#define ADC_CH_NUM 3 /* 需要转换的通道数目 */
#define ADC_COLL 100 /* 单采集次数 */
#define ADC_SUM ADC_CH_NUM * ADC_COLL /* 总采集次数 */
#define HC32F170 (0u) //HC32F170JATA
#define HC32L170 (1u) //HC32L170JATA
#define HC32F460JETA (2u) //HC32F460JETA
#define MCU HC32F460JETA
#if(MCU == HC32F460JETA)
#include "hc32_ddl.h"
#define TIMER4 0
#define TIMER6 1
#define TIMER TIMER4 //HC32F460单片机PWM输出控制定时器选择
#endif
// 电机控制参数
#define PWM_PERIOD TIM_PERIOD // PWM周期值 (ARR)
#define MAX_SPEED 480 // 最大速度(PWM占空比)
#define ACCEL_STEP 10 // 加速步进值
#define DECEL_STEP 10 // 减速步进值
#define ACCEL_INTERVAL 10 // 加减速间隔(ms)
// 电机控制命令
typedef enum {
MOTOR_CMD_STOP,
MOTOR_CMD_FORWARD,
MOTOR_CMD_REVERSE
} MotorCommand;
// 电机运行状态机
typedef enum {
MOTOR_STOPPED,
MOTOR_ACCELERATING,
MOTOR_RUNNING,
MOTOR_DECELERATING
} MotorState;
// 电机转动方向
typedef enum {
DIR_STOPPED,
DIR_FORWARD,
DIR_REVERSE
} MotorDirection;
/************************************* 第一部分 电压电流温度采集 ******************************/
/* 电流计算公式：
* I=（最终输出电压-初始参考电压）/（6*0.02）A
* ADC值转换为电压值：电压=ADC值*3.3/4096，这里电压单位为V，我们换算成mV,4096/1000=4.096，后面就直接算出为mA
* 整合公式可以得出电流 I= （当前ADC值-初始参考ADC值）* （3.3 / 4.096 / 0.12）
*/
#define ADC2CURT (float)(3.3f / 4.096f / 0.12f)
/* 电压计算公式：
* V_POWER = V_BUS * 25
* ADC值转换为电压值：电压=ADC值*3.3/4096
* 整合公式可以得出电压V_POWER= ADC值 *（3.3f * 25 / 4096）
*/
#define ADC2VBUS (float)(3.3f * 25 / 4096)
/*****************************************************************************************************/
/* 停止引脚操作宏定义
* 此引脚控制H桥是否生效以达到开启和关闭电机的效果
*/
#define SHUTDOWN1_Pin Pin07
#define SHUTDOWN1_GPIO_Port PortB
//#define SHUTDOWN2_Pin GPIO_PIN_2
//#define SHUTDOWN2_GPIO_Port GPIOF
#define SHUTDOWN_GPIO_CLK_ENABLE() do{ __HAL_RCC_GPIOF_CLK_ENABLE(); }while(0) /* PF口时钟使能 */
#if(MCU == HC32F460JETA)
/* 电机停止引脚定义 这里默认是接口1 */
#define ENABLE_MOTOR PORT_SetBits(SHUTDOWN1_GPIO_Port,SHUTDOWN1_Pin)
#define DISABLE_MOTOR PORT_ResetBits(SHUTDOWN1_GPIO_Port,SHUTDOWN1_Pin)
#endif
/******************************************************************************************/
/* 编码器参数结构体 */
typedef struct
{
int encode_old; /* 上一次计数值 */
int encode_now; /* 当前计数值 */
float speed; /* 编码器速度 */
} ENCODE_TypeDef;
extern ENCODE_TypeDef g_encode; /* 编码器参数变量 */
/************************************* 第三部分 编码器测速 ****************************************************/
#define ROTO_RATIO 44 /* 线数*倍频系数，即11*4=44 */
#define REDUCTION_RATIO 30 /* 减速比30:1 */
/* 电机参数结构体 */
typedef struct
{
uint8_t state; /*电机状态*/
float current; /*电机电流*/
float volatage; /*电机电压*/
float power; /*电机功率*/
float speed; /*电机实际速度*/
float location; /*电机位置*/
int32_t motor_pwm; /*设置比较值大小 */
} Motor_TypeDef;
extern Motor_TypeDef g_motor_data; /*电机参数变量*/
/*********************************************************************************************************************/
void dcmotor_init(void); /* 直流有刷电机初始化 */
void dcmotor_start(void); /* 开启电机 */
void dcmotor_stop(void); /* 关闭电机 */
void dcmotor_dir(uint8_t para); /* 设置电机方向 */
void dcmotor_speed(uint16_t para); /* 设置电机速度 */
void motor_pwm_set(float para); /* 电机控制 */
float get_temp(uint16_t para);
void AdcLoopHander(void);
void Adc1mSRoutine(void);
void Adc_Init(void);
void calc_adc_val(uint16_t * p);
void Encoder (void);
//外部调用接口函数
MotorDirection Motor_GetDirection(void);/* 获取电机转动方向 */
void Motor_Control(MotorCommand cmd); /* 电机控制 */
void Dcmotor1msRoutine(void);
void DcmotorLoopHandler(void);
float get_current(void); /* 获取工作电流 */
float get_volatage(void); /* 获取工作电压 */
float get_Temperature(void); /* 获取工作温度 */
float get_speed(void); /* 获取电机转速 */
float get_location(void); /* 获取电机位置 */
#endif
Project/source/Module/mmc5983/.gitignore
+130
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# ---> uVision
# git ignore file for Keil µVision Project
# µVision 5 and µVision 4 Project screen layout file
*.uvguix.*
*.uvgui.*
# Listing Files
*.i
*.lst
*.m51
*.m66
*.map
# Object Files
*.axf
*.b[0-2][0-9]
*.b3[0-1]
*.bak
*.build_log.htm
*.crf
*.d
*.dep
*.elf
*.htm
*.iex
*.lnp
*.o
*.obj
*.sbr
# Firmware Files
*.bin
*.h86
*.hex
# Build Files
.bat
# Debugger Files
.ini
# JLink Files
JLinkLog.txt
# Other Files
# ---> VisualStudioCode
.vscode/*
!.vscode/settings.json
!.vscode/tasks.json
!.vscode/launch.json
!.vscode/extensions.json
!.vscode/*.code-snippets
# Local History for Visual Studio Code
.history/
# Built Visual Studio Code Extensions
*.vsix
# ---> IAR
# Compiled binaries
*.o
*.bin
*.elf
*.hex
*.map
*.out
*.obj
# Trash
*.bak
thumbs.db
*.~*
# IAR Settings
**/settings/*.crun
**/settings/*.dbgdt
**/settings/*.cspy
**/settings/*.cspy.*
**/settings/*.xcl
**/settings/*.dni
**/settings/*.wsdt
**/settings/*.wspos
# IAR Debug Exe
**/Exe/*.sim
# IAR Debug Obj
**/Obj/*.pbd
**/Obj/*.pbd.*
**/Obj/*.pbi
**/Obj/*.pbi.*
# IAR project "Debug" directory
Debug/
# IAR project "Release" directory
Release/
# IAR project settings directory
settings/
# IAR backup files
Backup*
# IAR .dep files
*.dep
# ---> IAR_EWARM
# gitignore template for the IAR EWARM
# website: https://www.iar.com/knowledge/support/technical-notes/ide/which-files-should-be-version-controlled/
# Some tools will put the EWARM files
# under a subdirectory with the same name
# as the configuration.
# Example
# EWARM/Config1/Obj /List /Exe
# EWARM/Config2/Obj /List /Exe
EWARM/**/Obj
EWARM/**/List
EWARM/**/Exe
# Autogenerated project files
*.dep
*.ewt
# Autogenerated folder for debugger
EWARM/settings
Project/source/Module/mmc5983/README.md
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@@ -0,0 +1,3 @@
# MMC5983
MMC5983驱动代码
Project/source/Module/mmc5983/mmc5983.c
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#include "main.h"
#include "mmc5983.h"
#include "UartDebug.h"
#include "i2c.h"
#include "Algorithm.h"
//test
static int32_t max_in[XYZ];
static int32_t min_in[XYZ];
static bool InitFlag;
static bool MMC5983IntFlag;
static MMC5983Var_t MMC5983Var;
/*****************************************************************************************
* 函数名称: MMC5983_Write_Reg
* 功能描述: MMC5983写寄存器
* 参 数: reg 寄存器地址
val 寄存器数据
* 返 回 值: 成功返回true，失败返回false
*****************************************************************************************/
static bool MMC5983_Write_Reg(uint8_t reg, uint8_t val)
{
return I2C_MasterWriteData(M0P_I2C0, MMC5983_ADDRESS, reg, &val, 1);
}
/*****************************************************************************************
* 函数名称: MMC5983_Read_Reg
* 功能描述: MMC5983读寄存器
* 参 数: reg 寄存器地址
* 返 回 值: 返回寄存器值
*****************************************************************************************/
static uint8_t MMC5983_Read_Reg(uint8_t reg)
{
uint8_t res;
if(I2C_MasterReadData(M0P_I2C0, MMC5983_ADDRESS, reg, &res, 1) == false)
res = 0;
return res;
}
/*****************************************************************************************
* 函数名称: MMC5983_Read_Buffer
* 功能描述: MMC5983读数据
* 参 数: reg 寄存器地址
buffer 读取数据输出缓存入口
len 读取长度
* 返 回 值: 成功返回true，失败返回false
*****************************************************************************************/
static bool MMC5983_Read_Buffer(uint8_t reg, void *buffer, uint8_t len)
{
return I2C_MasterReadData(M0P_I2C0, MMC5983_ADDRESS, reg, buffer, len);
}
/*****************************************************************************************
* 函数名称: MMC5983StartCov
* 功能描述: MMC5983开启连续转换
* 参 数: 无
* 返 回 值: 无
*****************************************************************************************/
static void MMC5983StartCov(void)
{
MMC5983RegCtrl2 Ctrl2Reg; //开启/关闭连续转换
Ctrl2Reg.Byte = 0x00;
Ctrl2Reg.Bit.Cm_freq = 0x04;
Ctrl2Reg.Bit.Cmm_en = 1; //连续设1，单次设0
Ctrl2Reg.Bit.Prd_set = 3;
Ctrl2Reg.Bit.En_prd_set = 1; //连续设1，单次设0
MMC5983_Write_Reg(MMC5983_CTRL_2, Ctrl2Reg.Byte);
}
/*****************************************************************************************
* 函数名称: MMC5983_Init
* 功能描述: MMC5983初始化
* 参 数: 无
* 返 回 值: 无
*****************************************************************************************/
static void MMC5983_Init(void)
{
uint8_t id;
id = MMC5983_Read_Reg(MMC5983_ID);
//DBG_LOG("MMC5983 id=0x%x\r\n",id);
MMC5983Var.MMC5983Delay1mSCnt = 100;
while(id != 0x30){
if(MMC5983Var.MMC5983Delay1mSCnt <= 0) {
DBG_LOG("LEFT MMC5983 INIT Err...\r\n");
InitFlag = false;
return;
}
}
MMC5983RegCtrl1 Ctrl1Reg;
Ctrl1Reg.Byte = 0x00;
Ctrl1Reg.Bit.SW_RST = 1;
MMC5983_Write_Reg(MMC5983_CTRL_1, Ctrl1Reg.Byte);
MMC5983Delay(15);
MMC5983RegCtrl2 Ctrl2Reg; //开启/关闭连续转换
Ctrl2Reg.Byte = 0x00;
Ctrl2Reg.Bit.Cm_freq = 0x04;
Ctrl2Reg.Bit.Cmm_en = 0; //连续设1，单次设0
Ctrl2Reg.Bit.Prd_set = 3;
Ctrl2Reg.Bit.En_prd_set = 0; //连续设1，单次设0
MMC5983_Write_Reg(MMC5983_CTRL_2, Ctrl2Reg.Byte);
MMC5983RegCtrl3 Ctrl3Reg;
Ctrl3Reg.Byte = 0x00;
Ctrl3Reg.Bit.St_enm = 1;
Ctrl3Reg.Bit.St_enp = 1;
MMC5983_Write_Reg(MMC5983_CTRL_3, Ctrl3Reg.Byte);
MMC5983RegCtrl0 Ctrl0Reg;
Ctrl0Reg.Byte = 0x00;
Ctrl0Reg.Bit.TM_M = 1;
Ctrl0Reg.Bit.Auto_SR_en = 1;
Ctrl0Reg.Bit.NT_meas_done_en = 1;
MMC5983_Write_Reg(MMC5983_CTRL_0, Ctrl0Reg.Byte);
if(InitFlag == false){
DBG_LOG("MMC5983 INIT OK...\r\n");
InitFlag = true;
}
}
/*****************************************************************************************
* 函数名称: MMC5983_Read
* 功能描述: MMC5983读取原始数据
* 参 数: MagAdcX X轴数据
MagAdcY Y轴数据
MagAdcZ Z轴数据
* 返 回 值: 成功返回true，失败返回false
*****************************************************************************************/
static bool MMC5983_Read(int32_t *MagAdcX, int32_t *MagAdcY, int32_t *MagAdcZ)
{
static uint8_t buff[7];
if (MMC5983_Read_Buffer(MMC5983_X_OUT_H, buff, 7) == false)
return false;
*MagAdcX = (buff[0] << 10) | (buff[1] << 2) | ((buff[6] & 0xC0) >> 6);
*MagAdcY = (buff[2] << 10) | (buff[3] << 2) | ((buff[6] & 0x30) >> 4);
*MagAdcZ = (buff[4] << 10) | (buff[5] << 2) | ((buff[6] & 0x0C) >> 2);// Turn the 18 bits into unsigned 32-bit value
return true;
}
/*****************************************************************************************
* 函数名称: MMC5983_Get_Mag
* 功能描述: 外部获取MMC5983磁场强度数据
* 参 数: mag 读取数据输出缓存入口
* 返 回 值: 无
*****************************************************************************************/
void MMC5983_Get_Mag(float *mag)
{
if(mag == NULL)
return;
float ADVal[XYZ];
ADVal[X] = MMC5983Var.Mag_Original[X] - 131072.0f;
ADVal[Y] = MMC5983Var.Mag_Original[Y] - 131072.0f;
ADVal[Z] = MMC5983Var.Mag_Original[Z] - 131072.0f;
mag[0] = (float) (ADVal[X] * MMC5983_MAG_SCALE_18BIT);
mag[1] = (float) (ADVal[Y] * MMC5983_MAG_SCALE_18BIT);
mag[2] = (float) (ADVal[Z] * MMC5983_MAG_SCALE_18BIT);
}
/*****************************************************************************************
* 函数名称: MMC5983LoopHandler
* 功能描述: MMC5983循环处理函数
* 参 数: 无
* 返 回 值: 无
*****************************************************************************************/
extern void MmcDataProcessCallBack(float *Mag);
void MMC5983LoopHandler(void)
{
static int32_t mag_array[XYZ][10];
static uint8_t magcnt;
static uint8_t TimeOutMagcnt;
switch(MMC5983Var.Status) {
case MMC5983_STATUS_IDLE:{
break;}
case MMC5983_STATUS_START:{
for(int i = 0; i < 10; i++) {
mag_array[X][i] = 0;
mag_array[Y][i] = 0;
mag_array[Z][i] = 0;
}
magcnt = 0;
TimeOutMagcnt = 0;
memset(&MMC5983Var, NULL, sizeof(MMC5983Var));
MMC5983Var.Status = MMC5983_STATUS_DELAY;
break;}
case MMC5983_STATUS_DELAY:{
MMC5983StartRead();
MMC5983Var.MMC5983Delay1mSCnt = 50;
MMC5983Var.Status = MMC5983_STATUS_WAIT_DELAY;
break;}
case MMC5983_STATUS_WAIT_DELAY:{
if(MMC5983Var.MMC5983Delay1mSCnt <= 0){
MMC5983Var.Status = MMC5983_STATUS_READ;
}
break;}
case MMC5983_STATUS_READ:{
MMC5983Var.MMC5983Delay1mSCnt = 50;
MMC5983Var.Status = MMC5983_STATUS_WAIT_READ;
break;}
case MMC5983_STATUS_WAIT_READ:{
if(MMC5983Var.MMC5983Delay1mSCnt <= 0){
MMC5983Var.Status = MMC5983_STATUS_DELAY;
TimeOutMagcnt++;
}
if(MMC5983IntFlag == true){
MMC5983IntFlag = false;
MMC5983_Read(&mag_array[X][magcnt], &mag_array[Y][magcnt], &mag_array[Z][magcnt]);
magcnt++;
MMC5983Var.Status = MMC5983_STATUS_DELAY;
}
if(TimeOutMagcnt >= 10){
TimeOutMagcnt = 0;
if(magcnt > 0){
MMC5983Var.Mag_Original[X] = AverageFilter_32t(mag_array[X], magcnt);
MMC5983Var.Mag_Original[Y] = AverageFilter_32t(mag_array[Y], magcnt);
MMC5983Var.Mag_Original[Z] = AverageFilter_32t(mag_array[Z], magcnt);
magcnt = 0;
MMC5983_Get_Mag(MMC5983Var.Mag);
MmcDataProcessCallBack(MMC5983Var.Mag);
MMC5983Var.Status = MMC5983_STATUS_STOP;
}
else{
MMC5983Var.Status = MMC5983_STATUS_STOP;
// DBG_LOG("LEFT MMC5983 TimeOut...\r\n");
}
}
if(magcnt >= 10){
MMC5983Var.Mag_Original[X] = AverageFilter_32t(mag_array[X], magcnt);
MMC5983Var.Mag_Original[Y] = AverageFilter_32t(mag_array[Y], magcnt);
MMC5983Var.Mag_Original[Z] = AverageFilter_32t(mag_array[Z], magcnt);
magcnt = 0;
MMC5983_Get_Mag(MMC5983Var.Mag);
MmcDataProcessCallBack(MMC5983Var.Mag);
MMC5983Var.Status = MMC5983_STATUS_STOP;
}
break;}
case MMC5983_STATUS_STOP:{
MMC5983Stop();
MMC5983Var.Status = MMC5983_STATUS_IDLE;
//MMC5983Var.Status = MMC5983_STATUS_START;//持续工作
break;}
}
}
/*****************************************************************************************
* 函数名称: LeftMMC59831mSRoutine
* 功能描述: MMC59831ms时基循环处理函数
* 参 数: 无
* 返 回 值: 无
*****************************************************************************************/
void MMC59831mSRoutine(void)
{
if(MMC5983Var.MMC5983Delay1mSCnt > 0)
MMC5983Var.MMC5983Delay1mSCnt--;
}
/*****************************************************************************************
* 函数名称: LeftMMC5983Init
* 功能描述: MMC5983初始化
* 参 数: 无
* 返 回 值: 无
*****************************************************************************************/
void MMC5983Init(void)
{
if(!InitFlag){
MMC5983_Init();
return;
}
MMC5983Var.Status = MMC5983_STATUS_START;
}
/*****************************************************************************************
* 函数名称: LeftMMC5983Start
* 功能描述: MMC5983启动
* 参 数: 无
* 返 回 值: 无
*****************************************************************************************/
void MMC5983Start(void)
{
if(!InitFlag){
MMC5983_Init();
return;
}
MMC5983Var.Status = MMC5983_STATUS_START;
}
/*****************************************************************************************
* 函数名称: LeftMMC5983StartRead
* 功能描述: MMC5983启动读取
* 参 数: 无
* 返 回 值: 无
*****************************************************************************************/
void MMC5983StartRead(void)
{
MMC5983_Init();//读取时重新初始化
}
/*****************************************************************************************
* 函数名称: MMC5983Stop
* 功能描述: MMC5983停止
* 参 数: 无
* 返 回 值: 无
*****************************************************************************************/
void MMC5983Stop(void)
{
MMC5983RegCtrl0 Ctrl0Reg;
Ctrl0Reg.Byte = 0x00;
MMC5983_Write_Reg(MMC5983_CTRL_0, Ctrl0Reg.Byte);
MMC5983RegStatus StatusReg;
StatusReg.Byte = MMC5983_Read_Reg(MMC5983_STATUS);
if(StatusReg.Bit.Meas_M_Done == 1){
MMC5983_Write_Reg(MMC5983_STATUS, StatusReg.Byte);
}
}
/*****************************************************************************************
* 函数名称: LeftMMC5983IntCallBack
* 功能描述: MMC5983中断回调
* 参 数: 无
* 返 回 值: 无
*****************************************************************************************/
void MMC5983IntCallBack(void)
{
MMC5983IntFlag = true;
}
Project/source/Module/mmc5983/mmc5983.h
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/**
*****************************************************************************
* @file ak8975.h
* @author WWJ
* @version v1.0
* @date 2019/04/09
* @environment stm32f407
* @brief
*****************************************************************************
**/
#ifndef _MMC5983_H
#define _MMC5983_H
#include "bsp.h"
#define X 0
#define Y 1
#define Z 2
#define XYZ 3
#define MAX(A, B) (A > B) ? A : B;
#define MIN(A, B) (A < B) ? A : B;
#define MMC5983_X_OUT_H 0X00 //Device ID = 0x48
#define MMC5983_X_OUT_L 0X01
#define MMC5983_Y_OUT_H 0X02
#define MMC5983_Y_OUT_L 0X03
#define MMC5983_Z_OUT_H 0X04
#define MMC5983_Z_OUT_L 0X05
#define MMC5983_XYZ_OUT 0X06
#define MMC5983_TMP_OUT 0X07
#define MMC5983_STATUS 0X08
#define MMC5983_CTRL_0 0X09
#define MMC5983_CTRL_1 0X0A
#define MMC5983_CTRL_2 0X0B
#define MMC5983_CTRL_3 0X0C
#define MMC5983_ID 0X2F
#define MMC5983_ADDRESS 0x30
#define MMC5983_MAG_SCALE_16BIT 0.24414f
#define MMC5983_MAG_SCALE_18BIT 0.061035f
#define MMC5983Delay(x) delay_ms(x)
typedef union {
struct {
uint8_t Meas_M_Done: 1;
uint8_t Meas_T_Done: 1;
uint8_t Res0: 2;
uint8_t OTP_Read_Done: 1;
uint8_t Res1: 3;
}Bit;
uint8_t Byte;
}MMC5983RegStatus;
typedef union {
struct {
uint8_t TM_M: 1;
uint8_t TM_T: 1;
uint8_t NT_meas_done_en: 1;
uint8_t Set: 1;
uint8_t Reset: 1;
uint8_t Auto_SR_en: 1;
uint8_t OTP_Read: 1;
uint8_t Res0: 1;
}Bit;
uint8_t Byte;
}MMC5983RegCtrl0;
typedef union {
struct {
uint8_t BW: 2;
uint8_t X_Inhibit: 1;
uint8_t YZ_Inhibit: 2;
uint8_t Res0: 2;
uint8_t SW_RST: 1;
}Bit;
uint8_t Byte;
}MMC5983RegCtrl1;
typedef union {
struct {
uint8_t Cm_freq: 3;
uint8_t Cmm_en: 1;
uint8_t Prd_set: 3;
uint8_t En_prd_set: 1;
}Bit;
uint8_t Byte;
}MMC5983RegCtrl2;
typedef union {
struct {
uint8_t Res0: 1;
uint8_t St_enp: 1;
uint8_t St_enm: 1;
uint8_t Res1: 3;
uint8_t Spi_3w: 1;
uint8_t Res2: 1;
}Bit;
uint8_t Byte;
}MMC5983RegCtrl3;
typedef enum{
MMC5983_STATUS_IDLE,
MMC5983_STATUS_START,
MMC5983_STATUS_DELAY,
MMC5983_STATUS_WAIT_DELAY,
MMC5983_STATUS_READ,
MMC5983_STATUS_WAIT_READ,
MMC5983_STATUS_STOP,
}MMC5983Status_m;
typedef struct {
MMC5983Status_m Status;
uint16_t MMC5983Delay1mSCnt;
float Mag[3];
int32_t Mag_Original[XYZ];
}MMC5983Var_t;
void MMC5983LoopHandler(void);
void MMC59831mSRoutine(void);
void MMC5983Init(void);
void MMC5983Start(void);
void MMC5983Stop(void);
void MMC5983IntCallBack(void);
void MMC5983Calib(void);
void MMC5983GetADValue(int32_t *Mag);
void MMC5983_Get_Mag(float *mag);
MMC5983Status_m GetMMC5983Status(void);
void MMC5983StartRead(void);
bool GetMMC5983CalibStatus(void);
#endif
/* end of ak8975.h */