chore: 更新子模块指针到最新提交

chore: 清理废弃模块代码
chore: 更新 Gateway_Debug 子模块到最新提交
2026-06-22 11:41:32 +08:00 · 2026-06-22 10:11:33 +08:00 · 2026-06-17 17:47:38 +08:00 · 2026-06-17 17:46:33 +08:00 · 2026-06-17 12:33:11 +08:00 · 2026-06-17 12:30:57 +08:00
168 changed files with 96240 additions and 1 deletions
@@ -0,0 +1,12 @@
+[submodule "Project/GateWay/source/Module/sx127x"]
+	path = Project/GateWay/source/Module/sx127x
+	url = http://192.168.2.47:8418/YuanHongbin/sx127x.git
+[submodule "Project/GateWay/source/Module/FatFS"]
+	path = Project/GateWay/source/Module/FatFS
+	url = http://192.168.2.47:8418/YuanHongbin/FatFS.git
+[submodule "Project/GateWay/source/Module/SDCard"]
+	path = Project/GateWay/source/Module/SDCard
+	url = http://192.168.2.47:8418/YuanHongbin/SDCard.git
+[submodule "Project/GateWay/source/Module/GateWay_Debug"]
+	path = Project/GateWay/source/Module/GateWay_Debug
+	url = http://192.168.2.47:8418/YuanHongbin/GateWay_Debug.git
@@ -0,0 +1,88 @@
+---
+name: add-debug-command
+description: 在 GateWay_Debug 模块中添加新的 Debug 调试命令（函数指针表 + 字符串匹配模式）
+source: auto-skill
+extracted_at: '2026-06-15T08:10:31.194Z'
+---
+
+# 添加 Debug 调试命令
+
+本项目的 Debug 命令系统位于 `Project/GateWay/source/Module/GateWay_Debug/DebugCmd.c`，采用**函数指针表 + 字符串匹配**模式。
+
+## 修改步骤
+
+### 1. 编写 handler 函数
+
+在 `DebugCmd.c` 中添加函数，签名固定为 `void FuncName(int argc, char *argv[])`：
+
+```c
+static void DebugCmdXxx(int argc, char *argv[])
+{
+    DBG_LOG("\r\n");
+    if(strcmp(argv[1], "?") == 0) {
+        DBG_LOG("Debug Cmd: xxx\r\n");
+        DBG_LOG("  brief --> 功能描述.\r\n\r\n");
+        return;
+    }
+    // 实际逻辑...
+}
+```
+
+**必须遵循的模式：**
+- 函数体第一行：`DBG_LOG("\r\n");`
+- `"?"` 帮助分支：打印命令名和 brief 说明
+- 若修改了 `ConfigPara`，调用 `WritePara()` 保存
+- 需要被外部引用时声明为 `void`，仅内部使用时声明为 `static void`
+
+### 2. 注册到命令表
+
+在文件末尾的 `DebugFun[]` 常量数组中添加一行：
+
+```c
+const DBGFunType DebugFun[DEBUG_CMD_CNT] = {
+    // ... 已有命令 ...
+    "xxx",              DebugCmdXxx,
+};
+```
+
+**容量限制：** `DEBUG_CMD_CNT = 30`，添加前检查剩余空位（当前使用 28/30）。若超出需增大该宏。
+
+### 3. 添加到 help 输出
+
+在 `DebugCmdHelp` 函数末尾添加：
+
+```c
+len = strlen("xxx ?\r\n");
+memcpy(Data, "xxx ?\r\n", len);
+DebugAnalyze(GateWay, Data, len);
+```
+
+## 可用的关键 API
+
+| 函数 | 头文件 | 用途 |
+|---|---|---|
+| `CatOneEthSendQueue(data, len)` | CatOneTask.h | 将载荷放入网络发送队列（需 `SvrRegFlag == true`） |
+| `CommUintOrgData(GateWay, CUPara, CUData, buf)` | Public.h | 组装通讯单元传感器数据包 |
+| `GateWayRegister(TxBuff)` | CatOneTask.h | 组装网关注册包，返回长度 |
+| `NetCommOrgData(GateWay, payload, outBuf)` | Public.h | 为载荷添加网络帧头(0x7A)+MAC+CRC |
+| `WritePara(data, len)` | (bsp) | 保存配置参数到 Flash |
+| `CatOneTriggerRegister()` | CatOneTask.h | 将 Cat1 状态机立即切换到注册状态 |
+| `ETHTriggerRegister()` | CatOneTask.h | 将以太网状态机立即切换到注册状态 |
+
+## 可用的全局/extern 变量
+
+| 变量 | 类型 | 来源 |
+|---|---|---|
+| `GateWay` | `static GateWayPara` | DebugCmd.c 内静态指针，指向网关参数 |
+| `SComm1Para` / `SComm2Para` | `SensorCommPara_t` | RS485Task.c 中定义，DebugCmd.c 已 extern |
+| `GateWay->SvrRegFlag` | `bool` | 服务器注册状态 |
+| `GateWay->ConfigPara` | `GWConfigPara_t` | 网关配置参数 |
+
+## 注意事项
+
+- `CatOne_t CatOne` 和 `CatOneEthTxBuff[]` 均为 CatOneTask.c 中的 **static** 变量，不能直接在 DebugCmd.c 中访问；应使用封装好的接口函数（如 `CatOneTriggerRegister()`、`ETHTriggerRegister()`）来操作状态机
+- 重新注册应：清 `GateWay->SvrRegFlag = false`，然后根据通信模式调用 `CatOneTriggerRegister()` 或 `ETHTriggerRegister()` 立即切换状态机到注册状态，而不是仅清标志位等待状态机自动检测
+- `CatOneEthSendQueue` 内部检查 `SvrRegFlag`，未注册时返回 `false`
+- 命令解析函数 `DebugAnalyze` 按 `" "` 分割参数，去除 `\r`，最多 10 个参数
+- `DEBUG_CMD_CNT = 30` 为命令容量上限，添加新命令前需检查当前使用量，若超出需将此宏增大（如改为31）
+- 若模块需要保存独立的配置参数（如YOXO1007网络参数），可在DebugCmd.c中定义static变量，并通过Flash读写函数持久化（参考`EthNetPara_t`和`WriteEthNetPara`的实现）
@@ -0,0 +1,57 @@
+---
+name: fix-yoxo1007-receive-data
+description: 修复YOXO1007以太网模块接收数据解析错误问题
+source: auto-skill
+extracted_at: '2026-06-17T04:30:00.000Z'
+---
+
+# 修复 YOXO1007 以太网模块接收数据解析错误
+
+## 问题现象
+
+服务器已收到网关注册请求并响应，但网关端无法接收/解析服务器返回的数据。
+
+## 根本原因
+
+YOXO1007 模块在**透传模式**下发送的是**原始二进制数据**，不是 ASCII 格式的 hex 字符串。
+
+原代码错误地使用了 `AsciiToHex` 函数进行格式转换：
+
+```c
+// 错误代码 - CATONE 模式使用的 ASCII 转换不适用于 ETH 透传模式
+memset(HexData, 0x00, CatOneEthRxLen / 2);
+uint8_t ret = AsciiToHex(RxBuffTemp, HexData, CatOneEthRxLen);
+if(ret > 0)
+    GateWay->SvrRevCallBack(GateWay, HexData, ret);
+```
+
+这导致服务器返回的二进制数据被错误解析，回调函数无法正确处理。
+
+## 修复方案
+
+修改 `CatOneTask.c` 中 ETH 接收线程的数据处理逻辑，直接传递原始二进制数据：
+
+```c
+// 修改后的正确代码
+CAT1_DBG_LOG("Eth Rev: len=%d\r\n", CatOneEthRxLen);
+/* YOXO1007模块在透传模式下发送原始二进制数据,直接传递 */
+if(CatOneEthRxLen > 0)
+    GateWay->SvrRevCallBack(GateWay, (uint8_t *)CatOneEthRxBuff, CatOneEthRxLen);
+```
+
+## 修改位置
+
+`Project/GateWay/source/User/Src/CatOneTask.c` 中的 `CatOneRev_Thread_Entry` 函数内的 ETH 分支。
+
+## 关键区别
+
+| 模式 | 数据格式 | 解析方式 |
+|------|----------|----------|
+| CAT1 (4G) | ASCII 字符串 (AT 命令/响应) | 需要 AsciiToHex 转换 |
+| ETH (YOXO1007) | 原始二进制 (透传模式) | 直接传递，不转换 |
+
+## 注意事项
+
+- 此修改仅影响 ETH 通信模式，CAT1 模式的 ASCII 解析逻辑保持不变
+- YOXO1007 模块配置参数使用二进制命令协议（识别流 ED F2 A3 56...），与数据透传是不同层面
+- 模块配置保存后重启会自动进入之前保存的工作模式，无需额外进入透传模式的命令
@@ -0,0 +1,79 @@
+---
+name: git-branch-cleanup
+description: 批量删除/重命名本地和远端 Git 分支，并同步远端仓库结构（含中文分支名、upstream 修复）
+source: auto-skill
+extracted_at: '2026-06-17T10:06:37.947Z'
+---
+
+# Git 分支批量清理与重命名
+
+## 适用场景
+需要删除多余的本地/远端分支、将分支重命名、并让远端结构与本地保持一致。
+
+## 操作流程
+
+### 1. 切换到安全分支
+```bash
+# 先 stash 未提交的更改
+git stash --include-untracked
+
+# 如果有 untracked 文件冲突，使用 -f 强制切换
+git checkout -f master
+```
+
+> **坑点**：中文分支名之间的文件差异可能产生大量 untracked 冲突（如 FatFS 文档等），
+> `git checkout` 会拒绝切换，需要 `-f` 强制切换，之后 `git stash pop` 恢复。
+
+### 2. 删除本地分支
+```bash
+git branch -D "LAN口通讯"
+git branch -D "新版4G模块1"
+```
+
+### 3. 重命名本地分支
+```bash
+git branch -m "旧版4G模块" develop
+```
+
+### 4. 删除远端分支（每个远端都要操作）
+```bash
+# 一次性删除多个远端分支
+git push home --delete "LAN口通讯" "新版4G模块" "旧版4G模块"
+git push origin --delete "LAN口通讯" "新版4G模块" "旧版4G模块"
+```
+
+> **注意**：远端可能认证失败（如内网地址不可达），先确认网络可达再操作。
+> 远端分支名可能与本地不完全一致（本地有 `新版4G模块1`，远端只有 `新版4G模块`）。
+
+### 5. 强制推送重命名后的分支到远端
+```bash
+git push home develop --force
+git push origin develop --force
+```
+
+### 6. 修复上游跟踪分支
+重命名后，分支仍跟踪旧的远端名（如 `origin/旧版4G模块`，已不存在）：
+```bash
+git branch --set-upstream-to=origin/develop develop
+```
+
+### 7. 恢复工作内容并切回开发分支
+```bash
+git checkout develop
+git stash pop
+```
+
+### 8. 验证最终结构
+```bash
+git fetch --all --prune
+git branch -a
+```
+
+## 常见问题
+
+| 问题 | 解决方案 |
+|------|----------|
+| checkout 报 untracked files 冲突 | `git checkout -f <branch>` |
+| 远端认证失败 | 检查网络/VPN，确认远端地址可达 |
+| 重命名后 upstream 指向已删除的远端分支 | `git branch --set-upstream-to=origin/<new-name> <branch>` |
+| 中文分支名在命令行中需加引号 | `git branch -D "旧版4G模块"` |
@@ -0,0 +1,314 @@
+$PACKAGES
+bq25306rter ! bq25306rter ! '{Value}' ; U2 
+c0402m ! c0402m ! 100nF ; C9 C28 C41 
+c0402m ! c0402m ! 100pF ; C11 C42 C43 
+c0402m ! c0402m ! 10nF ; C10 
+c0402m ! c0402m ! 33pF ; C29 C30 C31 C32 
+C0603 ! C0603 ! '2.2uF' ; C59 C60 C68 
+C0603 ! C0603 ! '4.7uF' ; C65 
+C0603 ! C0603 ! 100nF ; C1 C3 C5 C15 C16 C19 C21 C23 C25 C26 C34 C36 C38 C40 ,
+        C44 C46 C48 C50 C52 C53 C54 C56 C61 C63 C64 C66 C70 C71 C76 C78 C79 ,
+        C80 C83 C84 C85 C86 
+C0603 ! C0603 ! 10uF ; C27 C55 C57 C62 
+C0603 ! C0603 ! 15pF ; C73 C77 
+C0603 ! C0603 ! 1uF ; C69 C72 C75 
+C0603 ! C0603 ! 22pF ; C67 C74 C81 C82 
+C0603 ! C0603 ! 22uF ; C58 
+C0603 ! C0603 ! 470pF ; C17 
+C0603 ! C0603 ! 47nF ; C4 
+C0805 ! C0805 ! '2.2uF' ; C13 
+C0805 ! C0805 ! 10nF ; C24 
+C0805 ! C0805 ! 22uF ; C2 C8 C12 C18 C20 C33 C35 C39 C45 C47 C49 C51 
+C1206 ! C1206 ! 22uF ; C14 C37 
+CAP-SMD_BD6.3-L6.6-W6.6-FD ! CAP-SMD_BD6.3-L6.6-W6.6-FD ! 470uF ; C6 C7 
+CAP-SMD_BD6.3-L6.6-W6.6-LS7.3-FD ! CAP-SMD_BD6.3-L6.6-W6.6-LS7.3-FD ! 220uF ; ,
+        C22 
+CONN-TH_2P-P2.50_HX25003-2A ! CONN-TH_2P-P2.50_HX25003-2A ! '{Value}' ; CN1 
+CONN-TH_2P-P3.81_L7.4-W7.6 ! CONN-TH_2P-P3.81_L7.4-W7.6 ! '{Value}' ; U1 U9 ,
+        U11 U13 U15 
+,
+        CONN-TH_3P-P2.00_HCTL_PH-3A_C2908624 ! CONN-TH_3P-P2.00_HCTL_PH-3A_C2908624 ! '{Value}' ,
+        ; CN3 
+CONN-TH_4P-P2.00_PH-4A_C2908625 ! CONN-TH_4P-P2.00_PH-4A_C2908625 ! '{Value}' ,
+        ; H4 
+,
+        CONN-TH_7P-P1.25_HCTL_HC-1.25-7A ! CONN-TH_7P-P1.25_HCTL_HC-1.25-7A ! '{Value}' ,
+        ; CN2 
+CONN-TH_PH-2A_C2908623 ! CONN-TH_PH-2A_C2908623 ! '{Value}' ; H1 
+CRYSTAL-SMD_4P-L3.2-W2.5-BL-2 ! CRYSTAL-SMD_4P-L3.2-W2.5-BL-2 ! '{Value}' ; ,
+        U21 
+DO-214AC_L4.3-W2.4-LS4.7-RD ! DO-214AC_L4.3-W2.4-LS4.7-RD ! '{Value}' ; D1 
+E32-400M30S ! E32-400M30S ! '{Value}' ; U12 
+,
+        ESOP-8_L4.9-W3.9-P1.27-LS6.0-TL-EP ! ESOP-8_L4.9-W3.9-P1.27-LS6.0-TL-EP ! '{Value}' ,
+        ; U4 
+FC-135R_L3.2-W1.5 ! FC-135R_L3.2-W1.5 ! '32.768kHz' ; X1 
+HDR-TH_2P-P2.54-V-M ! HDR-TH_2P-P2.54-V-M ! '{Value}' ; H5 
+HDR-TH_3P-P2.54-V-M ! HDR-TH_3P-P2.54-V-M ! '{Value}' ; H2 H3 
+IND-SMD_L2.5-W2.0_AHP252010TF ! IND-SMD_L2.5-W2.0_AHP252010TF ! 10uH ; L2 L4 
+IND-SMD_L4.8-W4.5 ! IND-SMD_L4.8-W4.5 ! '2.2uH' ; L1 
+IND-SMD_L7.0-W6.6_FXL0630 ! IND-SMD_L7.0-W6.6_FXL0630 ! 15uH ; L3 L5 
+IPEX-SMD_BWIPX-1-001E ! IPEX-SMD_BWIPX-1-001E ! '{Value}' ; RF1 
+L0603 ! L0603 ! '{Value}' ; L6 
+LED0603-FD_BLUE ! LED0603-FD_BLUE ! '{Value}' ; LORA 
+LED0603-RD ! LED0603-RD ! '{Value}' ; LAN LED1 
+,
+        LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL ! LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL ! '{Value}' ,
+        ; U20 
+NANO-SIM-SMD_SMN-305-ARP7 ! NANO-SIM-SMD_SMN-305-ARP7 ! '{Value}' ; CARD1 
+NT26E ! NT26E ! '{Value}' ; U19 
+OSC-SMD_4P-L3.2-W2.5-BL ! OSC-SMD_4P-L3.2-W2.5-BL ! 16MHz ; X2 
+,
+        QFN-48_L5.0-W5.0-P0.35-EP3.7_UC8288 ! QFN-48_L5.0-W5.0-P0.35-EP3.7_UC8288 ! '{Value}' ,
+        ; U17 
+R0402 ! R0402 ! '100kΩ' ; R5 R34 R41 R42 R44 
+R0402 ! R0402 ! '10kΩ' ; R2 R15 R23 R35 R37 R38 R39 R40 R43 R45 R55 R75 
+R0402 ! R0402 ! '1kΩ' ; R18 
+R0402 ! R0402 ! '22Ω' ; R25 R26 R30 
+R0603 ! R0603 ! '100kΩ' ; R13 R19 R57 R72 
+R0603 ! R0603 ! '100Ω' ; R56 
+R0603 ! R0603 ! '10kΩ' ; R10 R11 R14 R47 R50 R51 R54 R59 R63 R64 R65 R66 R67 ,
+        R68 
+R0603 ! R0603 ! '120kΩ' ; R73 
+R0603 ! R0603 ! '120Ω' ; R49 R52 
+R0603 ! R0603 ! '12kΩ' ; R22 R36 
+R0603 ! R0603 ! '169kΩ' ; R7 R28 
+R0603 ! R0603 ! '1kΩ' ; R1 R4 R8 R12 R29 R58 R69 R70 R74 
+R0603 ! R0603 ! '1MΩ' ; R17 
+R0603 ! R0603 ! '2.7kΩ' ; R61 
+R0603 ! R0603 ! '200kΩ' ; R16 R71 
+R0603 ! R0603 ! '24kΩ' ; R46 
+R0603 ! R0603 ! '3.24kΩ' ; R31 
+R0603 ! R0603 ! '3.3kΩ' ; R6 R21 
+R0603 ! R0603 ! '30kΩ' ; R3 
+R0603 ! R0603 ! '330kΩ' ; R20 
+R0603 ! R0603 ! '4.7kΩ' ; R60 R62 
+R0603 ! R0603 ! '64kΩ' ; R9 R27 
+R0805 ! R0805 ! '100kΩ' ; R53 
+R0805 ! R0805 ! '10kΩ' ; R24 R33 
+R0805 ! R0805 ! '1kΩ' ; R48 
+R0805 ! R0805 ! '20kΩ' ; R32 
+RJ45-TH_HR915310A ! RJ45-TH_HR915310A ! '{Value}' ; D7 
+,
+        SC-70-6_L2.2-W1.3-P0.65-LS2.1-BL ! SC-70-6_L2.2-W1.3-P0.65-LS2.1-BL ! '{Value}' ,
+        ; U22 U23 
+SMA_L4.3-W2.6-LS5.1-RD ! SMA_L4.3-W2.6-LS5.1-RD ! '{Value}' ; D3 D4 
+SOIC-8_L5.0-W4.0-P1.27-LS6.0-BL ! SOIC-8_L5.0-W4.0-P1.27-LS6.0-BL ! '{Value}' ,
+        ; U10 U14 
+SOIC-8_L5.3-W5.3-P1.27-LS8.0-BL ! SOIC-8_L5.3-W5.3-P1.27-LS8.0-BL ! '{Value}' ,
+        ; U18 
+,
+        SOT-223-3_L6.5-W3.4-P2.30-LS7.0-BR ! SOT-223-3_L6.5-W3.4-P2.30-LS7.0-BR ! '{Value}' ,
+        ; U8 
+SOT-23 ! SOT-23 ! '{Value}' ; D5 D6 
+SOT-23_L2.9-W1.3-P1.90-LS2.4-BR ! SOT-23_L2.9-W1.3-P1.90-LS2.4-BR ! '{Value}' ,
+        ; Q1 Q2 Q3 Q4 Q7 Q15 Q17 
+,
+        SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR ! SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR ! '{Value}' ,
+        ; Q5 Q11 Q19 
+,
+        SOT-23-3_L2.9-W1.6-P1.90-LS2.8-BR ! SOT-23-3_L2.9-W1.6-P1.90-LS2.8-BR ! '{Value}' ,
+        ; Q6 
+,
+        SOT-23-3_L3.0-W1.7-P0.95-LS2.9-BR ! SOT-23-3_L3.0-W1.7-P0.95-LS2.9-BR ! '{Value}' ,
+        ; Q18 
+sot-23-3p ! sot-23-3p ! '{Value}' ; Q8 Q9 Q10 Q12 Q13 Q14 
+,
+        SOT-23-6_L2.9-W1.6-P0.95-LS2.8-BL ! SOT-23-6_L2.9-W1.6-P0.95-LS2.8-BL ! '{Value}' ,
+        ; U3 U6 
+,
+        SOT-23-6_L2.9-W1.6-P0.95-LS2.8-BR ! SOT-23-6_L2.9-W1.6-P0.95-LS2.8-BR ! '{Value}' ,
+        ; U7 
+,
+        SOT-363_L2.0-W1.3-P0.65-LS2.1-BR ! SOT-363_L2.0-W1.3-P0.65-LS2.1-BR ! '{Value}' ,
+        ; D2 
+SOT323-6L_L2.0-W1.3-LS2.1-BL ! SOT323-6L_L2.0-W1.3-LS2.1-BL ! '{Value}' ; U16 
+TF-SMD_XKTF-1307-18 ! TF-SMD_XKTF-1307-18 ! '{Value}' ; CARD2 
+,
+        TO-263-5_L10.2-W9.9-P1.70-LS14.4-TL ! TO-263-5_L10.2-W9.9-P1.70-LS14.4-TL ! '{Value}' ,
+        ; U5 
+$A_PROPERTIES
+$NETS
+'$1N14156' ; R32.1 R33.1 U5.5 
+'$1N15120' ; C16.2 L2.1 U3.6 
+'$1N15124' ; C16.1 U3.1 
+'$1N156972' ; R61.2 U20.55 
+'$1N157217' ; LORA.2 R61.1 
+'$1N219298' ; Q3.1 R6.2 
+'$1N219301' ; Q7.1 R21.2 
+'$1N219303' ; Q6.3 R8.1 R19.2 
+'$1N219304' ; D1.1 R1.1 R10.1 
+'$1N219315' ; Q4.1 R8.2 
+'$1N219322' ; R11.2 R14.2 U2.7 
+'$1N219324' ; R16.2 U2.8 
+'$1N219325' ; C17.1 R16.1 R20.2 U2.9 
+'$1N219326' ; R17.1 R20.1 
+'$1N219329' ; C4.1 L1.1 U2.13 U2.14 
+'$1N219330' ; C5.2 C14.2 C17.2 CN1.1 L1.2 Q7.3 R17.2 U2.10 
+'$1N219388' ; Q3.3 U1.2 
+'$1N219660' ; Q6.1 R10.2 
+'$1N219673' ; C15.2 Q3.2 Q4.2 Q6.2 R1.2 
+'$1N219967' ; H5.2 R72.2 R74.2 U22.6 U23.6 
+'$1N220337' ; Q2.1 R12.2 R13.2 
+'$1N220644' ; H2.2 R22.2 U3.3 
+'$1N220659' ; H2.1 R9.1 
+'$1N220661' ; H2.3 R7.2 
+'$1N220812' ; H3.1 R27.2 
+'$1N220814' ; H3.3 R28.2 
+'$1N220820' ; H3.2 R36.2 U6.3 
+'$1N232426' ; C4.2 U2.15 
+'$1N232428' ; R3.2 U2.4 
+'$1N25321' ; C24.1 U4.1 
+'$1N25347' ; C24.2 D3.1 L3.1 U4.8 
+'$1N25981' ; R24.1 R31.2 U4.4 
+'$1N27457' ; C25.1 U6.1 
+'$1N27465' ; C25.2 L4.1 U6.6 
+'$1N27856' ; D4.2 L5.2 U7.1 
+'$1N27899' ; R46.1 R48.2 U7.3 
+'$1N284612' ; H4.2 R29.1 
+'$1N284617' ; H4.1 Q11.3 
+'$1N284675' ; Q11.1 R44.2 R45.2 
+'$1N284885' ; C3.2 C12.2 Q4.3 R12.1 U2.1 
+'$1N284896' ; R4.2 U2.3 
+'$1N284900' ; H1.2 R4.1 
+'$1N284903' ; C13.2 H1.1 R11.1 U2.2 
+'$1N285302' ; C54.2 C55.2 C56.2 C57.2 Q15.3 U12.9 U12.10 
+'$1N292841' ; Q15.1 Q19.3 R53.2 
+'$1N292934' ; Q19.1 R55.2 
+'$1N299251' ; H4.4 U4.7 
+'$1N330138' ; Q1.1 Q5.3 R5.2 
+'$1N330143' ; Q5.1 R2.1 
+'$1N330213' ; C58.2 C62.2 Q17.3 Q18.2 U16.5 
+'$1N330234' ; Q17.1 R57.1 R58.2 
+'$1N35056' ; Q9.1 R40.1 R41.2 
+'$1N35060' ; Q9.3 U19.20 
+'$1N35062' ; R26.2 U19.12 
+'$1N35065' ; R30.2 U19.13 
+'$1N35068' ; R25.2 U19.11 
+'$1N35087' ; LED1.1 Q8.3 
+'$1N35088' ; Q8.1 R15.1 
+'$1N35089' ; LED1.2 R18.2 
+'$1N35110' ; Q10.1 R34.2 R35.1 
+'$1N35118' ; Q14.1 R42.2 R43.1 
+'$1N35136' ; C43.2 Q13.1 R38.2 
+'$1N35141' ; C42.1 Q12.1 R37.1 
+'$1N35148' ; C6.1 C7.1 C8.1 C9.2 C10.2 C11.2 Q1.3 U19.45 U19.46 
+'$1N36133' ; LAN.2 U17.21 
+'$1N36222' ; C68.2 U17.33 
+'$1N36366' ; C59.1 L6.1 U17.1 U17.2 
+'$1N36373' ; C66.2 L6.2 U17.35 
+'$1N36810' ; C67.2 U17.32 U21.3 
+'$1N36815' ; C74.2 U17.31 U21.1 
+'$1N37705' ; Q18.1 U16.3 
+'$1N39412' ; C80.2 U20.30 
+'$1N45053' ; LAN.1 R62.2 
+'$1N46192' ; R60.1 U20.60 
+'$1N88506' ; D7.10 R69.1 
+'$1N88557' ; D7.11 R70.1 
+'$1N99689' ; RF1.1 U19.37 
+'4G/~LAN' ; R2.2 R58.1 R74.1 U20.61 
+'ADC_VBAT' ; C84.2 R71.1 R73.2 U20.15 
+'CAT1_NETSTATUS' ; R15.2 U19.17 
+'CAT1_PWRKEY' ; R35.2 U20.17 
+'CAT1_RESET' ; R43.2 U20.14 
+'CAT1_UART_RX' ; Q12.3 U19.18 
+'CAT1_UART_TX' ; Q13.2 U19.19 
+'CAT1_WAKEUP' ; R40.2 U20.16 
+'E32_INT' ; U12.20 U20.20 
+'E32_NRST' ; U12.21 U20.21 
+'E32_PXEN' ; U12.6 U20.26 
+'E32_TXEN' ; R75.2 U12.7 U20.27 
+'LORA_POWER' ; R55.1 U20.37 
+'MCU_SWCLK' ; CN2.3 U20.49 
+'MCU_SWDIO' ; CN2.4 U20.46 
+'NT26E_RX' ; Q13.3 R39.1 U22.1 
+'NT26E_TX' ; Q12.2 U23.1 
+'POWER_CONTROL' ; R45.1 U20.56 
+'RD-' ; D7.7 U17.12 
+'RD+' ; D7.6 U17.11 
+'RS485_1_A' ; D5.1 R49.1 R50.2 U9.1 U10.6 
+'RS485_1_B' ; D5.2 R47.2 R49.2 U9.2 U10.7 
+'RS485_1_CTRL' ; U10.2 U10.3 U20.38 
+'RS485_2_A' ; D6.1 R52.1 R54.2 U13.1 U14.6 
+'RS485_2_B' ; D6.2 R51.2 R52.2 U13.2 U14.7 
+'RS485_2_CTRL' ; U14.2 U14.3 U20.34 
+'SD1_CLK' ; CARD2.5 R65.1 U20.53 
+'SD1_CMD' ; CARD2.3 R66.1 U20.54 
+'SD1_DAT0' ; CARD2.7 R64.1 U20.39 
+'SD1_DAT1' ; CARD2.8 R63.1 U20.40 
+'SD1_DAT2' ; CARD2.1 R68.1 U20.42 
+'SD1_DAT3' ; CARD2.2 R67.1 U20.52 
+'SIM_CLK' ; C29.2 CARD1.3 D2.4 R30.1 
+'SIM_DATA' ; C31.2 CARD1.7 D2.6 R23.2 R25.1 
+'SIM_RST' ; C30.2 CARD1.2 D2.5 R26.1 
+'SIM_VDD' ; C32.1 C41.2 CARD1.1 CARD1.6 D2.3 R23.1 U19.15 
+'SPI1_MISO' ; U18.2 U20.9 
+'SPI1_MOSI' ; U18.5 U20.11 
+'SPI1_SCK' ; U18.6 U20.10 
+'SPI1_SS0' ; U18.1 U20.8 
+'SPI2_MISO' ; U12.22 U20.22 
+'SPI2_MOSI' ; U12.23 U20.23 
+'SPI2_SCK' ; U12.24 U20.24 
+'SPI2_SS0' ; U12.25 U20.25 
+'TD-' ; D7.2 U17.14 
+'TD+' ; D7.1 U17.13 
+'UART1_RX' ; CN2.6 CN3.3 U20.44 
+'UART1_TX' ; CN2.5 CN3.2 U20.45 
+'UART2_RX' ; U10.1 U20.43 
+'UART2_TX' ; U10.4 U20.41 
+'UART3_RX' ; U14.1 U20.35 
+'UART3_TX' ; U14.4 U20.33 
+'UART4_RX' ; U20.62 U22.4 
+'UART4_TX' ; U20.2 U23.4 
+'V_RS4851_5/12V' ; C20.2 C21.2 L2.2 R7.1 R9.2 U11.2 
+'V_RS4851_ON/~OFF' ; U3.4 U20.51 
+'V_RS4852_5/12V' ; C35.2 C36.2 L4.2 R27.1 R28.1 U15.2 
+'V_RS4852_ON/~OFF' ; U6.4 U20.28 
+'VCC_15V' ; C18.2 C19.2 C33.2 C34.2 C51.1 C52.2 D4.1 R46.2 U3.5 U6.5 
+'VCC_33' ; C60.1 C61.1 C69.2 D7.3 D7.5 D7.9 D7.12 Q18.3 R56.2 U17.3 
+'VCC_3V3' ; C42.2 C46.2 C47.2 C48.2 C53.2 C63.1 C64.1 C65.1 C71.1 C72.1 C75.1 ,
+        C76.1 C78.1 C79.2 C83.2 C85.2 C86.2 CARD2.4 CN2.7 Q17.2 R37.2 R39.2 ,
+        R50.1 R54.1 R57.2 R59.1 R60.2 R63.2 R64.2 R65.2 R66.2 R67.2 R68.2 ,
+        R72.1 U8.2 U8.4 U10.8 U14.8 U18.3 U18.7 U18.8 U20.13 U20.19 U20.32 ,
+        U20.48 U20.64 U22.5 U23.5 
+'VCC_3V8' ; C39.2 C40.2 Q1.2 Q15.2 R5.1 R18.1 R32.2 R53.1 U5.4 
+'VCC_5V' ; C22.1 C23.2 C37.2 C38.2 C44.2 C45.2 L3.2 R24.2 U5.1 U5.2 U8.3 
+'VCC_7V4' ; C1.2 C2.2 C26.2 C27.2 C49.1 C50.2 H4.3 L5.1 Q2.2 R29.2 U2.16 U7.4 ,
+        U7.5 
+'VDD_EXT' ; C28.2 C43.1 R38.1 U19.26 
+'XTAL_IN' ; C81.2 U20.5 X2.1 
+'XTAL_OUT' ; C82.2 U20.6 X2.3 
+'XTAL32_IN' ; C77.1 U20.4 X1.2 
+'XTAL32_OUT' ; C73.1 U20.3 X1.1 
+'YOXO_100MLINK' ; R69.2 U17.23 
+'YOXO_DEF' ; U17.22 U20.59 
+'YOXO_NRST' ; U17.25 U20.57 
+'YOXO_RX' ; U17.37 U22.3 
+'YOXO_TX' ; U17.36 U23.3 
+ACT ; R70.2 U17.27 
+CAT1PWRKEY ; Q10.3 U19.7 
+CAT1RESET ; Q14.3 U19.16 
+GND ; C1.1 C2.1 C3.1 C5.1 C6.2 C7.2 C8.2 C9.1 C10.1 C11.1 C12.1 C13.1 C14.1 ,
+        C15.1 C18.1 C19.1 C20.1 C21.1 C22.2 C23.1 C26.1 C27.1 C28.1 C29.1 ,
+        C30.1 C31.1 C32.2 C33.1 C34.1 C35.1 C36.1 C37.1 C38.1 C39.1 C40.1 ,
+        C41.1 C44.1 C45.1 C46.1 C47.1 C48.1 C49.2 C50.1 C51.2 C52.1 C53.1 ,
+        C54.1 C55.1 C56.1 C57.1 C58.1 C59.2 C60.2 C61.2 C62.1 C63.2 C64.2 ,
+        C65.2 C66.1 C67.1 C68.1 C69.1 C70.1 C71.2 C72.2 C73.2 C74.1 C75.2 ,
+        C76.2 C77.2 C78.2 C79.1 C80.1 C81.1 C82.1 C83.1 C84.1 C85.1 C86.1 ,
+        CARD1.5 CARD1.9 CARD1.10 CARD1.11 CARD2.6 CARD2.9 CARD2.10 CARD2.11 ,
+        CARD2.12 CN1.2 CN2.1 CN3.1 D1.2 D2.2 D3.2 D5.3 D6.3 H5.1 LORA.1 Q5.2 ,
+        Q8.2 Q9.2 Q10.2 Q11.2 Q14.2 Q19.2 R3.1 R6.1 R13.1 R14.1 R19.1 R21.1 ,
+        R22.1 R31.1 R33.2 R34.1 R36.1 R41.1 R42.1 R44.1 R47.1 R48.1 R51.1 ,
+        R56.1 R62.1 R73.1 R75.1 RF1.2 RF1.3 U1.1 U2.11 U2.12 U3.2 U4.6 U4.9 ,
+        U5.3 U5.6 U6.2 U7.2 U8.1 U10.5 U11.1 U12.1 U12.2 U12.3 U12.4 U12.5 ,
+        U12.11 U12.12 U12.17 U12.18 U12.26 U12.28 U14.5 U15.1 U16.2 U17.49 ,
+        U18.4 U19.1 U19.10 U19.29 U19.36 U19.39 U19.40 U19.43 U19.44 U19.50 ,
+        U19.51 U19.52 U19.53 U19.81 U19.82 U19.83 U19.85 U19.103 U19.107 ,
+        U19.108 U19.109 U19.110 U19.111 U19.112 U20.12 U20.18 U20.31 U20.47 ,
+        U20.63 U21.2 U21.4 U22.2 U23.2 X2.2 X2.4 
+LINK ; U17.28 U20.58 
+NRST ; C70.2 CN2.2 R59.2 U20.7 
+PGND ; D7.8 D7.13 D7.14 
+VBAT ; Q2.3 Q7.2 R71.2 
+$SCHEDULE
+$END
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>
@@ -0,0 +1,21 @@
+; ****************************************************************
+; Scatter-Loading Description File
+; ****************************************************************
+LR_IROM1 0x00008000 0x00078000  {    ; load region size_region
+    ER_IROM1 0x00008000 0x00078000  {  ; load address = execution address
+        *.o (RESET, +First)
+        *(InRoot$$Sections)
+        .ANY (+RO)
+        .ANY (+XO)
+    }
+    RW_IRAM1 0x1FFF8000 UNINIT 0x00000008  {  ; RW data
+        *(.bss.noinit)
+    }
+    RW_IRAM2 0x1FFF8008 0x00026FF8  {  ; RW data
+        .ANY (+RW +ZI)
+        .ANY (RAMCODE)
+    }
+    RW_IRAMB 0x200F0000 0x00001000  {  ; RW data
+        .ANY (+RW +ZI)
+    }
+}
@@ -0,0 +1,35 @@
+[BREAKPOINTS]
+ForceImpTypeAny = 0
+ShowInfoWin = 1
+EnableFlashBP = 2
+BPDuringExecution = 0
+[CFI]
+CFISize = 0x00
+CFIAddr = 0x00
+[CPU]
+OverrideMemMap = 0
+AllowSimulation = 1
+ScriptFile=""
+[FLASH]
+CacheExcludeSize = 0x00
+CacheExcludeAddr = 0x00
+MinNumBytesFlashDL = 0
+SkipProgOnCRCMatch = 1
+VerifyDownload = 1
+AllowCaching = 1
+EnableFlashDL = 2
+Override = 1
+Device="Cortex-M4"
+[GENERAL]
+WorkRAMSize = 0x00
+WorkRAMAddr = 0x00
+RAMUsageLimit = 0x00
+[SWO]
+SWOLogFile=""
+[MEM]
+RdOverrideOrMask = 0x00
+RdOverrideAndMask = 0xFFFFFFFF
+RdOverrideAddr = 0xFFFFFFFF
+WrOverrideOrMask = 0x00
+WrOverrideAndMask = 0xFFFFFFFF
+WrOverrideAddr = 0xFFFFFFFF
@@ -0,0 +1,78 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System
+ * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    FS_Config.c
+ * Purpose: File System Configuration
+ * Rev.:    V6.3.0
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>FAT File System
+// <i>Define FAT File System parameters
+
+//   <o>Number of open files <1-16>
+//   <i>Define number of files that can be opened at the same time.
+//   <i>Default: 4
+#define FAT_MAX_OPEN_FILES      4
+
+// </h>
+
+// <h>Embedded File System
+// <i>Define Embedded File System parameters
+
+//   <o>Number of open files <1-16>
+//   <i>Define number of files that can be opened at the same time.
+//   <i>Default: 4
+#define EFS_MAX_OPEN_FILES      4
+
+// </h>
+
+// <o>Initial Current Drive <0=>F0: <1=>F1:
+//                          <2=>M0: <3=>M1:
+//                          <4=>N0: <5=>N1:
+//                          <6=>R0: <9=>R1:
+//                          <7=>U0: <8=>U1:
+// <i>Set initial setting for current drive. Current drive is used for File System functions
+// <i>that are invoked with the "" string and can be altered anytime during run-time.
+#define FS_INITIAL_CDRIVE       2
+
+#include "RTE_Components.h"
+
+#ifdef  RTE_FileSystem_Drive_RAM_0
+#include "FS_Config_RAM_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_RAM_1
+#include "FS_Config_RAM_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_NOR_0
+#include "FS_Config_NOR_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_NOR_1
+#include "FS_Config_NOR_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_NAND_0
+#include "FS_Config_NAND_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_NAND_1
+#include "FS_Config_NAND_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_MC_0
+#include "FS_Config_MC_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_MC_1
+#include "FS_Config_MC_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_USB_0
+#include "FS_Config_USB_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_USB_1
+#include "FS_Config_USB_1.h"
+#endif
+
+#include "fs_config.h"
@@ -0,0 +1,55 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System:Drive
+ * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    FS_Config_MC_0.h
+ * Purpose: File System Configuration for Memory Card Drive
+ * Rev.:    V6.2.0
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>Memory Card Drive 0
+// <i>Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:"
+#define MC0_ENABLE              1
+
+//   <o>Connect to hardware via Driver_MCI# <0-255>
+//   <i>Select driver control block for hardware interface
+#define MC0_MCI_DRIVER          0
+
+//   <o>Connect to hardware via Driver_SPI# <0-255>
+//   <i>Select driver control block for hardware interface when in SPI mode
+#define MC0_SPI_DRIVER          0
+
+//   <o>Memory Card Interface Mode <0=>Native <1=>SPI
+//   <i>Native uses a SD Bus with up to 8 data lines, CLK, and CMD
+//   <i>SPI uses 2 data lines (MOSI and MISO), SCLK and CS
+#define MC0_SPI                 0
+          
+//   <o>Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+//                       <8=>8 KB <16=>16 KB <32=>32 KB
+//   <i>Drive Cache stores data sectors and may be increased to speed-up
+//   <i>file read/write operations on this drive (default: 4 KB)
+#define MC0_CACHE_SIZE          4
+
+//   <e>Locate Drive Cache and Drive Buffer
+//   <i>Some microcontrollers support DMA only in specific memory areas and
+//   <i>require to locate the drive buffers at a fixed address.
+#define MC0_CACHE_RELOC         0
+
+//     <o>Base address <0x0000-0xFFFFFE00:0x200>
+//     <i>Set buffer base address to RAM areas that support DMA with the drive.
+#define MC0_CACHE_ADDR          0x7FD00000
+
+//   </e>
+//   <o>Filename Cache Size <0-1000000>
+//   <i>Define number of cached file or directory names.
+//   <i>48 bytes of RAM is required for each cached name.
+#define MC0_NAME_CACHE_SIZE     0
+
+//   <q>Use FAT Journal
+//   <i>Protect File Allocation Table and Directory Entries for
+//   <i>fail-safe operation.
+#define MC0_FAT_JOURNAL         0
+
+// </h>
@@ -0,0 +1,50 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System
+ * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    FS_Debug.c
+ * Purpose: File System Debug Configuration
+ * Rev.:    V1.0.0
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+//   <e>File System Debug
+//   <i>Enable File System event recording
+#define FS_DEBUG_EVR_ENABLE     0
+
+//   <o>Core Management <0=>Off <1=>Errors <2=>Errors + API <3=>All
+//   <i>Configure FsCore: Core Management event recording
+#define FS_DEBUG_EVR_CORE       1
+
+//   <o>FAT File System <0=>Off <1=>Errors <2=>Errors + API <3=>All
+//   <i>Configure FsFAT: FAT File System event recording
+#define FS_DEBUG_EVR_FAT        1
+
+//   <o>EFS File System <0=>Off <1=>Errors <2=>Errors + API <3=>All
+//   <i>Configure FsEFS: EFS File System event recording
+#define FS_DEBUG_EVR_EFS        1
+
+//   <o>I/O Control Interface <0=>Off <1=>Errors <2=>Errors + API <3=>All
+//   <i>Configure FsIOC: I/O Control Interface event recording
+#define FS_DEBUG_EVR_IOC        1
+
+//   <o>NAND Flash Translation Layer <0=>Off <1=>Errors <2=>Errors + API <3=>All
+//   <i>Configure FsNFTL: NAND Flash Translation Layer event recording
+#define FS_DEBUG_EVR_NFTL       1
+
+//   <o>NAND Device Interface <0=>Off <1=>Errors <2=>Errors + API <3=>All
+//   <i>Configure FsNAND: NAND Device Interface event recording
+#define FS_DEBUG_EVR_NAND       1
+
+//   <o>Memory Card MCI <0=>Off <1=>Errors <2=>Errors + API <3=>All
+//   <i>Configure FsMcMCI: Memory Card MCI event recording
+#define FS_DEBUG_EVR_MC_MCI     1
+
+//   <o>Memory Card SPI <0=>Off <1=>Errors <2=>Errors + API <3=>All
+//   <i>Configure FsMcSPI: Memory Card SPI event recording
+#define FS_DEBUG_EVR_MC_SPI     1
+
+//   </e>
+
+#include "fs_debug.h"
@@ -0,0 +1,173 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network
+ * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config.c
+ * Purpose: Network Configuration
+ * Rev.:    V7.1.0
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>Network System Settings
+// <i>Global Network System definitions
+//   <s.15>Local Host Name
+//   <i>This is the name under which embedded host can be
+//   <i>accessed on a local area network.
+//   <i>Default: "my_host"
+#define NET_HOST_NAME           "my_host"
+
+//   <o>Memory Pool Size <1536-262144:4>
+//   <i>This is the size of a memory pool in bytes. Buffers for
+//   <i>network packets are allocated from this memory pool.
+//   <i>Default: 12000 bytes
+#define NET_MEM_POOL_SIZE       12000
+
+//   <q>Start System Services
+//   <i>If enabled, the system will automatically start server services
+//   <i>(HTTP, FTP, TFTP server, ...) when initializing the network system.
+//   <i>Default: Enabled
+#define NET_START_SERVICE       1
+
+//   <h>OS Resource Settings
+//   <i>These settings are used to optimize usage of OS resources.
+//     <o>Core Thread Stack Size <512-65535:4>
+//     <i>Default: 1024 bytes
+#define NET_THREAD_STACK_SIZE   1024
+
+//        Core Thread Priority
+#define NET_THREAD_PRIORITY     osPriorityNormal
+
+//   </h>
+// </h>
+
+//------------- <<< end of configuration section >>> ---------------------------
+
+#include "RTE_Components.h"
+
+#ifdef  RTE_Network_Interface_ETH_0
+#include "Net_Config_ETH_0.h"
+#endif
+#ifdef  RTE_Network_Interface_ETH_1
+#include "Net_Config_ETH_1.h"
+#endif
+
+#ifdef  RTE_Network_Interface_WiFi_0
+#include "Net_Config_WiFi_0.h"
+#endif
+
+#ifdef  RTE_Network_Interface_WiFi_1
+#include "Net_Config_WiFi_1.h"
+#endif
+
+#ifdef  RTE_Network_Interface_PPP
+#include "Net_Config_PPP.h"
+#endif
+
+#ifdef  RTE_Network_Interface_SLIP
+#include "Net_Config_SLIP.h"
+#endif
+
+#ifdef  RTE_Network_Socket_UDP
+#include "Net_Config_UDP.h"
+#endif
+#ifdef  RTE_Network_Socket_TCP
+#include "Net_Config_TCP.h"
+#endif
+#ifdef  RTE_Network_Socket_BSD
+#include "Net_Config_BSD.h"
+#endif
+
+#ifdef  RTE_Network_Web_Server_RO
+#include "Net_Config_HTTP_Server.h"
+#endif
+#ifdef  RTE_Network_Web_Server_FS
+#include "Net_Config_HTTP_Server.h"
+#endif
+
+#ifdef  RTE_Network_Telnet_Server
+#include "Net_Config_Telnet_Server.h"
+#endif
+
+#ifdef  RTE_Network_TFTP_Server
+#include "Net_Config_TFTP_Server.h"
+#endif
+#ifdef  RTE_Network_TFTP_Client
+#include "Net_Config_TFTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_FTP_Server
+#include "Net_Config_FTP_Server.h"
+#endif
+#ifdef  RTE_Network_FTP_Client
+#include "Net_Config_FTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_DNS_Client
+#include "Net_Config_DNS_Client.h"
+#endif
+
+#ifdef  RTE_Network_SMTP_Client
+#include "Net_Config_SMTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_SNMP_Agent
+#include "Net_Config_SNMP_Agent.h"
+#endif
+
+#ifdef  RTE_Network_SNTP_Client
+#include "Net_Config_SNTP_Client.h"
+#endif
+
+#include "net_config.h"
+
+/**
+\addtogroup net_genFunc
+@{
+*/
+/**
+  \fn          void net_sys_error (NET_ERROR error)
+  \ingroup     net_cores
+  \brief       Network system error handler.
+*/
+void net_sys_error (NET_ERROR error) {
+  /* This function is called when a fatal error is encountered. */
+  /* The normal program execution is not possible anymore.      */
+
+  switch (error) {
+    case NET_ERROR_MEM_ALLOC:
+      /* Out of memory */
+      break;
+
+    case NET_ERROR_MEM_FREE:
+      /* Trying to release non existing memory block */
+      break;
+
+    case NET_ERROR_MEM_CORRUPT:
+      /* Memory Link pointer corrupted */
+      /* More data written than the size of allocated memory block */
+      break;
+
+    case NET_ERROR_CONFIG:
+      /* Network configuration error detected */
+      break;
+
+    case NET_ERROR_UDP_ALLOC:
+      /* Out of UDP Sockets */
+      break;
+
+    case NET_ERROR_TCP_ALLOC:
+      /* Out of TCP Sockets */
+      break;
+
+    case NET_ERROR_TCP_STATE:
+      /* TCP State machine in undefined state */
+      break;
+  }
+
+  /* End-less loop */
+  while (1);
+}
+/**
+@}
+*/
@@ -0,0 +1,253 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Interface
+ * Copyright (c) 2004-2020 Arm Limited (or its affiliates). All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_ETH_0.h
+ * Purpose: Network Configuration for ETH Interface
+ * Rev.:    V7.3.0
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>Ethernet Network Interface 0
+#define ETH0_ENABLE             1
+
+//   <o>Connect to hardware via Driver_ETH# <0-255>
+//   <i>Select driver control block for MAC and PHY interface
+#define ETH0_DRIVER             0
+
+//   <s.17>MAC Address
+//   <i>Ethernet MAC Address in text representation
+//   <i>Value FF-FF-FF-FF-FF-FF is not allowed,
+//   <i>LSB of first byte must be 0 (an ethernet Multicast bit).
+//   <i>Default: "1E-30-6C-A2-45-5E"
+#define ETH0_MAC_ADDR           "1E-30-6C-A2-45-5E"
+
+//   <e>VLAN
+//   <i>Enable or disable Virtual LAN
+#define ETH0_VLAN_ENABLE        0
+
+//     <o>VLAN Identifier <1-4093>
+//     <i>A unique 12-bit numeric value
+//     <i>Default: 1
+#define ETH0_VLAN_ID            1
+//   </e>
+
+//   <e>IPv4
+//   <i>Enable IPv4 Protocol for Network Interface
+#define ETH0_IP4_ENABLE         1
+
+//     <s.15>IP Address
+//     <i>Static IPv4 Address in text representation
+//     <i>Default: "192.168.0.100"
+#define ETH0_IP4_ADDR           "192.168.0.100"
+
+//     <s.15>Subnet mask
+//     <i>Local Subnet mask in text representation
+//     <i>Default: "255.255.255.0"
+#define ETH0_IP4_MASK           "255.255.255.0"
+
+//     <s.15>Default Gateway
+//     <i>IP Address of Default Gateway in text representation
+//     <i>Default: "192.168.0.254"
+#define ETH0_IP4_GATEWAY        "192.168.0.254"
+
+//     <s.15>Primary DNS Server
+//     <i>IP Address of Primary DNS Server in text representation
+//     <i>Default: "8.8.8.8"
+#define ETH0_IP4_PRIMARY_DNS    "8.8.8.8"
+
+//     <s.15>Secondary DNS Server
+//     <i>IP Address of Secondary DNS Server in text representation
+//     <i>Default: "8.8.4.4"
+#define ETH0_IP4_SECONDARY_DNS  "8.8.4.4"
+
+//     <e>IP Fragmentation
+//     <i>This option enables fragmentation of outgoing IP datagrams,
+//     <i>and reassembling the fragments of incoming IP datagrams.
+//     <i>Default: enabled
+#define ETH0_IP4_FRAG_ENABLE    1
+
+//       <o>MTU size <576-1500>
+//       <i>Maximum Transmission Unit in bytes
+//       <i>Default: 1500
+#define ETH0_IP4_MTU            1500
+//     </e>
+
+//     <h>ARP Address Resolution
+//     <i>ARP cache and node address resolver settings
+//       <o>Cache Table size <5-100>
+//       <i>Number of cached MAC/IP addresses
+//       <i>Default: 10
+#define ETH0_ARP_TAB_SIZE       10
+
+//       <o>Cache Timeout in seconds <5-255>
+//       <i>A timeout for cached hardware/IP addresses
+//       <i>Default: 150
+#define ETH0_ARP_CACHE_TOUT     150
+
+//       <o>Number of Retries <0-20>
+//       <i>Number of Retries to resolve an IP address
+//       <i>before ARP module gives up
+//       <i>Default: 4
+#define ETH0_ARP_MAX_RETRY      4
+
+//       <o>Resend Timeout in seconds <1-10>
+//       <i>A timeout to resend the ARP Request
+//       <i>Default: 2
+#define ETH0_ARP_RESEND_TOUT    2
+
+//       <q>Send Notification on Address changes
+//       <i>When this option is enabled, the embedded host
+//       <i>will send a Gratuitous ARP notification at startup,
+//       <i>or when the device IP address has changed.
+//       <i>Default: Disabled
+#define ETH0_ARP_NOTIFY         0
+//     </h>
+
+//     <e>IGMP Group Management
+//     <i>Enable or disable Internet Group Management Protocol
+#define ETH0_IGMP_ENABLE        0
+
+//       <o>Membership Table size <2-50>
+//       <i>Number of Groups this host can join
+//       <i>Default: 5
+#define ETH0_IGMP_TAB_SIZE      5
+//     </e>
+
+//     <q>NetBIOS Name Service
+//     <i>When this option is enabled, the embedded host can be
+//     <i>accessed by its name on local LAN using NBNS protocol.
+#define ETH0_NBNS_ENABLE        1
+
+//     <e>Dynamic Host Configuration
+//     <i>When this option is enabled, local IP address, Net Mask
+//     <i>and Default Gateway are obtained automatically from
+//     <i>the DHCP Server on local LAN.
+#define ETH0_DHCP_ENABLE        1
+
+//       <s.40>Vendor Class Identifier
+//       <i>This value is optional. If specified, it is added
+//       <i>to DHCP request message, identifying vendor type.
+//       <i>Default: ""
+#define ETH0_DHCP_VCID          ""
+
+//       <q>Bootfile Name
+//       <i>This value is optional. If enabled, the Bootfile Name
+//       <i>(option 67) is also requested from DHCP server.
+//       <i>Default: disabled
+#define ETH0_DHCP_BOOTFILE      0
+
+//       <q>NTP Servers
+//       <i>This value is optional. If enabled, a list of NTP Servers
+//       <i>(option 42) is also requested from DHCP server.
+//       <i>Default: disabled
+#define ETH0_DHCP_NTP_SERVERS   0
+//     </e>
+
+//     Disable ICMP Echo response
+#define ETH0_ICMP_NO_ECHO       0
+//   </e>
+
+//   <e>IPv6
+//   <i>Enable IPv6 Protocol for Network Interface
+#define ETH0_IP6_ENABLE         1
+
+//     <s.40>IPv6 Address
+//     <i>Static IPv6 Address in text representation
+//     <i>Use unspecified address "::" when static
+//     <i>IPv6 address is not used.
+//     <i>Default: "fec0::2"
+#define ETH0_IP6_ADDR           "fec0::2"
+
+//     <o>Subnet prefix-length <1-128>
+//     <i>Number of bits that define network address
+//     <i>Default: 64
+#define ETH0_IP6_PREFIX_LEN     64
+
+//     <s.40>Default Gateway
+//     <i>Default Gateway IPv6 Address in text representation
+//     <i>Default: "fec0::1"
+#define ETH0_IP6_GATEWAY        "fec0::1"
+
+//     <s.40>Primary DNS Server
+//     <i>Primary DNS Server IPv6 Address in text representation
+//     <i>Default: "2001:4860:4860::8888"
+#define ETH0_IP6_PRIMARY_DNS    "2001:4860:4860::8888"
+
+//     <s.40>Secondary DNS Server
+//     <i>Secondary DNS Server IPv6 Address in text representation
+//     <i>Default: "2001:4860:4860::8844"
+#define ETH0_IP6_SECONDARY_DNS  "2001:4860:4860::8844"
+
+//     <h>Neighbor Discovery
+//     <i>Neighbor cache and node address resolver settings
+//       <o>Cache Table size <5-100>
+//       <i>Number of cached node addresses
+//       <i>Default: 5
+#define ETH0_NDP_TAB_SIZE       5
+
+//       <o>Cache Timeout in seconds <5-255>
+//       <i>Timeout for cached node addresses
+//       <i>Default: 150
+#define ETH0_NDP_CACHE_TOUT     150
+
+//       <o>Number of Retries <0-20>
+//       <i>Number of retries to resolve an IP address
+//       <i>before NDP module gives up
+//       <i>Default: 4
+#define ETH0_NDP_MAX_RETRY      4
+
+//       <o>Resend Timeout in seconds <1-10>
+//       <i>A timeout to resend Neighbor Solicitation
+//       <i>Default: 2
+#define ETH0_NDP_RESEND_TOUT    2
+//     </h>
+
+//     <e>Dynamic Host Configuration
+//     <i>When this option is enabled, local IPv6 address is
+//     <i>automatically configured.
+#define ETH0_DHCP6_ENABLE       1
+
+//       <o>DHCPv6 Client Mode  <0=>Stateless Mode <1=>Statefull Mode
+//       <i>Stateless DHCPv6 Client uses router advertisements
+//       <i>for IPv6 address autoconfiguration (SLAAC).
+//       <i>Statefull DHCPv6 Client connects to DHCPv6 server for a
+//       <i>leased IPv6 address and DNS server IPv6 addresses.
+#define ETH0_DHCP6_MODE         1
+
+//       <e>Vendor Class Option
+//       <i>If enabled, Vendor Class option is added to DHCPv6
+//       <i>request message, identifying vendor type.
+//       <i>Default: disabled
+#define ETH0_DHCP6_VCLASS_ENABLE 0
+
+//         <o>Enterprise ID
+//         <i>Enterprise-number as registered with IANA.
+//         <i>Default: 0 (Reserved)
+#define ETH0_DHCP6_VCLASS_EID   0
+
+//         <s.40>Vendor Class Data
+//         <i>This string identifies vendor type.
+//         <i>Default: ""
+#define ETH0_DHCP6_VCLASS_DATA  ""
+//       </e>
+//     </e>
+
+//     Disable ICMP6 Echo response
+#define ETH0_ICMP6_NO_ECHO      0
+//   </e>
+
+//   <h>OS Resource Settings
+//   <i>These settings are used to optimize usage of OS resources.
+//     <o>Interface Thread Stack Size <512-65535:4>
+//     <i>Default: 512 bytes
+#define ETH0_THREAD_STACK_SIZE  512
+
+//        Interface Thread Priority
+#define ETH0_THREAD_PRIORITY    osPriorityAboveNormal
+
+//   </h>
+// </h>
+
+//------------- <<< end of configuration section >>> ---------------------------
@@ -0,0 +1,69 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Socket
+ * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_TCP.h
+ * Purpose: Network Configuration for TCP Sockets
+ * Rev.:    V7.1.1
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>TCP Sockets
+#define TCP_ENABLE              1
+
+//   <o>Number of TCP Sockets <1-20>
+//   <i>Number of available TCP sockets
+//   <i>Default: 6
+#define TCP_NUM_SOCKS           6
+
+//   <o>Number of Retries <0-20>
+//   <i>How many times TCP module will try to retransmit data
+//   <i>before giving up. Increase this value for high-latency
+//   <i>and low throughput networks.
+//   <i>Default: 5
+#define TCP_MAX_RETRY           5
+
+//   <o>Retry Timeout in seconds <1-10>
+//   <i>If data frame not acknowledged within this time frame,
+//   <i>TCP module will try to resend the data again.
+//   <i>Default: 4
+#define TCP_RETRY_TOUT          4
+
+//   <o>Default Connect Timeout in seconds <1-65535>
+//   <i>If no TCP data frame has been exchanged during this time,
+//   <i>the TCP connection is either closed or a keep-alive frame
+//   <i>is sent to verify that the connection still exists.
+//   <i>Default: 120
+#define TCP_DEFAULT_TOUT        120
+
+//   <o>Maximum Segment Size <536-1440>
+//   <i>The Maximum Segment Size specifies the maximum
+//   <i>number of bytes in the TCP segment's Data field.
+//   <i>Default: 1440
+#define TCP_MAX_SEG_SIZE        1440
+
+//   <o>Receive Window Size <536-65535>
+//   <i>Receive Window Size specifies the size of data, 
+//   <i>that the socket is able to buffer in flow-control mode.
+//   <i>Default: 4320
+#define TCP_RECEIVE_WIN_SIZE    4320
+
+// </h>
+
+// TCP Initial Retransmit period in seconds
+#define TCP_INITIAL_RETRY_TOUT  1
+
+// TCP SYN frame retransmit period in seconds
+#define TCP_SYN_RETRY_TOUT      2
+
+// Number of retries to establish a connection
+#define TCP_CONNECT_RETRY       7
+
+// Dynamic port start (default 49152)
+#define TCP_DYN_PORT_START      49152
+
+// Dynamic port end (default 65535)
+#define TCP_DYN_PORT_END        65535
+
+//------------- <<< end of configuration section >>> ---------------------------
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-05-24                  the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "bsp.h"
+
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+/*
+ * Please modify RT_HEAP_SIZE if you enable RT_USING_HEAP
+ * the RT_HEAP_SIZE max value = (sram size - ZI size), 1024 means 1024 bytes
+ */
+#define RT_HEAP_SIZE (32*1024)
+static rt_uint8_t rt_heap[RT_HEAP_SIZE];
+
+RT_WEAK void *rt_heap_begin_get(void)
+{
+    return rt_heap;
+}
+
+RT_WEAK void *rt_heap_end_get(void)
+{
+    return rt_heap + RT_HEAP_SIZE;
+}
+#endif
+
+void rt_os_tick_callback(void)
+{
+    rt_interrupt_enter();
+    
+    rt_tick_increase();
+
+    rt_interrupt_leave();
+}
+
+void SysTick_IrqHandler(void)
+{
+	rt_os_tick_callback();
+}
+
+/**
+ * This function will initial your board.
+ */
+void rt_hw_board_init(void)
+{
+//#error "TODO 1: OS Tick Configuration."
+		BSP_Init();
+    /* 
+     * TODO 1: OS Tick Configuration
+     * Enable the hardware timer and call the rt_os_tick_callback function
+     * periodically with the frequency RT_TICK_PER_SECOND. 
+     */
+
+    /* Call components board initial (use INIT_BOARD_EXPORT()) */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+    rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get());
+#endif
+}
+
+#ifdef RT_USING_CONSOLE
+
+static int uart_init(void)
+{
+//#error "TODO 2: Enable the hardware uart and config baudrate."
+		DbgUart_Config(500000);
+    return 0;
+}
+INIT_BOARD_EXPORT(uart_init);
+
+void rt_hw_console_output(const char *str)
+{
+//#error "TODO 3: Output the string 'str' through the uart."
+	rt_enter_critical();
+	DebugUartSend((uint8_t *)str, strlen(str));
+	rt_exit_critical();
+}
+
+#endif
+
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-05-24                  the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+/*
+ * Please modify RT_HEAP_SIZE if you enable RT_USING_HEAP
+ * the RT_HEAP_SIZE max value = (sram size - ZI size), 1024 means 1024 bytes
+ */
+#define RT_HEAP_SIZE (15*1024)
+static rt_uint8_t rt_heap[RT_HEAP_SIZE];
+
+RT_WEAK void *rt_heap_begin_get(void)
+{
+    return rt_heap;
+}
+
+RT_WEAK void *rt_heap_end_get(void)
+{
+    return rt_heap + RT_HEAP_SIZE;
+}
+#endif
+
+void rt_os_tick_callback(void)
+{
+    rt_interrupt_enter();
+    
+    rt_tick_increase();
+
+    rt_interrupt_leave();
+}
+
+/**
+ * This function will initial your board.
+ */
+void rt_hw_board_init(void)
+{
+#error "TODO 1: OS Tick Configuration."
+    /* 
+     * TODO 1: OS Tick Configuration
+     * Enable the hardware timer and call the rt_os_tick_callback function
+     * periodically with the frequency RT_TICK_PER_SECOND. 
+     */
+
+    /* Call components board initial (use INIT_BOARD_EXPORT()) */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+    rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get());
+#endif
+}
+
+#ifdef RT_USING_CONSOLE
+
+static int uart_init(void)
+{
+#error "TODO 2: Enable the hardware uart and config baudrate."
+    return 0;
+}
+INIT_BOARD_EXPORT(uart_init);
+
+void rt_hw_console_output(const char *str)
+{
+#error "TODO 3: Output the string 'str' through the uart."
+}
+
+#endif
+
@@ -0,0 +1,139 @@
+/* RT-Thread config file */
+
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h>Basic Configuration
+// <o>Maximal level of thread priority <8-256>
+//  <i>Default: 32
+#define RT_THREAD_PRIORITY_MAX  16
+// <o>OS tick per second
+//  <i>Default: 1000   (1ms)
+#define RT_TICK_PER_SECOND  1000
+// <o>Alignment size for CPU architecture data access
+//  <i>Default: 4
+#define RT_ALIGN_SIZE   4
+// <o>the max length of object name<2-16>
+//  <i>Default: 8
+#define RT_NAME_MAX    10
+// <c1>Using RT-Thread components initialization
+//  <i>Using RT-Thread components initialization
+#define RT_USING_COMPONENTS_INIT
+// </c>
+
+#define RT_USING_USER_MAIN
+
+// <o>the stack size of main thread<1-4086>
+//  <i>Default: 512
+#define RT_MAIN_THREAD_STACK_SIZE     512
+
+// </h>
+
+// <h>Debug Configuration
+// <c1>enable kernel debug configuration
+//  <i>Default: enable kernel debug configuration
+//#define RT_DEBUG
+// </c>
+// <o>enable components initialization debug configuration<0-1>
+//  <i>Default: 0
+#define RT_DEBUG_INIT 0
+// <c1>thread stack over flow detect
+//  <i> Diable Thread stack over flow detect
+//#define RT_USING_OVERFLOW_CHECK
+// </c>
+// </h>
+
+// <h>Hook Configuration
+// <c1>using hook
+//  <i>using hook
+//#define RT_USING_HOOK
+// </c>
+// <c1>using idle hook
+//  <i>using idle hook
+//#define RT_USING_IDLE_HOOK
+// </c>
+// </h>
+
+// <e>Software timers Configuration
+// <i> Enables user timers
+#define RT_USING_TIMER_SOFT         0
+#if RT_USING_TIMER_SOFT == 0
+    #undef RT_USING_TIMER_SOFT
+#endif
+// <o>The priority level of timer thread <0-31>
+//  <i>Default: 4
+#define RT_TIMER_THREAD_PRIO        4
+// <o>The stack size of timer thread <0-8192>
+//  <i>Default: 512
+#define RT_TIMER_THREAD_STACK_SIZE  512
+// </e>
+
+// <h>IPC(Inter-process communication) Configuration
+// <c1>Using Semaphore
+//  <i>Using Semaphore
+#define RT_USING_SEMAPHORE
+// </c>
+// <c1>Using Mutex
+//  <i>Using Mutex
+#define RT_USING_MUTEX
+// </c>
+// <c1>Using Event
+//  <i>Using Event
+//#define RT_USING_EVENT
+// </c>
+// <c1>Using MailBox
+//  <i>Using MailBox
+#define RT_USING_MAILBOX
+// </c>
+// <c1>Using Message Queue
+//  <i>Using Message Queue
+#define RT_USING_MESSAGEQUEUE
+// </c>
+// </h>
+
+// <h>Memory Management Configuration
+// <c1>Memory Pool Management
+//  <i>Memory Pool Management
+//#define RT_USING_MEMPOOL
+// </c>
+// <c1>Dynamic Heap Management(Algorithm: small memory )
+//  <i>Dynamic Heap Management
+#define RT_USING_HEAP
+#define RT_USING_SMALL_MEM
+// </c>
+// <c1>using tiny size of memory
+//  <i>using tiny size of memory
+//#define RT_USING_TINY_SIZE
+// </c>
+// </h>
+
+// <h>Console Configuration
+// <c1>Using console
+//  <i>Using console
+#define RT_USING_CONSOLE
+// </c>
+// <o>the buffer size of console <1-1024>
+//  <i>the buffer size of console
+//  <i>Default: 128  (128Byte)
+#define RT_CONSOLEBUF_SIZE          512
+// </h>
+
+// <h>FinSH Configuration
+// <c1>include finsh config
+//  <i>Select this choice if you using FinSH 
+//#include "finsh_config.h"
+// </c>
+// </h>
+
+// <h>Device Configuration
+// <c1>using device framework
+//  <i>using device framework
+//#define RT_USING_DEVICE
+// </c>
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif
@@ -0,0 +1,139 @@
+/* RT-Thread config file */
+
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h>Basic Configuration
+// <o>Maximal level of thread priority <8-256>
+//  <i>Default: 32
+#define RT_THREAD_PRIORITY_MAX  32
+// <o>OS tick per second
+//  <i>Default: 1000   (1ms)
+#define RT_TICK_PER_SECOND  1000
+// <o>Alignment size for CPU architecture data access
+//  <i>Default: 4
+#define RT_ALIGN_SIZE   4
+// <o>the max length of object name<2-16>
+//  <i>Default: 8
+#define RT_NAME_MAX    8
+// <c1>Using RT-Thread components initialization
+//  <i>Using RT-Thread components initialization
+#define RT_USING_COMPONENTS_INIT
+// </c>
+
+#define RT_USING_USER_MAIN
+
+// <o>the stack size of main thread<1-4086>
+//  <i>Default: 512
+#define RT_MAIN_THREAD_STACK_SIZE     256
+
+// </h>
+
+// <h>Debug Configuration
+// <c1>enable kernel debug configuration
+//  <i>Default: enable kernel debug configuration
+//#define RT_DEBUG
+// </c>
+// <o>enable components initialization debug configuration<0-1>
+//  <i>Default: 0
+#define RT_DEBUG_INIT 0
+// <c1>thread stack over flow detect
+//  <i> Diable Thread stack over flow detect
+//#define RT_USING_OVERFLOW_CHECK
+// </c>
+// </h>
+
+// <h>Hook Configuration
+// <c1>using hook
+//  <i>using hook
+//#define RT_USING_HOOK
+// </c>
+// <c1>using idle hook
+//  <i>using idle hook
+//#define RT_USING_IDLE_HOOK
+// </c>
+// </h>
+
+// <e>Software timers Configuration
+// <i> Enables user timers
+#define RT_USING_TIMER_SOFT         0
+#if RT_USING_TIMER_SOFT == 0
+    #undef RT_USING_TIMER_SOFT
+#endif
+// <o>The priority level of timer thread <0-31>
+//  <i>Default: 4
+#define RT_TIMER_THREAD_PRIO        4
+// <o>The stack size of timer thread <0-8192>
+//  <i>Default: 512
+#define RT_TIMER_THREAD_STACK_SIZE  512
+// </e>
+
+// <h>IPC(Inter-process communication) Configuration
+// <c1>Using Semaphore
+//  <i>Using Semaphore
+#define RT_USING_SEMAPHORE
+// </c>
+// <c1>Using Mutex
+//  <i>Using Mutex
+//#define RT_USING_MUTEX
+// </c>
+// <c1>Using Event
+//  <i>Using Event
+//#define RT_USING_EVENT
+// </c>
+// <c1>Using MailBox
+//  <i>Using MailBox
+#define RT_USING_MAILBOX
+// </c>
+// <c1>Using Message Queue
+//  <i>Using Message Queue
+//#define RT_USING_MESSAGEQUEUE
+// </c>
+// </h>
+
+// <h>Memory Management Configuration
+// <c1>Memory Pool Management
+//  <i>Memory Pool Management
+//#define RT_USING_MEMPOOL
+// </c>
+// <c1>Dynamic Heap Management(Algorithm: small memory )
+//  <i>Dynamic Heap Management
+#define RT_USING_HEAP
+#define RT_USING_SMALL_MEM
+// </c>
+// <c1>using tiny size of memory
+//  <i>using tiny size of memory
+//#define RT_USING_TINY_SIZE
+// </c>
+// </h>
+
+// <h>Console Configuration
+// <c1>Using console
+//  <i>Using console
+//#define RT_USING_CONSOLE
+// </c>
+// <o>the buffer size of console <1-1024>
+//  <i>the buffer size of console
+//  <i>Default: 128  (128Byte)
+#define RT_CONSOLEBUF_SIZE          256
+// </h>
+
+// <h>FinSH Configuration
+// <c1>include finsh config
+//  <i>Select this choice if you using FinSH 
+//#include "finsh_config.h"
+// </c>
+// </h>
+
+// <h>Device Configuration
+// <c1>using device framework
+//  <i>using device framework
+//#define RT_USING_DEVICE
+// </c>
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'GateWay' 
+ * Target:  'Debug' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "HC32F460PETB.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'GateWay' 
+ * Target:  'Release' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "HC32F460KETA.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'GateWay' 
+ * Target:  'app_app' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "HC32F460KETA.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'GateWay' 
+ * Target:  'app_boot' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "HC32F460KETA.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'GateWay' 
+ * Target:  'app_dubeg' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "HC32F460KETA.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'DigitalModule_4Ch' 
+ * Target:  'i2c_24c256_Debug' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "HC32F460PETB.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'DigitalModule_4Ch' 
+ * Target:  'i2c_24c256_Release' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "HC32F460PETB.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'DigitalModule_4Ch' 
+ * Target:  'template_Debug' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "HC32F460PETB.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
@@ -0,0 +1,16 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00008000 0x0006C000  {    ; load region size_region
+  ER_IROM1 0x00008000 0x0006C000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  RW_IRAM1 0x1FFF8000 0x0002F000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
@@ -0,0 +1,621 @@
+;/******************************************************************************
+; * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+; *
+; * This software component is licensed by HDSC under BSD 3-Clause license
+; * (the "License"); You may not use this file except in compliance with the
+; * License. You may obtain a copy of the License at:
+; *                    opensource.org/licenses/BSD-3-Clause
+;/*****************************************************************************/
+;/*  Startup for ARM                                                          */
+;/*  Version     V1.0                                                         */
+;/*  Date        2018-10-13                                                     */
+;/*  Target-mcu  HC32F460                                                     */
+;/*****************************************************************************/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00008000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; Peripheral Interrupts
+                DCD     IRQ000_Handler        ; IRQ000_Handler
+                DCD     IRQ001_Handler        ; IRQ001_Handler
+                DCD     IRQ002_Handler        ; IRQ002_Handler
+                DCD     IRQ003_Handler        ; IRQ003_Handler
+                DCD     IRQ004_Handler        ; IRQ004_Handler
+                DCD     IRQ005_Handler        ; IRQ005_Handler
+                DCD     IRQ006_Handler        ; IRQ006_Handler
+                DCD     IRQ007_Handler        ; IRQ007_Handler
+                DCD     IRQ008_Handler        ; IRQ008_Handler
+                DCD     IRQ009_Handler        ; IRQ009_Handler
+                DCD     IRQ010_Handler        ; IRQ010_Handler
+                DCD     IRQ011_Handler        ; IRQ011_Handler
+                DCD     IRQ012_Handler        ; IRQ012_Handler
+                DCD     IRQ013_Handler        ; IRQ013_Handler
+                DCD     IRQ014_Handler        ; IRQ014_Handler
+                DCD     IRQ015_Handler        ; IRQ015_Handler
+                DCD     IRQ016_Handler        ; IRQ016_Handler
+                DCD     IRQ017_Handler        ; IRQ017_Handler
+                DCD     IRQ018_Handler        ; IRQ018_Handler
+                DCD     IRQ019_Handler        ; IRQ019_Handler
+                DCD     IRQ020_Handler        ; IRQ020_Handler
+                DCD     IRQ021_Handler        ; IRQ021_Handler
+                DCD     IRQ022_Handler        ; IRQ022_Handler
+                DCD     IRQ023_Handler        ; IRQ023_Handler
+                DCD     IRQ024_Handler        ; IRQ024_Handler
+                DCD     IRQ025_Handler        ; IRQ025_Handler
+                DCD     IRQ026_Handler        ; IRQ026_Handler
+                DCD     IRQ027_Handler        ; IRQ027_Handler
+                DCD     IRQ028_Handler        ; IRQ028_Handler
+                DCD     IRQ029_Handler        ; IRQ029_Handler
+                DCD     IRQ030_Handler        ; IRQ030_Handler
+                DCD     IRQ031_Handler        ; IRQ031_Handler
+                DCD     IRQ032_Handler        ; IRQ032_Handler
+                DCD     IRQ033_Handler        ; IRQ033_Handler
+                DCD     IRQ034_Handler        ; IRQ034_Handler
+                DCD     IRQ035_Handler        ; IRQ035_Handler
+                DCD     IRQ036_Handler        ; IRQ036_Handler
+                DCD     IRQ037_Handler        ; IRQ037_Handler
+                DCD     IRQ038_Handler        ; IRQ038_Handler
+                DCD     IRQ039_Handler        ; IRQ039_Handler
+                DCD     IRQ040_Handler        ; IRQ040_Handler
+                DCD     IRQ041_Handler        ; IRQ041_Handler
+                DCD     IRQ042_Handler        ; IRQ042_Handler
+                DCD     IRQ043_Handler        ; IRQ043_Handler
+                DCD     IRQ044_Handler        ; IRQ044_Handler
+                DCD     IRQ045_Handler        ; IRQ045_Handler
+                DCD     IRQ046_Handler        ; IRQ046_Handler
+                DCD     IRQ047_Handler        ; IRQ047_Handler
+                DCD     IRQ048_Handler        ; IRQ048_Handler
+                DCD     IRQ049_Handler        ; IRQ049_Handler
+                DCD     IRQ050_Handler        ; IRQ050_Handler
+                DCD     IRQ051_Handler        ; IRQ051_Handler
+                DCD     IRQ052_Handler        ; IRQ052_Handler
+                DCD     IRQ053_Handler        ; IRQ053_Handler
+                DCD     IRQ054_Handler        ; IRQ054_Handler
+                DCD     IRQ055_Handler        ; IRQ055_Handler
+                DCD     IRQ056_Handler        ; IRQ056_Handler
+                DCD     IRQ057_Handler        ; IRQ057_Handler
+                DCD     IRQ058_Handler        ; IRQ058_Handler
+                DCD     IRQ059_Handler        ; IRQ059_Handler
+                DCD     IRQ060_Handler        ; IRQ060_Handler
+                DCD     IRQ061_Handler        ; IRQ061_Handler
+                DCD     IRQ062_Handler        ; IRQ062_Handler
+                DCD     IRQ063_Handler        ; IRQ063_Handler
+                DCD     IRQ064_Handler        ; IRQ064_Handler
+                DCD     IRQ065_Handler        ; IRQ065_Handler
+                DCD     IRQ066_Handler        ; IRQ066_Handler
+                DCD     IRQ067_Handler        ; IRQ067_Handler
+                DCD     IRQ068_Handler        ; IRQ068_Handler
+                DCD     IRQ069_Handler        ; IRQ069_Handler
+                DCD     IRQ070_Handler        ; IRQ070_Handler
+                DCD     IRQ071_Handler        ; IRQ071_Handler
+                DCD     IRQ072_Handler        ; IRQ072_Handler
+                DCD     IRQ073_Handler        ; IRQ073_Handler
+                DCD     IRQ074_Handler        ; IRQ074_Handler
+                DCD     IRQ075_Handler        ; IRQ075_Handler
+                DCD     IRQ076_Handler        ; IRQ076_Handler
+                DCD     IRQ077_Handler        ; IRQ077_Handler
+                DCD     IRQ078_Handler        ; IRQ078_Handler
+                DCD     IRQ079_Handler        ; IRQ079_Handler
+                DCD     IRQ080_Handler        ; IRQ080_Handler
+                DCD     IRQ081_Handler        ; IRQ081_Handler
+                DCD     IRQ082_Handler        ; IRQ082_Handler
+                DCD     IRQ083_Handler        ; IRQ083_Handler
+                DCD     IRQ084_Handler        ; IRQ084_Handler
+                DCD     IRQ085_Handler        ; IRQ085_Handler
+                DCD     IRQ086_Handler        ; IRQ086_Handler
+                DCD     IRQ087_Handler        ; IRQ087_Handler
+                DCD     IRQ088_Handler        ; IRQ088_Handler
+                DCD     IRQ089_Handler        ; IRQ089_Handler
+                DCD     IRQ090_Handler        ; IRQ090_Handler
+                DCD     IRQ091_Handler        ; IRQ091_Handler
+                DCD     IRQ092_Handler        ; IRQ092_Handler
+                DCD     IRQ093_Handler        ; IRQ093_Handler
+                DCD     IRQ094_Handler        ; IRQ094_Handler
+                DCD     IRQ095_Handler        ; IRQ095_Handler
+                DCD     IRQ096_Handler        ; IRQ096_Handler
+                DCD     IRQ097_Handler        ; IRQ097_Handler
+                DCD     IRQ098_Handler        ; IRQ098_Handler
+                DCD     IRQ099_Handler        ; IRQ099_Handler
+                DCD     IRQ100_Handler        ; IRQ100_Handler
+                DCD     IRQ101_Handler        ; IRQ101_Handler
+                DCD     IRQ102_Handler        ; IRQ102_Handler
+                DCD     IRQ103_Handler        ; IRQ103_Handler
+                DCD     IRQ104_Handler        ; IRQ104_Handler
+                DCD     IRQ105_Handler        ; IRQ105_Handler
+                DCD     IRQ106_Handler        ; IRQ106_Handler
+                DCD     IRQ107_Handler        ; IRQ107_Handler
+                DCD     IRQ108_Handler        ; IRQ108_Handler
+                DCD     IRQ109_Handler        ; IRQ109_Handler
+                DCD     IRQ110_Handler        ; IRQ110_Handler
+                DCD     IRQ111_Handler        ; IRQ111_Handler
+                DCD     IRQ112_Handler        ; IRQ112_Handler
+                DCD     IRQ113_Handler        ; IRQ113_Handler
+                DCD     IRQ114_Handler        ; IRQ114_Handler
+                DCD     IRQ115_Handler        ; IRQ115_Handler
+                DCD     IRQ116_Handler        ; IRQ116_Handler
+                DCD     IRQ117_Handler        ; IRQ117_Handler
+                DCD     IRQ118_Handler        ; IRQ118_Handler
+                DCD     IRQ119_Handler        ; IRQ119_Handler
+                DCD     IRQ120_Handler        ; IRQ120_Handler
+                DCD     IRQ121_Handler        ; IRQ121_Handler
+                DCD     IRQ122_Handler        ; IRQ122_Handler
+                DCD     IRQ123_Handler        ; IRQ123_Handler
+                DCD     IRQ124_Handler        ; IRQ124_Handler
+                DCD     IRQ125_Handler        ; IRQ125_Handler
+                DCD     IRQ126_Handler        ; IRQ126_Handler
+                DCD     IRQ127_Handler        ; IRQ127_Handler
+                DCD     IRQ128_Handler        ; IRQ128_Handler
+                DCD     IRQ129_Handler        ; IRQ129_Handler
+                DCD     IRQ130_Handler        ; IRQ130_Handler
+                DCD     IRQ131_Handler        ; IRQ131_Handler
+                DCD     IRQ132_Handler        ; IRQ132_Handler
+                DCD     IRQ133_Handler        ; IRQ133_Handler
+                DCD     IRQ134_Handler        ; IRQ134_Handler
+                DCD     IRQ135_Handler        ; IRQ135_Handler
+                DCD     IRQ136_Handler        ; IRQ136_Handler
+                DCD     IRQ137_Handler        ; IRQ137_Handler
+                DCD     IRQ138_Handler        ; IRQ138_Handler
+                DCD     IRQ139_Handler        ; IRQ139_Handler
+                DCD     IRQ140_Handler        ; IRQ140_Handler
+                DCD     IRQ141_Handler        ; IRQ141_Handler
+                DCD     IRQ142_Handler        ; IRQ142_Handler
+                DCD     IRQ143_Handler        ; IRQ143_Handler
+
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+SET_SRAM3_WAIT
+                LDR     R0, =0x40050804
+                MOV     R1, #0x77
+                STR     R1, [R0]
+
+                LDR     R0, =0x4005080C
+                MOV     R1, #0x77
+                STR     R1, [R0]
+
+                LDR     R0, =0x40050800
+                MOV     R1, #0x1100
+                STR     R1, [R0]
+
+                LDR     R0, =0x40050804
+                MOV     R1, #0x76
+                STR     R1, [R0]
+
+                LDR     R0, =0x4005080C
+                MOV     R1, #0x76
+                STR     R1, [R0]
+
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  IRQ000_Handler        [WEAK]
+                EXPORT  IRQ001_Handler        [WEAK]
+                EXPORT  IRQ002_Handler        [WEAK]
+                EXPORT  IRQ003_Handler        [WEAK]
+                EXPORT  IRQ004_Handler        [WEAK]
+                EXPORT  IRQ005_Handler        [WEAK]
+                EXPORT  IRQ006_Handler        [WEAK]
+                EXPORT  IRQ007_Handler        [WEAK]
+                EXPORT  IRQ008_Handler        [WEAK]
+                EXPORT  IRQ009_Handler        [WEAK]
+                EXPORT  IRQ010_Handler        [WEAK]
+                EXPORT  IRQ011_Handler        [WEAK]
+                EXPORT  IRQ012_Handler        [WEAK]
+                EXPORT  IRQ013_Handler        [WEAK]
+                EXPORT  IRQ014_Handler        [WEAK]
+                EXPORT  IRQ015_Handler        [WEAK]
+                EXPORT  IRQ016_Handler        [WEAK]
+                EXPORT  IRQ017_Handler        [WEAK]
+                EXPORT  IRQ018_Handler        [WEAK]
+                EXPORT  IRQ019_Handler        [WEAK]
+                EXPORT  IRQ020_Handler        [WEAK]
+                EXPORT  IRQ021_Handler        [WEAK]
+                EXPORT  IRQ022_Handler        [WEAK]
+                EXPORT  IRQ023_Handler        [WEAK]
+                EXPORT  IRQ024_Handler        [WEAK]
+                EXPORT  IRQ025_Handler        [WEAK]
+                EXPORT  IRQ026_Handler        [WEAK]
+                EXPORT  IRQ027_Handler        [WEAK]
+                EXPORT  IRQ028_Handler        [WEAK]
+                EXPORT  IRQ029_Handler        [WEAK]
+                EXPORT  IRQ030_Handler        [WEAK]
+                EXPORT  IRQ031_Handler        [WEAK]
+                EXPORT  IRQ032_Handler        [WEAK]
+                EXPORT  IRQ033_Handler        [WEAK]
+                EXPORT  IRQ034_Handler        [WEAK]
+                EXPORT  IRQ035_Handler        [WEAK]
+                EXPORT  IRQ036_Handler        [WEAK]
+                EXPORT  IRQ037_Handler        [WEAK]
+                EXPORT  IRQ038_Handler        [WEAK]
+                EXPORT  IRQ039_Handler        [WEAK]
+                EXPORT  IRQ040_Handler        [WEAK]
+                EXPORT  IRQ041_Handler        [WEAK]
+                EXPORT  IRQ042_Handler        [WEAK]
+                EXPORT  IRQ043_Handler        [WEAK]
+                EXPORT  IRQ044_Handler        [WEAK]
+                EXPORT  IRQ045_Handler        [WEAK]
+                EXPORT  IRQ046_Handler        [WEAK]
+                EXPORT  IRQ047_Handler        [WEAK]
+                EXPORT  IRQ048_Handler        [WEAK]
+                EXPORT  IRQ049_Handler        [WEAK]
+                EXPORT  IRQ050_Handler        [WEAK]
+                EXPORT  IRQ051_Handler        [WEAK]
+                EXPORT  IRQ052_Handler        [WEAK]
+                EXPORT  IRQ053_Handler        [WEAK]
+                EXPORT  IRQ054_Handler        [WEAK]
+                EXPORT  IRQ055_Handler        [WEAK]
+                EXPORT  IRQ056_Handler        [WEAK]
+                EXPORT  IRQ057_Handler        [WEAK]
+                EXPORT  IRQ058_Handler        [WEAK]
+                EXPORT  IRQ059_Handler        [WEAK]
+                EXPORT  IRQ060_Handler        [WEAK]
+                EXPORT  IRQ061_Handler        [WEAK]
+                EXPORT  IRQ062_Handler        [WEAK]
+                EXPORT  IRQ063_Handler        [WEAK]
+                EXPORT  IRQ064_Handler        [WEAK]
+                EXPORT  IRQ065_Handler        [WEAK]
+                EXPORT  IRQ066_Handler        [WEAK]
+                EXPORT  IRQ067_Handler        [WEAK]
+                EXPORT  IRQ068_Handler        [WEAK]
+                EXPORT  IRQ069_Handler        [WEAK]
+                EXPORT  IRQ070_Handler        [WEAK]
+                EXPORT  IRQ071_Handler        [WEAK]
+                EXPORT  IRQ072_Handler        [WEAK]
+                EXPORT  IRQ073_Handler        [WEAK]
+                EXPORT  IRQ074_Handler        [WEAK]
+                EXPORT  IRQ075_Handler        [WEAK]
+                EXPORT  IRQ076_Handler        [WEAK]
+                EXPORT  IRQ077_Handler        [WEAK]
+                EXPORT  IRQ078_Handler        [WEAK]
+                EXPORT  IRQ079_Handler        [WEAK]
+                EXPORT  IRQ080_Handler        [WEAK]
+                EXPORT  IRQ081_Handler        [WEAK]
+                EXPORT  IRQ082_Handler        [WEAK]
+                EXPORT  IRQ083_Handler        [WEAK]
+                EXPORT  IRQ084_Handler        [WEAK]
+                EXPORT  IRQ085_Handler        [WEAK]
+                EXPORT  IRQ086_Handler        [WEAK]
+                EXPORT  IRQ087_Handler        [WEAK]
+                EXPORT  IRQ088_Handler        [WEAK]
+                EXPORT  IRQ089_Handler        [WEAK]
+                EXPORT  IRQ090_Handler        [WEAK]
+                EXPORT  IRQ091_Handler        [WEAK]
+                EXPORT  IRQ092_Handler        [WEAK]
+                EXPORT  IRQ093_Handler        [WEAK]
+                EXPORT  IRQ094_Handler        [WEAK]
+                EXPORT  IRQ095_Handler        [WEAK]
+                EXPORT  IRQ096_Handler        [WEAK]
+                EXPORT  IRQ097_Handler        [WEAK]
+                EXPORT  IRQ098_Handler        [WEAK]
+                EXPORT  IRQ099_Handler        [WEAK]
+                EXPORT  IRQ100_Handler        [WEAK]
+                EXPORT  IRQ101_Handler        [WEAK]
+                EXPORT  IRQ102_Handler        [WEAK]
+                EXPORT  IRQ103_Handler        [WEAK]
+                EXPORT  IRQ104_Handler        [WEAK]
+                EXPORT  IRQ105_Handler        [WEAK]
+                EXPORT  IRQ106_Handler        [WEAK]
+                EXPORT  IRQ107_Handler        [WEAK]
+                EXPORT  IRQ108_Handler        [WEAK]
+                EXPORT  IRQ109_Handler        [WEAK]
+                EXPORT  IRQ110_Handler        [WEAK]
+                EXPORT  IRQ111_Handler        [WEAK]
+                EXPORT  IRQ112_Handler        [WEAK]
+                EXPORT  IRQ113_Handler        [WEAK]
+                EXPORT  IRQ114_Handler        [WEAK]
+                EXPORT  IRQ115_Handler        [WEAK]
+                EXPORT  IRQ116_Handler        [WEAK]
+                EXPORT  IRQ117_Handler        [WEAK]
+                EXPORT  IRQ118_Handler        [WEAK]
+                EXPORT  IRQ119_Handler        [WEAK]
+                EXPORT  IRQ120_Handler        [WEAK]
+                EXPORT  IRQ121_Handler        [WEAK]
+                EXPORT  IRQ122_Handler        [WEAK]
+                EXPORT  IRQ123_Handler        [WEAK]
+                EXPORT  IRQ124_Handler        [WEAK]
+                EXPORT  IRQ125_Handler        [WEAK]
+                EXPORT  IRQ126_Handler        [WEAK]
+                EXPORT  IRQ127_Handler        [WEAK]
+                EXPORT  IRQ128_Handler        [WEAK]
+                EXPORT  IRQ129_Handler        [WEAK]
+                EXPORT  IRQ130_Handler        [WEAK]
+                EXPORT  IRQ131_Handler        [WEAK]
+                EXPORT  IRQ132_Handler        [WEAK]
+                EXPORT  IRQ133_Handler        [WEAK]
+                EXPORT  IRQ134_Handler        [WEAK]
+                EXPORT  IRQ135_Handler        [WEAK]
+                EXPORT  IRQ136_Handler        [WEAK]
+                EXPORT  IRQ137_Handler        [WEAK]
+                EXPORT  IRQ138_Handler        [WEAK]
+                EXPORT  IRQ139_Handler        [WEAK]
+                EXPORT  IRQ140_Handler        [WEAK]
+                EXPORT  IRQ141_Handler        [WEAK]
+                EXPORT  IRQ142_Handler        [WEAK]
+                EXPORT  IRQ143_Handler        [WEAK]
+IRQ000_Handler
+IRQ001_Handler
+IRQ002_Handler
+IRQ003_Handler
+IRQ004_Handler
+IRQ005_Handler
+IRQ006_Handler
+IRQ007_Handler
+IRQ008_Handler
+IRQ009_Handler
+IRQ010_Handler
+IRQ011_Handler
+IRQ012_Handler
+IRQ013_Handler
+IRQ014_Handler
+IRQ015_Handler
+IRQ016_Handler
+IRQ017_Handler
+IRQ018_Handler
+IRQ019_Handler
+IRQ020_Handler
+IRQ021_Handler
+IRQ022_Handler
+IRQ023_Handler
+IRQ024_Handler
+IRQ025_Handler
+IRQ026_Handler
+IRQ027_Handler
+IRQ028_Handler
+IRQ029_Handler
+IRQ030_Handler
+IRQ031_Handler
+IRQ032_Handler
+IRQ033_Handler
+IRQ034_Handler
+IRQ035_Handler
+IRQ036_Handler
+IRQ037_Handler
+IRQ038_Handler
+IRQ039_Handler
+IRQ040_Handler
+IRQ041_Handler
+IRQ042_Handler
+IRQ043_Handler
+IRQ044_Handler
+IRQ045_Handler
+IRQ046_Handler
+IRQ047_Handler
+IRQ048_Handler
+IRQ049_Handler
+IRQ050_Handler
+IRQ051_Handler
+IRQ052_Handler
+IRQ053_Handler
+IRQ054_Handler
+IRQ055_Handler
+IRQ056_Handler
+IRQ057_Handler
+IRQ058_Handler
+IRQ059_Handler
+IRQ060_Handler
+IRQ061_Handler
+IRQ062_Handler
+IRQ063_Handler
+IRQ064_Handler
+IRQ065_Handler
+IRQ066_Handler
+IRQ067_Handler
+IRQ068_Handler
+IRQ069_Handler
+IRQ070_Handler
+IRQ071_Handler
+IRQ072_Handler
+IRQ073_Handler
+IRQ074_Handler
+IRQ075_Handler
+IRQ076_Handler
+IRQ077_Handler
+IRQ078_Handler
+IRQ079_Handler
+IRQ080_Handler
+IRQ081_Handler
+IRQ082_Handler
+IRQ083_Handler
+IRQ084_Handler
+IRQ085_Handler
+IRQ086_Handler
+IRQ087_Handler
+IRQ088_Handler
+IRQ089_Handler
+IRQ090_Handler
+IRQ091_Handler
+IRQ092_Handler
+IRQ093_Handler
+IRQ094_Handler
+IRQ095_Handler
+IRQ096_Handler
+IRQ097_Handler
+IRQ098_Handler
+IRQ099_Handler
+IRQ100_Handler
+IRQ101_Handler
+IRQ102_Handler
+IRQ103_Handler
+IRQ104_Handler
+IRQ105_Handler
+IRQ106_Handler
+IRQ107_Handler
+IRQ108_Handler
+IRQ109_Handler
+IRQ110_Handler
+IRQ111_Handler
+IRQ112_Handler
+IRQ113_Handler
+IRQ114_Handler
+IRQ115_Handler
+IRQ116_Handler
+IRQ117_Handler
+IRQ118_Handler
+IRQ119_Handler
+IRQ120_Handler
+IRQ121_Handler
+IRQ122_Handler
+IRQ123_Handler
+IRQ124_Handler
+IRQ125_Handler
+IRQ126_Handler
+IRQ127_Handler
+IRQ128_Handler
+IRQ129_Handler
+IRQ130_Handler
+IRQ131_Handler
+IRQ132_Handler
+IRQ133_Handler
+IRQ134_Handler
+IRQ135_Handler
+IRQ136_Handler
+IRQ137_Handler
+IRQ138_Handler
+IRQ139_Handler
+IRQ140_Handler
+IRQ141_Handler
+IRQ142_Handler
+IRQ143_Handler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+                END
@@ -0,0 +1,13 @@
+#ifndef __ADS1231__
+#define	__ADS1231__
+
+#include "bsp.h"
+
+void ADS1231_Open(void);
+void ADS1231_SpeedSet(void);
+bool ADS1231_Read(uint32_t *r_data, uint8_t channel);
+void ADS1231_HighSpeedSet(void);
+void ADS1231_LowSpeedSet(void);
+
+#endif
+
@@ -0,0 +1,140 @@
+#ifndef __CAT_ONE_TASK_H
+#define	__CAT_ONE_TASK_H
+#include "main.h"
+#include "Public.h"
+
+#define	CAT_ONE_REV_TIMEOUT_MAX			(10 * 60 * 1000)
+#define	CAT_ONE_REV_LEN_MAX					512
+
+#define	CAT_ONE_POW_ON()						CAT1_POW_ON()
+#define	CAT_ONE_POW_OFF()						CAT1_POW_OFF()
+
+#define	CAT_ONE_LINKA_GET()					CAT1_LINKA_GET()
+#define	CAT_ONE_LINKB_GET()					CAT1_LINKB_GET()
+
+#define	CAT_ONE_DELAY_1MS(X)
+
+// ETH状态机相关宏定义
+#define ETH_RESET_DELAY_TIME_MAX		(5 * 60 * 1000)
+#define ETH_LINK_WAIT_TIME_MAX			(10 * 1000)
+#define ETH_REG_TIMEOUT_MAX				(30 * 1000)
+#define ETH_SEND_TIMEOUT_MAX			(5 * 1000)
+#define ETH_RECV_TIMEOUT_MAX			(60 * 1000)
+#define ETH_SEND_RETRY_MAX				3
+#define ETH_FIRST_REG_DELAY				(5 * 1000)
+
+typedef enum {
+	CAT_ONE_AT_NULL,
+	CAT_ONE_AT,					//开机检测
+	CAT_ONE_ATE0,				//关回显
+	CAT_ONE_CPIN,				//识卡
+	CAT_ONE_IMEI,
+	CAT_ONE_LCCID,			//读卡
+	CAT_ONE_CEREG,			//查询注册状态
+	CAT_ONE_CGPADDR,		//查询IP地址
+	CAT_ONE_CSQ,				//查询信号强度
+	CAT_ONE_LDNSGIP,		//域名解析
+	CAT_ONE_LBS,				//获取基站定位信息
+	CAT_ONE_LIPOPEN,		//设置TCP服务器地址和端口
+	CAT_ONE_LIPSEND,		//发送数据
+	CAT_ONE_LTPCLOSE,		//断开连接
+	CAT_ONE_LBSPARA,
+	CAT_ONE_CCLK,					//获取时间
+	CAT_ONE_AT_CMD_END,
+}CatOneATCMD_m;
+
+typedef enum {
+	CAT_ONE_IDEL,
+	CAT_ONE_INIT,
+	CAT_ONE_TCP_CONN,
+	CAT_ONE_WAIT_CONN,
+	CAT_ONE_SEND_DATA,
+	CAT_ONE_WAIT_SEND,
+	CAT_ONE_REV_DATA,
+	CAT_ONE_REG_SVR,
+	CAT_ONE_WAIT_REV,
+	CAT_ONE_RESET,
+	CAT_ONE_OFF,
+	CAT_ONE_CLOSE_TCP,
+}CatOneStatus_m;
+
+typedef enum {
+	ETH_IDEL,
+	ETH_RESET,
+	ETH_WAIT_LINK,
+	ETH_REG_SVR,
+	ETH_WAIT_SEND,
+	ETH_SEND_DATA,
+	ETH_WAIT_RECV,
+	ETH_OFF,
+}EthStatus_m;
+
+typedef enum {
+	CAT_ONE_RET_NULL,
+	CAT_ONE_RET_OK,
+	CAT_ONE_RET_ERR,
+	CAT_ONE_RET_TIMEOUT,
+}CatOneRetStatus_m;
+
+typedef enum {
+	CAT_ONE_CMD_MODE,
+	CAT_ONE_PT_MODE,
+}CatOneMode_m;
+
+typedef enum {
+	CAT_ONE_2G,
+	CAT_ONE_ATE,
+}CatOneNetType_m;
+
+typedef struct {
+	CatOneStatus_m Cat1Status;
+	CatOneStatus_m NextStatus;
+	CatOneRetStatus_m ATCmdRet;
+	uint32_t CatOne1mSDelayCnt;
+	uint32_t ResetDelayCnt;
+	uint32_t RegisterDelayCnt;
+	uint8_t AtCmdResendCnt;
+	uint8_t AtCmdIdx;
+	CatOneATCMD_m AtCmd;
+	bool RxFlag;
+	uint16_t CSQ;
+	char IMEI[20];
+	char SIM[32];
+	CatOneNetType_m  NetType;
+	bool TcpConnFlag;
+	
+	bool LBSFlag;
+	int Longitude;
+	int Latitude;
+	char CatOneSendBuff[1024];
+	
+	GateWayPara GateWay;	
+	DataRevCallBack CatOneRevCallBack;
+	
+	// ETH状态机相关字段
+	EthStatus_m EthStatus;
+	uint32_t EthResetDelayCnt;
+	uint32_t EthLinkWaitCnt;
+	uint32_t EthRecvTimeoutCnt;
+	uint8_t EthSendRetryCnt;
+	bool EthFirstRegFlag;
+}CatOne_t, *pCatOne_t;
+
+CatOneRetStatus_m CatOneSend(uint8_t *sData, uint16_t sLen);
+void CatOneStart(void);
+void CatOneStop(void);
+void CatOneReset(void);
+void ETHStop(void);
+void ETHReset(void);
+void Cat1DBGOnOff(bool OnOff);
+void CatOneGetLocationInfo(int *Longitude, int *Latitude);
+void CatOneGetIMEIAndSIM(char *Imei, char *Sim);
+bool CatOneGetStatus(void);
+bool CatOneEthSendQueue(uint8_t *sData, uint16_t sLen);
+void CatOneTriggerRegister(void);
+void ETHTriggerRegister(void);
+void ETHApplyNetPara(void);
+void CatOne_Eth_Thread_Entry(void *parameter);
+void EthRxOverhandler(void);
+void CatReadImeiOrSim(char *Imei, char *Sim);
+#endif
@@ -0,0 +1,7 @@
+#ifndef __EPT__
+#define	__EPT__
+
+void Encrypt_Code(unsigned char *data, unsigned char *EPT_data);
+void Decrypt_Code(unsigned char *EPT_data,unsigned char *DPT_data);
+
+#endif
@@ -0,0 +1,11 @@
+#ifndef __LORA_TASK_H
+#define	__LORA_TASK_H
+
+#include "bsp.h"
+#include "sx127x.h"
+
+void Lora_Thread_Entry(void *parameter);
+int LoraRevCallBack(GateWayPara GateWay, uint8_t *rData, uint16_t rLen);
+void LoraInit(void);
+#endif
+
@@ -0,0 +1,330 @@
+#ifndef __PUBLIC_H
+#define	__PUBLIC_H
+
+#include "bsp.h"
+
+#define	LORA_LOWPOWER			//LORA低功耗设备，采用主动上报方式
+
+#define	SENSOR_DATA_LEN_MAX										50
+#define	SENSOR_NUM_MAX												16
+#define	COMMUNIT_NUM_MAX											32
+
+#define	REGISTER_INTERVAL_MAX									(2 * 60)
+#define	COMMUNIT_READ_SENSOR_INTERVAL_MAX			(1 * 60)
+
+#define	LORA_ERR_RESET_DLY_MAX								(10 * 60)				//LORA接收超时复位延时，单位秒
+#define	CAT1_ERR_RESET_DLY_MAX								(60 * 60)				//CAT1接收超时复位延时，单位秒
+
+typedef struct GateWay_t GateWayPara_t, *GateWayPara;
+
+typedef void (*SendData)(uint8_t *sData, uint16_t sLen);
+typedef int (*DataRevCallBack)(GateWayPara GateWay, uint8_t *rData, uint16_t rLen);
+typedef int (*DataRevResCallBack)(GateWayPara GateWay, uint8_t *rData, uint16_t rLen, SendData Response);
+typedef int (*SendDataOrg)(uint8_t *sData);
+
+typedef enum {
+	DEBUG_CH_DBG,
+	DEBUG_CH_RS485_1,
+	DEBUG_CH_RS485_2,
+}DebugChannel_m;
+
+typedef enum {
+	DEV_TYPE_BROADCAST,
+	DEV_TYPE_INC_COMMUNIT = 0x8001,
+	DEV_TYPE_EXT_COMMUNIT,
+	DEV_TYPE_ICE_SENSOR,
+	DEV_TYPE_CRACK_SENSOR,
+	DEV_TYPE_PRESSURE_SENSOR,
+	DEV_TYPE_RAIN_SENSOR,
+}DevType_m;
+
+typedef enum {
+	CATONE_COMM,
+	ETH_COMM,
+}CommType_m;
+
+typedef enum {
+	LORA_COMM,
+	RS485CH1_COMM,
+	RS485CH2_COMM
+}SensorComm_m;
+
+typedef enum {
+	COMM_UNIT_CMD_REG,
+	COMM_UNIT_CMD_CAIL,
+	COMM_UNIT_CMD_READ,
+	COMM_UNIT_CMD_SET_SENSOR_COLL_TIME = 5,
+	COMM_UNIT_CMD_TIME_SYNC,
+	COMM_UNIT_CMD_CONT_LASER = 8,//激光独有指令
+	COMM_UNIT_CMD_END,
+}CommUnitCmd_m;
+
+typedef enum {
+	NET_COMM_CMD_REG,
+	NET_COMM_CMD_CAIL,
+	NET_COMM_CMD_UPDATE,
+	NET_COMM_CMD_READ_GW_INFO,
+	//NET_COMM_CMD_READ_UNIT_INFO,
+	NET_COMM_CMD_GW_PARA_CONFIG,
+	NET_COMM_CMD_HIS_DATA,
+	NET_COMM_CMD_ADD_UNIT,
+	NET_COMM_CMD_LP_DEV_CONFIG,
+	NET_COMM_CMD_ALARM,
+	NET_COMM_CMD_CONT_LASER,//激光独有指令
+	NET_COMM_CMD_END,
+}NetCommCmd_m;
+
+typedef enum {
+	SENSOR_TYPE_NULL,								//0x0000 空设备
+	FORCE_6D,										//0x0001 六维应力
+	OSMOTIC_PRESSURE,								//0x0002 渗透压
+	ELASTIC_WAVEGUIDE,							//0x0003 弹性波导
+	DIELECTRIC_MASS,								//0x0004 介电质普
+	VIBRATE_SENSOR,								//0x0005 微振动传感器
+	CONT_DEFOR_3D,									//0x0006 三维连续变形
+	COMM_UNIT,										//0x0007 通讯单元
+	FORCE_3D,										//0x0008 三维应力
+	LASER_TRACING,									//0x0009 激光示踪
+	WATER_LEVEL,									//0x000A 水位计
+	_0x000B,											//0x000B 保留
+	_0x000C,											//0x000C 保留	
+	MULTI_PARAMETER_FUSION,						//0x000D 多参数融合
+	CRACK_DETECTION,								//0x000E 裂缝仪
+	_0x000F,											//0x000F 保留
+	ATTITUDE_MONITOR,								//0x0010 姿态检测
+	LASER_DISPLACE,								//0x0011 激光位移
+	REBAR_STRESS,									//0x0012 钢筋应力
+	ANCHOR_ROD_STRESS,							//0x0013 锚杆轴力
+	SURFACE_STRESS,								//0x0014 表面应力
+	PRESSURE,										//0x0015 压力
+	MICROWAVE_DISPLACE,							//0x0016 微波位移 
+	DISPLACEMENT = 0x0020,						//0x0020 位移监测传感器
+}SensorType_m;
+
+typedef struct {//主设备固定包头
+	uint8_t BatLevel;								//电池电量
+	int8_t RSSI;									//信号强度
+	int8_t Nsr;										//信噪比
+}__attribute__ ((packed))MasterDev_T,*MasterDevDp;
+
+typedef struct {
+	int16_t AccX;
+	int16_t AccY;
+	int16_t AccZ;
+	int32_t Strain1;
+	int32_t Strain2;
+	int32_t Strain3;
+	int32_t Strain4;
+	int32_t Strain5;
+	int32_t Strain6;
+}__attribute__((packed))Force6D_T;
+
+typedef struct {
+	MasterDev_T MasterDev;
+	int16_t PitchAngle;							//俯仰角偏斜	（范围±900）单位0.1°
+	int16_t RollAngle;								//横滚角偏斜	（范围±900）单位0.1°
+	int16_t YawAngle;								//偏航角偏斜	（范围0~3600）单位0.1°
+}__attribute__((packed))LaserTracingType_T;
+
+typedef struct {//0x0020 位移计
+  MasterDev_T MasterDev;
+	int16_t PitchAngle;							//俯仰角偏斜（范围±900）单位0.1°
+	int16_t RollAngle;								//横滚角偏斜（范围±900）单位0.1°
+	int16_t YawAngle;								//偏航角偏斜（范围0~3600）单位0.1°
+  float Temp;                     //温度
+	float Altitude;									//海拔（）单位cm
+	int16_t Distance;								//1轴应力值转位移（范围±300,单位0.1mm）
+}__attribute__ ((packed))Displacement_T,*DisplacementDp;
+
+typedef struct {
+	int Distance;
+}__attribute__((packed))LaserDistanceSensorType_t;
+
+typedef struct {
+	uint8_t CommDevAddr[6];			//通讯单元地址
+	uint16_t CollectInterval;		//采集时间间隔
+	uint16_t ReportInterval;		//上报时间间隔
+	uint8_t ERInterval;				//紧急上报时间间隔
+	uint8_t ERTime;						//紧急上报时长
+}__attribute__((packed))SvrDownLPDevConfigPara_t;
+
+typedef struct {
+	uint8_t AlarmType;
+	uint8_t AlarmState;
+	uint8_t AlarmPara;
+}__attribute__((packed))GateWayAlarmType_t;
+
+#define	LW_DEV_COLLECT_INTERVAL_MAX					300//默认300秒
+#define	LW_DEV_REPORT_INTERVAL_MAX						20//20分钟
+#define	LW_DEV_ER_INTERVAL_MAX							2//2分钟
+#define	LW_DEV_ER_TIME_MAX								20//20分钟
+
+typedef struct {
+	uint16_t CollectInterval;		//采集时间间隔
+	uint16_t ReportInterval;		//上报时间间隔
+	uint8_t ERInterval;				//紧急上报时间间隔
+	uint8_t ERTime;						//紧急上报时长
+	uint32_t TimeStamp;				//时间戳
+}__attribute__((packed))LPDevConfigPara_t;
+
+typedef struct {
+	bool RegFlag;
+	bool RevNewDataFlag;
+	bool CommStatus;	//通讯状态，1-在线，0-离线
+	bool	CailFlag;	//校准标志（低功耗）
+	bool	TimeSyncFlag;	//时间同步标志（低功耗）
+	bool	ContLaser;	//激光控制标志（低功耗）
+	bool	LaserOnOff;	//激光状态（低功耗）
+	uint32_t CommErrCnt;
+	uint8_t MasterMac[6];
+	uint8_t Mac[SENSOR_NUM_MAX][6];//第一位是主设备，后面全是子设备
+	uint8_t BatLevel;
+	int8_t RSSI;									//信号强度
+	int8_t Nsr;										//信噪比
+	uint16_t CUType;
+	uint8_t SensorN;
+	uint16_t SensorType[SENSOR_NUM_MAX];
+	//低功耗设备配置信息
+	bool ConfigFlag;			//配置标志，为1表示有新配置，应答低功耗设备时需要附带发送
+	uint16_t CollectInterval;		//采集时间间隔
+	uint16_t ReportInterval;		//上报时间间隔
+	uint8_t ERInterval;				//紧急上报时间间隔
+	uint8_t ERTime;						//紧急上报时长
+}__attribute__((packed))CommUnitPara_t, *CommUnitPara;
+
+typedef struct {
+	bool ExclFlag;
+	uint8_t ExclMac[6];//需要排除的通讯单元MAC
+}__attribute__((packed))ExclCommUnit_t, *ExclCommUnit;
+
+typedef struct {
+	uint8_t Data[SENSOR_NUM_MAX][SENSOR_DATA_LEN_MAX];
+}__attribute__((packed))CommUnitData_t, *CommUnitData;
+
+typedef struct {
+	CommUnitPara_t Para;
+}__attribute__((packed))CommUnit_t, *CommUnit;
+
+typedef struct {
+	bool Enable;		//串口使能
+	bool CommUnitEnable;		//通讯单元使能，开启（使用内部通讯单元功能，直接和传感器通讯），关闭（直接和RS485类型的通讯单元通讯）
+	bool QuerySensorFlag;		//查询传感器标志
+	bool UpgradeEnable;//升级功能使能
+	uint8_t Power;
+	uint32_t BaudRate;
+	SendData RS485Send;
+	CommUnit_t CUPara;
+  CommUnitData_t CUData;
+}__attribute__((packed))RS485Para_t, *RS485Para;
+
+typedef struct {
+	uint8_t Header;
+	uint8_t GWMac[6];
+	uint8_t DevMac[6];
+	uint8_t Cmd;
+	//uint16_t DevType;
+	uint16_t PayloadLen;
+}__attribute__((packed))CommUnitFrameHeader_t, *CommUnitFrameHeader;
+
+typedef struct {
+	uint8_t Header;
+	uint8_t GWMac[6];
+	//uint8_t SvrMac[6];
+	uint8_t Cmd;
+	uint8_t BatLevel;
+	uint32_t Timestamp;
+	uint8_t PacketNum;
+	uint8_t PacketIdx;
+	uint16_t PayloadLen;
+}__attribute__((packed))NetCommFrameHeader_t, *NetCommFrameHeader;
+
+typedef struct {
+	bool OnOff;
+	SendData LoraSend;
+	uint8_t ucChannel;
+	int8_t ucPower;
+	uint8_t SignalBw;
+	uint8_t SpreadFactor;
+	uint8_t ErrorCoding;
+	uint8_t RegPreamble;
+	uint32_t FreqCent;
+}LoraPara_t, *pLoraPara;
+
+typedef struct {
+	uint8_t DestAddr[4];								//目的服务器地址
+	uint16_t DestPort;									//目的服务器端口
+	uint8_t LocalAddr[4];								//本地客户端地址(预留)
+	uint16_t LocalPort;									//本地客户端端口(预留)
+}LTENetPara_t, *pLTENetPara;
+
+typedef enum {
+	ETH_IP_DHCP,										//动态IP
+	ETH_IP_STATIC,									//静态IP
+}EthIpMode_m;
+
+typedef enum {
+	ETH_MODE_TCP_CLIENT,						//TCP客户端
+	ETH_MODE_TCP_SERVER,						//TCP服务器
+	ETH_MODE_UDP,										//UDP模式
+}EthWorkMode_m;
+
+typedef struct {
+	EthIpMode_m IpMode;								//IP模式：DHCP/静态
+	uint8_t IpAddr[4];								//本地IP地址
+	uint16_t IpPort;									//本地端口
+	EthWorkMode_m WorkMode;						//工作模式
+	uint8_t SubnetMask[4];						//子网掩码
+	uint8_t Gateway[4];								//网关
+	uint8_t DestIp[4];								//目的IP地址
+	uint16_t DestPort;								//目的端口
+}EthNetPara_t, *pEthNetPara;
+
+typedef struct {
+	uint32_t SavFlag;									//存储标志
+	CommType_m Comm;									//网关通讯方式
+	uint8_t GwMac[6];									//网关mac
+	LTENetPara_t LTENet;								//Cat1/4G服务器参数
+	EthNetPara_t EthNet;								//以太网网络参数
+	uint32_t CommUnitReadInterval;				//通讯单元读取时间间隔,单位S
+	CommUnitPara_t CommUnitArray[COMMUNIT_NUM_MAX];			//注册的通讯单元信息
+	ExclCommUnit_t ExclCommUnit[COMMUNIT_NUM_MAX];			//排除的通讯单元信息
+	RS485Para_t Rs485Ch1;							//RS485通道1配置
+	RS485Para_t Rs485Ch2;							//RS485通道2配置
+	uint8_t DebugChannel;							//调试通道
+	LoraPara_t Lora;									//Lora配置
+	bool OutageFlag;									//断电报警标志
+	uint16_t crc16;
+}__attribute__((packed))GWConfigPara_t, *GWConfigPara;
+
+struct GateWay_t{
+	bool TimeSyncFlag;								//时间同步标志
+	bool SvrRegFlag;									//服务器注册标志
+	uint8_t SvrMac[6];								//服务器mac
+	GWConfigPara_t ConfigPara;						//配置参数
+	CommUnitData_t CUDataArray[COMMUNIT_NUM_MAX];
+	uint8_t Battery;									//电池电量
+	uint16_t UploadInterval;						//上传间隔
+	uint32_t HistoryNum;								//历史数据数量
+	DataRevCallBack SvrRevCallBack;				//接收到服务器回调
+	DataRevResCallBack CommUnitRevCallBack;	//通讯单元接收回调
+	rt_mq_t NetSendData_MQ;							//网络发送数据队列，第一个字节用于存储消息长度, 第二字节存储命令字，后为数据
+	rt_mq_t LoraRev_MQ;								//Lora接收消息队列，第一个字节用于存储消息长度，后为数据
+	rt_mutex_t UartRevMutex;
+	
+	uint8_t BatteryReadDlyCnt;		//读取电压延时，单位秒，防止4G发送拉低电池电压，造成断电误报
+};
+
+int Cat1EthRevCallBack(GateWayPara GateWay, uint8_t *rData, uint16_t rLen);
+uint16_t CRC_Modbus(uint16_t wBase, __IO uint8_t *para, uint16_t length);
+uint8_t AsciiToHex(char *ASCData, uint8_t *HexData, uint8_t sLen);
+void HexToAscii(uint8_t *HexData, char *ASCData, uint8_t sLen);
+int NetCommOrgData(GateWayPara GateWay, uint8_t *MegData, uint8_t *OutData);
+int CommUnitAnalyze(GateWayPara GateWay, uint8_t *rData, uint16_t rLen, SendData Response);
+void DebugAnalyze(GateWayPara GateWay, uint8_t *rData, uint16_t rLen);
+void CommUnitCmdSend(GateWayPara GateWay, uint8_t *CommUnitMac, CommUnitCmd_m Cmd, uint8_t *Payload, uint16_t PayloadLen, SendData Send);
+int CheckCommUnitReg(GateWayPara GateWay, uint8_t *CommUnitMac);
+int CheckCommUnitExcl(GateWayPara GateWay, uint8_t *CommUnitMac);
+int CommUintOrgData(GateWayPara GateWay, CommUnitPara CUPara, CommUnitData CUData, uint8_t *sData);
+void DebugDisplaySensorData(int SensorIdx, uint16_t SensorType, uint8_t *SensorData);
+#endif
+
@@ -0,0 +1,14 @@
+#ifndef __PUBLIC_TYPES_H
+#define	__PUBLIC_TYPES_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+typedef void (*ReadPara)(pSFBTPara rPara);
+typedef void (*SavPara)(pSFBTPara wPara);
+typedef void (*UartSend)(uint8_t *sData, int sLen);
+typedef void (*DataRevCallBack)(uint8_t *rData, uint8_t rLen);
+typedef int (*SendDataOrg)(uint8_t *sData);
+
+#endif
+
@@ -0,0 +1,70 @@
+#ifndef __RS485_TASK_H
+#define	__RS485_TASK_H
+
+#include "bsp.h"
+#include "Public.h"
+
+#define	RS485_RX_BUFF_LEN_MAX									64
+
+typedef struct {
+	SensorComm_m Com;
+	uint16_t SensorType;
+}SensorTypes_t;
+
+typedef enum {
+	RS485_OUT_VOLTAGE_OV,
+	RS485_OUT_VOLTAGE_5V,
+	RS485_OUT_VOLTAGE_12V,
+}RS485Vol_m;
+
+typedef struct {
+	uint8_t Header;
+	uint8_t SlvAddr;
+	uint8_t Cmd;
+	//uint16_t DevType;
+	uint8_t PayloadLen;
+}__attribute__((packed))FrameHeader_t, *FrameHeader;
+
+typedef enum {
+	RS485_SENSOR_CMD_NULL,
+	RS485_SENSOR_CMD_CAIL,
+	RS485_SENSOR_CMD_READ,
+	RS485_SENSOR_CMD_QUERY,
+	RS485_SENSOR_CMD_SET_ADDR,
+	RS485_SENSOR_CMD_SET_INV_TIME,
+	RS485_SENSOR_CMD_TIME_SYNC,
+	RS485_SENSOR_CMD_END,
+}RS485SensorCmd_m;
+
+//´«¸ÐÆ÷Êý¾Ý·¢ËÍ½á¹¹Ìå
+typedef struct {
+	bool SendFlag;
+	uint8_t SensorCnt;
+	uint8_t SensorErrCnt[SENSOR_NUM_MAX];
+	uint8_t ReadSensorCnt;
+	int32_t ReadSensorInterval;
+	RS485SensorCmd_m Cmd;
+	uint8_t SensorAddr;
+	uint16_t SensorType;
+	uint8_t CmdParaLen;
+	uint8_t *CmdPara;
+	uint8_t RS485RxBuff[RS485_RX_BUFF_LEN_MAX];
+	uint8_t RS485RxLen;
+	uint8_t RS485TimeOutCnt;
+	uint32_t RS485CommUnitReadTimeDelay;
+	uint8_t SendUnitCommIdx;
+	rt_sem_t RS485Rev_Sem;
+	bool InitOverFlag;
+	CommUnitData_t SensorData;
+}SensorCommPara_t, *SensorCommPara;
+
+void RS485CmdSend(GateWayPara GateWay, uint8_t CommUintAddr, SensorCommPara SensorComm);
+void RS485Ch1_Thread_Entry(void *parameter);
+void RS485Ch2_Thread_Entry(void *parameter);
+void RS485RxOverhandler(void);
+
+extern SensorCommPara_t SComm1Para;
+extern SensorCommPara_t SComm2Para;
+#endif
+
+
@@ -0,0 +1,10 @@
+#ifndef _APP_COMM_H_
+#define _APP_COMM_H_
+
+#include "rtthread.h"
+
+#define BSP_LOG(format,...) do { \
+   rt_kprintf(format, ##__VA_ARGS__); \
+} while (0)
+
+#endif
@@ -0,0 +1,418 @@
+#ifndef __BSP_H
+#define __BSP_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <string.h>
+#include <time.h>
+#include "hc32_ddl.h"
+#include "rtthread.h"
+#include "ff.h"
+
+#define	SOFTWARE_VERSION								10
+#define	HARDWARE_VERSION								12
+
+//#define	USE_BOOTLOADER
+
+//#define FLASH_SECTOR_SIZE           		0x2000ul                     
+//#define FLASH_BASE                  		((uint32_t)0x00000000)   
+//#define FLASH_SIZE                  		(64u * FLASH_SECTOR_SIZE) 
+
+
+//#define SRAM_BASE												((uint32_t)0x1FFF8000)
+//#define RAM_SIZE												0x2F000ul
+
+
+//#define BOOT_SIZE												(4 * FLASH_SECTOR_SIZE)
+//#define	APP_ADDRESS											(FLASH_BASE + BOOT_SIZE)
+
+//#define BOOT_PARA_ADDRESS								(FLASH_SIZE - FLASH_SECTOR_SIZE)
+//#define	BOOT_PARA_SIZE									(FLASH_SECTOR_SIZE)
+
+/* flash rom map  存储分区*/
+//boot 16k
+#define FLASH_BASE                ((uint32_t)0x00000000)  
+#define FLASH_SECTOR_SIZE          0x2000ul    
+
+#define	FLASH_BOOT_BASE			(FLASH_BASE)
+#define	FLASH_BOOT_SIZE			(4*FLASH_SECTOR_SIZE)
+//app
+#define	FLASH_APP_BASE			(FLASH_BOOT_BASE+ FLASH_BOOT_SIZE)
+#define	FLASH_APP_SIZE		    (58*FLASH_SECTOR_SIZE)
+
+//boot info
+#define FLASH_BINFO_BASE		(FLASH_APP_BASE + FLASH_APP_SIZE)
+#define	FLASH_BINFO_SIZE		(1*FLASH_SECTOR_SIZE)
+
+//user config
+#define FLASH_CFG_BASE          (FLASH_BINFO_BASE + FLASH_BINFO_SIZE)
+#define FLASH_CFG_SIZE          (1*FLASH_SECTOR_SIZE)
+
+#define FLASH_CFG_MAGIC         (0xa5)
+
+#define	APP_START_FLAG						0x55AA5A5A
+#define	APP_UPDATE_FLAG						0xA5A5AA55
+
+
+#define	WATCH_DOG					1
+
+#define	DEBUG															1
+#define	USE_SD_CARD												0
+
+#define	RTC_IRQn													Int001_IRQn
+
+#define	LORA_DIO0_IRQn										Int005_IRQn
+
+#define	DBGUART_IRQn											Int006_IRQn
+#define	DBGUART_EI_IRQn										Int007_IRQn
+
+#define	RS485CH1_UART_IRQn								Int008_IRQn
+#define	RS485CH1_UART_EI_IRQn							Int009_IRQn
+
+#define	RS485CH2_UART_IRQn								Int010_IRQn
+#define	RS485CH2_UART_EI_IRQn							Int011_IRQn
+
+#define	ETH_OR_CAT1_UART_IRQn							Int012_IRQn
+#define	ETH_OR_CAT1_UART_EI_IRQn					Int013_IRQn
+
+#define	DBG_RXPIN_IRQn										Int002_IRQn
+
+
+//DEBUG
+#define	DBG_USART_CH											(M4_USART1)
+#define	DBG_USART_RX_PORT									(PortA)
+#define	DBG_USART_RX_PIN									(Pin11)
+#define	DBG_USART_TX_PORT									(PortA)
+#define	DBG_USART_TX_PIN									(Pin12)
+#define	DBG_USART_RX_FUNC									(Func_Usart1_Rx)
+#define DBG_USART_TX_FUNC       	  			(Func_Usart1_Tx)
+#define DBG_USART_RI_NUM									(INT_USART1_RI)
+#define DBG_USART_EI_NUM									(INT_USART1_EI)
+#define DBG_USART_TI_NUM									(INT_USART1_TI)
+#define DBG_USART_TCI_NUM									(INT_USART1_TCI)
+#define	DBG_FCG1_PERIPH										(PWC_FCG1_PERIPH_USART1)
+
+//RS485 Ch1
+#define	RS485_CH1_USART_CH								(M4_USART2)
+#define	RS485_CH1_USART_RX_PORT						(PortA)
+#define	RS485_CH1_USART_RX_PIN						(Pin10)
+#define	RS485_CH1_USART_TX_PORT						(PortA)
+#define	RS485_CH1_USART_TX_PIN						(Pin08)
+#define	RS485_CH1_USART_RX_FUNC						(Func_Usart2_Rx)
+#define RS485_CH1_USART_TX_FUNC       	  (Func_Usart2_Tx)
+#define RS485_CH1_USART_RI_NUM						(INT_USART2_RI)
+#define RS485_CH1_USART_EI_NUM						(INT_USART2_EI)
+#define RS485_CH1_USART_TI_NUM						(INT_USART2_TI)
+#define RS485_CH1_USART_TCI_NUM						(INT_USART2_TCI)
+#define	RS485_CH1_FCG1_PERIPH							(PWC_FCG1_PERIPH_USART2)
+
+#define RS485_CH1_CTRL_PORT               (PortC)
+#define RS485_CH1_CTRL_PIN                (Pin07)
+#define	RS485_CH1_TX()										PORT_SetBits(RS485_CH1_CTRL_PORT, RS485_CH1_CTRL_PIN)
+#define	RS485_CH1_RX()										PORT_ResetBits(RS485_CH1_CTRL_PORT, RS485_CH1_CTRL_PIN)
+
+#define RS485_CH1_POW_PORT              	(PortC)
+#define RS485_CH1_POW_PIN               	(Pin10)
+#define	RS485_CH1_POW_ON()								PORT_SetBits(RS485_CH1_POW_PORT, RS485_CH1_POW_PIN)
+#define	RS485_CH1_POW_OFF()								PORT_ResetBits(RS485_CH1_POW_PORT, RS485_CH1_POW_PIN)
+
+//#define	RS485_CH1_VOL_CTRL_PORT						(PortA)				
+//#define RS485_CH1_VOL_CTRL_PIN            (Pin15)
+//#define	RS485_CH1_VOL_5V()								PORT_SetBits(RS485_CH1_VOL_CTRL_PORT, RS485_CH1_VOL_CTRL_PIN)
+//#define	RS485_CH1_VOL_12V()								PORT_ResetBits(RS485_CH1_VOL_CTRL_PORT, RS485_CH1_VOL_CTRL_PIN)
+
+//RS485 Ch2
+#define	RS485_CH2_USART_CH								(M4_USART3)
+#define	RS485_CH2_USART_RX_PORT						(PortB)
+#define	RS485_CH2_USART_RX_PIN						(Pin14)
+#define	RS485_CH2_USART_TX_PORT						(PortB)
+#define	RS485_CH2_USART_TX_PIN						(Pin12)
+#define	RS485_CH2_USART_RX_FUNC						(Func_Usart3_Rx)
+#define RS485_CH2_USART_TX_FUNC       	  (Func_Usart3_Tx)
+#define RS485_CH2_USART_RI_NUM						(INT_USART3_RI)
+#define RS485_CH2_USART_EI_NUM						(INT_USART3_EI)
+#define RS485_CH2_USART_TI_NUM						(INT_USART3_TI)
+#define RS485_CH2_USART_TCI_NUM						(INT_USART3_TCI)
+#define	RS485_CH2_FCG1_PERIPH							(PWC_FCG1_PERIPH_USART3)
+
+#define RS485_CH2_CTRL_PORT               (PortB)
+#define RS485_CH2_CTRL_PIN                (Pin13)
+#define	RS485_CH2_TX()										PORT_SetBits(RS485_CH2_CTRL_PORT, RS485_CH2_CTRL_PIN)
+#define	RS485_CH2_RX()										PORT_ResetBits(RS485_CH2_CTRL_PORT, RS485_CH2_CTRL_PIN)
+
+#define RS485_CH2_POW_PORT              	(PortB)
+#define RS485_CH2_POW_PIN               	(Pin02)
+#define	RS485_CH2_POW_ON()								PORT_SetBits(RS485_CH2_POW_PORT, RS485_CH2_POW_PIN)
+#define	RS485_CH2_POW_OFF()								PORT_ResetBits(RS485_CH2_POW_PORT, RS485_CH2_POW_PIN)
+
+//#define	RS485_CH2_VOL_CTRL_PORT						(PortB)				
+//#define RS485_CH2_VOL_CTRL_PIN            (Pin10)
+//#define	RS485_CH2_VOL_5V()								PORT_SetBits(RS485_CH2_VOL_CTRL_PORT, RS485_CH2_VOL_CTRL_PIN)
+//#define	RS485_CH2_VOL_12V()								PORT_ResetBits(RS485_CH2_VOL_CTRL_PORT, RS485_CH2_VOL_CTRL_PIN)
+
+//ETH OR CAT1
+#define	ETH_OR_CAT1_USART_CH							(M4_USART4)
+#define	ETH_OR_CAT1_USART_RX_PORT					(PortB)
+#define	ETH_OR_CAT1_USART_RX_PIN					(Pin09)
+#define	ETH_OR_CAT1_USART_TX_PORT					(PortC)
+#define	ETH_OR_CAT1_USART_TX_PIN					(Pin13)
+#define	ETH_OR_CAT1_USART_RX_FUNC					(Func_Usart4_Rx)
+#define ETH_OR_CAT1_USART_TX_FUNC       	(Func_Usart4_Tx)
+#define ETH_OR_CAT1_USART_RI_NUM					(INT_USART4_RI)
+#define ETH_OR_CAT1_USART_EI_NUM					(INT_USART4_EI)
+#define ETH_OR_CAT1_USART_TI_NUM					(INT_USART4_TI)
+#define ETH_OR_CAT1_USART_TCI_NUM					(INT_USART4_TCI)
+#define	ETH_OR_CAT1_FCG1_PERIPH						(PWC_FCG1_PERIPH_USART4)
+
+#define ETH_OR_CAT1_CTRL_PORT							(PortB)
+#define ETH_OR_CAT1_CTRL_PIN							(Pin08)
+
+#if (HARDWARE_VERSION == 12)
+#define	ETH_ON()													PORT_SetBits(ETH_OR_CAT1_CTRL_PORT, ETH_OR_CAT1_CTRL_PIN)
+#define	CAT1_ON()													PORT_ResetBits(ETH_OR_CAT1_CTRL_PORT, ETH_OR_CAT1_CTRL_PIN)
+#elif (HARDWARE_VERSION >= 13)
+#define	ETH_ON()													PORT_ResetBits(ETH_OR_CAT1_CTRL_PORT, ETH_OR_CAT1_CTRL_PIN)
+#define	CAT1_ON()													PORT_SetBits(ETH_OR_CAT1_CTRL_PORT, ETH_OR_CAT1_CTRL_PIN)
+#endif
+
+//#define ETH_OR_CAT1_TX_CTRL_PORT					(PortH)
+//#define ETH_OR_CAT1_TX_CTRL_PIN						(Pin02)
+//#define	ETH_ON()													{ PORT_SetBits(ETH_OR_CAT1_CTRL_PORT, ETH_OR_CAT1_CTRL_PIN); PORT_SetBits(ETH_OR_CAT1_TX_CTRL_PORT, ETH_OR_CAT1_TX_CTRL_PIN); }
+//#define	CAT1_ON()													{ PORT_ResetBits(ETH_OR_CAT1_CTRL_PORT, ETH_OR_CAT1_CTRL_PIN); PORT_ResetBits(ETH_OR_CAT1_TX_CTRL_PORT, ETH_OR_CAT1_TX_CTRL_PIN);}
+
+#define	CAT1_PWR_KEY_PORT									(PortA)
+#define	CAT1_PWR_KEY_PIN									(Pin03)
+#define	CAT1_PWR_KEY_CLR()								PORT_SetBits(CAT1_PWR_KEY_PORT, CAT1_PWR_KEY_PIN)
+#define	CAT1_PWR_KEY_SET()								PORT_ResetBits(CAT1_PWR_KEY_PORT, CAT1_PWR_KEY_PIN)
+
+#define	CAT1_RESET_PORT										(PortA)
+#define	CAT1_RESET_PIN										(Pin00)
+#define	CAT1_RESET_CLR()									PORT_SetBits(CAT1_RESET_PORT, CAT1_RESET_PIN)
+#define	CAT1_RESET_SET()									PORT_ResetBits(CAT1_RESET_PORT, CAT1_RESET_PIN)
+
+#define	ETH_RESET_PORT										(PortB)
+#define	ETH_RESET_PIN											(Pin05)
+#define	ETH_RESET_SET()										PORT_SetBits(ETH_RESET_PORT, ETH_RESET_PIN)
+#define	ETH_RESET_CLR()										PORT_ResetBits(ETH_RESET_PORT, ETH_RESET_PIN)
+
+#define	ETH_DEF_PORT											(PortB)
+#define	ETH_DEF_PIN												(Pin07)
+#define	ETH_DEF_SET()											PORT_SetBits(ETH_DEF_PORT, ETH_DEF_PIN)
+#define	ETH_DEF_CLR()											PORT_ResetBits(ETH_DEF_PORT, ETH_DEF_PIN)
+
+#define	ETH_LINK_PORT											(PortB)
+#define	ETH_LINK_PIN											(Pin06)
+#define	ETH_LINK_GET()										PORT_GetBit(ETH_LINK_PORT, ETH_LINK_PIN)
+
+/* SPI_MOSI Port/Pin definition */
+#define SPI_NSS_PORT                   	(PortC)
+#define SPI_NSS_PIN                  	  (Pin00)
+#define SPI_NSS_FUNC                 	  (Func_Spi1_Nss0)
+#define	SPI_NSS_SET()										PORT_SetBits(SPI_NSS_PORT, SPI_NSS_PIN)
+#define	SPI_NSS_CLR()										PORT_ResetBits(SPI_NSS_PORT, SPI_NSS_PIN)
+
+/* SPI_SCK Port/Pin definition */
+#define SPI_SCK_PORT                    (PortC)
+#define SPI_SCK_PIN                     (Pin02)
+#define SPI_SCK_FUNC                    (Func_Spi1_Sck)
+
+/* SPI_MOSI Port/Pin definition */
+#define SPI_MOSI_PORT                   (PortC)
+#define SPI_MOSI_PIN                    (Pin03)
+#define SPI_MOSI_FUNC                   (Func_Spi1_Mosi)
+
+/* SPI_MISO Port/Pin definition */
+#define SPI_MISO_PORT                   (PortC)
+#define SPI_MISO_PIN                    (Pin01)
+#define SPI_MISO_FUNC                   (Func_Spi1_Miso)
+
+/* SPI unit and clock definition */
+#define SPI_UNIT                        (M4_SPI1)
+#define SPI_UNIT_CLOCK                  (PWC_FCG1_PERIPH_SPI1)
+
+
+//LORA IO
+/* SPI_SCK Port/Pin definition */
+#define SPI2_SCK_PORT                    (PortC)
+#define SPI2_SCK_PIN                     (Pin04)
+#define SPI2_SCK_FUNC                    (Func_Spi2_Sck)
+
+/* SPI_MOSI Port/Pin definition */
+#define SPI2_MOSI_PORT                   (PortA)
+#define SPI2_MOSI_PIN                    (Pin07)
+#define SPI2_MOSI_FUNC                   (Func_Spi2_Mosi)
+
+/* SPI_MISO Port/Pin definition */
+#define SPI2_MISO_PORT                   (PortA)
+#define SPI2_MISO_PIN                    (Pin06)
+#define SPI2_MISO_FUNC                   (Func_Spi2_Miso)
+
+/* SPI_MOSI Port/Pin definition */
+#define SPI2_NSS_PORT                   	(PortC)
+#define SPI2_NSS_PIN                  	  (Pin05)
+#define SPI2_NSS_FUNC                 	  (Func_Spi2_Nss0)
+#define	SPI2_NSS_SET()										PORT_SetBits(SPI2_NSS_PORT, SPI2_NSS_PIN)
+#define	SPI2_NSS_CLR()										PORT_ResetBits(SPI2_NSS_PORT, SPI2_NSS_PIN)
+
+/* SPI unit and clock definition */
+#define SPI2_UNIT                       	(M4_SPI2)
+#define SPI2_UNIT_CLOCK                 	(PWC_FCG1_PERIPH_SPI2)
+
+#define	LORA_DIO_PORT											(PortA)
+#define	LORA_DIO_PIN											(Pin04)
+#define	LORA_DIO_GET()										PORT_GetBit(LORA_DIO_PORT, LORA_DIO_PIN)
+#define	LORA_DIO_EXIT_CH									(ExtiCh04)
+#define	LORA_DIO_EXIT_SRC									(INT_PORT_EIRQ4)
+
+#define	LORA_RESET_PORT										(PortA)
+#define	LORA_RESET_PIN										(Pin05)
+#define	LORA_RESET_SET()									PORT_SetBits(LORA_RESET_PORT, LORA_RESET_PIN)
+#define	LORA_RESET_CLR()									PORT_ResetBits(LORA_RESET_PORT, LORA_RESET_PIN)
+
+#define	LORA_RXEN_PORT										(PortB)
+#define	LORA_RXEN_PIN											(Pin00)
+#define	LORA_RXEN_SET()										PORT_SetBits(LORA_RXEN_PORT, LORA_RXEN_PIN)
+#define	LORA_RXEN_CLR()										PORT_ResetBits(LORA_RXEN_PORT, LORA_RXEN_PIN)
+
+#define	LORA_TXEN_PORT										(PortB)
+#define	LORA_TXEN_PIN											(Pin01)
+#define	LORA_TXEN_SET()										PORT_SetBits(LORA_TXEN_PORT, LORA_TXEN_PIN)
+#define	LORA_TXEN_CLR()										PORT_ResetBits(LORA_TXEN_PORT, LORA_TXEN_PIN)
+
+#define	LORA_RX_LED_PORT									(PortB)
+#define	LORA_RX_LED_PIN										(Pin03)     
+#define	LORA_RX_LED_SET()									PORT_SetBits(LORA_RX_LED_PORT, LORA_RX_LED_PIN)
+#define	LORA_RX_LED_CLR()									PORT_ResetBits(LORA_RX_LED_PORT, LORA_RX_LED_PIN)	
+#define	LORA_RX_TOGGLE()									PORT_Toggle(LORA_RX_LED_PORT, LORA_RX_LED_PIN)
+
+#define	LORA_POW_PORT											(PortC)      
+#define	LORA_POW_PIN											(Pin06)
+#define	LORA_POW_ON()											PORT_SetBits(LORA_POW_PORT, LORA_POW_PIN)
+#define	LORA_POW_OFF()										PORT_ResetBits(LORA_POW_PORT, LORA_POW_PIN)	
+ 
+#define	POWER_LED_PORT										(PortB)
+#define	POWER_LED_PIN											(Pin04)
+#define	POWER_LED_ON()										PORT_SetBits(POWER_LED_PORT, POWER_LED_PIN)
+#define	POWER_LED_OFF() 									PORT_ResetBits(POWER_LED_PORT, POWER_LED_PIN)	
+#define	POWER_TOGGLE()										PORT_Toggle(POWER_LED_PORT, POWER_LED_PIN)
+
+#if USE_SD_CARD
+#include "sd_card.h"
+/* SDIOC Port/Pin definition */
+#define SDIOC_CD_PORT										  (PortA)
+#define SDIOC_CD_PIN										  (Pin10)
+
+#define SDIOC_CK_PORT										  (PortC)
+#define SDIOC_CK_PIN										  (Pin12)
+
+#define SDIOC_CMD_PORT										(PortD)
+#define SDIOC_CMD_PIN										  (Pin02)
+
+#define SDIOC_D0_PORT										  (PortC)
+#define SDIOC_D0_PIN										  (Pin08)
+
+#define SDIOC_D1_PORT										  (PortC)
+#define SDIOC_D1_PIN										  (Pin09)
+
+#define SDIOC_D2_PORT										  (PortA)
+#define SDIOC_D2_PIN										  (Pin09)
+
+#define SDIOC_D3_PORT										  (PortC)
+#define SDIOC_D3_PIN										  (Pin11)
+
+/* SD sector && count */
+#define SD_SECTOR_START										 (0u)
+#define SD_SECTOR_COUNT										 (4u)
+										  
+/* SDIOC unit */
+#define SDIOC_UNIT										  	(M4_SDIOC1)
+
+en_result_t SdioInit(void);
+bool SDCardErase(uint32_t u32BlkStartAddr, uint32_t u32BlkEndAddr);
+bool SDCardReadBlocks(uint32_t u32BlkStartAddr, uint32_t u32BlkEndAddr, uint8_t *ReadBuff);
+bool SDCardWriteBlocks(uint32_t u32BlkStartAddr, uint32_t u32BlkEndAddr, uint8_t *WriteBuff);
+#endif
+
+#define	BAT_COLL_ADC_CH										(ADC1_CH1)
+
+//帧头结构体
+typedef struct {
+	uint8_t Header;
+	uint8_t SlvAddr;
+	uint8_t Cmd;		
+	uint8_t PayloadLen;
+}update_protocol_hd_t;
+
+//主机下发升级请求载荷结构体
+typedef struct {
+	uint16_t PackageNum;
+	uint32_t AppSize;
+	uint32_t AppCrc32;
+}__attribute__ ((packed))update_protocol_req_t;
+
+//从机请求下发结构体
+typedef struct {
+	uint16_t PackageIndex;
+	uint32_t PackageNum;
+}__attribute__ ((packed))update_protocol_get_t;
+
+//主机应答下发数据结构体
+typedef struct {
+	uint16_t PackageIndex;
+	uint16_t PackageNum;
+	uint8_t  DataLen;
+}__attribute__ ((packed))update_protocol_rsp_t;
+
+typedef struct {
+	uint32_t AppFlag;
+	uint32_t DevType;
+	uint32_t DevAddr;
+	uint32_t UpdateFlag;
+	uint32_t PackageNum;
+	uint32_t AppSize;
+	uint32_t Crc32Check;
+}boot_para_t;
+
+void BSP_Init(void);
+
+void DbgUart_Config(uint32_t BaudRate);
+void DebugUartSend(uint8_t *sData, uint16_t sLen);
+void DbgRxIrqCallback(uint8_t rData);
+
+void RS485Ch1_Config(uint32_t BaudRate);
+void RS485Ch1UartSend(uint8_t *sData, uint16_t sLen);
+void RS485Ch1RxIrqCallback(uint8_t rData);
+
+void RS485Ch2_Config(uint32_t BaudRate);
+void RS485Ch2UartSend(uint8_t *sData, uint16_t sLen);
+void RS485Ch2RxIrqCallback(uint8_t rData);
+
+void EthOrCat1UartSend(uint8_t *sData, uint16_t sLen);
+void EthOrCat1RxIrqCallback(uint8_t rData);
+
+void LoraTxRxIrqCallback(void);
+
+uint16_t Spi1SendReceive(uint16_t sData);
+uint16_t Spi2SendReceive(uint16_t sData);
+
+//void ReadAdcValue(uint16_t *ADValue);
+uint16_t GetADCBuffPoint(void);
+void ADC_Start(void) ;
+
+void FeedDog(void);
+void Error_Handler(void);
+
+int TimeTs(void);
+void TimeShow(uint32_t dwStamp);
+void TimeSync(time_t ts) ;
+void TimeGet(struct tm *cTime);
+void TimeSync2(uint8_t Year, uint8_t Month, uint8_t Day, uint8_t Hour, uint8_t Min, uint8_t Sec);
+
+void FlashWrite(uint32_t Addr, uint32_t *wData, uint8_t wLen);
+void FlashRead(uint32_t Addr,uint32_t *rData, uint8_t rLen);
+void dev_boot_read_param(boot_para_t *pParam);
+int  dev_boot_write_param(boot_para_t  Param);
+//extern stc_sd_handle_t stcSdhandle;
+#endif
+
@@ -0,0 +1,164 @@
+/*******************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file ddl_config.h
+ **
+ ** A detailed description is available at
+ ** @link DdlConfigGroup Ddl Config description @endlink
+ **
+ **   - 2021-04-16  CDT  First version for Device Driver Library config.
+ **
+ ******************************************************************************/
+#ifndef __DDL_CONFIG_H__
+#define __DDL_CONFIG_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup DdlConfigGroup Device Driver Library config(DDLCONFIG)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/*! Chip module on-off define */
+#define DDL_ON                                      (1u)
+#define DDL_OFF                                     (0u)
+
+/**
+ *******************************************************************************
+ ** \brief This is the list of modules to be used in the device driver library
+ ** Select the modules you need to use to DDL_ON.
+ **
+ ** \note DDL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
+ ** properly.
+ **
+ ** \note DDL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
+ ** Library.
+ **
+ ** \note DDL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
+ ******************************************************************************/
+#ifndef BOOT_ENABLE
+#define DDL_ICG_ENABLE                               (DDL_ON)
+#endif
+ 
+//#define DDL_ICG_ENABLE                              (DDL_ON)
+#define DDL_UTILITY_ENABLE                          (DDL_ON)
+#define DDL_PRINT_ENABLE                            (DDL_OFF)
+
+#define DDL_ADC_ENABLE                              (DDL_ON)
+#define DDL_AES_ENABLE                              (DDL_OFF)
+#define DDL_CAN_ENABLE                              (DDL_OFF)
+#define DDL_CLK_ENABLE                              (DDL_ON)
+#define DDL_CMP_ENABLE                              (DDL_OFF)
+#define DDL_CRC_ENABLE                              (DDL_OFF)
+#define DDL_DCU_ENABLE                              (DDL_OFF)
+#define DDL_DMAC_ENABLE                             (DDL_ON)
+#define DDL_EFM_ENABLE                              (DDL_ON)
+#define DDL_EMB_ENABLE                              (DDL_OFF)
+#define DDL_EVENT_PORT_ENABLE                       (DDL_OFF)
+#define DDL_EXINT_NMI_SWI_ENABLE                    (DDL_ON)
+#define DDL_GPIO_ENABLE                             (DDL_ON)
+#define DDL_HASH_ENABLE                             (DDL_OFF)
+#define DDL_I2C_ENABLE                              (DDL_OFF)
+#define DDL_I2S_ENABLE                              (DDL_OFF)
+#define DDL_INTERRUPTS_ENABLE                       (DDL_ON)
+#define DDL_INTERRUPTS_SHARE_ENABLE                 (DDL_OFF)
+#define DDL_KEYSCAN_ENABLE                          (DDL_OFF)
+#define DDL_MPU_ENABLE                              (DDL_OFF)
+#define DDL_OTS_ENABLE                              (DDL_OFF)
+#define DDL_PWC_ENABLE                              (DDL_ON)
+#define DDL_QSPI_ENABLE                             (DDL_OFF)
+#define DDL_RMU_ENABLE                              (DDL_OFF)
+#define DDL_RTC_ENABLE                              (DDL_ON)
+#define DDL_SDIOC_ENABLE                            (DDL_ON)
+#define DDL_SPI_ENABLE                              (DDL_ON)
+#define DDL_SRAM_ENABLE                             (DDL_ON)
+#define DDL_SWDT_ENABLE                             (DDL_ON)
+#define DDL_TIMER0_ENABLE                           (DDL_OFF)
+#define DDL_TIMER4_CNT_ENABLE                       (DDL_OFF)
+#define DDL_TIMER4_EMB_ENABLE                       (DDL_OFF)
+#define DDL_TIMER4_OCO_ENABLE                       (DDL_OFF)
+#define DDL_TIMER4_PWM_ENABLE                       (DDL_OFF)
+#define DDL_TIMER4_SEVT_ENABLE                      (DDL_OFF)
+#define DDL_TIMER6_ENABLE                           (DDL_OFF)
+#define DDL_TIMERA_ENABLE                           (DDL_OFF)
+#define DDL_TRNG_ENABLE                             (DDL_OFF)
+#define DDL_USART_ENABLE                            (DDL_ON)
+#define DDL_USBFS_ENABLE                            (DDL_OFF)
+#define DDL_WDT_ENABLE                              (DDL_OFF)
+
+
+/*! Midware module on-off define */
+#define MW_ON                                       (1u)
+#define MW_OFF                                      (0u)
+
+/**
+ *******************************************************************************
+ ** \brief This is the list of Midware modules to use
+ ** Select the modules you need to use to MW_ON.
+ ******************************************************************************/
+#define MW_FS_ENABLE                                (MW_OFF)
+#define MW_SD_CARD_ENABLE                           (MW_OFF)
+#define MW_W25QXX_ENABLE                            (MW_OFF)
+#define MW_WM8731_ENABLE                            (MW_OFF)
+
+/* BSP on-off define */
+#define BSP_ON                                      (1u)
+#define BSP_OFF                                     (0u)
+
+/**
+ * @brief The following is a list of currently supported BSP boards.
+ */
+#define BSP_EV_HC32F460_LQFP100_V1                  (1u)
+#define BSP_EV_HC32F460_LQFP100_V2                  (2u)
+
+/**
+ * @brief The macro BSP_EV_HC32F460 is used to specify the BSP board currently
+ * in use.
+ * The value should be set to one of the list of currently supported BSP boards.
+ * @note  If there is no supported BSP board or the BSP function is not used,
+ * the value needs to be set to BSP_EV_HC32F460.
+ */
+#define BSP_EV_HC32F460                             (BSP_EV_HC32F460_LQFP100_V2)
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+
+//@} // DdlConfigGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DDL_CONFIG_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,13 @@
+#ifndef __MAIN__H
+#define __MAIN__H
+#include "bsp.h"
+#include "Public.h"
+#include "DebugCmd.h"
+
+#define	MAC_ADDR_TYPE									0//0为测试服务器
+
+extern bool MainDispEn;
+#define	MAIN_DBG_LOG(...)									{ if(MainDispEn) Debug_Printf(__VA_ARGS__);}
+
+void MainDBGOnOff(bool OnOff);
+#endif
@@ -0,0 +1,96 @@
+#ifndef _PROTOCOL_H_
+#define _PROTOCOL_H_
+
+
+#include "stdint.h"
+
+#define PROTOCOL_BUF_MAX (512)
+
+#define PROTOCOL_HEAD    (0x527A)
+
+#define PROTOCOL_FRAME_HEAD_SIZE (7)  // 最小帧长：头(2) + 地址(2) + 命令(1) + 长度(2) + CRC(2) 
+
+#define PROTOCOL_FRAME_MIN_SIZE  (9)  // 最小帧长：头(2) + 地址(2) + 命令(1) + 长度(2) + CRC(2) 
+// 错误码定义
+typedef enum {
+    PROTOCOL_SUCCESS = 0,
+    PROTOCOL_ERR_INVALID_PARAM,
+    PROTOCOL_ERR_BUFFER_OVERFLOW,
+    PROTOCOL_ERR_CRC
+}protocol_err_t;
+
+typedef enum
+{
+  PROTOCOL_CMD_GET_AD =0x81,
+  PROTOCOL_CMD_GET_TP =0x82,
+    
+  PROTOCOL_CMD_SET_ID =0x83,
+  PROTOCOL_CMD_GET_ID =0x84,
+    
+  PROTOCOL_CMD_SET_TP_OFFSET =0x8A,
+  PROTOCOL_CMD_GET_TP_OFFSET =0x8B,
+    
+  PROTOCOL_CMD_RESET_CHANNEL =0x8F,
+    
+}protocol_cmd_t;
+
+typedef struct __attribute__((packed)) {
+    uint8_t status;
+    float   value;    
+} ch_data_t;
+
+typedef struct __attribute__((packed)) {
+    uint8_t dev_status;
+    ch_data_t channels[8]; 
+    uint8_t   reserved[7];    
+} ad_datas_t;
+
+typedef struct __attribute__((packed)) {
+    uint8_t dev_status;
+    ch_data_t channels[8];
+    uint8_t   reserved[7];        
+} tp_datas_t;
+
+typedef struct __attribute__((packed)) {
+    uint8_t id;
+    uint8_t reserved[3];    
+} id_data_t;
+
+typedef struct __attribute__((packed)) {
+    uint8_t id;
+    union{
+      uint8_t bytes[4];
+      float value;    
+    }prams;
+    
+} offset_set_data_t,offset_get_data_t;
+
+typedef struct __attribute__((packed)) {
+    uint8_t id;    
+}offset_get_param_t;
+
+extern  int protocol_pack_frame(
+    uint16_t slave_addr,
+    uint8_t command,const 
+    uint8_t *payload,
+    uint16_t payload_len,
+    uint8_t *buffer,uint16_t buffer_size,
+    uint16_t *packed_len
+);
+
+extern int protocol_unpack_frame(    
+    const uint8_t *frame,
+    uint16_t frame_len,
+    uint16_t *slave_addr,
+    uint8_t *command,
+    uint8_t *payload,
+    uint16_t *payload_len);
+    
+#endif
+
+
+
+
+
+
+
@@ -0,0 +1,45 @@
+/******************************************************************************
+ * @brief    环形缓冲区管理(参考linux/kfifo)
+ *
+ * Copyright (c) 2016~2020, <morro_luo@163.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs: 
+ * Date           Author       Notes 
+ * 2016-05-30     Morro        初版完成
+ ******************************************************************************/
+
+#ifndef _RING_BUF_H_
+#define _RING_BUF_H_
+
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*环形缓冲区管理器*/
+typedef struct {
+     unsigned char *buf;    /*环形缓冲区        */
+     unsigned int size;     /*环形缓冲区        */
+     unsigned int front;    /*头指针            */
+     unsigned int rear;     /*尾指针            */
+}ring_buf_t;
+
+bool ring_buf_init(ring_buf_t *r,unsigned char *buf,unsigned int size);
+
+void ring_buf_clr(ring_buf_t *r);
+
+int ring_buf_len(ring_buf_t *r);
+
+int ring_buf_put(ring_buf_t *r,unsigned char *buf,unsigned int len);
+
+int ring_buf_get(ring_buf_t *r,unsigned char *buf,unsigned int len);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -0,0 +1,76 @@
+#ifndef __SPI_FLASH_H
+#define	__SPI_FLASH_H
+
+#include "bsp.h"
+
+#define	LOG_SAV_FLAG										(0xAA5555AA)
+#define	LOG_INFO_SAV_FLAG								(0xA55A)
+
+#define	SpiFlashClrNss()								SPI_NSS_CLR()
+#define	SpiFlashSetNss()								SPI_NSS_SET()
+
+#define SPIFLASH_CMD_WRITE							0x02  /* Write to Memory instruction */
+#define SPIFLASH_CMD_WRSR								0x01  /* Write Status Register instruction */
+#define SPIFLASH_CMD_WREN								0x06  /* Write enable instruction */
+#define SPIFLASH_CMD_READ								0x03  /* Read from Memory instruction */
+#define SPIFLASH_CMD_RDSR								0x05  /* Read Status Register instruction  */
+#define SPIFLASH_CMD_RDID								0x9F  /* Read identification */
+#define SPIFLASH_CMD_SE									0x20  /* 4KSector Erase instruction */
+#define SPIFLASH_CMD_BE									0xC7  /* Bulk Erase instruction */
+#define SPIFLASH_WIP_FLAG								0x01  /* Write In Progress (WIP) flag */
+#define SPIFLASH_DUMMY_BYTE							0xA5
+#define SPIFLASH_PAGESIZE								0x100
+#define	SPIFLASH_SECTORSIZE							4096
+#define SPIFLASH_M25P128_ID							0x202018
+#define SPIFLASH_M25P64_ID							0x202017
+
+void SpiFlashEraseChip(void);
+void SpiFlashEraseSector(uint32_t SectorAddr);
+void SpiFlashWriteAnyLengthData(uint8_t* wData, uint32_t wAddr, uint16_t wLen);
+void SpiFlashReadAnyLengthData(uint8_t* rData, uint32_t rAddr, uint16_t rLen);
+uint32_t SpiFlashReadId(void);
+
+/* USER CODE BEGIN */
+#define	SPIFLASH_SIZE										16777216
+#define	SPIFLASH_SECTOR_NUM							4096
+
+#define	GATEWEY_PARA_SAV_ADDR										0x00
+#define	GATEWEY_PARA_SAV_SECTOR									0x00
+
+#define	LOG_INFO_START_SECTOR										0x02
+#define	LOG_SAV_START_SECTOR										0x03
+
+//#if (LORA_MODULE == WH_LR36_L)
+//#define	LOG_SAV_SIZE														78
+//#define	LOG_SAV_NUM_SECTOR											52			//每扇区存储数量
+//#else
+//#define	LOG_SAV_SIZE														78  //150
+//#define	LOG_SAV_NUM_SECTOR											52  //27			//每扇区存储数量
+//#endif
+
+#define	LOG_SAV_SIZE_MAX													256
+#define	LOG_SAV_NUM_MAX													((SPIFLASH_SECTOR_NUM - LOG_SAV_START_SECTOR) * LOG_SAV_NUM_SECTOR)
+
+typedef struct {
+	uint32_t LogSavFlag;		//日志存储标志
+	uint32_t LogIdx;				//日志序号
+	uint32_t LogEndAddr;		//日志结束地址
+	uint32_t TimeStamp;			//存储时间
+}LogHeader_t, *LogHeader;
+
+void SavMMC5983Calib(uint8_t *wData, uint32_t wLen);
+void ReadMMC5983Calib(uint8_t *rData, uint32_t rLen);
+
+void LogInit(void);
+uint32_t ReadLogNum(void);
+uint32_t ReadLastLogEndAddr(void);
+uint32_t ReadFirstLogStartAddr(void);
+void SavLogNum(uint32_t LogNum);
+void AddLog(uint8_t *wData, uint32_t wLen);
+int ReadLog(LogHeader Header, uint8_t **wData, uint32_t LogIdx);
+int ReadPara(uint8_t *Para, uint32_t ParaLen);
+int WritePara(uint8_t *Para, uint32_t ParaLen);
+
+/* USER CODE END */
+	
+#endif
@@ -0,0 +1,20 @@
+#ifndef _UPDATE_PROTOCOL_H_
+#define _UPDATE_PROTOCOL_H_
+
+#include "stdint.h"
+
+#define	CRC16_BASE	0xA001
+
+typedef void (*update_send_t)(uint8_t *pBuf,uint16_t len);
+
+void  update_init(update_send_t pCbs);
+
+int   update_unpack(uint8_t* rxData, int rLen,uint8_t *cmd, uint8_t* dev_addr, void *pUser, int *pLen);
+ 
+void  update_send_cmd(uint8_t Cmd, uint16_t Indx, int PageNum);
+
+#endif
+
+
+
+
@@ -0,0 +1,8 @@
+#ifndef _UTILS_H_
+#define _UTILS_H_
+
+#include "stdint.h"
+
+extern uint16_t modbus_crc16(uint8_t *buf, int len);
+
+#endif
@@ -0,0 +1,126 @@
+#include "ADS1231.h"
+
+extern float Temperature; 
+
+
+void ADS1231_Open(void)
+{
+	PDWN1_SET();
+	PDWN2_SET();
+	PDWN3_SET();
+	PDWN4_SET();
+}
+
+void ADS1231_HighSpeedSet(void)
+{
+	SPEED1_SET();
+	SPEED2_SET();
+	SPEED3_SET();
+	SPEED4_SET();
+}
+
+void ADS1231_LowSpeedSet(void)
+{
+	SPEED1_RESET();
+	SPEED2_RESET();
+	SPEED3_RESET();
+	SPEED4_RESET();
+}
+
+uint32_t GpioAGetDout(en_pin_t enPin)
+{
+	return *(uint32_t *)((uint32_t)(&M4_PORT->PIDRA)) & (enPin);
+}
+
+uint32_t GpioBGetDout(en_pin_t enPin)
+{
+	return *(uint32_t *)((uint32_t)(&M4_PORT->PIDRB)) & (enPin);
+}
+
+bool ADS1231_Read(uint32_t *r_data, uint8_t channel) {
+	uint8_t i;
+	uint32_t data = 0;
+	
+	switch(channel) {
+		case 0:
+			if(GpioAGetDout(DRDY_DOUT1_PIN) != 0)
+				return false;
+			
+			for(i = 0; i < 24; i++) {
+				SCLK1_SET();
+				data <<= 0x01;
+				__NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
+				SCLK1_RESET();
+				
+				if(GpioAGetDout(DRDY_DOUT1_PIN) != 0)
+					data |= 0x01;
+			}
+			SCLK1_SET();
+			__NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
+			SCLK1_RESET();
+			break;
+		case 1:
+			if(GpioAGetDout(DRDY_DOUT2_PIN) != 0)
+				return false;
+			
+			for(i = 0; i < 24; i++) {
+				SCLK2_SET();
+				data <<= 0x01;
+				__NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
+				SCLK2_RESET();
+				__NOP(); __NOP(); 
+				if(GpioAGetDout(DRDY_DOUT2_PIN) != 0)
+					data |= 0x01;
+			}
+			SCLK2_SET();
+			__NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
+			SCLK2_RESET();
+			break;
+		case 2:
+			if(GpioBGetDout(DRDY_DOUT3_PIN) != 0)
+				return false;
+			
+			for(i = 0; i < 24; i++) {
+				SCLK3_SET();
+				data <<= 0x01;
+				__NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
+				SCLK3_RESET();
+				if(GpioBGetDout(DRDY_DOUT3_PIN) != 0 )
+					data |= 0x01;
+			}
+			SCLK3_SET();
+			__NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
+			SCLK3_RESET();
+			break;
+		case 3:
+			if(GpioBGetDout(DRDY_DOUT4_PIN) != 0 )
+				return false;
+			
+			for(i = 0; i < 24; i++) {
+				SCLK4_SET();
+				data <<= 0x01;
+				__NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
+				SCLK4_RESET();
+				if(GpioBGetDout(DRDY_DOUT4_PIN) != 0 )
+					data |= 0x01;
+			}
+			SCLK4_SET();
+			__NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
+			SCLK4_RESET();
+			break;
+		default:
+			return false;
+
+	}
+
+	if(data <= 0x00ffffff) {
+		if(data > 0x007fffff)
+			*r_data = data|0xff000000;
+		else
+			*r_data = data;
+	}
+	else 
+		return false;
+	
+	return true;
+}
@@ -0,0 +1,87 @@
+#include "encryption.h"
+
+//从机加密表
+const unsigned char EPT_Table[32][6] = {
+	{1, 6, 4, 2, 3, 5}, {2, 4, 6, 3, 5, 1}, {3, 5, 6, 2, 1, 4}, {5, 3, 2, 1, 4, 6},
+	{4, 2, 3, 1, 5, 6}, {6, 3, 5, 1, 4, 2}, {3, 5, 2, 6, 4, 1}, {2, 5, 4, 3, 1, 6},
+	{2, 4, 1, 5, 3, 6}, {4, 6, 1, 3, 2, 5}, {4, 2, 1, 5, 6, 3}, {3, 2, 6, 5, 1, 4},
+	{2, 6, 5, 1, 4, 3}, {6, 4, 3, 1, 2, 5}, {1, 6, 3, 2, 4, 5}, {5, 3, 4, 6, 2, 1},
+	{5, 3, 1, 2, 6, 4}, {1, 4, 2, 6, 5, 3}, {3, 5, 2, 1, 4, 6}, {6, 1, 4, 2, 3, 5},
+	{4, 1, 2, 5, 3, 6}, {4, 2, 6, 3, 5, 1}, {2, 6, 1, 4, 3, 5}, {4, 3, 1, 5, 6, 2},
+	{5, 1, 2, 4, 6, 3}, {6, 5, 1, 3, 4, 2}, {2, 1, 6, 3, 5, 4}, {1, 5, 6, 3, 4, 2},
+	{3, 6, 5, 4, 2, 1}, {1, 2, 6, 3, 5, 4}, {4, 6, 5, 3, 2, 1}, {5, 3, 4, 2, 6, 1}
+};
+
+//从机解密表：
+const unsigned char DPT_Table[32][5] ={
+	{1, 4, 2, 3, 5}, {2, 4, 3, 5, 1}, {3, 5, 2, 1, 4}, {5, 3, 2, 1, 4},
+	{4, 2, 3, 1, 5}, {3, 5, 1, 4, 2}, {3, 5, 2, 4, 1}, {2, 5, 4, 3, 1},
+	{2, 4, 1, 5, 3}, {4, 1, 3, 2, 5}, {4, 2, 1, 5, 3}, {3, 2, 5, 1, 4},
+	{2, 5, 1, 4, 3}, {4, 3, 1, 2, 5}, {1, 3, 2, 4, 5}, {5, 3, 4, 2, 1},
+	{5, 3, 1, 2, 4}, {1, 4, 2, 5, 3}, {3, 2, 1, 4, 5}, {1, 4, 5, 2, 3},
+	{4, 1, 2, 5, 3}, {4, 2, 3, 5, 1}, {2, 1, 4, 3, 5}, {4, 3, 1, 5, 2},
+	{5, 1, 2, 4, 3}, {5, 1, 3, 4, 2}, {2, 1, 3, 5, 4}, {1, 5, 3, 4, 2},
+	{3, 5, 4, 2, 1}, {1, 2, 3, 5, 4}, {4, 5, 3, 2, 1}, {5, 3, 4, 2, 1}
+};
+
+//数据位加密表：
+const unsigned char EPT_D[32] = {
+	0x23, 0x4c, 0x92, 0x38, 0x52, 0xa4, 0x9a, 0x61, 
+	0x86, 0xc8, 0x70, 0x16, 0x32, 0x58, 0x62, 0x83, 
+	0xa5, 0x16, 0x1c, 0x49, 0x48, 0xc1, 0x8c, 0x91, 
+	0xd0, 0x2c, 0x49, 0x42, 0xc1, 0x8c, 0x98, 0xd0
+};
+
+/****************************************************************/
+/*			加密函数										*/
+/*																	*/
+/*函数入口:	*data,未加密的普通协议数据					*/
+/*																*/
+/*函数出口:	*EPT_data，生成的加密协议				*/
+/****************************************************************/
+void Encrypt_Code(unsigned char *data, unsigned char *EPT_data) {
+	unsigned char Edata[6];
+	unsigned char i = 0;
+	unsigned char check;
+	unsigned char ept_byte;
+
+	check = (data[0]+data[1]+data[2]+data[3]+data[4]+data[5]) % 0xff;
+	ept_byte = check % 32;
+
+	for (i = 0; i < 6; i++) {
+		Edata[i] = ((~(data[i] & EPT_D[ept_byte])) & EPT_D[ept_byte]) | (data[i] & (~EPT_D[ept_byte]));
+	}
+
+	for (i = 0; i < 6; i++) {
+		EPT_data[i] = Edata[EPT_Table[ept_byte][i]-1];
+	}
+
+	EPT_data[6] = ((~(check & 0xaa)) & 0xaa) | (check & 0x55);
+}
+
+/****************************************************************/
+/*						解密函数							*/
+/*																*/
+/*函数入口：	*EPT_data，需要解密的加密协议	*/
+/*																*/	
+/*函数出口：	*DPT_data，生成的普通协议			*/
+/****************************************************************/
+void Decrypt_Code(unsigned char *EPT_data,unsigned char *DPT_data) {
+	unsigned char data[5];
+	unsigned char i = 0;
+	unsigned char check;
+	unsigned char ept_byte;
+
+	check = ((~(EPT_data[5]&0xaa))&0xaa)|(EPT_data[5]&0x55);
+	ept_byte = check % 32;
+
+	for(i=0;i<5;i++) {
+		data[i] = ((~(EPT_data[i]&EPT_D[ept_byte]))&EPT_D[ept_byte])|(EPT_data[i]&(~EPT_D[ept_byte]));
+	}
+	for(i=0;i<5;i++) {
+		DPT_data[DPT_Table[ept_byte][i]-1] = data[i];
+	}
+	DPT_data[5] = check;
+}
+
+
@@ -0,0 +1,212 @@
+#include "LoraTask.h"
+#include "main.h"
+#include "CatOneTask.h"
+#include "DebugCmd.h"
+
+#define	UC_OFFLINE_TIME_INTERVAL_MAX				(2 * 60 * 60)//离线判断最大时间间隔，单位秒
+
+static rt_sem_t LoraDioIRQ_Sem = RT_NULL;
+static rt_thread_t LoraIRQ_Thread = RT_NULL;
+static GateWayPara GateWay;
+
+void LoraSend(uint8_t* pucBuff, uint8_t ucLen)
+{
+	Sx1276LoRaSendBuffer(pucBuff, ucLen);
+}
+
+//Lora接收消息统一放到消息队列，由接收任务处理
+int LoraRevCallBack(GateWayPara GateWay, uint8_t *rData, uint16_t rLen)
+{
+	uint8_t *sData;
+	if(rLen > 255)
+		return -1;
+	
+	sData = rt_malloc(rLen + 5);
+	sData[0] = rLen;
+	
+//	Debug_Printf("Lora Rev: ");
+//	for(int i = 0; i < rLen; i++) {
+//		Debug_Printf("%02x ", rData[i]);
+//	}
+//	Debug_Printf("\r\n");
+	
+	memcpy(&sData[1], rData, rLen);
+	rt_mq_send(GateWay->LoraRev_MQ, sData, rLen + 1);
+	rt_free(sData);
+	return 0;
+}
+
+void LoraIRQ_Thread_Entry(void *parameter)
+{
+	rt_err_t result;
+	static uint16_t LoraErrCnt = 0;
+	
+	Debug_Printf("LoraRev Thread is running！\r\n");
+	while(1) {
+		if(GateWay->ConfigPara.Lora.OnOff == false) {
+			rt_thread_delay(100);
+			continue;
+		}
+			
+		result = rt_sem_take(LoraDioIRQ_Sem, 1000);
+		if(result == RT_EOK) {
+			IsrSx1276LoRaTxRx(GateWay);
+			LoraErrCnt = 0;
+		}
+		else {
+			LoraErrCnt++;
+			if(LoraErrCnt > LORA_ERR_RESET_DLY_MAX) {		//15分钟内没有收到lora数据重启lora模块
+				LoraErrCnt = 0;
+				Debug_Printf("Lora Reset！\r\n");
+				Sx1276LoRaInit(LoraRevCallBack);
+			}
+		}
+	}
+}
+
+static void LoRaSendBuffer(uint8_t* pucBuff, uint16_t ucLen)
+{
+	if(GateWay->ConfigPara.Lora.OnOff == true)
+		Sx1276LoRaSendBuffer(pucBuff, ucLen);
+}
+
+void Lora_Thread_Entry(void *parameter)
+{
+	rt_err_t result;
+#ifndef LORA_LOWPOWER
+	bool UnitCommSendFlag = false;
+	uint8_t SendUnitCommIdx = 0;
+	uint16_t UnitCommReadDelayCnt = 0;
+#endif	
+	uint8_t Payload[256];
+	uint8_t MegData[9];
+	
+	GateWay = (GateWayPara)parameter;
+	
+	while(GateWay->ConfigPara.Lora.OnOff == false) {
+		rt_thread_delay(100);
+	}
+	
+	LoraDioIRQ_Sem  = rt_sem_create("loradioirq_sem",	0, RT_IPC_FLAG_FIFO);
+	if(LoraDioIRQ_Sem == RT_NULL) {
+		Debug_Printf("CatOneIRQ Sem Create Failed!\r\n");
+	}
+	
+	LoraIRQ_Thread = rt_thread_create("LoraIRQ", LoraIRQ_Thread_Entry, NULL, 512, 3, 20);
+	if (LoraIRQ_Thread != RT_NULL)
+		rt_thread_startup(LoraIRQ_Thread);
+	
+	Sx1276LoRaInit(LoraRevCallBack);
+	Debug_Printf("Lora Thread is running！\r\n");
+#ifdef LORA_LOWPOWER
+	while(1) {
+		if(GateWay->ConfigPara.Lora.OnOff == false) {
+			rt_thread_delay(100);
+			continue;
+		}
+		
+		result = rt_mq_recv(GateWay->LoraRev_MQ, Payload, 256, 1000);
+		if(result == RT_EOK) {
+			int ret = GateWay->CommUnitRevCallBack(GateWay, &Payload[1], Payload[0], LoRaSendBuffer);
+			if(ret == 0xff)	//注册信息
+				continue;
+		}
+		else {	//离线判断    
+			for(int i = 0; i < COMMUNIT_NUM_MAX; i++) {
+				if(GateWay->ConfigPara.CommUnitArray[i].RegFlag == true) {
+					if(GateWay->ConfigPara.CommUnitArray[i].CommErrCnt < UC_OFFLINE_TIME_INTERVAL_MAX) {
+						GateWay->ConfigPara.CommUnitArray[i].CommErrCnt++;
+					}
+					else if(GateWay->ConfigPara.CommUnitArray[i].CommStatus) {
+						GateWay->ConfigPara.CommUnitArray[i].CommStatus = 0;
+						MegData[0] = 7;
+						MegData[1] = 0;
+						MegData[2] = COMM_UNIT_CMD_READ;
+						memcpy(&MegData[3], GateWay->ConfigPara.CommUnitArray[i].Mac[0], 6);
+						MegData[9] = GateWay->ConfigPara.CommUnitArray[i].CommStatus;
+						Debug_Printf("The CommUnit is offline.Mac:%02X-%02X-%02X-%02X-%02X-%02X\r\n",
+													GateWay->ConfigPara.CommUnitArray[i].Mac[0][0],
+													GateWay->ConfigPara.CommUnitArray[i].Mac[0][1],
+													GateWay->ConfigPara.CommUnitArray[i].Mac[0][2],
+													GateWay->ConfigPara.CommUnitArray[i].Mac[0][3],
+													GateWay->ConfigPara.CommUnitArray[i].Mac[0][4],
+													GateWay->ConfigPara.CommUnitArray[i].Mac[0][5]);
+						CatOneEthSendQueue(MegData, 10);		//发送离线消息
+					}
+				}
+			}
+		}
+	}
+#else		
+	while(1) {	
+		if(UnitCommSendFlag == false && UnitCommReadDelayCnt >= GateWay->ConfigPara.CommUnitReadInterval) {
+			if(SendUnitCommIdx < COMMUNIT_NUM_MAX) {
+				if(GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].RegFlag && 
+					GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].Mac[2] == 0x01) {
+					GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].RevNewDataFlag = false;	
+					Debug_Printf("Lora Read CommUnit: %02X:%02X:%02X:%02X:%02X:%02X\r\n",
+												GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].Mac[0],
+												GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].Mac[1],
+												GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].Mac[2],
+												GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].Mac[3],
+												GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].Mac[4],
+												GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].Mac[5]);	
+					CommUnitCmdSend(GateWay, GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].Mac[0], COMM_UNIT_CMD_READ, NULL, 0, Sx1276LoRaSendBuffer);
+					UnitCommSendFlag = true;
+				}
+				else {
+					SendUnitCommIdx++;
+					continue;
+				}
+			}
+			else {
+				SendUnitCommIdx = 0;
+				UnitCommReadDelayCnt = 0;
+			}
+		}
+		
+		if(UnitCommReadDelayCnt < GateWay->ConfigPara.CommUnitReadInterval)
+			UnitCommReadDelayCnt++;
+		
+		result = rt_mq_recv(GateWay->LoraRev_MQ, Payload, 256, 1000);
+		if(result == RT_EOK) {
+			int ret = GateWay->CommUnitRevCallBack(GateWay, &Payload[1], Payload[0], Sx1276LoRaSendBuffer);
+			if(ret == 0xff)	//注册信息
+				continue;
+			
+			if(UnitCommSendFlag && GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].RevNewDataFlag) {
+				UnitCommSendFlag = false;
+				SendUnitCommIdx++;
+			}
+		}
+		else if(UnitCommSendFlag) {	//离线判断
+			GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].CommErrCnt++;
+			if(GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].CommErrCnt == 10) {
+				GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].CommErrCnt = 0;
+				if(GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].CommStatus) {
+					GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].CommStatus = 0;
+					MegData[0] = 7;
+					MegData[1] = 0;
+					MegData[2] = COMM_UNIT_CMD_READ;
+					memcpy(&MegData[3], GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].Mac[0], 6);
+					MegData[9] = GateWay->ConfigPara.CommUnitArray[SendUnitCommIdx].CommStatus;
+					CatOneEthSendQueue(MegData, 10);		//发送离线消息
+				}
+			}
+			UnitCommSendFlag = false;
+			SendUnitCommIdx++;
+		}
+	}
+#endif
+}
+
+
+void LoraTxRxIrqCallback(void)
+{
+	rt_sem_release(LoraDioIRQ_Sem);
+}
+
+void LoraInit(void)
+{
+	Sx1276LoRaInit(LoraRevCallBack);
+}
@@ -0,0 +1,623 @@
+#include "main.h"
+#include "RS485Task.h"
+#include "Public.h"
+#include "spiflash.h"
+#include "CatOneTask.h"
+#include "DebugCmd.h"
+#include "update_protocol.h"
+#include "bsp.h"
+
+//#define	RS485_DBG_LOG(...)								{ if(RS485DispEn) Debug_Printf(__VA_ARGS__);}
+
+//static uint8_t RS485DispEn = false;
+
+SensorCommPara_t SComm1Para;
+SensorCommPara_t SComm2Para;
+
+const uint8_t RS485SensorCmdPayLoadLen[RS485_SENSOR_CMD_END] = {0, 0, 0, 1, 0};
+
+/*****************************************************************************************
+* 函数名称: SavSensorData
+* 功能描述: 记录传感器数据
+* 参    数: SensorIdx, 传感器序号
+						Para，传感器结构指针
+						Data, 传感器数据
+						Len, 传感器数据长度
+* 返 回 值: 无
+*****************************************************************************************/
+static void SavSensorData(uint8_t SensorIdx, CommUnitData CUData, uint8_t *Data, uint8_t Len)
+{
+	if(Data == NULL) {
+		memset(CUData->Data[SensorIdx], 0x00, SENSOR_DATA_LEN_MAX);
+	}
+	else {
+		memcpy(CUData->Data[SensorIdx], Data, Len);
+	}
+}
+
+/*****************************************************************************************
+* 函数名称: RS485Analyze
+* 功能描述: 485数据解析
+* 参    数: SCPara, 传感器发送参数
+						Para, 传感器结构指针
+						rData, 传感器数据入口
+						rLen, 传感器数据长度
+* 返 回 值: 无
+*****************************************************************************************/
+void RS485Analyze(GateWayPara GateWay, SensorCommPara SCPara, CommUnit Para, uint8_t *rData, uint8_t rLen)
+{
+	uint16_t crc16;
+	uint8_t *Payload;
+	
+	crc16 = (rData[rLen - 1] << 8)|rData[rLen - 2];
+	uint16_t Check = CRC_Modbus(0xA001, rData, rLen - 2);
+	if(crc16 != Check)
+		return;
+	
+	FrameHeader Header = (FrameHeader)rData;
+	if(Header->Cmd != RS485_SENSOR_CMD_QUERY) {
+		if(Header->SlvAddr != SCPara->SensorAddr)
+			return;
+	}
+	
+	Payload = &rData[sizeof(FrameHeader)];
+	if(Header->PayloadLen == 0)
+		return;
+	
+	if(Header->SlvAddr == 0 || Header->SlvAddr > SENSOR_NUM_MAX)
+		return;
+	
+	SCPara->SensorErrCnt[Header->SlvAddr - 1] = 0;
+	switch(Header->Cmd) {
+		case RS485_SENSOR_CMD_SET_ADDR:
+			if(*Payload == 1) {
+				MAIN_DBG_LOG("Sensor%d Addr Set succeed!\r\n", Header->SlvAddr);
+			}
+			else {
+				MAIN_DBG_LOG("Sensor%d Addr Set failed!\r\n", Header->SlvAddr);
+			}
+			break;
+			
+		case RS485_SENSOR_CMD_CAIL:
+			if(*Payload == 1) {
+				MAIN_DBG_LOG("Sensor%d calibration succeeded!\r\n", Header->SlvAddr);
+			}
+			else {
+				MAIN_DBG_LOG("Sensor%d calibration succeeded!\r\n", Header->SlvAddr);
+			}
+			break;
+		
+		case RS485_SENSOR_CMD_QUERY:
+			if(Para->Para.SensorN < 16) {
+				Para->Para.SensorN++;
+				Para->Para.SensorType[SCPara->SensorAddr - 1] = rData[6] | (rData[7] << 8);
+				MAIN_DBG_LOG("Found Sensor%d, Type: %d!\r\n", Header->SlvAddr, Para->Para.SensorType[SCPara->SensorAddr - 1]);
+			}
+			break;
+			
+		case RS485_SENSOR_CMD_READ: {
+			memcpy(SCPara->SensorData.Data[SCPara->SensorAddr - 1], &rData[sizeof(FrameHeader_t)], Header->PayloadLen);
+			if(SCPara->SendFlag)
+				SCPara->ReadSensorCnt++;
+			DebugDisplaySensorData(Header->SlvAddr, 0, &rData[sizeof(FrameHeader_t)]);
+		}
+
+		default:
+			break;
+	}
+}
+
+static void update_on_start(uint8_t* frame, int len, uint8_t* pload, int size)
+{
+    update_protocol_req_t* pReq = (void*)&frame[sizeof(update_protocol_hd_t)];
+
+	//TODO:
+	
+	 boot_para_t cfg = {0};
+
+    cfg.AppFlag = 0;
+    cfg.UpdateFlag = APP_UPDATE_FLAG;
+    cfg.Crc32Check = pReq->AppCrc32;
+    cfg.PackageNum = pReq->PackageNum;
+    cfg.AppSize    = pReq->AppSize;
+	 /**
+	  操作FALSH ，写升级参数
+	**/
+    dev_boot_write_param(cfg);
+
+    update_send_cmd(0x01, 1, pReq->PackageNum);
+
+    //重启进入BOOT
+    NVIC_SystemReset();
+}
+
+static int update_cmd_process(uint8_t cmd, void* frame, int len, void* pload, int size)
+{
+    int res = -1;
+
+    switch (cmd) {
+        case 0x81: {
+            update_on_start(frame, len, pload,  size);
+
+            res = 0;
+        }
+        break;
+
+        default:
+            break;
+
+    }
+
+    return res;
+}
+
+static int update_process(void* frame, int len)
+{
+       uint8_t  cmd = 0;
+
+    uint8_t  slave_addr = 0;
+
+    uint8_t  user_data[256] = {0};
+
+    int      user_data_len = 0;
+
+    int res = update_unpack(frame, len, &cmd, &slave_addr, user_data, &user_data_len);
+
+    if (res != 0)
+        return -1;
+
+    if (slave_addr != 0x01)
+        return -2;
+
+    res = update_cmd_process(cmd, frame, len, user_data, user_data_len);
+
+    if (res != 0)
+        return -3;
+
+    return 0;
+}
+
+
+/*****************************************************************************************
+* 函数名称: RS485SensorCmdSend
+* 功能描述: 下发传感器指令函数
+* 参    数: Para,通讯参数入口
+* 返 回 值: 无
+*****************************************************************************************/
+static void RS485SensorCmdSend(GateWayPara GateWay, SensorCommPara SensorComm)
+{
+	uint8_t sData[50];
+	uint8_t sLen;
+	
+	if(SensorComm->Cmd >= RS485_SENSOR_CMD_END)
+		return;
+	
+	FrameHeader Header = (FrameHeader)sData;
+	
+	Header->Header = 0x7C;
+	Header->SlvAddr = SensorComm->SensorAddr;
+	Header->Cmd = SensorComm->Cmd;
+	//Header->DevType = SensorComm->SensorType;
+	Header->PayloadLen = SensorComm->CmdParaLen;
+	
+	sLen = sizeof(FrameHeader_t);
+	if(SensorComm->CmdParaLen > 0) {
+		memcpy(&sData[sLen], SensorComm->CmdPara, SensorComm->CmdParaLen);
+		sLen += SensorComm->CmdParaLen;
+	}
+	uint16_t Check = CRC_Modbus(0xA001, sData, sLen);
+	
+	sData[sLen++] = Check & 0xff;
+	sData[sLen++] = (Check >> 0x08) & 0x00ff;
+	
+	if(SensorComm == &SComm1Para)
+		GateWay->ConfigPara.Rs485Ch1.RS485Send(sData, sLen);
+	else
+		GateWay->ConfigPara.Rs485Ch2.RS485Send(sData, sLen);
+}
+
+/*****************************************************************************************
+* 函数名称: RS485SensorCmdSend
+* 功能描述: 下发传感器指令函数
+* 参    数: CommUintAddr， 通讯单元地址
+						Para,通讯参数入口
+* 返 回 值: 无
+*****************************************************************************************/
+void RS485CmdSend(GateWayPara GateWay, uint8_t CommUintAddr, SensorCommPara SensorComm)
+{
+	SensorCommPara SC;
+	
+	if(CommUintAddr)
+		SC = &SComm1Para;
+	else
+		SC = &SComm2Para;
+	
+	SC->Cmd = SensorComm->Cmd;
+	SC->CmdPara = SensorComm->CmdPara;
+	SC->CmdParaLen = SensorComm->CmdParaLen;
+	SC->SensorAddr = SensorComm->SensorAddr;
+	//SC->SensorType = SensorComm->SensorType;
+	
+	RS485SensorCmdSend(GateWay, SC);
+}
+
+
+/*****************************************************************************************
+* 函数名称: RS485LoopHandler
+* 功能描述: RS485循环处理函数
+* 参    数: GateWay, 网关参数句柄
+						RS485Ch, RS485通道句柄
+						SCPara， RS485通讯句柄
+* 返 回 值: 无
+*****************************************************************************************/
+static uint8_t CommUintData[512];
+int test = 0;
+void RS485LoopHandler(GateWayPara GateWay, RS485Para RS485Ch, SensorCommPara SCPara)
+{
+	uint8_t RxBuffTemp[RS485_RX_BUFF_LEN_MAX];
+	uint8_t RxLenTemp;
+	uint16_t CommUintLen;
+	rt_err_t result;
+	uint8_t MegData[9];
+	int ret;
+	
+	if(RS485Ch->Enable == false) {
+		rt_thread_delay(10);
+		return;
+	}
+	
+	if(RS485Ch->CommUnitEnable == true) {				//使用内置通讯单元
+		if(RS485Ch->QuerySensorFlag == true) {		//开机查找传感器
+			if(SCPara->SensorCnt < SENSOR_NUM_MAX) {
+				rt_thread_delay(50);
+				SCPara->Cmd = RS485_SENSOR_CMD_QUERY;
+				SCPara->SensorAddr = SCPara->SensorCnt + 1;
+				SCPara->SensorType = 0;
+				SCPara->CmdParaLen = RS485SensorCmdPayLoadLen[RS485_SENSOR_CMD_QUERY];
+				SCPara->CmdPara = NULL;
+				//rt_mutex_take(GateWay->UartRevMutex, RT_WAITING_FOREVER);
+				SCPara->RS485TimeOutCnt = 0;
+				SCPara->RS485RxLen = 0;
+				RS485SensorCmdSend(GateWay, SCPara);
+				SCPara->SendFlag = true;
+				SCPara->SensorCnt++;
+				if(SCPara->SensorCnt >= SENSOR_NUM_MAX) {
+					SCPara->ReadSensorInterval = 2;
+					SCPara->SensorCnt = 0;
+					SCPara->ReadSensorCnt = 0;
+					RS485Ch->QuerySensorFlag = false;
+				}
+			}
+		}
+		else if(RS485Ch->CUPara.Para.SensorN > 0){
+			SCPara->SendFlag = false;
+			if(SCPara->ReadSensorInterval > 0) {
+				SCPara->ReadSensorInterval--;  
+			}
+			else {
+				if(SCPara->ReadSensorCnt >= RS485Ch->CUPara.Para.SensorN || SCPara->SensorCnt >= SENSOR_NUM_MAX) {
+					SCPara->SensorCnt = 0;
+					SCPara->ReadSensorCnt = 0;
+					SCPara->ReadSensorInterval = GateWay->ConfigPara.CommUnitReadInterval * 5;
+					RS485Ch->CUPara.Para.BatLevel = GateWay->Battery;
+					CommUintLen = CommUintOrgData(GateWay, &RS485Ch->CUPara.Para, &SCPara->SensorData, CommUintData);
+					//AddLog(&CommUintData[2], CommUintLen - 2);
+					CatOneEthSendQueue(CommUintData, CommUintLen);
+					if(RS485Ch == &GateWay->ConfigPara.Rs485Ch1) {
+						MAIN_DBG_LOG("InCommUint1 Send Meg...\r\n");
+					}
+					else {
+						MAIN_DBG_LOG("InCommUint2 Send Meg...\r\n");
+					}
+					SCPara->SensorCnt = 0;
+				}
+				else {
+					if(RS485Ch->CUPara.Para.SensorType[SCPara->SensorCnt] != 0) {
+						rt_thread_delay(50);
+						SCPara->Cmd = RS485_SENSOR_CMD_READ;
+						SCPara->SensorAddr = SCPara->SensorCnt + 1;
+						SCPara->SensorType = RS485Ch->CUPara.Para.SensorType[SCPara->SensorCnt];
+						SCPara->CmdParaLen = RS485SensorCmdPayLoadLen[RS485_SENSOR_CMD_READ];
+						SCPara->CmdPara = NULL;
+						//rt_mutex_take(GateWay->UartRevMutex, RT_WAITING_FOREVER);
+						RS485SensorCmdSend(GateWay, SCPara);
+						SCPara->SendFlag = true;
+					}
+					SCPara->SensorCnt++;
+				}
+			}
+		}
+	}
+	else {		//读取外置通讯单元
+		if(SCPara->RS485CommUnitReadTimeDelay >= (GateWay->ConfigPara.CommUnitReadInterval * 5) && SCPara->SendFlag == false) {
+			if(SCPara->SendUnitCommIdx < COMMUNIT_NUM_MAX) {
+				if(GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].RegFlag && 
+					GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].Mac[0][2] == 0x02) {
+					Debug_Printf("RS485Ch%d Read CommUnit: %02X:%02X:%02X:%02X:%02X:%02X\r\n",
+											((SCPara == &SComm1Para) ? 1 : 2),
+											GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].Mac[0][0],
+											GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].Mac[0][1],
+											GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].Mac[0][2],
+											GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].Mac[0][3],
+											GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].Mac[0][4],
+											GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].Mac[0][5]);
+					CommUnitCmdSend(GateWay, GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].Mac[0], COMM_UNIT_CMD_READ, NULL, 0, RS485Ch->RS485Send);
+					SCPara->SendFlag = true;
+				}
+				else {
+					SCPara->SendUnitCommIdx++;
+					return;
+				}
+			}
+			else {
+				SCPara->SendUnitCommIdx = 0;
+				SCPara->RS485CommUnitReadTimeDelay = 0;
+			}
+		}
+	}
+	
+	if(SCPara->RS485CommUnitReadTimeDelay < (GateWay->ConfigPara.CommUnitReadInterval * 5))
+		SCPara->RS485CommUnitReadTimeDelay++;
+	
+	result = rt_sem_take(SCPara->RS485Rev_Sem, 200);
+	if(result == RT_EOK) {
+		memcpy(RxBuffTemp, SCPara->RS485RxBuff, SCPara->RS485RxLen);
+		RxLenTemp = SCPara->RS485RxLen;
+//		memset(SCPara->RS485RxBuff, 0x00, RS485_RX_BUFF_LEN_MAX);
+		SCPara->RS485RxLen = 0;
+		if(RxBuffTemp[0] == 0x7A && RS485Ch->UpgradeEnable == true) {	//升级
+			update_process(RxBuffTemp,RxLenTemp);
+		}
+		else if(RxBuffTemp[0] == 0x7A && RS485Ch->CommUnitEnable == true) {	//内置通讯单元数据解析
+			if(SCPara->SendFlag == false) {
+				SCPara->RS485RxLen = 0;
+				return;
+			}
+			RS485Analyze(GateWay, SCPara, &RS485Ch->CUData, RxBuffTemp, RxLenTemp);
+			//rt_mutex_release(GateWay->UartRevMutex);
+		}
+		else if(RxBuffTemp[0] == 0x7B && RS485Ch->CommUnitEnable == false){		//读取外部通讯单元数据解析
+			if(SCPara == &SComm1Para)
+				ret = GateWay->CommUnitRevCallBack(GateWay, RxBuffTemp, RxLenTemp, GateWay->ConfigPara.Rs485Ch1.RS485Send);
+			else
+				ret = GateWay->CommUnitRevCallBack(GateWay, RxBuffTemp, RxLenTemp, GateWay->ConfigPara.Rs485Ch2.RS485Send);
+			if(ret == 0xff) {	//注册信息
+				SCPara->RS485RxLen = 0;
+				return;
+			}
+			if(SCPara->SendFlag && GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].RevNewDataFlag) {
+				SCPara->SendUnitCommIdx++;
+			}
+			else {
+				SCPara->RS485RxLen = 0;
+				return;
+			}
+		}
+		else {		//调试命令解析
+			DebugAnalyze(GateWay, RxBuffTemp, RxLenTemp);
+		}
+		SCPara->RS485RxLen = 0;
+		SCPara->SendFlag = false;
+	}
+	else {
+		if(RS485Ch->CommUnitEnable == true) {
+			//rt_mutex_release(GateWay->UartRevMutex);
+			if(SCPara->SendFlag == true) { //&& RS485Ch->CUPara.Para.SensorN > 0 && RS485Ch->QuerySensorFlag == false){
+				if(RS485Ch == &GateWay->ConfigPara.Rs485Ch1) {
+					test++;
+					MAIN_DBG_LOG("InCommUint1, Sensor %d Comm Error, Cmd %d...\r\n", SCPara->SensorAddr, SCPara->Cmd);
+				}
+				else {
+					MAIN_DBG_LOG("InCommUint2, Sensor %d Comm Error, Cmd %d...\r\n", SCPara->SensorAddr, SCPara->Cmd);
+				}
+				SCPara->SensorErrCnt[SCPara->SensorAddr - 1]++;
+				if(SCPara->SensorErrCnt[SCPara->SensorAddr - 1] >= 5)
+					SavSensorData(SCPara->SensorAddr - 1, &SCPara->SensorData, NULL, 0);
+			}
+		}
+		else if(SCPara->SendFlag){
+			GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].CommErrCnt++;
+			if(GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].CommErrCnt == 10) {
+				GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].CommErrCnt = 0;
+				if(GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].CommStatus) {
+					GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].CommStatus = 0;
+					MegData[0] = 7;
+					MegData[1] = COMM_UNIT_CMD_READ;
+					memcpy(&MegData[2], GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].Mac[0], 6);
+					MegData[8] = GateWay->ConfigPara.CommUnitArray[SCPara->SendUnitCommIdx].CommStatus;
+					CatOneEthSendQueue(MegData, 9);		//发送离线消息
+				}
+			}
+			SCPara->SendUnitCommIdx++;
+		}
+		SCPara->SendFlag = false;
+	}
+}
+
+/*****************************************************************************************
+* 函数名称: RS485Ch1_Thread_Entry
+* 功能描述: RS485通道1任务函数
+* 参    数: 任务参数入口
+* 返 回 值: 无
+*****************************************************************************************/
+void RS485Ch1_Thread_Entry(void *parameter)
+{
+	uint8_t InCommUnitMac[6] = {0x01, 0x80, 0x02, 0x00, 0x00, 0x01};
+	GateWayPara GateWay;
+	SensorCommPara SCPara;
+	RS485Para RS485Ch;
+	
+	SCPara = &SComm1Para;
+	SCPara->SensorCnt = 0;
+	SCPara->InitOverFlag = false;
+	SCPara->ReadSensorInterval = 300;
+	GateWay = (GateWayPara)parameter;
+	InCommUnitMac[3] = GateWay->ConfigPara.GwMac[4];
+	InCommUnitMac[4] = GateWay->ConfigPara.GwMac[5];
+	RS485Ch = &GateWay->ConfigPara.Rs485Ch1;
+	memcpy(RS485Ch->CUPara.Para.Mac, InCommUnitMac, 6);
+	if(RS485Ch->CommUnitEnable == true) {
+		RS485_CH1_POW_ON();
+		RS485Ch->CUPara.Para.SensorN = 0;
+		memset(RS485Ch->CUPara.Para.SensorType, 0x00, sizeof(SENSOR_NUM_MAX * 2));
+		RS485Ch->QuerySensorFlag = true;
+		RS485Ch->CUPara.Para.CommStatus = true;
+	}
+	SCPara->RS485CommUnitReadTimeDelay = 100;
+	SCPara->RS485Rev_Sem  = rt_sem_create("rsch1sem",	0, RT_IPC_FLAG_FIFO);
+	if(SCPara->RS485Rev_Sem == RT_NULL) {
+		Debug_Printf("RS485Ch1Rev Sem Create Failed!\r\n");
+	}
+	Debug_Printf("RS485Ch1Rev Thread is running！\r\n");
+
+	rt_thread_delay(3000);
+	SCPara->InitOverFlag = true;
+	
+	
+	update_init(RS485Ch1UartSend);
+	while(1) {
+		RS485LoopHandler(GateWay, RS485Ch, SCPara);
+		//rt_thread_delay(10);
+	}
+}
+
+/*****************************************************************************************
+* 函数名称: RS485Ch1RxIrqCallback
+* 功能描述: RS485通道1中断处理回调函数
+* 参    数: rData 接收到的数据
+* 返 回 值: 无
+*****************************************************************************************/
+void RS485Ch1RxIrqCallback(uint8_t rData)
+{
+	if(SComm1Para.RS485TimeOutCnt == 0) {
+		SComm1Para.RS485RxLen = 0;
+	}
+	if(SComm1Para.RS485RxLen < RS485_RX_BUFF_LEN_MAX)
+		SComm1Para.RS485RxBuff[SComm1Para.RS485RxLen++] = rData;
+	
+	SComm1Para.RS485TimeOutCnt = 3;
+}
+
+/*****************************************************************************************
+* 函数名称: RS485Ch2_Thread_Entry
+* 功能描述: RS485通道1任务函数
+* 参    数: 任务参数入口
+* 返 回 值: 无
+*****************************************************************************************/
+void RS485Ch2_Thread_Entry(void *parameter)
+{
+	uint8_t InCommUnitMac[6] = {0x01, 0x80, 0x02, 0x00, 0x00, 0x02};
+	GateWayPara GateWay;
+	SensorCommPara SCPara;
+	RS485Para RS485Ch;
+	
+	SCPara = &SComm2Para;
+	SCPara->SensorCnt = 0;
+	SCPara->InitOverFlag = false;
+	SCPara->ReadSensorInterval = 0;
+	GateWay = (GateWayPara)parameter;
+	InCommUnitMac[3] = GateWay->ConfigPara.GwMac[4];
+	InCommUnitMac[4] = GateWay->ConfigPara.GwMac[5];
+	RS485Ch = &GateWay->ConfigPara.Rs485Ch2;
+	memcpy(RS485Ch->CUPara.Para.Mac, InCommUnitMac, 6);
+	if(RS485Ch->CommUnitEnable == true) {
+		RS485_CH2_POW_ON();
+		RS485Ch->CUPara.Para.SensorN = 0;
+		memset(RS485Ch->CUPara.Para.SensorType, 0x00, sizeof(SENSOR_NUM_MAX * 2));
+		RS485Ch->QuerySensorFlag = true;
+		RS485Ch->CUPara.Para.CommStatus = 1;
+	}
+	SCPara->RS485CommUnitReadTimeDelay = 100;
+	SCPara->RS485Rev_Sem = rt_sem_create("rsch2sem",	0, RT_IPC_FLAG_FIFO);
+	if(SCPara->RS485Rev_Sem == RT_NULL) {
+		Debug_Printf("RS485Ch2Rev Sem Create Failed!\r\n");
+	}
+	Debug_Printf("RS485Ch2Rev Thread is running！\r\n");
+	rt_thread_delay(3000);
+	SCPara->InitOverFlag = true;
+	while(1) {
+		RS485LoopHandler(GateWay, RS485Ch, SCPara);
+		//rt_thread_delay(10);
+	}
+}
+
+/*****************************************************************************************
+* 函数名称: RS485Ch2RxIrqCallback
+* 功能描述: RS485通道1中断处理回调函数
+* 参    数: rData 接收到的数据
+* 返 回 值: 无
+*****************************************************************************************/
+void RS485Ch2RxIrqCallback(uint8_t rData)
+{
+	if(SComm2Para.RS485TimeOutCnt == 0) {
+		SComm2Para.RS485RxLen = 0;
+	}
+	
+	if(SComm2Para.RS485RxLen < RS485_RX_BUFF_LEN_MAX)
+		SComm2Para.RS485RxBuff[SComm2Para.RS485RxLen++] = rData;
+	
+	SComm2Para.RS485TimeOutCnt = 3;
+}
+
+
+void RS485RxOverhandler(void)
+{
+	if(SComm1Para.RS485TimeOutCnt > 0)
+		SComm1Para.RS485TimeOutCnt--;
+	
+	if(SComm1Para.RS485RxLen >= 1 && SComm1Para.RS485TimeOutCnt == 0) {
+		if(SComm1Para.InitOverFlag == true) {
+			rt_sem_release(SComm1Para.RS485Rev_Sem);
+			SComm1Para.RS485TimeOutCnt = 20;
+		}
+		else {
+			SComm1Para.RS485RxLen = 0;
+			SComm1Para.RS485TimeOutCnt = 0;
+		}
+	}
+	
+	if(SComm2Para.RS485TimeOutCnt > 0)
+		SComm2Para.RS485TimeOutCnt--;
+	
+	if(SComm2Para.RS485RxLen >= 1 && SComm2Para.RS485TimeOutCnt == 0) {
+		if(SComm2Para.InitOverFlag == true) {
+			SComm2Para.RS485TimeOutCnt = 20;
+			rt_sem_release(SComm2Para.RS485Rev_Sem);
+		}
+		else {
+			SComm2Para.RS485RxLen = 0;
+			SComm2Para.RS485TimeOutCnt = 0;
+		}
+	}
+}
+#if 0
+void RS485Ch2RxIrqCallback(uint8_t rData)
+{
+	static bool FrameHeader = false;
+	static uint8_t rLen = 0;
+	
+	if(FrameHeader == false) {
+		if(rData == 0x7a || rData == 0x7b) {
+			FrameHeader = true;
+			RS485Chr2RxLen = 0;
+		}
+	}
+	if(RS485Chr2RxLen < RS485_RX_BUFF_LEN_MAX) {
+		RS485Chr2RxBuff[RS485Chr2RxLen++] = rData;
+	}
+	else {
+		FrameHeader = false;
+		RS485Chr2RxLen = 0;
+	}
+	
+	if(RS485Chr2RxLen == 6) {
+		rLen = rData + 8;
+	}
+	else if(RS485Chr2RxLen > 6) {
+		if(RS485Chr2RxLen >= rLen) {
+			rt_sem_release(RS485Ch2Rev_Sem);
+			FrameHeader = false;
+		}
+	}
+}
+#endif
@@ -0,0 +1,420 @@
+/*
+数据通信任务
+*/
+#include "bsp.h"
+
+#include "ringbuffer.h"
+#include "protocol.h"
+#include "update_protocol.h"
+
+#include "app_comm.h"
+#include "app_tp_collect.h"
+#include "app_ad_collect.h"
+
+#define  USING_SIMULATOR ( 0 )
+
+#define  COMM_RECV_OUTTIME (20)
+
+static struct {
+    ring_buf_t rb;
+    uint8_t    rb_pool[128];
+} g_comm;
+
+static struct {
+    uint8_t    rxbuf[256];
+    int        rxbytes;
+} g_frame;
+
+static void rs485_rx_cb(uint8_t data)
+{
+    ring_buf_put(&g_comm.rb, &data, 1);
+}
+
+/**
+返回值:成功:len,失败: 0
+***/
+static int recive_frame(void)
+{
+    uint8_t data = 0;
+
+    int len = ring_buf_len(&g_comm.rb);
+
+    if (len == 0)
+        return 0;
+
+    for (int i = 0; i < len; i++) {
+
+        if (g_frame.rxbytes < sizeof(g_frame.rxbuf)) {
+
+            int byte = ring_buf_get(&g_comm.rb, &data, 1);
+
+            if (byte > 0) {
+
+                g_frame.rxbuf[ g_frame.rxbytes] = data;
+
+                g_frame.rxbytes++;
+            }
+        }
+    }
+
+    return len;
+}
+
+static void update_on_start(uint8_t* frame, int len, uint8_t* pload, int size)
+{
+    update_protocol_req_t* pReq = (void*)&frame[sizeof(update_protocol_hd_t)];
+
+    boot_para_t cfg = {0};
+
+    cfg.AppFlag = 0;
+    cfg.UpdateFlag = APP_UPDATE_FLAG;
+    cfg.Crc32Check = pReq->AppCrc32;
+    cfg.PackageNum = pReq->PackageNum;
+    cfg.AppSize    = pReq->AppSize;
+
+    dev_boot_write_param(cfg);
+
+    update_send_cmd(0x01, 1, pReq->PackageNum);
+
+    //重启进入BOOT
+    NVIC_SystemReset();
+}
+
+static int update_cmd_process(uint8_t cmd, void* frame, int len, void* pload, int size)
+{
+    int res = -1;
+
+    switch (cmd) {
+        case 0x81: {
+            update_on_start(frame, len, pload,  size);
+
+            res = 0;
+        }
+        break;
+
+        default:
+            break;
+
+    }
+
+    return res;
+}
+
+static int update_process(void* frame, int len)
+{
+    uint8_t  cmd = 0;
+
+    uint8_t  slave_addr = 0;
+
+    uint8_t  user_data[256] = {0};
+
+    int      user_data_len = 0;
+
+    int res = update_unpack(frame, len, &cmd, &slave_addr, user_data, &user_data_len);
+
+    if (res != 0)
+        return -1;
+
+    if (slave_addr != 0x01)
+        return -2;
+
+    res = update_cmd_process(cmd, frame, len, user_data, user_data_len);
+
+    if (res != 0)
+        return -3;
+
+    return 0;
+}
+
+static void comm_rsp(uint8_t slave_addr,uint8_t frame_cmd,void *pay, int len)
+{
+    uint8_t frame_ack[128] = {0};
+
+    uint16_t frame_ack_len = 0;
+
+    protocol_pack_frame(slave_addr, frame_cmd - 0x80, pay, len, frame_ack, sizeof(frame_ack), &frame_ack_len);
+
+    dev_rs485_send(frame_ack, frame_ack_len);      
+}
+
+static void comm_process(uint8_t* frame, int len)
+{
+    uint16_t slave_addr = 0;
+    uint8_t  frame_cmd = 0;
+    uint8_t  frame_data[64] = {0};
+    uint16_t frame_data_len = 0;
+
+    /***数据解码***/
+    int err = -1;
+    
+    err= protocol_unpack_frame(frame, len, &slave_addr, &frame_cmd, frame_data, &frame_data_len);
+
+    if (err != PROTOCOL_SUCCESS)
+        return ;
+
+    //TODO:获取本机地址
+    uint8_t local_addr = 0;
+    dev_cfg_get_devid(&local_addr);
+
+
+    uint8_t rsp_data[64] = {0};
+    void*  payload = rsp_data;
+    uint16_t payload_len = 0;
+    
+    uint8_t is_match =1;
+    
+    switch (frame_cmd) {
+        
+        case PROTOCOL_CMD_SET_ID: {
+            
+             //
+            if (slave_addr != local_addr)
+             return ;
+            
+            id_data_t data = {0};
+
+            memcpy(&data, &frame_data, sizeof(data));
+
+            dev_cfg_set_devid(data.id);
+            
+            BSP_LOG("set: device id =[%d] =[0x%x] \n", data.id,data.id);
+        }
+        break;
+        
+        case PROTOCOL_CMD_GET_ID:{
+        
+             id_data_t     id_data =  {0};
+
+             id_data.id = local_addr;
+            
+             payload_len = sizeof(id_data);
+                     
+             memcpy(payload ,&id_data,payload_len);
+            
+             BSP_LOG("get: device id =[%d] =[0x%x] \n", id_data.id,id_data.id);
+            
+        }break;
+
+
+        case PROTOCOL_CMD_GET_TP: {
+            //TODO: get tp datas
+           if (slave_addr != local_addr)
+           return ;
+
+           tp_datas_t    tp_data =  {0};
+                      
+           collect_tp_info_t tp_info={0};
+           
+           app_collect_tp_get(&tp_info);
+           
+           memcpy( &tp_data,&tp_info.tp_datas,sizeof(tp_data));
+
+           //兼容旧协议,没有用到的通道，填充无效数据
+           for(int i=0; i <8-TP_SENSOR_NUM; i++){
+           
+               tp_data.channels[i+TP_SENSOR_NUM].status =1;
+               tp_data.channels[i+TP_SENSOR_NUM].value  =0;
+           }
+           
+            for (int i = 0; i < TP_SENSOR_NUM ; i++) {
+
+                char strbuf[128]={0};
+           
+                snprintf(strbuf,sizeof(strbuf)," comm ad ch[%d] %08.4f \r\n", i, tp_data.channels[i].value);
+                
+                BSP_LOG("%s",strbuf);
+            }
+
+            BSP_LOG("\r\n");
+
+            payload_len = sizeof(tp_data);
+            
+            memcpy(payload, &tp_data, payload_len);
+
+        }break; 
+        
+        case PROTOCOL_CMD_GET_AD: {
+
+            //
+            if (slave_addr != local_addr)
+             return ;
+
+            //TODO: get ad datas
+            ad_datas_t ad_data = {0};
+            
+            app_collect_ad_get(&ad_data);
+
+           //兼容旧协议,没有用到的通道，填充无效数据
+            for(int i=0; i <8-YB_SENSOR_NUM; i++){
+           
+               ad_data.channels[i+5].status =1;
+            }
+            
+            BSP_LOG("\r\n");
+
+            for (int i = 0; i < YB_SENSOR_NUM ; i++) {
+
+                char strbuf[128] = {0};
+
+                snprintf(strbuf, sizeof(strbuf), " comm ad ch[%d] %08.4f \r\n", i, ad_data.channels[i].value);
+
+                BSP_LOG("%s", strbuf);
+            }
+
+            BSP_LOG("\r\n");
+
+            payload_len = sizeof(ad_data);
+            
+            memcpy(payload, &ad_data, payload_len);
+
+        }
+        break;
+        
+        case PROTOCOL_CMD_SET_TP_OFFSET:{
+        
+             if (slave_addr != local_addr)
+             return ;
+                   
+             offset_set_data_t  offset_data={0};
+             
+             memcpy( &offset_data,frame_data,sizeof(offset_data));
+
+             dev_cfg_set_temp_offset(offset_data.id, offset_data.prams.value);
+             
+             char strbuf[128]={0};
+
+             snprintf(strbuf,sizeof(strbuf)," set[%d] offset %.2f \r\n", offset_data.id , offset_data.prams.value);
+
+             BSP_LOG("%s",strbuf);
+              
+        }break;
+        
+        
+        case PROTOCOL_CMD_GET_TP_OFFSET:{
+        
+                       //
+            if (slave_addr != local_addr)
+             return ;
+            
+            offset_get_param_t *param = (void *)frame_data;
+                       
+            offset_get_data_t offset_data={0};
+            
+            float val = 200;
+            
+            dev_cfg_get_temp_offset( param->id,&val);
+
+            offset_data.id = param->id;
+            
+            offset_data.prams.value = val;
+            
+            payload_len = sizeof(offset_data);
+            
+            memcpy(payload,&offset_data,payload_len);
+            
+            char strbuf[128]={0};
+
+            snprintf(strbuf,sizeof(strbuf)," get[%d] offset %.2f \r\n", offset_data.id , offset_data.prams.value);
+
+            BSP_LOG("%s",strbuf);
+                    
+
+        }break;
+        
+        case PROTOCOL_CMD_RESET_CHANNEL: {
+            //
+            if (slave_addr != local_addr)
+            return ;
+
+            app_collect_ad_reset_offset();
+
+            BSP_LOG("reset offset start");
+
+        }
+        break;
+        
+        default:
+            is_match =0;
+        break;
+    }
+     
+    if(is_match ==0)
+    return;
+        
+    comm_rsp(slave_addr,frame_cmd, payload, payload_len);
+}
+
+
+void app_comm_entry(void *param)
+{
+    int len = 0;
+
+    dev_rs485_init();
+
+    dev_rs485_rx_register(rs485_rx_cb);
+
+    ring_buf_init(&g_comm.rb, g_comm.rb_pool, sizeof(g_comm.rb_pool));
+
+    /***/
+    update_init(dev_rs485_send);
+    
+    while (1) {
+       
+        rt_thread_mdelay(1);
+        
+        len = recive_frame();
+
+        if (len == 0) {
+           
+            rt_thread_mdelay(5);
+            
+            len = recive_frame();
+
+            if (len == 0) {
+                
+                if (g_frame.rxbytes > 0) {
+                    
+                    update_process(g_frame.rxbuf, g_frame.rxbytes);
+
+                    comm_process(g_frame.rxbuf, g_frame.rxbytes);
+
+                    g_frame.rxbytes = 0;
+                }
+            }
+        }
+    }
+}
+
+
+ALIGN(RT_ALIGN_SIZE)
+static uint8_t comm_thd_stack[4096];
+static struct rt_thread comm_thd;
+
+int app_comm_init(void)
+{
+
+#if USING_SIMULATOR
+    BSP_LOG("comm data using simulator \n");
+#endif
+
+    int ret = rt_thread_init(&comm_thd,
+                   "app_comm",
+                   app_comm_entry,
+                   RT_NULL,
+                   comm_thd_stack,
+                   sizeof(comm_thd_stack),
+                   10,
+                   20
+                  );
+
+
+    if(ret == RT_EOK){
+    
+        rt_thread_startup(&comm_thd);
+    }
+    
+   return 0; 
+}
+INIT_APP_EXPORT(app_comm_init);
+
+
@@ -0,0 +1,643 @@
+#include <stdlib.h>
+#include <math.h>
+#include "main.h"
+#include "CatOneTask.h"
+#include "LoraTask.h"
+#include "CatOneTask.h"
+#include "RS485Task.h"
+#include "DebugCmd.h"
+#include "spiflash.h"
+
+
+//雅下： 81-00-00-06-00-01
+//			81-00-00-06-00-02
+//			81-00-00-06-00-03
+//			81-00-00-06-00-04
+//			81-00-00-06-00-05
+//			81-00-00-06-00-06
+//			81-00-00-06-00-07
+//			81-00-00-06-00-08
+//			81-00-00-06-00-09
+//			81-00-00-06-00-0A
+
+static const uint8_t GateWayMac_Test[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x00};
+static const uint8_t GateWayMac_BL1[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x01};
+static const uint8_t GateWayMac_BL2[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x02};
+static const uint8_t GateWayMac_BL3[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x03};
+static const uint8_t GateWayMac_BL4[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x04};
+static const uint8_t GateWayMac_BL5[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x05};
+static const uint8_t GateWayMac_BL6[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x06};
+static const uint8_t GateWayMac_BL7[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x07};
+static const uint8_t GateWayMac_BL8[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x08};
+static const uint8_t GateWayMac_BL9[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x09};
+static const uint8_t GateWayMac_BL10[6] = {0x81, 0x00, 0x00, 0x06, 0x00, 0x0A};
+bool MainDispEn = true;
+
+static rt_thread_t Lora_Thread = RT_NULL;
+static rt_thread_t Cat1Eth_Thread = RT_NULL;
+static rt_thread_t RS485Ch1_Thread = RT_NULL;
+static rt_thread_t RS485Ch2_Thread = RT_NULL;
+static rt_thread_t Debug_Thread = RT_NULL;
+
+GateWayPara_t GateWay;
+
+#define ARRAY_DIM(a) (sizeof(a) / sizeof((a)[0]))
+//static int Battery_Level_Percent_Table[11] = {3000, 3650, 3700, 3740, 3760, 3795, 3840, 3910, 3980, 4070, 4150};
+static int Battery_Level_Percent_Table[11] = {6000, 7300, 7400, 7480, 7520, 7590, 7680, 7820, 7960, 8140, 8300};
+int toPercentage(int voltage)
+{
+	int i;
+	if(voltage < Battery_Level_Percent_Table[0])
+		return 0;
+ 
+	for(i = 0; i<ARRAY_DIM(Battery_Level_Percent_Table); i++){
+		if(voltage < Battery_Level_Percent_Table[i])
+			return i*10 - (10UL * (int)(Battery_Level_Percent_Table[i] - voltage)) / 
+			(int)(Battery_Level_Percent_Table[i] - Battery_Level_Percent_Table[i-1]);;
+	}
+ 
+	return 100;
+}
+
+/*****************************************************************************************
+* 函数名称: MainDBGOnOff
+* 功能描述: 主调试信息开关函数
+* 参    数: OnOff,开关
+* 返 回 值: 无
+*****************************************************************************************/
+void MainDBGOnOff(bool OnOff)
+{
+	MainDispEn = OnOff;
+	if(OnOff)
+		Debug_Printf("\r\nMain Display Enable!\r\n\r\n");
+	else
+		Debug_Printf("\r\nMain Display Disable!\r\n\r\n");
+}
+
+#if 0
+uint32_t SDStartBlock;
+uint8_t TestData[10 * 512];
+uint8_t ADBuff[10 * 512];
+
+void SDCardTest(void) 
+{
+	SDStartBlock = 0;
+	SDCardReadBlocks(SDStartBlock, 10, TestData);
+	if(TestData[0] != 0xAA) {
+		SDCardErase(SDStartBlock, 10);
+		memset(ADBuff, 0xAA, 10 * 512);
+		SDCardWriteBlocks(SDStartBlock, 10, (uint8_t *)&ADBuff);
+	}
+	SDCardReadBlocks(SDStartBlock, 10, TestData);
+}
+#endif
+
+void InfTest(void)
+{
+	uint8_t sData[10] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A};
+	RS485_CH1_RX();
+	RS485_CH1_POW_ON();
+ 	rt_thread_delay(100);
+	RS485_CH1_POW_OFF();
+
+	RS485_CH2_POW_ON();
+	rt_thread_delay(100);
+	RS485_CH2_POW_OFF();
+	
+	POWER_LED_OFF();
+	POWER_LED_ON();
+	LORA_RX_LED_SET();
+	LORA_RX_LED_CLR();
+	RS485_CH1_TX();
+	RS485_CH2_RX();
+	RS485Ch1_Config(500000);
+	RS485Ch2_Config(500000);
+	RS485Ch1UartSend(sData, 10);
+	rt_thread_delay(100);
+	
+	RS485_CH2_TX();
+	RS485_CH1_RX();
+	RS485Ch2UartSend(sData, 10);
+	rt_thread_delay(100);
+//	SDCardTest();
+}
+
+void GateWayInit(void)
+{
+	LogHeader_t Header;
+	uint32_t FlashID = SpiFlashReadId();
+	Debug_Printf("FlashID: %08x\r\n", FlashID);
+	
+	memset((uint8_t *)&GateWay.ConfigPara, 0x00, sizeof(GWConfigPara_t));
+	int ret = ReadPara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t));
+	if(GateWay.ConfigPara.SavFlag != LOG_SAV_FLAG) {
+		memset((uint8_t *)&GateWay.ConfigPara, 0x00, sizeof(GWConfigPara_t));
+		GateWay.ConfigPara.SavFlag = LOG_SAV_FLAG;
+		GateWay.ConfigPara.Comm = CATONE_COMM;
+#if MAC_ADDR_TYPE == 0//测试服务器
+	GateWay.ConfigPara.LTENet.DestAddr[0] = 39;
+	GateWay.ConfigPara.LTENet.DestAddr[1] = 106;
+	GateWay.ConfigPara.LTENet.DestAddr[2] = 103;
+	GateWay.ConfigPara.LTENet.DestAddr[3] = 147;
+	GateWay.ConfigPara.LTENet.DestPort = 8080;
+#elif MAC_ADDR_TYPE > 0
+	GateWay.ConfigPara.LTENet.DestAddr[0] = 103;
+	GateWay.ConfigPara.LTENet.DestAddr[1] = 217;
+	GateWay.ConfigPara.LTENet.DestAddr[2] = 192;
+	GateWay.ConfigPara.LTENet.DestAddr[3] = 248;
+	GateWay.ConfigPara.LTENet.DestPort = 12111;
+#endif
+
+		GateWay.ConfigPara.EthNet.IpMode = ETH_IP_STATIC;
+		GateWay.ConfigPara.EthNet.IpAddr[0] = 192;
+		GateWay.ConfigPara.EthNet.IpAddr[1] = 168;
+		GateWay.ConfigPara.EthNet.IpAddr[2] = 1;
+		GateWay.ConfigPara.EthNet.IpAddr[3] = 101;
+		GateWay.ConfigPara.EthNet.IpPort = 10000;
+		GateWay.ConfigPara.EthNet.WorkMode = ETH_MODE_TCP_CLIENT;
+		GateWay.ConfigPara.EthNet.SubnetMask[0] = 255;
+		GateWay.ConfigPara.EthNet.SubnetMask[1] = 255;
+		GateWay.ConfigPara.EthNet.SubnetMask[2] = 255;
+		GateWay.ConfigPara.EthNet.SubnetMask[3] = 0;
+		GateWay.ConfigPara.EthNet.Gateway[0] = 192;
+		GateWay.ConfigPara.EthNet.Gateway[1] = 168;
+		GateWay.ConfigPara.EthNet.Gateway[2] = 1;
+		GateWay.ConfigPara.EthNet.Gateway[3] = 1;
+		GateWay.ConfigPara.EthNet.DestIp[0] = 192;
+		GateWay.ConfigPara.EthNet.DestIp[1] = 168;
+		GateWay.ConfigPara.EthNet.DestIp[2] = 1;
+		GateWay.ConfigPara.EthNet.DestIp[3] = 100;
+		GateWay.ConfigPara.EthNet.DestPort = 8080;
+
+		GateWay.ConfigPara.CommUnitReadInterval = COMMUNIT_READ_SENSOR_INTERVAL_MAX;//非低功耗设备
+		memset(GateWay.ConfigPara.CommUnitArray, 0x00, sizeof(CommUnitData_t) * COMMUNIT_NUM_MAX);
+		GateWay.ConfigPara.Rs485Ch1.Enable = true;
+		GateWay.ConfigPara.Rs485Ch1.CommUnitEnable = false;
+		GateWay.ConfigPara.Rs485Ch1.BaudRate = 500000;
+		GateWay.ConfigPara.Rs485Ch1.UpgradeEnable = true;
+		GateWay.ConfigPara.Rs485Ch1.Power = false;
+		GateWay.ConfigPara.Rs485Ch2.Enable = true;
+		GateWay.ConfigPara.Rs485Ch2.BaudRate = 500000;
+		GateWay.ConfigPara.Rs485Ch2.UpgradeEnable = false;
+		GateWay.ConfigPara.Rs485Ch2.CommUnitEnable = false;
+		GateWay.ConfigPara.Rs485Ch2.Power = false;
+		GateWay.ConfigPara.Rs485Ch1.RS485Send = RS485Ch1UartSend;
+		GateWay.ConfigPara.Rs485Ch2.RS485Send = RS485Ch2UartSend;
+		
+		GateWay.ConfigPara.Lora.OnOff = true;
+		GateWay.ConfigPara.Lora.ucChannel = 8;
+		GateWay.ConfigPara.Lora.ucPower = 20;
+		GateWay.ConfigPara.Lora.SignalBw = 8;
+		GateWay.ConfigPara.Lora.SpreadFactor = 9;
+		GateWay.ConfigPara.Lora.ErrorCoding = 2;
+		GateWay.ConfigPara.Lora.RegPreamble = 10;
+		GateWay.ConfigPara.Lora.FreqCent = FREQ_CENT;
+		
+		GateWay.ConfigPara.OutageFlag = false;
+		GateWay.ConfigPara.DebugChannel = DEBUG_CH_RS485_1;
+		
+#if MAC_ADDR_TYPE == 0
+	memcpy(GateWay.ConfigPara.GwMac, GateWayMac_Test, 6);
+	GateWay.ConfigPara.DebugChannel = DEBUG_CH_RS485_1;
+#elif MAC_ADDR_TYPE == 1
+	memcpy(GateWay.ConfigPara.GwMac, GateWayMac_BL1, 6);
+	GateWay.ConfigPara.DebugChannel = DEBUG_CH_RS485_1;
+//	GateWay.ConfigPara.DebugChannel = DEBUG_CH_DBG;
+#elif MAC_ADDR_TYPE == 2
+	memcpy(GateWay.ConfigPara.GwMac, GateWayMac_BL2, 6);
+	GateWay.ConfigPara.DebugChannel = DEBUG_CH_RS485_1;
+//	GateWay.ConfigPara.DebugChannel = DEBUG_CH_DBG;
+#elif MAC_ADDR_TYPE == 3
+	memcpy(GateWay.ConfigPara.GwMac, GateWayMac_BL3, 6);
+	GateWay.ConfigPara.DebugChannel = DEBUG_CH_RS485_1;
+#elif MAC_ADDR_TYPE == 4
+	memcpy(GateWay.ConfigPara.GwMac, GateWayMac_BL4, 6);
+	GateWay.ConfigPara.DebugChannel = DEBUG_CH_RS485_1;
+#elif MAC_ADDR_TYPE == 5
+	memcpy(GateWay.ConfigPara.GwMac, GateWayMac_BL5, 6);
+	GateWay.ConfigPara.DebugChannel = DEBUG_CH_RS485_1;
+#elif MAC_ADDR_TYPE == 6
+	memcpy(GateWay.ConfigPara.GwMac, GateWayMac_BL6, 6);
+	GateWay.ConfigPara.DebugChannel = DEBUG_CH_RS485_1;
+#elif MAC_ADDR_TYPE == 7
+	memcpy(GateWay.ConfigPara.GwMac, GateWayMac_BL7, 6);
+	GateWay.ConfigPara.DebugChannel = DEBUG_CH_RS485_1;
+#elif MAC_ADDR_TYPE == 8
+	memcpy(GateWay.ConfigPara.GwMac, GateWayMac_BL8, 6);
+	GateWay.ConfigPara.DebugChannel = DEBUG_CH_RS485_1;
+#elif MAC_ADDR_TYPE == 9
+	memcpy(GateWay.ConfigPara.GwMac, GateWayMac_BL9, 6);
+	GateWay.ConfigPara.DebugChannel = DEBUG_CH_RS485_1;
+#elif MAC_ADDR_TYPE == 10
+	memcpy(GateWay.ConfigPara.GwMac, GateWayMac_BL10, 6);
+	GateWay.ConfigPara.DebugChannel = DEBUG_CH_RS485_1;
+#endif
+	}
+	
+	if(GateWay.ConfigPara.OutageFlag != true && GateWay.ConfigPara.OutageFlag != false)
+		GateWay.ConfigPara.OutageFlag = false;
+	
+	GateWay.SvrRegFlag = false;
+	memset(GateWay.SvrMac, 0x00, 6);
+	
+	if(GateWay.ConfigPara.DebugChannel == DEBUG_CH_RS485_1) {
+		GateWay.ConfigPara.Rs485Ch1.Enable = true;
+		GateWay.ConfigPara.Rs485Ch1.BaudRate = 500000;
+	}
+	if(GateWay.ConfigPara.Rs485Ch1.BaudRate < 2400 || GateWay.ConfigPara.Rs485Ch1.BaudRate > 921600)
+		GateWay.ConfigPara.Rs485Ch1.BaudRate = 500000;
+	RS485Ch1_Config(GateWay.ConfigPara.Rs485Ch1.BaudRate);
+	
+	if(GateWay.ConfigPara.DebugChannel == DEBUG_CH_RS485_2) {
+		GateWay.ConfigPara.Rs485Ch2.Enable = true;
+		GateWay.ConfigPara.Rs485Ch2.BaudRate = 500000;
+	}
+	if(GateWay.ConfigPara.Rs485Ch2.BaudRate < 2400 || GateWay.ConfigPara.Rs485Ch2.BaudRate > 921600)
+		GateWay.ConfigPara.Rs485Ch2.BaudRate = 500000;
+	RS485Ch2_Config(GateWay.ConfigPara.Rs485Ch2.BaudRate);
+	
+	if(GateWay.ConfigPara.Rs485Ch1.Power)
+		RS485_CH1_POW_ON();
+	else
+		RS485_CH1_POW_OFF();
+	
+	if(GateWay.ConfigPara.Rs485Ch2.Power) {
+		RS485_CH2_POW_OFF();
+		rt_thread_delay(1000);
+		RS485_CH2_POW_ON();
+	}
+	else
+		RS485_CH2_POW_OFF();
+	
+	if(GateWay.ConfigPara.Lora.OnOff == true) {
+		LORA_POW_ON();
+	}
+	else {
+		LORA_POW_OFF();
+	}
+	if(LoraSetChannel(GateWay.ConfigPara.Lora.ucChannel) == false) {
+		GateWay.ConfigPara.Lora.ucChannel = 8;
+		LoraSetChannel(GateWay.ConfigPara.Lora.ucChannel);
+		//WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t));
+	}
+	if(LoraSetFreqCent(GateWay.ConfigPara.Lora.FreqCent) == false)
+	{
+		GateWay.ConfigPara.Lora.FreqCent = 433100000;
+		LoraSetFreqCent(GateWay.ConfigPara.Lora.ucChannel);
+	}
+	if(LoraSetPower(GateWay.ConfigPara.Lora.ucPower) == false) {
+		GateWay.ConfigPara.Lora.ucPower = 20;
+		LoraSetPower(GateWay.ConfigPara.Lora.ucPower);
+		//WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t));
+	}
+	if(LoraSetSignalBw(GateWay.ConfigPara.Lora.SignalBw) == false) {
+		GateWay.ConfigPara.Lora.SignalBw = 8;
+		LoraSetSignalBw(GateWay.ConfigPara.Lora.SignalBw);
+		//WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t));
+	}
+	if(LoraSetSpreadFactor(GateWay.ConfigPara.Lora.SpreadFactor) == false) {
+		GateWay.ConfigPara.Lora.SpreadFactor = 9;
+		LoraSetSpreadFactor(GateWay.ConfigPara.Lora.SpreadFactor);
+		//WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t));
+	}
+	if(LoraSetErrorCoding(GateWay.ConfigPara.Lora.ErrorCoding) == false) {
+		GateWay.ConfigPara.Lora.ErrorCoding = 2;
+		LoraSetErrorCoding(GateWay.ConfigPara.Lora.ErrorCoding);
+		//WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t));
+	}
+	if(GateWay.ConfigPara.Lora.RegPreamble > 0xFE) {
+		GateWay.ConfigPara.Lora.RegPreamble = 10;
+		LoraSetRegPreamble(GateWay.ConfigPara.Lora.RegPreamble);
+		//WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t));
+	}
+	
+	WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t));
+
+	LogInit();
+	
+	Header.LogEndAddr = 0;
+	if(ReadLogNum() > 0) {
+		int ret = ReadLog(&Header, NULL, 0);
+		if(ret > 0) {
+			GateWay.HistoryNum = ReadLogNum() - Header.LogIdx + 1;
+			rt_kprintf("History Num: %d\r\n", GateWay.HistoryNum);
+		}
+		else {
+			rt_kprintf("History Num: 0\r\n");
+		}
+	}
+	else
+		rt_kprintf("History Num: 0\r\n");
+	if(GateWay.ConfigPara.Comm == CATONE_COMM) {
+		CAT1_ON();
+	}
+	else {
+		ETH_ON();
+    rt_thread_delay(1000);
+    ETHReset();
+	}
+}
+
+void OutageUpdate(uint8_t AlarmType, bool AlarmState, uint8_t Batt)
+{
+	GateWayAlarmType_t *Alarm;
+	uint8_t MegData[6],len;
+	len = sizeof(GateWayAlarmType_t);
+	MegData[0] = len & 0x00ff;;
+	MegData[1] = (len >> 8) & 0x00ff;
+	MegData[2] = NET_COMM_CMD_ALARM;
+	
+	Alarm = (GateWayAlarmType_t *)&MegData[3];
+	Alarm->AlarmType = AlarmType;
+	Alarm->AlarmState = AlarmState;
+	Alarm->AlarmPara = Batt;
+	CatOneEthSendQueue(MegData, 6);		//发送报警信息     
+}
+
+/*****************************************************************************************
+* 函数名称: main
+* 功能描述: 主函数
+* 参    数: 无
+* 返 回 值: 运行错误返回-1
+*****************************************************************************************/
+static	uint8_t LastBattery = 0xff;	//上一次电池电压
+int main(void) 
+{	
+	uint16_t OneSecondDlyCnt = 0;
+//	struct tm cTime;
+	uint16_t PowerONLedDly = 2000;
+	uint32_t SystemRseetDlyCnt = 0;
+	uint32_t BatteryUpdateDlyCnt = 0;
+	uint8_t AlarmType = 0;
+	
+	GateWayInit();
+
+	rt_kprintf("\r\n\r\n");
+	rt_kprintf("****************************************************\r\n");
+	rt_kprintf("**                                                **\r\n");
+	rt_kprintf("**                   GateWay                      **\r\n");
+	rt_kprintf("**                SoftWare V%d.%d                   **\r\n", SOFTWARE_VERSION / 10, SOFTWARE_VERSION % 10);
+	rt_kprintf("**                HardWare V%d.%d                   **\r\n", HARDWARE_VERSION / 10, HARDWARE_VERSION % 10);
+	rt_kprintf("**         Compile: %s %s          **\r\n", __DATE__, __TIME__);
+	rt_kprintf("**                                                **\r\n");
+	rt_kprintf("****************************************************\r\n\r\n");
+//	TimeGet(&cTime);
+//	TimeShow(TimeTs());
+	FeedDog();
+	//rt_thread_delay(500);
+	//InfTest();
+	//FeedDog();
+	
+	//Cat1DBGOnOff(true);
+	
+	
+	GateWay.CommUnitRevCallBack = CommUnitAnalyze;
+	GateWay.SvrRevCallBack = Cat1EthRevCallBack;
+	
+	GateWay.NetSendData_MQ = rt_mq_create("NetSendMQ", 512, 10, RT_IPC_FLAG_FIFO);
+	if(GateWay.NetSendData_MQ == RT_NULL) {
+		rt_kprintf("CatOne MQ Create Failed!\r\n");
+	}
+	
+	GateWay.LoraRev_MQ = rt_mq_create("LoraRevMQ", 256, 10, RT_IPC_FLAG_FIFO);
+	if(GateWay.LoraRev_MQ == RT_NULL) {
+		rt_kprintf("LoraRev MQ Create Failed!\r\n");
+	}
+	
+	GateWay.UartRevMutex = rt_mutex_create("urmutex", RT_IPC_FLAG_FIFO);
+	if(GateWay.UartRevMutex == RT_NULL) {
+		rt_kprintf("UR Mutex Create Failed!\r\n");
+	}
+	
+	GateWay.SvrRevCallBack = Cat1EthRevCallBack;
+	
+	RS485Ch1_Thread = rt_thread_create("RS485Ch1", RS485Ch1_Thread_Entry, &GateWay, 2048, 3, 20);
+	if (RS485Ch1_Thread != RT_NULL)
+		rt_thread_startup(RS485Ch1_Thread);
+	else
+		return -1;
+	
+	RS485Ch2_Thread = rt_thread_create("RS485Ch2", RS485Ch2_Thread_Entry, &GateWay, 2048, 3, 20);
+	if (RS485Ch2_Thread != RT_NULL)
+		rt_thread_startup(RS485Ch2_Thread);
+	else
+		return -1;
+	
+	Debug_Thread = rt_thread_create("DebugUart", Debug_Thread_Entry, &GateWay, 2048, 3, 20);
+	if (RS485Ch2_Thread != RT_NULL)
+		rt_thread_startup(Debug_Thread);
+	else
+		return -1;
+		
+	Cat1Eth_Thread = rt_thread_create("Cat1Eth", CatOne_Eth_Thread_Entry, &GateWay, 4096, 3, 20);
+	if (Cat1Eth_Thread != RT_NULL)
+		rt_thread_startup(Cat1Eth_Thread);
+	else
+		return -1;
+	
+	Lora_Thread = rt_thread_create("Lora", Lora_Thread_Entry, &GateWay, 1024, 3, 20);
+	if (Lora_Thread != RT_NULL)
+		rt_thread_startup(Lora_Thread);
+	else
+		return -1;
+	
+	while(1) {
+		if(PowerONLedDly > 0) {
+			PowerONLedDly--;
+			if(PowerONLedDly == 1) {
+				POWER_LED_OFF();
+			}
+		}
+		EthRxOverhandler();
+		RS485RxOverhandler();
+		DebugRxOverhandler();
+		if(OneSecondDlyCnt % 200 == 0) {
+			FeedDog();
+			LORA_RX_TOGGLE();
+			POWER_TOGGLE();
+		}
+		OneSecondDlyCnt++;
+		if(OneSecondDlyCnt == 1000) { 
+			OneSecondDlyCnt = 0;
+			
+			if(GateWay.BatteryReadDlyCnt > 0) {
+				GateWay.BatteryReadDlyCnt--;
+				continue;
+			}
+			
+			uint16_t ADValue = GetADCBuffPoint();
+			//V = (AD * 3.3 / 4096) * (R1+R2) / R1; R1 = 200, R2 = 120
+			//计算出常数为0.0021484375，扩大1000倍
+			float Voltage = ADValue * 2.1484375;
+			GateWay.Battery = toPercentage(Voltage);
+			
+			//上电判断电量
+			if(LastBattery == 0xff) {
+				LastBattery = GateWay.Battery;
+			
+				if(GateWay.ConfigPara.OutageFlag == true)	{	//有报警
+					AlarmType = 1;
+				}
+				else {
+					AlarmType = 0;
+				}
+				//BatteryUpdateDlyCnt = 2 * 60;
+				BatteryUpdateDlyCnt = 10;
+			}
+			else {
+				if(GateWay.ConfigPara.OutageFlag == false) {		//没有告警，判断电池电压是否降低
+					if(GateWay.Battery <= LastBattery) {
+						if(LastBattery <= 5) {
+							GateWay.ConfigPara.OutageFlag = true;
+							WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t));
+							Debug_Printf("The power is cutted.(1) Bat = %d, LBat = %d\r\n", GateWay.Battery, LastBattery);
+							LastBattery = GateWay.Battery;
+							AlarmType = 1;
+							OutageUpdate(AlarmType, GateWay.ConfigPara.OutageFlag, LastBattery);
+							BatteryUpdateDlyCnt = 20 * 60;
+						}
+						else if((LastBattery - GateWay.Battery) > 2) {
+							GateWay.ConfigPara.OutageFlag = true;
+							WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t));
+							LastBattery = GateWay.Battery;
+							AlarmType = 1;
+							Debug_Printf("The power is cutted.(2) Bat = %d, LBat = %d\r\n", GateWay.Battery, LastBattery);
+							OutageUpdate(AlarmType, GateWay.ConfigPara.OutageFlag, LastBattery);
+							BatteryUpdateDlyCnt = 20 * 60;
+						}
+					}
+					else {		//充电，更新上一次电池电压
+						LastBattery = GateWay.Battery;
+					}
+				}
+				else {
+					if(GateWay.Battery >= LastBattery) {
+						if(LastBattery > 95) {
+							GateWay.ConfigPara.OutageFlag = false;
+							WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t));
+							Debug_Printf("The power is restored.(1) Bat = %d, LBat = %d\r\n", GateWay.Battery, LastBattery);
+							LastBattery = GateWay.Battery;
+							AlarmType = 1;
+							OutageUpdate(AlarmType, GateWay.ConfigPara.OutageFlag, LastBattery);
+							BatteryUpdateDlyCnt = 90 * 60;
+							AlarmType = 0;
+						}
+						else if(GateWay.Battery - LastBattery > 5) {
+							GateWay.ConfigPara.OutageFlag = false;
+							WritePara((uint8_t *)&GateWay.ConfigPara, sizeof(GWConfigPara_t));
+							Debug_Printf("The power is restored.(2) Bat = %d, LBat = %d\r\n", GateWay.Battery, LastBattery);
+							LastBattery = GateWay.Battery;
+							AlarmType = 1;
+							OutageUpdate(AlarmType, GateWay.ConfigPara.OutageFlag, LastBattery);
+							BatteryUpdateDlyCnt = 90 * 60;
+							AlarmType = 0;
+						}
+					}
+					else {	//电池继续放电，更新上一次电池电压
+						LastBattery = GateWay.Battery;
+					}
+				}
+			}
+			BatteryUpdateDlyCnt--;
+			if(BatteryUpdateDlyCnt == 0) {
+				if(GateWay.ConfigPara.OutageFlag)	{	//有报警
+					BatteryUpdateDlyCnt = 20 * 60;
+				}
+				else {
+					BatteryUpdateDlyCnt = 90 * 60;
+				}
+  			OutageUpdate(AlarmType, GateWay.ConfigPara.OutageFlag, LastBattery);
+			}
+			//ADC_Start();
+		}
+		SystemRseetDlyCnt++;
+		if(SystemRseetDlyCnt > (24 * 60 * 60 * 1000)) {
+			SystemRseetDlyCnt = 0;
+			Debug_Printf("The system resets periodically.\r\n");
+			rt_thread_delay(10);
+			NVIC_SystemReset();
+		}
+		rt_thread_delay(1);
+	}
+}
+
+
+
+#if 0
+static FATFS SDFatFs;
+static FIL TestFile;
+static uint8_t u8WorkBuffer[FF_MAX_SS];
+
+void FSInit(void)
+{
+	FRESULT fRet;
+	uint32_t u32WBNbr, u32RBNbr;
+	char SDPath[] = "1:";
+	MKFS_PARM opt;
+	uint8_t u8ReadText[100];
+	en_result_t enTestRet = Error;
+	uint8_t u8WriteText[] = "This is a string used to test the FatFs";
+	
+	if (FR_OK != f_mount(&SDFatFs, (TCHAR const*)SDPath, 0U)) { 
+		rt_kprintf("FatFs Initialization Error!\r\n"); 
+	}
+	else { 
+		memset(&opt, 0, sizeof(MKFS_PARM));
+		opt.fmt = (BYTE)FM_FAT32;
+		/* Create a FAT file system (format) on the logical drive */
+		if (FR_OK != f_mkfs((TCHAR const*)SDPath, &opt, u8WorkBuffer, sizeof(u8WorkBuffer))) { 
+			rt_kprintf("FatFs Format Error!\r\n"); 
+		} 
+		else { 
+			/* Create and Open a new text file object with write access */
+			if (FR_OK != f_open(&TestFile, "1:Test.txt", ((BYTE)FA_CREATE_ALWAYS | (BYTE)FA_WRITE))) { 
+				rt_kprintf("\"Test.txt\" file Open for write Error!\r\n"); 
+			} 
+			else { 
+				/* Write data to the text file */
+				fRet = f_write(&TestFile, u8WriteText, sizeof(u8WriteText), (void *)&u32WBNbr);
+				if ((0UL == u32WBNbr) || (FR_OK != fRet)) { 
+					rt_kprintf("\"Test.txt\" file Write or EOF Error!\r\n"); 
+  				else { 
+					/* Close the open text file */
+					f_close(&TestFile);
+					/* Open the text file object with read access */
+					if (FR_OK != f_open(&TestFile, "1:Test.txt", (BYTE)FA_READ)) { 
+						rt_kprintf("\"Test.txt\" file Open for read Error!\r\n"); 
+					} 
+					else { 
+						memset(u8ReadText, 0, sizeof(u8ReadText));
+						/* Read data from the text file */
+						fRet = f_read(&TestFile, u8ReadText, sizeof(u8ReadText), (UINT*)(uint32_t)&u32RBNbr);
+						if ((0UL == u32RBNbr) || (FR_OK != fRet)) { 
+							rt_kprintf("\"Test.txt\" file Read or EOF Error!\r\n"); 
+						} 
+						else { 
+							/* Close the open text file */
+							f_close(&TestFile);
+							/* Compare read data with the expected data */
+							if (u32RBNbr == u32WBNbr) { 
+								/* Check data value */
+								if (0 == memcmp(u8WriteText, u8ReadText, u32RBNbr)) { 
+									enTestRet = Ok;
+								} 
+							} 
+						} 
+					} 
+				} 
+			} 
+		} 
+	} 
+	/* Unlink the micro SD disk I/O driver */
+	f_mount(NULL, (TCHAR const*)SDPath, 0U);
+	
+	if(enTestRet != Ok) {
+		rt_kprintf("Error!\r\n"); 
+	}
+	else {
+		rt_kprintf("Ok!\r\n"); 
+	}
+}
+
+#endif
+
@@ -0,0 +1,120 @@
+#include "protocol.h"
+#include "string.h"
+#include "utils.h"
+
+int protocol_pack_frame(
+    uint16_t slave_addr,
+    uint8_t command,const 
+    uint8_t *payload,
+    uint16_t payload_len,
+    uint8_t *buffer,uint16_t buffer_size,
+    uint16_t *packed_len)
+{
+
+    // 构建基础帧头
+
+    buffer[0] = PROTOCOL_HEAD & 0xFF;  
+    buffer[1] = (PROTOCOL_HEAD >> 8) & 0xFF;
+    buffer[2] = slave_addr & 0xFF;  
+    buffer[3] = (slave_addr >> 8) & 0xFF;
+    
+    buffer[4] = command;
+    
+    buffer[5] = payload_len & 0xFF;  
+    buffer[6] = (payload_len >> 8) & 0xFF;
+
+    // 复制有效载荷（保持小端格式）
+    if (payload_len > 0 && payload != NULL) {
+        memcpy(buffer + PROTOCOL_FRAME_HEAD_SIZE , payload, payload_len);
+    }
+
+     // 设置实际长度
+    int fram_len = PROTOCOL_FRAME_MIN_SIZE + payload_len;
+    
+    
+    // 计算CRC（覆盖地址、命令、长度和有效载荷）
+    uint16_t crc = 0xFFFF;
+    
+    crc = modbus_crc16(buffer,fram_len -2);
+    
+    // 写入CRC（保持小端格式）
+
+    buffer[fram_len-2] = (uint8_t)(crc & 0xFF);
+    buffer[fram_len-1] = (uint8_t)(crc >> 8);
+
+    *packed_len =fram_len;
+    
+    return PROTOCOL_SUCCESS;
+    
+}
+
+int protocol_unpack_frame(
+    const uint8_t *frame,
+    uint16_t frame_len,
+    uint16_t *slave_addr,
+    uint8_t *command,
+    uint8_t *payload,
+    uint16_t *payload_len
+) {
+    // 参数校验
+    if (frame == NULL || slave_addr == NULL || command == NULL || payload_len == NULL) {
+        return PROTOCOL_ERR_INVALID_PARAM;
+    }
+    if (frame_len < PROTOCOL_FRAME_MIN_SIZE) {
+        return PROTOCOL_ERR_INVALID_PARAM;
+    }
+
+    // 帧头校验
+    uint16_t header = (frame[0] | frame[1] <<8);
+    
+    if (header != PROTOCOL_HEAD) {
+        
+        return PROTOCOL_ERR_INVALID_PARAM;
+    }
+
+    // 基础字段解析
+    *slave_addr  =   (frame[2] | frame[3] << 8);
+    
+    
+    *command     =    frame[4];
+    
+    
+    *payload_len =   (frame[5] | frame[6] << 8);
+    
+    // 数据完整性校验
+    if (*payload_len > (frame_len - PROTOCOL_FRAME_MIN_SIZE)) {
+        
+        return PROTOCOL_ERR_BUFFER_OVERFLOW;
+    }
+
+    int frame_size = *payload_len + 9;
+    
+    uint16_t calc_crc =0xffff;
+    
+    calc_crc =  modbus_crc16((uint8_t *)frame, frame_size -2 );
+
+    // 校验CRC（保持小端格式）
+    union{
+    
+        uint16_t value;
+        struct{
+          uint8_t  crcl;
+          uint8_t  crch;
+        }bytes;
+        
+    }crc_data;
+    
+    crc_data.bytes.crcl  =(frame[frame_size - 2] ) ;
+    crc_data.bytes.crch  =(frame[frame_size - 1] ) ;
+    
+    if (calc_crc != crc_data.value) {
+        return PROTOCOL_ERR_CRC;
+    }
+
+    // 复制有效载荷（保持小端格式）
+    if (*payload_len > 0 && payload != NULL) {
+        memcpy(payload, frame + PROTOCOL_FRAME_HEAD_SIZE, *payload_len);
+    }
+
+    return PROTOCOL_SUCCESS;
+}
@@ -0,0 +1,89 @@
+/******************************************************************************
+ * @brief    环形缓冲区管理(参考linux/kfifo)
+ *
+ * Copyright (c) 2016~2020, <morro_luo@163.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs: 
+ * Date           Author       Notes 
+ * 2016-05-30     Morro        初版完成
+ ******************************************************************************/
+#include "ringbuffer.h"
+#include <string.h>
+#include <stddef.h>
+
+#define min(a,b) ( (a) < (b) )? (a):(b)     
+     
+/*
+ *@brief      构造一个空环形缓冲区
+ *@param[in]  r    - 环形缓冲区管理器
+ *@param[in]  buf  - 数据缓冲区
+ *@param[in]  len  - buf长度(必须是2的N次幂)
+ *@retval     bool
+ */
+bool ring_buf_init(ring_buf_t *r,unsigned char *buf, unsigned int len)
+{
+    r->buf    = buf;
+    r->size   = len;
+    r->front  = r->rear = 0;
+    return (buf != NULL) && ((len & len -1) == 0);
+}
+
+/*
+ *@brief      清空环形缓冲区 
+ *@param[in]  r - 待清空的环形缓冲区
+ *@retval     none
+ */
+void ring_buf_clr(ring_buf_t *r)
+{
+    r->front = r->rear = 0;
+}
+
+/*
+ *@brief      获取环形缓冲区数据长度
+ *@retval     环形缓冲区中有效字节数 
+ */
+int ring_buf_len(ring_buf_t *r)
+{
+    return r->rear - r->front;
+}
+
+/*
+ *@brief       将指定长度的数据放到环形缓冲区中 
+ *@param[in]   buf - 数据缓冲区
+ *             len - 缓冲区长度 
+ *@retval      实际放到中的数据 
+ */
+int ring_buf_put(ring_buf_t *r,unsigned char *buf,unsigned int len)
+{
+    unsigned int i;
+    unsigned int left;
+    left = r->size + r->front - r->rear;
+    len  = min(len , left);
+    i    = min(len, r->size - (r->rear & r->size - 1));   
+    memcpy(r->buf + (r->rear & r->size - 1), buf, i); 
+    memcpy(r->buf, buf + i, len - i);
+    r->rear += len;     
+    return len;
+    
+}
+
+/*
+ *@brief       从环形缓冲区中读取指定长度的数据 
+ *@param[in]   len - 读取长度 
+ *@param[out]  buf - 输出数据缓冲区
+ *@retval      实际读取长度 
+ */
+int ring_buf_get(ring_buf_t *r,unsigned char *buf,unsigned int len)
+{
+    unsigned int i;
+    unsigned int left;    
+    left = r->rear - r->front;
+    len  = min(len , left);                                
+    i    = min(len, r->size - (r->front & r->size - 1));
+    memcpy(buf, r->buf + (r->front & r->size - 1), i);    
+    memcpy(buf + i, r->buf, len - i);   
+    r->front += len;
+    return len;
+}
@@ -0,0 +1,498 @@
+#include "spiflash.h"
+#include "rtthread.h"
+#include "DebugCmd.h"
+#include "Public.h"
+
+//#define	FLASH_TEST
+
+#ifdef FLASH_TEST
+uint8_t flashtestbuff[SPIFLASH_SIZE];
+#endif
+
+static uint8_t SpiFlashReadByte(void)
+{
+	return Spi1SendReceive(0);
+}
+
+static void SpiFlashSendByte(uint8_t sData)
+{
+	Spi1SendReceive(sData);
+}
+
+static void SpiFlashWriteEnable(void)
+{
+	SpiFlashClrNss();
+	SpiFlashSendByte(SPIFLASH_CMD_WREN);
+	SpiFlashSetNss();
+}
+
+static void SpiFlashWaitForWriteEnd(void)
+{
+	uint8_t flashstatus = 0;
+	SpiFlashClrNss();
+	SpiFlashSendByte(SPIFLASH_CMD_RDSR);
+	do{
+		flashstatus = SpiFlashReadByte();
+		FeedDog();
+	}
+	while ((flashstatus & SPIFLASH_WIP_FLAG) == SPIFLASH_WIP_FLAG); 
+	SpiFlashSetNss();
+}
+
+//扇区擦除
+void SpiFlashEraseSector(uint32_t SectorAddr)
+{
+#ifdef FLASH_TEST
+	memset(&flashtestbuff[SectorAddr], 0xff, 4096);
+#else	
+	SpiFlashWriteEnable();
+	SpiFlashWaitForWriteEnd();
+	SpiFlashClrNss();
+	SpiFlashSendByte(SPIFLASH_CMD_SE);
+	SpiFlashSendByte((SectorAddr >> 16) & 0x00FF);
+	SpiFlashSendByte((SectorAddr >> 8) & 0x00FF);
+	SpiFlashSendByte(SectorAddr & 0x00FF);
+	SpiFlashSetNss();
+	SpiFlashWaitForWriteEnd();
+#endif
+}
+
+//整片擦除
+void SpiFlashEraseChip(void)
+{
+	SpiFlashWriteEnable();
+	SpiFlashClrNss();
+	SpiFlashSendByte(SPIFLASH_CMD_BE);
+	SpiFlashSetNss();
+	SpiFlashWaitForWriteEnd();
+}
+
+//写数据
+void SpiFlashWriteData(uint8_t* wData, uint32_t wAddr, uint16_t wLen)
+{
+#ifdef FLASH_TEST
+	memcpy(&flashtestbuff[wAddr], wData, wLen);
+#else
+	SpiFlashWriteEnable();
+	SpiFlashClrNss();
+	SpiFlashSendByte(SPIFLASH_CMD_WRITE);
+	SpiFlashSendByte((wAddr >> 16) & 0x00FF);
+	SpiFlashSendByte((wAddr >> 8) & 0x00FF);
+	SpiFlashSendByte(wAddr & 0x00FF);
+	for(int i = 0; i < wLen; i++) {
+		SpiFlashSendByte(wData[i]);
+	}
+	SpiFlashSetNss();
+	SpiFlashWaitForWriteEnd();
+#endif	
+}
+
+void SpiFlashWriteAnyLengthData(uint8_t* wData, uint32_t wAddr, uint16_t wLen)
+{
+	uint16_t PageCnt;	//需要写入页数
+	uint16_t FirstPageWriteSize;	//在起始地址不为页起始地址的情况下，先写入当前页剩余空间
+	uint16_t LastPageWriteSize;	//最后一页写入长度
+	uint32_t AddrOffset = 0;
+	uint32_t WriteAddr;
+	LogHeader LogH;
+	WriteAddr = wAddr;
+	
+	//写入的长度超出最大空间，从起始开始写起
+	if((WriteAddr + wLen) > SPIFLASH_SIZE) {
+		LogH = (LogHeader)wData;
+		WriteAddr = LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE;
+		LogH->LogEndAddr = WriteAddr + wLen;
+	}
+	
+	uint16_t FirstPageRemainSpace = SPIFLASH_PAGESIZE - (WriteAddr % SPIFLASH_PAGESIZE);
+	
+//	//判断是否跨扇区，跨扇区需要先擦除下一扇区
+	CheckDelSecter(wAddr, wLen);
+	
+	if(wLen < FirstPageRemainSpace) {
+		FirstPageWriteSize = wLen;		//计算首页写入长度
+		PageCnt = 0;
+		LastPageWriteSize = 0;
+	} 
+	else {
+//		FirstPageWriteSize = FirstPageRemainSpace % SPIFLASH_PAGESIZE;
+//		PageCnt = (wLen - (FirstPageWriteSize % SPIFLASH_PAGESIZE)) / SPIFLASH_PAGESIZE;		//计算需要写入多少整页
+//		LastPageWriteSize = (wLen - (FirstPageWriteSize % SPIFLASH_PAGESIZE)) % SPIFLASH_PAGESIZE;	//计算剩余需要写入的长度
+		FirstPageWriteSize = FirstPageRemainSpace;
+		PageCnt = (wLen - FirstPageWriteSize) / SPIFLASH_PAGESIZE;		//计算需要写入多少整页
+		LastPageWriteSize = (wLen - FirstPageWriteSize) % SPIFLASH_PAGESIZE;	//计算剩余需要写入的长度
+	}
+	
+	if(FirstPageWriteSize > 0) {	
+		SpiFlashWriteData(&wData[AddrOffset], WriteAddr, FirstPageWriteSize);
+		AddrOffset += FirstPageWriteSize;
+		WriteAddr += FirstPageWriteSize;
+	}
+	for(int i = 0; i < PageCnt; i++) {	
+		SpiFlashWriteData(&wData[AddrOffset], WriteAddr, SPIFLASH_PAGESIZE);
+		AddrOffset += SPIFLASH_PAGESIZE;
+		WriteAddr += SPIFLASH_PAGESIZE;
+	}
+	if(LastPageWriteSize > 0) {		
+		SpiFlashWriteData(&wData[AddrOffset], WriteAddr, LastPageWriteSize);
+	}
+}
+
+void SpiFlashReadAnyLengthData(uint8_t* rData, uint32_t rAddr, uint16_t rLen)
+{
+#ifdef FLASH_TEST
+	memcpy(rData, &flashtestbuff[rAddr], rLen);
+#else	
+	SpiFlashClrNss();
+	SpiFlashSendByte(SPIFLASH_CMD_READ);
+	SpiFlashSendByte((rAddr >> 16) & 0x00FF);
+	SpiFlashSendByte((rAddr >> 8) & 0x00FF);
+	SpiFlashSendByte(rAddr & 0x00FF);
+	for(int i = 0; i < rLen; i++) {
+		rData[i] = SpiFlashReadByte();
+	}
+	SpiFlashSetNss();
+#endif	
+}
+
+uint32_t SpiFlashReadId(void)
+{
+	uint32_t Temp = 0, Temp0 = 0, Temp1 = 0, Temp2 = 0;
+	SpiFlashClrNss();
+	SpiFlashSendByte(0x9F);
+	Temp0 = SpiFlashReadByte();
+	Temp1 = SpiFlashReadByte();
+	Temp2 = SpiFlashReadByte();
+	SpiFlashSetNss();
+	Temp = (Temp0 << 16) | (Temp1 << 8) | Temp2;
+	return Temp;
+}
+
+typedef struct {
+	uint16_t Flag;
+	uint16_t LoopSavFlag;					//循环存储标志
+	uint32_t LogCnt;							//日志最大数量
+	uint32_t FirstLogStartAddr;		//第一个数据的起始地址
+	uint32_t LastLogEndAddr;			//最后一个数据的结束地址
+}LogNumSav_t;
+
+static LogNumSav_t LogNumArray[256];
+static __IO uint32_t gLogCnt = 0;
+static __IO uint32_t FirstLogStartAddr = 0;			//第一个日志起始地址
+static __IO uint32_t LastLogEndAddr = 0;				//最后一个日志结束地址
+static __IO uint16_t LoopSavFlag = 0;						//循环存储标志
+static uint16_t LogNumIdx;
+
+uint16_t ReadLoopSavFlag(void)
+{
+	return LoopSavFlag;
+}
+
+void SetLoopSavFlag(uint16_t LoopFlag)
+{
+	LoopSavFlag = LoopFlag;
+}
+
+uint32_t ReadLogNum(void)
+{
+	return gLogCnt;
+}
+
+void SetLogNum(uint32_t LogCnt)
+{
+	gLogCnt = LogCnt;
+}
+
+uint32_t ReadFirstLogStartAddr(void)
+{
+	return FirstLogStartAddr;
+}
+
+void SetFirstLogStartAddr(uint32_t FLStartAddr)
+{
+	FirstLogStartAddr = FLStartAddr;
+}
+
+
+uint32_t ReadLastLogEndAddr(void)
+{
+	return LastLogEndAddr;
+}
+
+void SetLastLogEndAddr(uint32_t LLEndAddr)
+{
+	LastLogEndAddr = LLEndAddr;
+}
+
+void LogInit(void)
+{
+	LogNumIdx = 0xffff;
+	SpiFlashReadId();
+	SpiFlashReadAnyLengthData((uint8_t *)&LogNumArray, LOG_INFO_START_SECTOR * SPIFLASH_SECTORSIZE, sizeof(LogNumArray));	
+	for(int i = 0; i < 256; i++) {
+		if(LogNumArray[i].Flag != LOG_INFO_SAV_FLAG) {
+			LogNumIdx = i;
+			break;
+		}
+	}
+	if(LogNumIdx == 0xffff) {			//256条记录满，读最后一条记录
+		LogNumIdx = 0;
+		SetLogNum(LogNumArray[255].LogCnt);
+		SetLoopSavFlag(LogNumArray[255].LoopSavFlag);
+		SetFirstLogStartAddr(LogNumArray[255].FirstLogStartAddr);
+		SetLastLogEndAddr(LogNumArray[255].LastLogEndAddr);
+		return;
+	}
+	if(LogNumIdx == 0) {			//没有记录
+		LogNumIdx = 0;
+		SetLogNum(0);
+		SetLoopSavFlag(0);
+		SetFirstLogStartAddr(LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE);
+		SetLastLogEndAddr(LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE);
+		return;
+	}
+	SetLogNum(LogNumArray[LogNumIdx-1].LogCnt);
+	SetLoopSavFlag(LogNumArray[LogNumIdx-1].LoopSavFlag);
+	SetFirstLogStartAddr(LogNumArray[LogNumIdx-1].FirstLogStartAddr);
+	SetLastLogEndAddr(LogNumArray[LogNumIdx-1].LastLogEndAddr);
+}
+
+void SavLogNum(uint32_t LogNum)
+{
+	LogNumSav_t CLogSav;
+	
+	if(LogNum == 0) {
+		LogNumIdx = 0;
+		SetLogNum(0);
+		SetLoopSavFlag(0);
+		SetFirstLogStartAddr(LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE);
+		SetLastLogEndAddr(LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE);
+		SpiFlashEraseSector(LOG_INFO_START_SECTOR * SPIFLASH_SECTORSIZE);
+		return;
+	}
+	
+	SetLogNum(LogNum);
+	CLogSav.Flag = LOG_INFO_SAV_FLAG;
+	CLogSav.LogCnt = LogNum;
+	CLogSav.FirstLogStartAddr = ReadFirstLogStartAddr();
+	CLogSav.LastLogEndAddr = ReadLastLogEndAddr();
+	
+	if(LogNumIdx == 256) {
+		SpiFlashEraseSector(LOG_INFO_START_SECTOR * SPIFLASH_SECTORSIZE);
+		LogNumIdx = 0;
+	}
+	SpiFlashWriteData((uint8_t *)&CLogSav, LogNumIdx * sizeof(LogNumSav_t) + LOG_INFO_START_SECTOR * SPIFLASH_SECTORSIZE, sizeof(LogNumSav_t));
+	LogNumIdx++;
+}
+
+/*****************************************************************************************
+* 函数名称: CheckDelSecter
+* 功能描述: 检查需要删除的扇区，跨扇区删除下一扇区，如果到了删除最后一个扇区，循环到起始扇区
+* 参    数: wAddr, 写入地址
+						wLen, 写入长度
+* 返 回 值: 返回写入起始地址
+*****************************************************************************************/
+uint8_t LogBuff[LOG_SAV_SIZE_MAX];
+const uint8_t SavFlag[4] ={0xAA, 0x55, 0x55, 0xAA};
+void CheckDelSecter(uint32_t wAddr, uint16_t wLen)
+{
+	uint32_t DelOffsetAddr, FindFirstLogAddr;				//存储起始地址
+	uint32_t DelSectorNum = 0;
+	uint32_t SurplusSpace = SPIFLASH_SECTORSIZE - (wAddr % SPIFLASH_SECTORSIZE);
+	
+	if((wAddr + wLen) > SPIFLASH_SIZE) {
+		DelOffsetAddr = LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE;
+		SetLastLogEndAddr(DelOffsetAddr + wLen);
+		SetLoopSavFlag(1);
+		SpiFlashEraseSector(DelOffsetAddr);
+		FindFirstLogAddr = DelOffsetAddr + SPIFLASH_SECTORSIZE;
+	}
+	else {
+		if(wLen < SurplusSpace) {	//长度没有超过扇区剩余容量
+			SetLastLogEndAddr(wAddr + wLen);
+			return;
+		}
+		DelOffsetAddr = (wAddr / SPIFLASH_SECTORSIZE + 1) * SPIFLASH_SECTORSIZE;
+		DelSectorNum = (wLen - SurplusSpace) / SPIFLASH_SECTORSIZE + 1;
+		SetLastLogEndAddr(wAddr + wLen);
+		for(int i = 0; i < DelSectorNum; i++) {
+			SpiFlashEraseSector(DelOffsetAddr);
+			DelOffsetAddr += SPIFLASH_SECTORSIZE;
+		}
+		if(DelOffsetAddr == SPIFLASH_SIZE) {
+			DelOffsetAddr = LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE;
+		}
+		FindFirstLogAddr = DelOffsetAddr;
+	}
+	
+	if(!ReadLoopSavFlag())
+		return;
+	
+	uint32_t ReadAddr = FindFirstLogAddr;
+	while(1) {
+		SpiFlashReadAnyLengthData(LogBuff, ReadAddr, LOG_SAV_SIZE_MAX);
+		int i;
+		for(i = 0; i < LOG_SAV_SIZE_MAX; i++) {
+			if(memcmp(&LogBuff[i], SavFlag, 4) == 0) {
+				SetFirstLogStartAddr(ReadAddr + i);
+				return;;
+			}
+		}
+		if(i == LOG_SAV_SIZE_MAX) {
+			ReadAddr += LOG_SAV_SIZE_MAX;
+			if(ReadAddr >= SPIFLASH_SIZE) {		//找不到下一条数据，重置flash
+				Debug_Printf("Add LOG Error, Next Data No Find!\r\n");
+				SetLogNum(0);
+				SetLoopSavFlag(0);
+				SetFirstLogStartAddr(LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE);
+				SetLastLogEndAddr(LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE);
+				return;
+			}
+		}
+	}
+}
+
+uint8_t LogBuffTemp[LOG_SAV_SIZE_MAX];
+void AddLog(uint8_t *wData, uint32_t wLen)
+{
+	//const uint8_t SavFlag[4] ={0xAA, 0x55, 0x55, 0xAA};
+	uint32_t LogNum;
+	uint32_t LogSize;
+	//uint32_t FLStartAddr;
+	uint32_t LLEndAddr;
+//	uint32_t SectorN;
+	LogHeader LogH;
+	
+	LogH = (LogHeader)LogBuffTemp;
+	
+	LogNum = ReadLogNum();
+	if(LogNum == 0) {
+		SetFirstLogStartAddr(LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE);
+		SetLastLogEndAddr(LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE);
+		SpiFlashEraseSector(LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE);
+	}
+	//FLStartAddr = ReadFirstLogStartAddr();
+	LLEndAddr = ReadLastLogEndAddr();
+	LogNum++;
+	LogH->LogSavFlag = LOG_SAV_FLAG;
+	LogH->LogIdx = LogNum;
+	LogSize = wLen + sizeof(LogHeader_t);
+	LogH->LogEndAddr = LLEndAddr + LogSize;
+	LogH->TimeStamp = TimeTs();
+	memcpy(&LogBuffTemp[sizeof(LogHeader_t)], wData, wLen);
+	
+	//判断是否跨扇区，跨扇区需要先擦除下一扇区
+	CheckDelSecter(LLEndAddr, LogSize);
+	if(LogH->LogEndAddr > SPIFLASH_SIZE) {
+		LLEndAddr = LOG_SAV_START_SECTOR * SPIFLASH_SECTORSIZE;
+		LogH->LogEndAddr = ReadLastLogEndAddr();
+	}
+	SpiFlashWriteAnyLengthData(LogBuffTemp, LLEndAddr, LogSize);
+		
+	SavLogNum(LogNum);
+	//Debug_Printf("Add LOG: %d,endaddr = %d\r\n", LogNum, ReadLastLogEndAddr());
+}
+
+
+/*****************************************************************************************
+* 函数名称: ReadLog
+* 功能描述: 读取日志
+* 参    数: Header, 上一包日志头信息，连续读取时传入上一包数据信息，缩短日志遍历时间，
+										Header->LogEndAddr为0读取第一包数据,LogIdx数据无效
+						rData, 日志出口，需要释放
+						LogIdx, 读取的日志的序号，为0读取Header->LogEndAddr对应日志
+* 返 回 值: 返回数据长度
+*****************************************************************************************/
+int ReadLog(LogHeader Header, uint8_t **rData, uint32_t LogIdx)
+{	
+	uint32_t FSAddr;
+	int LogLen = 0;
+	//bool FirstIdx = false;
+	
+	if(Header == NULL)
+		return 0;
+	
+	if(Header->LogEndAddr == 0) {
+		Header->LogEndAddr = ReadFirstLogStartAddr();
+		LogIdx = 0;
+	}
+	
+	if(LogIdx == 1) {
+		FSAddr = ReadFirstLogStartAddr();
+	}
+	else
+		FSAddr = Header->LogEndAddr;
+	
+	while(1) {
+		SpiFlashReadAnyLengthData((uint8_t *)Header, FSAddr, sizeof(LogHeader_t));
+		if(Header->LogSavFlag != LOG_SAV_FLAG) {
+			if((SPIFLASH_SIZE - FSAddr) < LOG_SAV_SIZE_MAX)	{	//判断是否到片尾
+				FSAddr = LOG_SAV_START_SECTOR * SPIFLASH_SECTOR_NUM;
+				continue;
+			}
+			else 
+				return 0;
+		}
+		if(LogIdx == 0) {
+			LogIdx = Header->LogIdx;
+		}
+		else if(Header->LogIdx != LogIdx) {
+			FSAddr = Header->LogEndAddr;
+			continue;
+		}
+
+		if(Header->LogIdx == LogIdx) {
+			if(*rData == NULL)
+				return sizeof(LogHeader_t);
+				
+			SpiFlashReadAnyLengthData(LogBuffTemp, FSAddr, Header->LogEndAddr - FSAddr);
+			LogLen = Header->LogEndAddr - FSAddr - sizeof(LogHeader_t);
+			void *pTemp  = rt_malloc(LogLen);
+			if(pTemp == NULL)
+				return 0;
+			
+			*rData =pTemp;
+			memcpy(*rData, &LogBuffTemp[sizeof(LogHeader_t)], LogLen);
+			break;
+		}
+	}
+	return LogLen;
+}
+
+
+/*****************************************************************************************
+* 函数名称: ReadPara
+* 功能描述: 读取参数
+* 参    数: Para, 网关参数
+						ParaLen, 参数长度
+* 返 回 值: 无
+*****************************************************************************************/
+int ReadPara(uint8_t *Para, uint32_t ParaLen)
+{	
+	SpiFlashReadAnyLengthData(Para, GATEWEY_PARA_SAV_ADDR, ParaLen);		//读取片尾数据
+	uint16_t Check = CRC_Modbus(0xA001, Para, ParaLen - 2);
+	GWConfigPara CfgPara = (GWConfigPara)Para;
+	if(CfgPara->crc16 != Check)
+		return -1;
+	return 0;
+}
+
+/*****************************************************************************************
+* 函数名称: WritePara
+* 功能描述: 写入参数
+* 参    数: Para, 网关参数
+						ParaLen, 参数长度
+* 返 回 值: 无
+*****************************************************************************************/
+int WritePara(uint8_t *Para, uint32_t ParaLen)
+{	
+	SpiFlashEraseSector(GATEWEY_PARA_SAV_ADDR);
+	
+	uint16_t Check = CRC_Modbus(0xA001, Para, ParaLen - 2);
+	GWConfigPara CfgPara = (GWConfigPara)Para;
+	CfgPara->crc16 = Check;
+	SpiFlashWriteAnyLengthData(Para, GATEWEY_PARA_SAV_ADDR, ParaLen);		//读取片尾数据
+	return 0;
+}
+
+/* USER CODE END */
@@ -0,0 +1,95 @@
+#include "update_protocol.h"
+#include "string.h"
+#include "public.h"
+
+static struct
+{
+    update_send_t   pfnSend;
+
+}g_update_protoc;
+
+
+void update_send_cmd(uint8_t Cmd, uint16_t Indx, int PageNum)
+{
+    uint8_t sData[24]={0};
+    uint8_t sLen =0;
+    uint16_t crc16;
+
+    update_protocol_hd_t *Frame = (update_protocol_hd_t*)sData;
+
+    Frame->Header = 0x7a;
+    Frame->SlvAddr = 0x01;
+    Frame->Cmd = Cmd;
+
+    if (Cmd == 0x01)
+    {
+        Frame->PayloadLen = 1;
+        sData[sizeof(update_protocol_hd_t)] = Indx;
+    }
+    else if (Cmd == 0x02)
+    {
+        Frame->PayloadLen = 4;
+        update_protocol_get_t *GDData = (update_protocol_get_t*)&sData[sizeof(update_protocol_hd_t)];
+        GDData->PackageIndex = Indx;
+        GDData->PackageNum   = PageNum;
+    }
+
+    sLen = sizeof(update_protocol_hd_t) + Frame->PayloadLen;
+    crc16 = CRC_Modbus(CRC16_BASE, sData, sLen);
+    sData[sLen++] = crc16;
+    sData[sLen++] = (crc16 >> 8) & 0x00ff;
+
+    g_update_protoc.pfnSend(sData, sLen);
+}
+
+void update_init(update_send_t pCbs)
+{
+  g_update_protoc.pfnSend =pCbs;
+}
+
+
+int update_unpack(uint8_t* rxData, int rLen,uint8_t *cmd,  uint8_t* dev_addr, void *pload, int *pLen){
+
+    uint16_t crc16;
+    
+    uint16_t    check;
+
+    check = CRC_Modbus(CRC16_BASE, rxData, rLen - 2);
+    
+    crc16 = (rxData[rLen - 1] << 8) | rxData[rLen - 2];
+
+    if (check != crc16 || rxData[0] !=0x7a || pload ==0)
+    {
+        return -1;
+    }
+
+    update_protocol_hd_t *Frame = (update_protocol_hd_t*)rxData;
+
+    *dev_addr = Frame->SlvAddr;
+    
+    *cmd = Frame->Cmd;
+    
+    if (Frame->Cmd == 0x81){
+        
+        //update_protocol_req_t *UpData = (update_protocol_req_t*)&rxData[sizeof(update_protocol_hd_t)];
+ 
+        pload =  0;
+        
+        *pLen = 0;
+        
+        
+    }else if (Frame->Cmd == 0x82){
+
+        update_protocol_rsp_t *DownData = (update_protocol_rsp_t *)&rxData[sizeof(update_protocol_hd_t)];
+        
+        memcpy(pload , &rxData[sizeof(update_protocol_hd_t) + sizeof(update_protocol_rsp_t)],DownData->DataLen);
+
+        *pLen = DownData->DataLen;
+ 
+    }else{
+        
+        return -2;
+    }
+       
+    return 0;
+}
@@ -0,0 +1,43 @@
+#include "utils.h"
+
+/*
+生成多项式 (x^16 + x^15 + x^2 + 1）
+*/
+uint16_t modbus_crc16(uint8_t* data, int length)
+{
+
+    uint16_t crc = 0xFFFF;  // 初始值FFFF
+    uint16_t polynomial = 0x8005;  // 多项式8005
+
+    for (int  i = 0; i < length; i++) {
+        // 输入反转(REFIN)：对每个字节进行位反转
+        uint8_t byte = data[i];
+        uint8_t reversed_byte = 0;
+
+        for (int j = 0; j < 8; j++) {
+            reversed_byte = (reversed_byte << 1) | (byte & 0x01);
+            byte >>= 1;
+        }
+
+        crc ^= (reversed_byte << 8);  // 与高字节异或
+
+        for (int j = 0; j < 8; j++) {
+            if (crc & 0x8000) {  // 检查最高位
+                crc = (crc << 1) ^ polynomial;
+            } else {
+                crc <<= 1;
+            }
+        }
+    }
+
+    // 输出反转(REFOUT)：对16位CRC结果进行位反转
+    uint16_t reversed_crc = 0;
+
+    for (int i = 0; i < 16; i++) {
+        reversed_crc = (reversed_crc << 1) | (crc & 0x0001);
+        crc >>= 1;
+    }
+
+    // 结果异或值(XOROUT)：0000（实际不变）
+    return reversed_crc ^ 0x0000;
+}
@@ -1,2 +1,3 @@
-# LaserTracing_Debug
+# GateWay

+一代网关
@@ -0,0 +1,8 @@
+<<<<<<< HEAD
+# GateWay
+
+一代网关
+=======
+# LaserTracing_Debug
+
+>>>>>>> aaff1aeec5ea03de83eee8888e10da1bf6a62ded
@@ -0,0 +1,8 @@
+<<<<<<< HEAD
+# GateWay
+
+一代网关
+=======
+# LaserTracing_Debug
+
+>>>>>>> aaff1aeec5ea03de83eee8888e10da1bf6a62ded
@@ -0,0 +1,3 @@
+# GateWay
+
+一代网关
@@ -0,0 +1,3 @@
+# GateWay
+
+一代网关
@@ -0,0 +1,2 @@
+# LaserTracing_Debug
+
@@ -0,0 +1,2 @@
+# LaserTracing_Debug
+
@@ -0,0 +1,509 @@
+/*******************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_adc.h
+ **
+ ** A detailed description is available at
+ ** @link AdcGroup Adc description @endlink
+ **
+ **   - 2018-11-30  CDT First version for Device Driver Library of Adc.
+ **
+ ******************************************************************************/
+#ifndef __HC32F460_ADC_H__
+#define __HC32F460_ADC_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_ADC_ENABLE == DDL_ON)
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup AdcGroup Analog-to-Digital Converter(ADC)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ *******************************************************************************
+ ** \brief  ADC average count.
+ **
+ ******************************************************************************/
+typedef enum en_adc_avcnt
+{
+    AdcAvcnt_2   = 0x0,                 ///< Average after 2 conversions.
+    AdcAvcnt_4   = 0x1,                 ///< Average after 4 conversions.
+    AdcAvcnt_8   = 0x2,                 ///< Average after 8 conversions.
+    AdcAvcnt_16  = 0x3,                 ///< Average after 16 conversions.
+    AdcAvcnt_32  = 0x4,                 ///< Average after 32 conversions.
+    AdcAvcnt_64  = 0x5,                 ///< Average after 64 conversions.
+    AdcAvcnt_128 = 0x6,                 ///< Average after 128 conversions.
+    AdcAvcnt_256 = 0x7,                 ///< Average after 256 conversions.
+} en_adc_avcnt_t;
+
+/**
+ *******************************************************************************
+ ** \brief  ADC data alignment
+ **
+ ******************************************************************************/
+typedef enum en_adc_data_align
+{
+    AdcDataAlign_Right = 0x0,           ///< Data right alignment.
+    AdcDataAlign_Left  = 0x1,           ///< Data left alignment.
+} en_adc_data_align_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Automatically clear data registers after reading data.
+ **         The auto clear function is mainly used to detect whether the data register
+ **         is updated.
+ **
+ ******************************************************************************/
+typedef enum en_adc_clren
+{
+    AdcClren_Disable = 0x0,             ///< Automatic clear function disable.
+    AdcClren_Enable  = 0x1,             ///< Automatic clear function enable.
+} en_adc_clren_t;
+
+/**
+ *******************************************************************************
+ ** \brief  ADC resolution.
+ **
+ ******************************************************************************/
+typedef enum en_adc_resolution
+{
+    AdcResolution_12Bit = 0x0,          ///< Resolution is 12 bit.
+    AdcResolution_10Bit = 0x1,          ///< Resolution is 10 bit.
+    AdcResolution_8Bit  = 0x2,          ///< Resolution is 8 bit.
+} en_adc_resolution_t;
+
+/**
+ *******************************************************************************
+ ** \brief  ADC scan mode.
+ **
+ ******************************************************************************/
+typedef enum en_adc_scan_mode
+{
+    AdcMode_SAOnce = 0x0,               ///< Sequence A works once.
+    AdcMode_SAContinuous = 0x1,         ///< Sequence A works always.
+    AdcMode_SAOnceSBOnce = 0x2,         ///< Sequence A and sequence B work once.
+    AdcMode_SAContinuousSBOnce = 0x3,   ///< Sequence A works always, sequence works once.
+} en_adc_scan_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief  ADC sequence A restart position.
+ **
+ ******************************************************************************/
+typedef enum en_adc_rschsel
+{
+    AdcRschsel_Continue = 0x0,          ///< After sequence A is interrupted by sequence B,
+                                        ///< sequence A continues to scan from the interrupt
+                                        ///< when it restarts.
+
+    AdcRschsel_Restart  = 0x1,          ///< After sequence A is interrupted by sequence B,
+                                        ///< sequence A restarts scanning from the first channel
+                                        ///< when it restarts.
+} en_adc_rschsel_t;
+
+/**
+ *******************************************************************************
+ ** \brief  ADC external or internal trigger source enable/disable .
+ **
+ ******************************************************************************/
+typedef enum en_adc_trgen
+{
+    AdcTrgen_Disable = 0x0,             ///< External or internal trigger source disable.
+    AdcTrgen_Enable  = 0x1,             ///< External or internal trigger source enable.
+} en_adc_trgen_t;
+
+/**
+ *******************************************************************************
+ ** \brief  ADC sequence trigger source selection.
+ **
+ ******************************************************************************/
+typedef enum en_adc_trgsel
+{
+    AdcTrgsel_ADTRGX = 0x0,             ///< X = 1(use ADC1) / 2(use ADC2), same as below.
+    AdcTrgsel_TRGX0 = 0x1,              ///< Pin IN_TRG10 / IN_TRG20.
+    AdcTrgsel_TRGX1 = 0x2,              ///< Pin IN_TRG11 / IN_TRG21.
+    AdcTrgsel_TRGX0_TRGX1 = 0x3,        ///< Pin IN_TRG10 + IN_TRG11 / IN_TRG20 + IN_TRG21.
+} en_adc_trgsel_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Sequence A/B conversion completion interrupt enable/disable.
+ **
+ ******************************************************************************/
+typedef enum en_adc_eocien
+{
+    AdcEocien_Disable = 0x0,            ///< Conversion completion interrupt disable.
+    AdcEocien_Enable  = 0x1,            ///< Conversion completion interrupt enable.
+} en_adc_eocien_t;
+
+/**
+ *******************************************************************************
+ ** \brief ADC sync mode.
+ **
+ ******************************************************************************/
+typedef enum en_adc_sync_mode
+{
+    AdcSync_SingleSerial       = 0x0u,      ///< Single: ADC1 and ADC2 only sample and convert once after triggering.
+                                            ///< Serial: ADC2 start after ADC1 N PCLK4 cycles.
+    AdcSync_SingleParallel     = 0x2u,      ///< Parallel: ADC1 and ADC2 start at the same time.
+    AdcSync_ContinuousSerial   = 0x4u,      ///< Continuous: ADC1 and ADC2 continuously sample and convert after triggering.
+    AdcSync_ContinuousParallel = 0x6u,
+} en_adc_sync_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief  ADC sync enable/disable.
+ **
+ ******************************************************************************/
+typedef enum en_adc_syncen
+{
+    AdcSync_Disable = 0x0,              ///< Disable sync mode.
+    AdcSync_Enable  = 0x1,              ///< Enable sync mode.
+} en_adc_syncen_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Analog watchdog interrupt enable/disable.
+ **
+ ******************************************************************************/
+typedef enum en_adc_awdien
+{
+    AdcAwdInt_Disable = 0x0,            ///< Disable AWD interrupt.
+    AdcAwdInt_Enable  = 0x1,            ///< Enable AWD interrupt.
+} en_adc_awdien_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Analog watchdog interrupt event sequence selection.
+ **
+ ******************************************************************************/
+typedef enum en_adc_awdss
+{
+    AdcAwdSel_SA_SB = 0x0,              ///< Sequence A and B output interrupt event -- ADC_SEQCMP.
+    AdcAwdSel_SA    = 0x1,              ///< Sequence A output interrupt event -- ADC_SEQCMP.
+    AdcAwdSel_SB    = 0x2,              ///< Sequence B output interrupt event -- ADC_SEQCMP.
+    AdcAwdSel_SB_SA = 0x3,              ///< Same as AdcAwdSel_SA_SB.
+} en_adc_awdss_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Analog watchdog comparison mode selection.
+ **
+ ******************************************************************************/
+typedef enum en_adc_awdmd
+{
+    AdcAwdCmpMode_0 = 0x0,              ///< Upper limit is AWDDR0, lower limit is AWDDR1.
+                                        ///< If AWDDR0 > result or result > AWDDR1,
+                                        ///< the interrupt will be occur.
+
+    AdcAwdCmpMode_1 = 0x1,              ///< The range is [AWDDR0, AWDDR1].
+                                        ///< If AWDDR0 <= result <= AWDDR1, the interrupt will be occur.
+} en_adc_awdmd_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Analog watchdog enable/disable.
+ **
+ ******************************************************************************/
+typedef enum en_adc_awden
+{
+    AdcAwd_Disable = 0x0,               ///< Disable AWD.
+    AdcAwd_Enable  = 0x1,               ///< Enable AWD.
+} en_adc_awden_t;
+
+/**
+ *******************************************************************************
+ ** \brief  PGA control.
+ **
+ ******************************************************************************/
+typedef enum en_adc_pga_ctl
+{
+    AdcPgaCtl_Invalid = 0x0,            ///< Amplifier is invalid.
+    AdcPgaCtl_Amplify = 0xE,            ///< Amplifier effective.
+} en_adc_pga_ctl_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The amplification factor of the amplifier is as follows.
+ **
+ ******************************************************************************/
+typedef enum en_adc_pga_factor
+{
+    AdcPgaFactor_2      = 0x0,          ///< PGA magnification 2.
+    AdcPgaFactor_2P133  = 0x1,          ///< PGA magnification 2.133.
+    AdcPgaFactor_2P286  = 0x2,          ///< PGA magnification 2.286.
+    AdcPgaFactor_2P667  = 0x3,          ///< PGA magnification 2.667.
+    AdcPgaFactor_2P909  = 0x4,          ///< PGA magnification 2.909.
+    AdcPgaFactor_3P2    = 0x5,          ///< PGA magnification 3.2.
+    AdcPgaFactor_3P556  = 0x6,          ///< PGA magnification 3.556.
+    AdcPgaFactor_4      = 0x7,          ///< PGA magnification 4.
+    AdcPgaFactor_4P571  = 0x8,          ///< PGA magnification 4.571.
+    AdcPgaFactor_5P333  = 0x9,          ///< PGA magnification 5.333.
+    AdcPgaFactor_6P4    = 0xA,          ///< PGA magnification 6.4.
+    AdcPgaFactor_8      = 0xB,          ///< PGA magnification 8.
+    AdcPgaFactor_10P667 = 0xC,          ///< PGA magnification 10.667.
+    AdcPgaFactor_16     = 0xD,          ///< PGA magnification 16.
+    AdcPgaFactor_32     = 0xE,          ///< PGA magnification 32.
+} en_adc_pga_factor_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Negative phase input selection
+ **
+ ******************************************************************************/
+typedef enum en_adc_pga_negative
+{
+    AdcPgaNegative_PGAVSS = 0x0,        ///< Use external port PGAVSS as PGA negative input.
+    AdcPgaNegative_VSSA   = 0x1,        ///< Use internal analog ground VSSA as PGA negative input.
+} en_adc_pga_negative_t;
+
+/**
+ *******************************************************************************
+ ** \brief  ADC common trigger source select
+ **
+ ******************************************************************************/
+typedef enum en_adc_com_trigger
+{
+    AdcComTrigger_1   = 0x1,            ///< Select common trigger 1.
+    AdcComTrigger_2   = 0x2,            ///< Select common trigger 2.
+    AdcComTrigger_1_2 = 0x3,            ///< Select common trigger 1 and 2.
+} en_adc_com_trigger_t;
+
+/**
+ *******************************************************************************
+ ** \brief Structure definition of ADC
+ **
+ ******************************************************************************/
+typedef struct stc_adc_ch_cfg
+{
+    uint32_t            u32Channel;     ///< ADC channels mask.
+    uint8_t             u8Sequence;     ///< The sequence which the channel(s) belong to.
+    uint8_t            *pu8SampTime;    ///< Pointer to sampling time.
+} stc_adc_ch_cfg_t;
+
+typedef struct stc_adc_awd_cfg
+{
+    en_adc_awdmd_t      enAwdmd;        ///< Comparison mode of the values.
+    en_adc_awdss_t      enAwdss;        ///< Interrupt output select.
+    uint16_t            u16AwdDr0;      ///< Your range DR0.
+    uint16_t            u16AwdDr1;      ///< Your range DR1.
+} stc_adc_awd_cfg_t;
+
+typedef struct stc_adc_trg_cfg
+{
+    uint8_t           u8Sequence;       ///< The sequence will be configured trigger source.
+    en_adc_trgsel_t   enTrgSel;         ///< Trigger source type.
+    en_event_src_t    enInTrg0;         ///< Internal trigger 0 source number
+                                        ///< (event number @ref en_event_src_t).
+    en_event_src_t    enInTrg1;         ///< Internal trigger 1 source number
+                                        ///< (event number @ref en_event_src_t).
+} stc_adc_trg_cfg_t;
+
+typedef struct stc_adc_init
+{
+    en_adc_resolution_t enResolution;   ///< ADC resolution 12bit/10bit/8bit.
+    en_adc_data_align_t enDataAlign;    ///< ADC data alignment.
+    en_adc_clren_t      enAutoClear;    ///< Automatically clear data register.
+                                        ///< after reading data register(enable/disable).
+    en_adc_scan_mode_t  enScanMode;     ///< ADC scan mode.
+    en_adc_rschsel_t    enRschsel;      ///< Restart or continue.
+} stc_adc_init_t;
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ *******************************************************************************
+ ** \brief ADC sequence definition.
+ **
+ ******************************************************************************/
+/* ADC sequence definition */
+#define ADC_SEQ_A               ((uint8_t)0)
+#define ADC_SEQ_B               ((uint8_t)1)
+
+/* ADC pin definition */
+#define ADC1_IN0                ((uint8_t)0)
+#define ADC1_IN1                ((uint8_t)1)
+#define ADC1_IN2                ((uint8_t)2)
+#define ADC1_IN3                ((uint8_t)3)
+#define ADC12_IN4               ((uint8_t)4)
+#define ADC12_IN5               ((uint8_t)5)
+#define ADC12_IN6               ((uint8_t)6)
+#define ADC12_IN7               ((uint8_t)7)
+#define ADC12_IN8               ((uint8_t)8)
+#define ADC12_IN9               ((uint8_t)9)
+#define ADC12_IN10              ((uint8_t)10)
+#define ADC12_IN11              ((uint8_t)11)
+#define ADC1_IN12               ((uint8_t)12)
+#define ADC1_IN13               ((uint8_t)13)
+#define ADC1_IN14               ((uint8_t)14)
+#define ADC1_IN15               ((uint8_t)15)
+#define ADC_PIN_INVALID         ((uint8_t)0xFF)
+
+/* ADC channel index definition */
+#define ADC_CH_IDX0             (0u)
+#define ADC_CH_IDX1             (1u)
+#define ADC_CH_IDX2             (2u)
+#define ADC_CH_IDX3             (3u)
+#define ADC_CH_IDX4             (4u)
+#define ADC_CH_IDX5             (5u)
+#define ADC_CH_IDX6             (6u)
+#define ADC_CH_IDX7             (7u)
+#define ADC_CH_IDX8             (8u)
+#define ADC_CH_IDX9             (9u)
+#define ADC_CH_IDX10            (10u)
+#define ADC_CH_IDX11            (11u)
+#define ADC_CH_IDX12            (12u)
+#define ADC_CH_IDX13            (13u)
+#define ADC_CH_IDX14            (14u)
+#define ADC_CH_IDX15            (15u)
+#define ADC_CH_IDX16            (16u)
+
+/* ADC1 channel mask definition */
+#define ADC1_CH0                (0x1ul << 0u)       ///< Default mapping pin ADC1_IN0
+#define ADC1_CH1                (0x1ul << 1u)       ///< Default mapping pin ADC1_IN1
+#define ADC1_CH2                (0x1ul << 2u)       ///< Default mapping pin ADC1_IN2
+#define ADC1_CH3                (0x1ul << 3u)       ///< Default mapping pin ADC1_IN3
+#define ADC1_CH4                (0x1ul << 4u)       ///< Default mapping pin ADC12_IN4
+#define ADC1_CH5                (0x1ul << 5u)       ///< Default mapping pin ADC12_IN5
+#define ADC1_CH6                (0x1ul << 6u)       ///< Default mapping pin ADC12_IN6
+#define ADC1_CH7                (0x1ul << 7u)       ///< Default mapping pin ADC12_IN7
+#define ADC1_CH8                (0x1ul << 8u)       ///< Default mapping pin ADC12_IN8
+#define ADC1_CH9                (0x1ul << 9u)       ///< Default mapping pin ADC12_IN9
+#define ADC1_CH10               (0x1ul << 10u)      ///< Default mapping pin ADC12_IN10
+#define ADC1_CH11               (0x1ul << 11u)      ///< Default mapping pin ADC12_IN11
+#define ADC1_CH12               (0x1ul << 12u)      ///< Default mapping pin ADC12_IN12
+#define ADC1_CH13               (0x1ul << 13u)      ///< Default mapping pin ADC12_IN13
+#define ADC1_CH14               (0x1ul << 14u)      ///< Default mapping pin ADC12_IN14
+#define ADC1_CH15               (0x1ul << 15u)      ///< Default mapping pin ADC12_IN15
+#define ADC1_CH16               (0x1ul << 16u)
+#define ADC1_CH_INTERNAL        (ADC1_CH16)         ///< 8bit DAC_1/DAC_2 or internal VERF, dependent on CMP_RVADC
+#define ADC1_CH_ALL             (0x0001FFFFul)
+#define ADC1_PIN_MASK_ALL       (ADC1_CH_ALL & ~ADC1_CH_INTERNAL)
+
+/* ADC2 channel definition */
+#define ADC2_CH0                (0x1ul << 0u)       ///< Default mapping pin ADC12_IN4
+#define ADC2_CH1                (0x1ul << 1u)       ///< Default mapping pin ADC12_IN5
+#define ADC2_CH2                (0x1ul << 2u)       ///< Default mapping pin ADC12_IN6
+#define ADC2_CH3                (0x1ul << 3u)       ///< Default mapping pin ADC12_IN7
+#define ADC2_CH4                (0x1ul << 4u)       ///< Default mapping pin ADC12_IN8
+#define ADC2_CH5                (0x1ul << 5u)       ///< Default mapping pin ADC12_IN9
+#define ADC2_CH6                (0x1ul << 6u)       ///< Default mapping pin ADC12_IN10
+#define ADC2_CH7                (0x1ul << 7u)       ///< Default mapping pin ADC12_IN11
+#define ADC2_CH8                (0x1ul << 8u)
+#define ADC2_CH_INTERNAL        (ADC2_CH8)          ///< 8bit DAC_1/DAC_2 or internal VERF, dependent on CMP_RVADC
+#define ADC2_CH_ALL             (0x000001FFul)
+#define ADC2_PIN_MASK_ALL       (ADC2_CH_ALL & ~ADC2_CH_INTERNAL)
+
+/*
+* PGA channel definition.
+* NOTE: The PGA channel directly maps external pins and does not correspond to the ADC channel.
+*/
+#define PGA_CH0                 (0x1ul << ADC1_IN0)     ///< Mapping pin ADC1_IN0
+#define PGA_CH1                 (0x1ul << ADC1_IN1)     ///< Mapping pin ADC1_IN1
+#define PGA_CH2                 (0x1ul << ADC1_IN2)     ///< Mapping pin ADC1_IN2
+#define PGA_CH3                 (0x1ul << ADC1_IN3)     ///< Mapping pin ADC1_IN3
+#define PGA_CH4                 (0x1ul << ADC12_IN4)    ///< Mapping pin ADC12_IN4
+#define PGA_CH5                 (0x1ul << ADC12_IN5)    ///< Mapping pin ADC12_IN5
+#define PGA_CH6                 (0x1ul << ADC12_IN6)    ///< Mapping pin ADC12_IN6
+#define PGA_CH7                 (0x1ul << ADC12_IN7)    ///< Mapping pin ADC12_IN7
+#define PGA_CH8                 (0x1ul << ADC12_IN8)    ///< Mapping internal 8bit DAC1 output
+#define PGA_CH_ALL              (0x000001FFul)
+
+/* ADC1 has up to 17 channels */
+#define ADC1_CH_COUNT           (17u)
+
+/* ADC2 has up to 9 channels */
+#define ADC2_CH_COUNT           (9u)
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+en_result_t ADC_Init(M4_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcInit);
+en_result_t ADC_DeInit(M4_ADC_TypeDef *ADCx);
+
+en_result_t ADC_SetScanMode(M4_ADC_TypeDef *ADCx, en_adc_scan_mode_t enMode);
+en_result_t ADC_ConfigTriggerSrc(M4_ADC_TypeDef *ADCx, const stc_adc_trg_cfg_t *pstcTrgCfg);
+en_result_t ADC_TriggerSrcCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enState);
+void ADC_ComTriggerCmd(M4_ADC_TypeDef *ADCx, en_adc_trgsel_t enTrgSel, \
+                       en_adc_com_trigger_t enComTrigger, en_functional_state_t enState);
+
+en_result_t ADC_AddAdcChannel(M4_ADC_TypeDef *ADCx, const stc_adc_ch_cfg_t *pstcChCfg);
+en_result_t ADC_DelAdcChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel);
+en_result_t ADC_SeqITCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enState);
+
+en_result_t ADC_ConfigAvg(M4_ADC_TypeDef *ADCx, en_adc_avcnt_t enAvgCnt);
+en_result_t ADC_AddAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel);
+en_result_t ADC_DelAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel);
+
+en_result_t ADC_ConfigAwd(M4_ADC_TypeDef *ADCx, const stc_adc_awd_cfg_t *pstcAwdCfg);
+en_result_t ADC_AwdCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState);
+en_result_t ADC_AwdITCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState);
+en_result_t ADC_AddAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel);
+en_result_t ADC_DelAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel);
+
+void ADC_ConfigPga(en_adc_pga_factor_t enFactor, en_adc_pga_negative_t enNegativeIn);
+void ADC_PgaCmd(en_functional_state_t enState);
+void ADC_AddPgaChannel(uint32_t u32Channel);
+void ADC_DelPgaChannel(uint32_t u32Channel);
+
+void ADC_ConfigSync(en_adc_sync_mode_t enMode, uint8_t u8TrgDelay);
+void ADC_SyncCmd(en_functional_state_t enState);
+
+en_result_t ADC_StartConvert(M4_ADC_TypeDef *ADCx);
+en_result_t ADC_StopConvert(M4_ADC_TypeDef *ADCx);
+en_flag_status_t ADC_GetEocFlag(const M4_ADC_TypeDef *ADCx, uint8_t u8Seq);
+void ADC_ClrEocFlag(M4_ADC_TypeDef *ADCx, uint8_t u8Seq);
+en_result_t ADC_PollingSa(M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length, uint32_t u32Timeout);
+
+en_result_t ADC_GetAllData(const M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length);
+en_result_t ADC_GetChData(const M4_ADC_TypeDef *ADCx, uint32_t u32TargetCh, uint16_t *pu16AdcData, uint8_t u8Length);
+uint16_t ADC_GetValue(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex);
+
+uint32_t ADC_GetAwdFlag(const M4_ADC_TypeDef *ADCx);
+void ADC_ClrAwdFlag(M4_ADC_TypeDef *ADCx);
+void ADC_ClrAwdChFlag(M4_ADC_TypeDef *ADCx, uint32_t u32AwdCh);
+
+en_result_t ADC_ChannelRemap(M4_ADC_TypeDef *ADCx, uint32_t u32DestChannel, uint8_t u8AdcPin);
+uint8_t ADC_GetChannelPinNum(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex);
+
+//@} // AdcGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_ADC_ENABLE */
+
+#endif /* __HC32F460_ADC_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,81 @@
+/*******************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_aes.h
+ **
+ ** A detailed description is available at
+ ** @link AesGroup Aes description @endlink
+ **
+ **   - 2018-10-20  CDT First version for Device Driver Library of Aes.
+ **
+ ******************************************************************************/
+#ifndef __HC32F460_AES_H__
+#define __HC32F460_AES_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_AES_ENABLE == DDL_ON)
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup AesGroup Advanced Encryption Standard(AES)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+ /* AES key length in bytes is 16. */
+#define AES_KEYLEN                          ((uint8_t)16)
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+en_result_t AES_Encrypt(const uint8_t *pu8Plaintext,
+                        uint32_t u32PlaintextSize,
+                        const uint8_t *pu8Key,
+                        uint8_t *pu8Ciphertext);
+
+en_result_t AES_Decrypt(const uint8_t *pu8Ciphertext,
+                        uint32_t u32CiphertextSize,
+                        const uint8_t *pu8Key,
+                        uint8_t *pu8Plaintext);
+
+//@} // AesGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_AES_ENABLE */
+
+#endif /* __HC32F460_AES_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,518 @@
+/*****************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_can.h
+ **
+ ** A detailed description is available at
+ ** @link CanGroup CAN description @endlink
+ **
+ **   - 2018-11-27  CDT First version for Device Driver Library of CAN
+ **
+ ******************************************************************************/
+#ifndef __HC32F460_CAN_H__
+#define __HC32F460_CAN_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_CAN_ENABLE == DDL_ON)
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup CanGroup Controller Area Network(CAN)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/**
+ *******************************************************************************
+ ** \brief  The Can error types.
+ ******************************************************************************/
+typedef enum
+{
+    NO_ERROR        = 0U,
+    BIT_ERROR       = 1U,
+    FORM_ERROR      = 2U,
+    STUFF_ERROR     = 3U,
+    ACK_ERROR       = 4U,
+    CRC_ERROR       = 5U,
+    UNKOWN_ERROR    = 6U,
+}en_can_error_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Can transmit buffer select.(TCMD)
+ ******************************************************************************/
+typedef enum
+{
+    CanPTBSel       = 0U,        ///< high-priority buffer
+    CanSTBSel       = 1U,        ///< secondary buffer
+}en_can_buffer_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Can warning limits.(AFWL)
+ ******************************************************************************/
+typedef struct stc_can_warning_limit
+{
+    uint8_t CanWarningLimitVal;         ///< Receive buffer almost full warning limit
+    uint8_t CanErrorWarningLimitVal;    ///< Programmable error warning limit
+}stc_can_warning_limit_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Acceptance Filters Frame Format Check.(ACF)
+ ******************************************************************************/
+typedef enum en_can_acf_format_en
+{
+    CanStdFrames        = 0x02u,   ///< Accepts only Standard frames
+    CanExtFrames        = 0x03u,   ///< Accepts only Extended frames
+    CanAllFrames        = 0x00u,   ///< Accepts both standard or extended frames
+}en_can_acf_format_en_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Acceptance Filters Enable.(ACFEN)
+ ******************************************************************************/
+typedef enum en_can_filter_sel
+{
+    CanFilterSel1        = 0u,   ///< The Acceptance Filter 1 Enable
+    CanFilterSel2        = 1u,   ///< The Acceptance Filter 2 Enable
+    CanFilterSel3        = 2u,   ///< The Acceptance Filter 3 Enable
+    CanFilterSel4        = 3u,   ///< The Acceptance Filter 4 Enable
+    CanFilterSel5        = 4u,   ///< The Acceptance Filter 5 Enable
+    CanFilterSel6        = 5u,   ///< The Acceptance Filter 6 Enable
+    CanFilterSel7        = 6u,   ///< The Acceptance Filter 7 Enable
+    CanFilterSel8        = 7u,   ///< The Acceptance Filter 8 Enable
+}en_can_filter_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The can interrupt enable.(IE)
+ ******************************************************************************/
+typedef enum
+{
+    //<<Can Rx or Tx Irq En
+    CanRxIrqEn              = 0x00000080,   ///< Receive interrupt enable
+    CanRxOverIrqEn          = 0x00000040,   ///< RB overrun interrupt enable
+    CanRxBufFullIrqEn       = 0x00000020,   ///< RB full interrupt enable
+    CanRxBufAlmostFullIrqEn = 0x00000010,   ///< RB almost full interrupt enable
+    CanTxPrimaryIrqEn       = 0x00000008,   ///< Transmission primary interrupt enable
+    CanTxSecondaryIrqEn     = 0x00000004,   ///< Transmission secondary enable
+    CanErrorIrqEn           = 0x00000002,   ///< Error interrupt enable
+
+    //<<Can Error Irq En
+    CanErrorPassiveIrqEn    = 0x00200000,   ///< Error passive mode active enable
+    CanArbiLostIrqEn        = 0x00080000,   ///< Arbitration lost interrupt enable
+    CanBusErrorIrqEn        = 0x00020000,   ///< Bus error interrupt enable
+}en_can_irq_type_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The can interrupt flag.(IF)
+ ******************************************************************************/
+typedef enum
+{
+    //<<Can Tx or Tx Irq Flg
+    CanTxBufFullIrqFlg          = 0x00000001,   ///<
+    CanRxIrqFlg                 = 0x00008000,   ///< Receive interrupt flag
+    CanRxOverIrqFlg             = 0x00004000,   ///< RB overrun interrupt flag
+    CanRxBufFullIrqFlg          = 0x00002000,   ///< RB full interrupt flag
+    CanRxBufAlmostFullIrqFlg    = 0x00001000,   ///< RB almost full interrupt flag
+    CanTxPrimaryIrqFlg          = 0x00000800,   ///< Transmission primary interrupt flag
+    CanTxSecondaryIrqFlg        = 0x00000400,   ///< Transmission secondary interrupt flag
+    CanErrorIrqFlg              = 0x00000200,   ///< Error interrupt flag
+    CanAbortIrqFlg              = 0x00000100,   ///< Abort interrupt flag
+
+    //<< Can Error Irq Flg
+    CanErrorWarningIrqFlg       = 0x00800000,   ///< Error warning limit reached flag
+    CanErrorPassivenodeIrqFlg   = 0x00400000,   ///< Error passive mode active flag
+    CanErrorPassiveIrqFlg       = 0x00100000,   ///< Error passive interrupt flag
+    CanArbiLostIrqFlg           = 0x00040000,   ///< Arbitration lost interrupt flag
+    CanBusErrorIrqFlg           = 0x00010000,   ///< Bus error interrupt flag
+}en_can_irq_flag_type_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The can mode.(TCMD)
+ ******************************************************************************/
+typedef enum
+{
+    CanExternalLoopBackMode  = 0x40,        ///< Loop back mode, external
+    CanInternalLoopBackMode  = 0x20,        ///< Loop back mode, internal
+    CanTxSignalPrimaryMode   = 0x10,        ///< Transmission primary single shot mode for PTB
+    CanTxSignalSecondaryMode = 0x08,        ///< Transmission secondary single shot mode for STB
+    CanListenOnlyMode        = 0xFF,        ///< Listen only mode
+}en_can_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The can status.(STAT)
+ ******************************************************************************/
+typedef enum
+{
+    CanRxActive = 0x04,        ///< Reception active
+    CanTxActive = 0x02,        ///< Transmission active
+    CanBusoff   = 0x01,        ///< Bus off
+}en_can_status_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Can Tx Command.(TCMD)
+ ******************************************************************************/
+typedef enum
+{
+    CanPTBTxCmd      = 0x10,        ///< Transmit primary for PTB
+    CanPTBTxAbortCmd = 0x08,        ///< Transmit primary abort for PTB
+    CanSTBTxOneCmd   = 0x04,        ///< Transmit secondary one frame for STB
+    CanSTBTxAllCmd   = 0x02,        ///< Transmit secondary all frames for STB
+    CanSTBTxAbortCmd = 0x01,        ///< Transmit secondary abort for STB
+}en_can_tx_cmd_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Can Transmit buffer secondary operation mode.(TCTRL)
+ ******************************************************************************/
+typedef enum
+{
+    CanSTBFifoMode    = 0,        ///< FIFO mode
+    CanSTBPrimaryMode = 1,        ///< Priority decision mode
+}en_can_stb_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Can Self-ACKnowledge.(RCTRL)
+ ******************************************************************************/
+typedef enum
+{
+    CanSelfAckEnable  = 1,        ///< Self-ACK when LBME=1
+    CanSelfAckDisable = 0,        ///< no self-ACK
+}en_can_self_ack_en_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Can Receive Buffer Overflow Mode.(RCTRL)
+ ******************************************************************************/
+typedef enum
+{
+    CanRxBufOverwritten = 0,        ///< The oldest message will be overwritten
+    CanRxBufNotStored   = 1,        ///< The new message will not be stored
+}en_can_rx_buf_mode_en_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Can Receive Buffer Stores All data frames.(RCTRL)
+ ******************************************************************************/
+typedef enum
+{
+    CanRxNormal = 0,        ///< Normal operation
+    CanRxAll    = 1,        ///< RB stores correct data frames as well as data frames with error
+}en_can_rx_buf_all_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Can Receive Buffer Status.(RSTAT)
+ ******************************************************************************/
+typedef enum
+{
+    CanRxBufEmpty          = 0,        ///< Empty
+    CanRxBufnotAlmostFull  = 1,        ///< >empty and <almost full
+    CanRxBufAlmostFull     = 2,        ///< >=almost full, but not full and no overflow
+    CanRxBufFull           = 3,        ///< full
+}en_can_rx_buf_status_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Can Transmission secondary Status.(TSSTAT)
+ ******************************************************************************/
+typedef enum
+{
+    CanTxBufEmpty        = 0,       ///< TTEN=0 or  TTTBM=0: STB is empty
+                                    ///< TTEN=1 and TTTBM=1: PTB and STB are empty
+    CanTxBufnotHalfFull  = 1,       ///< TTEN=0 or  TTTBM=0: STB is less than or equal to half full
+                                    ///< TTEN=1 and TTTBM=1: PTB and STB are not empty and not full
+    CanTxBufHalfFull     = 2,       ///< TTEN=0 or  TTTBM=0: STB is more than half full
+                                    ///< TTEN=1 and TTTBM=1: None
+    CanTxBufFull         = 3,       ///< TTEN=0 or  TTTBM=0: STB is full
+                                    ///< TTEN=1 and TTTBM=1: PTB and STB are full
+}en_can_tx_buf_status_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN Acceptance Filter Code and Mask.
+ ******************************************************************************/
+typedef struct stc_can_filter
+{
+    uint32_t                u32CODE;        ///< Acceptance CODE
+    uint32_t                u32MASK;        ///< Acceptance MASK
+    en_can_filter_sel_t     enFilterSel;    ///< The Acceptance Filters Enable
+    en_can_acf_format_en_t  enAcfFormat;    ///< The Acceptance Filters Frame Format Check.
+}stc_can_filter_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN Bit Timing.
+ ******************************************************************************/
+typedef struct stc_can_bt
+{
+    uint8_t SEG_1;      ///< Bit timing segment 1(Tseg_1 = (SEG_1 + 2)*TQ)
+    uint8_t SEG_2;      ///< Bit timing segment 2(Tseg_2 = (SEG_2 + 1)*TQ)
+    uint8_t SJW;        ///< Synchronization jump width(Tsjw = (SJW + 1)*TQ)
+    uint8_t PRESC;      ///< The Prescaler divides the system clock to get the time quanta clock tq_clk(TQ)
+}stc_can_bt_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN Control Frame.
+ ******************************************************************************/
+typedef struct
+{
+    uint32_t DLC         : 4;       ///< Data length code
+    uint32_t RESERVED0   : 2;       ///< Ignore
+    uint32_t RTR         : 1;       ///< Remote transmission request
+    uint32_t IDE         : 1;       ///< IDentifier extension
+    uint32_t RESERVED1   : 24;      ///< Ignore
+}stc_can_txcontrol_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN Tx Frame.
+ ******************************************************************************/
+typedef struct stc_can_txframe
+{
+    union
+    {
+        uint32_t TBUF32_0;                  ///< Ignore
+        uint32_t StdID;                     ///< Standard ID
+        uint32_t ExtID;                     ///< Extended ID
+    };
+    union
+    {
+        uint32_t TBUF32_1;                  ///< Ignore
+        stc_can_txcontrol_t Control_f;      ///< CAN Tx Control
+    };
+    union
+    {
+        uint32_t TBUF32_2[2];               ///< Ignore
+        uint8_t  Data[8];                   ///< CAN data
+    };
+    en_can_buffer_sel_t     enBufferSel;    ///< CAN Tx buffer select
+}stc_can_txframe_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN Rx Ctrl.
+ ******************************************************************************/
+typedef struct
+{
+    uint8_t DLC          : 4;       ///< Data length code
+    uint8_t RESERVED0    : 2;       ///< Ignore
+    uint8_t RTR          : 1;       ///< Remote transmission request
+    uint8_t IDE          : 1;       ///< IDentifier extension
+}stc_can_rxcontrol_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN status.
+ ******************************************************************************/
+typedef struct
+{
+    uint8_t RESERVED0    : 4;       ///< Ignore
+    uint8_t TX           : 1;       ///< TX is set to 1 if the loop back mode is activated
+    uint8_t KOER         : 3;       ///< Kind of error
+}stc_can_status_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN control, status and cycletime.
+ ******************************************************************************/
+typedef struct
+{
+    stc_can_rxcontrol_t Control_f;      ///< @ref stc_can_rxcontrol_t
+    stc_can_status_t    Status_f;       ///< @ref stc_can_status_t
+    uint16_t            CycleTime;      ///< TTCAN cycletime
+}stc_can_cst_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN Rx frame.
+ ******************************************************************************/
+typedef struct stc_can_rxframe
+{
+    union
+    {
+        uint32_t RBUF32_0;              ///< Ignore
+        uint32_t StdID;                 ///< Standard ID
+        uint32_t ExtID;                 ///< Extended ID
+    };
+    union
+    {
+        uint32_t        RBUF32_1;       ///< Ignore
+        stc_can_cst_t   Cst;            ///< @ref stc_can_cst_t
+    };
+    union
+    {
+        uint32_t RBUF32_2[2];           ///< Ignore
+        uint8_t  Data[8];               ///< CAN data
+    };
+}stc_can_rxframe_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN Rx frame.
+ ******************************************************************************/
+typedef struct stc_can_init_config
+{
+    en_can_rx_buf_all_t     enCanRxBufAll;      ///< @ref en_can_rx_buf_all_t
+    en_can_rx_buf_mode_en_t enCanRxBufMode;     ///< @ref en_can_rx_buf_mode_en_t
+    en_can_self_ack_en_t    enCanSAck;          ///< @ref en_can_self_ack_en_t
+    en_can_stb_mode_t       enCanSTBMode;       ///< @ref en_can_stb_mode_t
+    stc_can_bt_t            stcCanBt;           ///< @ref stc_can_bt_t
+    stc_can_warning_limit_t stcWarningLimit;    ///< @ref stc_can_warning_limit_t
+    stc_can_filter_t        *pstcFilter;        ///< @ref stc_can_filter_t Pointer to a stc_can_filter_t type array that \
+                                                ///<  contains the configuration informations of the acceptance filters.
+    uint8_t                 u8FilterCount;      ///< Number of filters that to to initialized.
+}stc_can_init_config_t;
+
+/**
+ *******************************************************************************
+ ** \brief                         CAN TTCAN
+ ******************************************************************************/
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN TTCAN pointer to a TB message slot
+ ******************************************************************************/
+typedef enum
+{
+    CanTTcanPTBSel      = 0x00u,        ///< PTB
+    CanTTcanSTB1Sel     = 0x01u,        ///< STB1
+    CanTTcanSTB2Sel     = 0x02u,        ///< STB2
+    CanTTcanSTB3Sel     = 0x03u,        ///< STB3
+    CanTTcanSTB4Sel     = 0x04u,        ///< STB4
+}en_can_ttcan_tbslot_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN TTCAN Timer prescaler
+ ******************************************************************************/
+typedef enum
+{
+    CanTTcanTprescDiv1  = 0x00u,        ///< Div1
+    CanTTcanTprescDiv2  = 0x01u,        ///< Div2
+    CanTTcanTprescDiv3  = 0x02u,        ///< Div3
+    CanTTcanTprescDiv4  = 0x03u,        ///< Div4
+}en_can_ttcan_Tpresc_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN TTCAN Trigger type
+ ******************************************************************************/
+typedef enum
+{
+    CanTTcanImmediate   = 0x00,         ///< Immediate trigger for immediate transmission
+    CanTTcanTime        = 0x01,         ///< Time trigger for receive trigger
+    CanTTcanSingle      = 0x02,         ///< Single shot transmit trigger for exclusive time windows
+    CanTTcanTransStart  = 0x03,         ///< Transmit start trigger for merged arbitrating time windows
+    CanTTcanTransStop   = 0x04,         ///< Transmit stop trigger for merged arbitrating time windows
+}en_can_ttcan_trigger_type_t;
+
+typedef enum
+{
+    CanTTcanWdtTriggerIrq = 0x80,       ///< Watch trigger interrupt
+    CanTTcanTimTriggerIrq = 0x10,       ///< Time trigger interrupt
+}en_can_ttcan_irq_type_t;
+
+
+typedef struct stc_can_ttcan_ref_msg
+{
+    uint8_t       u8IDE;                ///< Reference message IDE:1-Extended; 0-Standard;
+    union                               ///< Reference message ID
+    {
+        uint32_t RefStdID;              ///< Reference standard ID
+        uint32_t RefExtID;              ///< Reference Extended ID
+    };
+}stc_can_ttcan_ref_msg_t;
+
+typedef struct stc_can_ttcan_trigger_config
+{
+    en_can_ttcan_tbslot_t       enTbSlot;           ///< Transmit trigger TB slot pointer
+    en_can_ttcan_trigger_type_t enTrigType;         ///< Trigger type
+    en_can_ttcan_Tpresc_t       enTpresc;           ///< Timer prescaler
+    uint8_t                     u8Tew;              ///< Transmit enable window
+    uint16_t                    u16TrigTime;        ///< TTCAN trigger time
+    uint16_t                    u16WatchTrigTime;   ///< TTCAN watch trigger time register
+}stc_can_ttcan_trigger_config_t;
+
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+void CAN_Init(const stc_can_init_config_t *pstcCanInitCfg);
+void CAN_DeInit(void);
+void CAN_IrqCmd(en_can_irq_type_t enCanIrqType, en_functional_state_t enNewState);
+bool CAN_IrqFlgGet(en_can_irq_flag_type_t enCanIrqFlgType);
+void CAN_IrqFlgClr(en_can_irq_flag_type_t enCanIrqFlgType);
+void CAN_ModeConfig(en_can_mode_t enMode, en_functional_state_t enNewState);
+en_can_error_t CAN_ErrorStatusGet(void);
+bool CAN_StatusGet(en_can_status_t enCanStatus);
+
+void CAN_FilterConfig(const stc_can_filter_t pstcFilter[], uint8_t u8FilterCount);
+void CAN_FilterCmd(en_can_filter_sel_t enFilter, en_functional_state_t enNewState);
+
+void CAN_SetFrame(stc_can_txframe_t *pstcTxFrame);
+en_can_tx_buf_status_t CAN_TransmitCmd(en_can_tx_cmd_t enTxCmd);
+en_can_rx_buf_status_t CAN_Receive(stc_can_rxframe_t *pstcRxFrame);
+
+uint8_t CAN_ArbitrationLostCap(void);
+uint8_t CAN_RxErrorCntGet(void);
+uint8_t CAN_TxErrorCntGet(void);
+
+
+//<< void CAN_TTCAN_Enable(void);
+//<< void CAN_TTCAN_Disable(void);
+//<< void CAN_TTCAN_IrqCmd(void);
+//<< void CAN_TTCAN_ReferenceMsgSet(stc_can_ttcan_ref_msg_t *pstcRefMsg);
+//<< void CAN_TTCAN_TriggerConfig(stc_can_ttcan_trigger_config_t *pstcTriggerCfg);
+
+//@} // CanGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_CAN_ENABLE */
+
+#endif /* __HC32F460_CAN_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
+
@@ -0,0 +1,514 @@
+/*****************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_can.h
+ **
+ ** A detailed description is available at
+ ** @link CanGroup CAN description @endlink
+ **
+ **   - 2018-11-27  CDT First version for Device Driver Library of CAN
+ **
+ ******************************************************************************/
+#ifndef __HC32F460_CAN_H__
+#define __HC32F460_CAN_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_CAN_ENABLE == DDL_ON)
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup CanGroup Controller Area Network(CAN)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/**
+ *******************************************************************************
+ ** \brief  The Can error types.
+ ******************************************************************************/
+typedef enum
+{
+    NO_ERROR        = 0U,
+    BIT_ERROR       = 1U,
+    FORM_ERROR      = 2U,
+    STUFF_ERROR     = 3U,
+    ACK_ERROR       = 4U,
+    CRC_ERROR       = 5U,
+    UNKOWN_ERROR    = 6U,
+}en_can_error_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Can transmit buffer select.(TCMD)
+ ******************************************************************************/
+typedef enum
+{
+    CanPTBSel       = 0U,        ///< high-priority buffer
+    CanSTBSel       = 1U,        ///< secondary buffer
+}en_can_buffer_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Can warning limits.(AFWL)
+ ******************************************************************************/
+typedef struct stc_can_warning_limit
+{
+    uint8_t CanWarningLimitVal;         ///< Receive buffer almost full warning limit
+    uint8_t CanErrorWarningLimitVal;    ///< Programmable error warning limit
+}stc_can_warning_limit_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Acceptance Filters Frame Format Check.(ACF)
+ ******************************************************************************/
+typedef enum en_can_acf_format_en
+{
+    CanStdFrames        = 0x02u,   ///< Accepts only Standard frames
+    CanExtFrames        = 0x03u,   ///< Accepts only Extended frames
+    CanAllFrames        = 0x00u,   ///< Accepts both standard or extended frames
+}en_can_acf_format_en_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Acceptance Filters Enable.(ACFEN)
+ ******************************************************************************/
+typedef enum en_can_filter_sel
+{
+    CanFilterSel1        = 0u,   ///< The Acceptance Filter 1 Enable
+    CanFilterSel2        = 1u,   ///< The Acceptance Filter 2 Enable
+    CanFilterSel3        = 2u,   ///< The Acceptance Filter 3 Enable
+    CanFilterSel4        = 3u,   ///< The Acceptance Filter 4 Enable
+    CanFilterSel5        = 4u,   ///< The Acceptance Filter 5 Enable
+    CanFilterSel6        = 5u,   ///< The Acceptance Filter 6 Enable
+    CanFilterSel7        = 6u,   ///< The Acceptance Filter 7 Enable
+    CanFilterSel8        = 7u,   ///< The Acceptance Filter 8 Enable
+}en_can_filter_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The can interrupt enable.(IE)
+ ******************************************************************************/
+typedef enum
+{
+    //<<Can Rx or Tx Irq En
+    CanRxIrqEn              = 0x00000080,   ///< Receive interrupt enable
+    CanRxOverIrqEn          = 0x00000040,   ///< RB overrun interrupt enable
+    CanRxBufFullIrqEn       = 0x00000020,   ///< RB full interrupt enable
+    CanRxBufAlmostFullIrqEn = 0x00000010,   ///< RB almost full interrupt enable
+    CanTxPrimaryIrqEn       = 0x00000008,   ///< Transmission primary interrupt enable
+    CanTxSecondaryIrqEn     = 0x00000004,   ///< Transmission secondary enable
+    CanErrorIrqEn           = 0x00000002,   ///< Error interrupt enable
+
+    //<<Can Error Irq En
+    CanErrorPassiveIrqEn    = 0x00200000,   ///< Error passive mode active enable
+    CanArbiLostIrqEn        = 0x00080000,   ///< Arbitration lost interrupt enable
+    CanBusErrorIrqEn        = 0x00020000,   ///< Bus error interrupt enable
+
+}en_can_irq_type_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The can interrupt flag.(IF)
+ ******************************************************************************/
+typedef enum
+{
+    //<<Can Tx or Tx Irq Flg
+    CanTxBufFullIrqFlg          = 0x00000001,   ///<
+    CanRxIrqFlg                 = 0x00008000,   ///< Receive interrupt flag
+    CanRxOverIrqFlg             = 0x00004000,   ///< RB overrun interrupt flag
+    CanRxBufFullIrqFlg          = 0x00002000,   ///< RB full interrupt flag
+    CanRxBufAlmostFullIrqFlg    = 0x00001000,   ///< RB almost full interrupt flag
+    CanTxPrimaryIrqFlg          = 0x00000800,   ///< Transmission primary interrupt flag
+    CanTxSecondaryIrqFlg        = 0x00000400,   ///< Transmission secondary interrupt flag
+    CanErrorIrqFlg              = 0x00000200,   ///< Error interrupt flag
+    CanAbortIrqFlg              = 0x00000100,   ///< Abort interrupt flag
+
+    //<< Can Error Irq Flg
+    CanErrorWarningIrqFlg       = 0x00800000,   ///< Error warning limit reached flag
+    CanErrorPassivenodeIrqFlg   = 0x00400000,   ///< Error passive mode active flag
+    CanErrorPassiveIrqFlg       = 0x00100000,   ///< Error passive interrupt flag
+    CanArbiLostIrqFlg           = 0x00040000,   ///< Arbitration lost interrupt flag
+    CanBusErrorIrqFlg           = 0x00010000,   ///< Bus error interrupt flag
+}en_can_irq_flag_type_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The can mode.(TCMD)
+ ******************************************************************************/
+typedef enum
+{
+    CanExternalLoopBackMode  = 0x40,        ///< Loop back mode, external
+    CanInternalLoopBackMode  = 0x20,        ///< Loop back mode, internal
+    CanTxSignalPrimaryMode   = 0x10,        ///< Transmission primary single shot mode for PTB
+    CanTxSignalSecondaryMode = 0x08,        ///< Transmission secondary single shot mode for STB
+    CanListenOnlyMode        = 0xFF,        ///< Listen only mode
+}en_can_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The can status.(STAT)
+ ******************************************************************************/
+typedef enum
+{
+    CanRxActive = 0x04,        ///< Reception active
+    CanTxActive = 0x02,        ///< Transmission active
+    CanBusoff   = 0x01,        ///< Bus off
+}en_can_status_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Can Tx Command.(TCMD)
+ ******************************************************************************/
+typedef enum
+{
+    CanPTBTxCmd      = 0x10,        ///< Transmit primary for PTB
+    CanPTBTxAbortCmd = 0x08,        ///< Transmit primary abort for PTB
+    CanSTBTxOneCmd   = 0x04,        ///< Transmit secondary one frame for STB
+    CanSTBTxAllCmd   = 0x02,        ///< Transmit secondary all frames for STB
+    CanSTBTxAbortCmd = 0x01,        ///< Transmit secondary abort for STB
+}en_can_tx_cmd_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Can Transmit buffer secondary operation mode.(TCTRL)
+ ******************************************************************************/
+typedef enum
+{
+    CanSTBFifoMode    = 0,        ///< FIFO mode
+    CanSTBPrimaryMode = 1,        ///< Priority decision mode
+}en_can_stb_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Can Self-ACKnowledge.(RCTRL)
+ ******************************************************************************/
+typedef enum
+{
+    CanSelfAckEnable  = 1,        ///< Self-ACK when LBME=1
+    CanSelfAckDisable = 0,        ///< no self-ACK
+}en_can_self_ack_en_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Can Receive Buffer Overflow Mode.(RCTRL)
+ ******************************************************************************/
+typedef enum
+{
+    CanRxBufOverwritten = 0,        ///< The oldest message will be overwritten
+    CanRxBufNotStored   = 1,        ///< The new message will not be stored
+}en_can_rx_buf_mode_en_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Can Receive Buffer Stores All data frames.(RCTRL)
+ ******************************************************************************/
+typedef enum
+{
+    CanRxNormal = 0,        ///< Normal operation
+    CanRxAll    = 1,        ///< RB stores correct data frames as well as data frames with error
+}en_can_rx_buf_all_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Can Receive Buffer Status.(RSTAT)
+ ******************************************************************************/
+typedef enum
+{
+    CanRxBufEmpty          = 0,        ///< Empty
+    CanRxBufnotAlmostFull  = 1,        ///< >empty and <almost full
+    CanRxBufAlmostFull     = 2,        ///< >=almost full, but not full and no overflow
+    CanRxBufFull           = 3,        ///< full
+}en_can_rx_buf_status_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The Can Transmission secondary Status.(TSSTAT)
+ ******************************************************************************/
+typedef enum
+{
+    CanTxBufEmpty        = 0,       ///< TTEN=0 or  TTTBM=0: STB is empty
+                                    ///< TTEN=1 and TTTBM=1: PTB and STB are empty
+    CanTxBufnotHalfFull  = 1,       ///< TTEN=0 or  TTTBM=0: STB is less than or equal to half full
+                                    ///< TTEN=1 and TTTBM=1: PTB and STB are not empty and not full
+    CanTxBufHalfFull     = 2,       ///< TTEN=0 or  TTTBM=0: STB is more than half full
+                                    ///< TTEN=1 and TTTBM=1: None
+    CanTxBufFull         = 3,       ///< TTEN=0 or  TTTBM=0: STB is full
+                                    ///< TTEN=1 and TTTBM=1: PTB and STB are full
+}en_can_tx_buf_status_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN Acceptance Filter Code and Mask.
+ ******************************************************************************/
+typedef struct stc_can_filter
+{
+    uint32_t                u32CODE;        ///< Acceptance CODE
+    uint32_t                u32MASK;        ///< Acceptance MASK
+    en_can_filter_sel_t     enFilterSel;    ///< The Acceptance Filters Enable
+    en_can_acf_format_en_t  enAcfFormat;    ///< The Acceptance Filters Frame Format Check.
+}stc_can_filter_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN Bit Timing.
+ ******************************************************************************/
+typedef struct stc_can_bt
+{
+    uint8_t SEG_1;      ///< Bit timing segment 1(Tseg_1 = (SEG_1 + 2)*TQ)
+    uint8_t SEG_2;      ///< Bit timing segment 2(Tseg_2 = (SEG_2 + 1)*TQ)
+    uint8_t SJW;        ///< Synchronization jump width(Tsjw = (SJW + 1)*TQ)
+    uint8_t PRESC;      ///< The Prescaler divides the system clock to get the time quanta clock tq_clk(TQ)
+}stc_can_bt_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN Control Frame.
+ ******************************************************************************/
+typedef struct
+{
+    uint32_t DLC         : 4;       ///< Data length code
+    uint32_t RESERVED0   : 2;       ///< Ignore
+    uint32_t RTR         : 1;       ///< Remote transmission request
+    uint32_t IDE         : 1;       ///< IDentifier extension
+    uint32_t RESERVED1   : 24;      ///< Ignore
+}stc_can_txcontrol_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN Tx Frame.
+ ******************************************************************************/
+typedef struct stc_can_txframe
+{
+    union
+    {
+        uint32_t TBUF32_0;                  ///< Ignore
+        uint32_t StdID;                     ///< Standard ID
+        uint32_t ExtID;                     ///< Extended ID
+    };
+    union
+    {
+        uint32_t TBUF32_1;                  ///< Ignore
+        stc_can_txcontrol_t Control_f;      ///< CAN Tx Control
+    };
+    union
+    {
+        uint32_t TBUF32_2[2];               ///< Ignore
+        uint8_t  Data[8];                   ///< CAN data
+    };
+    en_can_buffer_sel_t     enBufferSel;    ///< CAN Tx buffer select
+}stc_can_txframe_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN Rx Ctrl.
+ ******************************************************************************/
+typedef struct
+{
+    uint8_t DLC          : 4;       ///< Data length code
+    uint8_t RESERVED0    : 2;       ///< Ignore
+    uint8_t RTR          : 1;       ///< Remote transmission request
+    uint8_t IDE          : 1;       ///< IDentifier extension
+}stc_can_rxcontrol_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN status.
+ ******************************************************************************/
+typedef struct
+{
+    uint8_t RESERVED0    : 4;       ///< Ignore
+    uint8_t TX           : 1;       ///< TX is set to 1 if the loop back mode is activated
+    uint8_t KOER         : 3;       ///< Kind of error
+}stc_can_status_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN control, status and cycletime.
+ ******************************************************************************/
+typedef struct
+{
+    stc_can_rxcontrol_t Control_f;      ///< @ref stc_can_rxcontrol_t
+    stc_can_status_t    Status_f;       ///< @ref stc_can_status_t
+    uint16_t            CycleTime;      ///< TTCAN cycletime
+}stc_can_cst_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN Rx frame.
+ ******************************************************************************/
+typedef struct stc_can_rxframe
+{
+    union
+    {
+        uint32_t RBUF32_0;              ///< Ignore
+        uint32_t StdID;                 ///< Standard ID
+        uint32_t ExtID;                 ///< Extended ID
+    };
+    union
+    {
+        uint32_t        RBUF32_1;       ///< Ignore
+        stc_can_cst_t   Cst;            ///< @ref stc_can_cst_t
+    };
+    union
+    {
+        uint32_t RBUF32_2[2];           ///< Ignore
+        uint8_t  Data[8];               ///< CAN data
+    };
+}stc_can_rxframe_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN Rx frame.
+ ******************************************************************************/
+typedef struct stc_can_init_config
+{
+    en_can_rx_buf_all_t     enCanRxBufAll;      ///< @ref en_can_rx_buf_all_t
+    en_can_rx_buf_mode_en_t enCanRxBufMode;     ///< @ref en_can_rx_buf_mode_en_t
+    en_can_self_ack_en_t    enCanSAck;          ///< @ref en_can_self_ack_en_t
+    en_can_stb_mode_t       enCanSTBMode;       ///< @ref en_can_stb_mode_t
+    stc_can_bt_t            stcCanBt;           ///< @ref stc_can_bt_t
+    stc_can_warning_limit_t stcWarningLimit;    ///< @ref stc_can_warning_limit_t
+}stc_can_init_config_t;
+
+/**
+ *******************************************************************************
+ ** \brief                         CAN TTCAN
+ ******************************************************************************/
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN TTCAN pointer to a TB message slot
+ ******************************************************************************/
+typedef enum
+{
+    CanTTcanPTBSel      = 0x00u,        ///< PTB
+    CanTTcanSTB1Sel     = 0x01u,        ///< STB1
+    CanTTcanSTB2Sel     = 0x02u,        ///< STB2
+    CanTTcanSTB3Sel     = 0x03u,        ///< STB3
+    CanTTcanSTB4Sel     = 0x04u,        ///< STB4
+}en_can_ttcan_tbslot_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN TTCAN Timer prescaler
+ ******************************************************************************/
+typedef enum
+{
+    CanTTcanTprescDiv1  = 0x00u,        ///< Div1
+    CanTTcanTprescDiv2  = 0x01u,        ///< Div2
+    CanTTcanTprescDiv3  = 0x02u,        ///< Div3
+    CanTTcanTprescDiv4  = 0x03u,        ///< Div4
+}en_can_ttcan_Tpresc_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of CAN TTCAN Trigger type
+ ******************************************************************************/
+typedef enum
+{
+    CanTTcanImmediate   = 0x00,         ///< Immediate trigger for immediate transmission
+    CanTTcanTime        = 0x01,         ///< Time trigger for receive trigger
+    CanTTcanSingle      = 0x02,         ///< Single shot transmit trigger for exclusive time windows
+    CanTTcanTransStart  = 0x03,         ///< Transmit start trigger for merged arbitrating time windows
+    CanTTcanTransStop   = 0x04,         ///< Transmit stop trigger for merged arbitrating time windows
+}en_can_ttcan_trigger_type_t;
+
+typedef enum
+{
+    CanTTcanWdtTriggerIrq = 0x80,       ///< Watch trigger interrupt
+    CanTTcanTimTriggerIrq = 0x10,       ///< Time trigger interrupt
+}en_can_ttcan_irq_type_t;
+
+
+typedef struct stc_can_ttcan_ref_msg
+{
+    uint8_t       u8IDE;                ///< Reference message IDE:1-Extended; 0-Standard;
+    union                               ///< Reference message ID
+    {
+        uint32_t RefStdID;              ///< Reference standard ID
+        uint32_t RefExtID;              ///< Reference Extended ID
+    };
+}stc_can_ttcan_ref_msg_t;
+
+typedef struct stc_can_ttcan_trigger_config
+{
+    en_can_ttcan_tbslot_t       enTbSlot;           ///< Transmit trigger TB slot pointer
+    en_can_ttcan_trigger_type_t enTrigType;         ///< Trigger type
+    en_can_ttcan_Tpresc_t       enTpresc;           ///< Timer prescaler
+    uint8_t                     u8Tew;              ///< Transmit enable window
+    uint16_t                    u16TrigTime;        ///< TTCAN trigger time
+    uint16_t                    u16WatchTrigTime;   ///< TTCAN watch trigger time register
+}stc_can_ttcan_trigger_config_t;
+
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+void CAN_Init(stc_can_init_config_t *pstcCanInitCfg);
+void CAN_DeInit(void);
+void CAN_IrqCmd(en_can_irq_type_t enCanIrqType, en_functional_state_t enNewState);
+bool CAN_IrqFlgGet(en_can_irq_flag_type_t enCanIrqFlgType);
+void CAN_IrqFlgClr(en_can_irq_flag_type_t enCanIrqFlgType);
+void CAN_ModeConfig(en_can_mode_t enMode, en_functional_state_t enNewState);
+en_can_error_t CAN_ErrorStatusGet(void);
+bool CAN_StatusGet(en_can_status_t enCanStatus);
+
+void CAN_FilterConfig(const stc_can_filter_t *pstcFilter, en_functional_state_t enNewState);
+void CAN_SetFrame(stc_can_txframe_t *pstcTxFrame);
+en_can_tx_buf_status_t CAN_TransmitCmd(en_can_tx_cmd_t enTxCmd);
+en_can_rx_buf_status_t CAN_Receive(stc_can_rxframe_t *pstcRxFrame);
+
+uint8_t CAN_ArbitrationLostCap(void);
+uint8_t CAN_RxErrorCntGet(void);
+uint8_t CAN_TxErrorCntGet(void);
+
+
+//<< void CAN_TTCAN_Enable(void);
+//<< void CAN_TTCAN_Disable(void);
+//<< void CAN_TTCAN_IrqCmd(void);
+//<< void CAN_TTCAN_ReferenceMsgSet(stc_can_ttcan_ref_msg_t *pstcRefMsg);
+//<< void CAN_TTCAN_TriggerConfig(stc_can_ttcan_trigger_config_t *pstcTriggerCfg);
+
+//@} // CanGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_CAN_ENABLE */
+
+#endif /* __HC32F460_CAN_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
+
@@ -0,0 +1,647 @@
+/*****************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_clk.h
+ **
+ ** A detailed description is available at
+ ** @link CmuGroup Clock description @endlink
+ **
+ **   - 2018-10-13  CDT  First version for Device Driver Library of CMU.
+ **
+ ******************************************************************************/
+#ifndef __HC32F460_CLK_H__
+#define __HC32F460_CLK_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_CLK_ENABLE == DDL_ON)
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup CmuGroup Clock Manage Unit(CMU)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/**
+ *******************************************************************************
+ ** \brief  The system clock source.
+ **
+ ******************************************************************************/
+ typedef enum en_clk_sys_source
+ {
+     ClkSysSrcHRC                   = 0u,   ///< The system clock source is HRC.
+     ClkSysSrcMRC                   = 1u,   ///< The system clock source is MRC.
+     ClkSysSrcLRC                   = 2u,   ///< The system clock source is LRC.
+     ClkSysSrcXTAL                  = 3u,   ///< The system clock source is XTAL.
+     ClkSysSrcXTAL32                = 4u,   ///< The system clock source is XTAL32.
+     CLKSysSrcMPLL                  = 5u,   ///< The system clock source is MPLL.
+ }en_clk_sys_source_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The pll clock source.
+ **
+ ******************************************************************************/
+ typedef enum en_clk_pll_source
+ {
+     ClkPllSrcXTAL                  = 0u,   ///< The pll clock source is XTAL.
+     ClkPllSrcHRC                   = 1u,   ///< The pll clock source is HRC.
+ }en_clk_pll_source_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The usb clock source.
+ **
+ ******************************************************************************/
+typedef enum en_clk_usb_source
+{
+    ClkUsbSrcSysDiv2                = 2u,   ///< The usb clock source is 1/2 system clock.
+    ClkUsbSrcSysDiv3                = 3u,   ///< The usb clock source is 1/3 system clock.
+    ClkUsbSrcSysDiv4                = 4u,   ///< The usb clock source is 1/4 system clock.
+    ClkUsbSrcMpllp                  = 8u,   ///< The usb clock source is MPLLP.
+    ClkUsbSrcMpllq                  = 9u,   ///< The usb clock source is MPLLQ.
+    ClkUsbSrcMpllr                  = 10u,  ///< The usb clock source is MPLLR.
+    ClkUsbSrcUpllp                  = 11u,  ///< The usb clock source is UPLLP.
+    ClkUsbSrcUpllq                  = 12u,  ///< The usb clock source is UPLLQ.
+    ClkUsbSrcUpllr                  = 13u,  ///< The usb clock source is UPLLR.
+}en_clk_usb_source_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The peripheral(adc/trng/I2S) clock source.
+ **
+ ******************************************************************************/
+typedef enum en_clk_peri_source
+{
+    ClkPeriSrcPclk                  = 0u,   ///< The peripheral(adc/trng/I2S) clock source is division from system clock.
+    ClkPeriSrcMpllp                 = 8u,   ///< The peripheral(adc/trng/I2S) clock source is MPLLP.
+    ClkPeriSrcMpllq                 = 9u,   ///< The peripheral(adc/trng/I2S) clock source is MPLLQ.
+    ClkPeriSrcMpllr                 = 10u,  ///< The peripheral(adc/trng/I2S) clock source is MPLLR.
+    ClkPeriSrcUpllp                 = 11u,  ///< The peripheral(adc/trng/I2S) clock source is UPLLP.
+    ClkPeriSrcUpllq                 = 12u,  ///< The peripheral(adc/trng/I2S) clock source is UPLLQ.
+    ClkPeriSrcUpllr                 = 13u,  ///< The peripheral(adc/trng/I2S) clock source is UPLLR.
+}en_clk_peri_source_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The clock output source.
+ **
+ ******************************************************************************/
+typedef enum en_clk_output_source
+{
+    ClkOutputSrcHrc                 = 0u,   ///< The clock output source is HRC
+    ClkOutputSrcMrc                 = 1u,   ///< The clock output source is MRC.
+    ClkOutputSrcLrc                 = 2u,   ///< The clock output source is LRC.
+    ClkOutputSrcXtal                = 3u,   ///< The clock output source is XTAL.
+    ClkOutputSrcXtal32              = 4u,   ///< The clock output source is XTAL32
+    ClkOutputSrcMpllp               = 6u,   ///< The clock output source is MPLLP.
+    ClkOutputSrcUpllp               = 7u,   ///< The clock output source is UPLLP.
+    ClkOutputSrcMpllq               = 8u,   ///< The clock output source is MPLLQ.
+    ClkOutputSrcUpllq               = 9u,   ///< The clock output source is UPLLQ.
+    ClkOutputSrcSysclk              = 11u,  ///< The clock output source is system clock.
+}en_clk_output_source_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The clock frequency source for measure or reference.
+ **
+ ******************************************************************************/
+typedef enum en_clk_fcm_source
+{
+    ClkFcmSrcXtal                   = 0u,   ///< The clock frequency measure or reference source is XTAL
+    ClkFcmSrcXtal32                 = 1u,   ///< The clock frequency measure or reference source is XTAL32.
+    ClkFcmSrcHrc                    = 2u,   ///< The clock frequency measure or reference source is HRC.
+    ClkFcmSrcLrc                    = 3u,   ///< The clock frequency measure or reference source is LRC.
+    ClkFcmSrcSwdtrc                 = 4u,   ///< The clock frequency measure or reference source is SWDTRC
+    ClkFcmSrcPclk1                  = 5u,   ///< The clock frequency measure or reference source is PCLK1.
+    ClkFcmSrcUpllp                  = 6u,   ///< The clock frequency measure or reference source is UPLLP.
+    ClkFcmSrcMrc                    = 7u,   ///< The clock frequency measure or reference source is MRC.
+    ClkFcmSrcMpllp                  = 8u,   ///< The clock frequency measure or reference source is MPLLP.
+    ClkFcmSrcRtcLrc                 = 9u,   ///< The clock frequency measure or reference source is RTCLRC.
+}en_clk_fcm_intref_source_t,en_clk_fcm_measure_source_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The clock flag status.
+ **
+ ******************************************************************************/
+typedef enum en_clk_flag
+{
+    ClkFlagHRCRdy                   = 0u,   ///< The clock flag is HRC ready.
+    ClkFlagXTALRdy                  = 1u,   ///< The clock flag is XTAL ready.
+    ClkFlagMPLLRdy                  = 2u,   ///< The clock flag is MPLL ready.
+    ClkFlagUPLLRdy                  = 3u,   ///< The clock flag is UPLL ready.
+    ClkFlagXTALStoppage             = 4u,   ///< The clock flag is XTAL stoppage.
+}en_clk_flag_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The clock frequency measure flag status.
+ **
+ ******************************************************************************/
+typedef enum en_clk_fcm_flag
+{
+    ClkFcmFlagErrf                  = 0u,   ///< The clock frequency flag is frequency abnormal.
+    ClkFcmFlagMendf                 = 1u,   ///< The clock frequency flag is end of measurement.
+    ClkFcmFlagOvf                   = 2u,   ///< The clock frequency flag is counter overflow.
+}en_clk_fcm_flag_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The source of xtal.
+ **
+ ******************************************************************************/
+typedef enum en_clk_xtal_mode
+{
+    ClkXtalModeOsc                  = 0u,   ///< Use external high speed osc as source.
+    ClkXtalModeExtClk               = 1u,   ///< Use external clk as source.
+}en_clk_xtal_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The drive capability of xtal.
+ **
+ ******************************************************************************/
+typedef enum en_clk_xtal_drv
+{
+    ClkXtalHighDrv                  = 0u,   ///< High drive capability.20MHz~24MHz.
+    ClkXtalMidDrv                   = 1u,   ///< Middle drive capability.16MHz~20MHz.
+    ClkXtalLowDrv                   = 2u,   ///< Low drive capability.8MHz~16MHz.
+    ClkXtalTinyDrv                  = 3u,   ///< Tiny drive capability.8MHz.
+}en_clk_xtal_drv_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The stable time of XTAL.
+ **
+ ** \note   It depends on SUPDRV bit.
+ ******************************************************************************/
+typedef enum en_clk_xtal_stb_cycle
+{
+    ClkXtalStbCycle35               = 1u,   ///< stable time is 35(36) cycle.
+    ClkXtalStbCycle67               = 2u,   ///< stable time is 67(68) cycle.
+    ClkXtalStbCycle131              = 3u,   ///< stable time is 131(132) cycle.
+    ClkXtalStbCycle259              = 4u,   ///< stable time is 259(260) cycle.
+    ClkXtalStbCycle547              = 5u,   ///< stable time is 547(548) cycle.
+    ClkXtalStbCycle1059             = 6u,   ///< stable time is 1059(1060) cycle.
+    ClkXtalStbCycle2147             = 7u,   ///< stable time is 2147(2148) cycle.
+    ClkXtalStbCycle4291             = 8u,   ///< stable time is 4291(4292) cycle.
+    ClkXtalStbCycle8163             = 9u,   ///< stable time is 8163(8164) cycle.
+}en_clk_xtal_stb_cycle_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The handle of xtal stoppage.
+ **
+ ******************************************************************************/
+typedef enum en_clk_xtal_stp_mode
+{
+    ClkXtalStpModeInt               = 0u,   ///< The handle of stoppage is interrupt.
+    ClkXtalStpModeReset             = 1u,   ///< The handle of stoppage is reset.
+}en_clk_xtal_stp_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The drive capability of xtal32.
+ **
+ ******************************************************************************/
+typedef enum en_clk_xtal32_drv
+{
+    ClkXtal32MidDrv                 = 0u,   ///< Middle drive capability.32.768KHz.
+    ClkXtal32HighDrv                = 1u,   ///< High drive capability.32.768KHz.
+}en_clk_xtal32_drv_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The filter mode of xtal32.
+ **
+ ******************************************************************************/
+typedef enum en_clk_xtal32_filter_mode
+{
+    ClkXtal32FilterModeFull         = 0u,   ///< Valid in run,stop,power down mode.
+    ClkXtal32FilterModePart         = 2u,   ///< Valid in run mode.
+    ClkXtal32FilterModeNone         = 3u,   ///< Invalid in run,stop,power down mode.
+}en_clk_xtal32_filter_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The division factor of system clock.
+ **
+ ******************************************************************************/
+typedef enum en_clk_sysclk_div_factor
+{
+    ClkSysclkDiv1                   = 0u,   ///< 1 division.
+    ClkSysclkDiv2                   = 1u,   ///< 2 division.
+    ClkSysclkDiv4                   = 2u,   ///< 4 division.
+    ClkSysclkDiv8                   = 3u,   ///< 8 division.
+    ClkSysclkDiv16                  = 4u,   ///< 16 division.
+    ClkSysclkDiv32                  = 5u,   ///< 32 division.
+    ClkSysclkDiv64                  = 6u,   ///< 64 division.
+}en_clk_sysclk_div_factor_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The division factor of system clock.It will be used for debug clock.
+ **
+ ******************************************************************************/
+typedef enum en_clk_tpiuclk_div_factor
+{
+    ClkTpiuclkDiv1                  = 0u,   ///< 1 division.
+    ClkTpiuclkDiv2                  = 1u,   ///< 2 division.
+    ClkTpiuclkDiv4                  = 2u,   ///< 4 division.
+}en_clk_tpiuclk_div_factor_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The division factor of clock output.
+ **
+ ******************************************************************************/
+typedef enum en_clk_output_div_factor
+{
+    ClkOutputDiv1                   = 0u,   ///< 1 division.
+    ClkOutputDiv2                   = 1u,   ///< 2 division.
+    ClkOutputDiv4                   = 2u,   ///< 4 division.
+    ClkOutputDiv8                   = 3u,   ///< 8 division.
+    ClkOutputDiv16                  = 4u,   ///< 16 division.
+    ClkOutputDiv32                  = 5u,   ///< 32 division.
+    ClkOutputDiv64                  = 6u,   ///< 64 division.
+    ClkOutputDiv128                 = 7u,   ///< 128 division.
+}en_clk_output_div_factor_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The division factor of fcm measure source.
+ **
+ ******************************************************************************/
+typedef enum en_clk_fcm_measure_div_factor
+{
+    ClkFcmMeaDiv1                   = 0u,   ///< 1 division.
+    ClkFcmMeaDiv4                   = 1u,   ///< 4 division.
+    ClkFcmMeaDiv8                   = 2u,   ///< 8 division.
+    ClkFcmMeaDiv32                  = 3u,   ///< 32 division.
+}en_clk_fcm_measure_div_factor_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The division factor of fcm reference source.
+ **
+ ******************************************************************************/
+typedef enum en_clk_fcm_intref_div_factor
+{
+    ClkFcmIntrefDiv32               = 0u,   ///< 32 division.
+    ClkFcmIntrefDiv128              = 1u,   ///< 128 division.
+    ClkFcmIntrefDiv1024             = 2u,   ///< 1024 division.
+    ClkFcmIntrefDiv8192             = 3u,   ///< 8192 division.
+}en_clk_fcm_intref_div_factor_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The edge of the fcm reference source.
+ **
+ ******************************************************************************/
+typedef enum en_clk_fcm_edge
+{
+    ClkFcmEdgeRising                = 0u,   ///< Rising edge.
+    ClkFcmEdgeFalling               = 1u,   ///< Falling edge.
+    ClkFcmEdgeBoth                  = 2u,   ///< Both edge.
+}en_clk_fcm_edge_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The filter clock of the fcm reference source.
+ **
+ ******************************************************************************/
+typedef enum en_clk_fcm_filter_clk
+{
+    ClkFcmFilterClkNone             = 0u,   ///< None filter.
+    ClkFcmFilterClkFcmSrc           = 1u,   ///< Use fcm measurement source as filter clock.
+    ClkFcmFilterClkFcmSrcDiv4       = 2u,   ///< Use 1/4 fcm measurement source as filter clock.
+    ClkFcmFilterClkFcmSrcDiv16      = 3u,   ///< Use 1/16 fcm measurement source as filter clock.
+}en_clk_fcm_filter_clk_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The fcm reference source.
+ **
+ ******************************************************************************/
+typedef enum en_clk_fcm_refer
+{
+    ClkFcmExtRef                    = 0u,   ///< Use external reference.
+    ClkFcmInterRef                  = 1u,   ///< Use internal reference.
+}en_clk_fcm_refer_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The handle of fcm abnormal.
+ **
+ ******************************************************************************/
+typedef enum en_clk_fcm_abnormal_handle
+{
+    ClkFcmHandleInterrupt           = 0u,   ///< The handle of fcm abnormal is interrupt.
+    ClkFcmHandleReset               = 1u,   ///< The handle of fcm abnormal is reset.
+}en_clk_fcm_abnormal_handle_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The channel of clock output.
+ **
+ ******************************************************************************/
+typedef enum en_clk_output_ch
+{
+    ClkOutputCh1                      = 1u,   ///< The output of clk is MCO_1.
+    ClkOutputCh2                      = 2u,   ///< The output of clk is MCO_2.
+}en_clk_output_ch_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of XTAL.
+ **
+ ** \note   Configures the XTAL if needed.
+ **
+ ******************************************************************************/
+typedef struct stc_clk_xtal_cfg
+{
+    en_functional_state_t           enFastStartup;  ///< Enable fast start up or not.
+    en_clk_xtal_mode_t              enMode;         ///< Select xtal mode.
+    en_clk_xtal_drv_t               enDrv;          ///< Select xtal drive capability.
+}stc_clk_xtal_cfg_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of XTAL stoppage.
+ **
+ ** \note   Configures the XTAL stoppage if needed.
+ **
+ ******************************************************************************/
+typedef struct stc_clk_xtal_stp_cfg
+{
+    en_functional_state_t           enDetect;       ///< Enable detect stoppage or not.
+    en_clk_xtal_stp_mode_t          enMode;         ///< Select the handle of xtal stoppage.
+    en_functional_state_t           enModeReset;    ///< Enable reset for handle the xtal stoppage.
+    en_functional_state_t           enModeInt;      ///< Enable interrupt for handle the xtal stoppage.
+}stc_clk_xtal_stp_cfg_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of XTAL32.
+ **
+ ** \note   Configures the XTAL32 if needed.
+ **
+ ******************************************************************************/
+typedef struct stc_clk_xtal32_cfg
+{
+    en_clk_xtal32_drv_t             enDrv;          ///< Select xtal32 drive capability.
+    en_clk_xtal32_filter_mode_t     enFilterMode;   ///< The filter mode of xtal32.
+}stc_clk_xtal32_cfg_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of PLL.
+ **
+ ** \note   Configures the PLL if needed.
+ **
+ ******************************************************************************/
+typedef struct stc_clk_pll_cfg
+{
+    uint32_t         PllpDiv;            ///< Pllp clk, division factor of VCO out.
+    uint32_t         PllqDiv;            ///< Pllq clk, division factor of VCO out.
+    uint32_t         PllrDiv;            ///< Pllr clk, division factor of VCO out.
+    uint32_t         plln;               ///< Multiplication factor of vco out, ensure between 240M~480M
+    uint32_t         pllmDiv;            ///< Division factor of VCO in, ensure between 1M~12M.
+}stc_clk_mpll_cfg_t, stc_clk_upll_cfg_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of system clock.
+ **
+ ** \note   Configures the system clock if needed.
+ **
+ ******************************************************************************/
+typedef struct stc_clk_sysclk_cfg
+{
+    en_clk_sysclk_div_factor_t      enHclkDiv;        ///< Division for hclk.
+    en_clk_sysclk_div_factor_t      enExclkDiv;       ///< Division for exclk.
+    en_clk_sysclk_div_factor_t      enPclk0Div;       ///< Division for pclk0.
+    en_clk_sysclk_div_factor_t      enPclk1Div;       ///< Division for pclk1.
+    en_clk_sysclk_div_factor_t      enPclk2Div;       ///< Division for pclk2.
+    en_clk_sysclk_div_factor_t      enPclk3Div;       ///< Division for pclk3.
+    en_clk_sysclk_div_factor_t      enPclk4Div;       ///< Division for pclk4.
+}stc_clk_sysclk_cfg_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of clock output.
+ **
+ ** \note   Configures the clock output if needed.
+ **
+ ******************************************************************************/
+typedef struct stc_clk_output_cfg
+{
+    en_clk_output_source_t          enOutputSrc;    ///< The clock output source.
+    en_clk_output_div_factor_t      enOutputDiv;    ///< The division factor of clock output source.
+}stc_clk_output_cfg_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of fcm window.
+ **
+ ** \note   Configures the fcm window if needed.
+ **
+ ******************************************************************************/
+typedef struct stc_clk_fcm_window_cfg
+{
+    uint16_t                        windowLower;    ///< The lower value of the window.
+    uint16_t                        windowUpper;    ///< The upper value of the window.
+}stc_clk_fcm_window_cfg_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of fcm measurement.
+ **
+ ** \note   Configures the fcm measurement if needed.
+ **
+ ******************************************************************************/
+typedef struct stc_clk_fcm_measure_cfg
+{
+    en_clk_fcm_measure_source_t     enSrc;          ///< The measurement source.
+    en_clk_fcm_measure_div_factor_t enSrcDiv;       ///< The division factor of measurement source.
+}stc_clk_fcm_measure_cfg_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of fcm reference.
+ **
+ ** \note   Configures the fcm reference if needed.
+ **
+ ******************************************************************************/
+typedef struct stc_clk_fcm_reference_cfg
+{
+    en_functional_state_t           enExtRef;       ///< Enable external reference or not.
+    en_clk_fcm_edge_t               enEdge;         ///< The edge of internal reference.
+    en_clk_fcm_filter_clk_t         enFilterClk;    ///< The filter clock of internal reference.
+    en_clk_fcm_refer_t              enRefSel;       ///< Select reference.
+    en_clk_fcm_intref_source_t      enIntRefSrc;    ///< Select internal reference.
+    en_clk_fcm_intref_div_factor_t  enIntRefDiv;    ///< The division factor of internal reference.
+}stc_clk_fcm_reference_cfg_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of fcm interrupt.
+ **
+ ** \note   Configures the fcm interrupt if needed.
+ **
+ ******************************************************************************/
+typedef struct stc_clk_fcm_interrupt_cfg
+{
+    en_clk_fcm_abnormal_handle_t    enHandleSel;        ///< Use interrupt or reset.
+    en_functional_state_t           enHandleReset;      ///< Enable reset or not.
+    en_functional_state_t           enHandleInterrupt;  ///< Enable interrupt or not.
+    en_functional_state_t           enOvfInterrupt;     ///< Enable overflow interrupt or not.
+    en_functional_state_t           enEndInterrupt;     ///< Enable measurement end interrupt or not.
+}stc_clk_fcm_interrupt_cfg_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Configuration structure of fcm.
+ **
+ ** \note   Configures the fcm if needed.
+ **
+ ******************************************************************************/
+typedef struct stc_clk_fcm_cfg
+{
+    stc_clk_fcm_window_cfg_t        *pstcFcmWindowCfg;  ///< Window configuration struct.
+    stc_clk_fcm_measure_cfg_t       *pstcFcmMeaCfg;     ///< Measurement configuration struct.
+    stc_clk_fcm_reference_cfg_t     *pstcFcmRefCfg;     ///< Reference configuration struct.
+    stc_clk_fcm_interrupt_cfg_t     *pstcFcmIntCfg;     ///< Interrupt configuration struct.
+}stc_clk_fcm_cfg_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Clock frequency structure.
+ **
+ ******************************************************************************/
+typedef struct stc_clk_freq
+{
+    uint32_t            sysclkFreq;         ///< System clock frequency.
+    uint32_t            hclkFreq;           ///< Hclk frequency.
+    uint32_t            exckFreq;           ///< Exclk frequency.
+    uint32_t            pclk0Freq;          ///< Pclk0 frequency.
+    uint32_t            pclk1Freq;          ///< Pclk1 frequency.
+    uint32_t            pclk2Freq;          ///< Pclk2 frequency.
+    uint32_t            pclk3Freq;          ///< Pclk3 frequency.
+    uint32_t            pclk4Freq;          ///< Pclk4 frequency.
+}stc_clk_freq_t;
+
+/**
+ *******************************************************************************
+ ** \brief  PLL Clock frequency structure.
+ **
+ ******************************************************************************/
+typedef struct stc_pll_clk_freq
+{
+    uint32_t            mpllp;              ///< mpllp clock frequency.
+    uint32_t            mpllq;              ///< mpllq clock frequency.
+    uint32_t            mpllr;              ///< mpllr clock frequency.
+    uint32_t            upllp;              ///< upllp clock frequency.
+    uint32_t            upllq;              ///< upllq clock frequency.
+    uint32_t            upllr;              ///< upllr clock frequency.
+}stc_pll_clk_freq_t;
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+void CLK_XtalConfig(const stc_clk_xtal_cfg_t *pstcXtalCfg);
+void CLK_XtalStbConfig(const en_clk_xtal_stb_cycle_t enXtalStb);
+void CLK_XtalStpConfig(const stc_clk_xtal_stp_cfg_t *pstcXtalStpCfg);
+en_result_t CLK_XtalCmd(en_functional_state_t enNewState);
+
+void CLK_Xtal32Config(const stc_clk_xtal32_cfg_t *pstcXtal32Cfg);
+en_result_t CLK_Xtal32Cmd(en_functional_state_t enNewState);
+
+void CLK_HrcTrim(int8_t trimValue);
+en_result_t CLK_HrcCmd(en_functional_state_t enNewState);
+
+void CLK_MrcTrim(int8_t trimValue);
+en_result_t CLK_MrcCmd(en_functional_state_t enNewState);
+
+void CLK_LrcTrim(int8_t trimValue);
+en_result_t CLK_LrcCmd(en_functional_state_t enNewState);
+
+void CLK_SetPllSource(en_clk_pll_source_t enPllSrc);
+void CLK_MpllConfig(const stc_clk_mpll_cfg_t *pstcMpllCfg);
+en_result_t CLK_MpllCmd(en_functional_state_t enNewState);
+
+void CLK_UpllConfig(const stc_clk_upll_cfg_t *pstcUpllCfg);
+en_result_t CLK_UpllCmd(en_functional_state_t enNewState);
+
+void CLK_SetSysClkSource(en_clk_sys_source_t enTargetSysSrc);
+en_clk_sys_source_t CLK_GetSysClkSource(void);
+
+void CLK_SysClkConfig(const stc_clk_sysclk_cfg_t *pstcSysclkCfg);
+void CLK_GetClockFreq(stc_clk_freq_t *pstcClkFreq);
+void CLK_GetPllClockFreq(stc_pll_clk_freq_t *pstcPllClkFreq);
+
+void CLK_SetUsbClkSource(en_clk_usb_source_t enTargetUsbSrc);
+void CLK_SetPeriClkSource(en_clk_peri_source_t enTargetPeriSrc);
+void CLK_SetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg, en_clk_peri_source_t enTargetPeriSrc);
+en_clk_peri_source_t CLK_GetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg);
+
+void CLK_TpiuClkConfig(const en_clk_tpiuclk_div_factor_t enTpiuDiv);
+void CLK_TpiuClkCmd(en_functional_state_t enNewState);
+
+void CLK_OutputClkConfig(en_clk_output_ch_t enCh, const stc_clk_output_cfg_t *pstcOutputCfg);
+void CLK_OutputClkCmd(en_clk_output_ch_t enCh, en_functional_state_t enNewState);
+en_flag_status_t CLK_GetFlagStatus(en_clk_flag_t enClkFlag);
+
+void CLK_FcmConfig(const stc_clk_fcm_cfg_t *pstcClkFcmCfg);
+void CLK_FcmCmd(en_functional_state_t enNewState);
+
+uint16_t CLK_GetFcmCounter(void);
+en_flag_status_t CLK_GetFcmFlag(en_clk_fcm_flag_t enFcmFlag);
+void CLK_ClearFcmFlag(en_clk_fcm_flag_t enFcmFlag);
+
+void CLK_ClearXtalStdFlag(void);
+
+//@} // CmuGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_CLK_ENABLE */
+
+#endif /* __HC32F460_CLK_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,279 @@
+/*******************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_cmp.h
+ **
+ ** A detailed description is available at
+ ** @link CmpGroup CMP @endlink
+ **
+ **   - 2018-10-22  CDT  First version for Device Driver Library of CMP.
+ **
+ ******************************************************************************/
+#ifndef __HC32F460_CMP_H__
+#define __HC32F460_CMP_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_CMP_ENABLE == DDL_ON)
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup CmpGroup Comparator(CMP)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ *******************************************************************************
+ ** \brief CMP function enumeration
+ ******************************************************************************/
+typedef enum en_cmp_func
+{
+    CmpVcoutOutput = (1u << 12),                ///< CMP vcout output enable function
+    CmpOutpuInv    = (1u << 13),                ///< CMP output invert enable function
+    CmpOutput      = (1u << 14),                ///< CMP output enable function
+} en_cmp_func_t;
+
+/**
+ *******************************************************************************
+ ** \brief CMP edge selection enumeration
+ ******************************************************************************/
+typedef enum en_cmp_edge_sel
+{
+    CmpNoneEdge     = 0u,                       ///< None edge detection
+    CmpRisingEdge   = 1u,                       ///< Rising edge detection
+    CmpFaillingEdge = 2u,                       ///< Falling edge detection
+    CmpBothEdge     = 3u,                       ///< Falling or Rising edge detection
+} en_cmp_edge_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief CMP filter sample clock division enumeration
+ ******************************************************************************/
+typedef enum en_cmp_fltclk_div
+{
+    CmpNoneFlt       = 0u,                      ///< Unuse filter
+    CmpFltPclk3Div1  = 1u,                      ///< PCLK3/1
+    CmpFltPclk3Div2  = 2u,                      ///< PCLK3/2
+    CmpFltPclk3Div4  = 3u,                      ///< PCLK3/4
+    CmpFltPclk3Div8  = 4u,                      ///< PCLK3/8
+    CmpFltPclk3Div16 = 5u,                      ///< PCLK3/16
+    CmpFltPclk3Div32 = 6u,                      ///< PCLK3/32
+    CmpFltPclk3Div64 = 7u,                      ///< PCLK3/64
+} en_cmp_fltclk_div_t;
+
+/**
+ *******************************************************************************
+ ** \brief CMP INP4 input enumeration
+ ******************************************************************************/
+typedef enum en_cmp_inp4_sel
+{
+    CmpInp4None      = 0u,                      ///< None input
+    CmpInp4PGAO      = 1u,                      ///< PGAO output
+    CmpInp4PGAO_BP   = 2u,                      ///< PGAO_BP output
+    CmpInp4CMP1_INP4 = 4u,                      ///< CMP1_INP4
+} en_cmp_inp4_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief CMP INP input enumeration
+ ******************************************************************************/
+typedef enum en_cmp_inp_sel
+{
+    CmpInpNone             = 0u,                ///< None input
+    CmpInp1                = 1u,                ///< INP1 input
+    CmpInp2                = 2u,                ///< INP2 input
+    CmpInp1_Inp2           = 3u,                ///< INP1 INP2 input
+    CmpInp3                = 4u,                ///< INP3 input
+    CmpInp1_Inp3           = 5u,                ///< INP1 INP3 input
+    CmpInp2_Inp3           = 6u,                ///< INP2 INP3 input
+    CmpInp1_Inp2_Inp3      = 7u,                ///< INP1 INP2 INP3 input
+    CmpInp4                = 8u,                ///< INP4 input
+    CmpInp1_Inp4           = 9u,                ///< INP1 INP4 input
+    CmpInp2_Inp4           = 10u,               ///< INP2 INP4 input
+    CmpInp1_Inp2_Inp4      = 11u,               ///< INP1 INP2 INP4 input
+    CmpInp3_Inp4           = 12u,               ///< INP3 INP4 input
+    CmpInp1_Inp3_Inp4      = 13u,               ///< INP1 INP3 INP4 input
+    CmpInp2_Inp3_Inp4      = 14u,               ///< INP2 INP3 INP4 input
+    CmpInp1_Inp2_Inp3_Inp4 = 15u,               ///< INP1 INP2 INP3 INP4 input
+} en_cmp_inp_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief CMP INM input enumeration
+ ******************************************************************************/
+typedef enum en_cmp_inm_sel
+{
+    CmpInmNone = 0u,                            ///< None input
+    CmpInm1    = 1u,                            ///< INM1 input
+    CmpInm2    = 2u,                            ///< INM2 input
+    CmpInm3    = 4u,                            ///< INM3 input
+    CmpInm4    = 8u,                            ///< INM4 input
+} en_cmp_inm_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief CMP INP State enumeration (read only)
+ ******************************************************************************/
+typedef enum en_cmp_inp_state
+{
+    CmpInpNoneState = 0u,                       ///< none input state
+    CmpInp1State    = 1u,                       ///< INP1 input state
+    CmpInp2State    = 2u,                       ///< INP2 input state
+    CmpInp3State    = 4u,                       ///< INP3 input state
+    CmpInp4State    = 8u,                       ///< INP4 input state
+} en_cmp_inp_state_t;
+
+/**
+ *******************************************************************************
+ ** \brief CMP Output State enumeration (read only)
+ ******************************************************************************/
+typedef enum en_cmp_output_state
+{
+    CmpOutputLow  = 0u,                         ///< Compare output Low "0"
+    CmpOutputHigh = 1u,                         ///< Compare output High "1"
+} en_cmp_output_state_t;
+
+/**
+ *******************************************************************************
+ ** \brief CMP input selection
+ ******************************************************************************/
+typedef struct stc_cmp_input_sel
+{
+    en_cmp_inm_sel_t  enInmSel;                 ///< CMP INM sel
+
+    en_cmp_inp_sel_t  enInpSel;                 ///< CMP INP sel
+
+    en_cmp_inp4_sel_t enInp4Sel;                ///< CMP INP4 sel
+} stc_cmp_input_sel_t;
+
+/**
+ ******************************************************************************
+ ** \brief DAC channel
+ ******************************************************************************/
+typedef enum en_cmp_dac_ch
+{
+    CmpDac1 = 0u,                               ///< DAC1
+    CmpDac2 = 1u,                               ///< DAC2
+} en_cmp_dac_ch_t;
+
+/**
+ ******************************************************************************
+ ** \brief ADC internal reference voltage path
+ ******************************************************************************/
+typedef enum en_cmp_adc_int_ref_volt_path
+{
+    CmpAdcRefVoltPathDac1 = (1u << 0u),         ///< ADC internal reference voltage path: DAC1
+    CmpAdcRefVoltPathDac2 = (1u << 1u),         ///< ADC internal reference voltage path: DAC2
+    CmpAdcRefVoltPathVref = (1u << 4u),         ///< ADC internal reference voltage path: VREF
+} en_cmp_adc_int_ref_volt_path_t;
+
+/**
+ *******************************************************************************
+ ** \brief CMP initialization structure definition
+ ******************************************************************************/
+typedef struct stc_cmp_init
+{
+    en_cmp_edge_sel_t     enEdgeSel;            ///< CMP edge sel
+
+    en_cmp_fltclk_div_t   enFltClkDiv;          ///< CMP FLTclock division
+
+    en_functional_state_t enCmpOutputEn;        ///< CMP Output enable
+
+    en_functional_state_t enCmpVcoutOutputEn;   ///< CMP output result enable
+
+    en_functional_state_t enCmpInvEn;           ///< CMP INV sel for output
+
+    en_functional_state_t enCmpIntEN;           ///< CMP interrupt enable
+} stc_cmp_init_t;
+
+/**
+ *******************************************************************************
+ ** \brief CMP DAC initialization structure definition
+ ******************************************************************************/
+typedef struct stc_cmp_dac_init
+{
+    uint8_t               u8DacData;            ///< CMP DAC Data register value
+
+    en_functional_state_t enCmpDacEN;           ///< CMP DAC enable
+} stc_cmp_dac_init_t;
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+  Global function prototypes (definition in C source)
+ ******************************************************************************/
+en_result_t CMP_Init(M4_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcInitCfg);
+en_result_t CMP_DeInit(M4_CMP_TypeDef *CMPx);
+en_result_t CMP_Cmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd);
+en_result_t CMP_IrqCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd);
+en_result_t CMP_SetScanTime(M4_CMP_TypeDef *CMPx,
+                                uint8_t u8ScanStable,
+                                uint8_t u8ScanPeriod);
+en_result_t CMP_FuncCmd(M4_CMP_TypeDef *CMPx,
+                    en_cmp_func_t enFunc,
+                    en_functional_state_t enCmd);
+en_result_t CMP_StartScan(M4_CMP_TypeDef *CMPx);
+en_result_t CMP_StopScan(M4_CMP_TypeDef *CMPx);
+en_result_t CMP_SetFilterClkDiv(M4_CMP_TypeDef *CMPx,
+                                        en_cmp_fltclk_div_t enFltClkDiv);
+en_cmp_fltclk_div_t CMP_GetFilterClkDiv(M4_CMP_TypeDef *CMPx);
+en_result_t CMP_SetEdgeSel(M4_CMP_TypeDef *CMPx,
+                                en_cmp_edge_sel_t enEdgeSel);
+en_cmp_edge_sel_t CMP_GetEdgeSel(M4_CMP_TypeDef *CMPx);
+en_result_t CMP_InputSel(M4_CMP_TypeDef *CMPx,
+                            const stc_cmp_input_sel_t *pstcInputSel);
+en_result_t CMP_SetInp(M4_CMP_TypeDef *CMPx, en_cmp_inp_sel_t enInputSel);
+en_cmp_inp_sel_t CMP_GetInp(M4_CMP_TypeDef *CMPx);
+en_result_t CMP_SetInm(M4_CMP_TypeDef *CMPx, en_cmp_inm_sel_t enInputSel);
+en_cmp_inm_sel_t CMP_GetInm(M4_CMP_TypeDef *CMPx);
+en_result_t CMP_SetInp4(M4_CMP_TypeDef *CMPx,en_cmp_inp4_sel_t enInputSel);
+en_cmp_inp4_sel_t CMP_GetInp4(M4_CMP_TypeDef *CMPx);
+en_cmp_output_state_t CMP_GetOutputState(M4_CMP_TypeDef *CMPx);
+en_cmp_inp_state_t CMP_GetInpState(M4_CMP_TypeDef *CMPx);
+en_result_t CMP_DAC_Init(en_cmp_dac_ch_t enCh,
+                            const stc_cmp_dac_init_t *pstcInitCfg);
+en_result_t CMP_DAC_DeInit(en_cmp_dac_ch_t enCh);
+en_result_t CMP_DAC_Cmd(en_cmp_dac_ch_t enCh, en_functional_state_t enCmd);
+en_result_t CMP_DAC_SetData(en_cmp_dac_ch_t enCh, uint8_t u8DacData);
+uint8_t CMP_DAC_GetData(en_cmp_dac_ch_t enCh);
+en_result_t CMP_ADC_SetRefVoltPath(en_cmp_adc_int_ref_volt_path_t enRefVoltPath);
+
+//@} // CmpGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_CMP_ENABLE */
+
+#endif /* __HC32F460_CMP_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,118 @@
+/*******************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_crc.h
+ **
+ ** A detailed description is available at
+ ** @link CrcGroup Crc description @endlink
+ **
+ **   - 2019-03-07  CDT First version for Device Driver Library of Crc.
+ **
+ ******************************************************************************/
+#ifndef __HC32F460_CRC_H__
+#define __HC32F460_CRC_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_CRC_ENABLE == DDL_ON)
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup CrcGroup Cyclic Redundancy Check(CRC)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/* Bits definitions of CRC control register(CRC_CR). */
+/*
+ * Definitions of CRC protocol.
+ * NOTE: CRC16 polynomial is X16 + X12 + X5 + 1
+ *       CRC32 polynomial is X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + \
+ *                           X8 + X7 + X5 + X4 + X2 + X + 1
+ */
+#define CRC_SEL_16B         ((uint32_t)0x0)
+#define CRC_SEL_32B         ((uint32_t)(0x1ul << 1u))
+
+/*
+ * Identifies the transpose configuration of the source data.
+ * If this function is enabled, the source data's bits in bytes are transposed.
+ * e.g. There's a source data 0x1234 which will be calculated checksum and this
+ * function is enabled, the final data be calculated is 0x482C.
+ * 0x12: bit0->bit7, bit1->bit6, ..., bit7->bit0, the data byte changed to 0x48.
+ * 0x48: bit0->bit7, bit1->bit6, ..., bit7->bit0, the data byte changed to 0x2C.
+ * The same to 32 bit data while using CRC32.
+ */
+#define CRC_REFIN_DISABLE   ((uint32_t)0x0)
+#define CRC_REFIN_ENABLE    ((uint32_t)(0x1ul << 2u))
+
+/*
+ * Identifies the transpose configuration of the checksum.
+ * If this function is enabled, bits of the checksum will be transposed.
+ * e.g. There is a CRC16 checksum is 0x5678 before this function enabled, then
+ * this function is enabled, the checksum will be 0x1E6A.
+ * 0x5678: bit0->bit15, bit1->bit14, ..., bit15->bit0, the final data is 0x1E6A.
+ * The same to CRC32 checksum while using CRC32.
+ */
+#define CRC_REFOUT_DISABLE  ((uint32_t)0x0)
+#define CRC_REFOUT_ENABLE   ((uint32_t)(0x1ul << 3u))
+
+/*
+ * XORs the CRC checksum with 0xFFFF(CRC16) or 0xFFFFFFFF(CRC32).
+ * e.g. There is a CRC16 checksum is 0x5678 before this function enabled.
+ * If this function enabled, the checksum will be 0xA987.
+ * The same to CRC32 checksum while using CRC32.
+ */
+#define CRC_XOROUT_DISABLE  ((uint32_t)0x0)
+#define CRC_XOROUT_ENABLE   ((uint32_t)(0x1ul << 4u))
+
+#define CRC_CONFIG_MASK     ((uint32_t)(0x1Eu))
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+void CRC_Init(uint32_t u32Config);
+uint16_t CRC_Calculate16B(uint16_t u16InitVal, const uint16_t *pu16Data, uint32_t u32Length);
+uint32_t CRC_Calculate32B(uint32_t u32InitVal, const uint32_t *pu32Data, uint32_t u32Length);
+bool CRC_Check16B(uint16_t u16InitVal, uint16_t u16CheckSum, const uint16_t *pu16Data, uint32_t u32Length);
+bool CRC_Check32B(uint32_t u32InitVal, uint32_t u32CheckSum, const uint32_t *pu32Data, uint32_t u32Length);
+
+//@} // CrcGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_CRC_ENABLE */
+
+#endif /* __HC32F460_CRC_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,216 @@
+/*******************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_dcu.h
+ **
+ ** A detailed description is available at
+ ** @link DcuGroup DCU description @endlink
+ **
+ **   - 2018-10-15 CDT First version for Device Driver Library of DCU.
+ **
+ ******************************************************************************/
+#ifndef __HC32F460_DCU_H__
+#define __HC32F460_DCU_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_DCU_ENABLE == DDL_ON)
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup DcuGroup Data Computing Unit(DCU)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ *******************************************************************************
+ ** \brief DCU register data enumeration
+ **
+ ******************************************************************************/
+typedef enum en_dcu_data_register
+{
+    DcuRegisterData0 = 0u,                  ///< DCU DATA0
+    DcuRegisterData1 = 1u,                  ///< DCU DATA1
+    DcuRegisterData2 = 2u,                  ///< DCU DATA2
+} en_dcu_data_register_t;
+
+/**
+ *******************************************************************************
+ ** \brief DCU operation enumeration
+ **
+ ******************************************************************************/
+typedef enum en_dcu_operation_mode
+{
+    DcuInvalid     = 0u,                    ///< DCU Invalid
+    DcuOpAdd       = 1u,                    ///< DCU operation: Add
+    DcuOpSub       = 2u,                    ///< DCU operation: Sub
+    DcuHwTrigOpAdd = 3u,                    ///< DCU operation: Hardware trigger Add
+    DcuHwTrigOpSub = 4u,                    ///< DCU operation: Hardware trigger Sub
+    DcuOpCompare   = 5u,                    ///< DCU operation: Compare
+} en_dcu_operation_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief DCU data size enumeration
+ **
+ ******************************************************************************/
+typedef enum en_dcu_data_size
+{
+    DcuDataBit8  = 0u,                      ///< DCU data size: 8 bit
+    DcuDataBit16 = 1u,                      ///< DCU data size: 16 bit
+    DcuDataBit32 = 2u,                      ///< DCU data size: 32 bit
+} en_dcu_data_size_t;
+
+/**
+ *******************************************************************************
+ ** \brief DCU compare operation trigger mode enumeration
+ **
+ ******************************************************************************/
+typedef enum en_dcu_cmp_trigger_mode
+{
+    DcuCmpTrigbyData0   = 0u,               ///< DCU compare triggered by DATA0
+    DcuCmpTrigbyData012 = 1u,               ///< DCU compare triggered by DATA0 or DATA1 or DATA2
+} en_dcu_cmp_trigger_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief DCU interrupt selection enumeration
+ **
+ ******************************************************************************/
+typedef enum en_dcu_int_sel
+{
+    DcuIntOp  = (1ul << 0),                 ///< DCU overflow or underflow interrupt
+    DcuIntLs2 = (1ul << 1),                 ///< DCU DATA0 < DATA2 interrupt
+    DcuIntEq2 = (1ul << 2),                 ///< DCU DATA0 = DATA2 interrupt
+    DcuIntGt2 = (1ul << 3),                 ///< DCU DATA0 > DATA2 interrupt
+    DcuIntLs1 = (1ul << 4),                 ///< DCU DATA0 < DATA1 interrupt
+    DcuIntEq1 = (1ul << 5),                 ///< DCU DATA0 = DATA1 interrupt
+    DcuIntGt1 = (1ul << 6),                 ///< DCU DATA0 > DATA1 interrupt
+} en_dcu_int_sel_t, en_dcu_flag_t;
+
+/**
+ *******************************************************************************
+ ** \brief DCU window interrupt mode enumeration
+ **
+ ******************************************************************************/
+typedef enum en_dcu_int_win_mode
+{
+    DcuIntInvalid       = 0u,               ///< DCU don't occur interrupt
+    DcuWinIntInvalid    = 1u,               ///< DCU window interrupt is invalid.
+    DcuInsideWinCmpInt  = 2u,               ///< DCU occur interrupt when DATA2 ¡Ü DATA0 ¡Ü DATA2
+    DcuOutsideWinCmpInt = 3u,               ///< DCU occur interrupt when DATA0 > DATA1 or DATA0 < DATA2
+} en_dcu_int_win_mode_t;
+
+/* DCU common trigger source select */
+typedef enum en_dcu_com_trigger
+{
+    DcuComTrigger_1   = 1u,                 ///< Select common trigger 1.
+    DcuComTrigger_2   = 2u,                 ///< Select common trigger 2.
+    DcuComTrigger_1_2 = 3u,                 ///< Select common trigger 1 and 2.
+} en_dcu_com_trigger_t;
+
+/**
+ *******************************************************************************
+ ** \brief DCU initialization configuration
+ **
+ ******************************************************************************/
+typedef struct stc_dcu_init
+{
+    uint32_t                  u32IntSel;        ///< Specifies interrupt selection and This parameter can be a value of @ref en_dcu_int_sel_t
+
+    en_functional_state_t     enIntCmd;         ///< Select DCU interrupt function. Enable:Enable DCU interrupt function; Disable:Disable DCU interrupt function
+
+    en_dcu_int_win_mode_t     enIntWinMode;     ///< Specifies interrupt window mode and This parameter can be a value of @ref en_dcu_int_win_mode_t
+
+    en_dcu_data_size_t        enDataSize;       ///< Specifies DCU data size and This parameter can be a value of @ref en_dcu_data_size_t
+
+    en_dcu_operation_mode_t   enOperation;      ///< Specifies DCU operation and This parameter can be a value of @ref en_dcu_operation_mode_t
+
+    en_dcu_cmp_trigger_mode_t enCmpTriggerMode; ///< Specifies DCU compare operation trigger mode size and This parameter can be a value of @ref en_dcu_cmp_trigger_mode_t
+
+} stc_dcu_init_t;
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+en_result_t DCU_Init(M4_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcInitCfg);
+en_result_t DCU_DeInit(M4_DCU_TypeDef *DCUx);
+en_result_t DCU_SetOperationMode(M4_DCU_TypeDef *DCUx,
+                                en_dcu_operation_mode_t enMode);
+en_dcu_operation_mode_t DCU_GetOperationMode(M4_DCU_TypeDef *DCUx);
+en_result_t DCU_SetDataSize(M4_DCU_TypeDef *DCUx, en_dcu_data_size_t enSize);
+en_dcu_data_size_t DCU_GetDataSize(M4_DCU_TypeDef *DCUx);
+en_result_t DCU_SetIntWinMode(M4_DCU_TypeDef *DCUx,
+                                en_dcu_int_win_mode_t enIntWinMode);
+en_dcu_int_win_mode_t DCU_GetIntWinMode(M4_DCU_TypeDef *DCUx);
+en_result_t DCU_SetCmpTriggerMode(M4_DCU_TypeDef *DCUx,
+                                en_dcu_cmp_trigger_mode_t enTriggerMode);
+en_dcu_cmp_trigger_mode_t DCU_GetCmpTriggerMode(M4_DCU_TypeDef *DCUx);
+en_result_t DCU_EnableInterrupt(M4_DCU_TypeDef *DCUx);
+en_result_t DCU_DisableInterrupt(M4_DCU_TypeDef *DCUx);
+en_flag_status_t DCU_GetIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag);
+en_result_t DCU_ClearIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag);
+en_result_t DCU_IrqSelCmd(M4_DCU_TypeDef *DCUx,
+                                en_dcu_int_sel_t enIntSel,
+                                en_functional_state_t enCmd);
+uint8_t DCU_ReadDataByte(M4_DCU_TypeDef *DCUx,
+                                en_dcu_data_register_t enDataReg);
+en_result_t DCU_WriteDataByte(M4_DCU_TypeDef *DCUx,
+                                en_dcu_data_register_t enDataReg, uint8_t u8Data);
+uint16_t DCU_ReadDataHalfWord(M4_DCU_TypeDef *DCUx,
+                                en_dcu_data_register_t enDataReg);
+en_result_t DCU_WriteDataHalfWord(M4_DCU_TypeDef *DCUx,
+                                en_dcu_data_register_t enDataReg,
+                                uint16_t u16Data);
+uint32_t DCU_ReadDataWord(M4_DCU_TypeDef *DCUx,
+                                en_dcu_data_register_t enDataReg);
+en_result_t DCU_WriteDataWord(M4_DCU_TypeDef *DCUx,
+                                en_dcu_data_register_t enDataReg,
+                                uint32_t u32Data);
+en_result_t DCU_SetTriggerSrc(M4_DCU_TypeDef *DCUx,
+                                en_event_src_t enTriggerSrc);
+void DCU_ComTriggerCmd(M4_DCU_TypeDef *DCUx,
+                        en_dcu_com_trigger_t enComTrigger,
+                        en_functional_state_t enState);
+
+//@} // DcuGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_DCU_ENABLE */
+
+#endif /* __HC32F460_DCU_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,363 @@
+/*****************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_dmac.h
+ **
+ ** A detailed description is available at
+ ** @link DmacGroup DMAC description @endlink
+ **
+ **   - 2018-11-18  CDT  First version for Device Driver Library of DMAC.
+ **
+ ******************************************************************************/
+#ifndef __HC32F460_DMAC_H__
+#define __HC32F460_DMAC_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_DMAC_ENABLE == DDL_ON)
+
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup DmacGroup Direct Memory Access Control(DMAC)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/**
+ *******************************************************************************
+ ** \brief DMA Channel
+ **
+ ******************************************************************************/
+typedef enum en_dma_channel
+{
+    DmaCh0                          = 0u,    ///< DMA channel 0
+    DmaCh1                          = 1u,    ///< DMA channel 1
+    DmaCh2                          = 2u,    ///< DMA channel 2
+    DmaCh3                          = 3u,    ///< DMA channel 3
+    DmaChMax                        = 4u     ///< DMA channel max
+}en_dma_channel_t;
+
+/**
+ *******************************************************************************
+ ** \brief DMA transfer data width
+ **
+ ******************************************************************************/
+typedef enum en_dma_transfer_width
+{
+    Dma8Bit                         = 0u,    ///< 8 bit transfer via DMA
+    Dma16Bit                        = 1u,    ///< 16 bit transfer via DMA
+    Dma32Bit                        = 2u     ///< 32 bit transfer via DMA
+}en_dma_transfer_width_t;
+
+/**
+ *******************************************************************************
+ ** \brief DMA flag
+ **
+ ******************************************************************************/
+typedef enum en_dma_flag
+{
+    DmaTransferComplete             = 0u,    ///< DMA transfer complete
+    DmaBlockComplete                = 1u,    ///< DMA block transfer complete
+    DmaTransferErr                  = 2u,    ///< DMA transfer error
+    DmaReqErr                       = 3u,    ///< DMA transfer request error
+    DmaFlagMax                      = 4u
+}en_dma_flag_t;
+
+/**
+ *******************************************************************************
+ ** \brief DMA address mode
+ **
+ ******************************************************************************/
+typedef enum en_dma_address_mode
+{
+    AddressFix                      = 0u,    ///< Address fixed
+    AddressIncrease                 = 1u,    ///< Address increased
+    AddressDecrease                 = 2u,    ///< Address decreased
+}en_dma_address_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief DMA link list pointer mode
+ **
+ ******************************************************************************/
+typedef enum en_dma_llp_mode
+{
+    LlpWaitNextReq                  = 0u,    ///< DMA trigger transfer after wait next request
+    LlpRunNow                       = 1u,    ///< DMA trigger transfer now
+}en_dma_llp_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief DMA interrupt selection
+ **
+ ******************************************************************************/
+typedef enum en_dma_irq_sel
+{
+    TrnErrIrq                       = 0u,    ///< Select DMA transfer error interrupt
+    TrnReqErrIrq                    = 1u,    ///< Select DMA transfer req over error interrupt
+    TrnCpltIrq                      = 2u,    ///< Select DMA transfer completion interrupt
+    BlkTrnCpltIrq                   = 3u,    ///< Select DMA block completion interrupt
+    DmaIrqSelMax                    = 4u
+}en_dma_irq_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief DMA re_config count mode
+ **
+ ******************************************************************************/
+typedef enum en_dma_recfg_cnt_mode
+{
+    CntFix                          = 0u,    ///< Fix
+    CntSrcAddr                      = 1u,    ///< Source address mode
+    CntDesAddr                      = 2u,    ///< Destination address mode
+}en_dma_recfg_cnt_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief DMA re_config destination address mode
+ **
+ ******************************************************************************/
+typedef enum en_dma_recfg_daddr_mode
+{
+    DaddrFix                        = 0u,    ///< Fix
+    DaddrNseq                       = 1u,    ///< No_sequence address
+    DaddrRep                        = 2u,    ///< Repeat address
+}en_dma_recfg_daddr_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief DMA re_config source address mode
+ **
+ ******************************************************************************/
+typedef enum en_dma_recfg_saddr_mode
+{
+    SaddrFix                        = 0u,    ///< Fix
+    SaddrNseq                       = 1u,    ///< No_sequence address
+    SaddrRep                        = 2u,    ///< Repeat address
+}en_dma_recfg_saddr_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief DMA channel status
+ **
+ ******************************************************************************/
+typedef enum en_dma_ch_flag
+{
+    DmaSta                          = 0u,   ///< DMA status.
+    ReCfgSta                        = 1u,   ///< DMA re_configuration status.
+    DmaCh0Sta                       = 2u,   ///< DMA channel 0 status.
+    DmaCh1Sta                       = 3u,   ///< DMA channel 1 status.
+    DmaCh2Sta                       = 4u,   ///< DMA channel 2 status.
+    DmaCh3Sta                       = 5u,   ///< DMA channel 3 status.
+}en_dma_ch_flag_t;
+
+/**
+ *******************************************************************************
+ ** \brief  DMA common trigger source select
+ **
+ ******************************************************************************/
+typedef enum en_dma_com_trigger
+{
+    DmaComTrigger_1   = 0x1,            ///< Select common trigger 1.
+    DmaComTrigger_2   = 0x2,            ///< Select common trigger 2.
+    DmaComTrigger_1_2 = 0x3,            ///< Select common trigger 1 and 2.
+} en_dma_com_trigger_t;
+
+/**
+ *******************************************************************************
+ ** \brief DMA llp descriptor
+ **
+ ******************************************************************************/
+typedef struct stc_dma_llp_descriptor
+{
+    uint32_t SARx;                             ///< DMA source address register
+    uint32_t DARx;                             ///< DMA destination address register
+    union
+    {
+        uint32_t DTCTLx;
+        stc_dma_dtctl_field_t DTCTLx_f;        ///< DMA data control register
+    };
+    union
+    {
+        uint32_t RPTx;
+        stc_dma_rpt_field_t RPTx_f;            ///< DMA repeat control register
+    };
+    union
+    {
+        uint32_t SNSEQCTLx;
+        stc_dma_snseqctl_field_t SNSEQCTLx_f;  ///< DMA source no-sequence control register
+    };
+    union
+    {
+        __IO uint32_t DNSEQCTLx;
+        stc_dma_dnseqctl_field_t DNSEQCTLx_f;  ///< DMA destination no-sequence control register
+    };
+    union
+    {
+        uint32_t LLPx;
+        stc_dma_llp_field_t LLPx_f;            ///< DMA link-list-pointer register
+    };
+    union
+    {
+        uint32_t CHxCTL;
+        stc_dma_ch0ctl_field_t CHxCTL_f;       ///< DMA channel control register
+    };
+}stc_dma_llp_descriptor_t;
+
+/**
+ *******************************************************************************
+ ** \brief DMA no-sequence function configuration
+ **
+ ******************************************************************************/
+typedef struct stc_dma_nseq_cfg
+{
+    uint32_t                u32Offset;      ///< DMA no-sequence offset.
+    uint16_t                u16Cnt;         ///< DMA no-sequence count.
+}stc_dma_nseq_cfg_t;
+
+/**
+ *******************************************************************************
+ ** \brief DMA no-sequence function configuration
+ **
+ ******************************************************************************/
+typedef struct stc_dma_nseqb_cfg
+{
+    uint32_t                u32NseqDist;    ///< DMA no-sequence district interval.
+    uint16_t                u16CntB;        ///< DMA no-sequence count.
+}stc_dma_nseqb_cfg_t;
+
+/**
+ *******************************************************************************
+ ** \brief DMA re_config configuration
+ **
+ ******************************************************************************/
+typedef struct stc_dma_recfg_ctl
+{
+    uint16_t                    u16SrcRptBSize; ///< The source repeat size.
+    uint16_t                    u16DesRptBSize; ///< The destination repeat size.
+    en_dma_recfg_saddr_mode_t   enSaddrMd;      ///< DMA re_config source address mode.
+    en_dma_recfg_daddr_mode_t   enDaddrMd;      ///< DMA re_config destination address mode.
+    en_dma_recfg_cnt_mode_t     enCntMd;        ///< DMA re_config count mode.
+    stc_dma_nseq_cfg_t          stcSrcNseqBCfg; ///< The source no_sequence re_config.
+    stc_dma_nseq_cfg_t          stcDesNseqBCfg; ///< The destination no_sequence re_config.
+}stc_dma_recfg_ctl_t;
+
+/**
+ *******************************************************************************
+ ** \brief DMA channel configuration
+ **
+ ******************************************************************************/
+typedef struct stc_dma_ch_cfg
+{
+    en_dma_address_mode_t   enSrcInc;       ///< DMA source address update mode.
+    en_dma_address_mode_t   enDesInc;       ///< DMA destination address update mode.
+    en_functional_state_t   enSrcRptEn;     ///< Enable source repeat function or not.
+    en_functional_state_t   enDesRptEn;     ///< Enable destination repeat function or not.
+    en_functional_state_t   enSrcNseqEn;    ///< Enable source no_sequence function or not.
+    en_functional_state_t   enDesNseqEn;    ///< Enable destination no_sequence function or not.
+    en_dma_transfer_width_t enTrnWidth;     ///< DMA transfer data width.
+    en_functional_state_t   enLlpEn;        ///< Enable linked list pointer function or not.
+    en_dma_llp_mode_t       enLlpMd;        ///< Dma linked list pointer mode.
+    en_functional_state_t   enIntEn;        ///< Enable interrupt function or not.
+}stc_dma_ch_cfg_t;
+
+
+/**
+ *******************************************************************************
+ ** \brief DMA configuration
+ **
+ ******************************************************************************/
+typedef struct stc_dma_config
+{
+    uint16_t                u16BlockSize;       ///< Transfer block size = 1024, when 0 is set.
+    uint16_t                u16TransferCnt;     ///< Transfer counter.
+    uint32_t                u32SrcAddr;         ///< The source address.
+    uint32_t                u32DesAddr;         ///< The destination address.
+    uint16_t                u16SrcRptSize;      ///< The source repeat size.
+    uint16_t                u16DesRptSize;      ///< The destination repeat size.
+    uint32_t                u32DmaLlp;          ///< The Dma linked list pointer address
+    stc_dma_nseq_cfg_t      stcSrcNseqCfg;      ///< The source no_sequence configuration.
+    stc_dma_nseq_cfg_t      stcDesNseqCfg;      ///< The destination no_sequence configuration.
+    stc_dma_ch_cfg_t        stcDmaChCfg;        ///< The Dma channel configuration.
+}stc_dma_config_t;
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+void DMA_Cmd(M4_DMA_TypeDef* pstcDmaReg, en_functional_state_t enNewState);
+en_result_t DMA_EnableIrq(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel);
+en_result_t DMA_DisableIrq(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel);
+en_flag_status_t DMA_GetIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel);
+en_result_t DMA_ClearIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel);
+en_result_t DMA_ChannelCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_functional_state_t enNewState);
+void DMA_InitReConfig(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_recfg_ctl_t* pstcDmaReCfg);
+void DMA_ReCfgCmd(M4_DMA_TypeDef* pstcDmaReg,en_functional_state_t enNewState);
+en_flag_status_t DMA_GetChFlag(M4_DMA_TypeDef* pstcDmaReg, en_dma_ch_flag_t enDmaChFlag);
+
+en_result_t DMA_SetSrcAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address);
+en_result_t DMA_SetDesAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address);
+en_result_t DMA_SetBlockSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16BlkSize);
+en_result_t DMA_SetTransferCnt(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16TrnCnt);
+en_result_t DMA_SetSrcRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size);
+en_result_t DMA_SetDesRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size);
+en_result_t DMA_SetSrcRptbSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size);
+en_result_t DMA_SetDesRptbSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size);
+en_result_t DMA_SetSrcNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseq_cfg_t* pstcSrcNseqCfg);
+en_result_t DMA_SetSrcNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseqb_cfg_t* pstcSrcNseqBCfg);
+en_result_t DMA_SetDesNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseq_cfg_t* pstDesNseqCfg);
+en_result_t DMA_SetDesNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseqb_cfg_t* pstDesNseqBCfg);
+en_result_t DMA_SetLLP(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Pointer);
+
+void DMA_SetTriggerSrc(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_event_src_t enSrc);
+void DMA_SetReConfigTriggerSrc(en_event_src_t enSrc);
+void DMA_ComTriggerCmd(M4_DMA_TypeDef* pstcDmaReg,  uint8_t u8Ch, en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState);
+void DMA_ReConfigComTriggerCmd(en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState);
+
+void DMA_ChannelCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_ch_cfg_t* pstcChCfg);
+void DMA_InitChannel(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_config_t* pstcDmaCfg);
+void DMA_DeInit(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch);
+
+
+
+//@} // DmacGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_DMAC_ENABLE */
+
+#endif /* __HC32F460_DMAC_H__*/
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,209 @@
+/*****************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_efm.h
+ **
+ ** A detailed description is available at
+ ** @link EfmGroup EFM description @endlink
+ **
+ **   - 2018-10-29  CDT  First version for Device Driver Library of EFM.
+ **
+ ******************************************************************************/
+#ifndef __HC32F460_EFM_H__
+#define __HC32F460_EFM_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_EFM_ENABLE == DDL_ON)
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup EfmGroup Embedded Flash Management unit(EFM)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ *******************************************************************************
+ ** \brief  The flash status.
+ **
+ ******************************************************************************/
+typedef enum en_efm_flash_status
+{
+    FlashReady                  = 1u,   ///< The flash ready flag.
+    FlashRWErr                  = 2u,   ///< The flash read/write error flag.
+    FlashEOP                    = 3u,   ///< The flash end of operation flag.
+    FlashPgMissMatch            = 4u,   ///< The flash program miss match flag.
+    FlashPgSizeErr              = 5u,   ///< The flash program size error flag.
+    FlashPgareaPErr             = 6u,   ///< The flash program protect area error flag.
+    FlashWRPErr                 = 7u,   ///< The flash write protect error flag.
+}en_efm_flash_status_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The flash read mode.
+ **
+ ******************************************************************************/
+typedef enum en_efm_read_md
+{
+    NormalRead                  = 0u,   ///< The flash normal read mode.
+    UltraPowerRead              = 1u,   ///< The flash ultra power read mode.
+}en_efm_read_md_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The flash interrupt select.
+ **
+ ******************************************************************************/
+typedef enum en_efm_int_sel
+{
+    PgmErsErrInt                = 0u,   ///< The flash program / erase error interrupt.
+    EndPgmInt                   = 1u,   ///< The flash end of program interrupt.
+    ColErrInt                   = 2u,   ///< The flash read collided error interrupt.
+}en_efm_int_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The bus state while flash program & erase.
+ **
+ ******************************************************************************/
+typedef enum en_efm_bus_sta
+{
+    BusBusy                     = 0u,   ///< The bus busy while flash program & erase.
+    BusRelease                  = 1u,   ///< The bus release while flash program & erase.
+}en_efm_bus_sta_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Structure of windows protect address.
+ **
+ ** \note   None.
+ **
+ ******************************************************************************/
+typedef struct stc_efm_win_protect_addr
+{
+    uint32_t            StartAddr;      ///< The protect start address.
+    uint32_t            EndAddr;        ///< The protect end address.
+}stc_efm_win_protect_addr_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Structure of unique ID.
+ **
+ ** \note   None.
+ **
+ ******************************************************************************/
+typedef struct stc_efm_unique_id
+{
+    uint32_t            uniqueID1;      ///< unique ID 1.
+    uint32_t            uniqueID2;      ///< unique ID 2.
+    uint32_t            uniqueID3;      ///< unique ID 3.
+}stc_efm_unique_id_t;
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+ /* Flach latency cycle (0~15) */
+#define EFM_LATENCY_0                   (0ul)
+#define EFM_LATENCY_1                   (1ul)
+#define EFM_LATENCY_2                   (2ul)
+#define EFM_LATENCY_3                   (3ul)
+#define EFM_LATENCY_4                   (4ul)
+#define EFM_LATENCY_5                   (5ul)
+#define EFM_LATENCY_6                   (6ul)
+#define EFM_LATENCY_7                   (7ul)
+#define EFM_LATENCY_8                   (8ul)
+#define EFM_LATENCY_9                   (9ul)
+#define EFM_LATENCY_10                  (10ul)
+#define EFM_LATENCY_11                  (11ul)
+#define EFM_LATENCY_12                  (12ul)
+#define EFM_LATENCY_13                  (13ul)
+#define EFM_LATENCY_14                  (14ul)
+#define EFM_LATENCY_15                  (15ul)
+
+/* Flash flag */
+#define EFM_FLAG_WRPERR                 (0x00000001ul)
+#define EFM_FLAG_PEPRTERR               (0x00000002ul)
+#define EFM_FLAG_PGSZERR                (0x00000004ul)
+#define EFM_FLAG_PGMISMTCH              (0x00000008ul)
+#define EFM_FLAG_EOP                    (0x00000010ul)
+#define EFM_FLAG_COLERR                 (0x00000020ul)
+#define EFM_FLAG_RDY                    (0x00000100ul)
+
+/* Flash operate mode */
+#define EFM_MODE_READONLY               (0ul)
+#define EFM_MODE_SINGLEPROGRAM          (1ul)
+#define EFM_MODE_SINGLEPROGRAMRB        (2ul)
+#define EFM_MODE_SEQUENCEPROGRAM        (3ul)
+#define EFM_MODE_SECTORERASE            (4ul)
+#define EFM_MODE_CHIPERASE              (5ul)
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+void EFM_Unlock(void);
+void EFM_Lock(void);
+
+void EFM_FlashCmd(en_functional_state_t enNewState);
+void EFM_SetLatency(uint32_t u32Latency);
+void EFM_InstructionCacheCmd(en_functional_state_t enNewState);
+void EFM_DataCacheRstCmd(en_functional_state_t enNewState);
+void EFM_SetReadMode(en_efm_read_md_t enReadMD);
+void EFM_ErasePgmCmd(en_functional_state_t enNewState);
+en_result_t EFM_SetErasePgmMode(uint32_t u32Mode);
+void EFM_InterruptCmd(en_efm_int_sel_t enInt, en_functional_state_t enNewState);
+
+en_flag_status_t EFM_GetFlagStatus(uint32_t u32flag);
+en_flag_status_t EFM_GetSwitchStatus(void);
+void EFM_ClearFlag(uint32_t u32flag);
+en_efm_flash_status_t EFM_GetStatus(void);
+void EFM_SetBusState(en_efm_bus_sta_t enState);
+
+void EFM_SetWinProtectAddr(stc_efm_win_protect_addr_t stcAddr);
+
+en_result_t EFM_SingleProgram(uint32_t u32Addr, uint32_t u32Data);
+en_result_t EFM_SingleProgramRB(uint32_t u32Addr, uint32_t u32Data);
+en_result_t EFM_SequenceProgram(uint32_t u32Addr, uint32_t u32Len, void *pBuf);
+en_result_t EFM_SectorErase(uint32_t u32Addr);
+en_result_t EFM_MassErase(uint32_t u32Addr);
+
+en_result_t EFM_OtpLock(uint32_t u32Addr);
+stc_efm_unique_id_t EFM_ReadUID(void);
+
+
+//@} // EfmGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_EFM_ENABLE */
+
+#endif /* __HC32F460_EFM_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
+
@@ -0,0 +1,205 @@
+/*******************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_emb.h
+ **
+ ** A detailed description is available at
+ ** @link EMBGroup EMB description @endlink
+ **
+ **   - 2018-11-24  CDT  First version for Device Driver Library of EMB.
+ **
+ ******************************************************************************/
+#ifndef __HC32F460_EMB_H__
+#define __HC32F460_EMB_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_EMB_ENABLE == DDL_ON)
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup EMBGroup Emergency Brake(EMB)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/**
+ *******************************************************************************
+ ** \brief EMB status enumeration
+ ******************************************************************************/
+typedef enum en_emb_status
+{
+    EMBFlagPortIn  = 0u,      ///< EMB port in brake flag
+    EMBFlagPWMSame = 1u,      ///< EMB PWM same brake flag
+    EMBFlagCmp     = 2u,      ///< EMB CMP brake flag
+    EMBFlagOSCFail  = 3u,     ///< EMB oscillator fail brake flag
+    EMBPortInState = 4u,      ///< EMB port in state
+    EMBPWMState    = 5u,      ///< EMB PWM same state
+} en_emb_status_t;
+
+/**
+ *******************************************************************************
+ ** \brief EMB status clear(recover) enumeration
+ ******************************************************************************/
+typedef enum en_emb_status_clr
+{
+    EMBPortInFlagClr  = 0u,   ///< EMB port in brake flag clear
+    EMBPWMSameFlagCLr = 1u,   ///< EMB PWM same brake flag clear
+    EMBCmpFlagClr     = 2u,   ///< EMB CMP brake flag clear
+    EMBOSCFailFlagCLr  = 3u,  ///< EMB oscillator fail brake flag clear
+} en_emb_status_clr_t;
+
+/**
+ *******************************************************************************
+ ** \brief EMB irq enumeration
+ ******************************************************************************/
+typedef enum en_emb_irq_type
+{
+    PORTBrkIrq   = 0u,        ///< EMB port brake interrupt
+    PWMSmBrkIrq  = 1u,        ///< EMB PWM same brake interrupt
+    CMPBrkIrq    = 2u,        ///< EMB CMP brake interrupt
+    OSCFailBrkIrq = 3u,        ///< EMB oscillator fail brake interrupt
+} en_emb_irq_type_t;
+
+/**
+ *******************************************************************************
+ ** \brief EMB port in filter enumeration
+ ******************************************************************************/
+typedef enum en_emb_port_filter
+{
+    EMBPortFltDiv0    = 0u,   ///< EMB port in filter with PCLK clock
+    EMBPortFltDiv8    = 1u,   ///< EMB port in filter with PCLK/8 clock
+    EMBPortFltDiv32   = 2u,   ///< EMB port in filter with PCLK/32 clock
+    EMBPortFltDiv128  = 3u,   ///< EMB port in filter with PCLK/128 clock
+} en_emb_port_filter_t;
+
+/**
+ *******************************************************************************
+ ** \brief EMB CR0 for timer6 config
+ ** \note
+ ******************************************************************************/
+typedef struct stc_emb_ctrl_timer6
+{
+    bool                  bEnPortBrake;             ///< Enable port brake
+    bool                  bEnCmp1Brake;             ///< Enable CMP1 brake
+    bool                  bEnCmp2Brake;             ///< Enable CMP2 brake
+    bool                  bEnCmp3Brake;             ///< Enable CMP3 brake
+    bool                  bEnOSCFailBrake;          ///< Enable OSC fail brake
+    bool                  bEnTimer61PWMSBrake;      ///< Enable tiemr61 PWM same brake
+    bool                  bEnTimer62PWMSBrake;      ///< Enable tiemr62 PWM same brake
+    bool                  bEnTimer63PWMSBrake;      ///< Enable tiemr63 PWM same brake
+    en_emb_port_filter_t  enPortInFltClkSel;        ///< Port in filter clock selection
+    bool                  bEnPorInFlt;              ///< Enable port in filter
+    bool                  bEnPortInLevelSel_Low;    ///< Poit input active level 1: LowLevel 0:HighLevel
+}stc_emb_ctrl_timer6_t;
+
+/**
+ *******************************************************************************
+ ** \brief EMB CR1~3 for timer4x config
+ ** \note
+ ******************************************************************************/
+typedef struct stc_emb_ctrl_timer4
+{
+    bool                  bEnPortBrake;             ///< Enable port brake
+    bool                  bEnCmp1Brake;             ///< Enable CMP1 brake
+    bool                  bEnCmp2Brake;             ///< Enable CMP2 brake
+    bool                  bEnCmp3Brake;             ///< Enable CMP3 brake
+    bool                  bEnOSCFailBrake;          ///< Enable OS fail brake
+    bool                  bEnTimer4xWHLSammeBrake;  ///< Enable tiemr4x PWM WH WL same brake
+    bool                  bEnTimer4xVHLSammeBrake;  ///< Enable tiemr4x PWM VH VL same brake
+    bool                  bEnTimer4xUHLSammeBrake;  ///< Enable tiemr4x PWM UH UL same brake
+    en_emb_port_filter_t  enPortInFltClkSel;        ///< Port in filter clock selection
+    bool                  bEnPorInFlt;              ///< Enable port in filter
+    bool                  bEnPortInLevelSel_Low;    ///< Poit input active level 1: LowLevel 0:HighLevel
+}stc_emb_ctrl_timer4_t;
+
+
+/**
+ *******************************************************************************
+ ** \brief EMB PWM level detect timer6 config
+ ** \note
+ ******************************************************************************/
+typedef struct stc_emb_pwm_level_timer6
+{
+    bool      bEnTimer61HighLevelDect;             ///< Enable tiemr61 active detected level 1:HighLevel 0:LowLevel
+    bool      bEnTimer62HighLevelDect;             ///< Enable tiemr62 active detected level 1:HighLevel 0:LowLevel
+    bool      bEnTimer63HighLevelDect;             ///< Enable tiemr63 active detected level 1:HighLevel 0:LowLevel
+}stc_emb_pwm_level_timer6_t;
+
+/**
+ *******************************************************************************
+ ** \brief EMB PWM level detect timer4x config
+ ** \note
+ ******************************************************************************/
+typedef struct stc_emb_pwm_level_timer4
+{
+    bool      bEnUHLPhaseHighLevelDect;            ///< Enable tiemr4x UH UL active detected level 1:HighLevel 0:LowLevel
+    bool      bEnVHLPhaseHighLevelDect;            ///< Enable tiemr4x VH VL active detected level 1:HighLevel 0:LowLevel
+    bool      bEnWHLphaseHighLevelDect;            ///< Enable tiemr4x WH WL active detected level 1:HighLevel 0:LowLevel
+}stc_emb_pwm_level_timer4_t;
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+  Global function prototypes (definition in C source)
+ ******************************************************************************/
+/* IRQ config */
+en_result_t EMB_ConfigIrq(M4_EMB_TypeDef *EMBx,
+                                en_emb_irq_type_t enEMBIrq,
+                                bool bEn);
+/* Get status(flag) */
+bool EMB_GetStatus(M4_EMB_TypeDef *EMBx, en_emb_status_t enStatus);
+/*  Status(flag) clear (recover) */
+en_result_t EMB_ClrStatus(M4_EMB_TypeDef *EMBx,
+                                en_emb_status_clr_t enStatusClr);
+/*  Control Register(CTL) config for timer6 */
+en_result_t EMB_Config_CR_Timer6(const stc_emb_ctrl_timer6_t* pstcEMBConfigCR);
+/*  Control Register(CTL) config for timer4 */
+en_result_t EMB_Config_CR_Timer4(M4_EMB_TypeDef *EMBx,
+                                const stc_emb_ctrl_timer4_t* pstcEMBConfigCR);
+/*  PWM level detect (short detection) selection config for timer6 */
+en_result_t EMB_PWMLv_Timer6(const stc_emb_pwm_level_timer6_t* pstcEMBPWMlv);
+/*  PWM level detect (short detection) selection config for timer4 */
+en_result_t EMB_PWMLv_Timer4(M4_EMB_TypeDef *EMBx,
+                                const stc_emb_pwm_level_timer4_t* pstcEMBPWMlv);
+/*  Software brake */
+en_result_t EMB_SwBrake(M4_EMB_TypeDef *EMBx, bool bEn);
+
+//@} // EMBGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_EMB_ENABLE */
+
+#endif /* __HC32F460_EMB_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,176 @@
+/*****************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_event_port.h
+ **
+ ** A detailed description is available at
+ ** @link EventPortGroup EventPort description @endlink
+ **
+ **   - 2018-12-07 CDT First version for Device Driver Library of EventPort.
+ **
+ ******************************************************************************/
+
+#ifndef __HC32F460_EVENT_PORT_H__
+#define __HC32F460_EVENT_PORT_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_EVENT_PORT_ENABLE == DDL_ON)
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup EventPortGroup Event Port (EventPort)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ *******************************************************************************
+ ** \brief Event Port Index enumeration
+ **
+ ******************************************************************************/
+typedef enum en_event_port
+{
+    EventPort1 = 0,                     ///< Event port 1
+    EventPort2 = 1,                     ///< Event port 2
+    EventPort3 = 2,                     ///< Event port 3
+    EventPort4 = 3,                     ///< Event port 4
+}en_event_port_t;
+
+/**
+ *******************************************************************************
+ ** \brief Event Port Pin enumeration
+ **
+ ******************************************************************************/
+typedef enum en_event_pin
+{
+    EventPin00 = 1u << 0,               ///< Event port Pin 00
+    EventPin01 = 1u << 1,               ///< Event port Pin 01
+    EventPin02 = 1u << 2,               ///< Event port Pin 02
+    EventPin03 = 1u << 3,               ///< Event port Pin 03
+    EventPin04 = 1u << 4,               ///< Event port Pin 04
+    EventPin05 = 1u << 5,               ///< Event port Pin 05
+    EventPin06 = 1u << 6,               ///< Event port Pin 06
+    EventPin07 = 1u << 7,               ///< Event port Pin 07
+    EventPin08 = 1u << 8,               ///< Event port Pin 08
+    EventPin09 = 1u << 9,               ///< Event port Pin 09
+    EventPin10 = 1u << 10,              ///< Event port Pin 10
+    EventPin11 = 1u << 11,              ///< Event port Pin 11
+    EventPin12 = 1u << 12,              ///< Event port Pin 12
+    EventPin13 = 1u << 13,              ///< Event port Pin 13
+    EventPin14 = 1u << 14,              ///< Event port Pin 14
+    EventPin15 = 1u << 15,              ///< Event port Pin 15
+    EventPinAll= 0xFFFF,                ///< All event pins are selected
+}en_event_pin_t;
+
+/**
+ *******************************************************************************
+ ** \brief  Event Port common trigger source select
+ **
+ ******************************************************************************/
+typedef enum en_event_port_com_trigger
+{
+    EpComTrigger_1   = 0x1,            ///< Select common trigger 1.
+    EpComTrigger_2   = 0x2,            ///< Select common trigger 2.
+    EpComTrigger_1_2 = 0x3,            ///< Select common trigger 1 and 2.
+} en_event_port_com_trigger_t;
+
+/**
+ *******************************************************************************
+ ** \brief Event Port direction enumeration
+ **
+ ******************************************************************************/
+typedef enum en_event_port_dir
+{
+    EventPortIn     = 0,                ///< Event Port direction 'IN'
+    EventPortOut    = 1,                ///< Event Port direction 'OUT'
+}en_event_port_dir_t;
+
+/**
+ *******************************************************************************
+ ** \brief Enumeration to filter clock setting for Event port detect
+ **
+ ** \note
+ ******************************************************************************/
+typedef enum en_ep_flt_clk
+{
+    Pclk1Div1   = 0u,                   ///< PCLK1 as EP filter clock source
+    Pclk1Div8   = 1u,                   ///< PCLK1 div8 as EP filter clock source
+    Pclk1Div32  = 2u,                   ///< PCLK1 div32 as EP filter clock source
+    Pclk1Div64  = 3u,                   ///< PCLK1 div64 as EP filter clock source
+}en_ep_flt_clk_t;
+
+/**
+ *******************************************************************************
+ ** \brief Event port init structure definition
+ ******************************************************************************/
+typedef struct stc_event_port_init
+{
+    en_event_port_dir_t     enDirection;    ///< Input/Output setting
+    en_functional_state_t   enReset;        ///< Corresponding pin reset after triggered
+    en_functional_state_t   enSet;          ///< Corresponding pin set after triggered
+    en_functional_state_t   enRisingDetect; ///< Rising edge detect enable
+    en_functional_state_t   enFallingDetect;///< Falling edge detect enable
+    en_functional_state_t   enFilter;       ///< Filter clock source select
+    en_ep_flt_clk_t         enFilterClk;    ///< Filter clock, ref@ en_ep_flt_clk_t for details
+}stc_event_port_init_t;
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+  Global function prototypes (definition in C source)
+ ******************************************************************************/
+extern en_result_t EVENTPORT_Init(en_event_port_t enEventPort,                 \
+        uint16_t u16EventPin, const stc_event_port_init_t *pstcEventPortInit);
+extern en_result_t EVENTPORT_DeInit(void);
+extern en_result_t EVENTPORT_SetTriggerSrc(en_event_port_t enEventPort,        \
+                                           en_event_src_t enTriggerSrc);
+void EVENTPORT_ComTriggerCmd(en_event_port_t enEventPort,                      \
+                             en_event_port_com_trigger_t enComTrigger,         \
+                             en_functional_state_t enState);
+extern uint16_t EVENTPORT_GetData(en_event_port_t enEventPort);
+extern en_flag_status_t EVENTPORT_GetBit(en_event_port_t enEventPort,          \
+                                         en_event_pin_t enEventPin);
+extern en_result_t EVENTPORT_SetBits(en_event_port_t enEventPort,              \
+                                    en_event_pin_t u16EventPin);
+extern en_result_t EVENTPORT_ResetBits(en_event_port_t enEventPort,            \
+                                      en_event_pin_t u16EventPin);
+
+//@} // EventPortGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_EVENT_PORT_ENABLE */
+
+#endif /* __HC32F460_EVENT_PORT_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,257 @@
+/******************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_exint_nmi_swi.h
+ **
+ ** A detailed description is available at
+ ** @link ExintNmiSwiGroup Exint/Nmi/Swi description @endlink
+ **
+ **   - 2018-10-17 CDT First version for Device Driver Library of exint, Nmi, SW interrupt.
+ **
+ ******************************************************************************/
+
+#ifndef __HC32F460_EXINT_NMI_SWI_H__
+#define __HC32F460_EXINT_NMI_SWI_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_EXINT_NMI_SWI_ENABLE  == DDL_ON)
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup ExintNmiSwiGroup External Interrupts (External Interrupt),       \
+ ** NMI (Non-Maskable Interrupt), SWI (Software Interrupt)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ *******************************************************************************
+ ** \brief Enumeration to filter clock setting for EXINT and NMI
+ **
+ ** \note
+ ******************************************************************************/
+typedef enum en_ei_flt_clk
+{
+    Pclk3Div1   = 0u,                   ///< PCLK3 as EP filter clock source
+    Pclk3Div8   = 1u,                   ///< PCLK3 div8 as EP filter clock source
+    Pclk3Div32  = 2u,                   ///< PCLK3 div32 as EP filter clock source
+    Pclk3Div64  = 3u,                   ///< PCLK3 div64 as EP filter clock source
+}en_ei_flt_clk_t;
+
+/**
+ *******************************************************************************
+ ** \brief Enumeration to NMI detection
+ **
+ ** \note
+ ******************************************************************************/
+typedef enum en_nmi_lvl
+{
+    NmiFallingEdge = 0u,                ///< Falling edge detection
+    NmiRisingEdge  = 1u,                ///< Rising edge detection
+}en_nmi_lvl_t;
+
+/**
+ *******************************************************************************
+ ** \brief Enumeration to EXTI detection
+ **
+ ** \note
+ ******************************************************************************/
+typedef enum en_exti_lvl
+{
+    ExIntFallingEdge = 0u,              ///< Falling edge detection
+    ExIntRisingEdge  = 1u,              ///< Rising edge detection
+    ExIntBothEdge    = 2u,              ///< Falling or Rising edge detection
+    ExIntLowLevel    = 3u,              ///< "L" level detection
+}en_exti_lvl_t;
+
+/**
+ *******************************************************************************
+ ** \brief Enumeration to define an index for EXINT
+ ******************************************************************************/
+typedef enum en_exti_ch
+{
+    ExtiCh00    =  0u,
+    ExtiCh01    =  1u,
+    ExtiCh02    =  2u,
+    ExtiCh03    =  3u,
+    ExtiCh04    =  4u,
+    ExtiCh05    =  5u,
+    ExtiCh06    =  6u,
+    ExtiCh07    =  7u,
+    ExtiCh08    =  8u,
+    ExtiCh09    =  9u,
+    ExtiCh10    = 10u,
+    ExtiCh11    = 11u,
+    ExtiCh12    = 12u,
+    ExtiCh13    = 13u,
+    ExtiCh14    = 14u,
+    ExtiCh15    = 15u,
+}en_exti_ch_t;
+
+/**
+ *******************************************************************************
+ ** \brief Enumeration to define the SWI channel
+ ******************************************************************************/
+typedef enum en_swi_ch
+{
+    SwiCh00     = 1u << 0,
+    SwiCh01     = 1u << 1,
+    SwiCh02     = 1u << 2,
+    SwiCh03     = 1u << 3,
+    SwiCh04     = 1u << 4,
+    SwiCh05     = 1u << 5,
+    SwiCh06     = 1u << 6,
+    SwiCh07     = 1u << 7,
+    SwiCh08     = 1u << 8,
+    SwiCh09     = 1u << 9,
+    SwiCh10     = 1u << 10,
+    SwiCh11     = 1u << 11,
+    SwiCh12     = 1u << 12,
+    SwiCh13     = 1u << 13,
+    SwiCh14     = 1u << 14,
+    SwiCh15     = 1u << 15,
+    SwiCh16     = 1u << 16,
+    SwiCh17     = 1u << 17,
+    SwiCh18     = 1u << 18,
+    SwiCh19     = 1u << 19,
+    SwiCh20     = 1u << 20,
+    SwiCh21     = 1u << 21,
+    SwiCh22     = 1u << 22,
+    SwiCh23     = 1u << 23,
+    SwiCh24     = 1u << 24,
+    SwiCh25     = 1u << 25,
+    SwiCh26     = 1u << 26,
+    SwiCh27     = 1u << 27,
+    SwiCh28     = 1u << 28,
+    SwiCh29     = 1u << 29,
+    SwiCh30     = 1u << 30,
+    SwiCh31     = 1u << 31,
+}en_swi_ch_t;
+
+/**
+ *******************************************************************************
+ ** \brief External Interrupt configuration
+ **
+ ** \note The EXINT configuration
+ ******************************************************************************/
+typedef struct stc_exint_config
+{
+    en_exti_ch_t            enExitCh;           ///< External Int CH.0~15 ref@ en_exti_ch_t
+    en_functional_state_t   enFilterEn;         ///< TRUE: Enable filter function
+    en_ei_flt_clk_t         enFltClk;           ///< Filter clock, ref@ en_ei_flt_clk_t for details
+    en_exti_lvl_t           enExtiLvl;          ///< Detection level, ref@ en_exti_lvl_t for details
+}stc_exint_config_t;
+
+/**
+ *******************************************************************************
+ ** \brief Enumeration to NMI Trigger source
+ **
+ ** \note
+ ******************************************************************************/
+typedef enum en_nmi_src
+{
+    NmiSrcNmi       = 1u << 0,          ///< NMI pin
+    NmiSrcSwdt      = 1u << 1,          ///< Special watch dog timer
+    NmiSrcVdu1      = 1u << 2,          ///< Voltage detect 1
+    NmiSrcVdu2      = 1u << 3,          ///< Voltage detect 2
+    NmiSrcXtalStop  = 1u << 5,          ///< Xtal stop
+    NmiSrcSramPE    = 1u << 8,          ///< SRAM1/2/HS/Ret parity error
+    NmiSrcSramDE    = 1u << 9,          ///< SRAM3 ECC error
+    NmiSrcMpu       = 1u << 10,         ///< MPU error
+    NmiSrcWdt       = 1u << 11,         ///< Watch dog timer
+}en_nmi_src_t;
+
+/**
+ *******************************************************************************
+ ** \brief Enumeration to software interrupt or event
+ **
+ ** \note
+ ******************************************************************************/
+typedef enum en_swi_type
+{
+    SwEvent         = 0u,               ///< software event
+    SwInt           = 1u,               ///< software interrupt
+}en_swi_type_t;
+
+
+/**
+ *******************************************************************************
+ ** \brief NMI configuration
+ **
+ ** \note The NMI configuration
+ ******************************************************************************/
+typedef struct stc_nmi_config
+{
+    en_functional_state_t   enFilterEn;     ///< TRUE: Enable filter function
+    en_ei_flt_clk_t         enFilterClk;    ///< Filter clock, ref@ en_flt_clk_t for details
+    en_nmi_lvl_t            enNmiLvl;       ///< Detection level, ref@ en_nmi_lvl_t for details
+    uint16_t                u16NmiSrc;      ///< NMI trigger source, ref@ en_nmi_src_t for details
+    func_ptr_t              pfnNmiCallback; ///< Callback pointers
+}stc_nmi_config_t;
+
+/**
+ *******************************************************************************
+ ** \brief SWI configuration
+ **
+ ** \note The SWI configuration
+ ******************************************************************************/
+typedef struct stc_swi_config
+{
+    en_swi_ch_t             enSwiCh;        ///< SWI channel
+    en_swi_type_t           enSwiType;      ///< Select software interrupt or event
+    func_ptr_t              pfnSwiCallback; ///< Callback pointers
+}stc_swi_config_t;
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+extern en_result_t EXINT_Init(const stc_exint_config_t *pstcExtiConfig);
+extern en_int_status_t EXINT_IrqFlgGet(en_exti_ch_t enExint);
+extern en_result_t EXINT_IrqFlgClr(en_exti_ch_t enExint);
+extern en_result_t NMI_Init(const stc_nmi_config_t *pstcNmiConfig);
+extern en_result_t NMI_DeInit(void);
+extern en_int_status_t NMI_IrqFlgGet(en_nmi_src_t enNmiSrc);
+extern en_result_t NMI_IrqFlgClr(uint16_t u16NmiSrc);
+extern en_result_t SWI_Enable(uint32_t u32SwiCh);
+extern en_result_t SWI_Disable(uint32_t u32SwiCh);
+
+//@} // ExintNmiSwiGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_EXINT_NMI_SWI_ENABLE */
+
+#endif /* __HC32F460_EXINT_NMI_SWI_H__ */
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,294 @@
+/*****************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_gpio.h
+ **
+ ** A detailed description is available at
+ ** @link GpioGroup Gpio description @endlink
+ **
+ **   - 2018-10-12 CDT First version for Device Driver Library of Gpio.
+ **
+ ******************************************************************************/
+
+#ifndef __HC32F460_GPIO_H__
+#define __HC32F460_GPIO_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_GPIO_ENABLE == DDL_ON)
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup GpioGroup General Purpose Input/Output(GPIO)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+  /**
+ *******************************************************************************
+ ** \brief GPIO Configuration Mode enumeration
+ **
+ ******************************************************************************/
+typedef enum en_pin_mode
+{
+    Pin_Mode_In  = 0,                   ///< GPIO Input mode
+    Pin_Mode_Out = 1,                   ///< GPIO Output mode
+    Pin_Mode_Ana = 2,                   ///< GPIO Analog mode
+}en_pin_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief GPIO Drive Capacity enumeration
+ **
+ ******************************************************************************/
+typedef enum en_pin_drv
+{
+    Pin_Drv_L = 0,                      ///< Low Drive Capacity
+    Pin_Drv_M = 1,                      ///< Middle Drive Capacity
+    Pin_Drv_H = 2,                      ///< High Drive Capacity
+}en_pin_drv_t;
+
+/**
+ *******************************************************************************
+ ** \brief GPIO Output Type enumeration
+ ******************************************************************************/
+typedef enum en_pin_o_type
+{
+    Pin_OType_Cmos = 0,                 ///< CMOS
+    Pin_OType_Od   = 1,                 ///< Open Drain
+}en_pin_o_type_t;
+
+
+typedef enum en_debug_port
+{
+    TCK_SWCLK   =   1 << 0,             ///< TCK or SWCLK
+    TMS_SWDIO   =   1 << 1,             ///< TMS or SWDIO
+    TDO_SWO     =   1 << 2,             ///< TOD or SWD
+    TDI         =   1 << 3,             ///< TDI
+    TRST        =   1 << 4,             ///< TRest
+    ALL_DBG_PIN =   0x1Fu               ///< All above
+}en_debug_port_t;
+/**
+ *******************************************************************************
+ ** \brief GPIO Port Index enumeration
+ ******************************************************************************/
+typedef enum en_port
+{
+    PortA = 0,                          ///< port group A
+    PortB = 1,                          ///< port group B
+    PortC = 2,                          ///< port group C
+    PortD = 3,                          ///< port group D
+    PortE = 4,                          ///< port group E
+    PortH = 5,                          ///< port group H
+}en_port_t;
+
+/**
+ *******************************************************************************
+ ** \brief GPIO Pin Index enumeration
+ ******************************************************************************/
+typedef enum en_pin
+{
+    Pin00 = (1 <<  0),                  ///< Pin index 00 of each port group
+    Pin01 = (1 <<  1),                  ///< Pin index 01 of each port group
+    Pin02 = (1 <<  2),                  ///< Pin index 02 of each port group
+    Pin03 = (1 <<  3),                  ///< Pin index 03 of each port group
+    Pin04 = (1 <<  4),                  ///< Pin index 04 of each port group
+    Pin05 = (1 <<  5),                  ///< Pin index 05 of each port group
+    Pin06 = (1 <<  6),                  ///< Pin index 06 of each port group
+    Pin07 = (1 <<  7),                  ///< Pin index 07 of each port group
+    Pin08 = (1 <<  8),                  ///< Pin index 08 of each port group
+    Pin09 = (1 <<  9),                  ///< Pin index 09 of each port group
+    Pin10 = (1 << 10),                  ///< Pin index 10 of each port group
+    Pin11 = (1 << 11),                  ///< Pin index 11 of each port group
+    Pin12 = (1 << 12),                  ///< Pin index 12 of each port group
+    Pin13 = (1 << 13),                  ///< Pin index 13 of each port group
+    Pin14 = (1 << 14),                  ///< Pin index 14 of each port group
+    Pin15 = (1 << 15),                  ///< Pin index 15 of each port group
+    PinAll= 0xFFFF,                     ///< All pins selected
+}en_pin_t;
+
+/**
+ *******************************************************************************
+ ** \brief GPIO Pin read wait cycle enumeration
+ ******************************************************************************/
+typedef enum en_read_wait
+{
+    WaitCycle0  = 0,                    ///< no wait cycle, operation freq. lower than 42MHz
+    WaitCycle1  = 1,                    ///< one wait cycle, operation freq. @[42~84)MHz
+    WaitCycle2  = 2,                    ///< two wait cycles, operation freq. @[84~126)MHz
+    WaitCycle3  = 3,                    ///< three wait cycles, operation freq. @[126~200)MHz
+}en_read_wait_t;
+
+/**
+ *******************************************************************************
+ ** \brief GPIO Function enumeration
+ ******************************************************************************/
+typedef enum en_port_func
+{
+    Func_Gpio       = 0u,               ///< function set to gpio
+    Func_Fcmref     = 1u,               ///< function set to fcm reference
+    Func_Rtcout     = 1u,               ///< function set to rtc output
+    Func_Vcout      = 1u,               ///< function set to vc output
+    Func_Adtrg      = 1u,               ///< function set to adc trigger
+    Func_Mclkout    = 1u,               ///< function set to mclk output
+    Func_Tim4       = 2u,               ///< function set to timer4
+    Func_Tim6       = 3u,               ///< function set to timer6
+    Func_Tima0      = 4u,               ///< function set to timerA
+    Func_Tima1      = 5u,               ///< function set to timerA
+    Func_Tima2      = 6u,               ///< function set to timerA
+    Func_Emb        = 6u,               ///< function set to emb
+    Func_Usart_Ck   = 7u,               ///< function set to usart clk
+    Func_Spi_Nss    = 7u,               ///< function set to spi nss
+    Func_Qspi       = 7u,               ///< function set to qspi
+    Func_Key        = 8u,               ///< function set to key
+    Func_Sdio       = 9u,               ///< function set to sdio
+    Func_I2s        = 10u,              ///< function set to i2s
+    Func_UsbF       = 10u,              ///< function set to usb full speed
+    Func_Evnpt      = 14u,              ///< function set to event port
+    Func_Eventout   = 15u,              ///< function set to event out
+    Func_Usart1_Tx  = 32u,              ///< function set to usart tx of ch.1
+    Func_Usart3_Tx  = 32u,              ///< function set to usart tx of ch.3
+    Func_Usart1_Rx  = 33u,              ///< function set to usart rx of ch.1
+    Func_Usart3_Rx  = 33u,              ///< function set to usart rx of ch.3
+    Func_Usart1_Rts = 34u,              ///< function set to usart rts of ch.1
+    Func_Usart3_Rts = 34u,              ///< function set to usart rts of ch.3
+    Func_Usart1_Cts = 35u,              ///< function set to usart cts of ch.1
+    Func_Usart3_Cts = 35u,              ///< function set to usart cts of ch.3
+    Func_Usart2_Tx  = 36u,              ///< function set to usart tx of ch.2
+    Func_Usart4_Tx  = 36u,              ///< function set to usart tx of ch.4
+    Func_Usart2_Rx  = 37u,              ///< function set to usart rx of ch.2
+    Func_Usart4_Rx  = 37u,              ///< function set to usart rx of ch.4
+    Func_Usart2_Rts = 38u,              ///< function set to usart rts of ch.2
+    Func_Usart4_Rts = 38u,              ///< function set to usart rts of ch.4
+    Func_Usart2_Cts = 39u,              ///< function set to usart cts of ch.2
+    Func_Usart4_Cts = 39u,              ///< function set to usart cts of ch.4
+    Func_Spi1_Mosi  = 40u,              ///< function set to spi mosi of ch.1
+    Func_Spi3_Mosi  = 40u,              ///< function set to spi mosi of ch.3
+    Func_Spi1_Miso  = 41u,              ///< function set to spi miso of ch.1
+    Func_Spi3_Miso  = 41u,              ///< function set to spi miso of ch.3
+    Func_Spi1_Nss0  = 42u,              ///< function set to spi nss0 of ch.1
+    Func_Spi3_Nss0  = 42u,              ///< function set to spi nss0 of ch.3
+    Func_Spi1_Sck   = 43u,              ///< function set to spi sck of ch.1
+    Func_Spi3_Sck   = 43u,              ///< function set to spi sck of ch.3
+    Func_Spi2_Mosi  = 44u,              ///< function set to spi mosi of ch.2
+    Func_Spi4_Mosi  = 44u,              ///< function set to spi mosi of ch.2
+    Func_Spi2_Miso  = 45u,              ///< function set to spi miso of ch.4
+    Func_Spi4_Miso  = 45u,              ///< function set to spi miso of ch.4
+    Func_Spi2_Nss0  = 46u,              ///< function set to spi nss0 of ch.2
+    Func_Spi4_Nss0  = 46u,              ///< function set to spi nss0 of ch.4
+    Func_Spi2_Sck   = 47u,              ///< function set to spi sck of ch.2
+    Func_Spi4_Sck   = 47u,              ///< function set to spi sck of ch.4
+    Func_I2c1_Sda   = 48u,              ///< function set to i2c sda of ch.1
+    Func_I2c3_Sda   = 48u,              ///< function set to i2c sda of ch.3
+    Func_I2c1_Scl   = 49u,              ///< function set to i2c scl of ch.1
+    Func_I2c3_Scl   = 49u,              ///< function set to i2c scl of ch.3
+    Func_I2c2_Sda   = 50u,              ///< function set to i2c sda of ch.2
+    Func_Can1_Tx    = 50u,              ///< function set to can tx of ch.1
+    Func_I2c2_Scl   = 51u,              ///< function set to i2c scl of ch.2
+    Func_Can1_Rx    = 51u,              ///< function set to can rx of ch.1
+    Func_I2s1_Sd    = 52u,              ///< function set to i2s sd of ch.1
+    Func_I2s3_Sd    = 52u,              ///< function set to i2s sd of ch.3
+    Func_I2s1_Sdin  = 53u,              ///< function set to i2s sdin of ch.1
+    Func_I2s3_Sdin  = 53u,              ///< function set to i2s sdin of ch.3
+    Func_I2s1_Ws    = 54u,              ///< function set to i2s ws of ch.1
+    Func_I2s3_Ws    = 54u,              ///< function set to i2s ws of ch.3
+    Func_I2s1_Ck    = 55u,              ///< function set to i2s ck of ch.1
+    Func_I2s3_Ck    = 55u,              ///< function set to i2s ck of ch.3
+    Func_I2s2_Sd    = 56u,              ///< function set to i2s sd of ch.2
+    Func_I2s4_Sd    = 56u,              ///< function set to i2s sd of ch.4
+    Func_I2s2_Sdin  = 57u,              ///< function set to i2s sdin of ch.2
+    Func_I2s4_Sdin  = 57u,              ///< function set to i2s sdin of ch.4
+    Func_I2s2_Ws    = 58u,              ///< function set to i2s ws of ch.2
+    Func_I2s4_Ws    = 58u,              ///< function set to i2s ws of ch.4
+    Func_I2s2_Ck    = 59u,              ///< function set to i2s ck of ch.2
+    Func_I2s4_Ck    = 59u,              ///< function set to i2s ck of ch.4
+}en_port_func_t;
+
+/**
+ *******************************************************************************
+ ** \brief GPIO init structure definition
+ ******************************************************************************/
+typedef struct stc_port_init
+{
+    en_pin_mode_t           enPinMode;      ///< Set pin mode @ref en_pin_mode_t
+    en_functional_state_t   enLatch;        ///< Pin output latch enable
+    en_functional_state_t   enExInt;        ///< External int enable
+    en_functional_state_t   enInvert;       ///< Pin input/output invert enable
+    en_functional_state_t   enPullUp;       ///< Internal pull-up resistor enable
+    en_pin_drv_t            enPinDrv;       ///< Drive capacity setting @ref en_pin_drv_t
+    en_pin_o_type_t         enPinOType;     ///< Output mode setting @ref en_pin_o_type_t
+    en_functional_state_t   enPinSubFunc;   ///< Pin sub-function enable
+}stc_port_init_t;
+
+/**
+ *******************************************************************************
+ ** \brief GPIO public setting structure definition
+ ******************************************************************************/
+typedef struct stc_port_pub_set
+{
+    en_port_func_t          enSubFuncSel;   ///< Sub-function setting @ref en_port_func_t
+    en_read_wait_t          enReadWait;     ///< Read wait cycle setting @ref en_read_wait_t
+}stc_port_pub_set_t;
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+  Global function prototypes (definition in C source)
+ ******************************************************************************/
+extern en_result_t PORT_Init(en_port_t enPort, uint16_t u16Pin,                \
+                      const stc_port_init_t *pstcPortInit);
+extern en_result_t PORT_DeInit(void);
+extern void PORT_Unlock(void);
+extern void PORT_Lock(void);
+extern en_result_t PORT_DebugPortSetting(uint8_t u8DebugPort, en_functional_state_t enFunc);
+extern en_result_t PORT_PubSetting(const stc_port_pub_set_t *pstcPortPubSet);
+extern uint16_t PORT_GetData(en_port_t enPort);
+extern en_flag_status_t PORT_GetBit(en_port_t enPort, en_pin_t enPin);
+extern en_result_t PORT_SetPortData(en_port_t enPort, uint16_t u16Pin);
+extern en_result_t PORT_ResetPortData(en_port_t enPort, uint16_t u16Pin);
+extern en_result_t PORT_OE(en_port_t enPort, uint16_t u16Pin, en_functional_state_t enNewState);
+extern en_result_t PORT_SetBits(en_port_t enPort, uint16_t u16Pin);
+extern en_result_t PORT_ResetBits(en_port_t enPort, uint16_t u16Pin);
+extern en_result_t PORT_Toggle(en_port_t enPort, uint16_t u16Pin);
+extern en_result_t PORT_SetFunc(en_port_t enPort, uint16_t u16Pin,              \
+                        en_port_func_t enFuncSel, en_functional_state_t enSubFunc);
+extern en_result_t PORT_SetSubFunc(en_port_func_t enFuncSel);
+
+//@} // GpioGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_GPIO_ENABLE */
+
+#endif /* __HC32F460_GPIO_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,72 @@
+/*******************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_hash.h
+ **
+ ** A detailed description is available at
+ ** @link HashGroup Hash description @endlink
+ **
+ **   - 2018-10-18  CDT First version for Device Driver Library of Hash.
+ **
+ ******************************************************************************/
+#ifndef __HC32F460_HASH_H__
+#define __HC32F460_HASH_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_HASH_ENABLE == DDL_ON)
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup HashGroup Hash(HASH)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+void HASH_Init(void);
+void HASH_DeInit(void);
+en_result_t HASH_Start(const uint8_t *pu8SrcData,
+                       uint32_t u32SrcDataSize,
+                       uint8_t *pu8MsgDigest,
+                       uint32_t u32Timeout);
+
+//@} // HashGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_HASH_ENABLE */
+
+#endif /* __HC32F460_HASH_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,270 @@
+/*******************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_i2c.h
+ **
+ ** A detailed description is available at
+ ** @link I2cGroup Inter-Integrated Circuit(I2C) description @endlink
+ **
+ **   - 2018-10-16  CDT  First version for Device Driver Library of I2C.
+ **
+ ******************************************************************************/
+
+#ifndef __HC32F460_I2C_H__
+#define __HC32F460_I2C_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_I2C_ENABLE == DDL_ON)
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup I2cGroup Inter-Integrated Circuit (I2C)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ *******************************************************************************
+ ** \brief I2c configuration structure
+ **
+ ******************************************************************************/
+typedef struct stc_i2c_init
+{
+    uint32_t u32ClockDiv;    ///< I2C clock division for i2c source clock
+    uint32_t u32Baudrate;    ///< I2C baudrate config
+    uint32_t u32SclTime;     ///< The SCL rising and falling time, count of T(i2c source clock after frequency divider)
+}stc_i2c_init_t;
+
+/**
+ *******************************************************************************
+ ** \brief I2c SMBUS configuration structure
+ **
+ ******************************************************************************/
+typedef struct stc_i2c_smbus_init
+{
+    en_functional_state_t enHostAdrMatchFunc;     ///< SMBUS host address matching function
+    en_functional_state_t enDefaultAdrMatchFunc;  ///< SMBUS default address matching function
+    en_functional_state_t enAlarmAdrMatchFunc;    ///< SMBUS Alarm address matching function
+}stc_i2c_smbus_init_t;
+
+/**
+ *******************************************************************************
+ ** \brief I2c digital filter mode enumeration
+ **
+ ******************************************************************************/
+typedef enum en_i2c_digital_filter_mode
+{
+    Filter1BaseCycle = 0u,          ///< I2C digital filter ability 1 base cycle
+    Filter2BaseCycle = 1u,          ///< I2C digital filter ability 2 base cycle
+    Filter3BaseCycle = 2u,          ///< I2C digital filter ability 3 base cycle
+    Filter4BaseCycle = 3u,          ///< I2C digital filter ability 4 base cycle
+}en_i2c_digital_filter_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief I2c address bit enumeration
+ **
+ ******************************************************************************/
+typedef enum en_address_bit
+{
+    Adr7bit = 0u,       ///< I2C address length is 7 bits
+    Adr10bit = 1u,      ///< I2C address length is 10 bits
+}en_address_bit_t;
+
+/**
+ *******************************************************************************
+ ** \brief I2c transfer direction enumeration
+ **
+ ******************************************************************************/
+typedef enum en_trans_direction
+{
+    I2CDirTrans = 0u,
+    I2CDirReceive = 1u,
+}en_trans_direction_t;
+
+/**
+ *******************************************************************************
+ ** \brief I2c clock timeout switch enumeration
+ **
+ ******************************************************************************/
+typedef enum en_clock_timeout_switch
+{
+    TimeoutFunOff = 0u,  ///< I2C SCL pin time out function off
+    LowTimerOutOn = 3u,  ///< I2C SCL pin high level time out function on
+    HighTimeOutOn = 5u,  ///< I2C SCL pin low level time out function on
+    BothTimeOutOn = 7u,  ///< I2C SCL pin both(low and high) level time out function on
+}en_clock_timeout_switch_t;
+
+/**
+ *******************************************************************************
+ ** \brief I2c clock timeout initialize structure
+ **
+ ******************************************************************************/
+typedef struct stc_clock_timeout_init
+{
+    en_clock_timeout_switch_t   enClkTimeOutSwitch;  ///< I2C clock timeout function switch
+    uint16_t                    u16TimeOutHigh;      ///< I2C clock timeout period for High level
+    uint16_t                    u16TimeOutLow;       ///< I2C clock timeout period for Low level
+}stc_clock_timeout_init_t;
+
+/**
+ *******************************************************************************
+ ** \brief I2c ACK config enumeration
+ **
+ ******************************************************************************/
+typedef enum en_i2c_ack_config
+{
+    I2c_ACK = 0u,
+    I2c_NACK = 1u,
+}en_i2c_ack_config_t;
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/* define interrupt enable bit for I2C_CR2 register */
+#define I2C_CR2_STARTIE         (0x00000001ul)
+#define I2C_CR2_SLADDR0EN       (0x00000002ul)
+#define I2C_CR2_SLADDR1EN       (0x00000004ul)
+#define I2C_CR2_TENDIE          (0x00000008ul)
+#define I2C_CR2_STOPIE          (0x00000010ul)
+#define I2C_CR2_RFULLIE         (0x00000040ul)
+#define I2C_CR2_TEMPTYIE        (0x00000080ul)
+#define I2C_CR2_ARLOIE          (0x00000200ul)
+#define I2C_CR2_NACKIE          (0x00001000ul)
+#define I2C_CR2_TMOURIE         (0x00004000ul)
+#define I2C_CR2_GENCALLIE       (0x00100000ul)
+#define I2C_CR2_SMBDEFAULTIE    (0x00200000ul)
+#define I2C_CR2_SMBHOSTIE       (0x00400000ul)
+#define I2C_CR2_SMBALRTIE       (0x00800000ul)
+
+/* define status bit for I2C_SR register */
+#define I2C_SR_STARTF           (0x00000001ul)
+#define I2C_SR_SLADDR0F         (0x00000002ul)
+#define I2C_SR_SLADDR1F         (0x00000004ul)
+#define I2C_SR_TENDF            (0x00000008ul)
+#define I2C_SR_STOPF            (0x00000010ul)
+#define I2C_SR_RFULLF           (0x00000040ul)
+#define I2C_SR_TEMPTYF          (0x00000080ul)
+#define I2C_SR_ARLOF            (0x00000200ul)
+#define I2C_SR_ACKRF            (0x00000400ul)
+#define I2C_SR_NACKF            (0x00001000ul)
+#define I2C_SR_TMOUTF           (0x00004000ul)
+#define I2C_SR_MSL              (0x00010000ul)
+#define I2C_SR_BUSY             (0x00020000ul)
+#define I2C_SR_TRA              (0x00040000ul)
+#define I2C_SR_GENCALLF         (0x00100000ul)
+#define I2C_SR_SMBDEFAULTF      (0x00200000ul)
+#define I2C_SR_SMBHOSTF         (0x00400000ul)
+#define I2C_SR_SMBALRTF         (0x00800000ul)
+
+/* define status clear bit for I2C_CLR register*/
+#define I2C_CLR_STARTFCLR       (0x00000001ul)
+#define I2C_CLR_SLADDR0FCLR     (0x00000002ul)
+#define I2C_CLR_SLADDR1FCLR     (0x00000004ul)
+#define I2C_CLR_TENDFCLR        (0x00000008ul)
+#define I2C_CLR_STOPFCLR        (0x00000010ul)
+#define I2C_CLR_RFULLFCLR       (0x00000040ul)
+#define I2C_CLR_TEMPTYFCLR      (0x00000080ul)
+#define I2C_CLR_ARLOFCLR        (0x00000200ul)
+#define I2C_CLR_NACKFCLR        (0x00001000ul)
+#define I2C_CLR_TMOUTFCLR       (0x00004000ul)
+#define I2C_CLR_GENCALLFCLR     (0x00100000ul)
+#define I2C_CLR_SMBDEFAULTFCLR  (0x00200000ul)
+#define I2C_CLR_SMBHOSTFCLR     (0x00400000ul)
+#define I2C_CLR_SMBALRTFCLR     (0x00800000ul)
+#define I2C_CLR_MASK            (0x00F056DFul)
+
+/* I2C_Clock_Division I2C clock division */
+#define I2C_CLK_DIV1            (0ul)  /* I2c source clock/1 */
+#define I2C_CLK_DIV2            (1ul)  /* I2c source clock/2 */
+#define I2C_CLK_DIV4            (2ul)  /* I2c source clock/4 */
+#define I2C_CLK_DIV8            (3ul)  /* I2c source clock/8 */
+#define I2C_CLK_DIV16           (4ul)  /* I2c source clock/16 */
+#define I2C_CLK_DIV32           (5ul)  /* I2c source clock/32 */
+#define I2C_CLK_DIV64           (6ul)  /* I2c source clock/64 */
+#define I2C_CLK_DIV128          (7ul)  /* I2c source clock/128 */
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+  Global function prototypes (definition in C source)
+ ******************************************************************************/
+en_result_t I2C_BaudrateConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_init_t* pstcI2cInit, float32_t *pf32Error);
+en_result_t I2C_DeInit(M4_I2C_TypeDef* pstcI2Cx);
+en_result_t I2C_Init(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_init_t* pstcI2cInit, float32_t *pf32Error);
+void I2C_Cmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
+en_result_t I2C_SmbusConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_smbus_init_t* pstcI2C_SmbusInitStruct);
+void I2C_SmBusCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
+void I2C_SoftwareResetCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
+
+////////////////////////////////////////////////////////////////////////////////////////
+void I2C_DigitalFilterConfig(M4_I2C_TypeDef* pstcI2Cx, en_i2c_digital_filter_mode_t enDigiFilterMode);
+void I2C_DigitalFilterCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
+void I2C_AnalogFilterCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
+void I2C_GeneralCallCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
+void I2C_SlaveAdr0Config(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState, en_address_bit_t enAdrMode, uint32_t u32Adr);
+void I2C_SlaveAdr1Config(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState, en_address_bit_t enAdrMode, uint32_t u32Adr);
+en_result_t I2C_ClkTimeOutConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_clock_timeout_init_t* pstcTimoutInit);
+void I2C_IntCmd(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32IntEn, en_functional_state_t enNewState);
+void I2C_FastAckCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
+void I2C_BusWaitCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
+
+///////////////////////////////////////////////////////////////////////////////////////
+void I2C_GenerateStart(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
+void I2C_GenerateReStart(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
+void I2C_GenerateStop(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState);
+void I2C_WriteData(M4_I2C_TypeDef* pstcI2Cx, uint8_t u8Data);
+uint8_t I2C_ReadData(M4_I2C_TypeDef* pstcI2Cx);
+void I2C_AckConfig(M4_I2C_TypeDef* pstcI2Cx, en_i2c_ack_config_t u32AckConfig);
+en_flag_status_t I2C_GetStatus(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32StatusBit);
+void I2C_ClearStatus(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32StatusBit);
+
+/* High level functions for reference ********************************/
+en_result_t I2C_Start(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout);
+en_result_t I2C_Restart(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout);
+en_result_t I2C_TransAddr(M4_I2C_TypeDef* pstcI2Cx, uint8_t u8Addr, en_trans_direction_t enDir, uint32_t u32Timeout);
+en_result_t I2C_Trans10BitAddr(M4_I2C_TypeDef* pstcI2Cx, uint16_t u16Addr, en_trans_direction_t enDir, uint32_t u32Timeout);
+en_result_t I2C_TransData(M4_I2C_TypeDef* pstcI2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout);
+en_result_t I2C_ReceiveData(M4_I2C_TypeDef* pstcI2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout);
+en_result_t I2C_Stop(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout);
+en_result_t I2C_WaitStatus(const M4_I2C_TypeDef *pstcI2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout);
+en_result_t I2C_MasterDataReceiveAndStop(M4_I2C_TypeDef* pstcI2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout);
+
+//@} // I2cGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_I2C_ENABLE */
+
+#endif /* __HC32F460_I2C_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,206 @@
+/*******************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_i2s.h
+ **
+ ** A detailed description is available at
+ ** @link I2sGroup Inter-IC Sound Bus description @endlink
+ **
+ **   - 2018-10-28  CDT  First version for Device Driver Library of I2S.
+ **
+ ******************************************************************************/
+
+#ifndef __HC32F460_I2S_H__
+#define __HC32F460_I2S_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_I2S_ENABLE == DDL_ON)
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup I2sGroup Inter-IC Sound(I2S)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ *******************************************************************************
+ ** \brief I2S function
+ ******************************************************************************/
+typedef enum en_i2s_func
+{
+    TxEn = 0u,                              ///< Transfer enable function
+    TxIntEn = 1u,                           ///< Transfer interrupt enable function
+    RxEn = 2u,                              ///< receive enable function
+    RxIntEn = 3u,                           ///< receive interrupt enable function
+    ErrIntEn = 4u,                          ///< error interrupt enable function
+}en_i2s_func_t;
+
+
+/**
+ *******************************************************************************
+ ** \brief I2S status flag
+ ******************************************************************************/
+typedef enum en_i2s_std
+{
+    TxBufAlarmFlag = 0u,
+    RxBufAlarmFlag = 1u,
+    TxBufEmptFlag = 2u,
+    TxBufFullFlag = 3u,
+    RxBufEmptFlag = 4u,
+    RxBufFullFlag = 5u,
+}en_i2s_std_t;
+
+/**
+ *******************************************************************************
+ ** \brief I2S clr flag
+ ******************************************************************************/
+typedef enum en_i2s_err_flag
+{
+    ClrTxErrFlag = 0u,
+    ClrRxErrFlag = 1u,
+}en_i2s_err_flag_t;
+/**
+ *******************************************************************************
+ ** \brief I2S mode
+ ******************************************************************************/
+typedef enum en_i2s_mode
+{
+    I2sMaster = 0u,                     ///< I2S Master mode
+    I2sSlave = 1u,                      ///< I2S Slave mode
+}en_i2s_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief I2S full duplex mode
+ ******************************************************************************/
+typedef enum en_i2s_full_duplex_mode
+{
+    I2s_HalfDuplex = 0u,                 ///< I2S half duplex
+    I2s_FullDuplex = 1u,                 ///< I2S full duplex
+}en_i2s_full_duplex_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief I2S standard
+ ******************************************************************************/
+typedef enum en_i2s_standard
+{
+    Std_Philips = 0u,                   ///< I2S Philips standard
+    Std_MSBJust = 1u,                   ///< I2S MSB justified standart
+    Std_LSBJust = 2u,                   ///< I2S LSB justified standart
+    Std_PCM     = 3u,                   ///< I2S PCM standart
+}en_i2s_standard_t;
+
+/**
+ *******************************************************************************
+ ** \brief I2S channel data length
+ ******************************************************************************/
+typedef enum en_i2s_ch_len
+{
+    I2s_ChLen_16Bit = 0u,
+    I2s_ChLen_32Bit = 1u,
+}en_i2s_ch_len_t;
+
+/**
+ *******************************************************************************
+ ** \brief I2S data length
+ ******************************************************************************/
+typedef enum en_i2s_data_len
+{
+    I2s_DataLen_16Bit = 0u,
+    I2s_DataLen_24Bit = 1u,
+    I2s_DataLen_32Bit = 2u,
+}en_i2s_data_len_t;
+
+/**
+ *******************************************************************************
+ ** \brief I2S configuration structure
+ ******************************************************************************/
+typedef struct stc_i2s_config
+{
+    en_i2s_mode_t               enMode;              ///< I2S mode
+    en_i2s_full_duplex_mode_t   enFullDuplexMode;    ///< I2S full duplex mode
+    uint32_t                    u32I2sInterClkFreq;  ///< I2S internal clock frequency
+    en_i2s_standard_t           enStandrad;          ///< I2S standard
+    en_i2s_data_len_t           enDataBits;          ///< I2S data format, data bits
+    en_i2s_ch_len_t             enChanelLen;         ///< I2S channel length
+    en_functional_state_t       enMcoOutEn;          ///< I2S MCK output config
+    en_functional_state_t       enExckEn;            ///< I2S EXCK function config
+    uint32_t                    u32AudioFreq;        ///< I2S audio frequecy
+}stc_i2s_config_t;
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/* define audio frequency */
+#define I2S_AudioFreq_192k                          (192000ul)
+#define I2S_AudioFreq_96k                           (96000ul)
+#define I2S_AudioFreq_48k                           (48000ul)
+#define I2S_AudioFreq_44k                           (44100ul)
+#define I2S_AudioFreq_32k                           (32000ul)
+#define I2S_AudioFreq_22k                           (22050ul)
+#define I2S_AudioFreq_16k                           (16000ul)
+#define I2S_AudioFreq_11k                           (11025ul)
+#define I2S_AudioFreq_8k                            (8000ul)
+#define I2S_AudioFreq_Default                       (2ul)
+
+/* if use external clock open this define */
+#define I2S_EXTERNAL_CLOCK_VAL                      (12288000ul)
+
+/* 0,1 or 2 config for tx or tx buffer interrupt warning level */
+#define RXBUF_IRQ_WL                                (1ul)
+#define TXBUF_IRQ_WL                                (1ul)
+
+/* 0: Short frame synchronization; 1: Long frame synchronization */
+#define PCM_SYNC_FRAME                              (0ul)
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+  Global function prototypes (definition in C source)
+ ******************************************************************************/
+en_result_t I2s_Init(M4_I2S_TypeDef* pstcI2sReg, const stc_i2s_config_t* pstcI2sCfg);
+void I2S_SendData(M4_I2S_TypeDef* pstcI2sReg, uint32_t u32Data);
+uint32_t I2S_RevData(const M4_I2S_TypeDef* pstcI2sReg);
+void I2S_FuncCmd(M4_I2S_TypeDef* pstcI2sReg, en_i2s_func_t enFunc, en_functional_state_t enNewState);
+en_flag_status_t I2S_GetStatus(M4_I2S_TypeDef* pstcI2sReg, en_i2s_std_t enStd);
+en_flag_status_t I2S_GetErrFlag(M4_I2S_TypeDef* pstcI2sReg, en_i2s_err_flag_t enErrFlag);
+void I2S_ClrErrFlag(M4_I2S_TypeDef* pstcI2sReg, en_i2s_err_flag_t enErrFlag);
+en_result_t I2s_DeInit(M4_I2S_TypeDef* pstcI2sReg);
+
+//@} // I2sGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_I2S_ENABLE */
+
+#endif /* __HC32F460_I2S_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,406 @@
+/*******************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_icg.h
+ **
+ ** A detailed description is available at
+ ** @link IcgGroup Initialize configure description @endlink
+ **
+ **   - 2018-10-15  CDT  First version for Device Driver Library of ICG.
+ **
+ ******************************************************************************/
+#ifndef __HC32F460_ICG_H__
+#define __HC32F460_ICG_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_ICG_ENABLE == DDL_ON)
+
+#define	WATCH_DOG								1
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup IcgGroup Initialize Configure(ICG)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ *******************************************************************************
+ ** \brief SWDT running state after reset
+ ******************************************************************************/
+#define SWDT_AUTO_START_AFTER_RESET             ((uint16_t)0x0000)  ///< SWDT Auto Start after reset
+#define SWDT_STOP_AFTER_RESET                   ((uint16_t)0x0001)  ///< SWDT stop after reset
+
+/**
+ *******************************************************************************
+ ** \brief SWDT count underflow or refresh error trigger event type
+ ******************************************************************************/
+#define SWDT_INTERRUPT_REQUEST                  ((uint16_t)0x0000)  ///< WDT trigger interrupt request
+#define SWDT_RESET_REQUEST                      ((uint16_t)0x0002)  ///< WDT trigger reset request
+
+/**
+ *******************************************************************************
+ ** \brief SWDT count underflow cycle
+ ******************************************************************************/
+#define SWDT_COUNT_UNDERFLOW_CYCLE_256          ((uint16_t)0x0000)  ///< 256 clock cycle
+#define SWDT_COUNT_UNDERFLOW_CYCLE_4096         ((uint16_t)0x0004)  ///< 4096 clock cycle
+#define SWDT_COUNT_UNDERFLOW_CYCLE_16384        ((uint16_t)0x0008)  ///< 16384 clock cycle
+#define SWDT_COUNT_UNDERFLOW_CYCLE_65536        ((uint16_t)0x000C)  ///< 65536 clock cycle
+
+/**
+ *******************************************************************************
+ ** \brief SWDT count clock division
+ ******************************************************************************/
+#define SWDT_COUNT_SWDTCLK_DIV1                 ((uint16_t)0x0000)  ///< SWDTCLK
+#define SWDT_COUNT_SWDTCLK_DIV16                ((uint16_t)0x0040)  ///< SWDTCLK/16
+#define SWDT_COUNT_SWDTCLK_DIV32                ((uint16_t)0x0050)  ///< SWDTCLK/32
+#define SWDT_COUNT_SWDTCLK_DIV64                ((uint16_t)0x0060)  ///< SWDTCLK/64
+#define SWDT_COUNT_SWDTCLK_DIV128               ((uint16_t)0x0070)  ///< SWDTCLK/128
+#define SWDT_COUNT_SWDTCLK_DIV256               ((uint16_t)0x0080)  ///< SWDTCLK/256
+#define SWDT_COUNT_SWDTCLK_DIV2048              ((uint16_t)0x00B0)  ///< SWDTCLK/2048
+
+/**
+ *******************************************************************************
+ ** \brief SWDT allow refresh percent range
+ ******************************************************************************/
+#define SWDT_100PCT                             ((uint16_t)0x0000)  ///< 100%
+#define SWDT_0To25PCT                           ((uint16_t)0x0100)  ///< 0%~25%
+#define SWDT_25To50PCT                          ((uint16_t)0x0200)  ///< 25%~50%
+#define SWDT_0To50PCT                           ((uint16_t)0x0300)  ///< 0%~50%
+#define SWDT_50To75PCT                          ((uint16_t)0x0400)  ///< 50%~75%
+#define SWDT_0To25PCT_50To75PCT                 ((uint16_t)0x0500)  ///< 0%~25% & 50%~75%
+#define SWDT_25To75PCT                          ((uint16_t)0x0600)  ///< 25%~75%
+#define SWDT_0To75PCT                           ((uint16_t)0x0700)  ///< 0%~75%
+#define SWDT_75To100PCT                         ((uint16_t)0x0800)  ///< 75%~100%
+#define SWDT_0To25PCT_75To100PCT                ((uint16_t)0x0900)  ///< 0%~25% & 75%~100%
+#define SWDT_25To50PCT_75To100PCT               ((uint16_t)0x0A00)  ///< 25%~50% & 75%~100%
+#define SWDT_0To50PCT_75To100PCT                ((uint16_t)0x0B00)  ///< 0%~50% & 75%~100%
+#define SWDT_50To100PCT                         ((uint16_t)0x0C00)  ///< 50%~100%
+#define SWDT_0To25PCT_50To100PCT                ((uint16_t)0x0D00)  ///< 0%~25% & 50%~100%
+#define SWDT_25To100PCT                         ((uint16_t)0x0E00)  ///< 25%~100%
+#define SWDT_0To100PCT                          ((uint16_t)0x0F00)  ///< 0%~100%
+
+/**
+ *******************************************************************************
+ ** \brief SWDT count control in the sleep/stop mode
+ ******************************************************************************/
+#define SWDT_SPECIAL_MODE_COUNT_CONTINUE        ((uint16_t)0x0000)  ///< SWDT count continue in the sleep/stop mode
+#define SWDT_SPECIAL_MODE_COUNT_STOP            ((uint16_t)0x1000)  ///< SWDT count stop in the sleep/stop mode
+
+/**
+ *******************************************************************************
+ ** \brief WDT running state after reset
+ ******************************************************************************/
+#define WDT_AUTO_START_AFTER_RESET              ((uint16_t)0x0000)  ///< WDT Auto Start after reset
+#define WDT_STOP_AFTER_RESET                    ((uint16_t)0x0001)  ///< WDT stop after reset
+
+/**
+ *******************************************************************************
+ ** \brief WDT count underflow or refresh error trigger event type
+ ******************************************************************************/
+#define WDT_INTERRUPT_REQUEST                   ((uint16_t)0x0000)  ///< WDT trigger interrupt request
+#define WDT_RESET_REQUEST                       ((uint16_t)0x0002)  ///< WDT trigger reset request
+
+/**
+ *******************************************************************************
+ ** \brief WDT count underflow cycle
+ ******************************************************************************/
+#define WDT_COUNT_UNDERFLOW_CYCLE_256           ((uint16_t)0x0000)  ///< 256 clock cycle
+#define WDT_COUNT_UNDERFLOW_CYCLE_4096          ((uint16_t)0x0004)  ///< 4096 clock cycle
+#define WDT_COUNT_UNDERFLOW_CYCLE_16384         ((uint16_t)0x0008)  ///< 16384 clock cycle
+#define WDT_COUNT_UNDERFLOW_CYCLE_65536         ((uint16_t)0x000C)  ///< 65536 clock cycle
+
+/**
+ *******************************************************************************
+ ** \brief WDT count clock division
+ ******************************************************************************/
+#define WDT_COUNT_PCLK3_DIV4                    ((uint16_t)0x0020)  ///< PCLK3/4
+#define WDT_COUNT_PCLK3_DIV64                   ((uint16_t)0x0060)  ///< PCLK3/64
+#define WDT_COUNT_PCLK3_DIV128                  ((uint16_t)0x0070)  ///< PCLK3/128
+#define WDT_COUNT_PCLK3_DIV256                  ((uint16_t)0x0080)  ///< PCLK3/256
+#define WDT_COUNT_PCLK3_DIV512                  ((uint16_t)0x0090)  ///< PCLK3/512
+#define WDT_COUNT_PCLK3_DIV1024                 ((uint16_t)0x00A0)  ///< PCLK3/1024
+#define WDT_COUNT_PCLK3_DIV2048                 ((uint16_t)0x00B0)  ///< PCLK3/2048
+#define WDT_COUNT_PCLK3_DIV8192                 ((uint16_t)0x00D0)  ///< PCLK3/8192
+
+/**
+ *******************************************************************************
+ ** \brief WDT allow refresh percent range
+ ******************************************************************************/
+#define WDT_100PCT                              ((uint16_t)0x0000)  ///< 100%
+#define WDT_0To25PCT                            ((uint16_t)0x0100)  ///< 0%~25%
+#define WDT_25To50PCT                           ((uint16_t)0x0200)  ///< 25%~50%
+#define WDT_0To50PCT                            ((uint16_t)0x0300)  ///< 0%~50%
+#define WDT_50To75PCT                           ((uint16_t)0x0400)  ///< 50%~75%
+#define WDT_0To25PCT_50To75PCT                  ((uint16_t)0x0500)  ///< 0%~25% & 50%~75%
+#define WDT_25To75PCT                           ((uint16_t)0x0600)  ///< 25%~75%
+#define WDT_0To75PCT                            ((uint16_t)0x0700)  ///< 0%~75%
+#define WDT_75To100PCT                          ((uint16_t)0x0800)  ///< 75%~100%
+#define WDT_0To25PCT_75To100PCT                 ((uint16_t)0x0900)  ///< 0%~25% & 75%~100%
+#define WDT_25To50PCT_75To100PCT                ((uint16_t)0x0A00)  ///< 25%~50% & 75%~100%
+#define WDT_0To50PCT_75To100PCT                 ((uint16_t)0x0B00)  ///< 0%~50% & 75%~100%
+#define WDT_50To100PCT                          ((uint16_t)0x0C00)  ///< 50%~100%
+#define WDT_0To25PCT_50To100PCT                 ((uint16_t)0x0D00)  ///< 0%~25% & 50%~100%
+#define WDT_25To100PCT                          ((uint16_t)0x0E00)  ///< 25%~100%
+#define WDT_0To100PCT                           ((uint16_t)0x0F00)  ///< 0%~100%
+
+/**
+ *******************************************************************************
+ ** \brief WDT count control in the sleep mode
+ ******************************************************************************/
+#define WDT_SPECIAL_MODE_COUNT_CONTINUE         ((uint16_t)0x0000)  ///< WDT count continue in the sleep mode
+#define WDT_SPECIAL_MODE_COUNT_STOP             ((uint16_t)0x1000)  ///< WDT count stop in the sleep mode
+
+/**
+ *******************************************************************************
+ ** \brief HRC frequency select
+ ******************************************************************************/
+#define HRC_FREQUENCY_20MHZ                     ((uint16_t)0x0000)  ///< HRC frequency 20MHZ
+#define HRC_FREQUENCY_16MHZ                     ((uint16_t)0x0001)  ///< HRC frequency 16MHZ
+
+/**
+ *******************************************************************************
+ ** \brief HRC oscillation state control
+ ******************************************************************************/
+#define HRC_OSCILLATION_START                   ((uint16_t)0x0000)  ///< HRC oscillation start
+#define HRC_OSCILLATION_STOP                    ((uint16_t)0x0100)  ///< HRC oscillation stop
+
+/**
+ *******************************************************************************
+ ** \brief VDU0 threshold voltage select
+ ******************************************************************************/
+#define VDU0_VOLTAGE_THRESHOLD_1P5              ((uint8_t)0x00)   ///< VDU0 voltage threshold 1.9V
+#define VDU0_VOLTAGE_THRESHOLD_2P0              ((uint8_t)0x01)   ///< VDU0 voltage threshold 2.0V
+#define VDU0_VOLTAGE_THRESHOLD_2P1              ((uint8_t)0x02)   ///< VDU0 voltage threshold 2.1V
+#define VDU0_VOLTAGE_THRESHOLD_2P3              ((uint8_t)0x03)   ///< VDU0 voltage threshold 2.3V
+
+/**
+ *******************************************************************************
+ ** \brief VDU0 running state after reset
+ ******************************************************************************/
+#define VDU0_START_AFTER_RESET                  ((uint8_t)0x00)   ///< VDU0 start after reset
+#define VDU0_STOP_AFTER_RESET                   ((uint8_t)0x04)   ///< VDU0 stop after reset
+
+/**
+ *******************************************************************************
+ ** \brief NMI pin filter sample clock division
+ ******************************************************************************/
+#define NMI_PIN_FILTER_PCLK3_DIV1               ((uint8_t)0x00)   ///< PCLK3
+#define NMI_PIN_FILTER_PCLK3_DIV8               ((uint8_t)0x04)   ///< PCLK3/8
+#define NMI_PIN_FILTER_PCLK3_DIV32              ((uint8_t)0x08)   ///< PCLK3/32
+#define NMI_PIN_FILTER_PCLK3_DIV64              ((uint8_t)0x0C)   ///< PCLK3/64
+
+/**
+ *******************************************************************************
+ ** \brief NMI pin trigger edge type
+ ******************************************************************************/
+#define NMI_PIN_TRIGGER_EDGE_FALLING            ((uint8_t)0x00)   ///< Falling edge trigger
+#define NMI_PIN_TRIGGER_EDGE_RISING             ((uint8_t)0x10)   ///< Rising edge trigger
+
+/**
+ *******************************************************************************
+ ** \brief Enable or disable NMI pin interrupt request
+ ******************************************************************************/
+#define NMI_PIN_IRQ_DISABLE                     ((uint8_t)0x00)   ///< Disable NMI pin interrupt request
+#define NMI_PIN_IRQ_ENABLE                      ((uint8_t)0x20)   ///< Enable NMI pin interrupt request
+
+/**
+ *******************************************************************************
+ ** \brief Enable or disable NMI digital filter function
+ ******************************************************************************/
+#define NMI_DIGITAL_FILTER_DISABLE              ((uint8_t)0x00)   ///< Disable NMI digital filter
+#define NMI_DIGITAL_FILTER_ENABLE               ((uint8_t)0x40)   ///< Enable NMI digital filter
+
+/**
+ *******************************************************************************
+ ** \brief Enable or disable NMI pin ICG function
+ ******************************************************************************/
+#define NMI_PIN_ICG_FUNCTION_DISABLE            ((uint8_t)0x80)   ///< Disable NMI pin ICG function
+#define NMI_PIN_ICG_FUNCTION_ENABLE             ((uint8_t)0x00)   ///< Enable NMI pin ICG function
+
+/**
+ *******************************************************************************
+ ** \brief ICG start configure function on/off
+ ******************************************************************************/
+#ifndef ICG_FUNCTION_ON
+#define ICG_FUNCTION_ON                         (1u)
+#endif
+
+#ifndef ICG_FUNCTION_OFF
+#define ICG_FUNCTION_OFF                        (0u)
+#endif
+
+/**
+ *******************************************************************************
+ ** \brief SWDT hardware start configuration
+ ******************************************************************************/
+/*!< Enable or disable SWDT hardware start */
+#if (WATCH_DOG == 1)
+#define ICG0_SWDT_HARDWARE_START                (ICG_FUNCTION_ON)
+#else
+#define ICG0_SWDT_HARDWARE_START                (ICG_FUNCTION_OFF)
+#endif
+
+/*!< SWDT register config */
+#define ICG0_SWDT_AUTS                          (SWDT_AUTO_START_AFTER_RESET)
+#define ICG0_SWDT_ITS                           (SWDT_RESET_REQUEST)
+#define ICG0_SWDT_PERI                          (SWDT_COUNT_UNDERFLOW_CYCLE_256)		//  λʱ  0.8  
+#define ICG0_SWDT_CKS                           (SWDT_COUNT_SWDTCLK_DIV128)
+#define ICG0_SWDT_WDPT                          (SWDT_0To100PCT)
+#define ICG0_SWDT_SLTPOFF                       (SWDT_SPECIAL_MODE_COUNT_CONTINUE)
+
+/*!< SWDT register config value */
+#if ICG0_SWDT_HARDWARE_START == ICG_FUNCTION_ON
+#define ICG0_SWDT_REG_CONFIG                    (ICG0_SWDT_AUTS | ICG0_SWDT_ITS | ICG0_SWDT_PERI | \
+                                                 ICG0_SWDT_CKS | ICG0_SWDT_WDPT | ICG0_SWDT_SLTPOFF)
+#else
+#define ICG0_SWDT_REG_CONFIG                    ((uint16_t)0xFFFF)
+#endif
+
+/**
+ *******************************************************************************
+ ** \brief WDT hardware start configuration
+ ******************************************************************************/
+/*!< Enable or disable WDT hardware start */
+#define ICG0_WDT_HARDWARE_START                 (ICG_FUNCTION_OFF)
+
+/*!< WDT register config */
+#define ICG0_WDT_AUTS                           (WDT_STOP_AFTER_RESET)
+#define ICG0_WDT_ITS                            (WDT_RESET_REQUEST)
+#define ICG0_WDT_PERI                           (WDT_COUNT_UNDERFLOW_CYCLE_16384)
+#define ICG0_WDT_CKS                            (WDT_COUNT_PCLK3_DIV8192)
+#define ICG0_WDT_WDPT                           (WDT_0To100PCT)
+#define ICG0_WDT_SLPOFF                         (WDT_SPECIAL_MODE_COUNT_STOP)
+
+/*!< WDT register config value */
+#if ICG0_WDT_HARDWARE_START == ICG_FUNCTION_ON
+#define ICG0_WDT_REG_CONFIG                     (ICG0_WDT_AUTS | ICG0_WDT_ITS | ICG0_WDT_PERI | \
+                                                 ICG0_WDT_CKS | ICG0_WDT_WDPT | ICG0_WDT_SLPOFF)
+#else
+#define ICG0_WDT_REG_CONFIG                     ((uint16_t)0xFFFF)
+#endif
+
+/**
+ *******************************************************************************
+ ** \brief HRC hardware start configuration
+ ******************************************************************************/
+/*!< Enable or disable HRC hardware start */
+#define ICG1_HRC_HARDWARE_START                 (ICG_FUNCTION_ON)
+
+/*!< HRC register config */
+#define ICG1_HRC_FREQSEL                        (HRC_FREQUENCY_16MHZ)
+#define ICG1_HRC_STOP                           (HRC_OSCILLATION_START)
+
+/*!< HRC register config value */
+#if ICG1_HRC_HARDWARE_START == ICG_FUNCTION_ON
+#define ICG1_HRC_REG_CONFIG                     (ICG1_HRC_FREQSEL | ICG1_HRC_STOP)
+#else
+#define ICG1_HRC_REG_CONFIG                     ((uint16_t)0xFFFF)
+#endif
+
+/**
+ *******************************************************************************
+ ** \brief VDU0 hardware start configuration
+ ******************************************************************************/
+/*!< Enable or disable VDU0 hardware start */
+#define ICG1_VDU0_HARDWARE_START                (ICG_FUNCTION_OFF)
+
+/*!< VDU0 register config */
+#define ICG1_VDU0_BOR_LEV                       (VDU0_VOLTAGE_THRESHOLD_2P3)
+#define ICG1_VDU0_BORDIS                        (VDU0_STOP_AFTER_RESET)
+
+/*!< VDU0 register config value */
+#if ICG1_VDU0_HARDWARE_START == ICG_FUNCTION_ON
+#define ICG1_VDU0_REG_CONFIG                    (ICG1_VDU0_BOR_LEV | ICG1_VDU0_BORDIS)
+#else
+#define ICG1_VDU0_REG_CONFIG                    ((uint8_t)0xFF)
+#endif
+
+/**
+ *******************************************************************************
+ ** \brief NMI hardware start configuration
+ ******************************************************************************/
+/*!< Enable or disable NMI hardware start */
+#define ICG1_NMI_HARDWARE_START                 (ICG_FUNCTION_OFF)	
+
+/*!< NMI register config */
+#define ICG1_NMI_SMPCLK                         (NMI_PIN_FILTER_PCLK3_DIV1)
+#define ICG1_NMI_TRG                            (NMI_PIN_TRIGGER_EDGE_RISING)
+#define ICG1_NMI_IMR                            (NMI_PIN_IRQ_DISABLE)
+#define ICG1_NMI_NFEN                           (NMI_DIGITAL_FILTER_DISABLE)
+#define ICG1_NMI_ICGENA                         (NMI_PIN_ICG_FUNCTION_DISABLE)
+
+/*!< NMI register config value */
+#if ICG1_NMI_HARDWARE_START == ICG_FUNCTION_ON
+#define ICG1_NMI_REG_CONFIG                     (ICG1_NMI_SMPCLK | ICG1_NMI_TRG | \
+                                                 ICG1_NMI_IMR | ICG1_NMI_NFEN | ICG1_NMI_ICGENA)
+#else
+#define ICG1_NMI_REG_CONFIG                     ((uint8_t)0xFF)
+#endif
+
+/**
+ *******************************************************************************
+ ** \brief ICG registers configuration
+ ******************************************************************************/
+/*!< ICG0 register value */
+#define ICG0_REGISTER_CONSTANT                  (((uint32_t)ICG0_WDT_REG_CONFIG << 16)  | \
+                                                 ((uint32_t)ICG0_SWDT_REG_CONFIG)       | \
+                                                 ((uint32_t)0xE000E000ul))
+/*!< ICG1 register value */
+#define ICG1_REGISTER_CONSTANT                  (((uint32_t)ICG1_NMI_REG_CONFIG << 24)  | \
+                                                 ((uint32_t)ICG1_VDU0_REG_CONFIG << 16) | \
+                                                 ((uint32_t)ICG1_HRC_REG_CONFIG)        | \
+                                                 ((uint32_t)0x03F8FEFEul))
+/*!< ICG2~7 register reserved value */
+#define ICG2_REGISTER_CONSTANT                  ((uint32_t)0xFFFFFFFFul)
+#define ICG3_REGISTER_CONSTANT                  ((uint32_t)0xFFFFFFFFul)
+#define ICG4_REGISTER_CONSTANT                  ((uint32_t)0xFFFFFFFFul)
+#define ICG5_REGISTER_CONSTANT                  ((uint32_t)0xFFFFFFFFul)
+#define ICG6_REGISTER_CONSTANT                  ((uint32_t)0xFFFFFFFFul)
+#define ICG7_REGISTER_CONSTANT                  ((uint32_t)0xFFFFFFFFul)
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+  Global function prototypes (definition in C source)
+ ******************************************************************************/
+
+//@} // IcgGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_ICG_ENABLE */
+
+#endif /* __HC32F460_ICG_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,542 @@
+/*******************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_interrupts.h
+ **
+ ** A detailed description is available at
+ ** @link InterruptGroup Interrupt description @endlink
+ **
+ **   - 2018-10-12 CDT First version for Device Driver Library of interrupt.
+ **
+ ******************************************************************************/
+#ifndef __HC32F460_INTERRUPTS_H___
+#define __HC32F460_INTERRUPTS_H___
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_INTERRUPTS_ENABLE == DDL_ON)
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup InterruptGroup Interrupt
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ *******************************************************************************
+ ** \brief IRQ registration structure definition
+ ******************************************************************************/
+typedef struct stc_irq_regi_conf
+{
+    en_int_src_t enIntSrc;
+    IRQn_Type enIRQn;
+    func_ptr_t pfnCallback;
+}stc_irq_regi_conf_t;
+
+/**
+ *******************************************************************************
+ ** \brief stop mode interrupt wakeup source enumeration
+ ******************************************************************************/
+typedef enum en_int_wkup_src
+{
+    Extint0WU           =   1u << 0,
+    Extint1WU           =   1u << 1,
+    Extint2WU           =   1u << 2,
+    Extint3WU           =   1u << 3,
+    Extint4WU           =   1u << 4,
+    Extint5WU           =   1u << 5,
+    Extint6WU           =   1u << 6,
+    Extint7WU           =   1u << 7,
+    Extint8WU           =   1u << 8,
+    Extint9WU           =   1u << 9,
+    Extint10WU          =   1u << 10,
+    Extint11WU          =   1u << 11,
+    Extint12WU          =   1u << 12,
+    Extint13WU          =   1u << 13,
+    Extint14WU          =   1u << 14,
+    Extint15WU          =   1u << 15,
+    SwdtWU              =   1u << 16,
+    Vdu1WU              =   1u << 17,
+    Vdu2WU              =   1u << 18,
+    CmpWU               =   1u << 19,
+    WakeupTimerWU       =   1u << 20,
+    RtcAlarmWU          =   1u << 21,
+    RtcPeriodWU         =   1u << 22,
+    Timer0WU            =   1u << 23,
+    Usart1RxWU          =   1u << 25,
+}en_int_wkup_src_t;
+
+/**
+ *******************************************************************************
+ ** \brief event enumeration
+ ******************************************************************************/
+typedef enum en_evt
+{
+    Event0              =   1u << 0,
+    Event1              =   1u << 1,
+    Event2              =   1u << 2,
+    Event3              =   1u << 3,
+    Event4              =   1u << 4,
+    Event5              =   1u << 5,
+    Event6              =   1u << 6,
+    Event7              =   1u << 7,
+    Event8              =   1u << 8,
+    Event9              =   1u << 9,
+    Event10             =   1u << 10,
+    Event11             =   1u << 11,
+    Event12             =   1u << 12,
+    Event13             =   1u << 13,
+    Event14             =   1u << 14,
+    Event15             =   1u << 15,
+    Event16             =   1u << 16,
+    Event17             =   1u << 17,
+    Event18             =   1u << 18,
+    Event19             =   1u << 19,
+    Event20             =   1u << 20,
+    Event21             =   1u << 21,
+    Event22             =   1u << 22,
+    Event23             =   1u << 23,
+    Event24             =   1u << 24,
+    Event25             =   1u << 25,
+    Event26             =   1u << 26,
+    Event27             =   1u << 27,
+    Event28             =   1u << 28,
+    Event29             =   1u << 29,
+    Event30             =   1u << 30,
+    Event31             =   1u << 31,
+}en_evt_t;
+
+/**
+ *******************************************************************************
+ ** \brief interrupt enumeration
+ ******************************************************************************/
+typedef enum en_int
+{
+    Int0                =   1u << 0,
+    Int1                =   1u << 1,
+    Int2                =   1u << 2,
+    Int3                =   1u << 3,
+    Int4                =   1u << 4,
+    Int5                =   1u << 5,
+    Int6                =   1u << 6,
+    Int7                =   1u << 7,
+    Int8                =   1u << 8,
+    Int9                =   1u << 9,
+    Int10               =   1u << 10,
+    Int11               =   1u << 11,
+    Int12               =   1u << 12,
+    Int13               =   1u << 13,
+    Int14               =   1u << 14,
+    Int15               =   1u << 15,
+    Int16               =   1u << 16,
+    Int17               =   1u << 17,
+    Int18               =   1u << 18,
+    Int19               =   1u << 19,
+    Int20               =   1u << 20,
+    Int21               =   1u << 21,
+    Int22               =   1u << 22,
+    Int23               =   1u << 23,
+    Int24               =   1u << 24,
+    Int25               =   1u << 25,
+    Int26               =   1u << 26,
+    Int27               =   1u << 27,
+    Int28               =   1u << 28,
+    Int29               =   1u << 29,
+    Int30               =   1u << 30,
+    Int31               =   1u << 31,
+}en_int_t;
+
+
+/*! Bit mask definition*/
+#define     BIT_MASK_00                 (1ul << 0)
+#define     BIT_MASK_01                 (1ul << 1)
+#define     BIT_MASK_02                 (1ul << 2)
+#define     BIT_MASK_03                 (1ul << 3)
+#define     BIT_MASK_04                 (1ul << 4)
+#define     BIT_MASK_05                 (1ul << 5)
+#define     BIT_MASK_06                 (1ul << 6)
+#define     BIT_MASK_07                 (1ul << 7)
+#define     BIT_MASK_08                 (1ul << 8)
+#define     BIT_MASK_09                 (1ul << 9)
+#define     BIT_MASK_10                 (1ul << 10)
+#define     BIT_MASK_11                 (1ul << 11)
+#define     BIT_MASK_12                 (1ul << 12)
+#define     BIT_MASK_13                 (1ul << 13)
+#define     BIT_MASK_14                 (1ul << 14)
+#define     BIT_MASK_15                 (1ul << 15)
+#define     BIT_MASK_16                 (1ul << 16)
+#define     BIT_MASK_17                 (1ul << 17)
+#define     BIT_MASK_18                 (1ul << 18)
+#define     BIT_MASK_19                 (1ul << 19)
+#define     BIT_MASK_20                 (1ul << 20)
+#define     BIT_MASK_21                 (1ul << 21)
+#define     BIT_MASK_22                 (1ul << 22)
+#define     BIT_MASK_23                 (1ul << 23)
+#define     BIT_MASK_24                 (1ul << 24)
+#define     BIT_MASK_25                 (1ul << 25)
+#define     BIT_MASK_26                 (1ul << 26)
+#define     BIT_MASK_27                 (1ul << 27)
+#define     BIT_MASK_28                 (1ul << 28)
+#define     BIT_MASK_29                 (1ul << 29)
+#define     BIT_MASK_30                 (1ul << 30)
+#define     BIT_MASK_31                 (1ul << 31)
+
+/*! Default Priority for IRQ, Possible values are 0 (high priority) to 15 (low priority) */
+#define     DDL_IRQ_PRIORITY_DEFAULT    15u
+
+/*! Interrupt priority level 00 ~ 15*/
+#define     DDL_IRQ_PRIORITY_00         (0u)
+#define     DDL_IRQ_PRIORITY_01         (1u)
+#define     DDL_IRQ_PRIORITY_02         (2u)
+#define     DDL_IRQ_PRIORITY_03         (3u)
+#define     DDL_IRQ_PRIORITY_04         (4u)
+#define     DDL_IRQ_PRIORITY_05         (5u)
+#define     DDL_IRQ_PRIORITY_06         (6u)
+#define     DDL_IRQ_PRIORITY_07         (7u)
+#define     DDL_IRQ_PRIORITY_08         (8u)
+#define     DDL_IRQ_PRIORITY_09         (9u)
+#define     DDL_IRQ_PRIORITY_10         (10u)
+#define     DDL_IRQ_PRIORITY_11         (11u)
+#define     DDL_IRQ_PRIORITY_12         (12u)
+#define     DDL_IRQ_PRIORITY_13         (13u)
+#define     DDL_IRQ_PRIORITY_14         (14u)
+#define     DDL_IRQ_PRIORITY_15         (15u)
+
+/**
+ *******************************************************************************
+ ** \brief AOS software trigger function
+ **
+ ******************************************************************************/
+__STATIC_INLINE void AOS_SW_Trigger(void)
+{
+    bM4_AOS_INT_SFTTRG_STRG = 1u;
+}
+
+/**
+ *******************************************************************************
+ ** \brief AOS common trigger source 1 config.
+ **
+ ******************************************************************************/
+__STATIC_INLINE void AOS_COM_Trigger1(en_event_src_t enTrig)
+{
+    M4_AOS->COMTRG1 = enTrig;
+}
+
+/**
+ *******************************************************************************
+ ** \brief AOS common trigger source 2 config.
+ **
+ ******************************************************************************/
+__STATIC_INLINE void AOS_COM_Trigger2(en_event_src_t enTrig)
+{
+    M4_AOS->COMTRG2 = enTrig;
+}
+
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+extern en_result_t enIrqRegistration(const stc_irq_regi_conf_t *pstcIrqRegiConf);
+extern en_result_t enIrqResign(IRQn_Type enIRQn);
+extern en_result_t enShareIrqEnable(en_int_src_t enIntSrc);
+extern en_result_t enShareIrqDisable(en_int_src_t enIntSrc);
+extern en_result_t enIntWakeupEnable(uint32_t u32WakeupSrc);
+extern en_result_t enIntWakeupDisable(uint32_t u32WakeupSrc);
+extern en_result_t enEventEnable(uint32_t u32Event);
+extern en_result_t enEventDisable(uint32_t u32Event);
+extern en_result_t enIntEnable(uint32_t u32Int);
+extern en_result_t enIntDisable(uint32_t u32Int);
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+__WEAKDEF void NMI_IrqHandler(void);
+__WEAKDEF void HardFault_IrqHandler(void);
+__WEAKDEF void MemManage_IrqHandler(void);
+__WEAKDEF void BusFault_IrqHandler(void);
+__WEAKDEF void UsageFault_IrqHandler(void);
+__WEAKDEF void SVC_IrqHandler(void);
+__WEAKDEF void DebugMon_IrqHandler(void);
+__WEAKDEF void PendSV_IrqHandler(void);
+__WEAKDEF void SysTick_IrqHandler(void);
+
+__WEAKDEF void Extint00_IrqHandler(void);
+__WEAKDEF void Extint01_IrqHandler(void);
+__WEAKDEF void Extint02_IrqHandler(void);
+__WEAKDEF void Extint03_IrqHandler(void);
+__WEAKDEF void Extint04_IrqHandler(void);
+__WEAKDEF void Extint05_IrqHandler(void);
+__WEAKDEF void Extint06_IrqHandler(void);
+__WEAKDEF void Extint07_IrqHandler(void);
+__WEAKDEF void Extint08_IrqHandler(void);
+__WEAKDEF void Extint09_IrqHandler(void);
+__WEAKDEF void Extint10_IrqHandler(void);
+__WEAKDEF void Extint11_IrqHandler(void);
+__WEAKDEF void Extint12_IrqHandler(void);
+__WEAKDEF void Extint13_IrqHandler(void);
+__WEAKDEF void Extint14_IrqHandler(void);
+__WEAKDEF void Extint15_IrqHandler(void);
+
+__WEAKDEF void Dma1Tc0_IrqHandler(void);
+__WEAKDEF void Dma1Tc1_IrqHandler(void);
+__WEAKDEF void Dma1Tc2_IrqHandler(void);
+__WEAKDEF void Dma1Tc3_IrqHandler(void);
+__WEAKDEF void Dma2Tc0_IrqHandler(void);
+__WEAKDEF void Dma2Tc1_IrqHandler(void);
+__WEAKDEF void Dma2Tc2_IrqHandler(void);
+__WEAKDEF void Dma2Tc3_IrqHandler(void);
+__WEAKDEF void Dma1Btc0_IrqHandler(void);
+__WEAKDEF void Dma1Btc1_IrqHandler(void);
+__WEAKDEF void Dma1Btc2_IrqHandler(void);
+__WEAKDEF void Dma1Btc3_IrqHandler(void);
+__WEAKDEF void Dma2Btc0_IrqHandler(void);
+__WEAKDEF void Dma2Btc1_IrqHandler(void);
+__WEAKDEF void Dma2Btc2_IrqHandler(void);
+__WEAKDEF void Dma2Btc3_IrqHandler(void);
+__WEAKDEF void Dma1Err0_IrqHandler(void);
+__WEAKDEF void Dma1Err1_IrqHandler(void);
+__WEAKDEF void Dma1Err2_IrqHandler(void);
+__WEAKDEF void Dma1Err3_IrqHandler(void);
+__WEAKDEF void Dma2Err0_IrqHandler(void);
+__WEAKDEF void Dma2Err1_IrqHandler(void);
+__WEAKDEF void Dma2Err2_IrqHandler(void);
+__WEAKDEF void Dma2Err3_IrqHandler(void);
+
+__WEAKDEF void EfmPgmEraseErr_IrqHandler(void);
+__WEAKDEF void EfmColErr_IrqHandler(void);
+__WEAKDEF void EfmOpEnd_IrqHandler(void);
+__WEAKDEF void QspiInt_IrqHandler(void);
+__WEAKDEF void Dcu1_IrqHandler(void);
+__WEAKDEF void Dcu2_IrqHandler(void);
+__WEAKDEF void Dcu3_IrqHandler(void);
+__WEAKDEF void Dcu4_IrqHandler(void);
+
+__WEAKDEF void Timer01GCMA_IrqHandler(void);
+__WEAKDEF void Timer01GCMB_IrqHandler(void);
+__WEAKDEF void Timer02GCMA_IrqHandler(void);
+__WEAKDEF void Timer02GCMB_IrqHandler(void);
+
+__WEAKDEF void MainOscStop_IrqHandler(void);
+__WEAKDEF void WakeupTimer_IrqHandler(void);
+__WEAKDEF void Swdt_IrqHandler(void);
+
+__WEAKDEF void Timer61GCMA_IrqHandler(void);
+__WEAKDEF void Timer61GCMB_IrqHandler(void);
+__WEAKDEF void Timer61GCMC_IrqHandler(void);
+__WEAKDEF void Timer61GCMD_IrqHandler(void);
+__WEAKDEF void Timer61GCME_IrqHandler(void);
+__WEAKDEF void Timer61GCMF_IrqHandler(void);
+__WEAKDEF void Timer61GOV_IrqHandler(void);
+__WEAKDEF void Timer61GUD_IrqHandler(void);
+__WEAKDEF void Timer61GDT_IrqHandler(void);
+__WEAKDEF void Timer61SCMA_IrqHandler(void);
+__WEAKDEF void Timer61SCMB_IrqHandler(void);
+
+__WEAKDEF void Timer62GCMA_IrqHandler(void);
+__WEAKDEF void Timer62GCMB_IrqHandler(void);
+__WEAKDEF void Timer62GCMC_IrqHandler(void);
+__WEAKDEF void Timer62GCMD_IrqHandler(void);
+__WEAKDEF void Timer62GCME_IrqHandler(void);
+__WEAKDEF void Timer62GCMF_IrqHandler(void);
+__WEAKDEF void Timer62GOV_IrqHandler(void);
+__WEAKDEF void Timer62GUD_IrqHandler(void);
+__WEAKDEF void Timer62GDT_IrqHandler(void);
+__WEAKDEF void Timer62SCMA_IrqHandler(void);
+__WEAKDEF void Timer62SCMB_IrqHandler(void);
+
+__WEAKDEF void Timer63GCMA_IrqHandler(void);
+__WEAKDEF void Timer63GCMB_IrqHandler(void);
+__WEAKDEF void Timer63GCMC_IrqHandler(void);
+__WEAKDEF void Timer63GCMD_IrqHandler(void);
+__WEAKDEF void Timer63GCME_IrqHandler(void);
+__WEAKDEF void Timer63GCMF_IrqHandler(void);
+__WEAKDEF void Timer63GOV_IrqHandler(void);
+__WEAKDEF void Timer63GUD_IrqHandler(void);
+__WEAKDEF void Timer63GDT_IrqHandler(void);
+__WEAKDEF void Timer63SCMA_IrqHandler(void);
+__WEAKDEF void Timer63SCMB_IrqHandler(void);
+
+__WEAKDEF void TimerA1OV_IrqHandler(void);
+__WEAKDEF void TimerA1UD_IrqHandler(void);
+__WEAKDEF void TimerA1CMP_IrqHandler(void);
+__WEAKDEF void TimerA2OV_IrqHandler(void);
+__WEAKDEF void TimerA2UD_IrqHandler(void);
+__WEAKDEF void TimerA2CMP_IrqHandler(void);
+__WEAKDEF void TimerA3OV_IrqHandler(void);
+__WEAKDEF void TimerA3UD_IrqHandler(void);
+__WEAKDEF void TimerA3CMP_IrqHandler(void);
+__WEAKDEF void TimerA4OV_IrqHandler(void);
+__WEAKDEF void TimerA4UD_IrqHandler(void);
+__WEAKDEF void TimerA4CMP_IrqHandler(void);
+__WEAKDEF void TimerA5OV_IrqHandler(void);
+__WEAKDEF void TimerA5UD_IrqHandler(void);
+__WEAKDEF void TimerA5CMP_IrqHandler(void);
+__WEAKDEF void TimerA6OV_IrqHandler(void);
+__WEAKDEF void TimerA6UD_IrqHandler(void);
+__WEAKDEF void TimerA6CMP_IrqHandler(void);
+
+__WEAKDEF void UsbGlobal_IrqHandler(void);
+
+__WEAKDEF void Usart1RxErr_IrqHandler(void);
+__WEAKDEF void Usart1RxEnd_IrqHandler(void);
+__WEAKDEF void Usart1TxEmpty_IrqHandler(void);
+__WEAKDEF void Usart1TxEnd_IrqHandler(void);
+__WEAKDEF void Usart1RxTO_IrqHandler(void);
+__WEAKDEF void Usart2RxErr_IrqHandler(void);
+__WEAKDEF void Usart2RxEnd_IrqHandler(void);
+__WEAKDEF void Usart2TxEmpty_IrqHandler(void);
+__WEAKDEF void Usart2TxEnd_IrqHandler(void);
+__WEAKDEF void Usart2RxTO_IrqHandler(void);
+__WEAKDEF void Usart3RxErr_IrqHandler(void);
+__WEAKDEF void Usart3RxEnd_IrqHandler(void);
+__WEAKDEF void Usart3TxEmpty_IrqHandler(void);
+__WEAKDEF void Usart3TxEnd_IrqHandler(void);
+__WEAKDEF void Usart3RxTO_IrqHandler(void);
+__WEAKDEF void Usart4RxErr_IrqHandler(void);
+__WEAKDEF void Usart4RxEnd_IrqHandler(void);
+__WEAKDEF void Usart4TxEmpty_IrqHandler(void);
+__WEAKDEF void Usart4TxEnd_IrqHandler(void);
+__WEAKDEF void Usart4RxTO_IrqHandler(void);
+
+__WEAKDEF void Spi1RxEnd_IrqHandler(void);
+__WEAKDEF void Spi1TxEmpty_IrqHandler(void);
+__WEAKDEF void Spi1Err_IrqHandler(void);
+__WEAKDEF void Spi1Idle_IrqHandler(void);
+__WEAKDEF void Spi2RxEnd_IrqHandler(void);
+__WEAKDEF void Spi2TxEmpty_IrqHandler(void);
+__WEAKDEF void Spi2Err_IrqHandler(void);
+__WEAKDEF void Spi2Idle_IrqHandler(void);
+__WEAKDEF void Spi3RxEnd_IrqHandler(void);
+__WEAKDEF void Spi3TxEmpty_IrqHandler(void);
+__WEAKDEF void Spi3Err_IrqHandler(void);
+__WEAKDEF void Spi3Idle_IrqHandler(void);
+__WEAKDEF void Spi4RxEnd_IrqHandler(void);
+__WEAKDEF void Spi4TxEmpty_IrqHandler(void);
+__WEAKDEF void Spi4Err_IrqHandler(void);
+__WEAKDEF void Spi4Idle_IrqHandler(void);
+
+__WEAKDEF void Timer41GCMUH_IrqHandler(void);
+__WEAKDEF void Timer41GCMUL_IrqHandler(void);
+__WEAKDEF void Timer41GCMVH_IrqHandler(void);
+__WEAKDEF void Timer41GCMVL_IrqHandler(void);
+__WEAKDEF void Timer41GCMWH_IrqHandler(void);
+__WEAKDEF void Timer41GCMWL_IrqHandler(void);
+__WEAKDEF void Timer41GOV_IrqHandler(void);
+__WEAKDEF void Timer41GUD_IrqHandler(void);
+__WEAKDEF void Timer41ReloadU_IrqHandler(void);
+__WEAKDEF void Timer41ReloadV_IrqHandler(void);
+__WEAKDEF void Timer41ReloadW_IrqHandler(void);
+__WEAKDEF void Timer42GCMUH_IrqHandler(void);
+__WEAKDEF void Timer42GCMUL_IrqHandler(void);
+__WEAKDEF void Timer42GCMVH_IrqHandler(void);
+__WEAKDEF void Timer42GCMVL_IrqHandler(void);
+__WEAKDEF void Timer42GCMWH_IrqHandler(void);
+__WEAKDEF void Timer42GCMWL_IrqHandler(void);
+__WEAKDEF void Timer42GOV_IrqHandler(void);
+__WEAKDEF void Timer42GUD_IrqHandler(void);
+__WEAKDEF void Timer42ReloadU_IrqHandler(void);
+__WEAKDEF void Timer42ReloadV_IrqHandler(void);
+__WEAKDEF void Timer42ReloadW_IrqHandler(void);
+__WEAKDEF void Timer43GCMUH_IrqHandler(void);
+__WEAKDEF void Timer43GCMUL_IrqHandler(void);
+__WEAKDEF void Timer43GCMVH_IrqHandler(void);
+__WEAKDEF void Timer43GCMVL_IrqHandler(void);
+__WEAKDEF void Timer43GCMWH_IrqHandler(void);
+__WEAKDEF void Timer43GCMWL_IrqHandler(void);
+__WEAKDEF void Timer43GOV_IrqHandler(void);
+__WEAKDEF void Timer43GUD_IrqHandler(void);
+__WEAKDEF void Timer43ReloadU_IrqHandler(void);
+__WEAKDEF void Timer43ReloadV_IrqHandler(void);
+__WEAKDEF void Timer43ReloadW_IrqHandler(void);
+
+__WEAKDEF void Emb1_IrqHandler(void);
+__WEAKDEF void Emb2_IrqHandler(void);
+__WEAKDEF void Emb3_IrqHandler(void);
+__WEAKDEF void Emb4_IrqHandler(void);
+
+__WEAKDEF void I2s1Tx_IrqHandler(void);
+__WEAKDEF void I2s1Rx_IrqHandler(void);
+__WEAKDEF void I2s1Err_IrqHandler(void);
+__WEAKDEF void I2s2Tx_IrqHandler(void);
+__WEAKDEF void I2s2Rx_IrqHandler(void);
+__WEAKDEF void I2s2Err_IrqHandler(void);
+__WEAKDEF void I2s3Tx_IrqHandler(void);
+__WEAKDEF void I2s3Rx_IrqHandler(void);
+__WEAKDEF void I2s3Err_IrqHandler(void);
+__WEAKDEF void I2s4Tx_IrqHandler(void);
+__WEAKDEF void I2s4Rx_IrqHandler(void);
+__WEAKDEF void I2s4Err_IrqHandler(void);
+
+__WEAKDEF void I2c1RxEnd_IrqHandler(void);
+__WEAKDEF void I2c1TxEnd_IrqHandler(void);
+__WEAKDEF void I2c1TxEmpty_IrqHandler(void);
+__WEAKDEF void I2c1Err_IrqHandler(void);
+__WEAKDEF void I2c2RxEnd_IrqHandler(void);
+__WEAKDEF void I2c2TxEnd_IrqHandler(void);
+__WEAKDEF void I2c2TxEmpty_IrqHandler(void);
+__WEAKDEF void I2c2Err_IrqHandler(void);
+__WEAKDEF void I2c3RxEnd_IrqHandler(void);
+__WEAKDEF void I2c3TxEnd_IrqHandler(void);
+__WEAKDEF void I2c3TxEmpty_IrqHandler(void);
+__WEAKDEF void I2c3Err_IrqHandler(void);
+
+__WEAKDEF void Pvd1_IrqHandler(void);
+__WEAKDEF void Pvd2_IrqHandler(void);
+
+__WEAKDEF void FcmErr_IrqHandler(void);
+__WEAKDEF void FcmEnd_IrqHandler(void);
+__WEAKDEF void FcmOV_IrqHandler(void);
+
+__WEAKDEF void Wdt_IrqHandler(void);
+
+__WEAKDEF void ADC1A_IrqHandler(void);
+__WEAKDEF void ADC1B_IrqHandler(void);
+__WEAKDEF void ADC1ChCmp_IrqHandler(void);
+__WEAKDEF void ADC1SeqCmp_IrqHandler(void);
+__WEAKDEF void ADC2A_IrqHandler(void);
+__WEAKDEF void ADC2B_IrqHandler(void);
+__WEAKDEF void ADC2ChCmp_IrqHandler(void);
+__WEAKDEF void ADC2SeqCmp_IrqHandler(void);
+
+__WEAKDEF void Sdio1_IrqHandler(void);
+__WEAKDEF void Sdio2_IrqHandler(void);
+
+__WEAKDEF void Can_IrqHandler(void);
+
+//@} // InterruptGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_INTERRUPTS_ENABLE */
+
+#endif /* __HC32F460_INTERRUPTS_H___ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,191 @@
+/******************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_keyscan.h
+ **
+ ** A detailed description is available at
+ ** @link KeyscanGroup Keyscan description @endlink
+ **
+ **   - 2018-10-17 CDT First version for Device Driver Library of keyscan.
+ **
+ ******************************************************************************/
+
+#ifndef __HC32F460_KEYSCAN_H__
+#define __HC32F460_KEYSCAN_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_KEYSCAN_ENABLE == DDL_ON)
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ *  \defgroup KeyscanGroup Matrix Key Scan Module (KeyScan)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ *******************************************************************************
+ ** \brief Enumeration to hi-z state cycles of each keyout
+ **
+ ** \note
+ ******************************************************************************/
+typedef enum en_hiz_cycle
+{
+    Hiz4    = 0u,
+    Hiz8    = 1u,
+    Hiz16   = 2u,
+    Hiz32   = 3u,
+    Hiz64   = 4u,
+    Hiz256  = 5u,
+    Hiz512  = 6u,
+    Hiz1K   = 7u,
+}en_hiz_cycle_t;
+
+/**
+ *******************************************************************************
+ ** \brief Enumeration to low state cycles of each keyout
+ **
+ ** \note
+ ******************************************************************************/
+typedef enum en_low_cycle
+{
+    Low8    = 3u,
+    Low16   = 4u,
+    Low32   = 5u,
+    Low64   = 6u,
+    Low128  = 7u,
+    Low256  = 8u,
+    Low512  = 9u,
+    Low1K   = 10u,
+    Low2K   = 11u,
+    Low4K   = 12u,
+    Low8K   = 13u,
+    Low16K  = 14u,
+    Low32K  = 15u,
+    Low64K  = 16u,
+    Low128K = 17u,
+    Low256K = 18u,
+    Low512K = 19u,
+    Low1M   = 20u,
+    Low2M   = 21u,
+    Low4M   = 22u,
+    Low8M   = 23u,
+    Low16M  = 24u,
+}en_low_cycle_t;
+
+/**
+ *******************************************************************************
+ ** \brief Enumeration to key scan clock
+ **
+ ** \note
+ ******************************************************************************/
+typedef enum en_keyscan_clk
+{
+    KeyscanHclk     = 0u,               ///< use HCLK as scan clock
+    KeyscanLrc      = 1u,               ///< use internal Low RC as scan clock
+    KeyscanXtal32   = 2u,               ///< use external XTAL32 as scan clock
+}en_keyscan_clk_t;
+
+/**
+ *******************************************************************************
+ ** \brief Enumeration to KEYOUT combination
+ ******************************************************************************/
+typedef enum en_keyout_sel
+{
+    Keyout0To1      = 1u,               ///< KEYOUT 0 to 1 are selected
+    Keyout0To2      = 2u,               ///< KEYOUT 0 to 2 are selected
+    Keyout0To3      = 3u,               ///< KEYOUT 0 to 3 are selected
+    Keyout0To4      = 4u,               ///< KEYOUT 0 to 4 are selected
+    Keyout0To5      = 5u,               ///< KEYOUT 0 to 5 are selected
+    Keyout0To6      = 6u,               ///< KEYOUT 0 to 6 are selected
+    Keyout0To7      = 7u,               ///< KEYOUT 0 to 7 are selected
+}en_keyout_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief Enumeration to KEYIN combination
+ ******************************************************************************/
+typedef enum en_keyin_sel
+{
+    Keyin00         = 1u <<  0,          ///< KEYIN 0 is selected
+    Keyin01         = 1u <<  1,          ///< KEYIN 1 is selected
+    Keyin02         = 1u <<  2,          ///< KEYIN 2 is selected
+    Keyin03         = 1u <<  3,          ///< KEYIN 3 is selected
+    Keyin04         = 1u <<  4,          ///< KEYIN 4 is selected
+    Keyin05         = 1u <<  5,          ///< KEYIN 5 is selected
+    Keyin06         = 1u <<  6,          ///< KEYIN 6 is selected
+    Keyin07         = 1u <<  7,          ///< KEYIN 7 is selected
+    Keyin08         = 1u <<  8,          ///< KEYIN 8 is selected
+    Keyin09         = 1u <<  9,          ///< KEYIN 9 is selected
+    Keyin10         = 1u << 10,          ///< KEYIN 10 is selected
+    Keyin11         = 1u << 11,          ///< KEYIN 11 is selected
+    Keyin12         = 1u << 12,          ///< KEYIN 12 is selected
+    Keyin13         = 1u << 13,          ///< KEYIN 13 is selected
+    Keyin14         = 1u << 14,          ///< KEYIN 14 is selected
+    Keyin15         = 1u << 15,          ///< KEYIN 15 is selected
+}en_keyin_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief Keyscan configuration
+ **
+ ** \note The Keyscan configuration structure
+ ******************************************************************************/
+typedef struct stc_keyscan_config
+{
+    en_hiz_cycle_t      enHizCycle;     ///< KEYOUT Hiz state cycles, ref @ en_hiz_cycle_t for details
+    en_low_cycle_t      enLowCycle;     ///< KEYOUT Low state cycles, ref @ en_low_cycle_t for details
+    en_keyscan_clk_t    enKeyscanClk;   ///< Key scan clock, ref @ en_keyscan_clk_t for details
+    en_keyout_sel_t     enKeyoutSel;    ///< KEYOUT selection, ref @ en_keyout_sel_t for details
+    uint16_t            u16KeyinSel;    ///< KEYIN selection, ref @ en_keyin_sel_t for details
+}stc_keyscan_config_t;
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+extern en_result_t KEYSCAN_Init(const stc_keyscan_config_t *pstcKeyscanConfig);
+extern en_result_t KEYSCAN_DeInit(void);
+extern en_result_t KEYSCAN_Start(void);
+extern en_result_t KEYSCAN_Stop(void);
+extern uint8_t KEYSCAN_GetColIdx(void);
+
+//@} // KeyscanGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_KEYSCAN_ENABLE */
+
+#endif /* __HC32F460_KEYSCAN_H__ */
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,293 @@
+/*******************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_mpu.h
+ **
+ ** A detailed description is available at
+ ** @link MpuGroup MPU description @endlink
+ **
+ **   - 2018-10-20 CDT First version for Device Driver Library of MPU.
+ **
+ ******************************************************************************/
+#ifndef __HC32F460_MPU_H__
+#define __HC32F460_MPU_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_MPU_ENABLE == DDL_ON)
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup MpuGroup Memory Protection Unit(MPU)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ *******************************************************************************
+ ** \brief MPU region number enumeration
+ **
+ ******************************************************************************/
+typedef enum en_mpu_region_num
+{
+    MpuRegionNum0  = 0u,                    ///< MPU region number 0
+    MpuRegionNum1  = 1u,                    ///< MPU region number 1
+    MpuRegionNum2  = 2u,                    ///< MPU region number 2
+    MpuRegionNum3  = 3u,                    ///< MPU region number 3
+    MpuRegionNum4  = 4u,                    ///< MPU region number 4
+    MpuRegionNum5  = 5u,                    ///< MPU region number 5
+    MpuRegionNum6  = 6u,                    ///< MPU region number 6
+    MpuRegionNum7  = 7u,                    ///< MPU region number 7
+    MpuRegionNum8  = 8u,                    ///< MPU region number 8
+    MpuRegionNum9  = 9u,                    ///< MPU region number 9
+    MpuRegionNum10 = 10u,                   ///< MPU region number 10
+    MpuRegionNum11 = 11u,                   ///< MPU region number 11
+    MpuRegionNum12 = 12u,                   ///< MPU region number 12
+    MpuRegionNum13 = 13u,                   ///< MPU region number 13
+    MpuRegionNum14 = 14u,                   ///< MPU region number 14
+    MpuRegionNum15 = 15u,                   ///< MPU region number 15
+} en_mpu_region_num_t;
+
+/**
+ *******************************************************************************
+ ** \brief MPU region size enumeration
+ **
+ ******************************************************************************/
+typedef enum en_mpu_region_size
+{
+    MpuRegionSize32Byte   = 4u,             ///< 32 Byte
+    MpuRegionSize64Byte   = 5u,             ///< 64 Byte
+    MpuRegionSize128Byte  = 6u,             ///< 126 Byte
+    MpuRegionSize256Byte  = 7u,             ///< 256 Byte
+    MpuRegionSize512Byte  = 8u,             ///< 512 Byte
+    MpuRegionSize1KByte   = 9u,             ///< 1K Byte
+    MpuRegionSize2KByte   = 10u,            ///< 2K Byte
+    MpuRegionSize4KByte   = 11u,            ///< 4K Byte
+    MpuRegionSize8KByte   = 12u,            ///< 8K Byte
+    MpuRegionSize16KByte  = 13u,            ///< 16K Byte
+    MpuRegionSize32KByte  = 14u,            ///< 32K Byte
+    MpuRegionSize64KByte  = 15u,            ///< 64K Byte
+    MpuRegionSize128KByte = 16u,            ///< 128K Byte
+    MpuRegionSize256KByte = 17u,            ///< 256K Byte
+    MpuRegionSize512KByte = 18u,            ///< 512K Byte
+    MpuRegionSize1MByte   = 19u,            ///< 1M Byte
+    MpuRegionSize2MByte   = 20u,            ///< 2M Byte
+    MpuRegionSize4MByte   = 21u,            ///< 4M Byte
+    MpuRegionSize8MByte   = 22u,            ///< 8M Byte
+    MpuRegionSize16MByte  = 23u,            ///< 16M Byte
+    MpuRegionSize32MByte  = 24u,            ///< 32M Byte
+    MpuRegionSize64MByte  = 25u,            ///< 64M Byte
+    MpuRegionSize128MByte = 26u,            ///< 128M Byte
+    MpuRegionSize256MByte = 27u,            ///< 256M Byte
+    MpuRegionSize512MByte = 28u,            ///< 512M Byte
+    MpuRegionSize1GByte   = 29u,            ///< 1G Byte
+    MpuRegionSize2GByte   = 30u,            ///< 2G Byte
+    MpuRegionSize4GByte   = 31u,            ///< 4G Byte
+}  en_mpu_region_size_t;
+
+/**
+ *******************************************************************************
+ ** \brief MPU region enumeration
+ **
+ ******************************************************************************/
+typedef enum en_mpu_region_type
+{
+    SMPU1Region = 0u,                       ///< System DMA_1 MPU
+    SMPU2Region = 1u,                       ///< System DMA_2 MPU
+    FMPURegion  = 2u,                       ///< System USBFS_DMA MPU
+} en_mpu_region_type_t;
+
+/**
+ *******************************************************************************
+ ** \brief MPU action selection enumeration
+ **
+ ******************************************************************************/
+typedef enum en_mpu_action_sel
+{
+    MpuNoneAction   = 0u,                   ///< MPU don't action.
+    MpuTrigBusError = 1u,                   ///< MPU trigger bus error
+    MpuTrigNmi      = 2u,                   ///< MPU trigger bus NMI interrupt
+    MpuTrigReset    = 3u,                   ///< MPU trigger reset
+} en_mpu_action_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief MPU IP protection mode enumeration
+ **
+ ******************************************************************************/
+typedef enum en_mpu_ip_prot_mode
+{
+    AesReadProt     = (1ul << 0),           ///< AES read protection
+    AesWriteProt    = (1ul << 1),           ///< AES write protection
+    HashReadProt    = (1ul << 2),           ///< HASH read protection
+    HashWriteProt   = (1ul << 3),           ///< HASH write protection
+    TrngReadProt    = (1ul << 4),           ///< TRNG read protection
+    TrngWriteProt   = (1ul << 5),           ///< TRNG write protection
+    CrcReadProt     = (1ul << 6),           ///< CRC read protection
+    CrcWriteProt    = (1ul << 7),           ///< CRC write protection
+    FmcReadProt     = (1ul << 8),           ///< FMC read protection
+    FmcWriteProt    = (1ul << 9),           ///< FMC write protection
+    WdtReadProt     = (1ul << 12),          ///< WDT read protection
+    WdtWriteProt    = (1ul << 13),          ///< WDT write protection
+    SwdtReadProt    = (1ul << 14),          ///< WDT read protection
+    SwdtWriteProt   = (1ul << 15),          ///< WDT write protection
+    BksramReadProt  = (1ul << 16),          ///< BKSRAM read protection
+    BksramWriteProt = (1ul << 17),          ///< BKSRAM write protection
+    RtcReadProt     = (1ul << 18),          ///< RTC read protection
+    RtcWriteProt    = (1ul << 19),          ///< RTC write protection
+    DmpuReadProt    = (1ul << 20),          ///< DMPU read protection
+    DmpuWriteProt   = (1ul << 21),          ///< DMPU write protection
+    SramcReadProt   = (1ul << 22),          ///< SRAMC read protection
+    SramcWriteProt  = (1ul << 23),          ///< SRAMC write protection
+    IntcReadProt    = (1ul << 24),          ///< INTC read protection
+    IntcWriteProt   = (1ul << 25),          ///< INTC write protection
+    SyscReadProt    = (1ul << 26),          ///< SYSC read protection
+    SyscWriteProt   = (1ul << 27),          ///< SYSC write protection
+    MstpReadProt    = (1ul << 28),          ///< MSTP read protection
+    MstpWriteProt   = (1ul << 29),          ///< MSTP write protection
+    BusErrProt      = (1ul << 31),          ///< BUSERR write protection
+} en_mpu_ip_prot_mode_t;
+
+/**
+ *******************************************************************************
+ ** \brief MPU protection region permission
+ **
+ ******************************************************************************/
+typedef struct stc_mpu_prot_region_permission
+{
+    en_mpu_action_sel_t   enAction;         ///< Specifies MPU action
+
+    en_functional_state_t enRegionEnable;   ///< Disable: Disable region protection; Enable:Enable region protection
+
+    en_functional_state_t enWriteEnable;    ///< Disable: Prohibited to write; Enable:permitted to write
+
+    en_functional_state_t enReadEnable;     ///< Disable: Prohibited to read; Enable:permitted to read
+
+} stc_mpu_prot_region_permission_t;
+
+/**
+ *******************************************************************************
+ ** \brief MPU background region permission
+ **
+ ******************************************************************************/
+typedef struct stc_mpu_bkgd_region_permission
+{
+    en_functional_state_t enWriteEnable;    ///< Disable: Prohibited to write; Enable:permitted to write
+
+    en_functional_state_t enReadEnable;     ///< Disable: Prohibited to read; Enable:permitted to read
+} stc_mpu_bkgd_region_permission_t_t;
+
+/**
+ *******************************************************************************
+ ** \brief MPU background region initialization configuration
+ **
+ ******************************************************************************/
+typedef struct stc_mpu_bkgd_region_init
+{
+    stc_mpu_bkgd_region_permission_t_t stcSMPU1BkgdPermission;      ///< Specifies SMPU1 background permission and this stuctrue detail refer of @ref stc_mpu_bkgd_region_permission_t_t
+
+    stc_mpu_bkgd_region_permission_t_t stcSMPU2BkgdPermission;      ///< Specifies SMPU2 background permission and this stuctrue detail refer @ref stc_mpu_bkgd_region_permission_t_t
+
+    stc_mpu_bkgd_region_permission_t_t stcFMPUBkgdPermission;       ///< Specifies FMPU background permission and this stuctrue detail refer @ref stc_mpu_bkgd_region_permission_t_t
+} stc_mpu_bkgd_region_init_t;
+
+/**
+ *******************************************************************************
+ ** \brief MPU protect region initialization configuration
+ **
+ ******************************************************************************/
+typedef struct stc_mpu_prot_region_init
+{
+    uint32_t                         u32RegionBaseAddress;  ///< Specifies region base address
+
+    en_mpu_region_size_t             enRegionSize;          ///< Specifies region size and This parameter can be a value of @ref en_mpu_region_size_t
+
+    stc_mpu_prot_region_permission_t stcSMPU1Permission;    ///< Specifies DMA1 MPU region permission and this structure detail refer @ref stc_mpu_prot_region_permission_t
+
+    stc_mpu_prot_region_permission_t stcSMPU2Permission;    ///< Specifies DMA2 MPU region permission and this structure detail refer @ref stc_mpu_prot_region_permission_t
+
+    stc_mpu_prot_region_permission_t stcFMPUPermission;     ///< Specifies USBFS-DMA MPU region permission and this structure detail refer @ref stc_mpu_prot_region_permission_t
+} stc_mpu_prot_region_init_t;
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+en_result_t MPU_ProtRegionInit(en_mpu_region_num_t enRegionNum,
+                                const stc_mpu_prot_region_init_t *pstcInitCfg);
+en_result_t MPU_BkgdRegionInit(const stc_mpu_bkgd_region_init_t *pstcInitCfg);
+en_result_t MPU_SetRegionSize(en_mpu_region_num_t enRegionNum,
+                                en_mpu_region_size_t enRegionSize);
+en_mpu_region_size_t MPU_GetRegionSize(en_mpu_region_num_t enRegionNum);
+en_result_t MPU_SetRegionBaseAddress(en_mpu_region_num_t enRegionNum,
+                                uint32_t u32RegionBaseAddr);
+uint32_t MPU_GetRegionBaseAddress(en_mpu_region_num_t enRegionNum);
+en_result_t MPU_SetNoPermissionAcessAction(en_mpu_region_type_t enMpuRegionType,
+                                en_mpu_action_sel_t enActionSel);
+en_mpu_action_sel_t MPU_GetNoPermissionAcessAction(en_mpu_region_type_t enMpuRegionType);
+en_result_t MPU_ProtRegionCmd(en_mpu_region_num_t enRegionNum,
+                                en_mpu_region_type_t enMpuRegionType,
+                                en_functional_state_t enState);
+en_result_t MPU_RegionTypeCmd(en_mpu_region_type_t enMpuRegionType,
+                                en_functional_state_t enState);
+en_flag_status_t MPU_GetStatus(en_mpu_region_type_t enMpuRegionType);
+en_result_t MPU_ClearStatus(en_mpu_region_type_t enMpuRegionType);
+en_result_t MPU_SetProtRegionReadPermission(en_mpu_region_num_t enRegionNum,
+                                en_mpu_region_type_t enMpuRegionType,
+                                en_functional_state_t enState);
+en_functional_state_t MPU_GetProtRegionReadPermission(en_mpu_region_num_t enRegionNum,
+                                en_mpu_region_type_t enMpuRegionType);
+en_result_t MPU_SetProtRegionWritePermission(en_mpu_region_num_t enRegionNum,
+                                en_mpu_region_type_t enMpuRegionType,
+                                en_functional_state_t enState);
+en_functional_state_t MPU_GetProtRegionWritePermission(en_mpu_region_num_t enRegionNum,
+                                en_mpu_region_type_t enMpuRegionType);
+en_result_t MPU_SetBkgdRegionReadPermission(en_mpu_region_type_t enMpuRegionType,
+                                en_functional_state_t enState);
+en_functional_state_t MPU_GetBkgdRegionReadPermission(en_mpu_region_type_t enMpuRegionType);
+en_result_t MPU_SetBkgdRegionWritePermission(en_mpu_region_type_t enMpuRegionType,
+                                en_functional_state_t enState);
+en_functional_state_t MPU_GetBkgdRegionWritePermission(en_mpu_region_type_t enMpuRegionType);
+en_result_t MPU_WriteProtCmd(en_functional_state_t enState);
+en_result_t MPU_IpProtCmd(uint32_t u32ProtMode,
+                                en_functional_state_t enState);
+
+//@} // MpuGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_MPU_ENABLE */
+
+#endif /* __HC32F460_MPU_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,139 @@
+/*******************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_ots.h
+ **
+ ** A detailed description is available at
+ ** @link OtsGroup Ots description @endlink
+ **
+ **   - 2018-10-26  CDT First version for Device Driver Library of Ots.
+ **
+ ******************************************************************************/
+#ifndef __HC32F460_OTS_H__
+#define __HC32F460_OTS_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_OTS_ENABLE == DDL_ON)
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup OtsGroup On-chip Temperature Sensor(OTS)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/* Automatically turn off the analog temperature sensor after the temperature
+   measurement is over. */
+typedef enum en_ots_auto_off
+{
+    OtsAutoOff_Disable = 0x0,           ///< Disable automatically turn off OTS.
+    OtsAutoOff_Enable  = 0x1,           ///< Enable automatically turn off OTS.
+} en_ots_auto_off_t;
+
+/* Temperature measurement end interrupt request. */
+typedef enum en_ots_ie
+{
+    OtsInt_Disable = 0x0,               ///< Disable OTS interrupt.
+    OtsInt_Enable  = 0x1,               ///< Enable OTS interrupt.
+} en_ots_ie_t;
+
+/* OTS clock selection. */
+typedef enum en_ots_clk_sel
+{
+    OtsClkSel_Xtal = 0x0,               ///< Select XTAL as OTS clock.
+    OtsClkSel_Hrc  = 0x1,               ///< Select HRC as OTS clock.
+} en_ots_clk_sel_t;
+
+/* OTS OTS initialization structure definition. */
+typedef struct stc_ots_init
+{
+    en_ots_auto_off_t enAutoOff;        ///< @ref en_ots_auto_off_t.
+    en_ots_clk_sel_t  enClkSel;         ///< @ref en_ots_clk_sel_t.
+    float32_t f32SlopeK;                ///< K: Temperature slope (calculated by calibration experiment). */
+    float32_t f32OffsetM;               ///< M: Temperature offset (calculated by calibration experiment). */
+} stc_ots_init_t;
+
+/* OTS common trigger source select */
+typedef enum en_ots_com_trigger
+{
+    OtsComTrigger_1   = 0x1,            ///< Select common trigger 1.
+    OtsComTrigger_2   = 0x2,            ///< Select common trigger 2.
+    OtsComTrigger_1_2 = 0x3,            ///< Select common trigger 1 and 2.
+} en_ots_com_trigger_t;
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+
+/**
+ * @brief  Start OTS.
+ * @param  None
+ * @retval None
+ */
+__STATIC_INLINE void OTS_Start(void)
+{
+    bM4_OTS_CTL_OTSST = (uint32_t)1u;
+}
+
+/**
+ * @brief  Stop OTS.
+ * @param  None
+ * @retval None
+ */
+__STATIC_INLINE void OTS_Stop(void)
+{
+    bM4_OTS_CTL_OTSST = (uint32_t)0u;
+}
+
+en_result_t OTS_Init(const stc_ots_init_t *pstcInit);
+void OTS_DeInit(void);
+
+en_result_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout);
+
+void OTS_IntCmd(en_functional_state_t enNewState);
+void OTS_SetTriggerSrc(en_event_src_t enEvent);
+void OTS_ComTriggerCmd(en_ots_com_trigger_t enComTrigger, en_functional_state_t enState);
+
+en_result_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2, \
+                                  uint16_t *pu16Ecr, float32_t *pf32A,  \
+                                  uint32_t u32Timeout);
+
+float OTS_CalculateTemp(void);
+
+//@} // OtsGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_OTS_ENABLE */
+
+#endif /* __HC32F460_OTS_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
@@ -0,0 +1,567 @@
+/*****************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ */
+/******************************************************************************/
+/** \file hc32f460_pwc.h
+ **
+ ** A detailed description is available at
+ ** @link PwcGroup PWC description @endlink
+ **
+ **   - 2018-10-28  CDT  First version for Device Driver Library of PWC.
+ **
+ ******************************************************************************/
+#ifndef __HC32F460_PWC_H__
+#define __HC32F460_PWC_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_common.h"
+#include "ddl_config.h"
+
+#if (DDL_PWC_ENABLE == DDL_ON)
+
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ *******************************************************************************
+ ** \defgroup PwcGroup Power Control(PWC)
+ **
+ ******************************************************************************/
+//@{
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ *******************************************************************************
+ ** \brief  The power down mode.
+ **
+ ******************************************************************************/
+typedef enum en_pwc_powerdown_md
+{
+    PowerDownMd1                    = 0u,   ///< Power down mode 1.
+    PowerDownMd2                    = 1u,   ///< Power down mode 2.
+    PowerDownMd3                    = 2u,   ///< Power down mode 3.
+    PowerDownMd4                    = 3u,   ///< Power down mode 4.
+}en_pwc_powerdown_md_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The IO retain status under power down mode.
+ **
+ ******************************************************************************/
+typedef enum en_pwc_iortn
+{
+    IoPwrDownRetain                 = 0u,   ///< Io keep under power down mode.
+    IoPwrRstRetain                  = 1u,   ///< Io keep after power reset.
+    IoHighImp                       = 2u,   ///< IO high impedance either power down or power reset.
+}en_pwc_iortn_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The driver ability while different speed mode enter stop mode.
+ **
+ ******************************************************************************/
+typedef enum en_pwc_stopdas
+{
+    StopHighspeed                    = 0u,   ///< The driver ability while high speed mode enter stop mode.
+    StopUlowspeed                    = 3u,   ///< The driver ability while ultra_low speed mode enter stop mode.
+}en_pwc_stopdas_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The dynamic power driver voltage select.
+ **
+ ******************************************************************************/
+typedef enum en_pwc_rundrvs
+{
+    RunUHighspeed                  = 0u,   ///< The ultra_high speed.
+    RunUlowspeed                   = 2u,   ///< The ultra_low speed.
+    RunHighspeed                   = 3u,   ///< The high speed.
+}en_pwc_rundrvs_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The dynamic power driver ability scaling.
+ **
+ ******************************************************************************/
+typedef enum en_pwc_drvability_sca
+{
+    Ulowspeed                       = 8u,   ///< The ultra_low speed.
+    HighSpeed                       = 15u,  ///< The high speed.
+}en_pwc_drvability_sca_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The power down wake up time select.
+ **
+ ******************************************************************************/
+typedef enum en_pwc_waketime_sel
+{
+    Vcap01                          = 0u,   ///< Wake up while vcap capacitance 2*0.1uf.
+    Vcap0047                        = 1u,  ///< Wake up while vcap capacitance 2*0.047uf.
+}en_pwc_waketime_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The wait or not wait flash stable while stop mode awake.
+ **
+ ******************************************************************************/
+typedef enum en_pwc_stop_flash_sel
+{
+    Wait                            = 0u,  ///< wait flash stable.
+    NotWait                         = 1u,  ///< Not Wait flash stable.
+}en_pwc_stop_flash_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The clk value while stop mode awake.
+ **
+ ******************************************************************************/
+typedef enum en_pwc_stop_clk_sel
+{
+    ClkFix                          = 0u,  ///< clock fix.
+    ClkMrc                          = 1u,  ///< clock source is MRC, only ram code.
+}en_pwc_stop_clk_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The power down wake up event edge select.
+ **
+ ******************************************************************************/
+typedef enum en_pwc_edge_sel
+{
+    EdgeFalling                      = 0u,  ///< Falling edge.
+    EdgeRising                       = 1u,  ///< Rising edge.
+}en_pwc_edge_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The voltage detect edge select.
+ **
+ ******************************************************************************/
+typedef enum en_pwc_pvdedge_sel
+{
+    OverVcc                         = 0u,  ///< PVD > VCC.
+    BelowVcc                        = 1u,  ///< PVD < VCC.
+}en_pwc_pvdedge_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The flag of wake_up timer compare result.
+ **
+ ******************************************************************************/
+typedef enum en_pwc_wkover_flag
+{
+    UnEqual                         = 0u,  ///< Timer value unequal with the wake_up compare value whitch set.
+    Equal                           = 1u,  ///< Timer value equal with the wake_up compare value whitch set..
+}en_pwc_wkover_flag_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The RAM operating mode.
+ **
+ ******************************************************************************/
+typedef enum en_pwc_ram_op_md
+{
+    HighSpeedMd                     = 0x8043, ///< Work at high speed.
+    UlowSpeedMd                     = 0x9062, ///< Work at ultra low speed.
+}en_pwc_ram_op_md_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The wake up clock select.
+ **
+ ******************************************************************************/
+typedef enum en_pwc_wkclk_sel
+{
+    Wk64hz                          = 0u,  ///< 64Hz.
+    WkXtal32                        = 1u,  ///< Xtal32.
+    WkLrc                           = 2u,  ///< Lrc.
+}en_pwc_wkclk_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The pvd digital filtering sampling clock select.
+ **
+ ******************************************************************************/
+typedef enum en_pwc_pvdfiltclk_sel
+{
+    PvdLrc025                       = 0u,  ///< 0.25 LRC cycle.
+    PvdLrc05                        = 1u,  ///< 0.5 LRC cycle.
+    PvdLrc1                         = 2u,  ///< LRC 1 div.
+    PvdLrc2                         = 3u,  ///< LRC 2 div.
+}en_pwc_pvdfiltclk_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The pvd2 level select.
+ **
+ ******************************************************************************/
+typedef enum en_pwc_pvd2level_sel
+{
+    Pvd2Level0                     = 0u,  ///< 2.1V.while high_speed & ultra_low speed mode, 2.20V.while ultra_high speed mode.
+    Pvd2Level1                     = 1u,  ///< 2.3V.while high_speed & ultra_low speed mode, 2.40V.while ultra_high speed mode.
+    Pvd2Level2                     = 2u,  ///< 2.5V.while high_speed & ultra_low speed mode, 2.67V.while ultra_high speed mode.
+    Pvd2Level3                     = 3u,  ///< 2.6V.while high_speed & ultra_low speed mode, 2.77V.while ultra_high speed mode.
+    Pvd2Level4                     = 4u,  ///< 2.7V.while high_speed & ultra_low speed mode, 2.88V.while ultra_high speed mode.
+    Pvd2Level5                     = 5u,  ///< 2.8V.while high_speed & ultra_low speed mode, 2.98V.while ultra_high speed mode.
+    Pvd2Level6                     = 6u,  ///< 2.9V.while high_speed & ultra_low speed mode, 3.08V.while ultra_high speed mode.
+    Pvd2Level7                     = 7u,  ///< 1.1V.while high_speed & ultra_low speed mode, 1.15V.while ultra_high speed mode.
+}en_pwc_pvd2level_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The pvd1 level select.
+ **
+ ******************************************************************************/
+typedef enum en_pwc_pvd1level_sel
+{
+    Pvd1Level0                     = 0u,  ///< 2.0V.while high_speed & ultra_low speed mode, 2.09V.while ultra_high speed mode.
+    Pvd1Level1                     = 1u,  ///< 2.1V.while high_speed & ultra_low speed mode, 2.20V.while ultra_high speed mode.
+    Pvd1Level2                     = 2u,  ///< 2.3V.while high_speed & ultra_low speed mode, 2.40V.while ultra_high speed mode.
+    Pvd1Level3                     = 3u,  ///< 2.5V.while high_speed & ultra_low speed mode, 2.67V.while ultra_high speed mode.
+    Pvd1Level4                     = 4u,  ///< 2.6V.while high_speed & ultra_low speed mode, 2.77V.while ultra_high speed mode.
+    Pvd1Level5                     = 5u,  ///< 2.7V.while high_speed & ultra_low speed mode, 2.88V.while ultra_high speed mode.
+    Pvd1Level6                     = 6u,  ///< 2.8V.while high_speed & ultra_low speed mode, 2.98V.while ultra_high speed mode.
+    Pvd1Level7                     = 7u,  ///< 2.9V.while high_speed & ultra_low speed mode, 3.08V.while ultra_high speed mode.
+}en_pwc_pvd1level_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The pvd interrupt select.
+ **
+ ******************************************************************************/
+ typedef enum en_pwc_pvd_int_sel
+{
+    NonMskInt                       = 0u,  ///< Non-maskable Interrupt.
+    MskInt                          = 1u,  ///< Maskable Interrupt.
+}en_pwc_pvd_int_sel_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The handle of pvd mode.
+ **
+ ******************************************************************************/
+ typedef enum en_pwc_pvd_md
+{
+    PvdInt                          = 0u,  ///< The handle of pvd is interrupt.
+    PvdReset                        = 1u,  ///< The handle of pvd is reset.
+}en_pwc_pvd_md_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The unit of pvd detect.
+ **
+ ******************************************************************************/
+ typedef enum en_pwc_pvd
+{
+    PvdU1                        = 0u,      ///< The uint1 of pvd detect.
+    PvdU2                        = 1u,      ///< The unit2 of pvd detect.
+}en_pwc_pvd_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The power mode  configuration.
+ **
+ ******************************************************************************/
+typedef struct stc_pwc_pwr_mode_cfg
+{
+    en_pwc_powerdown_md_t   enPwrDownMd;    ///< Power down mode.
+    en_functional_state_t   enRLdo;         ///< Enable or disable RLDO.
+    en_functional_state_t   enRetSram;      ///< Enable or disable Ret_Sram.
+    en_pwc_iortn_t          enIoRetain;     ///< IO retain.
+    en_pwc_waketime_sel_t   enPwrDWkupTm;   ///< The power down wake up time select.
+}stc_pwc_pwr_mode_cfg_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The stop mode configuration.
+ **
+ ******************************************************************************/
+typedef struct stc_pwc_stop_mode_cfg
+{
+    en_pwc_stopdas_t        enStpDrvAbi;    ///< Driver ability while enter stop mode.
+    en_pwc_stop_flash_sel_t enStopFlash;    ///< Flash mode while stop mode awake.
+    en_pwc_stop_clk_sel_t   enStopClk;      ///< Clock value while stop mode awake.
+    en_functional_state_t   enPll;          ///< Whether the PLL enable or disable while enter stop mode.
+}stc_pwc_stop_mode_cfg_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The power down wake_up timer control.
+ **
+ ******************************************************************************/
+typedef struct stc_pwc_wktm_ctl
+{
+    uint16_t                u16WktmCmp;     ///< The wake_up timer compare value.
+    en_pwc_wkover_flag_t    enWkOverFlag;   ///< The flag of compare result.
+    en_pwc_wkclk_sel_t      enWkclk;        ///< The clock of wake_up timer.
+    en_functional_state_t   enWktmEn;       ///< Enable or disable wake_up timer.
+}stc_pwc_wktm_ctl_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The pvd control.
+ **
+ ******************************************************************************/
+typedef struct stc_pwc_pvd_ctl
+{
+    en_functional_state_t   enPvdIREn;      ///< Enable or disable pvd interrupt(reset).
+    en_pwc_pvd_md_t         enPvdMode;      ///< The handle of pvd is interrupt or reset.
+    en_functional_state_t   enPvdCmpOutEn;  ///< Enable or disable pvd output compare result .
+}stc_pwc_pvd_ctl_t;
+
+/**
+ *******************************************************************************
+ ** \brief  The power down wake_up event configuration.
+ **
+ ******************************************************************************/
+typedef struct stc_pwc_pvd_cfg
+{
+    stc_pwc_pvd_ctl_t       stcPvd1Ctl;     ///< Pvd1 control configuration.
+    stc_pwc_pvd_ctl_t       stcPvd2Ctl;     ///< Pvd2 control configuration.
+    en_functional_state_t   enPvd1FilterEn; ///< Pvd1 filtering enable or disable.
+    en_functional_state_t   enPvd2FilterEn; ///< Pvd2 filtering enable or disable.
+    en_pwc_pvdfiltclk_sel_t enPvd1Filtclk;  ///< Pvd1 filtering sampling clock.
+    en_pwc_pvdfiltclk_sel_t enPvd2Filtclk;  ///< Pvd2 filtering sampling clock.
+    en_pwc_pvd1level_sel_t  enPvd1Level;    ///< Pvd1 voltage.
+    en_pwc_pvd2level_sel_t  enPvd2Level;    ///< Pvd2 voltage.
+    en_pwc_pvd_int_sel_t    enPvd1Int;      ///< Pvd1 interrupt.
+    en_pwc_pvd_int_sel_t    enPvd2Int;      ///< Pvd2 interrupt.
+}stc_pwc_pvd_cfg_t;
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+#define PWC_PDWKEN0_WKUP00          ((uint8_t)0x01)
+#define PWC_PDWKEN0_WKUP01          ((uint8_t)0x02)
+#define PWC_PDWKEN0_WKUP02          ((uint8_t)0x04)
+#define PWC_PDWKEN0_WKUP03          ((uint8_t)0x08)
+#define PWC_PDWKEN0_WKUP10          ((uint8_t)0x10)
+#define PWC_PDWKEN0_WKUP11          ((uint8_t)0x20)
+#define PWC_PDWKEN0_WKUP12          ((uint8_t)0x40)
+#define PWC_PDWKEN0_WKUP13          ((uint8_t)0x80)
+
+#define PWC_PDWKEN1_WKUP20          ((uint8_t)0x01)
+#define PWC_PDWKEN1_WKUP21          ((uint8_t)0x02)
+#define PWC_PDWKEN1_WKUP22          ((uint8_t)0x04)
+#define PWC_PDWKEN1_WKUP23          ((uint8_t)0x08)
+#define PWC_PDWKEN1_WKUP30          ((uint8_t)0x10)
+#define PWC_PDWKEN1_WKUP31          ((uint8_t)0x20)
+#define PWC_PDWKEN1_WKUP32          ((uint8_t)0x40)
+#define PWC_PDWKEN1_WKUP33          ((uint8_t)0x80)
+
+#define PWC_PDWKEN2_PVD1            ((uint8_t)0x01)
+#define PWC_PDWKEN2_PVD2            ((uint8_t)0x02)
+#define PWC_PDWKEN2_NMI             ((uint8_t)0x04)
+#define PWC_PDWKEN2_RTCPRD          ((uint8_t)0x10)
+#define PWC_PDWKEN2_RTCAL           ((uint8_t)0x20)
+#define PWC_PDWKEN2_WKTM            ((uint8_t)0x80)
+
+#define PWC_PDWKUP_EDGE_WKP0        ((uint8_t)0x01)
+#define PWC_PDWKUP_EDGE_WKP1        ((uint8_t)0x02)
+#define PWC_PDWKUP_EDGE_WKP2        ((uint8_t)0x04)
+#define PWC_PDWKUP_EDGE_WKP3        ((uint8_t)0x08)
+#define PWC_PDWKUP_EDGE_PVD1        ((uint8_t)0x10)
+#define PWC_PDWKUP_EDGE_PVD2        ((uint8_t)0x20)
+#define PWC_PDWKUP_EDGE_NMI         ((uint8_t)0x40)
+
+#define PWC_RAMPWRDOWN_SRAM1        ((uint32_t)0x00000001)
+#define PWC_RAMPWRDOWN_SRAM2        ((uint32_t)0x00000002)
+#define PWC_RAMPWRDOWN_SRAM3        ((uint32_t)0x00000004)
+#define PWC_RAMPWRDOWN_SRAMH        ((uint32_t)0x00000008)
+#define PWC_RAMPWRDOWN_USBFS        ((uint32_t)0x00000010)
+#define PWC_RAMPWRDOWN_SDIOC0       ((uint32_t)0x00000020)
+#define PWC_RAMPWRDOWN_SDIOC1       ((uint32_t)0x00000040)
+#define PWC_RAMPWRDOWN_CAN          ((uint32_t)0x00000080)
+#define PWC_RAMPWRDOWN_CACHE        ((uint32_t)0x00000100)
+#define PWC_RAMPWRDOWN_FULL         ((uint32_t)0x000001FF)
+
+#define PWC_STOPWKUPEN_EIRQ0        ((uint32_t)0x00000001)
+#define PWC_STOPWKUPEN_EIRQ1        ((uint32_t)0x00000002)
+#define PWC_STOPWKUPEN_EIRQ2        ((uint32_t)0x00000004)
+#define PWC_STOPWKUPEN_EIRQ3        ((uint32_t)0x00000008)
+#define PWC_STOPWKUPEN_EIRQ4        ((uint32_t)0x00000010)
+#define PWC_STOPWKUPEN_EIRQ5        ((uint32_t)0x00000020)
+#define PWC_STOPWKUPEN_EIRQ6        ((uint32_t)0x00000040)
+#define PWC_STOPWKUPEN_EIRQ7        ((uint32_t)0x00000080)
+#define PWC_STOPWKUPEN_EIRQ8        ((uint32_t)0x00000100)
+#define PWC_STOPWKUPEN_EIRQ9        ((uint32_t)0x00000200)
+#define PWC_STOPWKUPEN_EIRQ10       ((uint32_t)0x00000400)
+#define PWC_STOPWKUPEN_EIRQ11       ((uint32_t)0x00000800)
+#define PWC_STOPWKUPEN_EIRQ12       ((uint32_t)0x00001000)
+#define PWC_STOPWKUPEN_EIRQ13       ((uint32_t)0x00002000)
+#define PWC_STOPWKUPEN_EIRQ14       ((uint32_t)0x00004000)
+#define PWC_STOPWKUPEN_EIRQ15       ((uint32_t)0x00008000)
+#define PWC_STOPWKUPEN_SWDT         ((uint32_t)0x00010000)
+#define PWC_STOPWKUPEN_VDU1         ((uint32_t)0x00020000)
+#define PWC_STOPWKUPEN_VDU2         ((uint32_t)0x00040000)
+#define PWC_STOPWKUPEN_CMPI0        ((uint32_t)0x00080000)
+#define PWC_STOPWKUPEN_WKTM         ((uint32_t)0x00100000)
+#define PWC_STOPWKUPEN_RTCAL        ((uint32_t)0x00200000)
+#define PWC_STOPWKUPEN_RTCPRD       ((uint32_t)0x00400000)
+#define PWC_STOPWKUPEN_TMR0         ((uint32_t)0x00800000)
+#define PWC_STOPWKUPEN_USARTRXD     ((uint32_t)0x02000000)
+
+#define PWC_PTWK0_WKUPFLAG          ((uint8_t)0x01)
+#define PWC_PTWK1_WKUPFLAG          ((uint8_t)0x02)
+#define PWC_PTWK2_WKUPFLAG          ((uint8_t)0x04)
+#define PWC_PTWK3_WKUPFLAG          ((uint8_t)0x08)
+#define PWC_PVD1_WKUPFLAG           ((uint8_t)0x10)
+#define PWC_PVD2_WKUPFLAG           ((uint8_t)0x20)
+#define PWC_NMI_WKUPFLAG            ((uint8_t)0x40)
+
+#define PWC_RTCPRD_WKUPFALG         ((uint8_t)0x10)
+#define PWC_RTCAL_WKUPFLAG          ((uint8_t)0x20)
+#define PWC_WKTM_WKUPFLAG           ((uint8_t)0x80)
+
+#define PWC_WKTMCMP_MSK             ((uint16_t)0x0FFF)
+
+#define PWC_FCG0_PERIPH_SRAMH       ((uint32_t)0x00000001)
+#define PWC_FCG0_PERIPH_SRAM12      ((uint32_t)0x00000010)
+#define PWC_FCG0_PERIPH_SRAM3       ((uint32_t)0x00000100)
+#define PWC_FCG0_PERIPH_SRAMRET     ((uint32_t)0x00000400)
+#define PWC_FCG0_PERIPH_DMA1        ((uint32_t)0x00004000)
+#define PWC_FCG0_PERIPH_DMA2        ((uint32_t)0x00008000)
+#define PWC_FCG0_PERIPH_FCM         ((uint32_t)0x00010000)
+#define PWC_FCG0_PERIPH_AOS         ((uint32_t)0x00020000)
+#define PWC_FCG0_PERIPH_AES         ((uint32_t)0x00100000)
+#define PWC_FCG0_PERIPH_HASH        ((uint32_t)0x00200000)
+#define PWC_FCG0_PERIPH_TRNG        ((uint32_t)0x00400000)
+#define PWC_FCG0_PERIPH_CRC         ((uint32_t)0x00800000)
+#define PWC_FCG0_PERIPH_DCU1        ((uint32_t)0x01000000)
+#define PWC_FCG0_PERIPH_DCU2        ((uint32_t)0x02000000)
+#define PWC_FCG0_PERIPH_DCU3        ((uint32_t)0x04000000)
+#define PWC_FCG0_PERIPH_DCU4        ((uint32_t)0x08000000)
+#define PWC_FCG0_PERIPH_KEY         ((uint32_t)0x80000000)
+
+
+#define PWC_FCG1_PERIPH_CAN         ((uint32_t)0x00000001)
+#define PWC_FCG1_PERIPH_QSPI        ((uint32_t)0x00000008)
+#define PWC_FCG1_PERIPH_I2C1        ((uint32_t)0x00000010)
+#define PWC_FCG1_PERIPH_I2C2        ((uint32_t)0x00000020)
+#define PWC_FCG1_PERIPH_I2C3        ((uint32_t)0x00000040)
+#define PWC_FCG1_PERIPH_USBFS       ((uint32_t)0x00000100)
+#define PWC_FCG1_PERIPH_SDIOC1      ((uint32_t)0x00000400)
+#define PWC_FCG1_PERIPH_SDIOC2      ((uint32_t)0x00000800)
+#define PWC_FCG1_PERIPH_I2S1        ((uint32_t)0x00001000)
+#define PWC_FCG1_PERIPH_I2S2        ((uint32_t)0x00002000)
+#define PWC_FCG1_PERIPH_I2S3        ((uint32_t)0x00004000)
+#define PWC_FCG1_PERIPH_I2S4        ((uint32_t)0x00008000)
+#define PWC_FCG1_PERIPH_SPI1        ((uint32_t)0x00010000)
+#define PWC_FCG1_PERIPH_SPI2        ((uint32_t)0x00020000)
+#define PWC_FCG1_PERIPH_SPI3        ((uint32_t)0x00040000)
+#define PWC_FCG1_PERIPH_SPI4        ((uint32_t)0x00080000)
+#define PWC_FCG1_PERIPH_USART1      ((uint32_t)0x01000000)
+#define PWC_FCG1_PERIPH_USART2      ((uint32_t)0x02000000)
+#define PWC_FCG1_PERIPH_USART3      ((uint32_t)0x04000000)
+#define PWC_FCG1_PERIPH_USART4      ((uint32_t)0x08000000)
+
+#define PWC_FCG2_PERIPH_TIM01       ((uint32_t)0x00000001)
+#define PWC_FCG2_PERIPH_TIM02       ((uint32_t)0x00000002)
+#define PWC_FCG2_PERIPH_TIMA1       ((uint32_t)0x00000004)
+#define PWC_FCG2_PERIPH_TIMA2       ((uint32_t)0x00000008)
+#define PWC_FCG2_PERIPH_TIMA3       ((uint32_t)0x00000010)
+#define PWC_FCG2_PERIPH_TIMA4       ((uint32_t)0x00000020)
+#define PWC_FCG2_PERIPH_TIMA5       ((uint32_t)0x00000040)
+#define PWC_FCG2_PERIPH_TIMA6       ((uint32_t)0x00000080)
+#define PWC_FCG2_PERIPH_TIM41       ((uint32_t)0x00000100)
+#define PWC_FCG2_PERIPH_TIM42       ((uint32_t)0x00000200)
+#define PWC_FCG2_PERIPH_TIM43       ((uint32_t)0x00000400)
+#define PWC_FCG2_PERIPH_EMB         ((uint32_t)0x00008000)
+#define PWC_FCG2_PERIPH_TIM61       ((uint32_t)0x00010000)
+#define PWC_FCG2_PERIPH_TIM62       ((uint32_t)0x00020000)
+#define PWC_FCG2_PERIPH_TIM63       ((uint32_t)0x00040000)
+
+#define PWC_FCG3_PERIPH_ADC1        ((uint32_t)0x00000001)
+#define PWC_FCG3_PERIPH_ADC2        ((uint32_t)0x00000002)
+#define PWC_FCG3_PERIPH_CMP         ((uint32_t)0x00000100)
+#define PWC_FCG3_PERIPH_OTS         ((uint32_t)0x00001000)
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+void PWC_PowerModeCfg(const stc_pwc_pwr_mode_cfg_t* pstcPwrMdCfg);
+void PWC_EnterPowerDownMd(void);
+
+void PWC_PdWakeup0Cmd(uint32_t u32Wkup0Event, en_functional_state_t enNewState);
+void PWC_PdWakeup1Cmd(uint32_t u32Wkup1Event, en_functional_state_t enNewState);
+void PWC_PdWakeup2Cmd(uint32_t u32Wkup2Event, en_functional_state_t enNewState);
+void PWC_PdWakeupEvtEdgeCfg(uint8_t u8WkupEvent, en_pwc_edge_sel_t enEdge);
+
+en_flag_status_t PWC_GetWakeup0Flag(uint8_t u8WkupFlag);
+en_flag_status_t PWC_GetWakeup1Flag(uint8_t u8WkupFlag);
+void PWC_ClearWakeup0Flag(uint8_t u8WkupFlag);
+void PWC_ClearWakeup1Flag(uint8_t u8WkupFlag);
+void PWC_PwrMonitorCmd(en_functional_state_t enNewState);
+
+void PWC_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState);
+void PWC_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState);
+void PWC_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState);
+void PWC_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState);
+
+en_result_t PWC_StopModeCfg(const stc_pwc_stop_mode_cfg_t*  pstcStpMdCfg);
+void PWC_StopWkupCmd(uint32_t u32Wkup0Event, en_functional_state_t enNewState);
+
+void PWC_EnterStopMd(void);
+void PWC_EnterSleepMd(void);
+
+void PWC_Xtal32CsCmd(en_functional_state_t enNewState);
+void PWC_HrcPwrCmd(en_functional_state_t enNewState);
+void PWC_PllPwrCmd(en_functional_state_t enNewState);
+void PWC_RamPwrdownCmd(uint32_t u32RamCtlBit, en_functional_state_t enNewState);
+void PWC_RamOpMdConfig(en_pwc_ram_op_md_t enRamOpMd);
+
+void PWC_WktmControl(const stc_pwc_wktm_ctl_t* pstcWktmCtl);
+
+void PWC_PvdCfg(const stc_pwc_pvd_cfg_t* pstcPvdCfg);
+void PWC_Pvd1Cmd(en_functional_state_t enNewState);
+void PWC_Pvd2Cmd(en_functional_state_t enNewState);
+void PWC_ExVccCmd(en_functional_state_t enNewState);
+void PWC_ClearPvdFlag(en_pwc_pvd_t enPvd);
+en_flag_status_t PWC_GetPvdFlag(en_pwc_pvd_t enPvd);
+en_flag_status_t PWC_GetPvdStatus(en_pwc_pvd_t enPvd);
+
+void PWC_enNvicBackup(void);
+void PWC_enNvicRecover(void);
+void PWC_ClkBackup(void);
+void PWC_ClkRecover(void);
+void PWC_IrqClkBackup(void);
+void PWC_IrqClkRecover(void);
+
+en_result_t PWC_HS2LS(void);
+en_result_t PWC_LS2HS(void);
+en_result_t PWC_HS2HP(void);
+en_result_t PWC_HP2HS(void);
+en_result_t PWC_LS2HP(void);
+en_result_t PWC_HP2LS(void);
+
+//@} // PwcGroup
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DDL_PWC_ENABLE */
+
+#endif /* __HC32F460_PWC_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
--- a/Show More
+++ b/Show More
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YuanHongbin	cdc0c59a3f	1、删除AD7924目录文件 2、删除SDCard目录文件 3、删除SHT20目录文件	2026-05-15 13:46:05 +08:00
YuanHongbin	9bb3309b30	FatFS文件修改为子模块方式	2026-05-15 13:41:56 +08:00
YuanHongbin	b93dda47ab	删除FatFS目录文件	2026-05-15 13:38:30 +08:00
YuanHongbin	72cf076b31	sx127x文件修改为子模块方式	2026-05-15 13:30:54 +08:00
YuanHongbin	28ef3921a1	删除SX127x目录文件	2026-05-15 13:28:35 +08:00
YuanHongbin	5383c83937	DebugCmd文件修改为子模块方式	2026-05-14 17:54:04 +08:00
YuanHongbin	2bf447ce1c	DebugCmd文件修改为子模块方式	2026-05-14 10:37:06 +08:00
YuanHongbin	aa5548d70e	SpiFlash全片擦除时喂狗	2026-05-12 18:29:33 +08:00
YuanHongbin	0986af5968	调试	2026-05-12 16:39:58 +08:00
YuanHongbin	a3198e56a9	1、public.h文件的结构体增加字节对齐 2、GATEMEY_PARA_SAV_ADDR扇区内存增加到两个扇区，日志扇区起始地址后移 3、spiflash写入函数中，跨扇区判断函数释放，用于修复网关参数存储扩容后的跨扇区读写	2026-04-28 15:11:44 +08:00
YuanHongbin	23ab9ca0f9	初始版本	2026-04-23 13:56:52 +08:00
YuanHongbin	6c611f1fa3	Initial commit	2026-04-23 13:54:29 +08:00